[bsp/raspberry-pico] add: SMP (#6888)
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螺丝松掉的人
GitHub
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4d6ceffcab
commit
6d00b28425
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-28 flybreak first version
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* 2023-01-22 rose_man add RT_USING_SMP
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*/
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#include <rthw.h>
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@ -21,12 +22,16 @@
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void isr_systick(void)
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{
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/* enter interrupt */
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#ifndef RT_USING_SMP
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rt_interrupt_enter();
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#endif
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rt_tick_increase();
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/* leave interrupt */
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#ifndef RT_USING_SMP
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rt_interrupt_leave();
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#endif
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}
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uint32_t systick_config(uint32_t ticks)
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@ -47,7 +52,14 @@ void rt_hw_board_init()
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{
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set_sys_clock_khz(PLL_SYS_KHZ, true);
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#ifdef RT_USING_HEAP
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rt_system_heap_init(HEAP_BEGIN, HEAP_END);
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#endif
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#ifdef RT_USING_SMP
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extern rt_hw_spinlock_t _cpus_lock;
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rt_hw_spin_lock_init(&_cpus_lock);
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#endif
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alarm_pool_init_default();
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@ -64,10 +76,16 @@ void rt_hw_board_init()
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}
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/* Configure the SysTick */
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systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY) * 1000 / RT_TICK_PER_SECOND);
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systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC)*10000/RT_TICK_PER_SECOND);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_SERIAL
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stdio_init_all();
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -0,0 +1,23 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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if rtconfig.PLATFORM in ['armcc', 'armclang']:
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src += Glob('*_rvds.S')
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if rtconfig.PLATFORM in ['gcc']:
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src += Glob('*_init.S')
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src += Glob('*_gcc.S')
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if rtconfig.PLATFORM in ['iccarm']:
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src += Glob('*_iar.S')
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group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2012-06-01 aozima set pendsv priority to 0xFF.
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2013-02-20 aozima port to gcc.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-11-04 bright fixed hardfault bug for gcc.
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*/
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.cpu cortex-m0
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
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.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
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.equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
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.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
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#include "../rtconfig.h"
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#ifdef RT_USING_SMP
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.equ SIO_CPUID, 0xd0000000 /* CPUID */
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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MRS R0, PRIMASK
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CPSID I
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BX LR
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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MSR PRIMASK, R0
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BX LR
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* R0 --> from
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* R1 --> to
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*/
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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#ifndef RT_USING_SMP
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/* set rt_thread_switch_interrupt_flag to 1 */
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LDR R2, =rt_thread_switch_interrupt_flag
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOVS R3, #1
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STR R3, [R2]
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LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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STR R0, [R2]
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_reswitch:
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LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR R1, [R2]
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#else
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/* context_switch_to smp */
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PUSH {LR}
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BL __rt_cpu_switch
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POP {R2}
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#endif
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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#ifndef RT_USING_SMP
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BX LR
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#else
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BX R2
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#endif
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/* R0 --> switch from thread stack
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* R1 --> switch to thread stack
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* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
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*/
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.global PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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/* disable interrupt to protect context switch */
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MRS R2, PRIMASK
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CPSID I
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#ifndef RT_USING_SMP
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/* get rt_thread_switch_interrupt_flag */
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LDR R0, =rt_thread_switch_interrupt_flag
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#else
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LDR R0, =SIO_CPUID
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LDR R1, [R0]
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LDR R3, =rt_thread_switch_array
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CMP R1, #0
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BEQ cpu0_info
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ADDS R3, #12
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cpu0_info:
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MOV R0, R3
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#endif
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LDR R1, [R0]
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CMP R1, #0x00
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BEQ pendsv_exit /* pendsv already handled */
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOVS R1, #0
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STR R1, [R0]
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#ifndef RT_USING_SMP
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LDR R0, =rt_interrupt_from_thread
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#else
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ADDS R0, #4
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#endif
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LDR R1, [R0]
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CMP R1, #0x00
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BEQ switch_to_thread /* skip register save at the first time */
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MRS R1, PSP /* get from thread stack pointer */
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SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */
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LDR R0, [R0]
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STR R1, [R0] /* update from thread stack pointer */
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STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */
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MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */
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MOV R5, R9
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MOV R6, R10
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MOV R7, R11
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STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */
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switch_to_thread:
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#ifndef RT_USING_SMP
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LDR R1, =rt_interrupt_to_thread
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#else
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MOV R1, R3
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ADDS R1, #8
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#endif
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LDR R1, [R1]
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LDR R1, [R1] /* load thread stack pointer */
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LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */
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PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */
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LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */
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MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */
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MOV R9, R5
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MOV R10, R6
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MOV R11, R7
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POP {R4 - R7} /* pop {R4 - R7} from MSP */
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MSR PSP, R1 /* update stack pointer */
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pendsv_exit:
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/* restore interrupt */
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MSR PRIMASK, R2
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MOVS R0, #0x03
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RSBS R0, R0, #0x00
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BX R0
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* R0 --> to
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*/
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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rt_hw_context_switch_to:
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#ifndef RT_USING_SMP
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LDR R1, =rt_interrupt_to_thread
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STR R0, [R1]
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/* set from thread to 0 */
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LDR R1, =rt_interrupt_from_thread
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MOVS R0, #0
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STR R0, [R1]
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/* set interrupt flag to 1 */
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LDR R1, =rt_thread_switch_interrupt_flag
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MOVS R0, #1
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STR R0, [R1]
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#else
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/* context_switch_to smp */
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MOV R2,R1
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MOV R1,R0
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MOVS R0,#0
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BL __rt_cpu_switch
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#endif
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/* set the PendSV and SysTick exception priority */
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LDR R0, =NVIC_SHPR3
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LDR R1, =NVIC_PENDSV_PRI
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LDR R2, [R0,#0x00] /* read */
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ORRS R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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NOP
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/* restore MSP */
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LDR R0, =SCB_VTOR
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LDR R0, [R0]
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LDR R0, [R0]
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NOP
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MSR MSP, R0
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/* enable interrupts at processor level */
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CPSIE I
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/* ensure PendSV exception taken place before subsequent operation */
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DSB
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ISB
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/* never reach here! */
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/* compatible with old version */
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.global rt_hw_interrupt_thread_switch
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.type rt_hw_interrupt_thread_switch, %function
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rt_hw_interrupt_thread_switch:
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BX LR
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NOP
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.global HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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/* get current context */
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MRS R0, PSP /* get fault thread stack pointer */
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PUSH {LR}
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BL rt_hw_hard_fault_exception
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POP {PC}
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/*
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* rt_uint32_t rt_hw_interrupt_check(void);
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* R0 --> state
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*/
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.global rt_hw_interrupt_check
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.type rt_hw_interrupt_check, %function
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rt_hw_interrupt_check:
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MRS R0, IPSR
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BX LR
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@ -0,0 +1,284 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2012-05-31 aozima Merge all of the C source code into cpuport.c
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2012-12-23 aozima stack addr align to 8byte.
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* 2023-01-22 rose_man add RT_USING_SMP
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <stdint.h>
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#include "board.h"
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#ifdef RT_USING_SMP
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#include "hardware/structs/sio.h"
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#include "hardware/irq.h"
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#include "pico/sync.h"
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#include "pico/multicore.h"
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int rt_hw_cpu_id(void)
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{
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return sio_hw->cpuid;
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}
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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static uint8_t spin_cnt = 0;
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if ( spin_cnt < 32)
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{
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lock->slock = (rt_uint32_t)spin_lock_instance(spin_cnt);
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spin_cnt = spin_cnt + 1;
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}
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else
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{
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lock->slock = 0;
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}
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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if ( lock->slock != 0 )
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{
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spin_lock_unsafe_blocking((spin_lock_t*)lock->slock);
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}
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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if ( lock->slock != 0 )
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{
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spin_unlock_unsafe((spin_lock_t*)lock->slock);
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}
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}
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void secondary_cpu_c_start(void)
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{
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irq_set_enabled(SIO_IRQ_PROC1,RT_TRUE);
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extern uint32_t systick_config(uint32_t ticks);
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systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC)*10000/RT_TICK_PER_SECOND);
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rt_hw_spin_lock(&_cpus_lock);
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_up(void)
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{
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multicore_launch_core1(secondary_cpu_c_start);
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irq_set_enabled(SIO_IRQ_PROC0,RT_TRUE);
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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asm volatile ("wfi");
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}
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#define IPI_MAGIC 0x5a5a
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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sio_hw->fifo_wr = IPI_MAGIC;
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}
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void rt_hw_ipi_handler(void)
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{
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uint32_t status = sio_hw->fifo_st;
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if ( status & (SIO_FIFO_ST_ROE_BITS | SIO_FIFO_ST_WOF_BITS) )
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{
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sio_hw->fifo_st = 0;
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}
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if ( status & SIO_FIFO_ST_VLD_BITS )
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{
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if ( sio_hw->fifo_rd == IPI_MAGIC )
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{
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//rt_schedule();
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}
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}
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}
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void isr_irq15(void)
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{
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rt_hw_ipi_handler();
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}
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void isr_irq16(void)
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{
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rt_hw_ipi_handler();
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}
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struct __rt_thread_switch_array
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{
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rt_ubase_t flag;
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rt_ubase_t from;
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rt_ubase_t to;
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};
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struct __rt_thread_switch_array rt_thread_switch_array[2] = { {0,0,0}, {0,0,0} };
|
||||
|
||||
void __rt_cpu_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *thread)
|
||||
{
|
||||
struct rt_cpu* pcpu = rt_cpu_self();
|
||||
rt_uint32_t cpuid = rt_hw_cpu_id();
|
||||
|
||||
if ( rt_thread_switch_array[cpuid].flag != 1)
|
||||
{
|
||||
rt_thread_switch_array[cpuid].flag = 1;
|
||||
rt_thread_switch_array[cpuid].from = from;
|
||||
}
|
||||
rt_thread_switch_array[cpuid].to = to;
|
||||
|
||||
if ( pcpu->current_thread != RT_NULL )
|
||||
{
|
||||
thread->cpus_lock_nest = pcpu->current_thread->cpus_lock_nest;
|
||||
thread->critical_lock_nest = pcpu->current_thread->critical_lock_nest;
|
||||
thread->scheduler_lock_nest = pcpu->current_thread->scheduler_lock_nest;
|
||||
}
|
||||
|
||||
pcpu->current_thread = thread;
|
||||
if (!thread->cpus_lock_nest)
|
||||
{
|
||||
rt_hw_spin_unlock(&_cpus_lock);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /*RT_USING_SMP*/
|
||||
|
||||
struct exception_stack_frame
|
||||
{
|
||||
rt_uint32_t r0;
|
||||
rt_uint32_t r1;
|
||||
rt_uint32_t r2;
|
||||
rt_uint32_t r3;
|
||||
rt_uint32_t r12;
|
||||
rt_uint32_t lr;
|
||||
rt_uint32_t pc;
|
||||
rt_uint32_t psr;
|
||||
};
|
||||
|
||||
struct stack_frame
|
||||
{
|
||||
/* r4 ~ r7 low register */
|
||||
rt_uint32_t r4;
|
||||
rt_uint32_t r5;
|
||||
rt_uint32_t r6;
|
||||
rt_uint32_t r7;
|
||||
|
||||
/* r8 ~ r11 high register */
|
||||
rt_uint32_t r8;
|
||||
rt_uint32_t r9;
|
||||
rt_uint32_t r10;
|
||||
rt_uint32_t r11;
|
||||
|
||||
struct exception_stack_frame exception_stack_frame;
|
||||
};
|
||||
|
||||
/* flag in interrupt handling */
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
void *parameter,
|
||||
rt_uint8_t *stack_addr,
|
||||
void *texit)
|
||||
{
|
||||
struct stack_frame *stack_frame;
|
||||
rt_uint8_t *stk;
|
||||
unsigned long i;
|
||||
|
||||
stk = stack_addr + sizeof(rt_uint32_t);
|
||||
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
|
||||
stk -= sizeof(struct stack_frame);
|
||||
|
||||
stack_frame = (struct stack_frame *)stk;
|
||||
|
||||
/* init all register */
|
||||
for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
|
||||
{
|
||||
((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
|
||||
}
|
||||
|
||||
stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */
|
||||
stack_frame->exception_stack_frame.r1 = 0; /* r1 */
|
||||
stack_frame->exception_stack_frame.r2 = 0; /* r2 */
|
||||
stack_frame->exception_stack_frame.r3 = 0; /* r3 */
|
||||
stack_frame->exception_stack_frame.r12 = 0; /* r12 */
|
||||
stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */
|
||||
stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */
|
||||
stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */
|
||||
|
||||
/* return task's current stack address */
|
||||
return stk;
|
||||
}
|
||||
|
||||
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
extern rt_thread_t rt_current_thread;
|
||||
/**
|
||||
* fault exception handling
|
||||
*/
|
||||
void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
|
||||
{
|
||||
rt_kprintf("psr: 0x%08x\n", contex->psr);
|
||||
rt_kprintf(" pc: 0x%08x\n", contex->pc);
|
||||
rt_kprintf(" lr: 0x%08x\n", contex->lr);
|
||||
rt_kprintf("r12: 0x%08x\n", contex->r12);
|
||||
rt_kprintf("r03: 0x%08x\n", contex->r3);
|
||||
rt_kprintf("r02: 0x%08x\n", contex->r2);
|
||||
rt_kprintf("r01: 0x%08x\n", contex->r1);
|
||||
rt_kprintf("r00: 0x%08x\n", contex->r0);
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
rt_thread_t rt_current_thread = rt_thread_self();
|
||||
rt_kprintf("hard fault on cpu : %d on thread: %s\n", rt_current_thread->oncpu, rt_current_thread->name);
|
||||
#else
|
||||
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
|
||||
#endif
|
||||
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||||
list_thread();
|
||||
#endif
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
|
||||
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
|
||||
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
|
||||
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
|
||||
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
|
||||
#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
|
||||
|
||||
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
|
||||
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
|
||||
#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
|
||||
|
||||
/**
|
||||
* reset CPU
|
||||
*/
|
||||
rt_weak void rt_hw_cpu_reset(void)
|
||||
{
|
||||
SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-01-22 rose_man add RT_USING_SMP
|
||||
*/
|
||||
|
||||
#ifndef CPUPORT_H__
|
||||
#define CPUPORT_H__
|
||||
|
||||
typedef union {
|
||||
unsigned long slock;
|
||||
struct __arch_tickets {
|
||||
unsigned short owner;
|
||||
unsigned short next;
|
||||
} tickets;
|
||||
} rt_hw_spinlock_t;
|
||||
|
||||
#endif /*CPUPORT_H__*/
|
||||
|
|
@ -7,6 +7,8 @@ cwd = GetCurrentDir()
|
|||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
pico-sdk/src/rp2_common/hardware_flash/flash.c
|
||||
pico-sdk/src/rp2_common/pico_multicore/multicore.c
|
||||
pico-sdk/src/rp2_common/pico_stdlib/stdlib.c
|
||||
pico-sdk/src/rp2_common/hardware_gpio/gpio.c
|
||||
pico-sdk/src/rp2_common/hardware_claim/claim.c
|
||||
|
|
@ -59,6 +61,8 @@ generated/bs2_default_padded_checksummed.S
|
|||
""")
|
||||
|
||||
path = [
|
||||
cwd + '/pico-sdk/src/rp2_common/hardware_flash/include',
|
||||
cwd + '/pico-sdk/src/rp2_common/pico_multicore/include',
|
||||
cwd + '/pico-sdk/src/common/pico_stdlib/include',
|
||||
cwd + '/pico-sdk/src/rp2_common/hardware_gpio/include',
|
||||
cwd + '/pico-sdk/src/common/pico_base/include',
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ import sys
|
|||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m0'
|
||||
CPU='cortex-m0-dual'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
|
|
|
|||
Loading…
Reference in New Issue