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modify mini2440/board.c serial device 

modify s3c24x0/clock.c clock initialization

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@225 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
gouqingsong@gmail.com 2009-12-25 10:38:56 +00:00
parent ffd0eecb28
commit 6cd35a87c3
2 changed files with 49 additions and 46 deletions
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58
bsp/mini2440/board.c
View File

@ -28,7 +28,8 @@
extern rt_uint32_t PCLK, FCLK, HCLK, UCLK;
extern rt_uint8_t asc16_font[];
extern rt_uint16_t _rt_hw_framebuffer[];
extern void rt_hw_clock_init(void);
extern void rt_hw_lcd_init(void);
extern void rt_hw_mmu_init(void);
extern void rt_hw_touch_init(void);
@ -84,10 +85,10 @@ void rt_serial_handler(int vector)
void rt_hw_uart_init(void)
{
int i;
GPHCON |= 0xa0;
/*PULLUP is enable */
GPHUP |= 0x0c;
/* UART0 port configure */
GPHCON |= 0xAA;
/* PULLUP is disable */
GPHUP |= 0xF;
/* FIFO enable, Tx/Rx FIFO clear */
uart0.uart_device->ufcon = 0x1;
@ -99,8 +100,9 @@ void rt_hw_uart_init(void)
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
uart0.uart_device->ucon = 0x245;
uart0.uart_device->ucon = 0x245;
/* Set uart0 bps */
uart0.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
/* output PCLK to UART0/1, PWMTIMER */
CLKCON |= 0x0D00;
@ -117,42 +119,12 @@ void rt_hw_uart_init(void)
* This function will init s3ceb2410 board
*/
void rt_hw_board_init()
{
/* FCLK = 304.8M */
#define MDIV 68
#define PDIV 1
#define SDIV 1
//rt_hw_set_clock(SDIV, PDIV, MDIV);
/* HCLK = PCLK = FCLK */
//rt_hw_set_dividor(0, 0);
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
TCFG0 = 0x0f00;
/* all divider = 1/2 */
TCFG1 = 0x0;
rt_hw_get_clock();
if (timer_load_val == 0)
{
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
timer_load_val = PCLK/(2 * 16 * 100);
}
/* load value for 10 ms timeout */
TCNTB4 = timer_load_val;
/* auto load, manual update of Timer 4 */
TCON = (TCON & ~0x0700000) | 0x600000;
/* auto load, start Timer 4 */
TCON = (TCON & ~0x0700000) | 0x500000 | 0x3;
/*Enable NAND, USBD, PWM TImer, UART0,1 and GPIO clock,*/
CLKCON = 0xfffff0;
{
/* initialize the system clock */
rt_hw_clock_init();
/* Get the clock */
rt_hw_get_clock();
/* initialize uart */
rt_hw_uart_init();

37
libcpu/arm/s3c24x0/clock.c
View File

@ -17,6 +17,21 @@
#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
/* MPLL=2*12*100/6=400MHz */
#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
/* UPLL=12*64/8=96MHz */
#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
#define HDIVN 0x2 /* HCLK = FCLK / 4 */
#define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
rt_uint32_t FCLK;
rt_uint32_t HCLK;
@ -65,13 +80,29 @@ void rt_hw_get_clock(void)
PCLK = HCLK;
}
void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
MPLLCON = sdiv | pdiv<<4 | mdiv<<12;
MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn)
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
CLKDIVN = (hdivn<<1) | pdivn;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
LOCKTIME = 0xFFFFFFFF;
rt_hw_set_divider(HDIVN, PDIVN);
rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
}