[bsp][hpmicro][hpm6e00evk] add hpm6e00evk support
- added hpm6e00evk support Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
Rbb666
parent
e19b63e5fb
commit
6c085218a3
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@ -341,6 +341,7 @@ jobs:
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- "hpmicro/hpm5300evk"
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- "hpmicro/hpm5301evklite"
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- "hpmicro/hpm6800evk"
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- "hpmicro/hpm6e00evk"
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- RTT_BSP: "llvm-arm"
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RTT_TOOL_CHAIN: "llvm-arm"
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SUB_RTT_BSP:
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,12 @@
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mainmenu "RT-Thread Configuration"
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BSP_DIR := .
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RTT_DIR := ../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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@ -0,0 +1,115 @@
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# HPMicro HPM6E00EVK BSP(Board Support Package) Introduction
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[中文页](README_zh.md) |
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## Introduction
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This document provides brief introduction of the BSP (board support package) for the HPM6E00EVK development board.
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The document consists of the following parts:
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- HPM6E00EVK Board Resources Introduction
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- Quickly Getting Started
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- Refreences
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By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
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## Board Resources Introduction
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HPM6E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, Audio, motor control，etc.
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## Peripheral Condition
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Each peripheral supporting condition for this BSP is as follows:
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| **On-board Peripherals** | **Support** | **Note** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| Ethernet | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| RTC | √ | |
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| PWM | √ | |
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| On-Board Debugger | √ | ft2232 |
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## Execution Instruction
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### Quickly Getting Started
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The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
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#### Parpare Environment
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- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
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- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
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- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
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- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
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- For example: `C:\DevTools\openocd-hpmicro\bin`
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#### Configure and Build project
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Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
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- Configure the project via `menuconfig` in `RT-Thread ENV`
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- Build the project using `scons -jN`, `N` equals to the number of CPU cores
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- Clean the project using `scons -c`
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#### Hardware Connection
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- Switch BOOT pin to 2'b00
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- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
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#### Dowload / Debug
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- Users can download the project via the below command:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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- Users can debug the project via the below command:
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- Connect debugger via `OpenOCD`:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg
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```
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- Start Debugger via `GDB`:
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
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- In the `gdb shell`, type the following commands:
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```console
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load
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c
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```
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### **Running Results**
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Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
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Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.0.1 build Aug 16 2023 18:18:18
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2006 - 2023 Copyright by RT-Thread team
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```
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## **References**
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- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
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- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
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- [HPM6800EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
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@ -0,0 +1,114 @@
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# 先楫 HPM6E00EVK BSP(板级支持包)说明
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[English](README.md) |
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## 简介
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本文档为 HPM6E00EVK 的 BSP (板级支持包) 说明。
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本文包含如下部分:
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- HPM6E00EVK 板级资源介绍
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- 快速上手指南
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- 参考链接
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 板级资源介绍
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HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。
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开发板外观如下图所示：
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## 板载外设
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本 BSP 目前对外设的支持情况如下:
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| **板载外设** | **支持情况** | **备注** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| 以太网 | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| RTC | √ | |
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| PWM | √ | |
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| 板载调试器 | √ | ft2232 |
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## 使用说明
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### 快速开始
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本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
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#### 准备环境
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- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
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- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
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- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
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#### 配置和构建工程
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通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
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- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
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- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
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- 通过 `scons -c` 命令清除构建
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#### 硬件连接
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- 将BOOT 引脚拨到2'b00
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- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
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#### 下载 和 调试
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- 通过如下命令完成下载:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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- 通过如下命令实现调试:
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- 通过 `OpenOCD` 来连接开发板:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg
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```
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- 通过 `GDB` 实现调试:
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
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- 在`GDB Shell`中使用如下命令来加载和运行:
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```console
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load
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c
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```
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### **运行结果**
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一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
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配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.0.1 build Aug 16 2023 18:18:18
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2006 - 2023 Copyright by RT-Thread team
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```
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## **参考链接**
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- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
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- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
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- [HPM6800EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
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@ -0,0 +1,17 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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ASFLAGS = ' -I' + cwd
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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AddOption('--run',
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dest = 'run',
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type='string',
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nargs=1,
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action = 'store',
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default = "",
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help = 'Upload or debug application using openocd')
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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env['ASCOM'] = env['ASPPCOM']
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
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libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
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else:
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libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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GDB = rtconfig.GDB
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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hpm_library = 'hpm_sdk'
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rtconfig.BSP_LIBRARY_TYPE = hpm_library
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# include soc
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
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# include components
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
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# includes rtt drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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import rtconfig
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPDEFINES=[]
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
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Return('group')
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@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2021-2024 HPMicro
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-13 Fan YANG first version
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*
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "rtt_board.h"
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void thread_entry(void *arg);
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int main(void)
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{
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app_init_led_pins();
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static uint32_t led_thread_arg = 0;
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rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
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rt_thread_startup(led_thread);
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return 0;
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}
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void thread_entry(void *arg)
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{
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while(1){
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app_led_write(0, APP_LED_ON);
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rt_thread_mdelay(500);
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app_led_write(0, APP_LED_OFF);
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rt_thread_mdelay(500);
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app_led_write(1, APP_LED_ON);
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rt_thread_mdelay(500);
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app_led_write(1, APP_LED_OFF);
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rt_thread_mdelay(500);
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app_led_write(2, APP_LED_ON);
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rt_thread_mdelay(500);
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app_led_write(2, APP_LED_OFF);
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rt_thread_mdelay(500);
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}
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}
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@ -0,0 +1,302 @@
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menu "Hardware Drivers Config"
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config SOC_HPM6E00
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bool
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select SOC_SERIES_HPM6E00
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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config BSP_USING_ENET_PHY_RTL8211
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bool
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default n
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||||
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||||
menu "On-chip Peripheral Drivers"
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||||
config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN if BSP_USING_GPIO
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default n
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menuconfig BSP_USING_UART
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||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
menuconfig BSP_USING_UART0
|
||||
bool "Enable UART0 (Debugger)"
|
||||
default y
|
||||
if BSP_USING_UART0
|
||||
config BSP_UART0_RX_USING_DMA
|
||||
bool "Enable UART0 RX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART0_TX_USING_DMA
|
||||
bool "Enable UART0 TX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART0_RX_BUFSIZE
|
||||
int "Set UART0 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 128
|
||||
config BSP_UART0_TX_BUFSIZE
|
||||
int "Set UART0 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
menuconfig BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
if BSP_USING_UART1
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART1_TX_USING_DMA
|
||||
bool "Enable UART1 TX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART1_RX_BUFSIZE
|
||||
int "Set UART1 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 1024
|
||||
config BSP_UART1_TX_BUFSIZE
|
||||
int "Set UART1 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI"
|
||||
default n
|
||||
select RT_USING_SPI if BSP_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI7
|
||||
bool "Enable SPI7"
|
||||
default n
|
||||
if BSP_USING_SPI7
|
||||
config BSP_SPI7_USING_DMA
|
||||
bool "Enable SPI7 DMA"
|
||||
default n
|
||||
choice
|
||||
prompt "Select SPI7 CS TYPE"
|
||||
default BSP_SPI7_USING_SOFT_CS
|
||||
config BSP_SPI7_USING_SOFT_CS
|
||||
bool "Enable SPI7 software cs"
|
||||
config BSP_SPI7_USING_HARD_CS
|
||||
bool "Enable SPI7 hardware cs"
|
||||
endchoice
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_ETH
|
||||
bool "Enable Ethernet"
|
||||
default n
|
||||
|
||||
select RT_USING_ETH
|
||||
if BSP_USING_ETH
|
||||
choice
|
||||
prompt "ETH"
|
||||
default BSP_USING_ETH0
|
||||
|
||||
config BSP_USING_ETH0
|
||||
bool "Enable ETH0"
|
||||
select BSP_USING_ENET_PHY_RTL8211
|
||||
endchoice
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_GPTMR
|
||||
bool "Enable GPTMR"
|
||||
default n
|
||||
select RT_USING_HWTIMER if BSP_USING_GPTMR
|
||||
if BSP_USING_GPTMR
|
||||
config BSP_USING_GPTMR0
|
||||
bool "Enable GPTMR0"
|
||||
default n
|
||||
config BSP_USING_GPTMR1
|
||||
bool "Enable GPTMR1"
|
||||
default n
|
||||
config BSP_USING_GPTMR2
|
||||
bool "Enable GPTMR2"
|
||||
default n
|
||||
config BSP_USING_GPTMR3
|
||||
bool "Enable GPTMR3"
|
||||
default n
|
||||
config BSP_USING_GPTMR4
|
||||
bool "Enable GPTMR4"
|
||||
default n
|
||||
config BSP_USING_GPTMR5
|
||||
bool "Enable GPTMR5"
|
||||
default n
|
||||
config BSP_USING_GPTMR6
|
||||
bool "Enable GPTMR6"
|
||||
default n
|
||||
config BSP_USING_GPTMR7
|
||||
bool "Enable GPTMR7"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C"
|
||||
default n
|
||||
select RT_USING_I2C if BSP_USING_I2C
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C0
|
||||
bool "Enable I2C0"
|
||||
default y
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable I2C1"
|
||||
default n
|
||||
config BSP_USING_I2C3
|
||||
bool "Enable I2C3"
|
||||
default n
|
||||
endif
|
||||
if BSP_USING_I2C0
|
||||
config BSP_I2C0_USING_DMA
|
||||
bool "Enable I2C0 DMA"
|
||||
default n
|
||||
endif
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_USING_DMA
|
||||
bool "Enable I2C1 DMA"
|
||||
default n
|
||||
endif
|
||||
if BSP_USING_I2C3
|
||||
config BSP_I2C3_USING_DMA
|
||||
bool "Enable I2C3 DMA"
|
||||
default n
|
||||
endif
|
||||
|
||||
|
||||
menuconfig BSP_USING_XPI_FLASH
|
||||
bool "Enable XPI FLASH"
|
||||
default n
|
||||
select RT_USING_FAL if BSP_USING_XPI_FLASH
|
||||
|
||||
menuconfig BSP_USING_DAO
|
||||
bool "Enable Audio DAO play"
|
||||
default n
|
||||
select RT_USING_AUDIO if BSP_USING_DAO
|
||||
|
||||
menuconfig BSP_USING_PDM
|
||||
bool "Enable Audio PDM record"
|
||||
default n
|
||||
select RT_USING_AUDIO if BSP_USING_PDM
|
||||
|
||||
menuconfig BSP_USING_I2S
|
||||
bool "Enable Audio I2S device"
|
||||
default n
|
||||
select RT_USING_AUDIO if BSP_USING_I2S
|
||||
if BSP_USING_I2S
|
||||
config BSP_USING_I2S3
|
||||
bool "Enable I2S3"
|
||||
default y
|
||||
config BSP_USING_AUDIO_CODEC_WM8960
|
||||
bool "Enable audio codec on board"
|
||||
default y
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_USB
|
||||
bool "Enable USB"
|
||||
default n
|
||||
if BSP_USING_USB
|
||||
config BSP_USING_USB_DEVICE
|
||||
bool "Enable USB Device"
|
||||
default n
|
||||
config BSP_USING_USB_HOST
|
||||
bool "Enable USB Host"
|
||||
select RT_USING_CACHE
|
||||
default n
|
||||
endif
|
||||
|
||||
|
||||
menuconfig BSP_USING_EWDG
|
||||
bool "Enable EWDG"
|
||||
default n
|
||||
select RT_USING_WDT if BSP_USING_EWDG
|
||||
if BSP_USING_EWDG
|
||||
config BSP_USING_EWDG0
|
||||
bool "Enable EWDG0"
|
||||
default n
|
||||
config BSP_USING_EWDG1
|
||||
bool "Enable EWDG1"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_PWMV2
|
||||
bool "Enable PWM"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_MCAN
|
||||
bool "Enable MCAN"
|
||||
default n
|
||||
select RT_USING_CAN if BSP_USING_MCAN
|
||||
if BSP_USING_MCAN
|
||||
config BSP_USING_MCAN0
|
||||
bool "Enable MCAN0"
|
||||
default n
|
||||
config BSP_USING_MCAN1
|
||||
bool "Enable MCAN1"
|
||||
default n
|
||||
config BSP_USING_MCAN2
|
||||
bool "Enable MCAN2"
|
||||
default n
|
||||
config BSP_USING_MCAN3
|
||||
bool "Enable MCAN3"
|
||||
default n
|
||||
config BSP_USING_MCAN4
|
||||
bool "Enable MCAN4"
|
||||
default n
|
||||
config BSP_USING_MCAN5
|
||||
bool "Enable MCAN5"
|
||||
default n
|
||||
config BSP_USING_MCAN6
|
||||
bool "Enable MCAN6"
|
||||
default n
|
||||
config BSP_USING_MCAN7
|
||||
bool "Enable MCAN7"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC if BSP_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
menuconfig BSP_USING_ADC12
|
||||
bool "Enable ADC12"
|
||||
default n
|
||||
if BSP_USING_ADC12
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
config BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default n
|
||||
config BSP_USING_ADC2
|
||||
bool "Enable ADC2"
|
||||
default n
|
||||
endif
|
||||
menuconfig BSP_USING_ADC16
|
||||
bool "Enable ADC16"
|
||||
default n
|
||||
if BSP_USING_ADC16
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
endif
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers
|
||||
src = Split("""
|
||||
board.c
|
||||
rtt_board.c
|
||||
pinmux.c
|
||||
fal_flash_port.c
|
||||
hpm_wm8960.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D45', 'HPM6880']
|
||||
|
||||
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,714 @@
|
|||
/*
|
||||
* Copyright (c) 2024 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPM_BOARD_H
|
||||
#define _HPM_BOARD_H
|
||||
#include <stdio.h>
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_soc.h"
|
||||
#include "hpm_soc_feature.h"
|
||||
#include "pinmux.h"
|
||||
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
|
||||
#include "hpm_debug_console.h"
|
||||
#endif
|
||||
|
||||
#define BOARD_NAME "hpm6e00evk"
|
||||
#define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
|
||||
#define BOARD_CPU_FREQ (600000000UL)
|
||||
|
||||
#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE
|
||||
|
||||
#ifndef BOARD_RUNNING_CORE
|
||||
#define BOARD_RUNNING_CORE HPM_CORE0
|
||||
#endif
|
||||
|
||||
/* ACMP desction */
|
||||
#define BOARD_ACMP HPM_ACMP0
|
||||
#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1
|
||||
#define BOARD_ACMP_IRQ IRQn_ACMP0_1
|
||||
#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */
|
||||
#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */
|
||||
|
||||
/* uart section */
|
||||
#ifndef BOARD_APP_UART_BASE
|
||||
#define BOARD_APP_UART_BASE HPM_UART1
|
||||
#define BOARD_APP_UART_IRQ IRQn_UART1
|
||||
#define BOARD_APP_UART_BAUDRATE (115200UL)
|
||||
#define BOARD_APP_UART_CLK_NAME clock_uart1
|
||||
#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART1_RX
|
||||
#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART1_TX
|
||||
#endif
|
||||
|
||||
#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PF27
|
||||
|
||||
/* uart rx idle demo section */
|
||||
#define BOARD_UART_IDLE BOARD_APP_UART_BASE
|
||||
#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ
|
||||
#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME
|
||||
#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ
|
||||
#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ
|
||||
|
||||
#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4
|
||||
#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4
|
||||
#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4
|
||||
#define BOARD_UART_IDLE_GPTMR_CMP_CH 0
|
||||
#define BOARD_UART_IDLE_GPTMR_CAP_CH 2
|
||||
|
||||
/* uart microros sample section */
|
||||
#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE
|
||||
#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ
|
||||
#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME
|
||||
|
||||
/* enet section */
|
||||
#define BOARD_ENET_PPS HPM_ENET0
|
||||
#define BOARD_ENET_PPS_IDX enet_pps_0
|
||||
#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0
|
||||
#define BOARD_ENET_RMII HPM_ENET0
|
||||
#define BOARD_ENET_RMII_RST_GPIO
|
||||
#define BOARD_ENET_RMII_RST_GPIO_INDEX
|
||||
#define BOARD_ENET_RMII_RST_GPIO_PIN
|
||||
#define BOARD_ENET_RMII HPM_ENET0
|
||||
#define BOARD_ENET_RMII_INT_REF_CLK (1U)
|
||||
#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0)
|
||||
#define BOARD_ENET_RMII_PPS0_PINOUT (1)
|
||||
|
||||
#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */
|
||||
#define BOARD_ENET0_INT_REF_CLK (0U)
|
||||
#define BOARD_ENET0_PHY_RST_TIME (30)
|
||||
#if BOARD_ENET0_INF
|
||||
#define BOARD_ENET0_TX_DLY (0U)
|
||||
#define BOARD_ENET0_RX_DLY (0U)
|
||||
#endif
|
||||
#if __USE_ENET_PTP
|
||||
#define BOARD_ENET0_PTP_CLOCK (clock_ptp0)
|
||||
#endif
|
||||
|
||||
/* usb cdc acm uart section */
|
||||
#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE
|
||||
#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME
|
||||
#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ
|
||||
#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ
|
||||
|
||||
/* uart lin sample section */
|
||||
#define BOARD_UART_LIN BOARD_APP_UART_BASE
|
||||
#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ
|
||||
#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME
|
||||
#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC
|
||||
#define BOARD_UART_LIN_TX_PIN (23U) /* PC23 should align with used pin in pinmux configuration */
|
||||
|
||||
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
|
||||
#ifndef BOARD_CONSOLE_TYPE
|
||||
#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
|
||||
#endif
|
||||
|
||||
#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
|
||||
#ifndef BOARD_CONSOLE_UART_BASE
|
||||
#if BOARD_RUNNING_CORE == HPM_CORE0
|
||||
#define BOARD_CONSOLE_UART_BASE HPM_UART0
|
||||
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
|
||||
#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
|
||||
#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
|
||||
#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
|
||||
#else
|
||||
#define BOARD_CONSOLE_UART_BASE HPM_UART1
|
||||
#define BOARD_CONSOLE_UART_CLK_NAME clock_uart1
|
||||
#define BOARD_CONSOLE_UART_IRQ IRQn_UART1
|
||||
#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART1_TX
|
||||
#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART1_RX
|
||||
#endif
|
||||
#endif
|
||||
#define BOARD_CONSOLE_UART_BAUDRATE (115200UL)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* rtthread-nano finsh section */
|
||||
#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE
|
||||
|
||||
/* modbus sample section */
|
||||
#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE
|
||||
#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME
|
||||
#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ
|
||||
#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ
|
||||
|
||||
/* sdram section */
|
||||
#define BOARD_SDRAM_ADDRESS (0x40000000UL)
|
||||
#define BOARD_SDRAM_SIZE (32 * SIZE_1MB)
|
||||
#define BOARD_SDRAM_CS FEMC_SDRAM_CS0
|
||||
#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS
|
||||
#define BOARD_SDRAM_REFRESH_COUNT (8192UL)
|
||||
#define BOARD_SDRAM_REFRESH_IN_MS (64UL)
|
||||
|
||||
/* nor flash section */
|
||||
#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL)
|
||||
#define BOARD_FLASH_SIZE (16 * SIZE_1MB)
|
||||
|
||||
/* i2c section */
|
||||
#define BOARD_APP_I2C_BASE HPM_I2C0
|
||||
#define BOARD_APP_I2C_IRQ IRQn_I2C0
|
||||
#define BOARD_APP_I2C_CLK_NAME clock_i2c0
|
||||
#define BOARD_APP_I2C_DMA HPM_HDMA
|
||||
#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX
|
||||
#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0
|
||||
|
||||
#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
|
||||
#define BOARD_I2C_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOY
|
||||
#define BOARD_I2C_SCL_GPIO_PIN 2
|
||||
#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOY
|
||||
#define BOARD_I2C_SDA_GPIO_PIN 3
|
||||
|
||||
/* i2c for i2s codec section */
|
||||
#define BOARD_CODEC_I2C_BASE HPM_I2C1
|
||||
#define BOARD_CODEC_I2C_CLK_NAME clock_i2c1
|
||||
|
||||
/* i2s section */
|
||||
#define BOARD_APP_I2S_BASE HPM_I2S0
|
||||
#define BOARD_APP_I2S_DATA_LINE (0U)
|
||||
#define BOARD_APP_I2S_CLK_NAME clock_i2s0
|
||||
#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0
|
||||
#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0
|
||||
#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX
|
||||
#define BOARD_APP_I2S_IRQ IRQn_I2S0
|
||||
#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U)
|
||||
#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U)
|
||||
|
||||
/* dma section */
|
||||
#define BOARD_APP_XDMA HPM_XDMA
|
||||
#define BOARD_APP_HDMA HPM_HDMA
|
||||
#define BOARD_APP_XDMA_IRQ IRQn_XDMA
|
||||
#define BOARD_APP_HDMA_IRQ IRQn_HDMA
|
||||
#define BOARD_APP_DMAMUX HPM_DMAMUX
|
||||
#define TEST_DMA_CONTROLLER HPM_HDMA
|
||||
#define TEST_DMA_IRQ IRQn_HDMA
|
||||
|
||||
/* APP PWM */
|
||||
#define BOARD_APP_PWM HPM_PWM1
|
||||
#define BOARD_APP_PWM_CLOCK_NAME clock_pwm1
|
||||
#define BOARD_APP_PWM_OUT1 pwm_channel_0
|
||||
#define BOARD_APP_PWM_OUT2 pwm_channel_1
|
||||
#define BOARD_APP_PWM_OUT3 pwm_channel_2
|
||||
#define BOARD_APP_PWM_OUT4 pwm_channel_3
|
||||
#define BOARD_APP_PWM_FAULT_PIN (5)
|
||||
#define BOARD_APP_TRGM HPM_TRGM0
|
||||
#define BOARD_APP_PWM_IRQ IRQn_PWM1
|
||||
#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0
|
||||
#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0
|
||||
|
||||
/* gptmr section */
|
||||
#define BOARD_GPTMR HPM_GPTMR4
|
||||
#define BOARD_GPTMR_IRQ IRQn_GPTMR4
|
||||
#define BOARD_GPTMR_CHANNEL 0
|
||||
#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_0
|
||||
#define BOARD_GPTMR_CLK_NAME clock_gptmr4
|
||||
#define BOARD_GPTMR_PWM HPM_GPTMR4
|
||||
#define BOARD_GPTMR_PWM_CHANNEL 0
|
||||
#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR4_0
|
||||
#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr4
|
||||
#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR4
|
||||
#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0
|
||||
#define BOARD_GPTMR_PWM_SYNC_CHANNEL 0
|
||||
#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0
|
||||
|
||||
/* User button */
|
||||
#define BOARD_APP_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOB
|
||||
#define BOARD_APP_GPIO_PIN 24
|
||||
#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_B
|
||||
|
||||
#define BOARD_APP_GPIO_CTRL2 HPM_GPIO0
|
||||
#define BOARD_APP_GPIO_INDEX2 GPIO_DI_GPIOB
|
||||
#define BOARD_APP_GPIO_PIN2 25
|
||||
#define BOARD_APP_GPIO_IRQ2 IRQn_GPIO0_B
|
||||
|
||||
/* gpiom section */
|
||||
#define BOARD_APP_GPIOM_BASE HPM_GPIOM
|
||||
#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO
|
||||
#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
|
||||
|
||||
/* spi section */
|
||||
#define BOARD_APP_SPI_BASE HPM_SPI7
|
||||
#define BOARD_APP_SPI_CLK_NAME clock_spi7
|
||||
#define BOARD_APP_SPI_IRQ IRQn_SPI7
|
||||
#define BOARD_APP_SPI_SCLK_FREQ (20000000UL)
|
||||
#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
|
||||
#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U)
|
||||
#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI7_RX
|
||||
#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI7_TX
|
||||
#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_SPI_CS_PIN IOC_PAD_PF27
|
||||
#define BOARD_SPI_CS_ACTIVE_LEVEL (0U)
|
||||
|
||||
/* Flash section */
|
||||
#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0)
|
||||
#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U)
|
||||
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U)
|
||||
#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U)
|
||||
|
||||
/* ADC section */
|
||||
#define BOARD_APP_ADC16_NAME "ADC0"
|
||||
#define BOARD_APP_ADC16_BASE HPM_ADC0
|
||||
#define BOARD_APP_ADC16_IRQn IRQn_ADC0
|
||||
#define BOARD_APP_ADC16_CH_1 (15U)
|
||||
#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
|
||||
|
||||
#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0
|
||||
#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0
|
||||
#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0
|
||||
#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
|
||||
#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI
|
||||
#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A
|
||||
#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_APP_CAN_BASE HPM_MCAN4
|
||||
#define BOARD_APP_CAN_IRQn IRQn_MCAN4
|
||||
|
||||
/*
|
||||
* timer for board delay
|
||||
*/
|
||||
#define BOARD_DELAY_TIMER (HPM_GPTMR3)
|
||||
#define BOARD_DELAY_TIMER_CH 0
|
||||
#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3)
|
||||
|
||||
#define BOARD_CALLBACK_TIMER (HPM_GPTMR3)
|
||||
#define BOARD_CALLBACK_TIMER_CH 1
|
||||
#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3
|
||||
#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)
|
||||
|
||||
/* USB section */
|
||||
#define BOARD_USB HPM_USB0
|
||||
|
||||
/* LED */
|
||||
#define BOARD_R_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define BOARD_R_GPIO_PIN 14
|
||||
#define BOARD_G_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define BOARD_G_GPIO_PIN 15
|
||||
#define BOARD_B_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define BOARD_B_GPIO_PIN 4
|
||||
|
||||
#define BOARD_LED_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define BOARD_LED_GPIO_PIN 15
|
||||
#define BOARD_LED_OFF_LEVEL 0
|
||||
#define BOARD_LED_ON_LEVEL 1
|
||||
|
||||
#define BOARD_LED_TOGGLE_RGB 1
|
||||
|
||||
/* RGB LED Section */
|
||||
#define BOARD_RED_PWM_IRQ IRQn_PWM1
|
||||
#define BOARD_RED_PWM HPM_PWM1
|
||||
#define BOARD_RED_PWM_OUT_CH 6
|
||||
#define BOARD_RED_PWM_SHADOW_ID 1
|
||||
#define BOARD_RED_PWM_CMP_ID 6
|
||||
#define BOARD_RED_PWM_COUNTER_INDEX 2
|
||||
#define BOARD_RED_PWM_CMP_INITIAL_ZERO true
|
||||
#define BOARD_RED_PWM_CLOCK_NAME clock_mot1
|
||||
|
||||
#define BOARD_GREEN_PWM_IRQ IRQn_PWM1
|
||||
#define BOARD_GREEN_PWM HPM_PWM1
|
||||
#define BOARD_GREEN_PWM_OUT_CH 7
|
||||
#define BOARD_GREEN_PWM_SHADOW_ID 2
|
||||
#define BOARD_GREEN_PWM_CMP_ID 7
|
||||
#define BOARD_GREEN_PWM_COUNTER_INDEX 2
|
||||
#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true
|
||||
#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1
|
||||
|
||||
#define BOARD_BLUE_PWM_IRQ IRQn_PWM0
|
||||
#define BOARD_BLUE_PWM HPM_PWM0
|
||||
#define BOARD_BLUE_PWM_OUT_CH 4
|
||||
#define BOARD_BLUE_PWM_SHADOW_ID 3
|
||||
#define BOARD_BLUE_PWM_CMP_ID 4
|
||||
#define BOARD_BLUE_PWM_COUNTER_INDEX 1
|
||||
#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true
|
||||
#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0
|
||||
|
||||
#define BOARD_RGB_RED 0
|
||||
#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1)
|
||||
#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2)
|
||||
|
||||
/* pdma section */
|
||||
#define BOARD_PDMA_BASE HPM_PDMA
|
||||
|
||||
#ifndef BOARD_SHOW_CLOCK
|
||||
#define BOARD_SHOW_CLOCK 1
|
||||
#endif
|
||||
#ifndef BOARD_SHOW_BANNER
|
||||
#define BOARD_SHOW_BANNER 1
|
||||
#endif
|
||||
|
||||
/* enet section */
|
||||
#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0
|
||||
#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOA
|
||||
#define BOARD_ENET_RGMII_RST_GPIO_PIN (14U)
|
||||
|
||||
#define BOARD_ENET_RGMII HPM_ENET0
|
||||
#define BOARD_ENET_RGMII_TX_DLY (0U)
|
||||
#define BOARD_ENET_RGMII_RX_DLY (0U)
|
||||
|
||||
#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0)
|
||||
|
||||
/* TSW section */
|
||||
#define BOARD_TSW HPM_TSW
|
||||
|
||||
/* MOTOR */
|
||||
#define BOARD_MOTOR_CLK_NAME clock_mot0
|
||||
|
||||
/*BLDC PWM */
|
||||
#define BOARD_BLDCPWM HPM_PWM1
|
||||
#define BOARD_BLDC_UH_PWM_OUTPIN (pwm_channel_0)
|
||||
#define BOARD_BLDC_UL_PWM_OUTPIN (pwm_channel_1)
|
||||
#define BOARD_BLDC_VH_PWM_OUTPIN (pwm_channel_2)
|
||||
#define BOARD_BLDC_VL_PWM_OUTPIN (pwm_channel_3)
|
||||
#define BOARD_BLDC_WH_PWM_OUTPIN (pwm_channel_4)
|
||||
#define BOARD_BLDC_WL_PWM_OUTPIN (pwm_channel_5)
|
||||
#define BOARD_BLDCPWM_TRGM HPM_TRGM0
|
||||
#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_0 (0U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_1 (1U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_2 (2U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_3 (3U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_4 (4U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_5 (5U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_6 (6U)
|
||||
#define BOARD_BLDCPWM_CMP_INDEX_7 (7U)
|
||||
#define BOARD_BLDCPWM_CMP_TRIG_CMP (16U)
|
||||
|
||||
#define BOARD_BLDC_TMR_1MS HPM_GPTMR2
|
||||
#define BOARD_BLDC_TMR_CH 0
|
||||
#define BOARD_BLDC_TMR_CMP 0
|
||||
#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2
|
||||
#define BOARD_BLDC_TMR_RELOAD (100000U)
|
||||
|
||||
/* BLDC ADC */
|
||||
#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16
|
||||
#define BOARD_BLDC_ADC_U_BASE HPM_ADC0
|
||||
#define BOARD_BLDC_ADC_V_BASE HPM_ADC1
|
||||
#define BOARD_BLDC_ADC_W_BASE HPM_ADC2
|
||||
#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete
|
||||
|
||||
#define BOARD_BLDC_ADC_CH_U (14U)
|
||||
#define BOARD_BLDC_ADC_CH_V (10U)
|
||||
#define BOARD_BLDC_ADC_CH_W (11U)
|
||||
#define BOARD_BLDC_ADC_IRQn IRQn_ADC0
|
||||
#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
|
||||
#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A
|
||||
#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U)
|
||||
#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A
|
||||
#define BOARD_BLDC_PWM_TRIG_OUT_CHN (0U)
|
||||
|
||||
/* BLDC TRGM */
|
||||
#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0
|
||||
#define BOARD_BLDC_TRIGMUX_OUT_NUM_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A
|
||||
#define BOARD_BLDC_TRIGMUX_OUT_NUM_VSC HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0
|
||||
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC0 trgm_adc_matrix_output_to_vsc0_adc0
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC1 trgm_adc_matrix_output_to_vsc0_adc1
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC2 trgm_adc_matrix_output_to_vsc0_adc2
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_U trgm_adc_matrix_in_from_adc0
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_V trgm_adc_matrix_in_from_adc1
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_W trgm_adc_matrix_in_from_adc2
|
||||
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_ID_ADC trgm_adc_matrix_output_to_clc0_id_adc
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_IQ_ADC trgm_adc_matrix_output_to_clc0_iq_adc
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_ID_ADC trgm_adc_matrix_in_from_vsc0_id_adc
|
||||
#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_IQ_ADC trgm_adc_matrix_in_from_vsc0_iq_adc
|
||||
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VD_DAC trgm_dac_matrix_output_to_qeo0_vd_dac
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VQ_DAC trgm_dac_matrix_output_to_qeo0_vq_dac
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VD_DAC trgm_dac_matrix_in_from_clc0_vd_dac
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VQ_DAC trgm_dac_matrix_in_from_clc0_vq_dac
|
||||
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC0 trgm_dac_matrix_output_to_pwm1_dac0
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC1 trgm_dac_matrix_output_to_pwm1_dac1
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC2 trgm_dac_matrix_output_to_pwm1_dac2
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC0 trgm_dac_matrix_in_from_qeo0_dac0
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC1 trgm_dac_matrix_in_from_qeo0_dac1
|
||||
#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC2 trgm_dac_matrix_in_from_qeo0_dac2
|
||||
|
||||
#define BOARD_BLDC_TRGM_POS_MATRIX_TO_VSC trgm_pos_matrix_output_to_vsc0
|
||||
#define BOARD_BLDC_TRGM_POS_MATRIX_TO_QEO trgm_pos_matrix_output_to_qeo0
|
||||
#define BOARD_BLDC_TRGM_POS_MATRIX_FROM_QEI trgm_pos_matrix_in_from_qei0
|
||||
|
||||
/* BLDC TIMER */
|
||||
#define BOARD_BLDC_TMR_BASE HPM_GPTMR2
|
||||
#define BOARD_BLDC_TMR_CH 0
|
||||
#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2
|
||||
#define BOARD_BLDC_TMR_CLOCK clock_gptmr2
|
||||
#define BOARD_BLDC_TMR_PERIOD_MS (1u)
|
||||
|
||||
/* HALL */
|
||||
|
||||
/* RDC */
|
||||
#define BOARD_RDC_BASE HPM_RDC0
|
||||
#define BOARD_RDC_TRGM HPM_TRGM0
|
||||
#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0
|
||||
#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0
|
||||
#define BOARD_RDC_TRG_ADC_NUM HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A
|
||||
#define BOARD_RDC_ADC_I_BASE HPM_ADC0
|
||||
#define BOARD_RDC_ADC_Q_BASE HPM_ADC1
|
||||
#define BOARD_RDC_ADC_I_CHN (14U)
|
||||
#define BOARD_RDC_ADC_Q_CHN (10U)
|
||||
#define BOARD_RDC_ADC_IRQn IRQn_ADC0
|
||||
#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete
|
||||
#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A
|
||||
#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_rdc0_adc0
|
||||
#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_rdc0_adc1
|
||||
#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_I trgm_adc_matrix_in_from_adc0
|
||||
#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_Q trgm_adc_matrix_in_from_adc1
|
||||
|
||||
/* QEIV2 */
|
||||
#define BOARD_BLDC_QEI_TRGM HPM_TRGM0
|
||||
#define BOARD_BLDC_QEIV2_BASE HPM_QEI0
|
||||
#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI0
|
||||
#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U)
|
||||
#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_qei0
|
||||
#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U)
|
||||
|
||||
#define BOARD_APP_QEIV2_BASE HPM_QEI3
|
||||
#define BOARD_APP_QEIV2_IRQ IRQn_QEI3
|
||||
#define BOARD_APP_QEI_CLOCK_SOURCE clock_qei3
|
||||
#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC2
|
||||
#define BOARD_APP_QEI_ADC_COS_CHN (11U)
|
||||
#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC0
|
||||
#define BOARD_APP_QEI_ADC_SIN_CHN (14U)
|
||||
#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei3_adc0
|
||||
#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei3_adc1
|
||||
#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc2
|
||||
#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc0
|
||||
|
||||
/* PLB */
|
||||
#define BOARD_PLB_COUNTER HPM_PLB
|
||||
#define BOARD_PLB_PWM_BASE HPM_PWM0
|
||||
#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0
|
||||
#define BOARD_PLB_TRGM HPM_TRGM0
|
||||
#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0)
|
||||
#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00)
|
||||
#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02)
|
||||
#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32)
|
||||
#define BOARD_PLB_TYPEB_INPUT0 (TRGM_TRGOCFG_PLB_IN_32)
|
||||
#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
|
||||
#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO5)
|
||||
#define BOARD_PLB_IO_TRG_SHIFT (5)
|
||||
#define BOARD_PLB_PWM_CMP (8U)
|
||||
#define BOARD_PLB_PWM_CHN (8U)
|
||||
#define BOARD_PLB_CHN plb_chn0
|
||||
|
||||
/* QEO */
|
||||
#define BOARD_QEO HPM_QEO0
|
||||
#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0
|
||||
|
||||
#define BOARD_QEO_PWM HPM_QEO1 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */
|
||||
#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo1
|
||||
|
||||
/* SEI */
|
||||
#define BOARD_SEI HPM_SEI
|
||||
#define BOARD_SEI_CTRL SEI_CTRL_1
|
||||
#define BOARD_SEI_IRQn IRQn_SEI_1
|
||||
#define BOARD_TRGM_POS_SOURCE_SEI trgm_pos_matrix_in_from_sei_pos1
|
||||
|
||||
/* MTG */
|
||||
#define BOARD_TRGM_POS_DEST_MTG trgm_pos_matrix_output_to_mtg0
|
||||
|
||||
/* VSC */
|
||||
#define BOARD_VSC HPM_VSC0
|
||||
#define BOARD_VSC_IRQn IRQn_VSC0
|
||||
|
||||
/* CLC */
|
||||
#define BOARD_CLC HPM_CLC0
|
||||
#define BOARD_CLC_IRQn IRQn_CLC0_0
|
||||
|
||||
/* Tamper Section */
|
||||
#define BOARD_TAMP_ACTIVE_CH 4
|
||||
#define BOARD_TAMP_LOW_LEVEL_CH 3
|
||||
|
||||
/* sdm section */
|
||||
#define BOARD_SDM HPM_SDM0
|
||||
#define BOARD_SDM_IRQ IRQn_SDM0
|
||||
#define BOARD_SDM_CHANNEL 0
|
||||
#define BOARD_SDM_TRGM HPM_TRGM0
|
||||
#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3
|
||||
#define BOARD_SDM_TRGM_GPTMR_CH 2
|
||||
#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2
|
||||
#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15
|
||||
#define BOARD_SDM_TRGM_SYNC_SRC (15)
|
||||
/* need to provide clock to sdm sensor */
|
||||
#define BOARD_SDM_SENSOR_REQUIRE_CLK true
|
||||
#define BOARD_SDM_CLK_PWM HPM_PWM2
|
||||
#define BOARD_SDM_CLK_PWM_CLK_NAME clock_pwm2
|
||||
#define BOARD_SDM_CLK_PWM_OUT (3)
|
||||
|
||||
|
||||
|
||||
/* EtherCAT definitions */
|
||||
/* ECAT PORT0 must support */
|
||||
#define BOARD_ECAT_SUPPORT_PORT1 (1)
|
||||
#define BOARD_ECAT_SUPPORT_PORT2 (0)
|
||||
|
||||
#define BOARD_ECAT_PHY0_RESET_GPIO HPM_GPIO0
|
||||
#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA
|
||||
#define BOARD_ECAT_PHY0_RESET_PIN_INDEX (10)
|
||||
|
||||
#define BOARD_ECAT_PHY1_RESET_GPIO HPM_GPIO0
|
||||
#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA
|
||||
#define BOARD_ECAT_PHY1_RESET_PIN_INDEX (10)
|
||||
#define BOARD_ECAT_PHY_RESET_LEVEL (0)
|
||||
|
||||
#define BOARD_ECAT_IN1_GPIO HPM_GPIO0
|
||||
#define BOARD_ECAT_IN1_GPIO_PORT_INDEX GPIO_DO_GPIOC
|
||||
#define BOARD_ECAT_IN1_GPIO_PIN_INDEX (31U)
|
||||
|
||||
#define BOARD_ECAT_IN2_GPIO HPM_GPIO0
|
||||
#define BOARD_ECAT_IN2_GPIO_PORT_INDEX GPIO_DO_GPIOD
|
||||
#define BOARD_ECAT_IN2_GPIO_PIN_INDEX (9U)
|
||||
|
||||
#define BOARD_ECAT_OUT1_GPIO HPM_GPIO0
|
||||
#define BOARD_ECAT_OUT1_GPIO_PORT_INDEX GPIO_DO_GPIOD
|
||||
#define BOARD_ECAT_OUT1_GPIO_PIN_INDEX (8U)
|
||||
|
||||
#define BOARD_ECAT_OUT2_GPIO BOARD_R_GPIO_CTRL /* reuse RGB red led */
|
||||
#define BOARD_ECAT_OUT2_GPIO_PORT_INDEX BOARD_R_GPIO_INDEX
|
||||
#define BOARD_ECAT_OUT2_GPIO_PIN_INDEX BOARD_R_GPIO_PIN
|
||||
|
||||
#define BOARD_ECAT_OUT_ON_LEVEL (1) /* ECAT control LED on level */
|
||||
|
||||
#define BOARD_ECAT_NMII_LINK0_CTRL_INDEX 3
|
||||
#define BOARD_ECAT_NMII_LINK1_CTRL_INDEX 0
|
||||
#define BOARD_ECAT_LED_RUN_CTRL_INDEX 1
|
||||
#define BOARD_ECAT_LED_ERROR_CTRL_INDEX 6
|
||||
|
||||
#ifndef BOARD_SHOW_CLOCK
|
||||
#define BOARD_SHOW_CLOCK 1
|
||||
#endif
|
||||
#ifndef BOARD_SHOW_BANNER
|
||||
#define BOARD_SHOW_BANNER 1
|
||||
#endif
|
||||
|
||||
/* FreeRTOS Definitions */
|
||||
#define BOARD_FREERTOS_TIMER HPM_GPTMR6
|
||||
#define BOARD_FREERTOS_TIMER_CHANNEL 1
|
||||
#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6
|
||||
#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6
|
||||
|
||||
#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR
|
||||
#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1
|
||||
#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR
|
||||
#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
|
||||
/* Threadx Definitions */
|
||||
#define BOARD_THREADX_TIMER HPM_GPTMR6
|
||||
#define BOARD_THREADX_TIMER_CHANNEL 1
|
||||
#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6
|
||||
#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6
|
||||
|
||||
#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR
|
||||
#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1
|
||||
#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR
|
||||
#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
|
||||
|
||||
/* LOBS */
|
||||
#define BOARD_LOBS_TRIG_GROUP 5 /* group5 <--> PF */
|
||||
#define BOARD_LOBS_TRIG_PIN 26
|
||||
|
||||
/* i2s over spi Section*/
|
||||
#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define BOARD_I2S_SPI_CS_GPIO_PIN 6
|
||||
#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA06
|
||||
|
||||
#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR5
|
||||
#define BOARD_GPTMR_I2S_MCLK_CHANNEL 2
|
||||
#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr5
|
||||
|
||||
#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR4
|
||||
#define BOARD_GPTMR_I2S_LRCK_CHANNEL 0
|
||||
#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr4
|
||||
|
||||
#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0
|
||||
#define BOARD_GPTMR_I2S_BLCK_CHANNEL 0
|
||||
#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
|
||||
|
||||
#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0
|
||||
#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0
|
||||
#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1
|
||||
#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef void (*board_timer_cb)(void);
|
||||
|
||||
void board_init(void);
|
||||
void board_init_console(void);
|
||||
void board_init_core1(void);
|
||||
void board_init_uart(UART_Type *ptr);
|
||||
void board_init_i2c(I2C_Type *ptr);
|
||||
void board_init_can(MCAN_Type *ptr);
|
||||
void board_init_sdram_pins(void);
|
||||
void board_init_gpio_pins(void);
|
||||
void board_init_spi_pins(SPI_Type *ptr);
|
||||
void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
|
||||
void board_write_spi_cs(uint32_t pin, uint8_t state);
|
||||
uint8_t board_get_led_gpio_off_level(void);
|
||||
void board_init_led_pins(void);
|
||||
void board_led_write(uint8_t state);
|
||||
void board_led_toggle(void);
|
||||
|
||||
/* Initialize SoC overall clocks */
|
||||
void board_init_clock(void);
|
||||
uint32_t board_init_femc_clock(void);
|
||||
uint32_t board_init_uart_clock(UART_Type *ptr);
|
||||
uint32_t board_init_spi_clock(SPI_Type *ptr);
|
||||
uint32_t board_init_can_clock(MCAN_Type *ptr);
|
||||
uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb);
|
||||
void board_init_i2s_pins(I2S_Type *ptr);
|
||||
uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate);
|
||||
uint32_t board_init_pdm_clock(void);
|
||||
uint32_t board_init_dao_clock(void);
|
||||
void board_init_dao_pins(void);
|
||||
void board_init_adc16_pins(void);
|
||||
void board_init_usb_pins(void);
|
||||
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
|
||||
void board_init_enet_pps_pins(ENET_Type *ptr);
|
||||
uint8_t board_get_enet_dma_pbl(ENET_Type *ptr);
|
||||
hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
|
||||
hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
|
||||
hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
|
||||
hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr);
|
||||
hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
|
||||
hpm_stat_t board_enable_enet_irq(ENET_Type *ptr);
|
||||
hpm_stat_t board_disable_enet_irq(ENET_Type *ptr);
|
||||
|
||||
/*
|
||||
* @brief Initialize PMP and PMA for but not limited to the following purposes:
|
||||
* -- non-cacheable memory initialization
|
||||
*/
|
||||
void board_init_pmp(void);
|
||||
void board_delay_us(uint32_t us);
|
||||
void board_delay_ms(uint32_t ms);
|
||||
void board_timer_create(uint32_t ms, board_timer_cb cb);
|
||||
void board_ungate_mchtmr_at_lp_mode(void);
|
||||
|
||||
/*
|
||||
* Get GPIO pin level of onboard LED
|
||||
*/
|
||||
uint8_t board_get_led_gpio_off_level(void);
|
||||
void board_init_ethercat(ESC_Type *ptr);
|
||||
void board_init_switch_led(void);
|
||||
void board_init_tsw(TSW_Type *ptr);
|
||||
void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
|
||||
void board_init_adc_qeiv2_pins(void);
|
||||
|
||||
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
|
||||
uint32_t board_init_pwm_clock(PWMV2_Type *ptr);
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _HPM_BOARD_H */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit 6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x1
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000800
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000810
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000820
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000830
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event gdb-attach {
|
||||
reset halt
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/cmsis-dap.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0208 0x020b
|
||||
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6014
|
||||
|
||||
ftdi_layout_init 0x0018 0x001b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/jlink.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
reset_config srst_only
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x010b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
|
||||
set _CHIP hpm6e00
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
|
||||
proc dmi_write {reg value} {
|
||||
$::_TARGET0 riscv dmi_write ${reg} ${value}
|
||||
}
|
||||
|
||||
proc dmi_read {reg} {
|
||||
set v [$::_TARGET0 riscv dmi_read ${reg}]
|
||||
return ${v}
|
||||
}
|
||||
proc dmi_write_memory {addr value} {
|
||||
dmi_write 0x39 ${addr}
|
||||
dmi_write 0x3C ${value}
|
||||
}
|
||||
|
||||
proc dmi_read_memory {addr} {
|
||||
set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
|
||||
dmi_write 0x38 ${sbcs}
|
||||
dmi_write 0x39 ${addr}
|
||||
set value [dmi_read 0x3C]
|
||||
return ${value}
|
||||
}
|
||||
|
||||
proc release_core1 {} {
|
||||
dmi_write_memory 0xF4002C00 0x1000
|
||||
}
|
||||
|
||||
set _TARGET1 $_CHIP.cpu1
|
||||
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
|
||||
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
$_TARGET1 configure -event examine-start {
|
||||
release_core1
|
||||
}
|
||||
|
||||
$_TARGET1 configure -event reset-deassert-pre {
|
||||
$::_TARGET0 arp_poll
|
||||
release_core1
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-end {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002010
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
}
|
||||
|
||||
proc reset_soc {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF410001C
|
||||
$::_TARGET0 riscv dmi_write 0x3C 24000000
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
set _CHIP hpm6e00
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
|
||||
proc reset_soc {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF410001C
|
||||
$::_TARGET0 riscv dmi_write 0x3C 24000000
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2022 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_FAL
|
||||
#define NOR_FLASH_DEV_NAME "norflash0"
|
||||
#define NOR_FLASH_MEM_BASE 0x80000000UL
|
||||
#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL
|
||||
|
||||
/* ===================== Flash device Configuration ========================= */
|
||||
extern const struct fal_flash_dev stm32f2_onchip_flash;
|
||||
extern struct fal_flash_dev nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&nor_flash0, \
|
||||
}
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#ifdef CONFIG_WEBNET_FAL_FS
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \
|
||||
}
|
||||
#else
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
#endif /* RT_USING_FAL */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Copyright (c) 2022 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-03-09 hpmicro First implementation
|
||||
* 2022-08-01 hpmicro Fixed random crashing during kvdb_init
|
||||
* 2022-08-03 hpmicro Improved erase speed
|
||||
* 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build
|
||||
*
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#ifdef RT_USING_FAL
|
||||
#include "fal.h"
|
||||
#include "hpm_romapi.h"
|
||||
#include "board.h"
|
||||
#include "hpm_l1c_drv.h"
|
||||
|
||||
#if defined(FLASH_XIP) && (FLASH_XIP == 1)
|
||||
|
||||
static rt_base_t s_interrupt_level;
|
||||
#define FAL_ENTER_CRITICAL() do {\
|
||||
rt_exit_critical();\
|
||||
fencei();\
|
||||
s_interrupt_level = rt_hw_interrupt_disable();\
|
||||
} while(0)
|
||||
|
||||
#define FAL_EXIT_CRITICAL() do {\
|
||||
ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
|
||||
fencei();\
|
||||
rt_exit_critical();\
|
||||
rt_hw_interrupt_enable(s_interrupt_level);\
|
||||
} while(0)
|
||||
|
||||
#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
|
||||
|
||||
#else
|
||||
#define FAL_ENTER_CRITICAL() rt_enter_critical()
|
||||
|
||||
#define FAL_EXIT_CRITICAL() rt_exit_critical()
|
||||
|
||||
#define FAL_RAMFUNC
|
||||
|
||||
#endif
|
||||
|
||||
/***************************************************************************************************
|
||||
* FAL Porting Guide
|
||||
*
|
||||
* 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
|
||||
* must be placed at RAM or ROM code
|
||||
* 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
|
||||
* interrupt related codes to RAM
|
||||
*
|
||||
***************************************************************************************************/
|
||||
|
||||
static int init(void);
|
||||
static int read(long offset, uint8_t *buf, size_t size);
|
||||
static int write(long offset, const uint8_t *buf, size_t size);
|
||||
static int erase(long offset, size_t size);
|
||||
|
||||
static xpi_nor_config_t s_flashcfg;
|
||||
|
||||
/**
|
||||
* @brief FAL Flash device context
|
||||
*/
|
||||
struct fal_flash_dev nor_flash0 =
|
||||
{
|
||||
.name = NOR_FLASH_DEV_NAME,
|
||||
/* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
|
||||
.addr = NOR_FLASH_MEM_BASE,
|
||||
.len = 8 * 1024 * 1024,
|
||||
.blk_size = 4096,
|
||||
.ops = { .init = init, .read = read, .write = write, .erase = erase },
|
||||
.write_gran = 1
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief FAL initialization
|
||||
* This function probes the FLASH using the ROM API
|
||||
*/
|
||||
FAL_RAMFUNC static int init(void)
|
||||
{
|
||||
int ret = RT_EOK;
|
||||
xpi_nor_config_option_t cfg_option;
|
||||
cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
|
||||
cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
|
||||
cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
|
||||
|
||||
FAL_ENTER_CRITICAL();
|
||||
hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
|
||||
FAL_EXIT_CRITICAL();
|
||||
if (status != status_success)
|
||||
{
|
||||
ret = -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* update the flash chip information */
|
||||
uint32_t sector_size;
|
||||
rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size);
|
||||
uint32_t flash_size;
|
||||
rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
|
||||
nor_flash0.blk_size = sector_size;
|
||||
nor_flash0.len = flash_size;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FAL read function
|
||||
* Read data from FLASH
|
||||
* @param offset FLASH offset
|
||||
* @param buf Buffer to hold data read by this API
|
||||
* @param size Size of data to be read
|
||||
* @return actual read bytes
|
||||
*/
|
||||
FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size)
|
||||
{
|
||||
uint32_t flash_addr = nor_flash0.addr + offset;
|
||||
uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
|
||||
uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
|
||||
uint32_t aligned_size = aligned_end - aligned_start;
|
||||
rt_base_t level = rt_hw_interrupt_disable();
|
||||
l1c_dc_invalidate(aligned_start, aligned_size);
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
(void) rt_memcpy(buf, (void*) flash_addr, size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write unaligned data to the page
|
||||
* @param offset FLASH offset
|
||||
* @param buf Data buffer
|
||||
* @param size Size of data to be written
|
||||
* @return actual size of written data or error code
|
||||
*/
|
||||
FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size)
|
||||
{
|
||||
hpm_stat_t status;
|
||||
|
||||
FAL_ENTER_CRITICAL();
|
||||
status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
|
||||
FAL_EXIT_CRITICAL();
|
||||
|
||||
if (status != status_success)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
rt_kprintf("write failed, status=%d\n", status);
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FAL write function
|
||||
* Write data to specified FLASH address
|
||||
* @param offset FLASH offset
|
||||
* @param buf Data buffer
|
||||
* @param size Size of data to be written
|
||||
* @return actual size of written data or error code
|
||||
*/
|
||||
FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size)
|
||||
{
|
||||
uint32_t *src = NULL;
|
||||
uint32_t buf_32[64];
|
||||
uint32_t write_size;
|
||||
size_t remaining_size = size;
|
||||
int ret = (int)size;
|
||||
|
||||
uint32_t page_size;
|
||||
rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
|
||||
uint32_t offset_in_page = offset % page_size;
|
||||
if (offset_in_page != 0)
|
||||
{
|
||||
uint32_t write_size_in_page = page_size - offset_in_page;
|
||||
uint32_t write_page_size = MIN(write_size_in_page, size);
|
||||
(void) rt_memcpy(buf_32, buf, write_page_size);
|
||||
write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
|
||||
if (write_size < 0)
|
||||
{
|
||||
ret = -RT_ERROR;
|
||||
goto write_quit;
|
||||
}
|
||||
|
||||
remaining_size -= write_page_size;
|
||||
offset += write_page_size;
|
||||
buf += write_page_size;
|
||||
}
|
||||
|
||||
while (remaining_size > 0)
|
||||
{
|
||||
write_size = MIN(remaining_size, sizeof(buf_32));
|
||||
rt_memcpy(buf_32, buf, write_size);
|
||||
src = &buf_32[0];
|
||||
|
||||
FAL_ENTER_CRITICAL();
|
||||
hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
|
||||
offset, write_size);
|
||||
FAL_EXIT_CRITICAL();
|
||||
|
||||
if (status != status_success)
|
||||
{
|
||||
ret = -RT_ERROR;
|
||||
rt_kprintf("write failed, status=%d\n", status);
|
||||
break;
|
||||
}
|
||||
|
||||
remaining_size -= write_size;
|
||||
buf += write_size;
|
||||
offset += write_size;
|
||||
}
|
||||
|
||||
write_quit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FAL erase function
|
||||
* Erase specified FLASH region
|
||||
* @param offset the start FLASH address to be erased
|
||||
* @param size size of the region to be erased
|
||||
* @ret RT_EOK Erase operation is successful
|
||||
* @retval -RT_ERROR Erase operation failed
|
||||
*/
|
||||
FAL_RAMFUNC static int erase(long offset, size_t size)
|
||||
{
|
||||
uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
|
||||
hpm_stat_t status;
|
||||
int ret = (int)size;
|
||||
|
||||
uint32_t block_size;
|
||||
uint32_t sector_size;
|
||||
(void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size);
|
||||
(void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
|
||||
uint32_t erase_unit;
|
||||
while (aligned_size > 0)
|
||||
{
|
||||
FAL_ENTER_CRITICAL();
|
||||
if ((offset % block_size == 0) && (aligned_size >= block_size))
|
||||
{
|
||||
erase_unit = block_size;
|
||||
status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
|
||||
}
|
||||
else
|
||||
{
|
||||
erase_unit = sector_size;
|
||||
status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
|
||||
}
|
||||
FAL_EXIT_CRITICAL();
|
||||
|
||||
if (status != status_success)
|
||||
{
|
||||
ret = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
offset += erase_unit;
|
||||
aligned_size -= erase_unit;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* RT_USING_FAL */
|
||||
|
|
@ -0,0 +1,543 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright (c) 2022 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "hpm_wm8960.h"
|
||||
|
||||
#ifndef HPM_WM8960_MCLK_TOLERANCE
|
||||
#define HPM_WM8960_MCLK_TOLERANCE (4U)
|
||||
#endif
|
||||
|
||||
/* wm8960 register default value */
|
||||
static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = {
|
||||
0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9,
|
||||
};
|
||||
|
||||
/* store reg value */
|
||||
static uint16_t wm8960_reg_val[WM8960_REG_NUM];
|
||||
|
||||
hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config)
|
||||
{
|
||||
assert(control != NULL);
|
||||
assert(config != NULL);
|
||||
|
||||
hpm_stat_t stat = status_success;
|
||||
|
||||
(void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val));
|
||||
|
||||
/* Reset */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00));
|
||||
|
||||
/* Power on input modules */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE));
|
||||
/* Power on output modules */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8));
|
||||
/* Power on PGA and mixer */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C));
|
||||
|
||||
/* ADC and DAC uses same clock */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40));
|
||||
|
||||
/* set data protocol */
|
||||
HPM_CHECK_RET(wm8960_set_protocol(control, config->bus));
|
||||
|
||||
/* set wm8960 as slave */
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0)));
|
||||
|
||||
/* invert LRCLK */
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1)));
|
||||
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40));
|
||||
|
||||
/* ADC volume, 8dB */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3));
|
||||
|
||||
/* Digital DAC volume, 0dB */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0));
|
||||
|
||||
/* Headphone volume, LOUT1 and ROUT1, 6dB */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F));
|
||||
|
||||
/* speaker volume 6dB */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff));
|
||||
/* enable class D output */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7));
|
||||
|
||||
/* Unmute DAC. */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117));
|
||||
|
||||
HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width));
|
||||
|
||||
/* set data route */
|
||||
HPM_CHECK_RET(wm8960_set_data_route(control, config));
|
||||
|
||||
return status_success;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_deinit(wm8960_control_t *control)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
|
||||
/* power off all modules */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U));
|
||||
|
||||
return status_success;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol)
|
||||
{
|
||||
return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol);
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
switch (module) {
|
||||
case wm8960_module_adc:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_dac:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_DACL_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_DACR_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_vref:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_VREF_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_ana_in:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_AINL_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_AINR_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK,
|
||||
((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK,
|
||||
((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_lineout:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_micbais:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK,
|
||||
((uint16_t)enable << WM8960_POWER1_MICB_SHIFT)));
|
||||
break;
|
||||
case wm8960_module_speaker:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK,
|
||||
((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7));
|
||||
break;
|
||||
case wm8960_module_output_mixer:
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK,
|
||||
((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT)));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK,
|
||||
((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT)));
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
|
||||
/* select left input */
|
||||
HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input));
|
||||
/* select right input */
|
||||
HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input));
|
||||
/* select source to output mixer */
|
||||
HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source));
|
||||
|
||||
switch (config->route) {
|
||||
case wm8960_route_bypass:
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true));
|
||||
break;
|
||||
case wm8960_route_playback:
|
||||
/* I2S_IN-> DAC-> HP */
|
||||
/* Set power for DAC */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true));
|
||||
break;
|
||||
case wm8960_route_playback_and_record:
|
||||
/* Set power */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true));
|
||||
break;
|
||||
case wm8960_route_record:
|
||||
/* ANA_IN->ADC->I2S_OUT */
|
||||
/* Power up ADC and AIN */
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true));
|
||||
HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true));
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
uint16_t val = 0;
|
||||
|
||||
switch (input) {
|
||||
case wm8960_input_closed:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
break;
|
||||
case wm8960_input_single_ended_mic:
|
||||
/* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_differential_mic_input2:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_differential_mic_input3:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_line_input2:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val));
|
||||
val |= 0xEU;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val));
|
||||
break;
|
||||
case wm8960_input_line_input3:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val));
|
||||
val |= 0x70U;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val));
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
uint16_t val = 0;
|
||||
|
||||
switch (input) {
|
||||
case wm8960_input_closed:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
break;
|
||||
case wm8960_input_single_ended_mic:
|
||||
/* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_differential_mic_input2:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_differential_mic_input3:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117));
|
||||
break;
|
||||
case wm8960_input_line_input2:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val));
|
||||
val |= 0xEU;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val));
|
||||
break;
|
||||
case wm8960_input_line_input3:
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val));
|
||||
val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val));
|
||||
HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val));
|
||||
val |= 0x70U;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val));
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume)
|
||||
{
|
||||
uint16_t vol = 0;
|
||||
hpm_stat_t stat = status_success;
|
||||
switch (module) {
|
||||
case wm8960_module_adc:
|
||||
if (volume > 255U) {
|
||||
stat = status_invalid_argument;
|
||||
} else {
|
||||
vol = (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol));
|
||||
/* Update volume */
|
||||
vol = (uint16_t)(0x100U | volume);
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol));
|
||||
}
|
||||
break;
|
||||
case wm8960_module_dac:
|
||||
if (volume > 255U) {
|
||||
stat = status_invalid_argument;
|
||||
} else {
|
||||
vol = (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol));
|
||||
vol = 0x100U | (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol));
|
||||
}
|
||||
break;
|
||||
case wm8960_module_headphone:
|
||||
if (volume > 0x7FU) {
|
||||
stat = status_invalid_argument;
|
||||
} else {
|
||||
vol = (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol));
|
||||
vol = 0x100U | (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol));
|
||||
}
|
||||
break;
|
||||
case wm8960_module_ana_in:
|
||||
if (volume > 0x3FU) {
|
||||
stat = status_invalid_argument;
|
||||
} else {
|
||||
vol = (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol));
|
||||
vol = 0x100U | (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol));
|
||||
}
|
||||
break;
|
||||
case wm8960_module_speaker:
|
||||
if (volume > 0x7FU) {
|
||||
stat = status_invalid_argument;
|
||||
} else {
|
||||
vol = (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol));
|
||||
vol = 0x100U | (uint16_t)volume;
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol));
|
||||
HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target)
|
||||
{
|
||||
uint32_t delta = (source >= target) ? (source - target) : (target - source);
|
||||
if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
uint16_t val = 0;
|
||||
uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6};
|
||||
bool clock_meet_requirement = false;
|
||||
|
||||
if (sysclk / sample_rate > 256 * 6) {
|
||||
sysclk = sysclk / 2;
|
||||
val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < 7; i++) {
|
||||
if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) {
|
||||
val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT));
|
||||
clock_meet_requirement = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!clock_meet_requirement) {
|
||||
return status_invalid_argument;
|
||||
}
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val));
|
||||
|
||||
/* set sample bit */
|
||||
switch (bits) {
|
||||
case 16:
|
||||
stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U));
|
||||
break;
|
||||
case 20:
|
||||
stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U));
|
||||
break;
|
||||
case 24:
|
||||
stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U));
|
||||
break;
|
||||
case 32:
|
||||
stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U));
|
||||
break;
|
||||
default:
|
||||
stat = status_invalid_argument;
|
||||
break;
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source)
|
||||
{
|
||||
hpm_stat_t stat = status_success;
|
||||
|
||||
if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) {
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U));
|
||||
}
|
||||
|
||||
if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) {
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U));
|
||||
}
|
||||
|
||||
if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) {
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U));
|
||||
HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U));
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
|
||||
hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val)
|
||||
{
|
||||
/* The first 7 bits (B15 to B9) are address bits that select which control register */
|
||||
/* is accessed. The remaining 9 bits (B8 to B0) are data bits */
|
||||
rt_size_t size;
|
||||
rt_uint8_t data[2];
|
||||
data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U);
|
||||
data[1] = (uint8_t)(val & 0xFFU);
|
||||
|
||||
size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U);
|
||||
if (size != 2) {
|
||||
return status_fail;
|
||||
}
|
||||
|
||||
wm8960_reg_val[reg] = val;
|
||||
return status_success;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val)
|
||||
{
|
||||
if (reg >= WM8960_REG_NUM) {
|
||||
return status_invalid_argument;
|
||||
}
|
||||
*val = wm8960_reg_val[reg];
|
||||
|
||||
return status_success;
|
||||
}
|
||||
|
||||
hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val)
|
||||
{
|
||||
hpm_stat_t stat = 0;
|
||||
uint16_t reg_val;
|
||||
|
||||
/* Read the register value out */
|
||||
stat = wm8960_read_reg(reg, ®_val);
|
||||
if (stat != status_success) {
|
||||
return status_fail;
|
||||
}
|
||||
|
||||
/* Modify the value */
|
||||
reg_val &= (uint16_t)~mask;
|
||||
reg_val |= val;
|
||||
|
||||
/* Write the data to register */
|
||||
stat = wm8960_write_reg(control, reg, reg_val);
|
||||
if (stat != status_success) {
|
||||
return status_fail;
|
||||
}
|
||||
|
||||
return status_success;
|
||||
}
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* Copyright (c) 2022 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPM_WM8960_H_
|
||||
#define _HPM_WM8960_H_
|
||||
|
||||
//#include "hpm_i2c_drv.h"
|
||||
//#include "hpm_common.h"
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "rtt_board.h"
|
||||
#include "drivers/i2c.h"
|
||||
#include "hpm_wm8960_regs.h"
|
||||
|
||||
#define WM8960_I2C_ADDR 0x1A
|
||||
|
||||
typedef enum wm8960_module {
|
||||
wm8960_module_adc = 0, /* ADC module in WM8960 */
|
||||
wm8960_module_dac = 1, /* DAC module in WM8960 */
|
||||
wm8960_module_vref = 2, /* VREF module */
|
||||
wm8960_module_headphone = 3, /* Headphone */
|
||||
wm8960_module_micbais = 4, /* Mic bias */
|
||||
wm8960_module_ana_in = 6, /* Analog in PGA */
|
||||
wm8960_module_lineout = 7, /* Line out module */
|
||||
wm8960_module_speaker = 8, /* Speaker module */
|
||||
wm8960_module_output_mixer = 9, /* Output mixer */
|
||||
} wm8960_module_t;
|
||||
|
||||
/* wm8960 play source for output mixer */
|
||||
typedef enum wm8960_play_source {
|
||||
wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */
|
||||
wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */
|
||||
wm8960_play_source_dac = 4, /* DAC to Output Mixer */
|
||||
} wm8960_play_source_t;
|
||||
|
||||
/* WM8960 data route */
|
||||
typedef enum wm8960_route {
|
||||
wm8960_route_bypass = 0, /* ANA_IN->Headphone. */
|
||||
wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */
|
||||
wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */
|
||||
wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */
|
||||
} wm8960_route_t;
|
||||
|
||||
/* The audio data transfer protocol choice */
|
||||
typedef enum wm8960_protocol {
|
||||
wm8960_bus_i2s = 2, /* I2S type */
|
||||
wm8960_bus_left_justified = 1, /* Left justified mode */
|
||||
wm8960_bus_right_justified = 0, /* Right justified mode */
|
||||
wm8960_bus_pcma = 3, /* PCM A mode */
|
||||
wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */
|
||||
} wm8960_protocol_t;
|
||||
|
||||
/* wm8960 input source */
|
||||
typedef enum wm8960_input {
|
||||
wm8960_input_closed = 0, /* Input device is closed */
|
||||
wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */
|
||||
wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */
|
||||
wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/
|
||||
wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */
|
||||
wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */
|
||||
} wm8960_input_t;
|
||||
|
||||
/* wm8960 audio format */
|
||||
typedef struct wm8960_audio_format {
|
||||
uint32_t mclk_hz; /* master clock frequency */
|
||||
uint32_t sample_rate; /* sample rate */
|
||||
uint32_t bit_width; /* bit width */
|
||||
} wm8960_audio_format_t;
|
||||
|
||||
/* configure structure of WM8960 */
|
||||
typedef struct wm8960_config {
|
||||
wm8960_route_t route; /* Audio data route.*/
|
||||
wm8960_protocol_t bus; /* Audio transfer protocol */
|
||||
bool enable_speaker; /* True means enable class D speaker as output, false means no */
|
||||
wm8960_input_t left_input; /* Left input source for WM8960 */
|
||||
wm8960_input_t right_input; /* Right input source for wm8960 */
|
||||
wm8960_play_source_t play_source; /* play source */
|
||||
wm8960_audio_format_t format; /* Audio format */
|
||||
} wm8960_config_t;
|
||||
|
||||
typedef struct {
|
||||
struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */
|
||||
uint8_t slave_address; /* code device address */
|
||||
} wm8960_control_t;
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief WM8960 initialize function.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param config WM8960 configuration structure.
|
||||
*/
|
||||
hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Deinit the WM8960 codec.
|
||||
*
|
||||
* This function close all modules in WM8960 to save power.
|
||||
*
|
||||
* @param control WM8960 control structure pointer.
|
||||
*/
|
||||
hpm_stat_t wm8960_deinit(wm8960_control_t *control);
|
||||
|
||||
/**
|
||||
* @brief Set audio data route in WM8960.
|
||||
*
|
||||
* This function would set the data route according to route.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param config Audio configure structure in WM8960.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Set left audio input source in WM8960.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param input Audio input source.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input);
|
||||
|
||||
/**
|
||||
* @brief Set right audio input source in WM8960.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param input Audio input source.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input);
|
||||
|
||||
/**
|
||||
* @brief Set the audio transfer protocol.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param protocol Audio data transfer protocol.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol);
|
||||
|
||||
/**
|
||||
* @brief Set the volume of different modules in WM8960.
|
||||
*
|
||||
* This function would set the volume of WM8960 modules. Uses need to appoint the module.
|
||||
* The function assume that left channel and right channel has the same volume.
|
||||
*
|
||||
* Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db
|
||||
* Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db
|
||||
* Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db
|
||||
* Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db
|
||||
* Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db
|
||||
*
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param module Module to set volume, it can be ADC, DAC, Headphone and so on.
|
||||
* @param volume Volume value need to be set.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume);
|
||||
|
||||
/**
|
||||
* @brief Enable/disable expected module.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param module Module expected to enable.
|
||||
* @param enable Enable or disable moudles.
|
||||
*/
|
||||
hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable);
|
||||
|
||||
/**
|
||||
* @brief SET the WM8960 play source.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param play_source play source
|
||||
*
|
||||
* @return kStatus_WM8904_Success if successful, different code otherwise..
|
||||
*/
|
||||
hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source);
|
||||
|
||||
/**
|
||||
* @brief Configure the data format of audio data.
|
||||
*
|
||||
* This function would configure the registers about the sample rate, bit depths.
|
||||
*
|
||||
* @param control WM8960 control structure pointer.
|
||||
* @param sysclk system clock of the codec which can be generated by MCLK or PLL output.
|
||||
* @param sample_rate Sample rate of audio file running in WM8960. WM8960 now
|
||||
* supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate.
|
||||
* @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit
|
||||
* and 32 bit in HW).
|
||||
*/
|
||||
hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write register to WM8960 using I2C.
|
||||
*
|
||||
* @param control WM8960 control structure.
|
||||
* @param reg The register address in WM8960.
|
||||
* @param val Value needs to write into the register.
|
||||
*/
|
||||
hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val);
|
||||
|
||||
/**
|
||||
* @brief Read register from WM8960 using I2C.
|
||||
* @param reg The register address in WM8960.
|
||||
* @param val Value written to.
|
||||
*/
|
||||
hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val);
|
||||
|
||||
/**
|
||||
* @brief Modify some bits in the register using I2C.
|
||||
* @param control WM8960 control structure.
|
||||
* @param reg The register address in WM8960.
|
||||
* @param mask The mask code for the bits want to write. The bit you want to write should be 0.
|
||||
* @param val Value needs to write into the register.
|
||||
*/
|
||||
hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val);
|
||||
|
||||
|
||||
#endif /* _HPM_WM8960_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* Copyright 2021-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
|
||||
HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
|
||||
FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
|
||||
NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
|
||||
ILM (wx) : ORIGIN = 0, LENGTH = 256K
|
||||
DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K
|
||||
AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K
|
||||
NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE
|
||||
AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k
|
||||
}
|
||||
|
||||
__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
|
||||
__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
|
||||
__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
|
||||
__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
|
||||
__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.nor_cfg_option __nor_cfg_option_load_addr__ : {
|
||||
KEEP(*(.nor_cfg_option))
|
||||
} > XPI0
|
||||
|
||||
.boot_header __boot_header_load_addr__ : {
|
||||
__boot_header_start__ = .;
|
||||
KEEP(*(.boot_header))
|
||||
KEEP(*(.fw_info_table))
|
||||
KEEP(*(.dc_info))
|
||||
__boot_header_end__ = .;
|
||||
} > XPI0
|
||||
|
||||
.start __app_load_addr__ : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.start))
|
||||
} > XPI0
|
||||
|
||||
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
|
||||
.vectors : AT(__vector_load_addr__) {
|
||||
. = ALIGN(8);
|
||||
__vector_ram_start__ = .;
|
||||
KEEP(*(.vector_table))
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
. = ALIGN(8);
|
||||
__vector_ram_end__ = .;
|
||||
} > ILM
|
||||
|
||||
.fast : AT(etext + __data_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
__ramfunc_start__ = .;
|
||||
*(.fast)
|
||||
|
||||
/* RT-Thread Core Start */
|
||||
KEEP(*context_gcc.o(.text* .rodata*))
|
||||
KEEP(*port*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*trap_common.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*irq.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*clock.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*kservice.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*scheduler.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*trap*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*idle.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*ipc.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*thread.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*object.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*timer.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*mem.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*mempool.o (.text .text* .rodata .rodata*))
|
||||
/* RT-Thread Core End */
|
||||
|
||||
/* HPMicro Driver Wrapper */
|
||||
KEEP(*drv_*.o (.text .text* .rodata .rodata*))
|
||||
|
||||
. = ALIGN(8);
|
||||
__ramfunc_end__ = .;
|
||||
} > ILM
|
||||
|
||||
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
|
||||
. = ALIGN(8);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.srodata)
|
||||
*(.srodata*)
|
||||
|
||||
*(.hash)
|
||||
*(.dyn*)
|
||||
*(.gnu*)
|
||||
*(.pl*)
|
||||
|
||||
KEEP(*(.eh_frame))
|
||||
*(.eh_frame*)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(8);
|
||||
|
||||
/*********************************************
|
||||
*
|
||||
* RT-Thread related sections - Start
|
||||
*
|
||||
*********************************************/
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
} > XPI0
|
||||
|
||||
.rel : {
|
||||
KEEP(*(.rel*))
|
||||
} > XPI0
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.fast_ram (NOLOAD) : {
|
||||
KEEP(*(.fast_ram))
|
||||
} > DLM
|
||||
|
||||
.bss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(.scommon)
|
||||
*(.scommon*)
|
||||
*(.dynsbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
__bss_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
/* Note: the .tbss and .tdata section should be adjacent */
|
||||
.tbss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__tbss_start__ = .;
|
||||
*(.tbss*)
|
||||
*(.tcommon*)
|
||||
_end = .;
|
||||
__tbss_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.tdata : AT(etext) {
|
||||
. = ALIGN(8);
|
||||
__tdata_start__ = .;
|
||||
__thread_pointer = .;
|
||||
*(.tdata)
|
||||
*(.tdata*)
|
||||
. = ALIGN(8);
|
||||
__tdata_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.data : AT(etext + __tdata_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
__data_start__ = .;
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.sdata)
|
||||
*(.sdata*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
KEEP(*(.dynamic))
|
||||
KEEP(*(.got*))
|
||||
KEEP(*(.got))
|
||||
KEEP(*(.gcc_except_table))
|
||||
KEEP(*(.gcc_except_table.*))
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE(__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__finit_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
|
||||
KEEP(*(.finit_array))
|
||||
PROVIDE(__finit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*crtbegin*.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
KEEP(*crtbegin*.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
. = ALIGN(8);
|
||||
__data_end__ = .;
|
||||
PROVIDE (__edata = .);
|
||||
PROVIDE (_edata = .);
|
||||
PROVIDE (edata = .);
|
||||
} > AXI_SRAM
|
||||
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
|
||||
|
||||
.heap(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__heap_start__ = .;
|
||||
. += HEAP_SIZE;
|
||||
__heap_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.framebuffer (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.framebuffer))
|
||||
. = ALIGN(8);
|
||||
} > AXI_SRAM
|
||||
|
||||
.stack(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__stack_base__ = .;
|
||||
. += STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
PROVIDE (_stack = .);
|
||||
PROVIDE (_stack_in_dlm = .);
|
||||
PROVIDE( __rt_rvstack = . );
|
||||
} > AXI_SRAM
|
||||
|
||||
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
|
||||
. = ALIGN(8);
|
||||
__noncacheable_init_start__ = .;
|
||||
KEEP(*(.noncacheable.init))
|
||||
__noncacheable_init_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
.noncacheable.bss (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.noncacheable))
|
||||
__noncacheable_bss_start__ = .;
|
||||
KEEP(*(.noncacheable.bss))
|
||||
__noncacheable_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
.ahb_sram (NOLOAD) : {
|
||||
KEEP(*(.ahb_sram))
|
||||
} > AHB_SRAM
|
||||
|
||||
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
|
||||
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,316 @@
|
|||
/*
|
||||
* Copyright 2021-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
|
||||
HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
|
||||
FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
|
||||
NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
|
||||
ILM (wx) : ORIGIN = 0, LENGTH = 256K
|
||||
DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K
|
||||
AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K
|
||||
NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE
|
||||
AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k
|
||||
}
|
||||
|
||||
__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
|
||||
__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
|
||||
__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
|
||||
__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
|
||||
__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.nor_cfg_option __nor_cfg_option_load_addr__ : {
|
||||
KEEP(*(.nor_cfg_option))
|
||||
} > XPI0
|
||||
|
||||
.boot_header __boot_header_load_addr__ : {
|
||||
__boot_header_start__ = .;
|
||||
KEEP(*(.boot_header))
|
||||
KEEP(*(.fw_info_table))
|
||||
KEEP(*(.dc_info))
|
||||
__boot_header_end__ = .;
|
||||
} > XPI0
|
||||
|
||||
.start __app_load_addr__ : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.start))
|
||||
} > XPI0
|
||||
|
||||
__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
|
||||
.vectors : AT(__vector_load_addr__) {
|
||||
. = ALIGN(8);
|
||||
__vector_ram_start__ = .;
|
||||
KEEP(*(.vector_table))
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
. = ALIGN(8);
|
||||
__vector_ram_end__ = .;
|
||||
} > ILM
|
||||
|
||||
.fast : AT(etext + __data_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
__ramfunc_start__ = .;
|
||||
*(.fast)
|
||||
|
||||
/* RT-Thread Core Start */
|
||||
KEEP(*context_gcc.o(.text* .rodata*))
|
||||
KEEP(*port*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*trap_common.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*irq.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*clock.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*kservice.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*scheduler*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*trap*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*idle.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*ipc.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*slab.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*thread.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*object.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*timer.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*mem.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*memheap.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*mempool.o (.text .text* .rodata .rodata*))
|
||||
/* RT-Thread Core End */
|
||||
|
||||
/* HPMicro Driver Wrapper */
|
||||
KEEP(*drv_*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*api_lib*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*api_msg*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*if_api*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*netbuf*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*netdb*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*netifapi*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*sockets*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*tcpip*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*ip*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*memp*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*netif*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*pbuf*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*tcp_in*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*tcp_out*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*tcp*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*ethernet*.o (.text .text* .rodata .rodata*))
|
||||
KEEP(*ethernetif*.o (.text .text* .rodata .rodata*))
|
||||
|
||||
. = ALIGN(8);
|
||||
__ramfunc_end__ = .;
|
||||
} > ILM
|
||||
|
||||
.fast_ram (NOLOAD) : {
|
||||
KEEP(*(.fast_ram))
|
||||
} > DLM
|
||||
|
||||
.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
|
||||
. = ALIGN(8);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.srodata)
|
||||
*(.srodata*)
|
||||
|
||||
*(.hash)
|
||||
*(.dyn*)
|
||||
*(.gnu*)
|
||||
*(.pl*)
|
||||
|
||||
KEEP(*(.eh_frame))
|
||||
*(.eh_frame*)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(8);
|
||||
|
||||
/*********************************************
|
||||
*
|
||||
* RT-Thread related sections - Start
|
||||
*
|
||||
*********************************************/
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
} > XPI0
|
||||
|
||||
.rel : {
|
||||
KEEP(*(.rel*))
|
||||
} > XPI0
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.bss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(.scommon)
|
||||
*(.scommon*)
|
||||
*(.dynsbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
__bss_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
/* Note: the .tbss and .tdata section should be adjacent */
|
||||
.tbss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__tbss_start__ = .;
|
||||
*(.tbss*)
|
||||
*(.tcommon*)
|
||||
_end = .;
|
||||
__tbss_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.tdata : AT(etext) {
|
||||
. = ALIGN(8);
|
||||
__tdata_start__ = .;
|
||||
__thread_pointer = .;
|
||||
*(.tdata)
|
||||
*(.tdata*)
|
||||
. = ALIGN(8);
|
||||
__tdata_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.data : AT(etext + __tdata_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
__data_start__ = .;
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.sdata)
|
||||
*(.sdata*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
KEEP(*(.dynamic))
|
||||
KEEP(*(.got*))
|
||||
KEEP(*(.got))
|
||||
KEEP(*(.gcc_except_table))
|
||||
KEEP(*(.gcc_except_table.*))
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE(__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__finit_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
|
||||
KEEP(*(.finit_array))
|
||||
PROVIDE(__finit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*crtbegin*.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
KEEP(*crtbegin*.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
. = ALIGN(8);
|
||||
__data_end__ = .;
|
||||
PROVIDE (__edata = .);
|
||||
PROVIDE (_edata = .);
|
||||
PROVIDE (edata = .);
|
||||
} > AXI_SRAM
|
||||
__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
|
||||
|
||||
.heap(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__heap_start__ = .;
|
||||
. += HEAP_SIZE;
|
||||
__heap_end__ = .;
|
||||
} > AXI_SRAM
|
||||
|
||||
.framebuffer (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.framebuffer))
|
||||
. = ALIGN(8);
|
||||
} > AXI_SRAM
|
||||
|
||||
.stack(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__stack_base__ = .;
|
||||
. += STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
PROVIDE (_stack = .);
|
||||
PROVIDE (_stack_in_dlm = .);
|
||||
PROVIDE( __rt_rvstack = . );
|
||||
} > AXI_SRAM
|
||||
|
||||
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
|
||||
. = ALIGN(8);
|
||||
__noncacheable_init_start__ = .;
|
||||
KEEP(*(.noncacheable.init))
|
||||
__noncacheable_init_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
.noncacheable.bss (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.noncacheable))
|
||||
__noncacheable_bss_start__ = .;
|
||||
KEEP(*(.noncacheable.bss))
|
||||
__noncacheable_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
.ahb_sram (NOLOAD) : {
|
||||
KEEP(*(.ahb_sram))
|
||||
} > AHB_SRAM
|
||||
|
||||
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
|
||||
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
|
||||
}
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
/*
|
||||
* Copyright 2021-2023 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
|
||||
HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
|
||||
NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ILM (wx) : ORIGIN = 0, LENGTH = 256K
|
||||
DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K
|
||||
AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K
|
||||
NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE
|
||||
AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.start : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.start))
|
||||
} > ILM
|
||||
|
||||
.vectors : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector))
|
||||
KEEP(*(.vector_table))
|
||||
. = ALIGN(8);
|
||||
} > ILM
|
||||
|
||||
.text : {
|
||||
. = ALIGN(8);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.srodata)
|
||||
*(.srodata*)
|
||||
|
||||
*(.hash)
|
||||
*(.dyn*)
|
||||
*(.gnu*)
|
||||
*(.pl*)
|
||||
*(FalPartTable)
|
||||
|
||||
KEEP(*(.eh_frame))
|
||||
*(.eh_frame*)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(8);
|
||||
|
||||
/*********************************************
|
||||
*
|
||||
* RT-Thread related sections - Start
|
||||
*
|
||||
*********************************************/
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
} > ILM
|
||||
|
||||
.rel : {
|
||||
KEEP(*(.rel*))
|
||||
} > AXI_SRAM
|
||||
|
||||
.fast_ram (NOLOAD) : {
|
||||
KEEP(*(.fast_ram))
|
||||
} > DLM
|
||||
|
||||
.bss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(.scommon)
|
||||
*(.scommon*)
|
||||
*(.dynsbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
__bss_end__ = .;
|
||||
} > DLM
|
||||
|
||||
/* Note: .tbss and .tdata should be adjacent */
|
||||
.tbss(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__tbss_start__ = .;
|
||||
*(.tbss*)
|
||||
*(.tcommon*)
|
||||
_end = .;
|
||||
__tbss_end__ = .;
|
||||
} > DLM
|
||||
|
||||
.tdata : AT(etext) {
|
||||
. = ALIGN(8);
|
||||
__tdata_start__ = .;
|
||||
__thread_pointer = .;
|
||||
*(.tdata)
|
||||
*(.tdata*)
|
||||
. = ALIGN(8);
|
||||
__tdata_end__ = .;
|
||||
} > DLM
|
||||
|
||||
.data : AT(etext + __tdata_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
__data_start__ = .;
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.sdata)
|
||||
*(.sdata*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
KEEP(*(.dynamic))
|
||||
KEEP(*(.got*))
|
||||
KEEP(*(.got))
|
||||
KEEP(*(.gcc_except_table))
|
||||
KEEP(*(.gcc_except_table.*))
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE(__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__init_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__finit_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
|
||||
KEEP(*(.finit_array))
|
||||
PROVIDE(__finit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*crtbegin*.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
KEEP(*crtbegin*.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
|
||||
. = ALIGN(8);
|
||||
__data_end__ = .;
|
||||
PROVIDE (__edata = .);
|
||||
PROVIDE (_edata = .);
|
||||
PROVIDE (edata = .);
|
||||
} > DLM
|
||||
|
||||
.fast : AT(etext + __data_end__ - __tdata_start__) {
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__ramfunc_start__ = .);
|
||||
*(.fast)
|
||||
. = ALIGN(8);
|
||||
PROVIDE(__ramfunc_end__ = .);
|
||||
} > AXI_SRAM
|
||||
|
||||
.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
|
||||
. = ALIGN(8);
|
||||
__noncacheable_init_start__ = .;
|
||||
KEEP(*(.noncacheable.init))
|
||||
__noncacheable_init_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
.noncacheable.bss (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.noncacheable))
|
||||
__noncacheable_bss_start__ = .;
|
||||
KEEP(*(.noncacheable.bss))
|
||||
__noncacheable_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
} > NONCACHEABLE_RAM
|
||||
|
||||
__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
|
||||
__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
|
||||
|
||||
.ahb_sram (NOLOAD) : {
|
||||
KEEP(*(.ahb_sram))
|
||||
} > AHB_SRAM
|
||||
|
||||
.stack(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__stack_base__ = .;
|
||||
. += STACK_SIZE;
|
||||
PROVIDE (_stack = .);
|
||||
PROVIDE (_stack_in_dlm = .);
|
||||
PROVIDE (__rt_rvstack = .);
|
||||
} > DLM
|
||||
|
||||
.framebuffer (NOLOAD) : {
|
||||
KEEP(*(.framebuffer))
|
||||
} > AXI_SRAM
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__heap_start__ = .;
|
||||
. += HEAP_SIZE;
|
||||
__heap_end__ = .;
|
||||
|
||||
} > AXI_SRAM
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,699 @@
|
|||
/*
|
||||
* Copyright (c) 2023-2024 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note:
|
||||
* PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
|
||||
* besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
|
||||
* expected SoC function can be enabled on these IOs.
|
||||
*
|
||||
*/
|
||||
#include "board.h"
|
||||
|
||||
void init_uart_pins(UART_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_UART0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
|
||||
} else if (ptr == HPM_UART1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART1_TXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07;
|
||||
HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART1_RXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06;
|
||||
} else if (ptr == HPM_UART14) {
|
||||
HPM_IOC->PAD[IOC_PAD_PF24].FUNC_CTL = IOC_PF24_FUNC_CTL_UART14_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PF25].FUNC_CTL = IOC_PF25_FUNC_CTL_UART14_RXD;
|
||||
} else if (ptr == HPM_PUART) {
|
||||
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PURT_TXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PURT_RXD;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_UART0) {
|
||||
/* pull-up */
|
||||
HPM_IOC->PAD[IOC_PAD_PA00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PA01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_GPIO_A_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_GPIO_A_01;
|
||||
}
|
||||
}
|
||||
|
||||
void init_i2c_pins(I2C_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_I2C0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_PY_02;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_SOC_PY_03;
|
||||
|
||||
} else if (ptr == HPM_I2C1) {
|
||||
/* WM8960 audio_codec */
|
||||
HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PF12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PF13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PF12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PF13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_i2c_pins_as_gpio(I2C_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_I2C0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_GPIO_Y_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_GPIO_Y_03;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03;
|
||||
} else if (ptr == HPM_I2C1) {
|
||||
#if 1
|
||||
/* WM8960 audio_codec */
|
||||
HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
#else
|
||||
/* raspberry-Pi_IF */
|
||||
HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_GPIO_Y_06;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_GPIO_Y_07;
|
||||
#endif
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_femc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_A_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_A_01;
|
||||
HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_A_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_A_03;
|
||||
HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_A_04;
|
||||
HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_A_05;
|
||||
HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_FEMC_A_06;
|
||||
HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_07;
|
||||
HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_A_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_A_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_A_10;
|
||||
HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_A_11; /* SRAM: NWE */
|
||||
HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_A_12; /* SRAM: NOE */
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_FEMC_DQ_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_FEMC_DQ_01;
|
||||
HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_FEMC_DQ_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_FEMC_DQ_03;
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_FEMC_DQ_04;
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_FEMC_DQ_05;
|
||||
HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_FEMC_DQ_06;
|
||||
HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_FEMC_DQ_07;
|
||||
HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_FEMC_DQ_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_FEMC_DQ_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_FEMC_DQ_10;
|
||||
HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_FEMC_DQ_11;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_FEMC_DQ_12;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_FEMC_DQ_13;
|
||||
HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_FEMC_DQ_14;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_FEMC_DQ_15;
|
||||
HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQ_16;
|
||||
HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_DQ_17;
|
||||
HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_DQ_18;
|
||||
HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_DQ_19;
|
||||
HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_DQ_20;
|
||||
HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_DQ_21;
|
||||
HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_FEMC_DQ_22;
|
||||
HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_DQ_23;
|
||||
HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_FEMC_DQ_24;
|
||||
HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_FEMC_DQ_25;
|
||||
HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_FEMC_DQ_26;
|
||||
HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_DQ_27;
|
||||
HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_DQ_28;
|
||||
HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_DQ_29;
|
||||
HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_DQ_30;
|
||||
HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_DQ_31;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_FEMC_DM_0; /* SRAM: NLB */
|
||||
HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_FEMC_DM_1; /* SRAM: NUB */
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_DM_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_DM_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PX07].FUNC_CTL = IOC_PX07_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
|
||||
/* SDRAM */
|
||||
HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_BA0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_BA1; /* SRAM: NADV */
|
||||
HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_RAS;
|
||||
HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_CAS;
|
||||
HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_CKE;
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_CLK_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_WE;
|
||||
HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_FEMC_CS_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_CS_1;
|
||||
|
||||
/* SRAM */
|
||||
HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_SCLK_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_SCLK_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_SCS_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_SCS_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_FEMC_SRDY;
|
||||
}
|
||||
|
||||
void init_ppi_pins(void)
|
||||
{
|
||||
/* DQ Group A */
|
||||
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PPI0_DQ_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PPI0_DQ_01;
|
||||
HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PPI0_DQ_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PPI0_DQ_03;
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_PPI0_DQ_04;
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_PPI0_DQ_05;
|
||||
HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_PPI0_DQ_06;
|
||||
HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_PPI0_DQ_07;
|
||||
HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_PPI0_DQ_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_PPI0_DQ_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_PPI0_DQ_10;
|
||||
HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_PPI0_DQ_11;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_PPI0_DQ_12;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_PPI0_DQ_13;
|
||||
HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_PPI0_DQ_14;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_PPI0_DQ_15;
|
||||
HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_PPI0_DQ_16;
|
||||
HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_PPI0_DQ_17;
|
||||
HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PPI0_DQ_18;
|
||||
HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PPI0_DQ_19;
|
||||
HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PPI0_DQ_20;
|
||||
HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PPI0_DQ_21;
|
||||
HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PPI0_DQ_22;
|
||||
HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_PPI0_DQ_23;
|
||||
HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PPI0_DQ_24;
|
||||
HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PPI0_DQ_25;
|
||||
HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PPI0_DQ_26;
|
||||
HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PPI0_DQ_27;
|
||||
HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PPI0_DQ_28;
|
||||
HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_PPI0_DQ_29;
|
||||
HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_PPI0_DQ_30;
|
||||
HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_PPI0_DQ_31;
|
||||
|
||||
/* DM Group A */
|
||||
HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_PPI0_DM_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_PPI0_DM_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_PPI0_DM_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_PPI0_DM_3;
|
||||
|
||||
/* CS */
|
||||
HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_PPI0_CS_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_PPI0_CS_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_PPI0_CS_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_PPI0_CS_3;
|
||||
|
||||
/* CTRL */
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_PPI0_CTR_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_PPI0_CTR_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_PPI0_CTR_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_PPI0_CTR_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PPI0_CTR_4;
|
||||
HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PPI0_CTR_5;
|
||||
HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_PPI0_CTR_6;
|
||||
HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PPI0_CTR_7;
|
||||
|
||||
/* CLK */
|
||||
HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_PPI0_CLK;
|
||||
|
||||
/* DQ Group B */
|
||||
/*
|
||||
* HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PPI0_DQ_00;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PPI0_DQ_01;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PPI0_DQ_02;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PPI0_DQ_03;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_PPI0_DQ_04;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_PPI0_DQ_05;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_PPI0_DQ_06;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_PPI0_DQ_07;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_PPI0_DQ_08;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_PPI0_DQ_09;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PPI0_DQ_10;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_PPI0_DQ_11;
|
||||
* HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_PPI0_DQ_12;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PPI0_DQ_13;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_PPI0_DQ_14;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_PPI0_DQ_15;
|
||||
*/
|
||||
|
||||
/* DM Group B */
|
||||
/*
|
||||
* HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_PPI0_DM_0;
|
||||
* HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_PPI0_DM_1;
|
||||
*/
|
||||
}
|
||||
|
||||
void init_sdm_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF17].FUNC_CTL = IOC_PF17_FUNC_CTL_SDM0_CLK_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PF16].FUNC_CTL = IOC_PF16_FUNC_CTL_SDM0_DAT_0;
|
||||
}
|
||||
|
||||
void init_pwm_pin_as_sdm_clock(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_PWM2_P_3;
|
||||
}
|
||||
|
||||
void init_gpio_pins(void)
|
||||
{
|
||||
/* configure pad setting: pull enable and pull up, schmitt trigger enable */
|
||||
/* enable schmitt trigger to eliminate jitter of pin used as button */
|
||||
|
||||
/* Button */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_GPIO_B_25;
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24;
|
||||
HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = pad_ctl;
|
||||
}
|
||||
|
||||
void init_spi_pins(SPI_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_SPI7) {
|
||||
HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_SPI7_CS_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_SPI7) {
|
||||
HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_GPIO_F_27;
|
||||
HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI;
|
||||
}
|
||||
}
|
||||
|
||||
void init_gptmr_pins(GPTMR_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_GPTMR4) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR4_COMP_0;
|
||||
}
|
||||
if (ptr == HPM_GPTMR0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_GPTMR0_COMP_0;
|
||||
}
|
||||
if (ptr == HPM_GPTMR5) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_GPTMR5_COMP_2;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void init_hall_trgm_pins(void)
|
||||
{
|
||||
init_qeiv2_uvw_pins(BOARD_BLDC_QEIV2_BASE);
|
||||
}
|
||||
|
||||
void init_qei_trgm_pins(void)
|
||||
{
|
||||
init_qeiv2_ab_pins(BOARD_BLDC_QEIV2_BASE);
|
||||
}
|
||||
|
||||
void init_butn_pins(void)
|
||||
{
|
||||
/* configure pad setting: pull enable and pull up, schmitt trigger enable */
|
||||
/* enable schmitt trigger to eliminate jitter of pin used as button */
|
||||
|
||||
/* Button */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24;
|
||||
HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_GPIO_B_25;
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = pad_ctl;
|
||||
}
|
||||
|
||||
void init_acmp_pins(void)
|
||||
{
|
||||
/* configure to CMP0_INN4 function */
|
||||
HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_pwm_fault_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05;
|
||||
}
|
||||
|
||||
void init_pwm_pins(PWMV2_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_PWM1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PE08].FUNC_CTL = IOC_PE08_FUNC_CTL_PWM1_P_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PE09].FUNC_CTL = IOC_PE09_FUNC_CTL_PWM1_P_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PE10].FUNC_CTL = IOC_PE10_FUNC_CTL_PWM1_P_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PE11].FUNC_CTL = IOC_PE11_FUNC_CTL_PWM1_P_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_PWM1_P_4;
|
||||
HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_PWM1_P_5;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_usb_pins(void)
|
||||
{
|
||||
/* USB0_ID */
|
||||
HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID;
|
||||
/* USB0_OC */
|
||||
HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC;
|
||||
/* USB0_PWR */
|
||||
HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR;
|
||||
}
|
||||
|
||||
void init_clk_obs_pins(void)
|
||||
{
|
||||
/* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */
|
||||
}
|
||||
|
||||
void init_i2s_pins(I2S_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_I2S0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2S0_MCLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_I2S0_BCLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2S0_FCLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_I2S0_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2S0_RXD_0;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_qeo_pins(QEOV2_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_QEO0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_QEO0_A; /* Motor CON3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_QEO0_B;
|
||||
HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_QEO0_Z;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx)
|
||||
{
|
||||
if (ptr == HPM_SEI) {
|
||||
if (sei_ctrl_idx == SEI_CTRL_1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_SEI1_DE;
|
||||
HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_SEI1_CK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_SEI1_TX;
|
||||
HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_SEI1_RX;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void init_qeiv2_uvw_pins(QEIV2_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_QEI0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A;
|
||||
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B;
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_QEI0_Z;
|
||||
}
|
||||
}
|
||||
|
||||
void init_qeiv2_ab_pins(QEIV2_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_QEI0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A;
|
||||
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B;
|
||||
}
|
||||
}
|
||||
|
||||
void init_qeiv2_abz_pins(QEIV2_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_QEI0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A;
|
||||
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B;
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_QEI0_Z;
|
||||
}
|
||||
}
|
||||
|
||||
void init_rdc_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 PWN_P */
|
||||
HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.10 / ADC1.10 PWN_N */
|
||||
HPM_IOC->PAD[IOC_PAD_PE08].FUNC_CTL = IOC_PE08_FUNC_CTL_RDC0_PWM_N;
|
||||
/*The GPIO is designed for debug */
|
||||
#ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT
|
||||
HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_TRGM_P_00;
|
||||
#endif
|
||||
}
|
||||
|
||||
void init_dao_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_DAO_RP;
|
||||
HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_DAO_RN;
|
||||
}
|
||||
|
||||
void init_pdm_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PDM0_CLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_PDM0_D_0;
|
||||
}
|
||||
|
||||
void init_enet_pins(ENET_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_ENET0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_ETH0_MDIO;
|
||||
HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_ETH0_MDC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH0_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_ETH0_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_ETH0_RXD_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ETH0_RXCK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_ETH0_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_ETH0_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_ETH0_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PE29_FUNC_CTL_ETH0_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_ETH0_TXD_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_ETH0_TXEN;
|
||||
}
|
||||
}
|
||||
|
||||
void init_enet_pps_pins(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void init_adc16_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */
|
||||
}
|
||||
|
||||
void init_adc_bldc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.10 / ADC1.10 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC2.11 / ADC3.11 */
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.1 / ADC1.1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.15 / ADC1.15 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC2.00 / ADC3.00 */
|
||||
HPM_IOC->PAD[IOC_PAD_PF20].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC2.03 / ADC3.03 */
|
||||
|
||||
}
|
||||
|
||||
void init_adc_qeiv2_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC2.11 / ADC3.11 cos_ch */
|
||||
HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 sin_ch */
|
||||
}
|
||||
|
||||
void init_can_pins(MCAN_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_MCAN4) {
|
||||
HPM_IOC->PAD[IOC_PAD_PZ00].FUNC_CTL = IOC_PZ00_FUNC_CTL_MCAN4_TXD;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ00].FUNC_CTL = BIOC_PZ00_FUNC_CTL_SOC_PZ_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ01].FUNC_CTL = IOC_PZ01_FUNC_CTL_MCAN4_RXD;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ01].FUNC_CTL = BIOC_PZ01_FUNC_CTL_SOC_PZ_01;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_MCAN4_STBY;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02;
|
||||
} else {
|
||||
/* Invalid CAN instance */
|
||||
}
|
||||
}
|
||||
|
||||
void init_led_pins_as_gpio(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04;
|
||||
HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14;
|
||||
HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15;
|
||||
}
|
||||
|
||||
void init_led_pins_as_pwm(void)
|
||||
{
|
||||
/* Red */
|
||||
HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_PWM1_P_6;
|
||||
/* Green */
|
||||
HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_PWM1_P_7;
|
||||
/* BLUE */
|
||||
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM0_P_4;
|
||||
}
|
||||
|
||||
void init_plb_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05;
|
||||
}
|
||||
|
||||
void init_esc_pins(void)
|
||||
{
|
||||
/* ESC */
|
||||
HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_ESC0_MDIO;
|
||||
HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_ESC0_MDC;
|
||||
HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_ESC0_SDA;
|
||||
HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_ESC0_SCL;
|
||||
|
||||
/* ESC needs to configure these pins for specific functions, see ESC IOCFG registers */
|
||||
HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; /* GPIO to reset PHY */
|
||||
HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_ESC0_CTR_3; /* NMII_LINK0(PORTA_LINK) function */
|
||||
HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_ESC0_CTR_0; /* NMII_LINK1(PORTB_LINK) function */
|
||||
HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ESC0_CTR_6; /* LED_ERROR function */
|
||||
HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ESC0_CTR_1; /* LED_RUN function */
|
||||
|
||||
/* ESC PORTA */
|
||||
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_ESC0_P0_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_ESC0_P0_TXEN;
|
||||
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ESC0_P0_RXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ESC0_P0_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ESC0_P0_RXER;
|
||||
HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3;
|
||||
|
||||
/* ESC PORTB */
|
||||
HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_ESC0_P1_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_ESC0_P1_TXEN;
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_ESC0_P1_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_ESC0_P1_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_ESC0_P1_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_ESC0_P1_TXD_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_ESC0_P1_RXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_ESC0_P1_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_ESC0_P1_RXER;
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_ESC0_P1_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_ESC0_P1_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_ESC0_P1_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_ESC0_P1_RXD_3;
|
||||
}
|
||||
|
||||
void init_tsw_pins(void)
|
||||
{
|
||||
/* PORT1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_TSW0_P1_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_TSW0_P1_RXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_TSW0_P1_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_TSW0_P1_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_TSW0_P1_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TSW0_P1_RXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_TSW0_P1_TXEN;
|
||||
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_TSW0_P1_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_TSW0_P1_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TSW0_P1_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_TSW0_P1_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_TSW0_P1_TXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TSW0_P1_RXER;
|
||||
HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_TSW0_P1_MDC;
|
||||
HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_TSW0_P1_MDIO;
|
||||
|
||||
/* PORT2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TSW0_P2_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_TSW0_P2_RXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TSW0_P2_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_TSW0_P2_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_TSW0_P2_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_TSW0_P2_RXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TSW0_P2_TXEN;
|
||||
HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_TSW0_P2_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_TSW0_P2_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_TSW0_P2_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TSW0_P2_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TSW0_P2_TXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_TSW0_P2_RXER;
|
||||
HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_TSW0_P2_MDC;
|
||||
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_TSW0_P2_MDIO;
|
||||
|
||||
/* PORT1/PORT2 PHY RST */
|
||||
HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10;
|
||||
|
||||
/* XI */
|
||||
HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK;
|
||||
|
||||
/* PORT3 PE */
|
||||
HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_TSW0_P3_RXDV;
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_TSW0_P3_RXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_TSW0_P3_RXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_TSW0_P3_RXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_TSW0_P3_RXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_TSW0_P3_RXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_TSW0_P3_TXEN;
|
||||
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_TSW0_P3_TXCK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_TSW0_P3_TXD_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_TSW0_P3_TXD_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PE29_FUNC_CTL_TSW0_P3_TXD_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_TSW0_P3_TXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_TSW0_P3_MDC;
|
||||
HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_TSW0_P3_MDIO;
|
||||
|
||||
/* PORT3 PHY INT */
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09;
|
||||
|
||||
/* PORT3 PHY RST */
|
||||
HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14;
|
||||
}
|
||||
|
||||
void init_tamper_pins(void)
|
||||
{
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_TAMP_PZ_03;
|
||||
}
|
||||
|
||||
void init_esc_in_out_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_GPIO_C_31;
|
||||
HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_GPIO_D_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_GPIO_D_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14;
|
||||
}
|
||||
|
||||
/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
|
||||
void init_uart_break_signal_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF27].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_GPIO_F_27;
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2023 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HPM_PINMUX_H
|
||||
#define HPM_PINMUX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void init_uart_pins(UART_Type *ptr);
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr);
|
||||
void init_i2c_pins_as_gpio(I2C_Type *ptr);
|
||||
void init_i2c_pins(I2C_Type *ptr);
|
||||
void init_femc_pins(void);
|
||||
void init_ppi_pins(void);
|
||||
void init_sdm_pins(void);
|
||||
void init_pwm_pin_as_sdm_clock(void);
|
||||
void init_gpio_pins(void);
|
||||
void init_spi_pins(SPI_Type *ptr);
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
|
||||
void init_gptmr_pins(GPTMR_Type *ptr);
|
||||
void init_hall_trgm_pins(void);
|
||||
void init_qei_trgm_pins(void);
|
||||
void init_butn_pins(void);
|
||||
void init_acmp_pins(void);
|
||||
void init_pwm_pins(PWMV2_Type *ptr);
|
||||
void init_usb_pins(void);
|
||||
void init_i2s_pins(I2S_Type *ptr);
|
||||
void init_qeo_pins(QEOV2_Type *ptr);
|
||||
void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
|
||||
void init_qeiv2_uvw_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_ab_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_abz_pins(QEIV2_Type *ptr);
|
||||
void init_rdc_pin(void);
|
||||
void init_dao_pins(void);
|
||||
void init_pdm_pins(void);
|
||||
void init_enet_pins(ENET_Type *ptr);
|
||||
void init_enet_pps_pins(void);
|
||||
void init_adc16_pins(void);
|
||||
void init_adc_bldc_pins(void);
|
||||
void init_adc_qeiv2_pins(void);
|
||||
void init_can_pins(MCAN_Type *ptr);
|
||||
void init_led_pins_as_gpio(void);
|
||||
void init_led_pins_as_pwm(void);
|
||||
void init_plb_pins(void);
|
||||
void init_esc_pins(void);
|
||||
void init_esc_in_out_pin(void);
|
||||
void init_tsw_pins(void);
|
||||
void init_tamper_pins(void);
|
||||
void init_pwm_fault_pins(void);
|
||||
void init_uart_break_signal_pin(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPM_PINMUX_H */
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright (c) 2023-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "rtt_board.h"
|
||||
#include "hpm_uart_drv.h"
|
||||
#include "hpm_gpio_drv.h"
|
||||
#include "hpm_pmp_drv.h"
|
||||
#include "assert.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_sysctl_drv.h"
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "hpm_dma_mgr.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
void os_tick_config(void);
|
||||
void rtt_board_init(void);
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rtt_board_init(void)
|
||||
{
|
||||
board_init_clock();
|
||||
board_init_console();
|
||||
board_init_pmp();
|
||||
|
||||
dma_mgr_init();
|
||||
|
||||
/* initialize memory system */
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
|
||||
/* Configure the OS Tick */
|
||||
os_tick_config();
|
||||
|
||||
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
|
||||
rt_hw_uart_init();
|
||||
|
||||
/* Set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
|
||||
void app_init_led_pins(void)
|
||||
{
|
||||
gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
|
||||
gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN);
|
||||
gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN);
|
||||
|
||||
gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF);
|
||||
gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF);
|
||||
gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF);
|
||||
}
|
||||
|
||||
void app_led_write(uint32_t index, bool state)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0:
|
||||
gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state);
|
||||
break;
|
||||
case 1:
|
||||
gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state);
|
||||
break;
|
||||
case 2:
|
||||
gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state);
|
||||
break;
|
||||
default:
|
||||
/* Suppress the toolchain warnings */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str != '\0')
|
||||
{
|
||||
uart_send_byte(BOARD_APP_UART_BASE, *str++);
|
||||
}
|
||||
}
|
||||
|
||||
void app_init_usb_pins(void)
|
||||
{
|
||||
board_init_usb_pins();
|
||||
}
|
||||
|
||||
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
|
||||
{
|
||||
HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
|
||||
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void rt_hw_cpu_reset(void)
|
||||
{
|
||||
HPM_PPOR->RESET_ENABLE = (1UL << 31);
|
||||
HPM_PPOR->SOFTWARE_RESET = 1000U;
|
||||
while(1) {
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
|
||||
|
||||
#ifdef RT_USING_CACHE
|
||||
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
|
||||
{
|
||||
if (ops == RT_HW_CACHE_FLUSH) {
|
||||
l1c_dc_flush((uint32_t)addr, size);
|
||||
} else {
|
||||
l1c_dc_invalidate((uint32_t)addr, size);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTT_BOARD_H
|
||||
#define _RTT_BOARD_H
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
|
||||
/* gpio section */
|
||||
#define APP_LED0_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED0_GPIO_PIN 14
|
||||
#define APP_LED1_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED1_GPIO_PIN 15
|
||||
#define APP_LED2_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED2_GPIO_PIN 4
|
||||
#define APP_LED_ON (0)
|
||||
#define APP_LED_OFF (1)
|
||||
|
||||
|
||||
|
||||
/* mchtimer section */
|
||||
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_CAN_NAME "can4"
|
||||
#define BOARD_CAN_HWFILTER_INDEX (4U)
|
||||
|
||||
/* UART section */
|
||||
#define BOARD_UART_NAME "uart1"
|
||||
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART1_RX_BUFSIZE
|
||||
|
||||
|
||||
/* audio section */
|
||||
#define BOARD_AUDIO_CODEC_I2C_NAME "i2c0"
|
||||
#define BOARD_AUDIO_CODEC_I2S_NAME "i2s0"
|
||||
|
||||
/* PWM section */
|
||||
#define BOARD_PWM_NAME "pwm1"
|
||||
#define BOARD_PWM_CHANNEL (0U)
|
||||
|
||||
#define IRQn_PendSV IRQn_DEBUG0
|
||||
|
||||
/***************************************************************
|
||||
*
|
||||
* RT-Thread related definitions
|
||||
*
|
||||
**************************************************************/
|
||||
extern unsigned int __heap_start__;
|
||||
extern unsigned int __heap_end__;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
|
||||
#define RT_HW_HEAP_END ((void*)&__heap_end__)
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t vdd;
|
||||
uint8_t bus_width;
|
||||
uint8_t drive_strength;
|
||||
}sdxc_io_cfg_t;
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
void app_init_led_pins(void);
|
||||
void app_led_write(uint32_t index, bool state);
|
||||
void app_init_usb_pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _RTT_BOARD_H */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 320 KiB |
|
|
@ -0,0 +1,337 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 1024
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 1024
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
/* end of kservice optimization */
|
||||
|
||||
/* klibc optimization */
|
||||
|
||||
/* end of klibc optimization */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50200
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define RT_USING_DFS_DEVFS
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HPM6E00
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART0
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
# Copyright 2021-2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='risc-v'
|
||||
CPU='hpmicro'
|
||||
SOC_FAMILY='HPM6E00'
|
||||
CHIP_NAME='HPM6E80'
|
||||
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
# Fallback toolchain info
|
||||
FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
|
||||
FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
|
||||
FALLBACK_TOOLCHAIN_VER='2022-04-12'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
if RTT_EXEC_PATH != None:
|
||||
folders = RTT_EXEC_PATH.split(os.sep)
|
||||
# If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
|
||||
if 'arm_gcc' in folders and 'platform' in folders:
|
||||
RTT_EXEC_PATH = ''
|
||||
for path in folders:
|
||||
if path != 'platform':
|
||||
RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
|
||||
else:
|
||||
break
|
||||
RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
|
||||
# Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
|
||||
if 'platform' in folders:
|
||||
os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_RISCV_TOOLCHAIN'):
|
||||
EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
|
||||
else:
|
||||
EXEC_PATH = r'/opt/riscv-gnu-gcc/bin'
|
||||
else:
|
||||
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
|
||||
|
||||
BUILD = 'flash_debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'riscv32-unknown-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
GDB = PREFIX + 'gdb'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
ARCH_ABI = ' -mcmodel=medlow '
|
||||
DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = CFLAGS
|
||||
LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'ram_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'ram_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'flash_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
elif BUILD == 'flash_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
LFLAGS += ' -T ' + LINKER_FILE
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
CFLAGS = CFLAGS + ' -std=gnu11'
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the startup files
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += [os.path.join('toolchains', 'gcc', 'start.S')]
|
||||
src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D45', rtconfig.CHIP_NAME]
|
||||
|
||||
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include "hpm_l1c_drv.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
void system_init(void);
|
||||
|
||||
extern int entry(void);
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern void __libc_fini_array(void);
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
disable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
disable_irq_from_intc();
|
||||
enable_irq_from_intc();
|
||||
enable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
#ifndef CONFIG_NOT_ENABLE_ICACHE
|
||||
l1c_ic_enable();
|
||||
#endif
|
||||
#ifndef CONFIG_NOT_ENABLE_DCACHE
|
||||
l1c_dc_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) void c_startup(void)
|
||||
{
|
||||
uint32_t i, size;
|
||||
#ifdef FLASH_XIP
|
||||
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
|
||||
size = __vector_ram_end__ - __vector_ram_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern uint8_t __etext[];
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __tbss_start__[], __tbss_end__[];
|
||||
extern uint8_t __tdata_start__[], __tdata_end__[];
|
||||
extern uint8_t __data_start__[], __data_end__[];
|
||||
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
|
||||
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
|
||||
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
|
||||
|
||||
/* tbss section */
|
||||
size = __tbss_end__ - __tbss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tbss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* bss section */
|
||||
size = __bss_end__ - __bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* noncacheable bss section */
|
||||
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* tdata section LMA: etext */
|
||||
size = __tdata_end__ - __tdata_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tdata_start__ + i) = *(__etext + i);
|
||||
}
|
||||
|
||||
/* data section LMA: etext */
|
||||
size = __data_end__ - __data_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* ramfunc section LMA: etext + data length */
|
||||
size = __ramfunc_end__ - __ramfunc_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* noncacheable init section LMA: etext + data length + ramfunc length */
|
||||
size = __noncacheable_init_end__ - __noncacheable_init_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((weak)) int main(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
/**
|
||||
* Disable preemptive interrupt
|
||||
*/
|
||||
HPM_PLIC->FEATURE = 0;
|
||||
/*
|
||||
* Initialize LMA/VMA sections.
|
||||
* Relocation for any sections that need to be copied from LMA to VMA.
|
||||
*/
|
||||
c_startup();
|
||||
|
||||
/* Call platform specific hardware initialization */
|
||||
system_init();
|
||||
|
||||
/* Do global constructors */
|
||||
__libc_init_array();
|
||||
|
||||
|
||||
|
||||
/* Entry function */
|
||||
entry();
|
||||
}
|
||||
|
||||
|
||||
__attribute__((weak)) void _init()
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include "cpuport.h"
|
||||
|
||||
.globl rt_hw_do_after_save_above
|
||||
.type rt_hw_do_after_save_above,@function
|
||||
rt_hw_do_after_save_above:
|
||||
addi sp, sp, -4
|
||||
STORE ra, 0 * REGBYTES(sp)
|
||||
|
||||
csrr t1, mcause
|
||||
andi t1, t1, 0x3FF
|
||||
/* get ISR */
|
||||
la t2, trap_entry
|
||||
jalr t2
|
||||
|
||||
LOAD ra, 0 * REGBYTES(sp)
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include <rtconfig.h>
|
||||
#include "hpm_csr_regs.h"
|
||||
.section .start, "ax"
|
||||
|
||||
.global _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
/* Initialize global pointer */
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
la tp, __thread_pointer
|
||||
.option pop
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
|
||||
#ifdef INIT_EXT_RAM_FOR_DATA
|
||||
la t0, _stack_in_dlm
|
||||
mv sp, t0
|
||||
call _init_ext_ram
|
||||
#endif
|
||||
|
||||
/* Initialize stack pointer */
|
||||
la t0, _stack
|
||||
mv sp, t0
|
||||
|
||||
#ifdef __nds_execit
|
||||
/* Initialize EXEC.IT table */
|
||||
la t0, _ITB_BASE_
|
||||
csrw uitb, t0
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
|
||||
#ifdef HPM_USING_VECTOR_PREEMPTED_MODE
|
||||
/* Initial machine trap-vector Base */
|
||||
la t0, __vector_table
|
||||
csrw mtvec, t0
|
||||
/* Enable vectored external PLIC interrupt */
|
||||
csrsi CSR_MMISC_CTL, 2
|
||||
#else
|
||||
/* Initial machine trap-vector Base */
|
||||
la t0, SW_handler
|
||||
csrw mtvec, t0
|
||||
/* Disable vectored external PLIC interrupt */
|
||||
csrci CSR_MMISC_CTL, 2
|
||||
#endif
|
||||
|
||||
/* System reset handler */
|
||||
call reset_handler
|
||||
|
||||
/* Infinite loop, if returned accidently */
|
||||
1: j 1b
|
||||
|
||||
.weak nmi_handler
|
||||
nmi_handler:
|
||||
1: j 1b
|
||||
|
||||
.global default_irq_handler
|
||||
.weak default_irq_handler
|
||||
.align 2
|
||||
default_irq_handler:
|
||||
1: j 1b
|
||||
|
||||
.macro IRQ_HANDLER irq
|
||||
.weak default_isr_\irq
|
||||
.set default_isr_\irq, default_irq_handler
|
||||
.long default_isr_\irq
|
||||
.endm
|
||||
|
||||
#include "vectors.S"
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
.section .vector_table, "a"
|
||||
.global __vector_table
|
||||
.align 9
|
||||
__vector_table:
|
||||
.weak default_isr_trap
|
||||
.set default_isr_trap, SW_handler
|
||||
.long default_isr_trap
|
||||
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
|
||||
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
|
||||
IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
|
||||
IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
|
||||
IRQ_HANDLER 5 /* GPIO0_E IRQ handler */
|
||||
IRQ_HANDLER 6 /* GPIO0_F IRQ handler */
|
||||
IRQ_HANDLER 7 /* GPIO0_V IRQ handler */
|
||||
IRQ_HANDLER 8 /* GPIO0_W IRQ handler */
|
||||
IRQ_HANDLER 9 /* GPIO0_X IRQ handler */
|
||||
IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */
|
||||
IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */
|
||||
IRQ_HANDLER 12 /* GPIO1_A IRQ handler */
|
||||
IRQ_HANDLER 13 /* GPIO1_B IRQ handler */
|
||||
IRQ_HANDLER 14 /* GPIO1_C IRQ handler */
|
||||
IRQ_HANDLER 15 /* GPIO1_D IRQ handler */
|
||||
IRQ_HANDLER 16 /* GPIO1_E IRQ handler */
|
||||
IRQ_HANDLER 17 /* GPIO1_F IRQ handler */
|
||||
IRQ_HANDLER 18 /* GPIO1_V IRQ handler */
|
||||
IRQ_HANDLER 19 /* GPIO1_W IRQ handler */
|
||||
IRQ_HANDLER 20 /* GPIO1_X IRQ handler */
|
||||
IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */
|
||||
IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */
|
||||
IRQ_HANDLER 23 /* GPTMR0 IRQ handler */
|
||||
IRQ_HANDLER 24 /* GPTMR1 IRQ handler */
|
||||
IRQ_HANDLER 25 /* GPTMR2 IRQ handler */
|
||||
IRQ_HANDLER 26 /* GPTMR3 IRQ handler */
|
||||
IRQ_HANDLER 27 /* GPTMR4 IRQ handler */
|
||||
IRQ_HANDLER 28 /* GPTMR5 IRQ handler */
|
||||
IRQ_HANDLER 29 /* GPTMR6 IRQ handler */
|
||||
IRQ_HANDLER 30 /* GPTMR7 IRQ handler */
|
||||
IRQ_HANDLER 31 /* UART0 IRQ handler */
|
||||
IRQ_HANDLER 32 /* UART1 IRQ handler */
|
||||
IRQ_HANDLER 33 /* UART2 IRQ handler */
|
||||
IRQ_HANDLER 34 /* UART3 IRQ handler */
|
||||
IRQ_HANDLER 35 /* UART4 IRQ handler */
|
||||
IRQ_HANDLER 36 /* UART5 IRQ handler */
|
||||
IRQ_HANDLER 37 /* UART6 IRQ handler */
|
||||
IRQ_HANDLER 38 /* UART7 IRQ handler */
|
||||
IRQ_HANDLER 39 /* I2C0 IRQ handler */
|
||||
IRQ_HANDLER 40 /* I2C1 IRQ handler */
|
||||
IRQ_HANDLER 41 /* I2C2 IRQ handler */
|
||||
IRQ_HANDLER 42 /* I2C3 IRQ handler */
|
||||
IRQ_HANDLER 43 /* SPI0 IRQ handler */
|
||||
IRQ_HANDLER 44 /* SPI1 IRQ handler */
|
||||
IRQ_HANDLER 45 /* SPI2 IRQ handler */
|
||||
IRQ_HANDLER 46 /* SPI3 IRQ handler */
|
||||
IRQ_HANDLER 47 /* TSNS IRQ handler */
|
||||
IRQ_HANDLER 48 /* MBX0A IRQ handler */
|
||||
IRQ_HANDLER 49 /* MBX0B IRQ handler */
|
||||
IRQ_HANDLER 50 /* MBX1A IRQ handler */
|
||||
IRQ_HANDLER 51 /* MBX1B IRQ handler */
|
||||
IRQ_HANDLER 52 /* EWDG0 IRQ handler */
|
||||
IRQ_HANDLER 53 /* EWDG1 IRQ handler */
|
||||
IRQ_HANDLER 54 /* EWDG2 IRQ handler */
|
||||
IRQ_HANDLER 55 /* EWDG3 IRQ handler */
|
||||
IRQ_HANDLER 56 /* HDMA IRQ handler */
|
||||
IRQ_HANDLER 57 /* LOBS IRQ handler */
|
||||
IRQ_HANDLER 58 /* ADC0 IRQ handler */
|
||||
IRQ_HANDLER 59 /* ADC1 IRQ handler */
|
||||
IRQ_HANDLER 60 /* ADC2 IRQ handler */
|
||||
IRQ_HANDLER 61 /* ADC3 IRQ handler */
|
||||
IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */
|
||||
IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */
|
||||
IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */
|
||||
IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */
|
||||
IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */
|
||||
IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */
|
||||
IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */
|
||||
IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */
|
||||
IRQ_HANDLER 70 /* I2S0 IRQ handler */
|
||||
IRQ_HANDLER 71 /* I2S1 IRQ handler */
|
||||
IRQ_HANDLER 72 /* DAO IRQ handler */
|
||||
IRQ_HANDLER 73 /* PDM IRQ handler */
|
||||
IRQ_HANDLER 74 /* UART8 IRQ handler */
|
||||
IRQ_HANDLER 75 /* UART9 IRQ handler */
|
||||
IRQ_HANDLER 76 /* UART10 IRQ handler */
|
||||
IRQ_HANDLER 77 /* UART11 IRQ handler */
|
||||
IRQ_HANDLER 78 /* UART12 IRQ handler */
|
||||
IRQ_HANDLER 79 /* UART13 IRQ handler */
|
||||
IRQ_HANDLER 80 /* UART14 IRQ handler */
|
||||
IRQ_HANDLER 81 /* UART15 IRQ handler */
|
||||
IRQ_HANDLER 82 /* I2C4 IRQ handler */
|
||||
IRQ_HANDLER 83 /* I2C5 IRQ handler */
|
||||
IRQ_HANDLER 84 /* I2C6 IRQ handler */
|
||||
IRQ_HANDLER 85 /* I2C7 IRQ handler */
|
||||
IRQ_HANDLER 86 /* SPI4 IRQ handler */
|
||||
IRQ_HANDLER 87 /* SPI5 IRQ handler */
|
||||
IRQ_HANDLER 88 /* SPI6 IRQ handler */
|
||||
IRQ_HANDLER 89 /* SPI7 IRQ handler */
|
||||
IRQ_HANDLER 90 /* MCAN0 IRQ handler */
|
||||
IRQ_HANDLER 91 /* MCAN1 IRQ handler */
|
||||
IRQ_HANDLER 92 /* MCAN2 IRQ handler */
|
||||
IRQ_HANDLER 93 /* MCAN3 IRQ handler */
|
||||
IRQ_HANDLER 94 /* MCAN4 IRQ handler */
|
||||
IRQ_HANDLER 95 /* MCAN5 IRQ handler */
|
||||
IRQ_HANDLER 96 /* MCAN6 IRQ handler */
|
||||
IRQ_HANDLER 97 /* MCAN7 IRQ handler */
|
||||
IRQ_HANDLER 98 /* PTPC IRQ handler */
|
||||
IRQ_HANDLER 99 /* QEI0 IRQ handler */
|
||||
IRQ_HANDLER 100 /* QEI1 IRQ handler */
|
||||
IRQ_HANDLER 101 /* QEI2 IRQ handler */
|
||||
IRQ_HANDLER 102 /* QEI3 IRQ handler */
|
||||
IRQ_HANDLER 103 /* PWM0 IRQ handler */
|
||||
IRQ_HANDLER 104 /* PWM1 IRQ handler */
|
||||
IRQ_HANDLER 105 /* PWM2 IRQ handler */
|
||||
IRQ_HANDLER 106 /* PWM3 IRQ handler */
|
||||
IRQ_HANDLER 107 /* RDC0 IRQ handler */
|
||||
IRQ_HANDLER 108 /* RDC1 IRQ handler */
|
||||
IRQ_HANDLER 109 /* SDM0 IRQ handler */
|
||||
IRQ_HANDLER 110 /* SDM1 IRQ handler */
|
||||
IRQ_HANDLER 111 /* SEI[0] IRQ handler */
|
||||
IRQ_HANDLER 112 /* SEI[1] IRQ handler */
|
||||
IRQ_HANDLER 113 /* SEI[2] IRQ handler */
|
||||
IRQ_HANDLER 114 /* SEI[3] IRQ handler */
|
||||
IRQ_HANDLER 115 /* MTG0 IRQ handler */
|
||||
IRQ_HANDLER 116 /* MTG1 IRQ handler */
|
||||
IRQ_HANDLER 117 /* VSC0 IRQ handler */
|
||||
IRQ_HANDLER 118 /* VSC1 IRQ handler */
|
||||
IRQ_HANDLER 119 /* CLC0[0] IRQ handler */
|
||||
IRQ_HANDLER 120 /* CLC0[1] IRQ handler */
|
||||
IRQ_HANDLER 121 /* CLC1[0] IRQ handler */
|
||||
IRQ_HANDLER 122 /* CLC1[1] IRQ handler */
|
||||
IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */
|
||||
IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */
|
||||
IRQ_HANDLER 125 /* ENET0 IRQ handler */
|
||||
IRQ_HANDLER 126 /* NTMR0 IRQ handler */
|
||||
IRQ_HANDLER 127 /* USB0 IRQ handler */
|
||||
IRQ_HANDLER 128 /* TSW[0] IRQ handler */
|
||||
IRQ_HANDLER 129 /* TSW[1] IRQ handler */
|
||||
IRQ_HANDLER 130 /* TSW[2] IRQ handler */
|
||||
IRQ_HANDLER 131 /* TSW[3] IRQ handler */
|
||||
IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */
|
||||
IRQ_HANDLER 133 /* ESC IRQ handler */
|
||||
IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */
|
||||
IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */
|
||||
IRQ_HANDLER 136 /* ESC_RESET IRQ handler */
|
||||
IRQ_HANDLER 137 /* XPI0 IRQ handler */
|
||||
IRQ_HANDLER 138 /* FEMC IRQ handler */
|
||||
IRQ_HANDLER 139 /* PPI IRQ handler */
|
||||
IRQ_HANDLER 140 /* XDMA IRQ handler */
|
||||
IRQ_HANDLER 141 /* FFA IRQ handler */
|
||||
IRQ_HANDLER 142 /* SDP IRQ handler */
|
||||
IRQ_HANDLER 143 /* RNG IRQ handler */
|
||||
IRQ_HANDLER 144 /* PKA IRQ handler */
|
||||
IRQ_HANDLER 145 /* PSEC IRQ handler */
|
||||
IRQ_HANDLER 146 /* PGPIO IRQ handler */
|
||||
IRQ_HANDLER 147 /* PEWDG IRQ handler */
|
||||
IRQ_HANDLER 148 /* PTMR IRQ handler */
|
||||
IRQ_HANDLER 149 /* PUART IRQ handler */
|
||||
IRQ_HANDLER 150 /* FUSE IRQ handler */
|
||||
IRQ_HANDLER 151 /* SECMON IRQ handler */
|
||||
IRQ_HANDLER 152 /* RTC IRQ handler */
|
||||
IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */
|
||||
IRQ_HANDLER 154 /* BGPIO IRQ handler */
|
||||
IRQ_HANDLER 155 /* BVIO IRQ handler */
|
||||
IRQ_HANDLER 156 /* BROWNOUT IRQ handler */
|
||||
IRQ_HANDLER 157 /* SYSCTL IRQ handler */
|
||||
IRQ_HANDLER 158 /* CPU0 IRQ handler */
|
||||
IRQ_HANDLER 159 /* CPU1 IRQ handler */
|
||||
IRQ_HANDLER 160 /* DEBUG0 IRQ handler */
|
||||
IRQ_HANDLER 161 /* DEBUG1 IRQ handler */
|
||||
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include <rtthread.h>
|
||||
#include "rt_hw_stack_frame.h"
|
||||
|
||||
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
|
||||
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
|
||||
#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction
|
||||
#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint
|
||||
#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned
|
||||
#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault
|
||||
#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned
|
||||
#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault
|
||||
#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode
|
||||
#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode
|
||||
#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode
|
||||
#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault
|
||||
#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault
|
||||
#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault
|
||||
|
||||
#define IRQ_S_SOFT 1
|
||||
#define IRQ_H_SOFT 2
|
||||
#define IRQ_M_SOFT 3
|
||||
#define IRQ_S_TIMER 5
|
||||
#define IRQ_H_TIMER 6
|
||||
#define IRQ_M_TIMER 7
|
||||
#define IRQ_S_EXT 9
|
||||
#define IRQ_H_EXT 10
|
||||
#define IRQ_M_EXT 11
|
||||
#define IRQ_COP 12
|
||||
#define IRQ_HOST 13
|
||||
|
||||
#ifdef DEBUG
|
||||
#define RT_EXCEPTION_TRACE rt_kprintf
|
||||
#else
|
||||
#define RT_EXCEPTION_TRACE(...)
|
||||
#endif
|
||||
|
||||
typedef void (*isr_func_t)(void);
|
||||
|
||||
static volatile rt_hw_stack_frame_t *s_stack_frame;
|
||||
|
||||
__attribute((weak)) void mchtmr_isr(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__((weak)) void mswi_isr(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
|
||||
{
|
||||
}
|
||||
|
||||
void rt_show_stack_frame(void)
|
||||
{
|
||||
RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n");
|
||||
RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra);
|
||||
RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
|
||||
RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0);
|
||||
RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1);
|
||||
RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2);
|
||||
RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0);
|
||||
RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1);
|
||||
RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2);
|
||||
RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3);
|
||||
RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4);
|
||||
RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5);
|
||||
#ifndef __riscv_32e
|
||||
RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6);
|
||||
RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7);
|
||||
RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3);
|
||||
RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4);
|
||||
RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5);
|
||||
RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t exception_handler(uint32_t cause, uint32_t epc)
|
||||
{
|
||||
/* Unhandled Trap */
|
||||
uint32_t mdcause = read_csr(CSR_MDCAUSE);
|
||||
uint32_t mtval = read_csr(CSR_MTVAL);
|
||||
rt_uint32_t mscratch = read_csr(0x340);
|
||||
|
||||
s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
|
||||
rt_show_stack_frame();
|
||||
|
||||
switch (cause)
|
||||
{
|
||||
case MCAUSE_INSTR_ADDR_MISALIGNED:
|
||||
RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
|
||||
break;
|
||||
case MCAUSE_INSTR_ACCESS_FAULT:
|
||||
RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
|
||||
switch (mdcause & 0x07)
|
||||
{
|
||||
case 1:
|
||||
RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
|
||||
break;
|
||||
case 2:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
|
||||
break;
|
||||
case 3:
|
||||
RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
|
||||
break;
|
||||
case 4:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
|
||||
break;
|
||||
default:
|
||||
RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MCAUSE_ILLEGAL_INSTR:
|
||||
RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
|
||||
switch (mdcause & 0x07)
|
||||
{
|
||||
case 0:
|
||||
RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
|
||||
break;
|
||||
case 1:
|
||||
RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n");
|
||||
break;
|
||||
case 2:
|
||||
RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n");
|
||||
break;
|
||||
default:
|
||||
RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MCAUSE_BREAKPOINT:
|
||||
RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
|
||||
break;
|
||||
case MCAUSE_LOAD_ADDR_MISALIGNED:
|
||||
RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
|
||||
break;
|
||||
case MCAUSE_LOAD_ACCESS_FAULT:
|
||||
RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
|
||||
switch (mdcause & 0x07)
|
||||
{
|
||||
case 1:
|
||||
RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
|
||||
break;
|
||||
case 2:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
|
||||
break;
|
||||
case 3:
|
||||
RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
|
||||
break;
|
||||
case 4:
|
||||
RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
|
||||
break;
|
||||
case 5:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
|
||||
break;
|
||||
case 6:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
|
||||
break;
|
||||
default:
|
||||
RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
|
||||
RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc);
|
||||
break;
|
||||
case MCAUSE_STORE_AMO_ACCESS_FAULT:
|
||||
RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc);
|
||||
switch (mdcause & 0x07)
|
||||
{
|
||||
case 1:
|
||||
RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
|
||||
break;
|
||||
case 2:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
|
||||
break;
|
||||
case 3:
|
||||
RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
|
||||
break;
|
||||
case 4:
|
||||
RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
|
||||
break;
|
||||
case 5:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
|
||||
break;
|
||||
case 6:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
|
||||
break;
|
||||
case 7:
|
||||
RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n");
|
||||
default:
|
||||
RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause);
|
||||
break;
|
||||
}
|
||||
|
||||
rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra);
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
void trap_entry(void);
|
||||
|
||||
void trap_entry(void)
|
||||
{
|
||||
uint32_t mcause = read_csr(CSR_MCAUSE);
|
||||
uint32_t mepc = read_csr(CSR_MEPC);
|
||||
uint32_t mstatus = read_csr(CSR_MSTATUS);
|
||||
|
||||
#if SUPPORT_PFT_ARCH
|
||||
uint32_t mxstatus = read_csr(CSR_MXSTATUS);
|
||||
#endif
|
||||
#ifdef __riscv_dsp
|
||||
int ucode = read_csr(CSR_UCODE);
|
||||
#endif
|
||||
#ifdef __riscv_flen
|
||||
int fcsr = read_fcsr();
|
||||
#endif
|
||||
|
||||
/* clobbers list for ecall */
|
||||
#ifdef __riscv_32e
|
||||
__asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
|
||||
#else
|
||||
__asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
|
||||
#endif
|
||||
|
||||
/* Do your trap handling */
|
||||
uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
|
||||
uint32_t irq_index;
|
||||
if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
|
||||
{
|
||||
switch (cause_type)
|
||||
{
|
||||
/* Machine timer interrupt */
|
||||
case IRQ_M_TIMER:
|
||||
mchtmr_isr();
|
||||
break;
|
||||
/* Machine EXT interrupt */
|
||||
case IRQ_M_EXT:
|
||||
/* Claim interrupt */
|
||||
irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
|
||||
/* Execute EXT interrupt handler */
|
||||
if (irq_index > 0)
|
||||
{
|
||||
((isr_func_t) __vector_table[irq_index])();
|
||||
/* Complete interrupt */
|
||||
__plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
|
||||
}
|
||||
break;
|
||||
/* Machine SWI interrupt */
|
||||
case IRQ_M_SOFT:
|
||||
mswi_isr();
|
||||
intc_m_complete_swi();
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
|
||||
{
|
||||
/* Machine Syscal call */
|
||||
__asm volatile(
|
||||
"mv a4, a3\n"
|
||||
"mv a3, a2\n"
|
||||
"mv a2, a1\n"
|
||||
"mv a1, a0\n"
|
||||
#ifdef __riscv_32e
|
||||
"mv a0, t0\n"
|
||||
#else
|
||||
"mv a0, a7\n"
|
||||
#endif
|
||||
"call syscall_handler\n"
|
||||
: : : "a4"
|
||||
);
|
||||
mepc += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
mepc = exception_handler(mcause, mepc);
|
||||
}
|
||||
|
||||
/* Restore CSR */
|
||||
write_csr(CSR_MSTATUS, mstatus);
|
||||
write_csr(CSR_MEPC, mepc);
|
||||
#if SUPPORT_PFT_ARCH
|
||||
write_csr(CSR_MXSTATUS, mxstatus);
|
||||
#endif
|
||||
#ifdef __riscv_dsp
|
||||
write_csr(CSR_UCODE, ucode);
|
||||
#endif
|
||||
#ifdef __riscv_flen
|
||||
write_fcsr(fcsr);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Trap Handler
|
||||
*/
|
||||
rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
# for module compiling
|
||||
import os
|
||||
Import('rtconfig')
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
|
||||
objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
Return('objs')
|
||||
Loading…
Reference in New Issue