[Bsp][STM32F4xx-HAL]fix warning

This commit is contained in:
zyh 2018-07-16 22:32:07 +08:00
parent 6deeb61efb
commit 6bb167e995
1 changed files with 9 additions and 9 deletions

View File

@ -1580,7 +1580,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
}; };
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const rt_uint16_t get_pin(uint8_t pin) static rt_uint16_t get_pin(uint8_t pin)
{ {
rt_uint16_t gpio_pin = __STM32_PIN_DEFAULT; rt_uint16_t gpio_pin = __STM32_PIN_DEFAULT;
if (pin < ITEM_NUM(pins)) if (pin < ITEM_NUM(pins))
@ -1590,7 +1590,7 @@ const rt_uint16_t get_pin(uint8_t pin)
return gpio_pin; return gpio_pin;
}; };
void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
gpio_pin = get_pin(pin); gpio_pin = get_pin(pin);
@ -1601,7 +1601,7 @@ void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
HAL_GPIO_WritePin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin), (GPIO_PinState)value); HAL_GPIO_WritePin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin), (GPIO_PinState)value);
} }
int stm32_pin_read(rt_device_t dev, rt_base_t pin) static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
gpio_pin = get_pin(pin); gpio_pin = get_pin(pin);
@ -1612,7 +1612,7 @@ int stm32_pin_read(rt_device_t dev, rt_base_t pin)
return HAL_GPIO_ReadPin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin)); return HAL_GPIO_ReadPin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin));
} }
void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
@ -1653,7 +1653,7 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
HAL_GPIO_Init(get_st_gpio(gpio_pin), &GPIO_InitStruct); HAL_GPIO_Init(get_st_gpio(gpio_pin), &GPIO_InitStruct);
} }
rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) static const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
{ {
rt_int32_t mapindex = gpio_pin & 0xFF; rt_int32_t mapindex = gpio_pin & 0xFF;
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
@ -1663,7 +1663,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
return &pin_irq_map[mapindex]; return &pin_irq_map[mapindex];
}; };
rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args) rt_uint32_t mode, void (*hdr)(void *args), void *args)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
@ -1701,7 +1701,7 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
return RT_EOK; return RT_EOK;
} }
rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) static rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
rt_base_t level; rt_base_t level;
@ -1730,7 +1730,7 @@ rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
return RT_EOK; return RT_EOK;
} }
rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled) rt_uint32_t enabled)
{ {
rt_uint16_t gpio_pin; rt_uint16_t gpio_pin;
@ -1814,7 +1814,7 @@ int rt_hw_pin_init(void)
} }
INIT_BOARD_EXPORT(rt_hw_pin_init); INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) static void pin_irq_hdr(uint16_t GPIO_Pin)
{ {
int irqno = 0; int irqno = 0;
for(irqno = 0; irqno < 16; irqno ++) for(irqno = 0; irqno < 16; irqno ++)