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[libcpu] fix s-mode issue

This commit is contained in:
BernardXiong 2021-10-19 14:35:22 +08:00
parent bcdd4a6256
commit 6b66207048
3 changed files with 21 additions and 10 deletions
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9
libcpu/risc-v/virt64/interrupt.c
View File

@ -14,7 +14,6 @@
#include "riscv.h" #include "riscv.h"
#include "interrupt.h" #include "interrupt.h"
#define CPU_NUM 2
#define MAX_HANDLERS 128 #define MAX_HANDLERS 128
static struct rt_irq_desc irq_desc[MAX_HANDLERS]; static struct rt_irq_desc irq_desc[MAX_HANDLERS];
@ -60,7 +59,6 @@ void rt_hw_interrupt_init(void)
/* init exceptions table */ /* init exceptions table */
for (idx = 0; idx < MAX_HANDLERS; idx++) for (idx = 0; idx < MAX_HANDLERS; idx++)
{ {
//rt_hw_interrupt_mask(idx);
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
irq_desc[idx].param = RT_NULL; irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO #ifdef RT_USING_INTERRUPT_INFO
@ -68,6 +66,8 @@ void rt_hw_interrupt_init(void)
irq_desc[idx].counter = 0; irq_desc[idx].counter = 0;
#endif #endif
} }
plic_set_threshold(0);
} }
/** /**
@ -86,7 +86,7 @@ void rt_hw_interrupt_mask(int vector)
void rt_hw_interrupt_umask(int vector) void rt_hw_interrupt_umask(int vector)
{ {
plic_set_priority(vector, 1); plic_set_priority(vector, 1);
plic_set_threshold(0);
rt_hw_plic_irq_enable(vector); rt_hw_plic_irq_enable(vector);
} }
@ -182,6 +182,7 @@ void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_st
{ {
int cause = (xcause & 0xFFFFFFFF); int cause = (xcause & 0xFFFFFFFF);
int plic_irq = 0; int plic_irq = 0;
if (xcause & (1UL << 63)) if (xcause & (1UL << 63))
{ {
switch (cause) switch (cause)
@ -197,11 +198,13 @@ void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_st
case IRQ_S_TIMER: case IRQ_S_TIMER:
tick_isr(); tick_isr();
break; break;
case IRQ_S_EXT: case IRQ_S_EXT:
plic_irq = plic_claim(); plic_irq = plic_claim();
plic_complete(plic_irq); plic_complete(plic_irq);
irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param); irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
break; break;
case IRQ_M_EXT: case IRQ_M_EXT:
plic_irq = plic_claim(); plic_irq = plic_claim();
plic_complete(plic_irq); plic_complete(plic_irq);

10
libcpu/risc-v/virt64/riscv_io.h
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@ -10,15 +10,15 @@
#ifndef __RISCV_IO_H__ #ifndef __RISCV_IO_H__
#define __RISCV_IO_H__ #define __RISCV_IO_H__
// which hart (core) is this? static inline uint32_t __raw_hartid(void)
static inline uint32_t r_mhartid()
{ {
#ifndef RISCV_S_MODE #ifdef RISCV_S_MODE
extern int boot_hartid;
return boot_hartid;
#else
uint32_t x; uint32_t x;
asm volatile("csrr %0, mhartid" : "=r" (x) ); asm volatile("csrr %0, mhartid" : "=r" (x) );
return x; return x;
#else
return 0;
#endif #endif
} }

12
libcpu/risc-v/virt64/startup_gcc.S
View File

@ -14,10 +14,18 @@
#define XSTATUS_PUM (1 << 18) #define XSTATUS_PUM (1 << 18)
#include <cpuport.h> #include <cpuport.h>
boot_hartid: .int
.global boot_hartid
.global _start .global _start
.section ".start", "ax" .section ".start", "ax"
_start: _start:
#ifndef RISCV_S_MODE #ifdef RISCV_S_MODE
# save hartid
la t0, boot_hartid # global varible rt_boot_hartid
mv t1, a0 # get hartid in S-mode frome a0 register
sw t1, (t0) # store t1 register low 4 bits in memory address which is stored in t0
#else
# setup stacks per hart # setup stacks per hart
csrr t0, mhartid # read current hart id csrr t0, mhartid # read current hart id
slli t0, t0, 10 # shift left the hart id by 1024 slli t0, t0, 10 # shift left the hart id by 1024
@ -54,4 +62,4 @@ _start:
park: park:
wfi wfi
j park j park