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[bsp][renesas] add renesas soft spi driver

This commit is contained in:
Yuqiang Wang 2024-03-12 16:22:57 +08:00 committed by Rbb666
parent fad78950ea
commit 6aa1442f64
7 changed files with 317 additions and 440 deletions
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3
bsp/renesas/libraries/HAL_Drivers/SConscript
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@ -41,6 +41,9 @@ if GetDepend(['BSP_USING_SPI']):
if GetDepend(['BSP_USING_SCI_SPI']):
src += ['drv_sci_spi.c']
if GetDepend(['BSP_USING_SOFT_SPI']):
src += ['drv_soft_spi.c']
if GetDepend(['BSP_USING_SCI']):
src += ['drv_sci.c']

225
bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.c Normal file
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@ -0,0 +1,225 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-12 Wangyuqiang the first version
*/
#include <board.h>
#include <string.h>
#include "drv_soft_spi.h"
#include "drv_config.h"
#if defined BSP_USING_SOFT_SPI
//#define DRV_DEBUG
#define LOG_TAG "drv.soft_spi"
#include <drv_log.h>
static struct ra_soft_spi_config soft_spi_config[] =
{
#ifdef BSP_USING_SOFT_SPI1
SOFT_SPI1_BUS_CONFIG,
#endif
#ifdef BSP_USING_SOFT_SPI2
SOFT_SPI2_BUS_CONFIG,
#endif
};
/**
* Attach the spi device to soft SPI bus, this function must be used after initialization.
*/
rt_err_t rt_soft_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
{
rt_err_t result;
struct rt_spi_device *spi_device;
/* attach the device to soft spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
return result;
}
static void ra_spi_gpio_init(struct ra_soft_spi *spi)
{
struct ra_soft_spi_config *cfg = (struct ra_soft_spi_config *)spi->cfg;
rt_pin_mode(cfg->sck, PIN_MODE_OUTPUT);
rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
rt_pin_write(cfg->miso, PIN_HIGH);
rt_pin_write(cfg->sck, PIN_HIGH);
rt_pin_write(cfg->mosi, PIN_HIGH);
}
static void ra_tog_sclk(void *data)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if(rt_pin_read(cfg->sck) == PIN_HIGH)
{
rt_pin_write(cfg->sck, PIN_LOW);
}
else
{
rt_pin_write(cfg->sck, PIN_HIGH);
}
}
static void ra_set_sclk(void *data, rt_int32_t state)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if (state)
{
rt_pin_write(cfg->sck, PIN_HIGH);
}
else
{
rt_pin_write(cfg->sck, PIN_LOW);
}
}
static void ra_set_mosi(void *data, rt_int32_t state)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if (state)
{
rt_pin_write(cfg->mosi, PIN_HIGH);
}
else
{
rt_pin_write(cfg->mosi, PIN_LOW);
}
}
static void ra_set_miso(void *data, rt_int32_t state)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if (state)
{
rt_pin_write(cfg->miso, PIN_HIGH);
}
else
{
rt_pin_write(cfg->miso, PIN_LOW);
}
}
static rt_int32_t ra_get_sclk(void *data)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
return rt_pin_read(cfg->sck);
}
static rt_int32_t ra_get_mosi(void *data)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
return rt_pin_read(cfg->mosi);
}
static rt_int32_t ra_get_miso(void *data)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
return rt_pin_read(cfg->miso);
}
static void ra_dir_mosi(void *data, rt_int32_t state)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if (state)
{
rt_pin_mode(cfg->mosi, PIN_MODE_INPUT);
}
else
{
rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
}
}
static void ra_dir_miso(void *data, rt_int32_t state)
{
struct ra_soft_spi_config* cfg = (struct ra_soft_spi_config*)data;
if (state)
{
rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
}
else
{
rt_pin_mode(cfg->miso, PIN_MODE_OUTPUT);
}
}
static void ra_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000UL / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
static struct rt_spi_bit_ops ra_soft_spi_ops =
{
.data = RT_NULL,
.tog_sclk = ra_tog_sclk,
.set_sclk = ra_set_sclk,
.set_mosi = ra_set_mosi,
.set_miso = ra_set_miso,
.get_sclk = ra_get_sclk,
.get_mosi = ra_get_mosi,
.get_miso = ra_get_miso,
.dir_mosi = ra_dir_mosi,
.dir_miso = ra_dir_miso,
.udelay = ra_udelay,
.delay_us = 1,
};
static struct ra_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])];
/* Soft SPI initialization function */
int rt_hw_softspi_init(void)
{
rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct ra_soft_spi);
rt_err_t result;
for (int i = 0; i < obj_num; i++)
{
memcpy(&spi_obj[i].ops, &ra_soft_spi_ops, sizeof(struct rt_spi_bit_ops));
spi_obj[i].ops.data = (void *)&soft_spi_config[i];
spi_obj[i].spi.ops = &ra_soft_spi_ops;
spi_obj[i].cfg = (void *)&soft_spi_config[i];
ra_spi_gpio_init(&spi_obj[i]);
result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &spi_obj[i].ops);
RT_ASSERT(result == RT_EOK);
}
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_softspi_init);
#endif /* BSP_USING_SOFT_SPI */

57
bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.h Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-14 Wangyuqiang the first version
*/
#ifndef __DRV_SOFT_SPI__
#define __DRV_SOFT_SPI__
#include <rthw.h>
#include <rtdevice.h>
#include <spi-bit-ops.h>
/* ra soft spi config */
struct ra_soft_spi_config
{
rt_base_t sck;
rt_base_t mosi;
rt_base_t miso;
const char *bus_name;
};
/* ra soft spi dirver */
struct ra_soft_spi
{
struct rt_spi_bit_obj spi;
struct rt_spi_bit_ops ops;
struct ra_soft_spi_config *cfg;
};
#ifdef BSP_USING_SOFT_SPI1
#define SOFT_SPI1_BUS_CONFIG \
{ \
.sck = BSP_S_SPI1_SCK_PIN, \
.mosi = BSP_S_SPI1_MOSI_PIN, \
.miso = BSP_S_SPI1_MISO_PIN, \
.bus_name = "sspi1", \
}
#endif /* BSP_USING_SOFT_SPI1 */
#ifdef BSP_USING_SOFT_SPI2
#define SOFT_SPI2_BUS_CONFIG \
{ \
.sck = BSP_S_SPI2_SCK_PIN, \
.mosi = BSP_S_SPI2_MOSI_PIN, \
.miso = BSP_S_SPI2_MISO_PIN, \
.bus_name = "sspi2", \
}
#endif /* BSP_USING_SOFT_SPI2 */
rt_err_t rt_soft_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
int rt_soft_spi_init(void);
#endif /* __DRV_SOFT_SPI__ */

1
bsp/renesas/ra6m3-hmi-board/.project
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@ -20,6 +20,7 @@
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.rt-thread.studio.rttnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>

29
bsp/renesas/ra6m3-hmi-board/board/Kconfig
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@ -22,6 +22,8 @@ menu "Hardware Drivers Config"
select BSP_USING_PWM8
select BSP_USING_SOFT_I2C
select BSP_USING_I2C0
select BSP_USING_SOFT_SPI
select BSP_USING_SOFT_SPI1
imply RTDUINO_USING_SERVO
imply RTDUINO_USING_WIRE
default n
@ -536,6 +538,33 @@ menu "Hardware Drivers Config"
default n
endif
menuconfig BSP_USING_SOFT_SPI
bool "Enable soft SPI BUS"
default n
select RT_USING_PIN
select RT_USING_SPI_BITOPS
select RT_USING_SPI
if BSP_USING_SOFT_SPI
config BSP_USING_SOFT_SPI1
bool "Enable soft SPI1 BUS (software simulation)"
default n
if BSP_USING_SOFT_SPI1
comment "Please select your spi analog pin, e.g. 'P512': 0x512"
config BSP_S_SPI1_SCK_PIN
hex "spi1 sck pin number (hex)"
range 0x0000 0x0E0F
default 0x204
config BSP_S_SPI1_MOSI_PIN
hex "spi1 mosi pin number (hex)"
range 0x0000 0x0E0F
default 0x512
config BSP_S_SPI1_MISO_PIN
hex "spi1 miso pin number (hex)"
range 0x0000 0x0E0F
default 0x511
endif
endif
menuconfig BSP_USING_SOFT_I2C
bool "Enable software I2C bus"
select RT_USING_I2C

4
bsp/renesas/ra6m3-hmi-board/ra/SConscript
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@ -20,11 +20,11 @@ elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
cwd + '/fsp/inc/instances',
cwd + '/tes/dave2d/inc']
if GetDepend('BSP_USING_G2D'):
src += Glob(cwd + '/tes/dave2d/src/*.c')
CPPPATH += [cwd + '/tes/dave2d/inc']
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

438
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_gpt.h
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@ -1,438 +0,0 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_GPT_H
#define R_GPT_H
/*******************************************************************************************************************//**
* @addtogroup GPT
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_timer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */
typedef enum e_gpt_io_pin
{
GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA
GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB
GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB
GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
} gpt_io_pin_t;
/** Level of GPT pin */
typedef enum e_gpt_pin_level
{
GPT_PIN_LEVEL_LOW = 0, ///< Pin level low
GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high
} gpt_pin_level_t;
/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent
* a bitmask. Multiple sources can be ORed together. */
typedef enum e_gpt_source
{
/** No active event sources. */
GPT_SOURCE_NONE = 0U,
/** Action performed on GTETRGA rising edge. **/
GPT_SOURCE_GTETRGA_RISING = (1U << 0),
/** Action performed on GTETRGA falling edge. **/
GPT_SOURCE_GTETRGA_FALLING = (1U << 1),
/** Action performed on GTETRGB rising edge. **/
GPT_SOURCE_GTETRGB_RISING = (1U << 2),
/** Action performed on GTETRGB falling edge. **/
GPT_SOURCE_GTETRGB_FALLING = (1U << 3),
/** Action performed on GTETRGC rising edge. **/
GPT_SOURCE_GTETRGC_RISING = (1U << 4),
/** Action performed on GTETRGC falling edge. **/
GPT_SOURCE_GTETRGC_FALLING = (1U << 5),
/** Action performed on GTETRGB rising edge. **/
GPT_SOURCE_GTETRGD_RISING = (1U << 6),
/** Action performed on GTETRGB falling edge. **/
GPT_SOURCE_GTETRGD_FALLING = (1U << 7),
/** Action performed when GTIOCA input rises while GTIOCB is low. **/
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8),
/** Action performed when GTIOCA input rises while GTIOCB is high. **/
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9),
/** Action performed when GTIOCA input falls while GTIOCB is low. **/
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10),
/** Action performed when GTIOCA input falls while GTIOCB is high. **/
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11),
/** Action performed when GTIOCB input rises while GTIOCA is low. **/
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12),
/** Action performed when GTIOCB input rises while GTIOCA is high. **/
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13),
/** Action performed when GTIOCB input falls while GTIOCA is low. **/
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14),
/** Action performed when GTIOCB input falls while GTIOCA is high. **/
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15),
/** Action performed on ELC GPTA event. **/
GPT_SOURCE_GPT_A = (1U << 16),
/** Action performed on ELC GPTB event. **/
GPT_SOURCE_GPT_B = (1U << 17),
/** Action performed on ELC GPTC event. **/
GPT_SOURCE_GPT_C = (1U << 18),
/** Action performed on ELC GPTD event. **/
GPT_SOURCE_GPT_D = (1U << 19),
/** Action performed on ELC GPTE event. **/
GPT_SOURCE_GPT_E = (1U << 20),
/** Action performed on ELC GPTF event. **/
GPT_SOURCE_GPT_F = (1U << 21),
/** Action performed on ELC GPTG event. **/
GPT_SOURCE_GPT_G = (1U << 22),
/** Action performed on ELC GPTH event. **/
GPT_SOURCE_GPT_H = (1U << 23),
} gpt_source_t;
/** Configurations for output pins. */
typedef struct s_gpt_output_pin
{
bool output_enabled; ///< Set to true to enable output, false to disable output
gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t
} gpt_output_pin_t;
/** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */
typedef struct s_gpt_gtior_setting
{
union
{
uint32_t gtior;
struct
{
/* Settings for GTIOCxA pin. */
uint32_t gtioa : 5; ///< GTIOCA Pin Function Select.
uint32_t : 1; // Reserved
uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop.
uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count.
uint32_t oae : 1; ///< GTIOCA Pin Output Enable
uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting.
uint32_t : 2; /// Reserved
uint32_t nfaen : 1; /// Noise Filter A Enable.
uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select.
/* Settings for GTIOCxB pin. */
uint32_t gtiob : 5; ///< GTIOCB Pin Function Select.
uint32_t : 1; // Reserved
uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop.
uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count.
uint32_t obe : 1; ///< GTIOCB Pin Output Enable
uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting.
uint32_t : 2; /// Reserved
uint32_t nfben : 1; /// Noise Filter B Enable.
uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select.
} gtior_b;
};
} gpt_gtior_setting_t;
/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB.
* The noise filter samples the external signal at intervals of the PCLK divided by one of the values.
* When 3 consecutive samples are at the same level (high or low), then that level is passed on as
* the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section.
*/
typedef enum e_gpt_capture_filter
{
GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering
GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling
GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4
GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16
GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling
} gpt_capture_filter_t;
/** Trigger options to start A/D conversion. */
typedef enum e_gpt_adc_trigger
{
GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
} gpt_adc_trigger_t;
/** POEG channel to link to this channel. */
typedef enum e_gpt_poeg_link
{
GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA)
GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB)
GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC)
GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD)
} gpt_poeg_link_t;
/** Select trigger to send output disable request to POEG. */
typedef enum e_gpt_output_disable
{
GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request
GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time
} gpt_output_disable_t;
/** Disable level options for GTIOC pins. */
typedef enum e_gpt_gtioc_disable
{
GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable
GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled
GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled
GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled
} gpt_gtioc_disable_t;
/** Trigger options to start A/D conversion. */
typedef enum e_gpt_adc_compare_match
{
GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A
GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B
} gpt_adc_compare_match_t;
/** Interrupt skipping modes */
typedef enum e_gpt_interrupt_skip_source
{
GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts
GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts
/** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
* @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest
* interrupt. */
GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U,
/** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
* @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough
* interrupt. */
GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U,
} gpt_interrupt_skip_source_t;
/** Number of interrupts to skip between events */
typedef enum e_gpt_interrupt_skip_count
{
GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts
GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt
GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts
GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts
GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts
GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts
GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts
GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts
} gpt_interrupt_skip_count_t;
/** ADC events to skip during interrupt skipping */
typedef enum e_gpt_interrupt_skip_adc
{
GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events
GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events
GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events
GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events
} gpt_interrupt_skip_adc_t;
/** Delay setting for the PWM Delay Generation Circuit (PDG). */
typedef enum e_gpt_pwm_output_delay_setting
{
GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied.
GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit.
} gpt_pwm_output_delay_setting_t;
/** Select which PWM Output Delay setting to apply. */
typedef enum e_gpt_pwm_output_delay_edge
{
GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge.
GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge.
} gpt_pwm_output_delay_edge_t;
/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */
typedef struct st_gpt_instance_ctrl
{
uint32_t open; // Whether or not channel is open
const timer_cfg_t * p_cfg; // Pointer to initial configurations
R_GPT0_Type * p_reg; // Base register for this channel
uint32_t channel_mask; // Channel bitmask
timer_variant_t variant; // Timer variant
void (* p_callback)(timer_callback_args_t *); // Pointer to callback
timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory
void const * p_context; // Pointer to context to be passed into callback function
} gpt_instance_ctrl_t;
/** GPT extension for advanced PWM features. */
typedef struct st_gpt_extended_pwm_cfg
{
uint8_t trough_ipl; ///< Trough interrupt priority
IRQn_Type trough_irq; ///< Trough interrupt
gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel
gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG
gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion
uint32_t dead_time_count_up; ///< Set a dead time value for counting up
uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only)
uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A
uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B
gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping
gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events
gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled
gpt_gtioc_disable_t gtioca_disable_setting; ///< DEPRECATED - Select how to configure GTIOCA when output is disabled
gpt_gtioc_disable_t gtiocb_disable_setting; ///< DEPRECATED - Select how to configure GTIOCB when output is disabled
} gpt_extended_pwm_cfg_t;
/** GPT extension configures the output pins for GPT. */
typedef struct st_gpt_extended_cfg
{
gpt_output_pin_t gtioca; ///< DEPRECATED - Configuration for GPT I/O pin A
gpt_output_pin_t gtiocb; ///< DEPRECATED - Configuration for GPT I/O pin B
gpt_source_t start_source; ///< Event sources that trigger the timer to start
gpt_source_t stop_source; ///< Event sources that trigger the timer to stop
gpt_source_t clear_source; ///< Event sources that trigger the timer to clear
gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA
gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB
/** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source
* and count_down_source, then the timer count source is PCLK. */
gpt_source_t count_up_source;
/** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source
* and count_down_source, then the timer count source is PCLK. */
gpt_source_t count_down_source;
/* Debounce filter for GTIOCxA input signal pin (DEPRECATED). */
gpt_capture_filter_t capture_filter_gtioca;
/* Debounce filter for GTIOCxB input signal pin (DEPRECATED). */
gpt_capture_filter_t capture_filter_gtiocb;
uint8_t capture_a_ipl; ///< Capture A interrupt priority
uint8_t capture_b_ipl; ///< Capture B interrupt priority
IRQn_Type capture_a_irq; ///< Capture A interrupt
IRQn_Type capture_b_irq; ///< Capture B interrupt
gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional
gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins.
} gpt_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const timer_api_t g_timer_on_gpt;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl,
gpt_adc_compare_match_t which_compare_match,
uint32_t compare_match_value);
fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl,
gpt_pwm_output_delay_edge_t edge,
gpt_pwm_output_delay_setting_t delay_setting,
uint32_t const pin);
fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl,
void ( * p_callback)(timer_callback_args_t *),
void const * const p_context,
timer_callback_args_t * const p_callback_memory);
fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl);
fsp_err_t R_GPT_PwmOutputDelayInitialize();
/*******************************************************************************************************************//**
* @} (end defgroup GPT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif