[bsp/at32] ethernet support phy lan8720 and yt8512
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2d266742e0
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6a30ec2625
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@ -42,6 +42,12 @@ menu "On-chip Peripheral Drivers"
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config PHY_USING_DP83848
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bool "PHY USING DP83848"
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config PHY_USING_LAN8720
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bool "PHY USING LAN8720"
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config PHY_USING_YT8512
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bool "PHY USING YT8512"
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endchoice
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endif
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@ -81,6 +81,12 @@ menu "On-chip Peripheral Drivers"
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config PHY_USING_DP83848
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bool "PHY USING DP83848"
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config PHY_USING_LAN8720
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bool "PHY USING LAN8720"
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config PHY_USING_YT8512
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bool "PHY USING YT8512"
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endchoice
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endif
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@ -10,6 +10,7 @@
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* performance
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* 2022-10-15 shelton optimize code
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* 2023-10-18 shelton optimize code
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* 2024-09-02 shelton add support phy lan8720 and yt8512
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*/
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#include "drv_emac.h"
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@ -161,7 +162,8 @@ static void phy_clock_config(void)
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/* 83848 clkout output 50 mhz */
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#if defined (SOC_SERIES_AT32F407)
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crm_clock_out_set(CRM_CLKOUT_SCLK);
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#if defined (PHY_USING_DM9162)
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#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \
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defined (PHY_USING_YT8512)
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crm_clkout_div_set(CRM_CLKOUT_DIV_8);
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#elif defined (PHY_USING_DP83848)
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crm_clkout_div_set(CRM_CLKOUT_DIV_4);
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@ -170,7 +172,8 @@ static void phy_clock_config(void)
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#if defined (SOC_SERIES_AT32F437)
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crm_clock_out1_set(CRM_CLKOUT1_PLL);
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#if defined (PHY_USING_DM9162)
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#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \
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defined (PHY_USING_YT8512)
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crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_2);
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#elif defined (PHY_USING_DP83848)
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crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_1);
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@ -260,7 +263,7 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl
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{
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return ERROR;
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}
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#ifdef PHY_USING_DM9162
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#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720)
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if(data & PHY_FULL_DUPLEX_100MBPS_BIT)
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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@ -282,7 +285,7 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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#endif
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#ifdef PHY_USING_DP83848
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#if defined (PHY_USING_DP83848)
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if(data & PHY_DUPLEX_MODE)
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{
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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@ -299,6 +302,24 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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}
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#endif
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#if defined (PHY_USING_YT8512)
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if(data & PHY_DUPLEX_MODE)
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{
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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}
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else
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{
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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if(data & PHY_SPEED_MODE)
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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}
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else
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{
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emac_fast_speed_set(EMAC_SPEED_10MBPS);
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}
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#endif
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}
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else
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@ -475,12 +496,12 @@ rt_err_t emac_txpkt_chainmode(rt_uint32_t frame_length)
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if((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != (u32)RESET)
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{
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/* return error: own bit set */
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return RT_ERROR;
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return -RT_ERROR;
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}
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if(frame_length == 0)
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{
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return RT_ERROR;
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return -RT_ERROR;
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}
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if(frame_length > EMAC_MAX_PACKET_LENGTH)
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@ -629,7 +650,7 @@ rt_err_t emac_rxpkt_chainmode(void)
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if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) != (u32)RESET)
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{
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/* return error: own bit set */
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return RT_ERROR;
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return -RT_ERROR;
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}
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if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET)
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{
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@ -660,7 +681,7 @@ rt_err_t emac_rxpkt_chainmode(void)
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dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
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}
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return RT_ERROR;
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return -RT_ERROR;
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}
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/**
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@ -809,7 +830,9 @@ static void phy_linkchange()
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if (SR & (PHY_SPEED_MODE))
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{
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#if defined (PHY_USING_DP83848)
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phy_speed_new |= PHY_10M;
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#endif
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}
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if (SR & (PHY_DUPLEX_MODE))
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2024-09-02 shelton add support phy lan8720 and yt8512
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*/
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#ifndef __DRV_EMAC_H__
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@ -57,8 +58,6 @@
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#define PHY_INTERRUPT_FLAG_REG 0x15U
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x15U
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#define PHY_LINK_CHANGE_FLAG (1<<2)
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#define PHY_LINK_CHANGE_MASK (1<<9)
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#define PHY_INT_MASK 0
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#elif defined (PHY_USING_DP83848)
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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@ -84,6 +83,50 @@
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x12U
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#define PHY_INT_MASK (1<<5)
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#elif defined (PHY_USING_LAN8720)
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x1F) /*!< specified configuration and status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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/* phy specified control/status register */
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#define PHY_FULL_DUPLEX_100MBPS_BIT (0x0018) /*!< full duplex 100 mbps */
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#define PHY_HALF_DUPLEX_100MBPS_BIT (0x0008) /*!< half duplex 100 mbps */
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#define PHY_FULL_DUPLEX_10MBPS_BIT (0x0014) /*!< full duplex 10 mbps */
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#define PHY_HALF_DUPLEX_10MBPS_BIT (0x0004) /*!< half duplex 10 mbps */
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#define PHY_DUPLEX_MODE (0x0100) /*!< full duplex mode */
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#define PHY_SPEED_MODE (0x2000) /*!< 100 mbps */
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/* the phy interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x1DU
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x1EU
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#define PHY_INT_MASK (1<<4)
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#elif defined (PHY_USING_YT8512)
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x11) /*!< phy status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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#define PHY_DUPLEX_MODE (0x2000) /*!< full duplex mode */
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#define PHY_SPEED_MODE (0x4000) /*!< 100 mbps */
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/* the phy interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x13U
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#define PHY_LINK_CHANGE_FLAG (3<<10)
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x12U
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#define PHY_INT_MASK (3<<10)
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#endif
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#endif /* __DRV_EMAC_H__ */
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