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Update sdram (#6280) 

增加1170系列SDRAM时钟配置
修复sdram中memheap自动初始化时机错误导致被assert的情况

Co-authored-by: Meco Man <920369182@qq.com>
This commit is contained in:
xjy198903 2022-08-15 15:34:49 +08:00 committed by GitHub
parent 814b1abb08
commit 6a225fff22
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 645 additions and 6 deletions
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623
bsp/imxrt/imxrt1170-nxp-evk/board/board.c
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@ -6,6 +6,7 @@
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2009-01-05 Bernard first implementation * 2009-01-05 Bernard first implementation
* 2022-08-15 xjy198903 add sdram pin config
*/ */
#include <rthw.h> #include <rthw.h>
@ -605,6 +606,624 @@ void imxrt_eth_pins_init(void) {
} }
#endif #endif
#ifdef BSP_USING_SDRAM
void imxrt_sdram_pins_init(void)
{
// SEMC
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 is configured as SEMC_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 is configured as SEMC_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 is configured as SEMC_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 is configured as SEMC_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 is configured as SEMC_DATA04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 is configured as SEMC_DATA05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 is configured as SEMC_DATA06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 is configured as SEMC_DATA07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 is configured as SEMC_DM00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 is configured as SEMC_ADDR00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 is configured as SEMC_ADDR01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 is configured as SEMC_ADDR02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 is configured as SEMC_ADDR03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 is configured as SEMC_ADDR04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 is configured as SEMC_ADDR05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 is configured as SEMC_ADDR06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 is configured as SEMC_ADDR07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 is configured as SEMC_ADDR08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 is configured as SEMC_ADDR09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 is configured as SEMC_ADDR11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 is configured as SEMC_ADDR12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 is configured as SEMC_BA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 is configured as SEMC_BA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 is configured as SEMC_ADDR10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 is configured as SEMC_CAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 is configured as SEMC_RAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 is configured as SEMC_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 is configured as SEMC_CKE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 is configured as SEMC_WE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 is configured as SEMC_CS0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 is configured as SEMC_DATA08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 is configured as SEMC_DATA09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 is configured as SEMC_DATA10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 is configured as SEMC_DATA11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 is configured as SEMC_DATA12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 is configured as SEMC_DATA13 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 is configured as SEMC_DATA14 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 is configured as SEMC_DATA15 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 is configured as SEMC_DM01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 is configured as SEMC_DQS */
1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B1_39 */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 is configured as SEMC_RDY */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 is configured as SEMC_CSX00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 is configured as SEMC_DATA16 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 is configured as SEMC_DATA17 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 is configured as SEMC_DATA18 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 is configured as SEMC_DATA19 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 is configured as SEMC_DATA20 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 is configured as SEMC_DATA21 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 is configured as SEMC_DATA22 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 is configured as SEMC_DATA23 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 is configured as SEMC_DM02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 is configured as SEMC_DATA24 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 is configured as SEMC_DATA25 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 is configured as SEMC_DATA26 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 is configured as SEMC_DATA27 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 is configured as SEMC_DATA28 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 is configured as SEMC_DATA29 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 is configured as SEMC_DATA30 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 is configured as SEMC_DATA31 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 is configured as SEMC_DM03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 is configured as SEMC_DQS4 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 PAD functional properties : */
0x04U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pullup resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 PAD functional properties : */
0x04U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pullup resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 PAD functional properties : */
0x08U); /* PDRV Field: high drive strength
Pull Down Pull Up Field: Internal pulldown resistor enabled
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
#endif
void rt_hw_us_delay(rt_uint32_t us) void rt_hw_us_delay(rt_uint32_t us)
{ {
} }
@ -622,6 +1241,10 @@ void rt_hw_board_init()
imxrt_uart_pins_init(); imxrt_uart_pins_init();
#endif #endif
#ifdef BSP_USING_SDRAM
imxrt_sdram_pins_init();
#endif
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif #endif

8
bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h
View File

@ -7,6 +7,7 @@
* Date Author Notes * Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx * 2018-12-05 zylx The first version for STM32F4xx
* 2019-4-25 misonyo port to IMXRT * 2019-4-25 misonyo port to IMXRT
* 2022-08-15 xjy198903 add sdram config for rt1170
*/ */
#ifndef SDRAM_PORT_H__ #ifndef SDRAM_PORT_H__
@ -19,10 +20,17 @@
#define SDRAM_REGION kSEMC_SDRAM_CS0 #define SDRAM_REGION kSEMC_SDRAM_CS0
/* CS pin: kSEMC_MUXCSX0/1/2/3 */ /* CS pin: kSEMC_MUXCSX0/1/2/3 */
#define SDRAM_CS_PIN kSEMC_MUXCSX0 #define SDRAM_CS_PIN kSEMC_MUXCSX0
/* size(kbyte):64MB = 2*32*1024*1KBytes */
#if defined(SOC_IMXRT1170_SERIES)
#define SDRAM_SIZE ((uint32_t)(0x10000))
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize32Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize32Bit
#else
/* size(kbyte):32MB = 32*1024*1KBytes */ /* size(kbyte):32MB = 32*1024*1KBytes */
#define SDRAM_SIZE ((uint32_t)0x8000) #define SDRAM_SIZE ((uint32_t)0x8000)
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ /* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit #define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
#endif
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ /* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit #define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ /* cas latency clock number: kSEMC_LatencyOne/Two/Three */

3
bsp/imxrt/libraries/MIMXRT1170/SConscript
View File

@ -40,6 +40,9 @@ if GetDepend(['BSP_USING_PWM']):
if GetDepend(['BSP_USING_SDIO']): if GetDepend(['BSP_USING_SDIO']):
src += ['MIMXRT1176/drivers/fsl_usdhc.c'] src += ['MIMXRT1176/drivers/fsl_usdhc.c']
if GetDepend(['BSP_USING_SDRAM']):
src += ['MIMXRT1176/drivers/fsl_semc.c']
if rtconfig.CROSS_TOOL == 'gcc': if rtconfig.CROSS_TOOL == 'gcc':
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS') group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
else: else:

17
bsp/imxrt/libraries/drivers/drv_sdram.c
View File

@ -17,16 +17,21 @@
#define LOG_TAG "drv.sdram" #define LOG_TAG "drv.sdram"
#include <drv_log.h> #include <drv_log.h>
#ifdef RT_USING_MEMHEAP_AS_HEAP #ifdef RT_USING_MEMHEAP
static struct rt_memheap system_heap; static struct rt_memheap system_heap;
#endif #endif
int rt_hw_sdram_Init(void) static int rt_hw_sdram_init(void)
{ {
int result = RT_EOK; int result = RT_EOK;
semc_config_t config; semc_config_t config;
semc_sdram_config_t sdramconfig; semc_sdram_config_t sdramconfig;
#if defined(SOC_IMXRT1170_SERIES)
rt_uint32_t clockFrq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);
#else
rt_uint32_t clockFrq = CLOCK_GetFreq(kCLOCK_SemcClk); rt_uint32_t clockFrq = CLOCK_GetFreq(kCLOCK_SemcClk);
#endif
/* Initializes the MAC configure structure to zero. */ /* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t)); memset(&config, 0, sizeof(semc_config_t));
@ -67,9 +72,9 @@ int rt_hw_sdram_Init(void)
else else
{ {
LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE);
#ifdef RT_USING_MEMHEAP_AS_HEAP #ifdef RT_USING_MEMHEAP
/* /*
* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap. * If RT_USING_MEMHEAP is enabled, SDRAM is initialized to the heap.
* The heap start address is (base + half size), and the size is (half size - 2M). * The heap start address is (base + half size), and the size is (half size - 2M).
* The reasons are: * The reasons are:
* 1. Reserve the half space for SDRAM link case * 1. Reserve the half space for SDRAM link case
@ -82,7 +87,7 @@ int rt_hw_sdram_Init(void)
return result; return result;
} }
INIT_BOARD_EXPORT(rt_hw_sdram_Init); INIT_PREV_EXPORT(rt_hw_sdram_init);
#ifdef DRV_DEBUG #ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH #ifdef FINSH_USING_MSH
@ -92,7 +97,7 @@ rt_uint32_t sdram_writeBuffer[SEMC_DATALEN];
rt_uint32_t sdram_readBuffer[SEMC_DATALEN]; rt_uint32_t sdram_readBuffer[SEMC_DATALEN];
/* read write 32bit test */ /* read write 32bit test */
void sdram_test(void) static void sdram_test(void)
{ {
rt_uint32_t index; rt_uint32_t index;
rt_uint32_t datalen = SEMC_DATALEN; rt_uint32_t datalen = SEMC_DATALEN;