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*** EFM32 branch *** 

1. Add SD card driver (SPI mode)
2. Add ELM ChaN FatFs support (Please read "Readme.txt")
   - Warning: FatFs is really FAT! (35KB)
3. Upgrade EFM32 libraries (CMSIS and efm32lib) to version 2.0.0
4. Merge all of the C source code in "libcpu\arm\cortex-m3\" into "cpuport.c"
5. Merge all of the assembly source code in "libcpu\arm\cortex-m3\" into "context_gcc.S" (except "start_gcc.S")

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1525 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
onelife.real 2011-06-20 01:56:28 +00:00
parent 1eca19cb01
commit 69ad018bc0
168 changed files with 505057 additions and 12953 deletions
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845
bsp/efm32/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
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@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
* @version V2.00
* @date 13. September 2010
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@ -43,740 +43,297 @@
#endif
/* ################### Compiler specific Intrinsics ########################### */
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__ASM int32_t __REVSH(int16_t value)
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__ARMCC_VERSION < 400000)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/* ########################### Core Function Access ########################### */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/** \brief Get Control Register
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
This function returns the content of the ISPR Register.
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
\return ISPR Register value
*/
uint32_t __get_PSP(void)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
void __set_PSP(uint32_t topOfProcStack)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
__ASM("msr psp, r0");
__ASM("bx lr");
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
uint32_t __get_MSP(void)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
void __set_MSP(uint32_t topOfMainStack)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
__ASM("msr msp, r0");
__ASM("bx lr");
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
uint32_t __REV16(uint16_t value)
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
uint32_t __RBIT(uint32_t value)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
uint8_t __LDREXB(uint8_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
uint16_t __LDREXH(uint16_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
uint32_t __LDREXW(uint32_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask Register.
\return Fault Mask value
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
mrs r0, faultmask
bx lr
}
#pragma diag_default=Pe940
#endif /* __ARMCC_VERSION */
/** \brief Set the Fault Mask
This function assigns the given value to the Fault Mask Register.
\param [in] faultMask Fault Mask value value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, psp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack);
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n"
"BX lr \n" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, msp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack);
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n"
"BX lr \n" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif

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bsp/efm32/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
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bsp/efm32/Libraries/CMSIS/CM3/CoreSupport/core_cmFunc.h Normal file
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@ -0,0 +1,851 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
/* Energy Micro: Add support for new versions of IAR */
#if __VER__ >= 6020000
#include "cmsis_iar.h"
#else
/* Energy Micro: Fix end */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/* Energy Micro: This function is present in new IAR versions */
#if __VER__ < 6010002
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
#endif
/* Energy Micro: Fix end */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#endif
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H__ */

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@ -0,0 +1,782 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
/* Energy Micro: Add support for new versions of IAR */
#if __VER__ >= 6020000
#include "cmsis_iar.h"
#else
/* Energy Micro: Adpaptation end */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#endif
/* Energy Micro: Fix end */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H__ */

122
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h
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@ -1,6 +1,6 @@
/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 Gxxx Device series
* @brief CMSIS Cortex-M0/M3 Peripheral Access Layer for EFM32 device series
*
* This is a convenience header file for defining the EFM32 part number on the
* build command line, instead of specifying the part specific header file.
@ -9,10 +9,10 @@
* Add "#include "efm32.h" to your source files
* @endverbatim
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
@ -36,7 +36,6 @@
#ifndef __EFM32_H
#define __EFM32_H
/* Gecko Parts */
#if defined(EFM32G200F16)
#include "efm32g200f16.h"
@ -50,6 +49,15 @@
#elif defined(EFM32G210F128)
#include "efm32g210f128.h"
#elif defined(EFM32G222F128)
#include "efm32g222f128.h"
#elif defined(EFM32G222F32)
#include "efm32g222f32.h"
#elif defined(EFM32G222F64)
#include "efm32g222f64.h"
#elif defined(EFM32G230F128)
#include "efm32g230f128.h"
@ -59,6 +67,15 @@
#elif defined(EFM32G230F64)
#include "efm32g230f64.h"
#elif defined(EFM32G232F128)
#include "efm32g232f128.h"
#elif defined(EFM32G232F32)
#include "efm32g232f32.h"
#elif defined(EFM32G232F64)
#include "efm32g232f64.h"
#elif defined(EFM32G280F128)
#include "efm32g280f128.h"
@ -86,6 +103,15 @@
#elif defined(EFM32G840F64)
#include "efm32g840f64.h"
#elif defined(EFM32G842F128)
#include "efm32g842f128.h"
#elif defined(EFM32G842F32)
#include "efm32g842f32.h"
#elif defined(EFM32G842F64)
#include "efm32g842f64.h"
#elif defined(EFM32G880F128)
#include "efm32g880f128.h"
@ -104,6 +130,94 @@
#elif defined(EFM32G890F64)
#include "efm32g890f64.h"
#elif defined(EFM32TG108F16)
#include "efm32tg108f16.h"
#elif defined(EFM32TG108F32)
#include "efm32tg108f32.h"
#elif defined(EFM32TG108F4)
#include "efm32tg108f4.h"
#elif defined(EFM32TG108F8)
#include "efm32tg108f8.h"
#elif defined(EFM32TG110F16)
#include "efm32tg110f16.h"
#elif defined(EFM32TG110F32)
#include "efm32tg110f32.h"
#elif defined(EFM32TG110F4)
#include "efm32tg110f4.h"
#elif defined(EFM32TG110F8)
#include "efm32tg110f8.h"
#elif defined(EFM32TG210F16)
#include "efm32tg210f16.h"
#elif defined(EFM32TG210F32)
#include "efm32tg210f32.h"
#elif defined(EFM32TG210F8)
#include "efm32tg210f8.h"
#elif defined(EFM32TG222F16)
#include "efm32tg222f16.h"
#elif defined(EFM32TG222F32)
#include "efm32tg222f32.h"
#elif defined(EFM32TG222F8)
#include "efm32tg222f8.h"
#elif defined(EFM32TG230F16)
#include "efm32tg230f16.h"
#elif defined(EFM32TG230F32)
#include "efm32tg230f32.h"
#elif defined(EFM32TG230F8)
#include "efm32tg230f8.h"
#elif defined(EFM32TG232F16)
#include "efm32tg232f16.h"
#elif defined(EFM32TG232F32)
#include "efm32tg232f32.h"
#elif defined(EFM32TG232F8)
#include "efm32tg232f8.h"
#elif defined(EFM32TG822F16)
#include "efm32tg822f16.h"
#elif defined(EFM32TG822F32)
#include "efm32tg822f32.h"
#elif defined(EFM32TG822F8)
#include "efm32tg822f8.h"
#elif defined(EFM32TG840F16)
#include "efm32tg840f16.h"
#elif defined(EFM32TG840F32)
#include "efm32tg840f32.h"
#elif defined(EFM32TG840F8)
#include "efm32tg840f8.h"
#elif defined(EFM32TG842F16)
#include "efm32tg842f16.h"
#elif defined(EFM32TG842F32)
#include "efm32tg842f32.h"
#elif defined(EFM32TG842F8)
#include "efm32tg842f8.h"
#else
#error "efm32.h: PART NUMBER undefined"
#endif

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10
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/arm/startup_efm32.s
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@ -2,8 +2,8 @@
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro EFM32 device series
; * @version 1.3.0
; * @date: 7. September 2010
; * @version 2.0.0
; * @date: January 2011
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
@ -49,6 +49,8 @@ __heap_limit
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
@ -99,6 +101,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD MSC_IRQHandler ; 28: MSC Interrupt
DCD AES_IRQHandler ; 29: AES Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler

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bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/arm/startup_efm32tg.s Normal file
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@ -0,0 +1,240 @@
;/*****************************************************************************
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro EFM32 device series
; * @version 2.0.0
; * @date: January 2011
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
DCD USART1_RX_IRQHandler ; 11: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 12: USART1_TX Interrupt
DCD LESENSE_IRQHandler ; 13: LESENSE Interrupt
DCD LEUART0_IRQHandler ; 14: LEUART0 Interrupt
DCD LETIMER0_IRQHandler ; 15: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 16: PCNT0 Interrupt
DCD RTC_IRQHandler ; 17: RTC Interrupt
DCD CMU_IRQHandler ; 18: CMU Interrupt
DCD VCMP_IRQHandler ; 19: VCMP Interrupt
DCD LCD_IRQHandler ; 20: LCD Interrupt
DCD MSC_IRQHandler ; 21: MSC Interrupt
DCD AES_IRQHandler ; 22: AES Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA_IRQHandler [WEAK]
EXPORT GPIO_EVEN_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT USART0_RX_IRQHandler [WEAK]
EXPORT USART0_TX_IRQHandler [WEAK]
EXPORT ACMP0_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT GPIO_ODD_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT USART1_RX_IRQHandler [WEAK]
EXPORT USART1_TX_IRQHandler [WEAK]
EXPORT LESENSE_IRQHandler [WEAK]
EXPORT LEUART0_IRQHandler [WEAK]
EXPORT LETIMER0_IRQHandler [WEAK]
EXPORT PCNT0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT CMU_IRQHandler [WEAK]
EXPORT VCMP_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT MSC_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
DMA_IRQHandler
GPIO_EVEN_IRQHandler
TIMER0_IRQHandler
USART0_RX_IRQHandler
USART0_TX_IRQHandler
ACMP0_IRQHandler
ADC0_IRQHandler
DAC0_IRQHandler
I2C0_IRQHandler
GPIO_ODD_IRQHandler
TIMER1_IRQHandler
USART1_RX_IRQHandler
USART1_TX_IRQHandler
LESENSE_IRQHandler
LEUART0_IRQHandler
LETIMER0_IRQHandler
PCNT0_IRQHandler
RTC_IRQHandler
CMU_IRQHandler
VCMP_IRQHandler
LCD_IRQHandler
MSC_IRQHandler
AES_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

245
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/efm32tg.ld Normal file
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@ -0,0 +1,245 @@
/* Linker script for Energy Micro EFM32G
*
* Version: Sourcery G++ 4.4-180
* Support: https://support.codesourcery.com/GNUToolchain/
*
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
ENTRY(__cs3_reset)
SEARCH_DIR(.)
GROUP(-lgcc -lc -lcs3 -lcs3unhosted)
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 32768
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4096
}
/* These force the linker to search for particular symbols from
* the start of the link process and thus ensure the user's
* overrides are picked up
*/
EXTERN(__cs3_reset __cs3_reset_efm32)
EXTERN(__cs3_start_asm _start)
EXTERN(__cs3_stack)
EXTERN(__cs3_reset)
EXTERN(NMI_Handler)
EXTERN(HardFault_Handler)
EXTERN(MemManage_Handler)
EXTERN(BusFault_Handler)
EXTERN(UsageFault_Handler)
EXTERN(Reserved7_Handler)
EXTERN(Reserved8_Handler)
EXTERN(Reserved9_Handler)
EXTERN(Reserved10_Handler)
EXTERN(SVC_Handler)
EXTERN(DebugMon_Handler)
EXTERN(Reserved13_Handler)
EXTERN(PendSV_Handler)
EXTERN(SysTick_Handler)
EXTERN(DMA_IRQHandler)
EXTERN(GPIO_EVEN_IRQHandler)
EXTERN(TIMER0_IRQHandler)
EXTERN(USART0_RX_IRQHandler)
EXTERN(USART0_TX_IRQHandler)
EXTERN(ACMP0_IRQHandler)
EXTERN(ADC0_IRQHandler)
EXTERN(DAC0_IRQHandler)
EXTERN(I2C0_IRQHandler)
EXTERN(GPIO_ODD_IRQHandler)
EXTERN(TIMER1_IRQHandler)
EXTERN(USART1_RX_IRQHandler)
EXTERN(USART1_TX_IRQHandler)
EXTERN(LESENSE_IRQHandler)
EXTERN(LEUART0_IRQHandler)
EXTERN(LETIMER0_IRQHandler)
EXTERN(PCNT0_IRQHandler)
EXTERN(RTC_IRQHandler)
EXTERN(CMU_IRQHandler)
EXTERN(VCMP_IRQHandler)
EXTERN(LCD_IRQHandler)
EXTERN(MSC_IRQHandler)
EXTERN(AES_IRQHandler)
EXTERN(__cs3_interrupt_vector_efm32g)
EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
/* Provide fall-back values */
PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
SECTIONS
{
.text :
{
CREATE_OBJECT_SYMBOLS
__cs3_region_start_rom = .;
*(.cs3.region-head.rom)
ASSERT (. == __cs3_region_start_rom, ".cs3.region-head.rom not permitted");
__cs3_interrupt_vector = __cs3_interrupt_vector_efm32g;
*(.cs3.interrupt_vector)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cs3_interrupt_vector_efm32g, "No interrupt vector");
PROVIDE(__cs3_reset = __cs3_reset_efm32);
*(.cs3.reset)
PROVIDE(__cs3_start_asm = _start);
*(.text.cs3.init)
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
} >rom
.eh_frame_hdr : ALIGN (4)
{
KEEP (*(.eh_frame_hdr))
} >rom
.eh_frame : ALIGN (4)
{
KEEP (*(.eh_frame))
} >rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >rom
PROVIDE_HIDDEN (__exidx_end = .);
.rodata : ALIGN (4)
{
*(.rodata .rodata.* .gnu.linkonce.r.*)
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
LONG (__cs3_region_start_ram)
LONG (__cs3_region_init_size_ram)
LONG (__cs3_region_zero_size_ram)
__cs3_regions_end = .;
. = ALIGN (8);
*(.rom)
*(.rom.b .bss.rom)
_etext = .;
} >rom
/* __cs3_region_end_rom is deprecated */
__cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
__cs3_region_size_rom = LENGTH(rom);
.data : ALIGN (8)
{
__cs3_region_start_ram = .;
*(.cs3.region-head.ram)
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (8);
*(.ram)
_edata = .;
} >ram AT>rom
.bss :
{
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
*(.ram.b .bss.ram)
_end = .;
__end = .;
} >ram AT>rom
/* __cs3_region_end_ram is deprecated */
__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
__cs3_region_size_ram = LENGTH(ram);
__cs3_region_init_ram = LOADADDR (.data);
__cs3_region_init_size_ram = _edata - ADDR (.data);
__cs3_region_zero_size_ram = _end - _edata;
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to
* the beginning of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

2
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/startup_efm32.s
View File

@ -16,7 +16,7 @@
* they apply.
*
* Energy Micro release version
* @version 1.3.0
* @version 2.0.0
*/
.section ".cs3.interrupt_vector", "ax"
.globl __cs3_interrupt_vector_efm32g

197
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/startup_efm32tg.s Normal file
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@ -0,0 +1,197 @@
/* Vector table for efm32g
*
* Version: Sourcery G++ 4.4-180
* Support: https://support.codesourcery.com/GNUToolchain/
*
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* Energy Micro release version
* @version 2.0.0
*/
.section ".cs3.interrupt_vector", "ax"
.globl __cs3_interrupt_vector_efm32g
.type __cs3_interrupt_vector_efm32g, %object
__cs3_interrupt_vector_efm32g:
.long __cs3_stack
.long __cs3_reset
.long NMI_Handler
.long HardFault_Handler
.long MemManage_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long Reserved7_Handler
.long Reserved8_Handler
.long Reserved9_Handler
.long Reserved10_Handler
.long SVC_Handler
.long DebugMon_Handler
.long Reserved13_Handler
.long PendSV_Handler
.long SysTick_Handler
.long DMA_IRQHandler
.long GPIO_EVEN_IRQHandler
.long TIMER0_IRQHandler
.long USART0_RX_IRQHandler
.long USART0_TX_IRQHandler
.long ACMP0_IRQHandler
.long ADC0_IRQHandler
.long DAC0_IRQHandler
.long I2C0_IRQHandler
.long GPIO_ODD_IRQHandler
.long TIMER1_IRQHandler
.long USART1_RX_IRQHandler
.long USART1_TX_IRQHandler
.long LESENSE_IRQHandler
.long LEUART0_IRQHandler
.long LETIMER0_IRQHandler
.long PCNT0_IRQHandler
.long RTC_IRQHandler
.long CMU_IRQHandler
.long VCMP_IRQHandler
.long LCD_IRQHandler
.long MSC_IRQHandler
.long AES_IRQHandler
.size __cs3_interrupt_vector_efm32g, . - __cs3_interrupt_vector_efm32g
.thumb
.thumb_func
.section .cs3.reset,"ax",%progbits
.globl __cs3_reset_efm32
.type __cs3_reset_efm32, %function
__cs3_reset_efm32:
/* jump to common start code */
ldr r0,=__cs3_start_asm
bx r0
.pool
.size __cs3_reset_efm32,.-__cs3_reset_efm32
.thumb
.globl _IRQHandlerinterrupt
.type _IRQHandlerinterrupt, %function
_IRQHandlerinterrupt:
b .
.size _IRQHandlerinterrupt, . - _IRQHandlerinterrupt
.weak NMI_Handler
.globl NMI_Handler
.set NMI_Handler, _IRQHandlerinterrupt
.weak HardFault_Handler
.globl HardFault_Handler
.set HardFault_Handler, _IRQHandlerinterrupt
.weak MemManage_Handler
.globl MemManage_Handler
.set MemManage_Handler, _IRQHandlerinterrupt
.weak BusFault_Handler
.globl BusFault_Handler
.set BusFault_Handler, _IRQHandlerinterrupt
.weak UsageFault_Handler
.globl UsageFault_Handler
.set UsageFault_Handler, _IRQHandlerinterrupt
.weak Reserved7_Handler
.globl Reserved7_Handler
.set Reserved7_Handler, _IRQHandlerinterrupt
.weak Reserved8_Handler
.globl Reserved8_Handler
.set Reserved8_Handler, _IRQHandlerinterrupt
.weak Reserved9_Handler
.globl Reserved9_Handler
.set Reserved9_Handler, _IRQHandlerinterrupt
.weak Reserved10_Handler
.globl Reserved10_Handler
.set Reserved10_Handler, _IRQHandlerinterrupt
.weak SVC_Handler
.globl SVC_Handler
.set SVC_Handler, _IRQHandlerinterrupt
.weak DebugMon_Handler
.globl DebugMon_Handler
.set DebugMon_Handler, _IRQHandlerinterrupt
.weak Reserved13_Handler
.globl Reserved13_Handler
.set Reserved13_Handler, _IRQHandlerinterrupt
.weak PendSV_Handler
.globl PendSV_Handler
.set PendSV_Handler, _IRQHandlerinterrupt
.weak SysTick_Handler
.globl SysTick_Handler
.set SysTick_Handler, _IRQHandlerinterrupt
.weak DMA_IRQHandler
.globl DMA_IRQHandler
.set DMA_IRQHandler, _IRQHandlerinterrupt
.weak GPIO_EVEN_IRQHandler
.globl GPIO_EVEN_IRQHandler
.set GPIO_EVEN_IRQHandler, _IRQHandlerinterrupt
.weak TIMER0_IRQHandler
.globl TIMER0_IRQHandler
.set TIMER0_IRQHandler, _IRQHandlerinterrupt
.weak USART0_RX_IRQHandler
.globl USART0_RX_IRQHandler
.set USART0_RX_IRQHandler, _IRQHandlerinterrupt
.weak USART0_TX_IRQHandler
.globl USART0_TX_IRQHandler
.set USART0_TX_IRQHandler, _IRQHandlerinterrupt
.weak ACMP0_IRQHandler
.globl ACMP0_IRQHandler
.set ACMP0_IRQHandler, _IRQHandlerinterrupt
.weak ADC0_IRQHandler
.globl ADC0_IRQHandler
.set ADC0_IRQHandler, _IRQHandlerinterrupt
.weak DAC0_IRQHandler
.globl DAC0_IRQHandler
.set DAC0_IRQHandler, _IRQHandlerinterrupt
.weak I2C0_IRQHandler
.globl I2C0_IRQHandler
.set I2C0_IRQHandler, _IRQHandlerinterrupt
.weak GPIO_ODD_IRQHandler
.globl GPIO_ODD_IRQHandler
.set GPIO_ODD_IRQHandler, _IRQHandlerinterrupt
.weak TIMER1_IRQHandler
.globl TIMER1_IRQHandler
.set TIMER1_IRQHandler, _IRQHandlerinterrupt
.weak USART1_RX_IRQHandler
.globl USART1_RX_IRQHandler
.set USART1_RX_IRQHandler, _IRQHandlerinterrupt
.weak USART1_TX_IRQHandler
.globl USART1_TX_IRQHandler
.set USART1_TX_IRQHandler, _IRQHandlerinterrupt
.weak LESENSE_IRQHandler
.globl LESENSE_IRQHandler
.set LESENSE_IRQHandler, _IRQHandlerinterrupt
.weak LEUART0_IRQHandler
.globl LEUART0_IRQHandler
.set LEUART0_IRQHandler, _IRQHandlerinterrupt
.weak LETIMER0_IRQHandler
.globl LETIMER0_IRQHandler
.set LETIMER0_IRQHandler, _IRQHandlerinterrupt
.weak PCNT0_IRQHandler
.globl PCNT0_IRQHandler
.set PCNT0_IRQHandler, _IRQHandlerinterrupt
.weak RTC_IRQHandler
.globl RTC_IRQHandler
.set RTC_IRQHandler, _IRQHandlerinterrupt
.weak CMU_IRQHandler
.globl CMU_IRQHandler
.set CMU_IRQHandler, _IRQHandlerinterrupt
.weak VCMP_IRQHandler
.globl VCMP_IRQHandler
.set VCMP_IRQHandler, _IRQHandlerinterrupt
.weak LCD_IRQHandler
.globl LCD_IRQHandler
.set LCD_IRQHandler, _IRQHandlerinterrupt
.weak MSC_IRQHandler
.globl MSC_IRQHandler
.set MSC_IRQHandler, _IRQHandlerinterrupt
.weak AES_IRQHandler
.globl AES_IRQHandler
.set AES_IRQHandler, _IRQHandlerinterrupt

8
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32.c
View File

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file
* @brief CMSIS Compatible EFM32 startup file in Cfor IAR EWARM
* @brief CMSIS Compatible EFM32 startup file in C for IAR EWARM
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
@ -238,7 +238,7 @@ __weak void AES_IRQHandler(void)
}
/* With IAR, the CSTACK is defined via project options settings */
/* With IAR, the CSTACK size is defined via project options settings */
#pragma location = ".intvec"
const void * const __vector_table[]= {
&CSTACK$$Limit,

4
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32.s
View File

@ -2,8 +2,8 @@
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro 'EFM32G' Device Series
; * @version 1.3.0
; * @date: 7. September 2010
; * @version 2.0.0
; * @date: January 2011
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.

249
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32tg.c Normal file
View File

@ -0,0 +1,249 @@
/**************************************************************************//**
* @file
* @brief CMSIS Compatible EFM32 startup file in Cfor IAR EWARM
* @author Energy Micro AS
* @version 2.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#pragma language=extended
#pragma segment="CSTACK"
/* IAR start function */
extern void __iar_program_start(void);
/* CMSIS init function */
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{
SystemInit();
__iar_program_start();
}
__weak void NMI_Handler(void)
{
while(1);
}
__weak void HardFault_Handler(void)
{
while(1);
}
__weak void MemManage_Handler(void)
{
while(1);
}
__weak void BusFault_Handler(void)
{
while(1);
}
__weak void UsageFault_Handler(void)
{
while(1);
}
__weak void SVC_Handler(void)
{
while(1);
}
__weak void DebugMon_Handler(void)
{
while(1);
}
__weak void PendSV_Handler(void)
{
while(1);
}
__weak void SysTick_Handler(void)
{
while(1);
}
__weak void DMA_IRQHandler(void)
{
while(1);
}
__weak void GPIO_EVEN_IRQHandler(void)
{
while(1);
}
__weak void TIMER0_IRQHandler(void)
{
while(1);
}
__weak void USART0_RX_IRQHandler(void)
{
while(1);
}
__weak void USART0_TX_IRQHandler(void)
{
while(1);
}
__weak void ACMP0_IRQHandler(void)
{
while(1);
}
__weak void ADC0_IRQHandler(void)
{
while(1);
}
__weak void DAC0_IRQHandler(void)
{
while(1);
}
__weak void I2C0_IRQHandler(void)
{
while(1);
}
__weak void GPIO_ODD_IRQHandler(void)
{
while(1);
}
__weak void TIMER1_IRQHandler(void)
{
while(1);
}
__weak void USART1_RX_IRQHandler(void)
{
while(1);
}
__weak void USART1_TX_IRQHandler(void)
{
while(1);
}
__weak void LESENSE_IRQHandler(void)
{
while(1);
}
__weak void LEUART0_IRQHandler(void)
{
while(1);
}
__weak void LETIMER0_IRQHandler(void)
{
while(1);
}
__weak void PCNT0_IRQHandler(void)
{
while(1);
}
__weak void RTC_IRQHandler(void)
{
while(1);
}
__weak void CMU_IRQHandler(void)
{
while(1);
}
__weak void VCMP_IRQHandler(void)
{
while(1);
}
__weak void LCD_IRQHandler(void)
{
while(1);
}
__weak void MSC_IRQHandler(void)
{
while(1);
}
__weak void AES_IRQHandler(void)
{
while(1);
}
/* With IAR, the CSTACK is defined via project options settings */
#pragma location = ".intvec"
const void * const __vector_table[]= {
&CSTACK$$Limit,
(void *) Reset_Handler, /* 1 - Reset (start instruction) */
(void *) NMI_Handler, /* 2 - NMI */
(void *) HardFault_Handler, /* 3 - HardFault */
(void *) MemManage_Handler,
(void *) BusFault_Handler,
(void *) UsageFault_Handler,
(void *) 0,
(void *) 0,
(void *) 0,
(void *) 0,
(void *) SVC_Handler,
(void *) DebugMon_Handler,
(void *) 0,
(void *) PendSV_Handler,
(void *) SysTick_Handler,
(void *) DMA_IRQHandler, /* 0 - DMA */
(void *) GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */
(void *) TIMER0_IRQHandler, /* 2 - TIMER0 */
(void *) USART0_RX_IRQHandler, /* 3 - USART0_RX */
(void *) USART0_TX_IRQHandler, /* 4 - USART0_TX */
(void *) ACMP0_IRQHandler, /* 5 - ACMP0 */
(void *) ADC0_IRQHandler, /* 6 - ADC0 */
(void *) DAC0_IRQHandler, /* 7 - DAC0 */
(void *) I2C0_IRQHandler, /* 8 - I2C0 */
(void *) GPIO_ODD_IRQHandler, /* 9 - GPIO_ODD */
(void *) TIMER1_IRQHandler, /* 10 - TIMER1 */
(void *) USART1_RX_IRQHandler, /* 11 - USART1_RX */
(void *) USART1_TX_IRQHandler, /* 12 - USART1_TX */
(void *) LESENSE_IRQHandler, /* 13 - LESENSE */
(void *) LEUART0_IRQHandler, /* 14 - LEUART0 */
(void *) LETIMER0_IRQHandler, /* 15 - LETIMER0 */
(void *) PCNT0_IRQHandler, /* 16 - PCNT0 */
(void *) RTC_IRQHandler, /* 17 - RTC */
(void *) CMU_IRQHandler, /* 18 - CMU */
(void *) VCMP_IRQHandler, /* 19 - VCMP */
(void *) LCD_IRQHandler, /* 20 - LCD */
(void *) MSC_IRQHandler, /* 21 - MSC */
(void *) AES_IRQHandler, /* 22 - AES */
};

286
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32tg.s Normal file
View File

@ -0,0 +1,286 @@
;/*************************************************************************//**
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro 'EFM32G' Device Series
; * @version 2.0.0
; * @date: January 2011
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM wtih at least a 128 byte
; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
;
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
DCD USART1_RX_IRQHandler ; 11: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 12: USART1_TX Interrupt
DCD LESENSE_IRQHandler ; 13: LESENSE Interrupt
DCD LEUART0_IRQHandler ; 14: LEUART0 Interrupt
DCD LETIMER0_IRQHandler ; 15: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 16: PCNT0 Interrupt
DCD RTC_IRQHandler ; 17: RTC Interrupt
DCD CMU_IRQHandler ; 18: CMU Interrupt
DCD VCMP_IRQHandler ; 19: VCMP Interrupt
DCD LCD_IRQHandler ; 20: LCD Interrupt
DCD MSC_IRQHandler ; 21: MSC Interrupt
DCD AES_IRQHandler ; 22: AES Interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
; EFM32G specific interrupt handlers
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK GPIO_EVEN_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_EVEN_IRQHandler
B GPIO_EVEN_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK USART0_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_RX_IRQHandler
B USART0_RX_IRQHandler
PUBWEAK USART0_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_TX_IRQHandler
B USART0_TX_IRQHandler
PUBWEAK ACMP0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACMP0_IRQHandler
B ACMP0_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK DAC0_IRQHandler
SECTION .text:CODE:REORDER(1)
DAC0_IRQHandler
B DAC0_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK GPIO_ODD_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_ODD_IRQHandler
B GPIO_ODD_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK USART1_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_RX_IRQHandler
B USART1_RX_IRQHandler
PUBWEAK USART1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_TX_IRQHandler
B USART1_TX_IRQHandler
PUBWEAK LESENSE_IRQHandler
SECTION .text:CODE:REORDER(1)
LESENSE_IRQHandler
B LESENSE_IRQHandler
PUBWEAK LEUART0_IRQHandler
SECTION .text:CODE:REORDER(1)
LEUART0_IRQHandler
B LEUART0_IRQHandler
PUBWEAK LETIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
LETIMER0_IRQHandler
B LETIMER0_IRQHandler
PUBWEAK PCNT0_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT0_IRQHandler
B PCNT0_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK CMU_IRQHandler
SECTION .text:CODE:REORDER(1)
CMU_IRQHandler
B CMU_IRQHandler
PUBWEAK VCMP_IRQHandler
SECTION .text:CODE:REORDER(1)
VCMP_IRQHandler
B VCMP_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK MSC_IRQHandler
SECTION .text:CODE:REORDER(1)
MSC_IRQHandler
B MSC_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
END

28
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c
View File

@ -2,10 +2,10 @@
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
@ -34,7 +34,8 @@
******************************************************************************/
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFM32_LFRCO_FREQ (32768)
#define EFM32_LFRCO_FREQ (32768UL)
#define EFM32_ULFRCO_FREQ (1000UL)
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
@ -49,7 +50,7 @@
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#define EFM32_HFXO_FREQ (32000000)
#define EFM32_HFXO_FREQ (32000000UL)
#endif
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
@ -66,7 +67,7 @@ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = 32768;
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -289,6 +290,23 @@ uint32_t SystemLFRCOClockGet(void)
}
/**************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* ULFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFM32_ULFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.

146
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h
View File

@ -2,10 +2,10 @@
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
@ -45,6 +45,138 @@ extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
***************************** PROTOTYPES **********************************
******************************************************************************/
/* Interrupt routines - prototypes */
#if defined(_EFM32_GECKO_FAMILY)
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
void USART0_RX_IRQHandler(void);
void USART0_TX_IRQHandler(void);
void ACMP0_IRQHandler(void);
void ADC0_IRQHandler(void);
void DAC0_IRQHandler(void);
void I2C0_IRQHandler(void);
void GPIO_ODD_IRQHandler(void);
void TIMER1_IRQHandler(void);
void TIMER2_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void USART2_RX_IRQHandler(void);
void USART2_TX_IRQHandler(void);
void UART0_RX_IRQHandler(void);
void UART0_TX_IRQHandler(void);
void LEUART0_IRQHandler(void);
void LEUART1_IRQHandler(void);
void LETIMER0_IRQHandler(void);
void PCNT0_IRQHandler(void);
void PCNT1_IRQHandler(void);
void PCNT2_IRQHandler(void);
void RTC_IRQHandler(void);
void CMU_IRQHandler(void);
void VCMP_IRQHandler(void);
void LCD_IRQHandler(void);
void MSC_IRQHandler(void);
void AES_IRQHandler(void);
#endif
#if defined(_EFM32_TINY_FAMILY)
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
void USART0_RX_IRQHandler(void);
void USART0_TX_IRQHandler(void);
void ACMP0_IRQHandler(void);
void ADC0_IRQHandler(void);
void DAC0_IRQHandler(void);
void I2C0_IRQHandler(void);
void GPIO_ODD_IRQHandler(void);
void TIMER1_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void LESENSE_IRQHandler(void);
void LEUART0_IRQHandler(void);
void LETIMER0_IRQHandler(void);
void PCNT0_IRQHandler(void);
void RTC_IRQHandler(void);
void CMU_IRQHandler(void);
void VCMP_IRQHandler(void);
void LCD_IRQHandler(void);
void MSC_IRQHandler(void);
void AES_IRQHandler(void);
#endif
#if defined(_EFM32_GIANT_FAMILY)
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
void USART0_RX_IRQHandler(void);
void USART0_TX_IRQHandler(void);
void USB_IRQHandler(void);
void ACMP0_IRQHandler(void);
void ADC0_IRQHandler(void);
void DAC0_IRQHandler(void);
void I2C0_IRQHandler(void);
void I2C1_IRQHandler(void);
void GPIO_ODD_IRQHandler(void);
void TIMER1_IRQHandler(void);
void TIMER2_IRQHandler(void);
void TIMER3_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void LESENSE_IRQHandler(void);
void USART2_RX_IRQHandler(void);
void USART2_TX_IRQHandler(void);
void UART0_RX_IRQHandler(void);
void UART0_TX_IRQHandler(void);
void UART1_RX_IRQHandler(void);
void UART1_TX_IRQHandler(void);
void LEUART0_IRQHandler(void);
void LEUART1_IRQHandler(void);
void LETIMER0_IRQHandler(void);
void PCNT0_IRQHandler(void);
void PCNT1_IRQHandler(void);
void PCNT2_IRQHandler(void);
void RTC_IRQHandler(void);
void BURTC_IRQHandler(void);
void CMU_IRQHandler(void);
void VCMP_IRQHandler(void);
void LCD_IRQHandler(void);
void MSC_IRQHandler(void);
void AES_IRQHandler(void);
void EBI_IRQHandler(void);
void EMU_IRQHandler(void);
#endif
uint32_t SystemCoreClockGet(void);
/**************************************************************************//**
@ -66,15 +198,13 @@ static __INLINE void SystemCoreClockUpdate(void)
SystemCoreClockGet();
}
uint32_t SystemHFClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
void SystemInit(void);
uint32_t SystemHFClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
uint32_t SystemLFRCOClockGet(void);
uint32_t SystemULFRCOClockGet(void);
uint32_t SystemLFXOClockGet(void);
void SystemLFXOClockSet(uint32_t freq);

15
bsp/efm32/Libraries/SConscript
View File

@ -34,11 +34,24 @@ efm32lib/src/efm32_vcmp.c
efm32lib/src/efm32_wdog.c
""")
# starupt scripts for each EFM32 family
#startup_scripts = {}
#startup_scripts['Gecko'] = 'startup_efm32.s'
#startup_scripts['TinyGecko'] = 'startup_efm32tg.s'
# linker scripts for each EFM32 family
#linker_scripts = {}
#linker_scripts['Gecko'] = 'efm32g.ld'
#linker_scripts['TinyGecko'] = 'efm32tg.ld'
# add startup script
#src = src + ['CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/' + startup_scripts[rtconfig.EFM32_FAMILY]]
path = [RTT_ROOT + '/bsp/efm32/Libraries/efm32lib/inc',
RTT_ROOT + '/bsp/efm32/Libraries/CMSIS/CM3/CoreSupport',
RTT_ROOT + '/bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.EFM32_TYPE]
group = DefineGroup('EFM32_StdPeriph', src, depend = [''], CPPPATH = path)
group = DefineGroup('EFM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

130
bsp/efm32/Libraries/efm32lib/inc/efm32_acmp.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Analog Comparator (ACMP) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -135,24 +135,24 @@ typedef enum
/** Capsense initialization structure. */
typedef struct
{
/** Full bias current. See section 23.3.2 in the reference manual
* for details. */
bool fullBias;
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
/** Half bias current. See section 23.3.2 in the reference manual
* for details. */
bool halfBias;
/** Half bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool halfBias;
/** Bias current. See section 23.3.2 in the reference manual for
* details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Bias current. See the ACMP chapter about bias and response time in the
* reference manual for details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Warmup time. This is measured in HFPERCLK cycles and should be
* about 10us in wall clock time. */
ACMP_WarmTime_TypeDef warmTime;
ACMP_WarmTime_TypeDef warmTime;
/** Hysteresis level */
ACMP_HysteresisLevel_TypeDef hysteresisLevel;
ACMP_HysteresisLevel_TypeDef hysteresisLevel;
/** Resistor used in the capacative sensing circuit. For values see
* your device datasheet. */
@ -160,45 +160,49 @@ typedef struct
/** Low power reference enabled. This setting, if enabled, reduces the
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
uint32_t vddLevel;
/** If true, ACMP is being enabled after configuration. */
bool enable;
} ACMP_CapsenseInit_TypeDef;
/** Default config for capacitive sense on the STK */
#define ACMP_CAPSENSE_STK_DEFAULT \
/** Default config for capacitive sense mode initialization. */
#define ACMP_CAPSENSE_INIT_DEFAULT \
{ false, /* fullBias */ \
false, /* halfBias */ \
0xF, /* biasProg */ \
0x7, /* biasProg */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D /* VDD level */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
/** ACMP initialization structure. */
typedef struct
{
/** Full bias current. See section 23.3.2 in the reference manual
* for details. */
bool fullBias;
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
/** Half bias current. See section 23.3.2 in the reference manual
* for details. */
bool halfBias;
/** Half bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool halfBias;
/** Bias current. See section 23.3.2 in the reference manual for
* details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Bias current. See the ACMP chapter about bias and response time in the
* reference manual for details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Enable setting the interrupt flag on falling edge */
bool interruptOnFallingEdge;
bool interruptOnFallingEdge;
/** Enable setting the interrupt flag on rising edge */
bool interruptOnRisingEdge;
bool interruptOnRisingEdge;
/** Warmup time. This is measured in HFPERCLK cycles and should be
* about 10us in wall clock time. */
@ -212,13 +216,32 @@ typedef struct
/** Low power reference enabled. This setting, if enabled, reduces the
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
uint32_t vddLevel;
/** If true, ACMP is being enabled after configuration. */
bool enable;
} ACMP_Init_TypeDef;
/** Default config for ACMP regular initialization. */
#define ACMP_INIT_DEFAULT \
{ false, /* fullBias */ \
false, /* halfBias */ \
0x7, /* biasProg */ \
false, /* No interrupt on falling edge. */ \
false, /* No interrupt on rising edge. */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
false, /* Disabled emitting inactive value during warmup. */ \
false, /* low power reference */ \
0x3D, /* VDD level */ \
true /* Enable after init. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -227,7 +250,6 @@ void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init
void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel);
void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel);
void ACMP_Disable(ACMP_TypeDef *acmp);
void ACMP_DisableNoReset(ACMP_TypeDef *acmp);
void ACMP_Enable(ACMP_TypeDef *acmp);
void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert);
void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init);
@ -241,7 +263,7 @@ void ACMP_Reset(ACMP_TypeDef *acmp);
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* Pending ACMP interrupt source to clear. Use a logical OR combination
* Pending ACMP interrupt source to clear. Use a bitwise logic OR combination
* of valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags)
@ -258,7 +280,7 @@ static __INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags)
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to disable. Use a logical OR combination of
* ACMP interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags)
@ -280,7 +302,7 @@ static __INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags)
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to enable. Use a logical OR combination of
* ACMP interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags)
@ -300,7 +322,7 @@ static __INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags)
* Pointer to ACMP peripheral register block.
*
* @return
* ACMP interrupt sources pending. A logical OR combination of valid
* ACMP interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
@ -309,6 +331,38 @@ static __INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
}
/***************************************************************************//**
* @brief
* Get enabled and pending ACMP interrupt flags.
* Useful for handling more interrupt sources in the same interrupt handler.
*
* @param[in] usart
* Pointer to ACMP peripheral register block.
*
* @note
* Interrupt flags are not cleared by the use of this function.
*
* @return
* Pending and enabled ACMP interrupt sources.
* The return value is the bitwise AND combination of
* - the OR combination of enabled interrupt sources in ACMPx_IEN_nnn
* register (ACMPx_IEN_nnn) and
* - the OR combination of valid interrupt flags of the ACMP module
* (ACMPx_IF_nnn).
******************************************************************************/
static __INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp)
{
uint32_t tmp;
/* Store ACMPx->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
tmp = acmp->IEN;
/* Bitwise AND of pending and enabled interrupts */
return acmp->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending ACMP interrupts from SW.
@ -317,8 +371,8 @@ static __INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to set to pending. Use a logical OR combination
* of valid interrupt flags for the ACMP module (ACMP_IF_nnn).
* ACMP interrupt sources to set to pending. Use a bitwise logic OR
* combination of valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntSet(ACMP_TypeDef *acmp, uint32_t flags)
{

46
bsp/efm32/Libraries/efm32lib/inc/efm32_adc.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Analog to Digital Converter (ADC) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -261,13 +261,13 @@ typedef struct
* is at least 1 us. See ADC_TimebaseCalcDefault() for a way to obtain
* a suggested timebase of at least 1 us.
*/
uint8_t timebase;
uint8_t timebase;
/** Clock division factor N, ADC clock = HFPERCLK / (N + 1). */
uint8_t prescale;
uint8_t prescale;
/** Enable/disable conversion tailgating. */
bool tailgate;
bool tailgate;
} ADC_Init_TypeDef;
/** Default config for ADC init structure. */
@ -297,10 +297,10 @@ typedef struct
* Sample reference selection. Notice that for external references, the
* ADC calibration register must be set explicitly.
*/
ADC_Ref_TypeDef reference;
ADC_Ref_TypeDef reference;
/** Sample resolution. */
ADC_Res_TypeDef resolution;
ADC_Res_TypeDef resolution;
/**
* Input scan selection. If single ended (@p diff is false), use logical
@ -308,19 +308,19 @@ typedef struct
* (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy
* defines. (Notice underscore prefix for defines used.)
*/
uint32_t input;
uint32_t input;
/** Select if single ended or differential input. */
bool diff;
bool diff;
/** Peripheral reflex system trigger enable. */
bool prsEnable;
bool prsEnable;
/** Select if left adjustment should be done. */
bool leftAdjust;
bool leftAdjust;
/** Select if continuous conversion until explicit stop. */
bool rep;
bool rep;
} ADC_InitScan_TypeDef;
/** Default config for ADC scan init structure. */
@ -344,19 +344,19 @@ typedef struct
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
*/
ADC_PRSSEL_TypeDef prsSel;
ADC_PRSSEL_TypeDef prsSel;
/** Acquisition time (in ADC clock cycles). */
ADC_AcqTime_TypeDef acqTime;
ADC_AcqTime_TypeDef acqTime;
/**
* Sample reference selection. Notice that for external references, the
* ADC calibration register must be set explicitly.
*/
ADC_Ref_TypeDef reference;
ADC_Ref_TypeDef reference;
/** Sample resolution. */
ADC_Res_TypeDef resolution;
ADC_Res_TypeDef resolution;
/**
* Sample input selection, use single ended or differential input according
@ -442,8 +442,8 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
* Pointer to ADC peripheral register block.
*
* @param[in] flags
* Pending ADC interrupt source to clear. Use a logical OR combination of
* valid interrupt flags for the ADC module (ADC_IF_nnn).
* Pending ADC interrupt source to clear. Use a bitwise logic OR combination
* of valid interrupt flags for the ADC module (ADC_IF_nnn).
******************************************************************************/
static __INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
{
@ -459,7 +459,7 @@ static __INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
* Pointer to ADC peripheral register block.
*
* @param[in] flags
* ADC interrupt sources to disable. Use a logical OR combination of
* ADC interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the ADC module (ADC_IF_nnn).
******************************************************************************/
static __INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
@ -481,7 +481,7 @@ static __INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
* Pointer to ADC peripheral register block.
*
* @param[in] flags
* ADC interrupt sources to enable. Use a logical OR combination of
* ADC interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the ADC module (ADC_IF_nnn).
******************************************************************************/
static __INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
@ -501,7 +501,7 @@ static __INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
* Pointer to ADC peripheral register block.
*
* @return
* ADC interrupt sources pending. A logical OR combination of valid
* ADC interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the ADC module (ADC_IF_nnn).
******************************************************************************/
static __INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
@ -518,8 +518,8 @@ static __INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
* Pointer to ADC peripheral register block.
*
* @param[in] flags
* ADC interrupt sources to set to pending. Use a logical OR combination of
* valid interrupt flags for the ADC module (ADC_IF_nnn).
* ADC interrupt sources to set to pending. Use a bitwise logic OR combination
* of valid interrupt flags for the ADC module (ADC_IF_nnn).
******************************************************************************/
static __INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags)
{
@ -541,7 +541,7 @@ uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
******************************************************************************/
static __INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd)
{
adc->CMD = (uint32_t) cmd;
adc->CMD = (uint32_t)cmd;
}
void ADC_Reset(ADC_TypeDef *adc);

14
bsp/efm32/Libraries/efm32lib/inc/efm32_aes.h
View File

@ -3,7 +3,7 @@
* @brief Advanced encryption standard (AES) accelerator peripheral API for
* EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -130,7 +130,7 @@ void AES_ECB256(uint8_t *out,
* Clear one or more pending AES interrupts.
*
* @param[in] flags
* Pending AES interrupt source to clear. Use a logical OR combination of
* Pending AES interrupt source to clear. Use a bitwise logic OR combination of
* valid interrupt flags for the AES module (AES_IF_nnn).
******************************************************************************/
static __INLINE void AES_IntClear(uint32_t flags)
@ -144,7 +144,7 @@ static __INLINE void AES_IntClear(uint32_t flags)
* Disable one or more AES interrupts.
*
* @param[in] flags
* AES interrupt sources to disable. Use a logical OR combination of
* AES interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the AES module (AES_IF_nnn).
******************************************************************************/
static __INLINE void AES_IntDisable(uint32_t flags)
@ -163,7 +163,7 @@ static __INLINE void AES_IntDisable(uint32_t flags)
* if such a pending interrupt should be ignored.
*
* @param[in] flags
* AES interrupt sources to enable. Use a logical OR combination of
* AES interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the AES module (AES_IF_nnn).
******************************************************************************/
static __INLINE void AES_IntEnable(uint32_t flags)
@ -180,7 +180,7 @@ static __INLINE void AES_IntEnable(uint32_t flags)
* The event bits are not cleared by the use of this function.
*
* @return
* AES interrupt sources pending. A logical OR combination of valid
* AES interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the AES module (AES_IF_nnn).
******************************************************************************/
static __INLINE uint32_t AES_IntGet(void)
@ -194,8 +194,8 @@ static __INLINE uint32_t AES_IntGet(void)
* Set one or more pending AES interrupts from SW.
*
* @param[in] flags
* AES interrupt sources to set to pending. Use a logical OR combination of
* valid interrupt flags for the AES module (AES_IF_nnn).
* AES interrupt sources to set to pending. Use a bitwise logic OR combination
* of valid interrupt flags for the AES module (AES_IF_nnn).
******************************************************************************/
static __INLINE void AES_IntSet(uint32_t flags)
{

6
bsp/efm32/Libraries/efm32lib/inc/efm32_assert.h
View File

@ -2,7 +2,7 @@
* @file
* @brief EFM32 peripheral API "assert" implementation.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*
* @details
* By default, EFM32 library assert usage is not included in order to reduce
@ -57,11 +57,11 @@ extern "C" {
/* Due to footprint considerations, we only pass file name and line number, */
/* not the assert expression (nor function name (C99)) */
void assertEFM(const char *file, int line);
#define EFM_ASSERT(expr) ((expr) ? ((void) 0) : assertEFM(__FILE__, __LINE__))
#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__))
#else
#define EFM_ASSERT(expr) ((void) 0)
#define EFM_ASSERT(expr) ((void)0)
#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */

18
bsp/efm32/Libraries/efm32lib/inc/efm32_bitband.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file
* @brief EFM32 bitband utilities.
* @brief Bitband Peripheral API for EFM32
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -41,7 +41,7 @@ extern "C" {
/***************************************************************************//**
* @addtogroup BITBAND
* @brief EFM32 bit-band utilities.
* @brief BITBAND Peripheral API for EFM32
* @{
******************************************************************************/
@ -61,12 +61,12 @@ extern "C" {
* @param[in] val Value to set bit to, 0 or 1.
******************************************************************************/
static __INLINE void BITBAND_Peripheral(volatile uint32_t *addr,
uint32_t bit,
uint32_t val)
uint32_t bit,
uint32_t val)
{
uint32_t tmp = BITBAND_PER_BASE + (((uint32_t) addr - PER_MEM_BASE) * 32) + (bit * 4);
uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
*((volatile uint32_t *) tmp) = (uint32_t) val;
*((volatile uint32_t *)tmp) = (uint32_t)val;
}
@ -87,9 +87,9 @@ static __INLINE void BITBAND_Peripheral(volatile uint32_t *addr,
******************************************************************************/
static __INLINE void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
{
uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t) addr - RAM_MEM_BASE) * 32) + (bit * 4);
uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) * 32) + (bit * 4);
*((volatile uint32_t *) tmp) = (uint32_t) val;
*((volatile uint32_t *)tmp) = (uint32_t)val;
}

46
bsp/efm32/Libraries/efm32lib/inc/efm32_chip.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file
* @brief Chip initialization, SW workarounds for chip errata issues
* @brief Chip Initialization API for EFM32
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -42,6 +42,7 @@ extern "C" {
/***************************************************************************//**
* @addtogroup CHIP
* @brief Chip Initialization API for EFM32
* @{
******************************************************************************/
@ -49,7 +50,7 @@ extern "C" {
* @brief
* Chip initialization routine for revision errata workarounds
*
* This init function will configure the EFM32 device to a state where it is
* This init function will configure the EFM32 device to a state where it is
* as similar as later revisions as possible, to improve software compatibility
* with newer parts. See the device specific errata for details.
*****************************************************************************/
@ -63,28 +64,28 @@ static __INLINE void CHIP_Init(void)
/* Engineering Sample calibration setup */
if ((rev >> 24) == 0)
{
reg = (volatile uint32_t *) 0x400CA00C;
reg = (volatile uint32_t *)0x400CA00C;
*reg &= ~(0x70UL);
/* DREG */
reg = (volatile uint32_t *) 0x400C6020;
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0xE0000000UL);
*reg |= ~(7UL << 25);
}
if ((rev >> 24) <= 3)
{
/* DREG */
reg = (volatile uint32_t *) 0x400C6020;
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0x00001F80UL);
/* Update CMU reset values */
reg = (volatile uint32_t *) 0x400C8040;
reg = (volatile uint32_t *)0x400C8040;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8044;
reg = (volatile uint32_t *)0x400C8044;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8058;
reg = (volatile uint32_t *)0x400C8058;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8060;
reg = (volatile uint32_t *)0x400C8060;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8078;
reg = (volatile uint32_t *)0x400C8078;
*reg = 0;
}
@ -95,7 +96,7 @@ static __INLINE void CHIP_Init(void)
/* to work. This will be fixed in later chip revisions, so only do for rev A. */
if (chipRev.minor == 00)
{
reg = (volatile uint32_t *) 0x400C8040;
reg = (volatile uint32_t *)0x400C8040;
*reg |= 0x2;
}
@ -104,19 +105,19 @@ static __INLINE void CHIP_Init(void)
/* later chip revisions, so only do for rev A+B. */
if (chipRev.minor <= 0x01)
{
reg = (volatile uint32_t *) 0x400C8044;
reg = (volatile uint32_t *)0x400C8044;
*reg |= 0x1;
}
}
/* Ensure correct ADC/DAC calibration value */
rev = *(volatile uint32_t *) 0x0FE081F0;
if ( rev < 0x4C8ABA00 )
rev = *(volatile uint32_t *)0x0FE081F0;
if (rev < 0x4C8ABA00)
{
uint32_t cal;
/* Enable ADC/DAC clocks */
reg = (volatile uint32_t *) 0x400C8044UL;
*reg |= (1<<14|1<<11);
reg = (volatile uint32_t *)0x400C8044UL;
*reg |= (1 << 14 | 1 << 11);
/* Retrive calibration values */
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
@ -132,19 +133,18 @@ static __INLINE void CHIP_Init(void)
0) << 0;
/* ADC0->CAL = 1.25 reference */
reg = (volatile uint32_t *) 0x40002034UL;
reg = (volatile uint32_t *)0x40002034UL;
*reg = cal;
/* DAC0->CAL = 1.25 reference */
reg = (volatile uint32_t *) (0x4000402CUL);
cal = *(volatile uint32_t *) 0x0FE081C8UL;
reg = (volatile uint32_t *)(0x4000402CUL);
cal = *(volatile uint32_t *)0x0FE081C8UL;
*reg = cal;
/* Turn off ADC/DAC clocks */
reg = (volatile uint32_t *) 0x400C8044UL;
*reg &= ~(1<<14|1<<11);
reg = (volatile uint32_t *)0x400C8044UL;
*reg &= ~(1 << 14 | 1 << 11);
}
}
/** @} (end addtogroup SYSTEM) */

216
bsp/efm32/Libraries/efm32lib/inc/efm32_cmu.h
View File

@ -2,10 +2,10 @@
* @file
* @brief Clock management unit (CMU) API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
@ -30,6 +30,7 @@
#include <stdbool.h>
#include "efm32.h"
#include "efm32_bitband.h"
#ifdef __cplusplus
extern "C" {
@ -82,7 +83,7 @@ extern "C" {
#define CMU_EN_BIT_POS 12
#define CMU_EN_BIT_MASK 0x1f
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
/** @endcond */
/*******************************************************************************
******************************** ENUMS ************************************
@ -152,7 +153,7 @@ typedef enum
(_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS),
/** Universal sync/async receiver/transmitter 0 clock. */
#if defined(USART_COUNT) && (USART_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_USART0_MASK)
cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -160,7 +161,7 @@ typedef enum
#endif
/** Universal sync/async receiver/transmitter 1 clock. */
#if defined(USART_COUNT) && (USART_COUNT > 1)
#if defined(_CMU_HFPERCLKEN0_USART1_MASK)
cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -168,7 +169,7 @@ typedef enum
#endif
/** Universal sync/async receiver/transmitter 2 clock. */
#if defined(USART_COUNT) && (USART_COUNT > 2)
#if defined(_CMU_HFPERCLKEN0_USART2_MASK)
cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -176,7 +177,7 @@ typedef enum
#endif
/** Universal async receiver/transmitter 0 clock. */
#if defined(UART_COUNT) && (UART_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_UART0_MASK)
cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -184,7 +185,7 @@ typedef enum
#endif
/** Timer 0 clock. */
#if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)
cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -192,7 +193,7 @@ typedef enum
#endif
/** Timer 1 clock. */
#if defined(TIMER_COUNT) && (TIMER_COUNT > 1)
#if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)
cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -200,7 +201,7 @@ typedef enum
#endif
/** Timer 2 clock. */
#if defined(TIMER_COUNT) && (TIMER_COUNT > 2)
#if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)
cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -208,7 +209,7 @@ typedef enum
#endif
/** Analog comparator 0 clock. */
#if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)
cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -216,7 +217,7 @@ typedef enum
#endif
/** Analog comparator 1 clock. */
#if defined(ACMP_COUNT) && (ACMP_COUNT > 1)
#if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)
cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -232,7 +233,7 @@ typedef enum
#endif
/** Digital to analog converter 0 clock. */
#if defined(DAC_COUNT) && (DAC_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_DAC0_MASK)
cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -256,7 +257,7 @@ typedef enum
#endif
/** Analog to digital converter 0 clock. */
#if defined(ADC_COUNT) && (ADC_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_ADC0_MASK)
cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -264,7 +265,7 @@ typedef enum
#endif
/** I2C 0 clock. */
#if defined(I2C_COUNT) && (I2C_COUNT > 0)
#if defined(_CMU_HFPERCLKEN0_I2C0_MASK)
cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -329,7 +330,7 @@ typedef enum
#endif
/** Low energy timer 0 clock. */
#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0)
#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -337,7 +338,7 @@ typedef enum
#endif
/** Liquid crystal display, pre FDIV clock. */
#if defined(LCD_PRESENT)
#if defined(_CMU_LFACLKEN0_LCD_MASK)
cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_NO_EN_REG << CMU_EN_REG_POS) |
@ -352,7 +353,7 @@ typedef enum
#endif
/** Pulse counter 0 clock. */
#if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
@ -360,7 +361,7 @@ typedef enum
#endif
/** Pulse counter 1 clock. */
#if defined(PCNT_COUNT) && (PCNT_COUNT > 1)
#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
@ -368,12 +369,19 @@ typedef enum
#endif
/** Pulse counter 2 clock. */
#if defined(PCNT_COUNT) && (PCNT_COUNT > 2)
#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
(_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS),
#endif
/** LESENSE clock. */
#if defined(_CMU_LFACLKEN0_LESENSE_MASK)
cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
(_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS),
#endif
/***************/
/* LF B branch */
@ -386,7 +394,7 @@ typedef enum
(0 << CMU_EN_BIT_POS),
/** Low energy universal asynchronous receiver/transmitter 0 clock. */
#if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -394,7 +402,7 @@ typedef enum
#endif
/** Low energy universal asynchronous receiver/transmitter 1 clock. */
#if defined(LEUART_COUNT) && (LEUART_COUNT > 1)
#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
@ -406,24 +414,30 @@ typedef enum
/** Oscillator types. */
typedef enum
{
cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
cmuOsc_HFXO, /**< High frequency crystal oscillator. */
cmuOsc_HFRCO, /**< High frequency RC oscillator. */
cmuOsc_AUXHFRCO /**< Auxiliary high frequency RC oscillator. */
cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
cmuOsc_HFXO, /**< High frequency crystal oscillator. */
cmuOsc_HFRCO, /**< High frequency RC oscillator. */
cmuOsc_AUXHFRCO, /**< Auxiliary high frequency RC oscillator. */
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */
#endif
} CMU_Osc_TypeDef;
/** Selectable clock sources. */
typedef enum
{
cmuSelect_Error, /**< Usage error. */
cmuSelect_Disabled, /**< Clock selector disabled. */
cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
cmuSelect_HFXO, /**< High frequency crystal oscillator. */
cmuSelect_HFRCO, /**< High frequency RC oscillator. */
cmuSelect_CORELEDIV2 /**< Core low energy clock divided by 2. */
cmuSelect_Error, /**< Usage error. */
cmuSelect_Disabled, /**< Clock selector disabled. */
cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
cmuSelect_HFXO, /**< High frequency crystal oscillator. */
cmuSelect_HFRCO, /**< High frequency RC oscillator. */
cmuSelect_CORELEDIV2, /**< Core low energy clock divided by 2. */
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
cmuSelect_ULFRCO /**< Ultra low frequency RC oscillator. */
#endif
} CMU_Select_TypeDef;
@ -431,21 +445,32 @@ typedef enum
***************************** PROTOTYPES **********************************
******************************************************************************/
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
void CMU_FreezeEnable(bool enable);
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
uint32_t CMU_HFRCOStartupDelayGet(void);
void CMU_HFRCOStartupDelaySet(uint32_t delay);
uint32_t CMU_HFRCOStartupDelayGet(void);
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
bool CMU_PCNTClockExternalGet(unsigned int inst);
void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
uint32_t CMU_LCDClkFDIVGet(void);
void CMU_LCDClkFDIVSet(uint32_t div);
void CMU_FreezeEnable(bool enable);
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
CMU_Osc_TypeDef upSel);
/***************************************************************************//**
* @brief
@ -500,7 +525,39 @@ static __INLINE void CMU_IntEnable(uint32_t flags)
******************************************************************************/
static __INLINE uint32_t CMU_IntGet(void)
{
return(CMU->IF);
return CMU->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending CMU interrupt flags.
*
* @details
* Useful for handling more interrupt sources in the same interrupt handler.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @return
* Pending and enabled CMU interrupt sources.
* The return value is the bitwise AND combination of
* - the OR combination of enabled interrupt sources in CMU_IEN_nnn
* register (CMU_IEN_nnn) and
* - the OR combination of valid interrupt flags of the CMU module
* (CMU_IF_nnn).
******************************************************************************/
static __INLINE uint32_t CMU_IntGetEnabled(void)
{
uint32_t tmp = 0U;
/* Store LESENSE->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
tmp = CMU->IEN;
/* Bitwise AND of pending and enabled interrupts */
return CMU->IF & tmp;
}
@ -516,8 +573,6 @@ static __INLINE void CMU_IntSet(uint32_t flags)
CMU->IFS = flags;
}
uint32_t CMU_LCDClkFDIVGet(void);
void CMU_LCDClkFDIVSet(uint32_t div);
/***************************************************************************//**
* @brief
@ -537,11 +592,6 @@ static __INLINE void CMU_Lock(void)
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
bool CMU_PCNTClockExternalGet(unsigned int inst);
void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
/***************************************************************************//**
* @brief
@ -553,6 +603,74 @@ static __INLINE void CMU_Unlock(void)
}
/***************************************************************************//**
* @brief
* Get calibration count register
* @note
* If continuous calibrartion mode is active, calibration busy will allmost
* always be on, and we just need to read the value, where the normal case
* would be that this function call has been triggered by the CALRDY
* interrupt flag.
* @return
* Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
* in the period of DOWNSEL oscillator clock cycles configured by a previous
* write operation to CMU->CALCNT
******************************************************************************/
static __INLINE uint32_t CMU_CalibrateCountGet(void)
{
/* Wait until calibration completes, UNLESS continuous calibration mode is */
/* active */
#if defined (_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))
{
while (CMU->STATUS & CMU_STATUS_CALBSY)
;
}
#else
while (CMU->STATUS & CMU_STATUS_CALBSY)
;
#endif
return CMU->CALCNT;
}
/***************************************************************************//**
* @brief
* Starts calibration
* @note
* This call is usually invoked after CMU_CalibrateConfig() and possibly
* CMU_CalibrateCont()
******************************************************************************/
static __INLINE void CMU_CalibrateStart(void)
{
CMU->CMD = CMU_CMD_CALSTART;
}
#if defined (_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/***************************************************************************//**
* @brief
* Stop the calibration counters
******************************************************************************/
static __INLINE void CMU_CalibrateStop(void)
{
CMU->CMD = CMU_CMD_CALSTOP;
}
/***************************************************************************//**
* @brief
* Configures continuous calibration mode
* @param[in] enable
* If true, enables continuous calibration, if false disables continuous
* calibrartion
******************************************************************************/
static __INLINE void CMU_CalibrateCont(bool enable)
{
BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
}
#endif
/** @} (end addtogroup CMU) */
/** @} (end addtogroup EFM32_Library) */

73
bsp/efm32/Libraries/efm32lib/inc/efm32_common.h Normal file
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@ -0,0 +1,73 @@
/***************************************************************************//**
* @file
* @brief EFM32 general purpose utilities.
* @author Energy Micro AS
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __EFM32_COMMON_H
#define __EFM32_COMMON_H
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup EFM32_Library
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup COMMON
* @brief EFM32 general purpose utilities.
* @{
******************************************************************************/
#if !defined(__GNUC__)
/** Macro for getting minimum value. */
#define EFM32_MIN(a, b) ((a) < (b) ? (a) : (b))
/** Macro for getting maximum value. */
#define EFM32_MAX(a, b) ((a) > (b) ? (a) : (b))
#else
/** Macro for getting minimum value. No sideeffects, a and b are evaluated once only. */
#define EFM32_MIN(a, b) ({ typeof(a)_a = (a); typeof(b)_b = (b); _a < _b ? _a : _b; })
/** Macro for getting maximum value. No sideeffects, a and b are evaluated once only. */
#define EFM32_MAX(a, b) ({ typeof(a)_a = (a); typeof(b)_b = (b); _a > _b ? _a : _b; })
#endif
/** @} (end addtogroup COMMON) */
/** @} (end addtogroup EFM32_Library) */
#ifdef __cplusplus
}
#endif
#endif /* __EFM32_COMMON_H */

79
bsp/efm32/Libraries/efm32lib/inc/efm32_dac.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Digital to Analog Converter (DAC) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -45,6 +45,13 @@ extern "C" {
* @{
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of DAC register block pointer reference for assert statements. */
#define DAC_REF_VALID(ref) ((ref) == DAC0)
/** @endcond */
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
@ -57,20 +64,6 @@ typedef enum
dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */
} DAC_ConvMode_TypeDef;
/**
* Low pass filter cut-off frequency. Refer to datasheet for filter
* characteristics.
*/
typedef enum
{
dacLPFreq0 = _DAC_CTRL_LPFFREQ_FREQ0, /**< Cut-off frequency at FREQ0. */
dacLPFreq1 = _DAC_CTRL_LPFFREQ_FREQ1, /**< Cut-off frequency at FREQ1. */
dacLPFreq2 = _DAC_CTRL_LPFFREQ_FREQ2, /**< Cut-off frequency at FREQ2. */
dacLPFreq3 = _DAC_CTRL_LPFFREQ_FREQ3 /**< Cut-off frequency at FREQ3. */
} DAC_LPFreq_TypeDef;
/** Output mode. */
typedef enum
{
@ -124,9 +117,6 @@ typedef struct
/** Refresh interval. Only used if REFREN bit set for a DAC channel. */
DAC_Refresh_TypeDef refresh;
/** Low pass cut-off frequency. Only applicable if @p lpEnable true. */
DAC_LPFreq_TypeDef lpFreq;
/** Reference voltage to use. */
DAC_Ref_TypeDef reference;
@ -140,37 +130,36 @@ typedef struct
* Prescaler used to get DAC clock. Derived as follows:
* DACclk=HFPERclk/(2^prescale). The DAC clock should be <= 1MHz.
*/
uint8_t prescale;
uint8_t prescale;
/** Enable/disable use of low pass filter on output. */
bool lpEnable;
bool lpEnable;
/** Enable/disable reset of prescaler on ch0 start. */
bool ch0ResetPre;
bool ch0ResetPre;
/** Enable/disable output enable control by CH1 PRS signal. */
bool outEnablePRS;
bool outEnablePRS;
/** Enable/disable sine mode. */
bool sineEnable;
bool sineEnable;
/** Select if single ended or differential mode. */
bool diff;
bool diff;
} DAC_Init_TypeDef;
/** Default config for DAC init structure. */
#define DAC_INIT_DEFAULT \
{ dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
dacLPFreq0, /* Cut-off at freq0 (if cut-off enabled). */ \
dacRef1V25, /* 1.25V internal reference. */ \
dacOutputPin, /* Output to pin only. */ \
dacConvModeContinuous, /* Continuous mode. */ \
0, /* No prescaling. */ \
false, /* Do not enable low pass filter. */ \
false, /* Do not reset prescaler on ch0 start. */ \
false, /* DAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
#define DAC_INIT_DEFAULT \
{ dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
dacRef1V25, /* 1.25V internal reference. */ \
dacOutputPin, /* Output to pin only. */ \
dacConvModeContinuous, /* Continuous mode. */ \
0, /* No prescaling. */ \
false, /* Do not enable low pass filter. */ \
false, /* Do not reset prescaler on ch0 start. */ \
false, /* DAC output enable always on. */ \
false, /* Disable sine mode. */ \
false /* Single ended mode. */ \
}
@ -178,19 +167,19 @@ typedef struct
typedef struct
{
/** Enable channel. */
bool enable;
bool enable;
/**
* Peripheral reflex system trigger enable. If false, channel is triggered
* by writing to CHnDATA.
*/
bool prsEnable;
bool prsEnable;
/**
* Enable/disable automatic refresh of channel. Refresh interval must be
* defined in common control init, please see DAC_Init().
*/
bool refreshEnable;
bool refreshEnable;
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
@ -226,7 +215,7 @@ void DAC_InitChannel(DAC_TypeDef *dac,
* Pointer to DAC peripheral register block.
*
* @param[in] flags
* Pending DAC interrupt source to clear. Use a logical OR combination of
* Pending DAC interrupt source to clear. Use a bitwise logic OR combination of
* valid interrupt flags for the DAC module (DAC_IF_nnn).
******************************************************************************/
static __INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
@ -243,7 +232,7 @@ static __INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
* Pointer to DAC peripheral register block.
*
* @param[in] flags
* DAC interrupt sources to disable. Use a logical OR combination of
* DAC interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the DAC module (DAC_IF_nnn).
******************************************************************************/
static __INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
@ -265,7 +254,7 @@ static __INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
* Pointer to DAC peripheral register block.
*
* @param[in] flags
* DAC interrupt sources to enable. Use a logical OR combination of
* DAC interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the DAC module (DAC_IF_nnn).
******************************************************************************/
static __INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
@ -285,7 +274,7 @@ static __INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
* Pointer to DAC peripheral register block.
*
* @return
* DAC interrupt sources pending. A logical OR combination of valid
* DAC interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the DAC module (DAC_IF_nnn).
******************************************************************************/
static __INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
@ -302,8 +291,8 @@ static __INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
* Pointer to DAC peripheral register block.
*
* @param[in] flags
* DAC interrupt sources to set to pending. Use a logical OR combination of
* valid interrupt flags for the DAC module (DAC_IF_nnn).
* DAC interrupt sources to set to pending. Use a bitwise logic OR combination
* of valid interrupt flags for the DAC module (DAC_IF_nnn).
******************************************************************************/
static __INLINE void DAC_IntSet(DAC_TypeDef *dac, uint32_t flags)
{

4
bsp/efm32/Libraries/efm32lib/inc/efm32_dbg.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file
* @brief Debug (DBG) utilities API for EFM32.
* @brief Debug (DBG) API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>

26
bsp/efm32/Libraries/efm32lib/inc/efm32_dma.h
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@ -2,7 +2,7 @@
* @file
* @brief Direct memory access (DMA) API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -156,7 +156,7 @@ typedef struct
* or alternate descriptor completion. Mainly useful for ping-pong DMA
* cycles. Set this value to 0 prior to configuring callback handling.
*/
uint8_t primary;
uint8_t primary;
} DMA_CB_TypeDef;
@ -168,7 +168,7 @@ typedef struct
* with respect to arbitration. Within a priority group, lower numbered
* channels have higher priority than higher numbered channels.
*/
bool highPri;
bool highPri;
/**
* Select if interrupt shall be enabled for channel (triggering interrupt
@ -176,7 +176,7 @@ typedef struct
* enabled if using the callback feature for a channel, and disabled if
* not using the callback feature.
*/
bool enableInt;
bool enableInt;
/**
* Channel control specifying the source of DMA signals. If accessing
@ -210,13 +210,13 @@ typedef struct
typedef struct
{
/** Destination increment size for each DMA transfer */
DMA_DataInc_TypeDef dstInc;
DMA_DataInc_TypeDef dstInc;
/** Source increment size for each DMA transfer */
DMA_DataInc_TypeDef srcInc;
DMA_DataInc_TypeDef srcInc;
/** DMA transfer unit size. */
DMA_DataSize_TypeDef size;
DMA_DataSize_TypeDef size;
/**
* Arbitration rate, ie number of DMA transfers done before rearbitration
@ -241,19 +241,19 @@ typedef struct
typedef struct
{
/** Pointer to location to transfer data from. */
void *src;
void *src;
/** Pointer to location to transfer data to. */
void *dst;
void *dst;
/** Destination increment size for each DMA transfer */
DMA_DataInc_TypeDef dstInc;
DMA_DataInc_TypeDef dstInc;
/** Source increment size for each DMA transfer */
DMA_DataInc_TypeDef srcInc;
DMA_DataInc_TypeDef srcInc;
/** DMA transfer unit size. */
DMA_DataSize_TypeDef size;
DMA_DataSize_TypeDef size;
/**
* Arbitration rate, ie number of DMA transfers done before rearbitration
@ -281,7 +281,7 @@ typedef struct
* @li true - this is a peripheral scatter-gather cycle
* @li false - this is a memory scatter-gather cycle
*/
bool peripheral;
bool peripheral;
} DMA_CfgDescrSGAlt_TypeDef;

40
bsp/efm32/Libraries/efm32lib/inc/efm32_ebi.h
View File

@ -2,7 +2,7 @@
* @file
* @brief External Bus Iterface (EBI) peripheral API for EFM32
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -166,25 +166,25 @@ typedef struct
/** Default config for EBI init structures */
#define EBI_INIT_DEFAULT \
{ ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
true, /* enable EBI */ \
{ ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
true, /* enable EBI */ \
}
/*******************************************************************************

2
bsp/efm32/Libraries/efm32lib/inc/efm32_emu.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Energy management unit (EMU) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>

132
bsp/efm32/Libraries/efm32lib/inc/efm32_gpio.h
View File

@ -2,7 +2,7 @@
* @file
* @brief General Purpose IO (GPIO) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -31,6 +31,7 @@
#include <stdbool.h>
#include "efm32.h"
#include "efm32_bitband.h"
#include "efm32_assert.h"
#ifdef __cplusplus
extern "C" {
@ -117,6 +118,9 @@ typedef enum
******************************************************************************/
void GPIO_DbgLocationSet(unsigned int location);
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
static __INLINE void GPIO_EM4SetPinRetention(bool enable);
#endif
/***************************************************************************//**
* @brief
@ -132,7 +136,7 @@ void GPIO_DbgLocationSet(unsigned int location);
******************************************************************************/
static __INLINE void GPIO_DbgSWDClkEnable(bool enable)
{
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, (unsigned int) enable);
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, (unsigned int)enable);
}
@ -150,7 +154,7 @@ static __INLINE void GPIO_DbgSWDClkEnable(bool enable)
******************************************************************************/
static __INLINE void GPIO_DbgSWDIOEnable(bool enable)
{
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, (unsigned int) enable);
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, (unsigned int)enable);
}
@ -169,12 +173,98 @@ static __INLINE void GPIO_DbgSWDIOEnable(bool enable)
******************************************************************************/
static __INLINE void GPIO_DbgSWOEnable(bool enable)
{
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, (unsigned int) enable);
BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, (unsigned int)enable);
}
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
/**************************************************************************//**
* @brief
* Disable GPIO pin wake-up from EM4.
*
* @param[in] pinmask
* Bitmask containing the bitwise logic OR of which GPIO pin(s) to disable.
* Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
*****************************************************************************/
static __INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask)
{
EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
GPIO->EM4WUEN &= ~pinmask;
}
/**************************************************************************//**
* @brief
* Enable GPIO pin wake-up from EM4. When the function exits,
* EM4 mode can be safely entered.
*
* @note
* It is assumed that the GPIO pin modes are set correctly.
* Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.
*
* @param[in] pinmask
* Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.
* Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
* @param[in] polaritymask
* Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.
* Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
*****************************************************************************/
static __INLINE void GPIO_EM4EnablePinWakeup(uint32_t pinmask,
uint32_t polaritymask)
{
EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */
GPIO->EM4WUPOL |= pinmask & polaritymask;
GPIO->EM4WUEN |= pinmask; /* Enable wakeup */
GPIO_EM4SetPinRetention(true); /* Enable pin retention */
GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */
}
/**************************************************************************//**
* @brief
* Check which GPIO pin(s) that caused a wake-up from EM4.
*
* @return
* Bitmask containing the bitwise logic OR of which GPIO pin(s) caused the
* wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
*****************************************************************************/
static __INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
{
return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;
}
/**************************************************************************//**
* @brief
* Enable GPIO pin retention of output enable, output value, pull enable and
* pull direction in EM4.
*
* @param[in] enable
* @li true - enable EM4 pin retention.
* @li false - disable EM4 pin retention.
*****************************************************************************/
static __INLINE void GPIO_EM4SetPinRetention(bool enable)
{
if (enable)
{
GPIO->CTRL |= GPIO_CTRL_EM4RET;
}
else
{
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
}
}
#endif
/***************************************************************************//**
* @brief
* Enable/disable input sensing.
@ -183,12 +273,12 @@ void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
* Disabling input sensing if not used, can save some energy consumption.
*
* @param[in] val
* Logical OR of one or more of:
* Bitwise logic OR of one or more of:
* @li GPIO_INSENSE_INTSENSE - interrupt input sensing.
* @li GPIO_INSENSE_PRSSENSE - peripheral reflex system input sensing.
*
* @param[in] mask
* Mask containing logical OR of bits similar as for @p val used to indicate
* Mask containing bitwise logic OR of bits similar as for @p val used to indicate
* which input sense options to disable/enable.
******************************************************************************/
static __INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)
@ -202,7 +292,7 @@ static __INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)
* Clear one or more pending GPIO interrupts.
*
* @param[in] flags
* GPIO interrupt sources to clear.
* Bitwise logic OR of GPIO interrupt sources to clear.
******************************************************************************/
static __INLINE void GPIO_IntClear(uint32_t flags)
{
@ -261,6 +351,34 @@ static __INLINE uint32_t GPIO_IntGet(void)
}
/***************************************************************************//**
* @brief
* Get enabled and pending GPIO interrupt flags.
* Useful for handling more interrupt sources in the same interrupt handler.
*
* @note
* Interrupt flags are not cleared by the use of this function.
*
* @return
* Pending and enabled GPIO interrupt sources.
* The return value is the bitwise AND combination of
* - the OR combination of enabled interrupt sources in GPIO_IEN register
* and
* - the OR combination of valid interrupt flags in GPIO_IF register.
******************************************************************************/
static __INLINE uint32_t GPIO_IntGetEnabled(void)
{
uint32_t tmp;
/* Store GPIO->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
tmp = GPIO->IEN;
/* Bitwise AND of pending and enabled interrupts */
return GPIO->IF & tmp;
}
/**************************************************************************//**
* @brief
* Set one or more pending GPIO interrupts from SW.

26
bsp/efm32/Libraries/efm32lib/inc/efm32_i2c.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Inter-intergrated circuit (I2C) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -176,17 +176,17 @@ typedef enum
typedef struct
{
/** Enable I2C peripheral when init completed. */
bool enable;
bool enable;
/** Set to master (true) or slave (false) mode */
bool master;
bool master;
/**
* I2C reference clock assumed when configuring bus frequency setup.
* Set it to 0 if currently configurated reference clock shall be used
* This parameter is only applicable if operating in master mode.
*/
uint32_t refFreq;
uint32_t refFreq;
/**
* (Max) I2C bus frequency to use. This parameter is only applicable
@ -245,7 +245,7 @@ typedef struct
struct
{
/** Buffer used for data to transmit/receive, must be @p len long. */
uint8_t *data;
uint8_t *data;
/**
* Number of bytes in @p data to send or receive. Notice that when
@ -279,7 +279,7 @@ void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init);
* Pointer to I2C peripheral register block.
*
* @param[in] flags
* Pending I2C interrupt source to clear. Use a logical OR combination of
* Pending I2C interrupt source to clear. Use a bitwse logic OR combination of
* valid interrupt flags for the I2C module (I2C_IF_nnn).
******************************************************************************/
static __INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags)
@ -296,7 +296,7 @@ static __INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags)
* Pointer to I2C peripheral register block.
*
* @param[in] flags
* I2C interrupt sources to disable. Use a logical OR combination of
* I2C interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the I2C module (I2C_IF_nnn).
******************************************************************************/
static __INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags)
@ -318,7 +318,7 @@ static __INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags)
* Pointer to I2C peripheral register block.
*
* @param[in] flags
* I2C interrupt sources to enable. Use a logical OR combination of
* I2C interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the I2C module (I2C_IF_nnn).
******************************************************************************/
static __INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags)
@ -338,7 +338,7 @@ static __INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags)
* Pointer to I2C peripheral register block.
*
* @return
* I2C interrupt sources pending. A logical OR combination of valid
* I2C interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the I2C module (I2C_IF_nnn).
******************************************************************************/
static __INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
@ -355,8 +355,8 @@ static __INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
* Pointer to I2C peripheral register block.
*
* @param[in] flags
* I2C interrupt sources to set to pending. Use a logical OR combination of
* valid interrupt flags for the I2C module (I2C_IF_nnn).
* I2C interrupt sources to set to pending. Use a bitwise logic OR combination
* of valid interrupt flags for the I2C module (I2C_IF_nnn).
******************************************************************************/
static __INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags)
{
@ -407,7 +407,7 @@ static __INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
******************************************************************************/
static __INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
{
i2c->SADDR = (uint32_t) addr & 0xfe;
i2c->SADDR = (uint32_t)addr & 0xfe;
}
@ -465,7 +465,7 @@ static __INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
******************************************************************************/
static __INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask)
{
i2c->SADDRMASK = (uint32_t) mask & 0xfe;
i2c->SADDRMASK = (uint32_t)mask & 0xfe;
}

110
bsp/efm32/Libraries/efm32lib/inc/efm32_int.h Normal file
View File

@ -0,0 +1,110 @@
/***************************************************************************//**
* @file
* @brief Interrupt enable/disable unit API for EFM32.
* @author Energy Micro AS
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __EFM32_INT_H
#define __EFM32_INT_H
#include "efm32.h"
extern uint32_t INT_LockCnt;
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup EFM32_Library
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup INT
* @{
******************************************************************************/
/***************************************************************************//**
* @brief
* Disable interrupts.
*
* @return
* The resulting interrupt nesting level.
*
* @details
* Disable interrupts and increment lock level counter.
*
******************************************************************************/
static __INLINE uint32_t INT_Disable(void)
{
__disable_irq();
if (INT_LockCnt < UINT32_MAX)
{
INT_LockCnt++;
}
return INT_LockCnt;
}
/***************************************************************************//**
* @brief
* Enable interrupts.
*
* @return
* The resulting interrupt nesting level.
*
* @details
* Decrement interrupt lock level counter and enable interrupts if counter
* reached zero.
*
******************************************************************************/
static __INLINE uint32_t INT_Enable(void)
{
uint32_t retVal;
if (INT_LockCnt > 0)
{
INT_LockCnt--;
retVal = INT_LockCnt;
if (retVal == 0)
{
__enable_irq();
}
return retVal;
}
else
{
return 0;
}
}
/** @} (end addtogroup INT) */
/** @} (end addtogroup EFM32_Library) */
#ifdef __cplusplus
}
#endif
#endif /* __EFM32_INT_H */

141
bsp/efm32/Libraries/efm32lib/inc/efm32_lcd.h
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@ -2,7 +2,7 @@
* @file
* @brief Liquid Crystal Display (LCD) peripheral API for EFM32
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -62,18 +62,28 @@ typedef enum
/** Triplex / 1/3 Duty cycle (segments can be multiplexed with LCD_COM[0:2]) */
lcdMuxTriplex = LCD_DISPCTRL_MUX_TRIPLEX,
/** Quadruplex / 1/4 Duty cycle (segments can be multiplexed with LCD_COM[0:3]) */
lcdMuxQuadruplex = LCD_DISPCTRL_MUX_QUADRUPLEX
lcdMuxQuadruplex = LCD_DISPCTRL_MUX_QUADRUPLEX,
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_QUADRUPLEX
#endif
} LCD_Mux_TypeDef;
/** Bias setting */
typedef enum
{
/** Static (2 levels) */
lcdBiasStatic = LCD_DISPCTRL_BIAS_STATIC,
lcdBiasStatic = LCD_DISPCTRL_BIAS_STATIC,
/** 1/2 Bias (3 levels) */
lcdBiasOneHalf = LCD_DISPCTRL_BIAS_ONEHALF,
lcdBiasOneHalf = LCD_DISPCTRL_BIAS_ONEHALF,
/** 1/3 Bias (4 levels) */
lcdBiasOneThird = LCD_DISPCTRL_BIAS_ONETHIRD
lcdBiasOneThird = LCD_DISPCTRL_BIAS_ONETHIRD,
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/** 1/4 Bias (5 levels) */
lcdBiasOneFourth = LCD_DISPCTRL_BIAS_ONEFOURTH,
#endif
} LCD_Bias_TypeDef;
/** Wave type */
@ -144,6 +154,11 @@ typedef enum
lcdSegment16_19 = (1 << 4),
/** Select segment lines 20 to 23 */
lcdSegment20_23 = (1 << 5),
#if defined(_EFM32_TINY_FAMILY)
/** Select all segment lines */
lcdSegmentAll = (0x003f)
#endif
#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/** Select segment lines 24 to 27 */
lcdSegment24_27 = (1 << 6),
/** Select segment lines 28 to 31 */
@ -153,7 +168,8 @@ typedef enum
/** Select segment lines 36 to 39 */
lcdSegment36_39 = (1 << 9),
/** Select all segment lines */
lcdSegmentAll = (0x3ff)
lcdSegmentAll = (0x03ff)
#endif
} LCD_SegmentRange_TypeDef;
/** Update Data Control */
@ -181,9 +197,9 @@ typedef enum
/** Animation Logic Control, how AReg and BReg should be combined */
typedef enum
{
/** Use logical AND to mix animation register A (AREGA) and B (AREGB) */
/** Use bitwise logic AND to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicAnd = LCD_BACTRL_ALOGSEL_AND,
/** Use logical OR to mix animation register A (AREGA) and B (AREGB) */
/** Use bitwise logic OR to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicOr = LCD_BACTRL_ALOGSEL_OR
} LCD_AnimLogic_TypeDef;
@ -260,11 +276,37 @@ void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit);
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);
void LCD_SegmentSet(int com, int bit, bool enable);
void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);
#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY)
void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);
#endif
void LCD_ContrastSet(int level);
void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
void LCD_BiasSegmentSet(int segment, int biasLevel);
void LCD_BiasComSet(int com, int biasLevel);
#endif
static __INLINE void LCD_Enable(bool enable);
static __INLINE void LCD_AnimEnable(bool enable);
static __INLINE void LCD_BlinkEnable(bool enable);
static __INLINE void LCD_BlankEnable(bool enable);
static __INLINE void LCD_FrameCountEnable(bool enable);
static __INLINE int LCD_AnimState(void);
static __INLINE int LCD_BlinkState(void);
static __INLINE void LCD_FreezeEnable(bool enable);
static __INLINE uint32_t LCD_SyncBusyGet(void);
static __INLINE void LCD_SyncBusyDelay(uint32_t flags);
static __INLINE uint32_t LCD_IntGet(void);
static __INLINE uint32_t LCD_IntGetEnabled(void);
static __INLINE void LCD_IntSet(uint32_t flags);
static __INLINE void LCD_IntEnable(uint32_t flags);
static __INLINE void LCD_IntDisable(uint32_t flags);
static __INLINE void LCD_IntClear(uint32_t flags);
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
static __INLINE void LCD_DSCEnable(bool enable);
#endif
/***************************************************************************//**
* @brief
* Enable or disable LCD controller
@ -436,7 +478,8 @@ static __INLINE uint32_t LCD_SyncBusyGet(void)
******************************************************************************/
static __INLINE void LCD_SyncBusyDelay(uint32_t flags)
{
while (LCD->SYNCBUSY & flags) ;
while (LCD->SYNCBUSY & flags)
;
}
@ -445,7 +488,8 @@ static __INLINE void LCD_SyncBusyDelay(uint32_t flags)
* Get pending LCD interrupt flags
*
* @return
* Pending LCD interrupts, which need to be cleared.
* Pending LCD interrupt sources. Returns a set of interrupt flags OR-ed
* together for multiple interrupt sources in the LCD module (LCD_IFS_nnn).
******************************************************************************/
static __INLINE uint32_t LCD_IntGet(void)
{
@ -453,12 +497,45 @@ static __INLINE uint32_t LCD_IntGet(void)
}
/***************************************************************************//**
* @brief
* Get enabled and pending LCD interrupt flags.
*
* @details
* Useful for handling more interrupt sources in the same interrupt handler.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @return
* Pending and enabled LCD interrupt sources.
* The return value is the bitwise AND combination of
* - the OR combination of enabled interrupt sources in LCD_IEN_nnn
* register (LCD_IEN_nnn) and
* - the bitwise OR combination of valid interrupt flags of the LCD module
* (LCD_IF_nnn).
******************************************************************************/
static __INLINE uint32_t LCD_IntGetEnabled(void)
{
uint32_t tmp = 0U;
/* Store LCD->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
tmp = LCD->IEN;
/* Bitwise AND of pending and enabled interrupts */
return LCD->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending LCD interrupts from SW.
*
* @param[in] flags
* Bit field for interrupts to set
* LCD interrupt sources to set to pending. Use a set of interrupt flags
* OR-ed together to set multiple interrupt sources for the LCD module
* (LCD_IFS_nnn).
******************************************************************************/
static __INLINE void LCD_IntSet(uint32_t flags)
{
@ -468,10 +545,12 @@ static __INLINE void LCD_IntSet(uint32_t flags)
/***************************************************************************//**
* @brief
* Enable LCD (Frame Counter) interrupt
* Enable LCD interrupts
*
* @param[in] flags
* LCD_IF_FC, which is the only supported interrupt for the LCD controller
* LCD interrupt sources to enable. Use a set of interrupt flags OR-ed
* together to set multiple interrupt sources for the LCD module
* (LCD_IFS_nnn).
******************************************************************************/
static __INLINE void LCD_IntEnable(uint32_t flags)
{
@ -481,10 +560,12 @@ static __INLINE void LCD_IntEnable(uint32_t flags)
/***************************************************************************//**
* @brief
* Disable LCD (Frame Counter) interrupt
* Disable LCD interrupts
*
* @param[in] flags
* LCD_IF_FC, which is the only supported interrupt for the LCD controller
* LCD interrupt sources to disable. Use a set of interrupt flags OR-ed
* together to disable multiple interrupt sources for the LCD module
* (LCD_IFS_nnn).
******************************************************************************/
static __INLINE void LCD_IntDisable(uint32_t flags)
{
@ -497,13 +578,39 @@ static __INLINE void LCD_IntDisable(uint32_t flags)
* Clear one or more interrupt flags
*
* @param[in] flags
* LCD_IF_FC, which is the only supported interrupt for the LCD controller
* LCD interrupt sources to clear. Use a set of interrupt flags OR-ed
* together to clear multiple interrupt sources for the LCD module
* (LCD_IFS_nnn).
******************************************************************************/
static __INLINE void LCD_IntClear(uint32_t flags)
{
LCD->IFC = flags;
}
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/***************************************************************************//**
* @brief
* Enable or disable LCD Direct Segment Control
*
* @param[in] enable
* If true, enables LCD controller Direct Segment Control
* Segment and COM line bias levels needs to be set explicitly with the
* LCD_BiasSegmentSet() and LCD_BiasComSet() function calls.
******************************************************************************/
static __INLINE void LCD_DSCEnable(bool enable)
{
if (enable)
{
LCD->CTRL |= LCD_CTRL_DSC;
}
else
{
LCD->CTRL &= ~(LCD_CTRL_DSC);
}
}
#endif
/** @} (end addtogroup LCD) */
/** @} (end addtogroup EFM32_Library) */

1335
bsp/efm32/Libraries/efm32lib/inc/efm32_lesense.h Normal file
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File diff suppressed because it is too large Load Diff

19
bsp/efm32/Libraries/efm32lib/inc/efm32_letimer.h
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@ -2,7 +2,7 @@
* @file
* @brief Low Energy Timer (LETIMER) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -157,8 +157,9 @@ void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);
* Pointer to LETIMER peripheral register block.
*
* @param[in] flags
* Pending LETIMER interrupt source to clear. Use a logical OR combination
* of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
* Pending LETIMER interrupt source to clear. Use a bitwise logic OR
* combination of valid interrupt flags for the LETIMER module
* (LETIMER_IF_nnn).
******************************************************************************/
static __INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags)
{
@ -174,7 +175,7 @@ static __INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags)
* Pointer to LETIMER peripheral register block.
*
* @param[in] flags
* LETIMER interrupt sources to disable. Use a logical OR combination of
* LETIMER interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
******************************************************************************/
static __INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags)
@ -196,7 +197,7 @@ static __INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags
* Pointer to LETIMER peripheral register block.
*
* @param[in] flags
* LETIMER interrupt sources to enable. Use a logical OR combination of
* LETIMER interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
******************************************************************************/
static __INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags)
@ -216,8 +217,8 @@ static __INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags)
* Pointer to LETIMER peripheral register block.
*
* @return
* LETIMER interrupt sources pending. A logical OR combination of valid
* interrupt flags for the LETIMER module (LETIMER_IF_nnn).
* LETIMER interrupt sources pending. A bitwise logic OR combination of
* valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
******************************************************************************/
static __INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)
{
@ -233,8 +234,8 @@ static __INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)
* Pointer to LETIMER peripheral register block.
*
* @param[in] flags
* LETIMER interrupt sources to set to pending. Use a logical OR combination
* of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
* LETIMER interrupt sources to set to pending. Use a bitwise logic OR
* combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn).
******************************************************************************/
static __INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags)
{

18
bsp/efm32/Libraries/efm32lib/inc/efm32_leuart.h
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@ -3,7 +3,7 @@
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -100,7 +100,7 @@ typedef enum
typedef struct
{
/** Specifies whether TX and/or RX shall be enabled when init completed. */
LEUART_Enable_TypeDef enable;
LEUART_Enable_TypeDef enable;
/**
* LEUART reference clock assumed when configuring baudrate setup. Set
@ -154,8 +154,8 @@ void LEUART_Init(LEUART_TypeDef *leuart, LEUART_Init_TypeDef *init);
* Pointer to LEUART peripheral register block.
*
* @param[in] flags
* Pending LEUART interrupt source to clear. Use a logical OR combination
* of valid interrupt flags for the LEUART module (LEUART_IF_nnn).
* Pending LEUART interrupt source to clear. Use a bitwise logic OR
* combination of valid interrupt flags for the LEUART module (LEUART_IF_nnn).
******************************************************************************/
static __INLINE void LEUART_IntClear(LEUART_TypeDef *leuart, uint32_t flags)
{
@ -171,7 +171,7 @@ static __INLINE void LEUART_IntClear(LEUART_TypeDef *leuart, uint32_t flags)
* Pointer to LEUART peripheral register block.
*
* @param[in] flags
* LEUART interrupt sources to disable. Use a logical OR combination of
* LEUART interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the LEUART module (LEUART_IF_nnn).
******************************************************************************/
static __INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)
@ -193,7 +193,7 @@ static __INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)
* Pointer to LEUART peripheral register block.
*
* @param[in] flags
* LEUART interrupt sources to enable. Use a logical OR combination of
* LEUART interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the LEUART module (LEUART_IF_nnn).
******************************************************************************/
static __INLINE void LEUART_IntEnable(LEUART_TypeDef *leuart, uint32_t flags)
@ -213,7 +213,7 @@ static __INLINE void LEUART_IntEnable(LEUART_TypeDef *leuart, uint32_t flags)
* Pointer to LEUART peripheral register block.
*
* @return
* LEUART interrupt sources pending. A logical OR combination of valid
* LEUART interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the LEUART module (LEUART_IF_nnn).
******************************************************************************/
static __INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)
@ -230,8 +230,8 @@ static __INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)
* Pointer to LEUART peripheral register block.
*
* @param[in] flags
* LEUART interrupt sources to set to pending. Use a logical OR combination
* of valid interrupt flags for the LEUART module (LEUART_IF_nnn).
* LEUART interrupt sources to set to pending. Use a bitwise logic OR
* combination of valid interrupt flags for the LEUART module (LEUART_IF_nnn).
******************************************************************************/
static __INLINE void LEUART_IntSet(LEUART_TypeDef *leuart, uint32_t flags)
{

2
bsp/efm32/Libraries/efm32lib/inc/efm32_mpu.h
View File

@ -2,7 +2,7 @@
* @file
* @brief Memory protection unit (MPU) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>

171
bsp/efm32/Libraries/efm32lib/inc/efm32_msc.h
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@ -1,9 +1,8 @@
/***************************************************************************//**
* @file
* @brief On-board Flash controller module peripheral API for EFM32
* devices.
* @brief Flash controller module (MSC) peripheral API for EFM32
* @author Energy Micro AS
* @version 1.3.0
* @version 2.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
@ -33,9 +32,13 @@
extern "C" {
#endif
#include "efm32.h"
#include "core_cm3.h"
#include <stdint.h>
#include <stdbool.h>
#include "efm32.h"
#include "efm32_bitband.h"
/***************************************************************************//**
* @addtogroup EFM32_Library
@ -44,7 +47,7 @@ extern "C" {
/***************************************************************************//**
* @addtogroup MSC
* @brief EFM32 Flash controller utilities.
* @brief Flash controller (MSC) peripheral API for EFM32
* @{
******************************************************************************/
@ -91,8 +94,8 @@ void MSC_Init(void);
* Clear one or more pending MSC interrupts.
*
* @param[in] flags
* Pending MSC intterupt source to clear. Use a logical OR combination of
* valid interrupt flags for the MSC module (MSC_IF_nnn).
* Pending MSC intterupt source to clear. Use a bitwise logic OR combination
* of valid interrupt flags for the MSC module (MSC_IF_nnn).
******************************************************************************/
static __INLINE void MSC_IntClear(uint32_t flags)
{
@ -104,7 +107,7 @@ static __INLINE void MSC_IntClear(uint32_t flags)
* Disable one or more MSC interrupts.
*
* @param[in] flags
* MSC interrupt sources to disable. Use a logical OR combination of
* MSC interrupt sources to disable. Use a bitwise logic OR combination of
* valid interrupt flags for the MSC module (MSC_IF_nnn).
******************************************************************************/
static __INLINE void MSC_IntDisable(uint32_t flags)
@ -123,7 +126,7 @@ static __INLINE void MSC_IntDisable(uint32_t flags)
* if such a pending interrupt should be ignored.
*
* @param[in] flags
* MSC interrupt sources to enable. Use a logical OR combination of
* MSC interrupt sources to enable. Use a bitwise logic OR combination of
* valid interrupt flags for the MSC module (MSC_IF_nnn).
******************************************************************************/
static __INLINE void MSC_IntEnable(uint32_t flags)
@ -140,7 +143,7 @@ static __INLINE void MSC_IntEnable(uint32_t flags)
* The event bits are not cleared by the use of this function.
*
* @return
* MSC interrupt sources pending. A logical OR combination of valid
* MSC interrupt sources pending. A bitwise logic OR combination of valid
* interrupt flags for the MSC module (MSC_IF_nnn).
******************************************************************************/
static __INLINE uint32_t MSC_IntGet(void)
@ -154,7 +157,7 @@ static __INLINE uint32_t MSC_IntGet(void)
* Set one or more pending MSC interrupts from SW.
*
* @param[in] flags
* MSC interrupt sources to set to pending. Use a logical OR combination of
* MSC interrupt sources to set to pending. Use a bitwise logic OR combination of
* valid interrupt flags for the MSC module (MSC_IF_nnn).
******************************************************************************/
static __INLINE void MSC_IntSet(uint32_t flags)
@ -162,22 +165,158 @@ static __INLINE void MSC_IntSet(uint32_t flags)
MSC->IFS = flags;
}
#if _EFM32_TINY_FAMILY == 1
/***************************************************************************//**
* @brief
* Starts measuring cache hit ratio.
* @details
* This function starts the performance counters. It is defined inline to
* minimize the impact of this code on the measurement itself.
******************************************************************************/
static __INLINE void MSC_StartCacheMeasurement(void)
{
/* Clear CMOF and CHOF to catch these later */
MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
/* Start performance counters */
MSC->CMD = MSC_CMD_STARTPC;
}
/***************************************************************************//**
* @brief
* Stops measuring the hit rate.
* @note
* This function is defined inline to minimize the impact of this
* code on the measurement itself.
* This code only works for relatively short sections of code. If you wish
* to measure longer sections of code you need to implement a IRQ Handler for
* The CHOF and CMOF overflow interrupts. Theses overflows needs to be
* counted and included in the total.
* The functions can then be implemented as follows:
* @verbatim
* volatile uint32_t hitOverflows
* volatile uint32_t missOverflows
*
* void MSC_IRQHandler(void)
* {
* uint32_t flags;
* flags = MSC->IF;
* if (flags & MSC_IF_CHOF)
* {
* MSC->IFC = MSC_IF_CHOF;
* hitOverflows++;
* }
* if (flags & MSC_IF_CMOF)
* {
* MSC->IFC = MSC_IF_CMOF;
* missOverflows++;
* }
* }
*
* void startPerformanceCounters(void)
* {
* hitOverflows = 0;
* missOverflows = 0;
*
* MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF);
* NVIC_EnableIRQ(MSC_IRQn);
*
* MSC_StartCacheMeasurement();
* }
* @endverbatim
* @return
* Returns -1 if there has been no cache accesses.
* Returns -2 if there has been an overflow in the performance counters.
* If not, it will return the percentage of hits versus misses.
******************************************************************************/
static __INLINE int32_t MSC_GetCacheMeasurement(void)
{
int32_t total;
/* Stop the counter before computing the hit-rate */
MSC->CMD = MSC_CMD_STOPPC;
/* Check for overflows in performance counters */
if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
return -2;
/* Because the hits and misses are volatile, we need to split this up into
* two statements to avoid a compiler warning regarding the order of volatile
* accesses. */
total = MSC->CACHEHITS;
total += MSC->CACHEMISSES;
/* To avoid a division by zero. */
if (total == 0)
return -1;
return (MSC->CACHEHITS * 100) / total;
}
/***************************************************************************//**
* @brief
* Flush the contents of the instruction cache.
******************************************************************************/
static __INLINE void MSC_FlushCache(void)
{
MSC->CMD = MSC_CMD_INVCACHE;
}
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality
* @param[in] enable
* Enable instruction cache. Default is on.
******************************************************************************/
static __INLINE void MSC_EnableCache(bool enable)
{
BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, ~enable);
}
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality in IRQs
* @param[in] enable
* Enable instruction cache. Default is on.
******************************************************************************/
static __INLINE void MSC_EnableCacheIRQs(bool enable)
{
BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, ~enable);
}
/***************************************************************************//**
* @brief
* Enable or disable instruction cache flushing when writing to flash
* @param[in] enable
* Enable automatic cache flushing. Default is on.
******************************************************************************/
static __INLINE void MSC_EnableAutoCacheFlush(bool enable)
{
BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, ~enable);
}
#endif
#ifdef __CC_ARM /* MDK-ARM compiler */
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void *data, int numBytes);
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes);
msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress);
#endif /* __CC_ARM */
#ifdef __ICCARM__ /* IAR compiler */
__ramfunc msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void *data, int numBytes);
__ramfunc msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes);
__ramfunc msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress);
#endif /* __ICCARM__ */
#ifdef __GNUC__ /* GCC based compilers */
#ifdef __CROSSWORKS_ARM /* Rowley Crossworks */
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void *data, int numBytes) __attribute__ ((section(".fast")));
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes) __attribute__ ((section(".fast")));
msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".fast")));
#else /* Sourcery G++ */
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void *data, int numBytes) __attribute__ ((section(".ram")));
msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes) __attribute__ ((section(".ram")));
msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".ram")));
#endif /* __GNUC__ */
#endif /* __CROSSWORKS_ARM */

538
bsp/efm32/Libraries/efm32lib/inc/efm32_opamp.h Normal file
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@ -0,0 +1,538 @@
/**************************************************************************//**
* @file
* @brief Operational Amplifier (OPAMP) peripheral API for EFM32.
* @author Energy Micro AS
* @version 2.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __EFM32_OPAMP_H
#define __EFM32_OPAMP_H
#include "efm32.h"
#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "efm32_dac.h"
/***************************************************************************//**
* @addtogroup EFM32_Library
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup OPAMP
* @{
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of DAC OPA number for assert statements. */
#define DAC_OPA_VALID(opa) ((opa) <= OPA2)
/** @endcond */
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** OPAMP selector values. */
typedef enum
{
OPA0 = 0, /**< Select OPA0. */
OPA1 = 1, /**< Select OPA1. */
OPA2 = 2 /**< Select OPA2. */
} OPAMP_TypeDef;
/** OPAMP negative terminal input selection values. */
typedef enum
{
opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */
opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */
opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */
opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */
} OPAMP_NegSel_TypeDef;
/** OPAMP positive terminal input selection values. */
typedef enum
{
opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */
opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */
opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */
opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA1IN, /**< Input from OPAx. */
opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */
} OPAMP_PosSel_TypeDef;
/** OPAMP output terminal selection values. */
typedef enum
{
opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */
opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */
opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */
opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */
} OPAMP_OutMode_TypeDef;
/** OPAMP gain values. */
typedef enum
{
opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */
opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */
opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */
opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */
opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */
opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */
opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */
opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */
opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */
} OPAMP_ResSel_TypeDef;
/** OPAMP resistor ladder input selector values. */
typedef enum
{
opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */
opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA2INP, /**< Input from OPAx. */
opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */
opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */
opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */
} OPAMP_ResInMux_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** OPAMP init structure. */
typedef struct
{
OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */
OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */
OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */
OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */
OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */
uint32_t outPen; /**< Select alternate output terminal connections. */
uint32_t bias; /**< Set OPAMP bias current. */
bool halfBias; /**< Divide OPAMP bias current by 2. */
bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */
bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */
bool nextOut; /**< Enable NEXTOUT signal source. */
bool npEn; /**< Enable positive pad. */
bool ppEn; /**< Enable negative pad. */
bool shortInputs; /**< Short OPAMP input terminals. */
bool hcmDisable; /**< Disable input rail-to-rail capability. */
bool defaultOffset; /**< Use factory calibrated opamp offset value. */
uint32_t offset; /**< Opamp offset value when @ref defaultOffset is false.*/
} OPAMP_Init_TypeDef;
/** Configuration of OPA0/1 in unity gain voltage follower mode. */
#define OPA_INIT_UNITY_GAIN \
{ \
opaNegSelUnityGain, /* Unity gain. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelDefault, /* Resistor ladder is not used. */ \
opaResInMuxDisable, /* Resistor ladder disabled. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in unity gain voltage follower mode. */
#define OPA_INIT_UNITY_GAIN_OPA2 \
{ \
opaNegSelUnityGain, /* Unity gain. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelDefault, /* Resistor ladder is not used. */ \
opaResInMuxDisable, /* Resistor ladder disabled. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0/1 in non-inverting amplifier mode. */
#define OPA_INIT_NON_INVERTING \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
true, /* Neg pad enabled, used as signal ground. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in non-inverting amplifier mode. */
#define OPA_INIT_NON_INVERTING_OPA2 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
true, /* Neg pad enabled, used as signal ground. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0/1 in inverting amplifier mode. */
#define OPA_INIT_INVERTING \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
true, /* Neg pad enabled, used as signal input. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in inverting amplifier mode. */
#define OPA_INIT_INVERTING_OPA2 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
true, /* Neg pad enabled, used as signal input. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA1). */ \
true, /* Neg pad enabled, used as signal ground. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA2). */ \
true, /* Neg pad enabled, used as signal ground. */ \
false, /* Pos pad disabled. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
true, /* Neg pad enabled, used as signal ground. */ \
false, /* Pos pad disabled. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA0 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA1). */ \
true, /* Neg pad enabled, used as signal input. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA1 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA1 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA2). */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA2 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA0 \
{ \
opaNegSelUnityGain, /* Unity gain. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelDefault, /* Resistor ladder is not used. */ \
opaResInMuxDisable, /* Resistor ladder disabled. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA1). */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA1 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA1 \
{ \
opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal ground. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA0 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA0 \
{ \
opaNegSelUnityGain, /* Unity gain. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA2). */ \
true, /* Neg pad enabled, used as signal ground. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA1 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA1 \
{ \
opaNegSelUnityGain, /* Unity gain. */ \
opaPosSelPosPad, /* Pos input from pad. */ \
opaOutModeAll, /* Both main and alternate outputs. */ \
opaResSelDefault, /* Resistor ladder is not used. */ \
opaResInMuxDisable, /* Disable resistor ladder. */ \
0, /* No alternate outputs enabled. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
true, /* Pass output to next stage (OPA2). */ \
false, /* Neg pad disabled. */ \
true, /* Pos pad enabled, used as signal input. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/** Configuration of OPA2 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA2 \
{ \
opaNegSelResTap, /* Input from resistor ladder tap. */ \
opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \
opaOutModeMain, /* Main output enabled. */ \
opaResSelR2eqR1, /* R2 = R1 */ \
opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \
_DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
_DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
false, /* No low pass filter on pos pad. */ \
false, /* No low pass filter on neg pad. */ \
false, /* No nextout output enabled. */ \
false, /* Neg pad disabled. */ \
false, /* Pos pad disabled. */ \
false, /* No shorting of inputs. */ \
false, /* Rail-to-rail input enabled. */ \
true, /* Use factory calibrated opamp offset. */ \
0 /* Opamp offset value (not used). */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa);
void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, OPAMP_Init_TypeDef *init);
/** @} (end addtogroup OPAMP) */
/** @} (end addtogroup EFM32_Library) */
#ifdef __cplusplus
}
#endif
#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */
#endif /* __EFM32_DAC_H */

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