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update IA32 branch for new rt-thread platform. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1948 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2012-02-16 04:19:20 +00:00
parent 7906287cfe
commit 68bee363ff
7 changed files with 31 additions and 352 deletions
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4
libcpu/ia32/context.S → libcpu/ia32/context_gcc.S
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@ -1,11 +1,11 @@
/*
* File : context.S
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes

5
libcpu/ia32/hdisr.S → libcpu/ia32/hdisr_gcc.S
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@ -1,14 +1,15 @@
/*
* File : hdisr.S
* File : hdisr_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-09-15 QiuYi The first version
*/
/**

125
libcpu/ia32/include/bsp.h
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@ -1,125 +0,0 @@
/*
* File : bsp.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-09-15 QiuYi the first version */
#ifndef __BSP_H_
#define __BSP_H_
#include <i386.h>
/*******************************************************************/
/* Timer Register */
/*******************************************************************/
#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
#define TIMER_SEL0 0x00 /* select counter 0 */
#define TIMER_SEL1 0x40 /* select counter 1 */
#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
#define TIMER_LATCH 0x00 /* latch counter for reading */
#define TIMER_LSB 0x10 /* r/w counter LSB */
#define TIMER_MSB 0x20 /* r/w counter MSB */
#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
#define TIMER_BCD 0x01 /* count in BCD */
#define TIMER_FREQ 1193182
#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
#define IO_TIMER1 0x040 /* 8253 Timer #1 */
/*******************************************************************/
/* Interrupt Controller */
/*******************************************************************/
/* these are processor defined */
#define T_DIVIDE 0 /* divide error */
#define T_DEBUG 1 /* debug exception */
#define T_NMI 2 /* non-maskable interrupt */
#define T_BRKPT 3 /* breakpoint */
#define T_OFLOW 4 /* overflow */
#define T_BOUND 5 /* bounds check */
#define T_ILLOP 6 /* illegal opcode */
#define T_DEVICE 7 /* device not available */
#define T_DBLFLT 8 /* double fault */
/* 9 is reserved */
#define T_TSS 10 /* invalid task switch segment */
#define T_SEGNP 11 /* segment not present */
#define T_STACK 12 /* stack exception */
#define T_GPFLT 13 /* genernal protection fault */
#define T_PGFLT 14 /* page fault */
/* 15 is reserved */
#define T_FPERR 16 /* floating point error */
#define T_ALIGN 17 /* aligment check */
#define T_MCHK 18 /* machine check */
#define T_DEFAULT 500 /* catchall */
#define INTTIMER0 0
#define INTKEYBOARD 1
#define INTUART0_RX 4
/* I/O Addresses of the two 8259A programmable interrupt controllers */
#define IO_PIC1 0x20 /* Master(IRQs 0-7) */
#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */
#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */
#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */
#define MAX_HANDLERS 16 /*max number of isr handler*/
/*******************************************************************/
/* CRT Register */
/*******************************************************************/
#define MONO_BASE 0x3b4
#define MONO_BUF 0xb0000
#define CGA_BASE 0x3d4
#define CGA_BUF 0xb8000
#define CRT_ROWS 25
#define CRT_COLS 80
#define CRT_SIZE (CRT_ROWS * CRT_COLS)
/*******************************************************************/
/* Keyboard Register */
/*******************************************************************/
#define KBSTATP 0x64 /* kbd controller status port(I) */
#define KBS_DIB 0x01 /* kbd data in buffer */
#define KBDATAP 0x60 /* kbd data port(I) */
/*******************************************************************/
/* Serial Register */
/*******************************************************************/
/*Serial I/O code */
#define COM1 0x3F8
#define COMSTATUS 5
#define COMDATA 0x01
#define COMREAD 0
#define COMWRITE 0
/* Bits definition of the Line Status Register (LSR)*/
#define DR 0x01 /* Data Ready */
#define OE 0x02 /* Overrun Error */
#define PE 0x04 /* Parity Error */
#define FE 0x08 /* Framing Error */
#define BI 0x10 /* Break Interrupt */
#define THRE 0x20 /* Transmitter Holding Register Empty */
#define TEMT 0x40 /* Transmitter Empty */
#define ERFIFO 0x80 /* Error receive Fifo */
#ifdef __cplusplus
}
#endif
#endif /* __BSP_H_ */

93
libcpu/ia32/include/grub.h
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@ -1,93 +0,0 @@
/*
* File : grub.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-10-09 Bernard the grub related definitions
* (multiboot)
*/
#ifndef __GRUB_H__
#define __GRUB_H__
/* the magic number for the multiboot header. */
#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
/* the flags for the multiboot header. */
#define MULTIBOOT_HEADER_FLAGS 0x00000003
/* the magic number passed by a multiboot-compliant boot loader. */
#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
#ifndef __ASM__
/* the multiboot header. */
typedef struct multiboot_header
{
unsigned long magic;
unsigned long flags;
unsigned long checksum;
unsigned long header_addr;
unsigned long load_addr;
unsigned long load_end_addr;
unsigned long bss_end_addr;
unsigned long entry_addr;
} multiboot_header_t;
/* the section header table for elf. */
typedef struct elf_section_header_table
{
unsigned long num;
unsigned long size;
unsigned long addr;
unsigned long shndx;
} elf_section_header_table_t;
/* the multiboot information. */
typedef struct multiboot_info
{
unsigned long flags;
unsigned long mem_lower;
unsigned long mem_upper;
unsigned long boot_device;
unsigned long cmdline;
unsigned long mods_count;
unsigned long mods_addr;
union
{
aout_symbol_table_t aout_sym;
elf_section_header_table_t elf_sec;
} u;
unsigned long mmap_length;
unsigned long mmap_addr;
} multiboot_info_t;
/* the module structure. */
typedef struct module
{
unsigned long mod_start;
unsigned long mod_end;
unsigned long string;
unsigned long reserved;
} module_t;
/* the memory map. be careful that the offset 0 is base_addr_low
but no size. */
typedef struct memory_map
{
unsigned long size;
unsigned long base_addr_low;
unsigned long base_addr_high;
unsigned long length_low;
unsigned long length_high;
unsigned long type;
} memory_map_t;
#endif
#endif

108
libcpu/ia32/include/i386.h
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@ -1,108 +0,0 @@
#ifndef __I386_H_
#define __I386_H_
#ifdef __cplusplus
extern "C" {
#endif
static __inline unsigned char inb(int port)
{
unsigned char data;
__asm __volatile("inb %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline unsigned short inw(int port)
{
unsigned short data;
__asm __volatile("inw %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline unsigned int inl(int port)
{
unsigned int data;
__asm __volatile("inl %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void insl(int port, void *addr, int cnt)
{
__asm __volatile("cld\n\trepne\n\tinsl" :
"=D" (addr), "=c" (cnt) :
"d" (port), "0" (addr), "1" (cnt) :
"memory", "cc");
}
static __inline void outb(int port, unsigned char data)
{
__asm __volatile("outb %0,%w1" : : "a" (data), "d" (port));
}
static __inline void outw(int port, unsigned short data)
{
__asm __volatile("outw %0,%w1" : : "a" (data), "d" (port));
}
/* Gate descriptors are slightly different*/
struct Gatedesc {
unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment
unsigned gd_ss : 16; // segment selector
unsigned gd_args : 5; // # args, 0 for interrupt/trap gates
unsigned gd_rsv1 : 3; // reserved(should be zero I guess)
unsigned gd_type :4; // type(STS_{TG,IG32,TG32})
unsigned gd_s : 1; // must be 0 (system)
unsigned gd_dpl : 2; // descriptor(meaning new) privilege level
unsigned gd_p : 1; // Present
unsigned gd_off_31_16 : 16; // high bits of offset in segment
};
/* Pseudo-descriptors used for LGDT, LLDT and LIDT instructions*/
struct Pseudodesc {
rt_uint16_t pd__garbage; // LGDT supposed to be from address 4N+2
rt_uint16_t pd_lim; // Limit
rt_uint32_t pd_base __attribute__ ((packed)); // Base address
};
#define SETGATE(gate, istrap, sel, off, dpl) \
{ \
(gate).gd_off_15_0 = (rt_uint32_t) (off) & 0xffff; \
(gate).gd_ss = (sel); \
(gate).gd_args = 0; \
(gate).gd_rsv1 = 0; \
(gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \
(gate).gd_s = 0; \
(gate).gd_dpl = dpl; \
(gate).gd_p = 1; \
(gate).gd_off_31_16 = (rt_uint32_t) (off) >> 16; \
}
/* Global descriptor numbers*/
#define GD_KT 0x08 // kernel text
#define GD_KD 0x10 // kernel data
#define GD_UT 0x18 // user text
#define GD_UD 0x20 // user data
/* Application segment type bits*/
#define STA_X 0x8 // Executable segment
#define STA_E 0x4 // Expand down(non-executable segments)
#define STA_C 0x4 // Conforming code segment(executable only)
#define STA_W 0x2 // Writeable(non-executable segments)
#define STA_R 0x2 // Readable(executable segments)
#define STA_A 0x1 // Accessed
/* System segment type bits*/
#define STS_T16A 0x1 // Available 16-bit TSS
#define STS_LDT 0x2 // Local Descriptor Table
#define STS_T16B 0x3 // Busy 16-bit TSS
#define STS_CG16 0x4 // 16-bit Call Gate
#define STS_TG 0x5 // Task Gate / Coum Transmitions
#define STS_IG16 0x6 // 16-bit Interrupt Gate
#define STS_TG16 0x7 // 16-bit Trap Gate
#define STS_T32A 0x9 // Available 32-bit TSS
#define STS_T32B 0xb // Busy 32-bit TSS
#define STS_CG32 0xc // 32-bit Call Gate
#define STS_IG32 0xe // 32-bit Interrupt Gate
#define STS_TG32 0xf // 32-bit Trap Gate
#endif

15
libcpu/ia32/start.S → libcpu/ia32/start_gcc.S
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@ -1,19 +1,23 @@
/*
* File : start.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-09-15 QiuYi The first version
* 2006-09-15 QiuYi The first version.
* 2012-02-15 aozima update.
*/
#define __ASM__
#include <grub.h>
/* the magic number for the multiboot header. */
#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
/* the flags for the multiboot header. */
#define MULTIBOOT_HEADER_FLAGS 0x00000003
#define CONFIG_STACKSIZE 8192
@ -23,7 +27,6 @@
/*@{*/
.section .init, "ax"
.text
/* the system entry */
.globl _start

5
libcpu/ia32/trapisr.S → libcpu/ia32/trapisr_gcc.S
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@ -1,14 +1,15 @@
/*
* File : trapisr.S
* File : trapisr_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-09-15 QiuYi The first version.
*/
/**