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implement serialX UART device framework

This commit is contained in:
thewon86 2023-02-21 12:30:29 +08:00 committed by GitHub
parent 7f588dc3a9
commit 67bc7e816c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 2846 additions and 2 deletions
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2
bsp/stm32/libraries/HAL_Drivers/SConscript
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@ -13,6 +13,8 @@ if GetDepend(['RT_USING_PIN']):
if GetDepend(['RT_USING_SERIAL']): if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SERIAL_V2']): if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c'] src += ['drv_usart_v2.c']
elif GetDepend(['RT_USING_SERIAL_X']):
src += ['drv_usartX.c']
else: else:
src += ['drv_usart.c'] src += ['drv_usart.c']

876
bsp/stm32/libraries/HAL_Drivers/drv_usartX.c Normal file
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@ -0,0 +1,876 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-10 THEWON first version
*/
#include "board.h"
#include "drv_usartX.h"
#include "drv_config.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.usart"
#include <drv_log.h>
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
#ifdef RT_SERIAL_USING_DMA
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
#endif
enum
{
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
#ifdef BSP_USING_UART4
UART4_INDEX,
#endif
#ifdef BSP_USING_UART5
UART5_INDEX,
#endif
#ifdef BSP_USING_UART6
UART6_INDEX,
#endif
#ifdef BSP_USING_UART7
UART7_INDEX,
#endif
#ifdef BSP_USING_UART8
UART8_INDEX,
#endif
#ifdef BSP_USING_LPUART1
LPUART1_INDEX,
#endif
};
static struct stm32_uart_config uart_config[] =
{
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
#ifdef BSP_USING_UART2
UART2_CONFIG,
#endif
#ifdef BSP_USING_UART3
UART3_CONFIG,
#endif
#ifdef BSP_USING_UART4
UART4_CONFIG,
#endif
#ifdef BSP_USING_UART5
UART5_CONFIG,
#endif
#ifdef BSP_USING_UART6
UART6_CONFIG,
#endif
#ifdef BSP_USING_UART7
UART7_CONFIG,
#endif
#ifdef BSP_USING_UART8
UART8_CONFIG,
#endif
#ifdef BSP_USING_LPUART1
LPUART1_CONFIG,
#endif
};
static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
{
rt_uint32_t mask;
if (word_length == UART_WORDLENGTH_8B)
{
if (parity == UART_PARITY_NONE)
{
mask = 0x00FFU ;
}
else
{
mask = 0x007FU ;
}
}
#ifdef UART_WORDLENGTH_9B
else if (word_length == UART_WORDLENGTH_9B)
{
if (parity == UART_PARITY_NONE)
{
mask = 0x01FFU ;
}
else
{
mask = 0x00FFU ;
}
}
#endif
#ifdef UART_WORDLENGTH_7B
else if (word_length == UART_WORDLENGTH_7B)
{
if (parity == UART_PARITY_NONE)
{
mask = 0x007FU ;
}
else
{
mask = 0x003FU ;
}
}
else
{
mask = 0x0000U;
}
#endif
return mask;
}
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
uart->handle.Instance = uart->config->Instance;
uart->handle.Init.BaudRate = cfg->baud_rate;
uart->handle.Init.Mode = UART_MODE_TX_RX;
uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
switch (cfg->flowcontrol)
{
case RT_SERIAL_FLOWCONTROL_NONE:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
break;
case RT_SERIAL_FLOWCONTROL_CTSRTS:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
break;
default:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
break;
}
switch (cfg->data_bits)
{
case DATA_BITS_8:
if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
else
uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
break;
case DATA_BITS_9:
uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
break;
default:
uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
uart->handle.Init.StopBits = UART_STOPBITS_1;
break;
case STOP_BITS_2:
uart->handle.Init.StopBits = UART_STOPBITS_2;
break;
default:
uart->handle.Init.StopBits = UART_STOPBITS_1;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
uart->handle.Init.Parity = UART_PARITY_NONE;
break;
case PARITY_ODD:
uart->handle.Init.Parity = UART_PARITY_ODD;
break;
case PARITY_EVEN:
uart->handle.Init.Parity = UART_PARITY_EVEN;
break;
default:
uart->handle.Init.Parity = UART_PARITY_NONE;
break;
}
uart->config->mask = stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
if (HAL_UART_Init(&uart->handle) != HAL_OK)
{
return -RT_ERROR;
}
return RT_EOK;
}
static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct stm32_uart *uart;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
switch (cmd)
{
case RT_DEVICE_CTRL_OPEN:
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
/* enable interrupt */
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
#ifdef RT_SERIAL_USING_DMA
uart->dmaTxing = RT_FALSE;
HAL_NVIC_EnableIRQ(uart->config->dma_conf_rx->dma_irq);
HAL_NVIC_EnableIRQ(uart->config->dma_conf_tx->dma_irq);
#endif
break;
case RT_DEVICE_CTRL_CLOSE:
HAL_NVIC_DisableIRQ(uart->config->irq_type);
#ifdef RT_SERIAL_USING_DMA
HAL_NVIC_DisableIRQ(uart->config->dma_conf_rx->dma_irq);
HAL_NVIC_DisableIRQ(uart->config->dma_conf_tx->dma_irq);
#endif
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
{
}
break;
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable interrupt */
if (ctrl_arg & RT_DEVICE_FLAG_INT_RX) {
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
}
#ifdef RT_SERIAL_USING_DMA
/* disable DMA */
if (ctrl_arg & RT_DEVICE_FLAG_DMA_RX)
{
HAL_NVIC_DisableIRQ(uart->config->dma_conf_rx->dma_irq);
if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
}
if(ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
{
HAL_NVIC_DisableIRQ(uart->config->dma_conf_tx->dma_irq);
if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
}
#endif
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
if (ctrl_arg & RT_DEVICE_FLAG_INT_RX) {
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
}
break;
#ifdef RT_SERIAL_USING_DMA
case RT_DEVICE_CTRL_CONFIG:
stm32_dma_config(serial, ctrl_arg);
break;
#endif
default :
break;
}
return RT_EOK;
}
static int stm32_putc(struct rt_serial_device *serial, char c)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) == RESET);
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
uart->handle.Instance->TDR = c;
#else
uart->handle.Instance->DR = c;
#endif
return 1;
}
static int stm32_getc(struct rt_serial_device *serial)
{
int ch = -1;
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) == RESET)
{
return -1;
}
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
ch = uart->handle.Instance->RDR & uart->config->mask;
#else
ch = uart->handle.Instance->DR & uart->config->mask;
#endif
return ch;
}
static int stm32_flush(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
return 1;
}
static void stm32_start_tx(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE);
}
static void stm32_stop_tx(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
}
#ifdef RT_SERIAL_USING_DMA
static rt_bool_t stm32_is_dma_txing(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
return uart->dmaTxing; //RT_FALSE;
}
static void stm32_start_dma_tx(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size)
{
struct stm32_uart *uart;
HAL_StatusTypeDef status;
DMA_HandleTypeDef *hdma;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
do { // may fallin dead loop
status = HAL_UART_Transmit_DMA(&uart->handle, buf, size);
} while (status != HAL_OK);
uart->dmaTxing = RT_TRUE;
}
static void stm32_stop_dma_tx(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if ((uart->dma_tx.handle.Instance->CR & DMA_SxCR_EN) == DMA_SxCR_EN) {
return;
}
__HAL_DMA_DISABLE(&uart->dma_tx.handle);
uart->dmaTxing = RT_FALSE;
}
#endif
static void stm32_enable_interrupt(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
#ifdef RT_SERIAL_USING_DMA
if (uart->uart_dma_flag) {
HAL_NVIC_EnableIRQ(uart->config->dma_conf_rx->dma_irq);
}
#endif
}
static void stm32_disable_interrupt(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
HAL_NVIC_DisableIRQ(uart->config->irq_type);
#ifdef RT_SERIAL_USING_DMA
if (uart->uart_dma_flag) {
HAL_NVIC_DisableIRQ(uart->config->dma_conf_rx->dma_irq);
}
#endif
}
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
#ifdef RT_SERIAL_USING_DMA
rt_size_t dma_cnt;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
/* UART in mode Receiver -------------------------------------------------*/
if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) &&
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE) != RESET))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
}
#ifdef RT_SERIAL_USING_DMA
else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
&& (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
{
__HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
dma_cnt = RT_SERIAL_DMA_BUFSZ - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (dma_cnt << 8));
}
else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
{
if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
{
HAL_UART_IRQHandler(&(uart->handle));
}
}
#endif
else
{
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
{
__HAL_UART_CLEAR_OREFLAG(&uart->handle);
}
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
{
__HAL_UART_CLEAR_NEFLAG(&uart->handle);
}
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
{
__HAL_UART_CLEAR_FEFLAG(&uart->handle);
}
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
{
__HAL_UART_CLEAR_PEFLAG(&uart->handle);
}
#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
&& !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
#ifdef SOC_SERIES_STM32F3
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
}
#else
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
}
#endif
#endif
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
}
// if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
// {
// UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
// }
// if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
// {
// UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
// }
// if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
// {
// UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
// }
}
}
#ifdef RT_SERIAL_USING_DMA
static void dma_isr(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
rt_size_t dma_cnt;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
(__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
{
dma_cnt = RT_SERIAL_DMA_BUFSZ - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (dma_cnt << 8));
}
}
#endif
#if defined(BSP_USING_UART1)
void USART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART1_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
void UART1_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
void UART1_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
#endif /* BSP_USING_UART1 */
#ifdef RT_SERIAL_USING_DMA
static void stm32_uart_get_dma_config(void)
{
#ifdef BSP_USING_UART1
uart_obj[UART1_INDEX].uart_dma_flag = 0;
#ifdef BSP_UART1_RX_USING_DMA
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
uart_config[UART1_INDEX].dma_conf_rx = &uart1_dma_rx;
#endif
#ifdef BSP_UART1_TX_USING_DMA
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
uart_config[UART1_INDEX].dma_conf_tx = &uart1_dma_tx;
#endif
#endif
}
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
{
DMA_HandleTypeDef *DMA_Handle;
struct dma_config *dma_config;
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle = &uart->dma_rx.handle;
dma_config = uart->config->dma_conf_rx;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle = &uart->dma_tx.handle;
dma_config = uart->config->dma_conf_tx;
}
LOG_D("%s dma config start", uart->config->name);
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32MP1)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
#endif
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
}
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
DMA_Handle->Instance = dma_config->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Channel = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Request = dma_config->request;
#endif
DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle->Init.Mode = DMA_CIRCULAR;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle->Init.Mode = DMA_NORMAL;
}
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
/* enable interrupt */
if (flag == RT_DEVICE_FLAG_DMA_RX)
{
/* Start DMA transfer */
if (HAL_UART_Receive_DMA(&(uart->handle), serial->serial_dma_rx, RT_SERIAL_DMA_BUFSZ) != HAL_OK)
{
/* Transfer error in reception process */
RT_ASSERT(0);
}
CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
}
/* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(dma_config->dma_irq);
}
/**
* @brief UART error callbacks
* @param huart: UART handle
* @note This example shows a simple way to report transfer error, and you can
* add your own implementation.
* @retval None
*/
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
UNUSED(uart);
}
/**
* @brief Rx Transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx transfer, and
* you can add your own implementation.
* @retval None
*/
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
/**
* @brief Rx Half transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx Half transfer,
* and you can add your own implementation.
* @retval None
*/
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
/**
* @brief HAL_UART_TxCpltCallback
* @param huart: UART handle
* @note This callback can be called by two functions, first in UART_EndTransmit_IT when
* UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
* @retval None
*/
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
rt_size_t dma_cnt;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_cnt = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
if (dma_cnt == 0)
{
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
}
}
#endif /* RT_SERIAL_USING_DMA */
static const struct rt_uart_ops stm32_uart_ops =
{
.configure = stm32_configure,
.control = stm32_control,
.putc = stm32_putc,
.getc = stm32_getc,
.flush = stm32_flush,
.start_tx = stm32_start_tx,
.stop_tx = stm32_stop_tx,
#ifdef RT_SERIAL_USING_DMA
.is_dma_txing = stm32_is_dma_txing,
.start_dma_tx = stm32_start_dma_tx,
.stop_dma_tx = stm32_stop_dma_tx,
#endif
.enable_interrupt = stm32_enable_interrupt,
.disable_interrupt = stm32_disable_interrupt,
};
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
#ifdef RT_SERIAL_USING_DMA
stm32_uart_get_dma_config();
#endif
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &stm32_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
#ifdef RT_SERIAL_USING_DMA
| uart_obj[i].uart_dma_flag
#endif
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */

74
bsp/stm32/libraries/HAL_Drivers/drv_usartX.h Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-10 THEWON first version
*/
#ifndef __DRV_USARTX_H__
#define __DRV_USARTX_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include "drv_dma.h"
int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F2) \
|| defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32MP1)
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
#endif
/* stm32 config class */
struct stm32_uart_config
{
const char *name;
USART_TypeDef *Instance;
IRQn_Type irq_type;
rt_uint32_t mask;
#ifdef RT_SERIAL_USING_DMA
struct dma_config *dma_conf_rx;
struct dma_config *dma_conf_tx;
#endif
};
/* stm32 uart dirver class */
struct stm32_uart
{
UART_HandleTypeDef handle;
struct rt_serial_device serial;
struct stm32_uart_config *config;
#ifdef RT_SERIAL_USING_DMA
rt_bool_t dmaTxing;
struct
{
DMA_HandleTypeDef handle;
} dma_rx;
struct
{
DMA_HandleTypeDef handle;
} dma_tx;
rt_uint16_t uart_dma_flag;
#endif
};
#endif /* __DRV_USART_H__ */

5
bsp/stm32/stm32f429-armfly-v6/board/Kconfig
View File

@ -93,6 +93,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART1" bool "Enable UART1"
default y default y
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_USING_DMA config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA" bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA

15
bsp/stm32/stm32f429-atk-apollo/board/Kconfig
View File

@ -99,6 +99,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART1" bool "Enable UART1"
default y default y
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_USING_DMA config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA" bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
@ -108,6 +113,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART2" bool "Enable UART2"
default n default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_RX_USING_DMA config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA" bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
@ -116,7 +126,12 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART3 config BSP_USING_UART3
bool "Enable UART3" bool "Enable UART3"
default n default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
depends on !BSP_USING_ETH depends on !BSP_USING_ETH
default n
config BSP_UART3_RX_USING_DMA config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA" bool "Enable UART3 RX DMA"

10
bsp/stm32/stm32f429-fire-challenger/board/Kconfig
View File

@ -97,6 +97,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART1" bool "Enable UART1"
default y default y
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_USING_DMA config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA" bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
@ -106,6 +111,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART2" bool "Enable UART2"
default n default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_RX_USING_DMA config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA" bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA

10
bsp/stm32/stm32f429-st-disco/board/Kconfig
View File

@ -32,6 +32,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART1" bool "Enable UART1"
default y default y
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_USING_DMA config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA" bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
@ -41,6 +46,11 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART2" bool "Enable UART2"
default n default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_RX_USING_DMA config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA" bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA

34
components/drivers/Kconfig
View File

@ -38,6 +38,10 @@ menuconfig RT_USING_SERIAL
bool "RT_USING_SERIAL_V1" bool "RT_USING_SERIAL_V1"
config RT_USING_SERIAL_V2 config RT_USING_SERIAL_V2
bool "RT_USING_SERIAL_V2" bool "RT_USING_SERIAL_V2"
config RT_USING_SERIAL_X
bool "RT_USING_SERIAL_X"
help
A serial driver that supporting True NonBlock.
endchoice endchoice
config RT_SERIAL_USING_DMA config RT_SERIAL_USING_DMA
bool "Enable serial DMA mode" bool "Enable serial DMA mode"
@ -45,8 +49,36 @@ menuconfig RT_USING_SERIAL
config RT_SERIAL_RB_BUFSZ config RT_SERIAL_RB_BUFSZ
int "Set RX buffer size" int "Set RX buffer size"
depends on !RT_USING_SERIAL_V2 depends on RT_USING_SERIAL_V1
default 64 default 64
if RT_USING_SERIAL_X
config RT_SERIAL_FIFO_BUFSZ
int "Set SerialX FIFO buffer size"
default 128
help
suggestion: RT_SERIAL_FIFO_BUFSZ == 2^N
and RT_SERIAL_FIFO_BUFSZ >= 2*RT_SERIAL_DMA_BUFSZ
config RT_SERIAL_DMA_BUFSZ
int "Set SerialX DMA buffer size"
depends on RT_SERIAL_USING_DMA
default 64
help
suggestion: RT_SERIAL_DMA_BUFSZ == 2^N
and RT_SERIAL_FIFO_BUFSZ >= 2*RT_SERIAL_DMA_BUFSZ
config RT_SERIAL_HARD_FIFO
bool "Set Hard FIFO buffer size"
default n
help
Useful only if the chip supported
eg: NUC970 N9H30 serial chips
The UART1/2/4/6/8/10 is built-in with a 64-byte transmitter FIFO (TX_FIFO)
and a 64-byte receiver FIFO (RX_FIFO),
and the UART0/3/5/7/9 are equipped 16-byte transmitter FIFO (TX_FIFO)
and 16-byte receiver FIFO (RX_FIFO).
endif
endif endif
config RT_USING_TTY config RT_USING_TTY

207
components/drivers/include/drivers/serialX.h Normal file
View File

@ -0,0 +1,207 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-10 THEWON first version
*/
#ifndef __SERIALX_H__
#define __SERIALX_H__
#include <rtthread.h>
#include <rtdevice.h>
#define BAUD_RATE_2400 2400
#define BAUD_RATE_4800 4800
#define BAUD_RATE_9600 9600
#define BAUD_RATE_19200 19200
#define BAUD_RATE_38400 38400
#define BAUD_RATE_57600 57600
#define BAUD_RATE_115200 115200
#define BAUD_RATE_230400 230400
#define BAUD_RATE_460800 460800
#define BAUD_RATE_921600 921600
#define BAUD_RATE_2000000 2000000
#define BAUD_RATE_3000000 3000000
#define DATA_BITS_5 5
#define DATA_BITS_6 6
#define DATA_BITS_7 7
#define DATA_BITS_8 8
#define DATA_BITS_9 9
#define STOP_BITS_1 0
#define STOP_BITS_2 1
#define STOP_BITS_3 2
#define STOP_BITS_4 3
#ifdef _WIN32
#include <windows.h>
#else
#define PARITY_NONE 0
#define PARITY_ODD 1
#define PARITY_EVEN 2
#endif
#define BIT_ORDER_LSB 0
#define BIT_ORDER_MSB 1
#define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */
#define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */
#ifndef RT_SERIAL_FIFO_BUFSZ
#define RT_SERIAL_FIFO_BUFSZ 128
#endif
#ifndef RT_SERIAL_DMA_BUFSZ
#define RT_SERIAL_DMA_BUFSZ 32
#endif
#if RT_SERIAL_DMA_BUFSZ < 32
#define RT_SERIAL_DMA_BUFSZ 32
#endif
#if RT_SERIAL_FIFO_BUFSZ < (RT_SERIAL_DMA_BUFSZ*2)
#define RT_SERIAL_FIFO_BUFSZ RT_SERIAL_DMA_BUFSZ*2
#endif
#define RT_SERIAL_EVENT_RX_IND 0x01 /* Rx indication */
#define RT_SERIAL_EVENT_TX_DONE 0x02 /* Tx complete */
#define RT_SERIAL_EVENT_RX_DMADONE 0x03 /* Rx DMA transfer done */
#define RT_SERIAL_EVENT_TX_DMADONE 0x04 /* Tx DMA transfer done */
#define RT_SERIAL_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
#define RT_SERIAL_DMA_RX 0x01
#define RT_SERIAL_DMA_TX 0x02
#define RT_SERIAL_RX_INT 0x01
#define RT_SERIAL_TX_INT 0x02
#define RT_SERIAL_ERR_OVERRUN 0x01
#define RT_SERIAL_ERR_FRAMING 0x02
#define RT_SERIAL_ERR_PARITY 0x03
#define RT_SERIAL_TX_DATAQUEUE_SIZE 2048
#define RT_SERIAL_TX_DATAQUEUE_LWM 30
#define RT_SERIAL_FLOWCONTROL_CTSRTS 1
#define RT_SERIAL_FLOWCONTROL_NONE 0
/* Default config for serial_configure structure */
#define RT_SERIAL_CONFIG_DEFAULT \
{ \
BAUD_RATE_115200, /* 115200 bits/s */ \
DATA_BITS_8, /* 8 databits */ \
STOP_BITS_1, /* 1 stopbit */ \
PARITY_NONE, /* No parity */ \
BIT_ORDER_LSB, /* LSB first sent */ \
NRZ_NORMAL, /* Normal mode */ \
RT_SERIAL_FIFO_BUFSZ, /* Buffer size */ \
RT_SERIAL_FLOWCONTROL_NONE, /* Off flowcontrol */ \
0 \
}
#define RT_SERIAL_EVENT_TXDONE (1 << 0)
#define RT_SERIAL_EVENT_RXDONE (1 << 1)
//#define RT_SERIAL_USE_EVENT // Just for test, maybe using event in the future
struct rt_serial_device;
typedef int (*cb_serial_tx)(struct rt_serial_device *serial, const rt_uint8_t *data, int length);
typedef int (*cb_serial_rx)(struct rt_serial_device *serial, rt_uint8_t *data, int length);
struct serial_configure
{
rt_uint32_t baud_rate;
rt_uint32_t data_bits :4;
rt_uint32_t stop_bits :2;
rt_uint32_t parity :2;
rt_uint32_t bit_order :1;
rt_uint32_t invert :1;
rt_uint32_t bufsz :16;
rt_uint32_t flowcontrol :1;
rt_uint32_t reserved :5;
};
/*
* Serial FIFO mode
*/
struct rt_serial_fifo
{
rt_uint32_t buf_sz;
/* software fifo */
rt_uint8_t *buffer;
rt_uint16_t put_index, get_index;
rt_bool_t is_full;
};
struct rt_serial_device
{
struct rt_device parent;
const struct rt_uart_ops *ops;
struct serial_configure config;
void *serial_rx;
void *serial_tx;
#ifdef RT_SERIAL_USING_DMA
rt_size_t dma_idx_rx;
rt_uint8_t serial_dma_rx[RT_SERIAL_DMA_BUFSZ];
rt_uint8_t serial_dma_tx[RT_SERIAL_DMA_BUFSZ];
#endif
cb_serial_rx _cb_rx;
cb_serial_tx _cb_tx;
#ifndef RT_SERIAL_USE_EVENT
struct rt_completion completion_rx;
struct rt_completion completion_tx;
#else
rt_event_t rx_done;
rt_event_t tx_done;
#endif
};
typedef struct rt_serial_device rt_serial_t;
/**
* uart operators
*/
struct rt_uart_ops
{
rt_err_t (*configure)(struct rt_serial_device *serial, struct serial_configure *cfg);
rt_err_t (*control)(struct rt_serial_device *serial, int cmd, void *arg);
int (*putc)(struct rt_serial_device *serial, char c);
int (*getc)(struct rt_serial_device *serial);
int (*flush)(struct rt_serial_device *serial);
void (*start_tx)(struct rt_serial_device *serial);
void (*stop_tx)(struct rt_serial_device *serial);
#ifdef RT_SERIAL_USING_DMA
rt_bool_t (*is_dma_txing)(struct rt_serial_device *serial);
void (*start_dma_tx)(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size);
void (*stop_dma_tx)(struct rt_serial_device *serial);
#endif
void (*enable_interrupt)(struct rt_serial_device *serial);
void (*disable_interrupt)(struct rt_serial_device *serial);
};
void rt_hw_serial_isr(struct rt_serial_device *serial, int event);
rt_err_t rt_hw_serial_register(struct rt_serial_device *serial,
const char *name,
rt_uint32_t flag,
void *data);
#endif

5
components/drivers/include/rtdevice.h
View File

@ -7,6 +7,7 @@
* Date Author Notes * Date Author Notes
* 2012-01-08 bernard first version. * 2012-01-08 bernard first version.
* 2014-07-12 bernard Add workqueue implementation. * 2014-07-12 bernard Add workqueue implementation.
* 2022-04-10 THEWON add serialX
*/ */
#ifndef __RT_DEVICE_H__ #ifndef __RT_DEVICE_H__
@ -57,7 +58,9 @@ extern "C" {
#endif /* RT_USING_USB_HOST */ #endif /* RT_USING_USB_HOST */
#ifdef RT_USING_SERIAL #ifdef RT_USING_SERIAL
#ifdef RT_USING_SERIAL_V2 #ifdef RT_USING_SERIAL_X
#include "drivers/serialX.h"
#elif defined RT_USING_SERIAL_V2
#include "drivers/serial_v2.h" #include "drivers/serial_v2.h"
#else #else
#include "drivers/serial.h" #include "drivers/serial.h"

3
components/drivers/serial/SConscript
View File

@ -7,6 +7,9 @@ if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SERIAL_V2']): if GetDepend(['RT_USING_SERIAL_V2']):
src = Glob('serial_v2.c') src = Glob('serial_v2.c')
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL_V2'], CPPPATH = CPPPATH) group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL_V2'], CPPPATH = CPPPATH)
elif GetDepend(['RT_USING_SERIAL_X']):
src = Glob('serialX.c')
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL_X'], CPPPATH = CPPPATH)
else: else:
src = Glob('serial.c') src = Glob('serial.c')
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL'], CPPPATH = CPPPATH) group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SERIAL'], CPPPATH = CPPPATH)

1560
components/drivers/serial/serialX.c Normal file
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File diff suppressed because it is too large Load Diff

9
include/rtdef.h
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@ -41,6 +41,7 @@
* 2022-01-01 Gabriel improve hooking method * 2022-01-01 Gabriel improve hooking method
* 2022-01-07 Gabriel move some __on_rt_xxxxx_hook to dedicated c source files * 2022-01-07 Gabriel move some __on_rt_xxxxx_hook to dedicated c source files
* 2022-01-12 Meco Man remove RT_THREAD_BLOCK * 2022-01-12 Meco Man remove RT_THREAD_BLOCK
* 2022-04-10 THEWON add flush for device & some device flags
* 2022-04-20 Meco Man change version number to v4.1.1 * 2022-04-20 Meco Man change version number to v4.1.1
* 2022-04-21 THEWON add macro RT_VERSION_CHECK * 2022-04-21 THEWON add macro RT_VERSION_CHECK
* 2022-06-29 Meco Man add RT_USING_LIBC and standard libc headers * 2022-06-29 Meco Man add RT_USING_LIBC and standard libc headers
@ -1165,6 +1166,10 @@ enum rt_device_class_type
#define RT_DEVICE_OFLAG_WRONLY 0x002 /**< write only access */ #define RT_DEVICE_OFLAG_WRONLY 0x002 /**< write only access */
#define RT_DEVICE_OFLAG_RDWR 0x003 /**< read and write */ #define RT_DEVICE_OFLAG_RDWR 0x003 /**< read and write */
#define RT_DEVICE_OFLAG_OPEN 0x008 /**< device is opened */ #define RT_DEVICE_OFLAG_OPEN 0x008 /**< device is opened */
#define RT_DEVICE_OFLAG_BLOCKING 0x000 /**< blocking io mode */
#define RT_DEVICE_OFLAG_NONBLOCKING 0x004 /**< non-blocking io mode */
#define RT_DEVICE_OFLAG_MASK 0xf0f /**< mask of open flag */ #define RT_DEVICE_OFLAG_MASK 0xf0f /**< mask of open flag */
/** /**
@ -1182,6 +1187,8 @@ enum rt_device_class_type
#define RT_DEVICE_CTRL_CLR_INT 0x07 /**< clear interrupt */ #define RT_DEVICE_CTRL_CLR_INT 0x07 /**< clear interrupt */
#define RT_DEVICE_CTRL_GET_INT 0x08 /**< get interrupt status */ #define RT_DEVICE_CTRL_GET_INT 0x08 /**< get interrupt status */
#define RT_DEVICE_CTRL_CONSOLE_OFLAG 0x09 /**< get console open flag */ #define RT_DEVICE_CTRL_CONSOLE_OFLAG 0x09 /**< get console open flag */
#define RT_DEVICE_CTRL_OPEN 0x0A /**< open device */
#define RT_DEVICE_CTRL_BLOCKING 0x0B /**< blocking io */
#define RT_DEVICE_CTRL_MASK 0x1f /**< mask for contrl commands */ #define RT_DEVICE_CTRL_MASK 0x1f /**< mask for contrl commands */
/** /**
@ -1220,6 +1227,7 @@ struct rt_device_ops
rt_ssize_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); rt_ssize_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
rt_ssize_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); rt_ssize_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
rt_err_t (*control)(rt_device_t dev, int cmd, void *args); rt_err_t (*control)(rt_device_t dev, int cmd, void *args);
rt_err_t (*flush) (rt_device_t dev);
}; };
#endif /* RT_USING_DEVICE_OPS */ #endif /* RT_USING_DEVICE_OPS */
@ -1264,6 +1272,7 @@ struct rt_device
rt_ssize_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); rt_ssize_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
rt_ssize_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); rt_ssize_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
rt_err_t (*control)(rt_device_t dev, int cmd, void *args); rt_err_t (*control)(rt_device_t dev, int cmd, void *args);
rt_err_t (*flush) (rt_device_t dev);
#endif /* RT_USING_DEVICE_OPS */ #endif /* RT_USING_DEVICE_OPS */
#ifdef RT_USING_POSIX_DEVIO #ifdef RT_USING_POSIX_DEVIO

38
src/device.c
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@ -13,6 +13,7 @@
* 2013-07-09 Grissiom add ref_count support * 2013-07-09 Grissiom add ref_count support
* 2016-04-02 Bernard fix the open_flag initialization issue. * 2016-04-02 Bernard fix the open_flag initialization issue.
* 2021-03-19 Meco Man remove rt_device_init_all() * 2021-03-19 Meco Man remove rt_device_init_all()
* 2022-04-10 THEWON add flush for device
*/ */
#include <rtthread.h> #include <rtthread.h>
@ -28,6 +29,7 @@
#define device_close (dev->ops->close) #define device_close (dev->ops->close)
#define device_read (dev->ops->read) #define device_read (dev->ops->read)
#define device_write (dev->ops->write) #define device_write (dev->ops->write)
#define device_flush (dev->ops->flush)
#define device_control (dev->ops->control) #define device_control (dev->ops->control)
#else #else
#define device_init (dev->init) #define device_init (dev->init)
@ -35,6 +37,7 @@
#define device_close (dev->close) #define device_close (dev->close)
#define device_read (dev->read) #define device_read (dev->read)
#define device_write (dev->write) #define device_write (dev->write)
#define device_flush (dev->flush)
#define device_control (dev->control) #define device_control (dev->control)
#endif /* RT_USING_DEVICE_OPS */ #endif /* RT_USING_DEVICE_OPS */
@ -290,7 +293,11 @@ rt_err_t rt_device_close(rt_device_t dev)
/* set open flag */ /* set open flag */
if (result == RT_EOK || result == -RT_ENOSYS) if (result == RT_EOK || result == -RT_ENOSYS)
{
dev->open_flag = RT_DEVICE_OFLAG_CLOSE; dev->open_flag = RT_DEVICE_OFLAG_CLOSE;
dev->rx_indicate = RT_NULL;
dev->tx_complete = RT_NULL;
}
return result; return result;
} }
@ -382,6 +389,37 @@ rt_ssize_t rt_device_write(rt_device_t dev,
} }
RTM_EXPORT(rt_device_write); RTM_EXPORT(rt_device_write);
/**
* @brief This function will flush a device's buffers.
*
* @param dev is the pointer of device driver structure.
*
* @return the result, RT_EOK on successfully.
*/
rt_err_t rt_device_flush(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
if (dev->ref_count == 0)
{
rt_set_errno(-RT_ERROR);
return 0;
}
/* call device_write interface */
if (device_flush != RT_NULL)
{
return device_flush(dev);
}
/* set error code */
rt_set_errno(-RT_ENOSYS);
return 0;
}
RTM_EXPORT(rt_device_flush);
/** /**
* @brief This function will perform a variety of control functions on devices. * @brief This function will perform a variety of control functions on devices.
* *