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Add Libraries directory for lm3s 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@229 bbd45198-f89e-11dd-88c7-29a3b14d5316
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qiuyiuestc 2009-12-25 14:39:36 +00:00
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//*****************************************************************************
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup adc_api
//! @{
//
//*****************************************************************************
#include "inc/hw_adc.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/adc.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// These defines are used by the ADC driver to simplify access to the ADC
// sequencer's registers.
//
//*****************************************************************************
#define ADC_SEQ (ADC_O_SSMUX0)
#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
//*****************************************************************************
//
// The currently configured software oversampling factor for each of the ADC
// sequencers.
//
//*****************************************************************************
static unsigned char g_pucOversampleFactor[3];
//*****************************************************************************
//
//! Registers an interrupt handler for an ADC interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pfnHandler is a pointer to the function to be called when the
//! ADC sample sequence interrupt occurs.
//!
//! This function sets the handler to be called when a sample sequence
//! interrupt occurs. This will enable the global interrupt in the interrupt
//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source via
//! ADCIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Determine the interrupt to register based on the sequence number.
//
ulInt = INT_ADC0 + ulSequenceNum;
//
// Register the interrupt handler.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the timer interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for an ADC interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller; the sequence interrupt must
//! be disabled via ADCIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Determine the interrupt to unregister based on the sequence number.
//
ulInt = INT_ADC0 + ulSequenceNum;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Disables a sample sequence interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function disables the requested sample sequence interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Disable this sample sequence interrupt.
//
HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
}
//*****************************************************************************
//
//! Enables a sample sequence interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function enables the requested sample sequence interrupt. Any
//! outstanding interrupts are cleared before enabling the sample sequence
//! interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Clear any outstanding interrupts on this sample sequence.
//
HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
//
// Enable this sample sequence interrupt.
//
HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified sample sequence.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current raw or masked interrupt status.
//
//*****************************************************************************
unsigned long
ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
}
else
{
return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
}
}
//*****************************************************************************
//
//! Clears sample sequence interrupt source.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! The specified sample sequence interrupt is cleared, so that it no longer
//! asserts. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Clear the interrupt.
//
HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Enables a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! Allows the specified sample sequence to be captured when its trigger is
//! detected. A sample sequence must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Enable the specified sequence.
//
HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Disables a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! Prevents the specified sample sequence from being captured when its trigger
//! is detected. A sample sequence should be disabled before it is configured.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Disable the specified sequences.
//
HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
}
//*****************************************************************************
//
//! Configures the trigger source and priority of a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulTrigger is the trigger source that initiates the sample sequence;
//! must be one of the \b ADC_TRIGGER_* values.
//! \param ulPriority is the relative priority of the sample sequence with
//! respect to the other sample sequences.
//!
//! This function configures the initiation criteria for a sample sequence.
//! Valid sample sequences range from zero to three; sequence zero will capture
//! up to eight samples, sequences one and two will capture up to four samples,
//! and sequence three will capture a single sample. The trigger condition and
//! priority (with respect to other sample sequence execution) is set.
//!
//! The \e ulTrigger parameter can take on the following values:
//!
//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
//! ADCProcessorTrigger() function.
//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
//! B4 pin.
//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
//! TimerControlTrigger().
//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
//! sample sequence to capture repeatedly (so long as
//! there is not a higher priority source active).
//!
//! Note that not all trigger sources are available on all Stellaris family
//! members; consult the data sheet for the device in question to determine the
//! availability of triggers.
//!
//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
//! the highest priority and 3 the lowest. Note that when programming the
//! priority among a set of sample sequences, each must have unique priority;
//! it is up to the caller to guarantee the uniqueness of the priorities.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long ulTrigger, unsigned long ulPriority)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
(ulTrigger == ADC_TRIGGER_COMP0) ||
(ulTrigger == ADC_TRIGGER_COMP1) ||
(ulTrigger == ADC_TRIGGER_COMP2) ||
(ulTrigger == ADC_TRIGGER_EXTERNAL) ||
(ulTrigger == ADC_TRIGGER_TIMER) ||
(ulTrigger == ADC_TRIGGER_PWM0) ||
(ulTrigger == ADC_TRIGGER_PWM1) ||
(ulTrigger == ADC_TRIGGER_PWM2) ||
(ulTrigger == ADC_TRIGGER_ALWAYS));
ASSERT(ulPriority < 4);
//
// Compute the shift for the bits that control this sample sequence.
//
ulSequenceNum *= 4;
//
// Set the trigger event for this sample sequence.
//
HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
~(0xf << ulSequenceNum)) |
((ulTrigger & 0xf) << ulSequenceNum));
//
// Set the priority for this sample sequence.
//
HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
~(0xf << ulSequenceNum)) |
((ulPriority & 0x3) << ulSequenceNum));
}
//*****************************************************************************
//
//! Configure a step of the sample sequencer.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step; must be a logical OR of
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
//!
//! This function will set the configuration of the ADC for one step of a
//! sample sequence. The ADC can be configured for single-ended or
//! differential operation (the \b ADC_CTL_D bit selects differential
//! operation when set), the channel to be sampled can be chosen (the
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
//! can be configured to cause an interrupt when the step is complete (the
//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
//! appropriate time when the trigger for this sequence occurs.
//!
//! The \e ulStep parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
//! seven for the first sample sequence, from zero to three for the second and
//! third sample sequence, and can only be zero for the fourth sample sequence.
//!
//! Differential mode only works with adjacent channel pairs (for example, 0
//! and 1). The channel select must be the number of the channel pair to
//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
//! and 3) or undefined results will be returned by the ADC. Additionally, if
//! differential mode is selected when the temperature sensor is being sampled,
//! undefined results will be returned by the ADC.
//!
//! It is the responsibility of the caller to ensure that a valid configuration
//! is specified; this function does not check the validity of the specified
//! configuration.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long ulStep, unsigned long ulConfig)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
((ulSequenceNum == 1) && (ulStep < 4)) ||
((ulSequenceNum == 2) && (ulStep < 4)) ||
((ulSequenceNum == 3) && (ulStep < 1)));
//
// Get the offset of the sequence to be configured.
//
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
//
// Compute the shift for the bits that control this step.
//
ulStep *= 4;
//
// Set the analog mux value for this step.
//
HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the control value for this step.
//
HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf0) >> 4) << ulStep));
}
//*****************************************************************************
//
//! Determines if a sample sequence overflow occurred.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence overflow has occurred. This will
//! happen if the captured samples are not read from the FIFO before the next
//! trigger occurs.
//!
//! \return Returns zero if there was not an overflow, and non-zero if there
//! was.
//
//*****************************************************************************
long
ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Determine if there was an overflow on this sequence.
//
return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
}
//*****************************************************************************
//
//! Clears the overflow condition on a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an overflow condition on one of the sample sequences. The
//! overflow condition must be cleared in order to detect a subsequent overflow
//! condition (it otherwise causes no harm).
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Clear the overflow condition for this sequence.
//
HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Determines if a sample sequence underflow occurred.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence underflow has occurred. This will
//! happen if too many samples are read from the FIFO.
//!
//! \return Returns zero if there was not an underflow, and non-zero if there
//! was.
//
//*****************************************************************************
long
ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Determine if there was an underflow on this sequence.
//
return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
}
//*****************************************************************************
//
//! Clears the underflow condition on a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an underflow condition on one of the sample sequences. The
//! underflow condition must be cleared in order to detect a subsequent
//! underflow condition (it otherwise causes no harm).
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Clear the underflow condition for this sequence.
//
HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Gets the captured data for a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer. The number of samples available in the hardware
//! FIFO are copied into the buffer, which is assumed to be large enough to
//! hold that many samples. This will only return the samples that are
//! presently available, which may not be the entire sample sequence if it is
//! in the process of being executed.
//!
//! \return Returns the number of samples copied to the buffer.
//
//*****************************************************************************
long
ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long *pulBuffer)
{
unsigned long ulCount;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Get the offset of the sequence to be read.
//
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
//
// Read samples from the FIFO until it is empty.
//
ulCount = 0;
while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
{
//
// Read the FIFO and copy it to the destination.
//
*pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
//
// Increment the count of samples read.
//
ulCount++;
}
//
// Return the number of samples read.
//
return(ulCount);
}
//*****************************************************************************
//
//! Causes a processor trigger for a sample sequence.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function triggers a processor-initiated sample sequence if the sample
//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
//!
//! \return None.
//
//*****************************************************************************
void
ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Generate a processor trigger for this sample sequence.
//
HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
}
//*****************************************************************************
//
//! Configures the software oversampling factor of the ADC.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulFactor is the number of samples to be averaged.
//!
//! This function configures the software oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input.
//! Three different oversampling rates are supported; 2x, 4x, and 8x.
//!
//! Oversampling is only supported on the sample sequencers that are more than
//! one sample in depth (that is, the fourth sample sequencer is not
//! supported). Oversampling by 2x (for example) divides the depth of the
//! sample sequencer by two; so 2x oversampling on the first sample sequencer
//! can only provide four samples per trigger. This also means that 8x
//! oversampling is only available on the first sample sequencer.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor)
{
unsigned long ulValue;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
((ulSequenceNum == 0) || (ulFactor != 8)));
//
// Convert the oversampling factor to a shift factor.
//
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
{
}
//
// Save the sfiht factor.
//
g_pucOversampleFactor[ulSequenceNum] = ulValue;
}
//*****************************************************************************
//
//! Configures a step of the software oversampled sequencer.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step.
//!
//! This function configures a step of the sample sequencer when using the
//! software oversampling feature. The number of steps available depends on
//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
(ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
//
// Get the offset of the sequence to be configured.
//
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
//
// Compute the shift for the bits that control this step.
//
ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
//
// Loop through the hardware steps that make up this step of the software
// oversampled sequence.
//
for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
ulSequenceNum; ulSequenceNum--)
{
//
// Set the analog mux value for this step.
//
HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the control value for this step.
//
HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf0) >> 4) << ulStep));
if(ulSequenceNum != 1)
{
HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
ADC_SSCTL0_END0) << ulStep);
}
//
// Go to the next hardware step.
//
ulStep += 4;
}
}
//*****************************************************************************
//
//! Gets the captured data for a sample sequence using software oversampling.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//! \param ulCount is the number of samples to be read.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer with software oversampling applied. The requested
//! number of samples are copied into the data buffer; if there are not enough
//! samples in the hardware FIFO to satisfy this many oversampled data items
//! then incorrect results will be returned. It is the caller's responsibility
//! to read only the samples that are available and wait until enough data is
//! available, for example as a result of receiving an interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long *pulBuffer, unsigned long ulCount)
{
unsigned long ulIdx, ulAccum;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
(ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
//
// Get the offset of the sequence to be read.
//
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
//
// Read the samples from the FIFO until it is empty.
//
while(ulCount--)
{
//
// Compute the sum of the samples.
//
ulAccum = 0;
for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
{
//
// Read the FIFO and add it to the accumulator.
//
ulAccum += HWREG(ulBase + ADC_SSFIFO);
}
//
// Write the averaged sample to the output buffer.
//
*pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
}
}
//*****************************************************************************
//
//! Configures the hardware oversampling factor of the ADC.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulFactor is the number of samples to be averaged.
//!
//! This function configures the hardware oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input. Six
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
//! Specifying an oversampling factor of zero will disable hardware
//! oversampling.
//!
//! Hardware oversampling applies uniformly to all sample sequencers. It does
//! not reduce the depth of the sample sequencers like the software
//! oversampling APIs; each sample written into the sample sequence FIFO is a
//! fully oversampled analog input reading.
//!
//! Enabling hardware averaging increases the precision of the ADC at the cost
//! of throughput. For example, enabling 4x oversampling reduces the
//! throughput of a 250 Ksps ADC to 62.5 Ksps.
//!
//! \note Hardware oversampling is available beginning with Rev C0 of the
//! Stellaris microcontroller.
//!
//! \return None.
//
//*****************************************************************************
void
ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
{
unsigned long ulValue;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
(ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
(ulFactor == 64)));
//
// Convert the oversampling factor to a shift factor.
//
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
{
}
//
// Write the shift factor to the ADC to configure the hardware oversampler.
//
HWREG(ulBase + ADC_O_SAC) = ulValue;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceOverflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CAN_H__
#define __CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
//! These are the flags used by the tCANMsgObject variable when calling the
//! CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
typedef enum
{
//
//! This indicates that transmit interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_TX_INT_ENABLE = 0x00000001,
//
//! This indicates that receive interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_RX_INT_ENABLE = 0x00000002,
//
//! This indicates that a message object will use or is using an extended
//! identifier.
//
MSG_OBJ_EXTENDED_ID = 0x00000004,
//
//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.
//
MSG_OBJ_USE_ID_FILTER = 0x00000008,
//
//! This indicates that new data was available in the message object.
//
MSG_OBJ_NEW_DATA = 0x00000080,
//
//! This indicates that data was lost since this message object was last
//! read.
//
MSG_OBJ_DATA_LOST = 0x00000100,
//
//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object is a remote frame.
//
MSG_OBJ_REMOTE_FRAME = 0x00000040,
//
//! This indicates that a message object has no flags set.
//
MSG_OBJ_NO_FLAGS = 0x00000000
}
tCANObjFlags;
//*****************************************************************************
//
//! This define is used with the #tCANObjFlags enumerated values to allow
//! checking only status flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
unsigned long ulMsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
unsigned long ulMsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
unsigned long ulFlags;
//
//! This value is the number of bytes of data in the message object.
//
unsigned long ulMsgLen;
//
//! This is a pointer to the message object's data.
//
unsigned char *pucMsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
//! These definitions are used to specify interrupt sources to CANIntEnable()
//! and CANIntDisable().
//
//*****************************************************************************
typedef enum
{
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
CAN_INT_ERROR = 0x00000008,
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
CAN_INT_STATUS = 0x00000004,
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts will be generated
//! by the CAN controller.
//
CAN_INT_MASTER = 0x00000002
}
tCANIntFlags;
//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
//! The following enumeration contains all error or status indicators that can
//! be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! CAN controller has entered a Bus Off state.
//
CAN_STATUS_BUS_OFF = 0x00000080,
//
//! CAN controller error level has reached warning level.
//
CAN_STATUS_EWARN = 0x00000040,
//
//! CAN controller error level has reached error passive level.
//
CAN_STATUS_EPASS = 0x00000020,
//
//! A message was received successfully since the last read of this status.
//
CAN_STATUS_RXOK = 0x00000010,
//
//! A message was transmitted successfully since the last read of this
//! status.
//
CAN_STATUS_TXOK = 0x00000008,
//
//! This is the mask for the last error code field.
//
CAN_STATUS_LEC_MSK = 0x00000007,
//
//! There was no error.
//
CAN_STATUS_LEC_NONE = 0x00000000,
//
//! A bit stuffing error has occurred.
//
CAN_STATUS_LEC_STUFF = 0x00000001,
//
//! A formatting error has occurred.
//
CAN_STATUS_LEC_FORM = 0x00000002,
//
//! An acknowledge error has occurred.
//
CAN_STATUS_LEC_ACK = 0x00000003,
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
CAN_STATUS_LEC_BIT1 = 0x00000004,
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
CAN_STATUS_LEC_BIT0 = 0x00000005,
//
//! A CRC error has occurred.
//
CAN_STATUS_LEC_CRC = 0x00000006,
//
//! This is the mask for the CAN Last Error Code (LEC).
//
CAN_STATUS_LEC_MASK = 0x00000007
}
tCANStatusCtrl;
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern unsigned long CANBitRateSet(unsigned long ulBase,
unsigned long ulSourceClock,
unsigned long ulBitRate);
extern void CANDisable(unsigned long ulBase);
extern void CANEnable(unsigned long ulBase);
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
unsigned long *pulTxCount);
extern void CANInit(unsigned long ulBase);
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern unsigned long CANIntStatus(unsigned long ulBase,
tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(unsigned long ulBase);
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern tBoolean CANRetryGet(unsigned long ulBase);
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Several CAN APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#define CANSetBitTiming(a, b) CANBitTimingSet(a, b)
#define CANGetBitTiming(a, b) CANBitTimingGet(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __CAN_H__

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//*****************************************************************************
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup comp_api
//! @{
//
//*****************************************************************************
#include "inc/hw_comp.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/comp.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
//! Configures a comparator.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
//!
//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
//! high.
//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
//! or high.
//!
//! The \b COMP_INT_xxx term can take on the following values:
//!
//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
//! high.
//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
//! low.
//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
//! low.
//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
//! high.
//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
//! low or high.
//!
//! The \b COMP_ASRCP_xxx term can take on the following values:
//!
//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
//! voltage.
//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
//! the same as \b COMP_ASRCP_PIN for the comparator 0).
//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
//! reference voltage.
//!
//! The \b COMP_OUTPUT_xxx term can take on the following values:
//!
//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
//! to a device pin.
//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
//! a device pin.
//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as
//! \b COMP_OUTPUT_NORMAL.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Configure this comparator.
//
HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;
}
//*****************************************************************************
//
//! Sets the internal reference voltage.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulRef is the desired reference voltage.
//!
//! This function will set the internal reference voltage value. The voltage
//! is specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
//
// Set the voltage reference voltage as requested.
//
HWREG(ulBase + COMP_O_ACREFCTL) = ulRef;
}
//*****************************************************************************
//
//! Gets the current comparator output value.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function retrieves the current value of the comparator output.
//!
//! \return Returns \b true if the comparator output is high and \b false if
//! the comparator output is low.
//
//*****************************************************************************
tBoolean
ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return the appropriate value based on the comparator's present output
// value.
//
if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL)
{
return(true);
}
else
{
return(false);
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This sets the handler to be called when the comparator interrupt occurs.
//! This will enable the interrupt in the interrupt controller; it is the
//! interrupt-handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_COMP0 + ulComp, pfnHandler);
//
// Enable the interrupt in the interrupt controller.
//
IntEnable(INT_COMP0 + ulComp);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function will clear the handler to be called when a comparator
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
//
// Disable the interrupt in the interrupt controller.
//
IntDisable(INT_COMP0 + ulComp);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_COMP0 + ulComp);
}
//*****************************************************************************
//
//! Enables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
}
//*****************************************************************************
//
//! Disables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the comparator. Either the raw or
//! the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
//! asserted.
//
//*****************************************************************************
tBoolean
ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false);
}
else
{
return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false);
}
}
//*****************************************************************************
//
//! Clears a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! must be done in the interrupt handler to keep it from being called again
//! immediately upon exit. Note that for a level triggered interrupt, the
//! interrupt cannot be cleared until it stops asserting.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Clear the interrupt.
//
HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and combined together with values from the other
// groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#ifndef DEPRECATED
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#endif
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#include "driverlib/cpu.h"
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUcpsid(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs %0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
mrs r0, PRIMASK;
cpsid i;
bx lr
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUcpsie(void)
{
unsigned long ulRet;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs %0, PRIMASK\n"
" cpsie i\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
mrs r0, PRIMASK;
cpsie i;
bx lr
}
#endif
//*****************************************************************************
//
// Wrapper function for the WFI instruction.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
void __attribute__((naked))
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n");
}
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
wfi;
bx lr
}
#endif

60
bsp/lm3s/Libraries/driverlib/cpu.h Normal file
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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern void CPUwfi(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

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bsp/lm3s/Libraries/driverlib/cr_project.xml Normal file
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<!--
Configuration file for Code Red project libdriver
Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
Software License Agreement
Luminary Micro, Inc. (LMI) is supplying this software for use solely and
exclusively on LMI's microcontroller products.
The software is owned by LMI and/or its suppliers, and is protected under
applicable copyright laws. All rights are reserved. You may not combine
this software with "viral" open-source software in order to form a larger
program. Any use in violation of the foregoing restrictions may subject
the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 4694 of the Stellaris Peripheral Driver Library.
-->
<project chip="LM3S101"
target="driver"
type="Static library"
vendor="LMI">
<import src=".">
<exclude>{(Makefile|codered|ewarm|gcc|rvmdk|sourcerygxx)}</exclude>
<exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|Uv2|xml|ld)}</exclude>
</import>
<requires>
<value>inc</value>
</requires>
<setting id="assembler.def">
<value>codered</value>
</setting>
<setting id="compiler.def"
buildType="Debug"
mode="replace">
<value>DEBUG</value>
</setting>
<setting id="compiler.def"
buildType="Release"
mode="replace">
<value>NDEBUG</value>
</setting>
<setting id="compiler.def">
<value>__CODE_RED</value>
<value>codered</value>
<value>PART_LM3S101</value>
</setting>
<setting id="compiler.opt"
buildType="Debug">
<value>-O2</value>
</setting>
<setting id="compiler.opt"
buildType="Release">
<value>-O2</value>
</setting>
<setting id="compiler.inc">
<value>${workspace_loc:/}</value>
</setting>
</project>

56
bsp/lm3s/Libraries/driverlib/debug.h Normal file
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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

59
bsp/lm3s/Libraries/driverlib/driverlib.Opt Normal file
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### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
GRPOPT 1,(Source),1,0,0
GRPOPT 2,(Documentation),0,0,0
OPTFFF 1,1,1,0,0,0,0,0,<.\adc.c><adc.c>
OPTFFF 1,2,1,0,0,0,0,0,<.\can.c><can.c>
OPTFFF 1,3,1,0,0,0,0,0,<.\comp.c><comp.c>
OPTFFF 1,4,1,0,0,0,0,0,<.\cpu.c><cpu.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\epi.c><epi.c>
OPTFFF 1,6,1,0,0,0,0,0,<.\ethernet.c><ethernet.c>
OPTFFF 1,7,1,0,0,0,0,0,<.\flash.c><flash.c>
OPTFFF 1,8,1,0,0,0,0,0,<.\gpio.c><gpio.c>
OPTFFF 1,9,1,0,0,0,0,0,<.\hibernate.c><hibernate.c>
OPTFFF 1,10,1,0,0,0,0,0,<.\i2c.c><i2c.c>
OPTFFF 1,11,1,0,0,0,0,0,<.\i2s.c><i2s.c>
OPTFFF 1,12,1,0,0,0,0,0,<.\interrupt.c><interrupt.c>
OPTFFF 1,13,1,0,0,0,0,0,<.\mpu.c><mpu.c>
OPTFFF 1,14,1,0,0,0,0,0,<.\pwm.c><pwm.c>
OPTFFF 1,15,1,0,0,0,0,0,<.\qei.c><qei.c>
OPTFFF 1,16,1,0,0,0,0,0,<.\ssi.c><ssi.c>
OPTFFF 1,17,1,0,0,0,0,0,<.\sysctl.c><sysctl.c>
OPTFFF 1,18,1,0,0,0,0,0,<.\systick.c><systick.c>
OPTFFF 1,19,1,0,0,0,0,0,<.\timer.c><timer.c>
OPTFFF 1,20,1,738197506,0,707,707,0,<.\uart.c><uart.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,182,2,0,0,196,0,0,0 }
OPTFFF 1,21,1,0,0,0,0,0,<.\udma.c><udma.c>
OPTFFF 1,22,1,0,0,0,0,0,<.\usb.c><usb.c>
OPTFFF 1,23,1,0,0,0,0,0,<.\watchdog.c><watchdog.c>
OPTFFF 2,24,5,0,0,0,0,0,<.\readme.txt><readme.txt>
TARGOPT 1, (driverlib)
ADSCLK=6000000
OPTTT 0,1,1,0
OPTHX 1,65535,0,0,0
OPTLX 79,66,8,<.\rvmdk\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTAX 0
OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
OPTDF 0x0
OPTLE <>
OPTLC <>
EndOpt

124
bsp/lm3s/Libraries/driverlib/driverlib.Uv2 Normal file
View File

@ -0,0 +1,124 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
Group (Source)
Group (Documentation)
File 1,1,<.\adc.c><adc.c>
File 1,1,<.\can.c><can.c>
File 1,1,<.\comp.c><comp.c>
File 1,1,<.\cpu.c><cpu.c>
File 1,1,<.\epi.c><epi.c>
File 1,1,<.\ethernet.c><ethernet.c>
File 1,1,<.\flash.c><flash.c>
File 1,1,<.\gpio.c><gpio.c>
File 1,1,<.\hibernate.c><hibernate.c>
File 1,1,<.\i2c.c><i2c.c>
File 1,1,<.\i2s.c><i2s.c>
File 1,1,<.\interrupt.c><interrupt.c>
File 1,1,<.\mpu.c><mpu.c>
File 1,1,<.\pwm.c><pwm.c>
File 1,1,<.\qei.c><qei.c>
File 1,1,<.\ssi.c><ssi.c>
File 1,1,<.\sysctl.c><sysctl.c>
File 1,1,<.\systick.c><systick.c>
File 1,1,<.\timer.c><timer.c>
File 1,1,<.\uart.c><uart.c>
File 1,1,<.\udma.c><udma.c>
File 1,1,<.\usb.c><usb.c>
File 1,1,<.\watchdog.c><watchdog.c>
File 2,5,<.\readme.txt><readme.txt>
Options 1,0,0 // Target 'driverlib'
Device (LM3S6965)
Vendor (Luminary Micro)
Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3"))
FlashUt ()
StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))
FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000))
DevID (4337)
Rgf (LM3Sxxxx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿLuminary\)
OrgReg (ÿLuminary\)
TgStat=16
OutDir (.\rvmdk\)
OutName (driverlib)
GenApp=0
GenLib=1
GenHex=0
Debug=1
Browse=1
LstDir (.\rvmdk\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP ("Cortex-M3")
RVDEV ()
ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
OCMADSIROM { 1,0,0,0,0,0,0,4,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
RV_STAVEC ()
ADSCCFLG { 12,34,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN (rvmdk)
ADSCUDEF ()
ADSCINCD (..;)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x00000000)
ADSLDDA (0x20000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC ()
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2CM3.DLL)
FLASH3 ("" ())
FLASH4 ()
EndOpt

839
bsp/lm3s/Libraries/driverlib/driverlib.ewp Normal file
View File

@ -0,0 +1,839 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>1</fileVersion>
<configuration>
<name>Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>14</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>ExePath</name>
<state>ewarm\Exe</state>
</option>
<option>
<name>ObjPath</name>
<state>ewarm\Obj</state>
</option>
<option>
<name>ListPath</name>
<state>ewarm\List</state>
</option>
<option>
<name>Variant</name>
<version>7</version>
<state>31</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
</option>
<option>
<name>Input variant</name>
<version>1</version>
<state>0</state>
</option>
<option>
<name>Input description</name>
<state>Full formatting.</state>
</option>
<option>
<name>Output variant</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>Output description</name>
<state>Full formatting.</state>
</option>
<option>
<name>GOutputBinary</name>
<state>1</state>
</option>
<option>
<name>FPU</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelect</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>RTDescription</name>
<state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
</option>
<option>
<name>RTConfigPath</name>
<state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>
</option>
<option>
<name>OGProductVersion</name>
<state>5.11.0.50579</state>
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>5.11.0.50579</state>
</option>
<option>
<name>GeneralMisraRules</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>LM3S101 Luminary LM3S101</state>
</option>
<option>
<name>GenLowLevelInterface</name>
<state>1</state>
</option>
<option>
<name>GEndianModeBE</name>
<state>1</state>
</option>
<option>
<name>OGBufferedTerminalOutput</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>19</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCDefines</name>
<state>ewarm</state>
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
</option>
<option>
<name>CCListCFile</name>
<state>0</state>
</option>
<option>
<name>CCListCMnemonics</name>
<state>0</state>
</option>
<option>
<name>CCListCMessages</name>
<state>0</state>
</option>
<option>
<name>CCListAssFile</name>
<state>0</state>
</option>
<option>
<name>CCListAssSource</name>
<state>0</state>
</option>
<option>
<name>CCEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>CCDiagSuppress</name>
<state>Pa050</state>
</option>
<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
</option>
<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
<option>
<name>CCAllowList</name>
<version>1</version>
<state>1111111</state>
</option>
<option>
<name>CCDebugInfo</name>
<state>1</state>
</option>
<option>
<name>IEndianMode</name>
<state>1</state>
</option>
<option>
<name>IProcessor</name>
<state>1</state>
</option>
<option>
<name>IExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>IExtraOptions</name>
<state></state>
</option>
<option>
<name>CCLangConformance</name>
<state>0</state>
</option>
<option>
<name>CCSignedPlainChar</name>
<state>1</state>
</option>
<option>
<name>CCRequirePrototypes</name>
<state>0</state>
</option>
<option>
<name>CCMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>CCDiagWarnAreErr</name>
<state>0</state>
</option>
<option>
<name>CCCompilerRuntimeInfo</name>
<state>0</state>
</option>
<option>
<name>IFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>CCLangSelect</name>
<state>0</state>
</option>
<option>
<name>CCLibConfigHeader</name>
<state>1</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraRules</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
</option>
<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCStdIncludePath</name>
<state>$TOOLKIT_DIR$\INC\</state>
</option>
<option>
<name>CCCodeSection</name>
<state>.text</state>
</option>
<option>
<name>IInterwork2</name>
<state>0</state>
</option>
<option>
<name>IProcessorMode2</name>
<state>1</state>
</option>
<option>
<name>CCOptLevel</name>
<state>3</state>
</option>
<option>
<name>CCOptStrategy</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCOptLevelSlave</name>
<state>3</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>7</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>AObjPrefix</name>
<state>1</state>
</option>
<option>
<name>AEndian</name>
<state>1</state>
</option>
<option>
<name>ACaseSensitivity</name>
<state>1</state>
</option>
<option>
<name>MacroChars</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>AWarnEnable</name>
<state>0</state>
</option>
<option>
<name>AWarnWhat</name>
<state>0</state>
</option>
<option>
<name>AWarnOne</name>
<state></state>
</option>
<option>
<name>AWarnRange1</name>
<state></state>
</option>
<option>
<name>AWarnRange2</name>
<state></state>
</option>
<option>
<name>ADebug</name>
<state>1</state>
</option>
<option>
<name>AltRegisterNames</name>
<state>0</state>
</option>
<option>
<name>ADefines</name>
<state>ewarm</state>
</option>
<option>
<name>AList</name>
<state>0</state>
</option>
<option>
<name>AListHeader</name>
<state>1</state>
</option>
<option>
<name>AListing</name>
<state>1</state>
</option>
<option>
<name>Includes</name>
<state>0</state>
</option>
<option>
<name>MacDefs</name>
<state>0</state>
</option>
<option>
<name>MacExps</name>
<state>1</state>
</option>
<option>
<name>MacExec</name>
<state>0</state>
</option>
<option>
<name>OnlyAssed</name>
<state>0</state>
</option>
<option>
<name>MultiLine</name>
<state>0</state>
</option>
<option>
<name>PageLengthCheck</name>
<state>0</state>
</option>
<option>
<name>PageLength</name>
<state>80</state>
</option>
<option>
<name>TabSpacing</name>
<state>8</state>
</option>
<option>
<name>AXRef</name>
<state>0</state>
</option>
<option>
<name>AXRefDefines</name>
<state>0</state>
</option>
<option>
<name>AXRefInternal</name>
<state>0</state>
</option>
<option>
<name>AXRefDual</name>
<state>0</state>
</option>
<option>
<name>AProcessor</name>
<state>1</state>
</option>
<option>
<name>AFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>AOutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>AMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsCheck</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsEdit</name>
<state>100</state>
</option>
<option>
<name>AIgnoreStdInclude</name>
<state>0</state>
</option>
<option>
<name>AStdIncludes</name>
<state>$TOOLKIT_DIR$\INC\</state>
</option>
<option>
<name>AUserIncludes</name>
<state></state>
</option>
<option>
<name>AExtraOptionsCheckV2</name>
<state>0</state>
</option>
<option>
<name>AExtraOptionsV2</name>
<state></state>
</option>
</data>
</settings>
<settings>
<name>OBJCOPY</name>
<archiveVersion>0</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
<version>1</version>
<state>0</state>
</option>
<option>
<name>OCOutputOverride</name>
<state>0</state>
</option>
<option>
<name>OOCOutputFile</name>
<state>driverlib.srec</state>
</option>
<option>
<name>OOCCommandLineProducer</name>
<state>1</state>
</option>
<option>
<name>OOCObjCopyEnable</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>CUSTOM</name>
<archiveVersion>3</archiveVersion>
<data>
<extensions></extensions>
<cmdline></cmdline>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
<data>
<prebuild></prebuild>
<postbuild></postbuild>
</data>
</settings>
<settings>
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>5</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
</option>
<option>
<name>IlinkOutputFile</name>
<state>driverlib.out</state>
</option>
<option>
<name>IlinkDebugInfoEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkKeepSymbols</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryFile</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySymbol</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySegment</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryAlign</name>
<state></state>
</option>
<option>
<name>IlinkDefines</name>
<state></state>
</option>
<option>
<name>IlinkConfigDefines</name>
<state></state>
</option>
<option>
<name>IlinkMapFile</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFile</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInitialization</name>
<state>0</state>
</option>
<option>
<name>IlinkLogModule</name>
<state>0</state>
</option>
<option>
<name>IlinkLogSection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogVeneer</name>
<state>0</state>
</option>
<option>
<name>IlinkIcfOverride</name>
<state>0</state>
</option>
<option>
<name>IlinkIcfFile</name>
<state>lnk0t.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
<state></state>
</option>
<option>
<name>IlinkEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>IlinkSuppressDiags</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsRem</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsWarn</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsErr</name>
<state></state>
</option>
<option>
<name>IlinkWarningsAreErrors</name>
<state>0</state>
</option>
<option>
<name>IlinkUseExtraOptions</name>
<state>0</state>
</option>
<option>
<name>IlinkExtraOptions</name>
<state></state>
</option>
<option>
<name>IlinkLowLevelInterfaceSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkAutoLibEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkAdditionalLibs</name>
<state></state>
</option>
<option>
<name>IlinkOverrideProgramEntryLabel</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabelSelect</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabel</name>
<state></state>
</option>
<option>
<name>IlinkNXPLPCChecksum</name>
<state>0</state>
</option>
<option>
<name>DoFill</name>
<state>0</state>
</option>
<option>
<name>FillerByte</name>
<state>0xFF</state>
</option>
<option>
<name>FillerStart</name>
<state>0x0</state>
</option>
<option>
<name>FillerEnd</name>
<state>0x0</state>
</option>
<option>
<name>CrcSize</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
</option>
<option>
<name>CrcCompl</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcBitOrder</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcInitialValue</name>
<state>0x0</state>
</option>
<option>
<name>DoCrc</name>
<state>0</state>
</option>
<option>
<name>IlinkBE8Slave</name>
<state>1</state>
</option>
<option>
<name>IlinkBufferedTerminalOutput</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>IARCHIVE</name>
<archiveVersion>0</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IarchiveInputs</name>
<state></state>
</option>
<option>
<name>IarchiveOverride</name>
<state>0</state>
</option>
<option>
<name>IarchiveOutput</name>
<state>$PROJ_DIR$\ewarm\Exe\driverlib.a</state>
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
</configuration>
<group>
<name>Source</name>
<file>
<name>$PROJ_DIR$\adc.c</name>
</file>
<file>
<name>$PROJ_DIR$\can.c</name>
</file>
<file>
<name>$PROJ_DIR$\comp.c</name>
</file>
<file>
<name>$PROJ_DIR$\cpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\epi.c</name>
</file>
<file>
<name>$PROJ_DIR$\ethernet.c</name>
</file>
<file>
<name>$PROJ_DIR$\flash.c</name>
</file>
<file>
<name>$PROJ_DIR$\gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\hibernate.c</name>
</file>
<file>
<name>$PROJ_DIR$\i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\i2s.c</name>
</file>
<file>
<name>$PROJ_DIR$\interrupt.c</name>
</file>
<file>
<name>$PROJ_DIR$\mpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\pwm.c</name>
</file>
<file>
<name>$PROJ_DIR$\qei.c</name>
</file>
<file>
<name>$PROJ_DIR$\ssi.c</name>
</file>
<file>
<name>$PROJ_DIR$\sysctl.c</name>
</file>
<file>
<name>$PROJ_DIR$\systick.c</name>
</file>
<file>
<name>$PROJ_DIR$\timer.c</name>
</file>
<file>
<name>$PROJ_DIR$\uart.c</name>
</file>
<file>
<name>$PROJ_DIR$\udma.c</name>
</file>
<file>
<name>$PROJ_DIR$\usb.c</name>
</file>
<file>
<name>$PROJ_DIR$\watchdog.c</name>
</file>
</group>
</project>

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bsp/lm3s/Libraries/driverlib/driverlib.sgxx Normal file
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bsp/lm3s/Libraries/driverlib/epi.h Normal file
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//*****************************************************************************
//
// epi.h - Prototypes and macros for the EPI module.
//
// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __EPI_H__
#define __EPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EPIModeSet()
//
//*****************************************************************************
#define EPI_MODE_NONE 0x00000010
#define EPI_MODE_SDRAM 0x00000011
#define EPI_MODE_HB8 0x00000012
#define EPI_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
//
//*****************************************************************************
#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000
#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000
#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000
#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000
#define EPI_SDRAM_LOW_POWER 0x00000200
#define EPI_SDRAM_FULL_POWER 0x00000000
#define EPI_SDRAM_SIZE_64MBIT 0x00000000
#define EPI_SDRAM_SIZE_128MBIT 0x00000001
#define EPI_SDRAM_SIZE_256MBIT 0x00000002
#define EPI_SDRAM_SIZE_512MBIT 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigNoModeSet()
//
//*****************************************************************************
#define EPI_NONMODE_CLKPIN 0x80000000
#define EPI_NONMODE_CLKSTOP 0x40000000
#define EPI_NONMODE_CLKENA 0x10000000
#define EPI_NONMODE_FRAMEPIN 0x08000000
#define EPI_NONMODE_FRAME50 0x04000000
#define EPI_NONMODE_READWRITE 0x00200000
#define EPI_NONMODE_WRITE2CYCLE 0x00080000
#define EPI_NONMODE_READ2CYCLE 0x00040000
#define EPI_NONMODE_ASIZE_NONE 0x00000000
#define EPI_NONMODE_ASIZE_4 0x00000010
#define EPI_NONMODE_ASIZE_12 0x00000020
#define EPI_NONMODE_ASIZE_20 0x00000030
#define EPI_NONMODE_DSIZE_8 0x00000000
#define EPI_NONMODE_DSIZE_16 0x00000001
#define EPI_NONMODE_DSIZE_24 0x00000002
#define EPI_NONMODE_DSIZE_32 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB8ModeSet()
//
//*****************************************************************************
#define EPI_HB8_USE_TXEMPTY 0x00800000
#define EPI_HB8_USE_RXFULL 0x00400000
#define EPI_HB8_WRHIGH 0x00200000
#define EPI_HB8_RDHIGH 0x00100000
#define EPI_HB8_WRWAIT_0 0x00000000
#define EPI_HB8_WRWAIT_1 0x00000040
#define EPI_HB8_WRWAIT_2 0x00000080
#define EPI_HB8_WRWAIT_3 0x000000C0
#define EPI_HB8_RDWAIT_0 0x00000000
#define EPI_HB8_RDWAIT_1 0x00000010
#define EPI_HB8_RDWAIT_2 0x00000020
#define EPI_HB8_RDWAIT_3 0x00000030
#define EPI_HB8_MODE_ADMUX 0x00000000
#define EPI_HB8_MODE_ADDEMUX 0x00000001
#define EPI_HB8_MODE_SRAM 0x00000002
#define EPI_HB8_MODE_FIFO 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
//
//*****************************************************************************
#define EPI_ADDR_PER_SIZE_256B 0x00000000
#define EPI_ADDR_PER_SIZE_64KB 0x00000040
#define EPI_ADDR_PER_SIZE_16MB 0x00000080
#define EPI_ADDR_PER_SIZE_512MB 0x000000C0
#define EPI_ADDR_PER_BASE_NONE 0x00000000
#define EPI_ADDR_PER_BASE_A 0x00000010
#define EPI_ADDR_PER_BASE_C 0x00000020
#define EPI_ADDR_RAM_SIZE_256B 0x00000000
#define EPI_ADDR_RAM_SIZE_64KB 0x00000004
#define EPI_ADDR_RAM_SIZE_16MB 0x00000008
#define EPI_ADDR_RAM_SIZE_512MB 0x0000000C
#define EPI_ADDR_RAM_BASE_NONE 0x00000000
#define EPI_ADDR_RAM_BASE_6 0x00000001
#define EPI_ADDR_RAM_BASE_8 0x00000002
//*****************************************************************************
//
// Values that can be passed to EPINonBlockingReadConfigure()
//
//*****************************************************************************
#define EPI_NBCONFIG_SIZE_8 1
#define EPI_NBCONFIG_SIZE_16 2
#define EPI_NBCONFIG_SIZE_32 3
//*****************************************************************************
//
// Values that can be passed to EPIFIFOConfig()
//
//*****************************************************************************
#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000
#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000
#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000
#define EPI_FIFO_CONFIG_TX_1_4 0x00000020
#define EPI_FIFO_CONFIG_TX_1_2 0x00000030
#define EPI_FIFO_CONFIG_TX_3_4 0x00000040
#define EPI_FIFO_CONFIG_RX_1_8 0x00000001
#define EPI_FIFO_CONFIG_RX_1_4 0x00000002
#define EPI_FIFO_CONFIG_RX_1_2 0x00000003
#define EPI_FIFO_CONFIG_RX_3_4 0x00000004
#define EPI_FIFO_CONFIG_RX_7_8 0x00000005
#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
//*****************************************************************************
//
// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
// as flags from EPIIntStatus()
//
//*****************************************************************************
#define EPI_INT_TXREQ 0x00000004
#define EPI_INT_RXREQ 0x00000002
#define EPI_INT_ERR 0x00000001
//*****************************************************************************
//
// Values that can be passed to EPIIntErrorClear(), or returned as flags from
// EPIIntErrorStatus()
//
//*****************************************************************************
#define EPI_INT_ERR_WTFULL 0x00000004
#define EPI_INT_ERR_RSTALL 0x00000002
#define EPI_INT_ERR_TIMEOUT 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulRefresh);
void EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulFrameCount, unsigned long ulMaxWait);
void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
void EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDataSize, unsigned long ulAddress);
void EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulCount);
void EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel);
unsigned long EPINonBlockingReadCount(unsigned long ulBase,
unsigned long ulChannel);
unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
unsigned long ulCount,
unsigned long *pulBuf);
unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
unsigned long ulCount,
unsigned short *pusBuf);
unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
unsigned long ulCount,
unsigned char *pucBuf);
void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
unsigned long EPINonBlockingWriteCount(unsigned long ulBase);
void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
unsigned long EPIIntErrorStatus(unsigned long ulBase);
void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
void EPIIntUnregister(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EPI_H__

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//*****************************************************************************
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ETHERNET_H__
#define __ETHERNET_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EthernetConfigSet as the ulConfig value, and
// returned from EthernetConfigGet.
//
//*****************************************************************************
#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
//*****************************************************************************
//
// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
// EthernetIntClear as the ulIntFlags parameter, and returned from
// EthernetIntStatus.
//
//*****************************************************************************
#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
#define ETH_INT_MDIO 0x020 // Management Transaction
#define ETH_INT_RXER 0x010 // RX Error
#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
#define ETH_INT_TX 0x004 // TX Complete
#define ETH_INT_TXER 0x002 // TX Error
#define ETH_INT_RX 0x001 // RX Complete
//*****************************************************************************
//
// Helper Macros for Ethernet Processing
//
//*****************************************************************************
//
// htonl/ntohl - big endian/little endian byte swapping macros for
// 32-bit (long) values
//
//*****************************************************************************
#ifndef htonl
#define htonl(a) \
((((a) >> 24) & 0x000000ff) | \
(((a) >> 8) & 0x0000ff00) | \
(((a) << 8) & 0x00ff0000) | \
(((a) << 24) & 0xff000000))
#endif
#ifndef ntohl
#define ntohl(a) htonl((a))
#endif
//*****************************************************************************
//
// htons/ntohs - big endian/little endian byte swapping macros for
// 16-bit (short) values
//
//*****************************************************************************
#ifndef htons
#define htons(a) \
((((a) >> 8) & 0x00ff) | \
(((a) << 8) & 0xff00))
#endif
#ifndef ntohs
#define ntohs(a) htons((a))
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long EthernetConfigGet(unsigned long ulBase);
extern void EthernetMACAddrSet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetMACAddrGet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetEnable(unsigned long ulBase);
extern void EthernetDisable(unsigned long ulBase);
extern tBoolean EthernetPacketAvail(unsigned long ulBase);
extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern void EthernetIntRegister(unsigned long ulBase,
void (*pfnHandler)(void));
extern void EthernetIntUnregister(unsigned long ulBase);
extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
//*****************************************************************************
//
// Several Ethernet APIs have been renamed, with the original function name
// being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define EthernetInit(a) \
EthernetInitExpClk(a, SysCtlClockGet())
#define EthernetPacketNonBlockingGet(a, b, c) \
EthernetPacketGetNonBlocking(a, b, c)
#define EthernetPacketNonBlockingPut(a, b, c) \
EthernetPacketPutNonBlocking(a, b, c)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ETHERNET_H__

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//*****************************************************************************
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "inc/hw_flash.h"
#include "inc/hw_ints.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/flash.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Program Enable (FMPPE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPPERegs[] =
{
FLASH_FMPPE,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3
};
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Read Enable (FMPRE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPRERegs[] =
{
FLASH_FMPRE,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3
};
//*****************************************************************************
//
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//!
//! \return Returns the number of processor clocks per micro-second.
//
//*****************************************************************************
unsigned long
FlashUsecGet(void)
{
//
// Return the number of clocks per micro-second.
//
return(HWREG(FLASH_USECRL) + 1);
}
//*****************************************************************************
//
//! Sets the number of processor clocks per micro-second.
//!
//! \param ulClocks is the number of processor clocks per micro-second.
//!
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//!
//! \return None.
//
//*****************************************************************************
void
FlashUsecSet(unsigned long ulClocks)
{
//
// Set the number of clocks per micro-second.
//
HWREG(FLASH_USECRL) = ulClocks - 1;
}
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access interrupt.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
//
// Erase the block.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
//
// Wait until the block has been erased.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
{
}
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a word can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access interrupt.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
//
// See if this device has a write buffer.
//
if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words.
//
HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
{
}
}
}
else
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMD) = *pulData;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Calculate the Flash Bank from Base Address, and mask off the Bank
// from ulAddress for subsequent reference.
//
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
//
// Read the appropriate flash protection registers for the specified
// flash bank.
//
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG protect options, and are
// not available for the FLASH protection scheme. When Querying Block
// Protection, assume these bits are 1.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
}
//
// Check the appropriate protection bits for the block of memory that
// is specified by the address.
//
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fetch interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (that is, it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
//*****************************************************************************
//
//! Sets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be protected.
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (that is, read-only to read/write) will
//! result in a failure (and be prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
//! protection was specified.
//
//*****************************************************************************
long
FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
unsigned long ulProtectRE, ulProtectPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
(eProtect == FlashExecuteOnly));
//
// Convert the address into a block number.
//
ulAddress /= FLASH_PROTECT_SIZE;
//
// ulAddress contains a "raw" block number. Derive the Flash Bank from
// the "raw" block number, and convert ulAddress to a "relative"
// block number.
//
ulBank = ((ulAddress / 32) % 4);
ulAddress %= 32;
//
// Get the current protection for the specified flash bank.
//
ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG protect options, and are
// not available for the FLASH protection scheme. When setting protection,
// check to see if block 30 or 31 and protection is FlashExecuteOnly. If
// so, return an error condition.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
{
return(-1);
}
}
//
// Set the protection based on the requested proection.
//
switch(eProtect)
{
//
// Make this block execute only.
//
case FlashExecuteOnly:
{
//
// Turn off the read and program bits for this block.
//
ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read only.
//
case FlashReadOnly:
{
//
// The block can not be made read only if it is execute only.
//
if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0)
{
return(-1);
}
//
// Make this block read only.
//
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read/write.
//
case FlashReadWrite:
default:
{
//
// The block can not be made read/write if it is not already
// read/write.
//
if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0) ||
(((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0))
{
return(-1);
}
//
// The block is already read/write, so there is nothing to do.
//
return(0);
}
}
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG options, and are not
// available for the FLASH protection scheme. When setting block
// protection, ensure that these bits are not altered.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
}
//
// Set the new protection for the specified flash bank.
//
HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashProtectSave(void)
{
int ulTemp, ulLimit;
//
// If running on a Sandstorm-class device, only trigger a save of the first
// two protection registers (FMPRE and FMPPE). Otherwise, save the
// entire bank of flash protection registers.
//
ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
{
//
// Tell the flash controller to write the flash protection register.
//
HWREG(FLASH_FMA) = ulTemp;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the user registers.
//!
//! \param pulUser0 is a pointer to the location to store USER Register 0.
//! \param pulUser1 is a pointer to the location to store USER Register 1.
//!
//! This function will read the contents of user registers (0 and 1), and
//! store them in the specified locations.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
{
//
// Verify that the pointers are valid.
//
ASSERT(pulUser0 != 0);
ASSERT(pulUser1 != 0);
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Get and store the current value of the user registers.
//
*pulUser0 = HWREG(FLASH_USERREG0);
*pulUser1 = HWREG(FLASH_USERREG1);
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Sets the user registers.
//!
//! \param ulUser0 is the value to store in USER Register 0.
//! \param ulUser1 is the value to store in USER Register 1.
//!
//! This function will set the contents of the user registers (0 and 1) to
//! the specified values.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
{
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Save the new values into the user registers.
//
HWREG(FLASH_USERREG0) = ulUser0;
HWREG(FLASH_USERREG1) = ulUser1;
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Saves the user registers.
//!
//! This function will make the currently programmed user register settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change this setting.
//!
//! This function will not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserSave(void)
{
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Setting the MSB of FMA will trigger a permanent save of a USER
// register. Bit 0 will indicate User 0 (0) or User 1 (1).
//
HWREG(FLASH_FMA) = 0x80000000;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Tell the flash controller to write the USER1 Register.
//
HWREG(FLASH_FMA) = 0x80000001;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_FCIM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_FCIM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
//
//*****************************************************************************
unsigned long
FlashIntGetStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_FCMISC));
}
else
{
return(HWREG(FLASH_FCRIS));
}
}
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_FCMISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
extern long FlashUserSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
//
//*****************************************************************************
//
// GPIO pin A0
//
#define GPIO_PA0_U0RX 0x00000001
#define GPIO_PA0_I2C1SCL 0x00000008
#define GPIO_PA0_U1RX 0x00000009
//
// GPIO pin A1
//
#define GPIO_PA1_U0TX 0x00000401
#define GPIO_PA1_I2C1SDA 0x00000408
#define GPIO_PA1_U1TX 0x00000409
//
// GPIO pin A2
//
#define GPIO_PA2_SSI0CLK 0x00000801
#define GPIO_PA2_PWM4 0x00000804
#define GPIO_PA2_I2S0RXSD 0x00000809
//
// GPIO pin A3
//
#define GPIO_PA3_SSI0FSS 0x00000c01
#define GPIO_PA3_PWM5 0x00000c04
#define GPIO_PA3_I2S0RXMCLK 0x00000c09
//
// GPIO pin A4
//
#define GPIO_PA4_SSI0RX 0x00001001
#define GPIO_PA4_PWM6 0x00001004
#define GPIO_PA4_CAN0RX 0x00001005
#define GPIO_PA4_I2S0TXSCK 0x00001009
//
// GPIO pin A5
//
#define GPIO_PA5_SSI0TX 0x00001401
#define GPIO_PA5_PWM7 0x00001404
#define GPIO_PA5_CAN0TX 0x00001405
#define GPIO_PA5_I2S0TXWS 0x00001409
//
// GPIO pin A6
//
#define GPIO_PA6_I2C1SCL 0x00001801
#define GPIO_PA6_CCP1 0x00001802
#define GPIO_PA6_PWM0 0x00001804
#define GPIO_PA6_PWM4 0x00001805
#define GPIO_PA6_CAN0RX 0x00001806
#define GPIO_PA6_USB0EPEN 0x00001808
#define GPIO_PA6_U1CTS 0x00001809
//
// GPIO pin A7
//
#define GPIO_PA7_I2C1SDA 0x00001c01
#define GPIO_PA7_CCP4 0x00001c02
#define GPIO_PA7_PWM1 0x00001c04
#define GPIO_PA7_PWM5 0x00001c05
#define GPIO_PA7_CAN0TX 0x00001c06
#define GPIO_PA7_CCP3 0x00001c07
#define GPIO_PA7_USB0PFLT 0x00001c08
#define GPIO_PA7_U1DCD 0x00001c09
//
// GPIO pin B0
//
#define GPIO_PB0_CCP0 0x00010001
#define GPIO_PB0_PWM2 0x00010002
#define GPIO_PB0_U1RX 0x00010005
//
// GPIO pin B1
//
#define GPIO_PB1_CCP2 0x00010401
#define GPIO_PB1_PWM3 0x00010402
#define GPIO_PB1_CCP1 0x00010404
#define GPIO_PB1_U1TX 0x00010405
//
// GPIO pin B2
//
#define GPIO_PB2_I2C0SCL 0x00010801
#define GPIO_PB2_IDX0 0x00010802
#define GPIO_PB2_CCP3 0x00010804
#define GPIO_PB2_CCP0 0x00010805
#define GPIO_PB2_USB0EPEN 0x00010808
//
// GPIO pin B3
//
#define GPIO_PB3_I2C0SDA 0x00010c01
#define GPIO_PB3_FAULT0 0x00010c02
#define GPIO_PB3_FAULT3 0x00010c04
#define GPIO_PB3_USB0PFLT 0x00010c08
//
// GPIO pin B4
//
#define GPIO_PB4_U2RX 0x00011004
#define GPIO_PB4_CAN0RX 0x00011005
#define GPIO_PB4_IDX0 0x00011006
#define GPIO_PB4_U1RX 0x00011007
#define GPIO_PB4_EPI0S23 0x00011008
//
// GPIO pin B5
//
#define GPIO_PB5_C0O 0x00011401
#define GPIO_PB5_CCP5 0x00011402
#define GPIO_PB5_CCP6 0x00011403
#define GPIO_PB5_CCP0 0x00011404
#define GPIO_PB5_CAN0TX 0x00011405
#define GPIO_PB5_CCP2 0x00011406
#define GPIO_PB5_U1TX 0x00011407
#define GPIO_PB5_EPI0S22 0x00011408
//
// GPIO pin B6
//
#define GPIO_PB6_CCP1 0x00011801
#define GPIO_PB6_CCP7 0x00011802
#define GPIO_PB6_C0O 0x00011803
#define GPIO_PB6_FAULT1 0x00011804
#define GPIO_PB6_IDX0 0x00011805
#define GPIO_PB6_CCP5 0x00011806
#define GPIO_PB6_I2S0TXSCK 0x00011809
//
// GPIO pin B7
//
#define GPIO_PB7_NMI 0x00011c04
//
// GPIO pin C0
//
#define GPIO_PC0_TCK 0x00020003
//
// GPIO pin C1
//
#define GPIO_PC1_TMS 0x00020403
//
// GPIO pin C2
//
#define GPIO_PC2_TDI 0x00020803
//
// GPIO pin C3
//
#define GPIO_PC3_TDO 0x00020c03
//
// GPIO pin C4
//
#define GPIO_PC4_CCP5 0x00021001
#define GPIO_PC4_PHA0 0x00021002
#define GPIO_PC4_PWM6 0x00021004
#define GPIO_PC4_CCP2 0x00021005
#define GPIO_PC4_CCP4 0x00021006
#define GPIO_PC4_EPI0S2 0x00021008
#define GPIO_PC4_CCP1 0x00021009
//
// GPIO pin C5
//
#define GPIO_PC5_CCP1 0x00021401
#define GPIO_PC5_C1O 0x00021402
#define GPIO_PC5_C0O 0x00021403
#define GPIO_PC5_FAULT2 0x00021404
#define GPIO_PC5_CCP3 0x00021405
#define GPIO_PC5_USB0EPEN 0x00021406
#define GPIO_PC5_EPI0S3 0x00021408
//
// GPIO pin C6
//
#define GPIO_PC6_CCP3 0x00021801
#define GPIO_PC6_PHB0 0x00021802
#define GPIO_PC6_C2O 0x00021803
#define GPIO_PC6_PWM7 0x00021804
#define GPIO_PC6_U1RX 0x00021805
#define GPIO_PC6_CCP0 0x00021806
#define GPIO_PC6_USB0PFLT 0x00021807
#define GPIO_PC6_EPI0S4 0x00021808
//
// GPIO pin C7
//
#define GPIO_PC7_CCP4 0x00021c01
#define GPIO_PC7_PHB0 0x00021c02
#define GPIO_PC7_CCP0 0x00021c04
#define GPIO_PC7_U1TX 0x00021c05
#define GPIO_PC7_USB0PFLT 0x00021c06
#define GPIO_PC7_C1O 0x00021c07
#define GPIO_PC7_EPI0S5 0x00021c08
//
// GPIO pin D0
//
#define GPIO_PD0_PWM0 0x00030001
#define GPIO_PD0_CAN0RX 0x00030002
#define GPIO_PD0_IDX0 0x00030003
#define GPIO_PD0_U2RX 0x00030004
#define GPIO_PD0_U1RX 0x00030005
#define GPIO_PD0_CCP6 0x00030006
#define GPIO_PD0_I2S0RXSCK 0x00030008
#define GPIO_PD0_U1CTS 0x00030009
//
// GPIO pin D1
//
#define GPIO_PD1_PWM1 0x00030401
#define GPIO_PD1_CAN0TX 0x00030402
#define GPIO_PD1_PHA0 0x00030403
#define GPIO_PD1_U2TX 0x00030404
#define GPIO_PD1_U1TX 0x00030405
#define GPIO_PD1_CCP7 0x00030406
#define GPIO_PD1_I2S0RXWS 0x00030408
#define GPIO_PD1_U1DCD 0x00030409
#define GPIO_PD1_CCP2 0x0003040a
#define GPIO_PD1_PHB1 0x0003040b
//
// GPIO pin D2
//
#define GPIO_PD2_U1RX 0x00030801
#define GPIO_PD2_CCP6 0x00030802
#define GPIO_PD2_PWM2 0x00030803
#define GPIO_PD2_CCP5 0x00030804
#define GPIO_PD2_EPI0S20 0x00030808
//
// GPIO pin D3
//
#define GPIO_PD3_U1TX 0x00030c01
#define GPIO_PD3_CCP7 0x00030c02
#define GPIO_PD3_PWM3 0x00030c03
#define GPIO_PD3_CCP0 0x00030c04
#define GPIO_PD3_EPI0S21 0x00030c08
//
// GPIO pin D4
//
#define GPIO_PD4_CCP0 0x00031001
#define GPIO_PD4_CCP3 0x00031002
#define GPIO_PD4_I2S0RXSD 0x00031008
#define GPIO_PD4_U1RI 0x00031009
#define GPIO_PD4_EPI0S19 0x0003100a
//
// GPIO pin D5
//
#define GPIO_PD5_CCP2 0x00031401
#define GPIO_PD5_CCP4 0x00031402
#define GPIO_PD5_I2S0RXMCLK 0x00031408
#define GPIO_PD5_U2RX 0x00031409
#define GPIO_PD5_EPI0S28 0x0003140a
//
// GPIO pin D6
//
#define GPIO_PD6_FAULT0 0x00031801
#define GPIO_PD6_I2S0TXSCK 0x00031808
#define GPIO_PD6_U2TX 0x00031809
#define GPIO_PD6_EPI0S29 0x0003180a
//
// GPIO pin D7
//
#define GPIO_PD7_IDX0 0x00031c01
#define GPIO_PD7_C0O 0x00031c02
#define GPIO_PD7_CCP1 0x00031c03
#define GPIO_PD7_I2S0TXWS 0x00031c08
#define GPIO_PD7_U1DTR 0x00031c09
#define GPIO_PD7_EPI0S30 0x00031c0a
//
// GPIO pin E0
//
#define GPIO_PE0_PWM4 0x00040001
#define GPIO_PE0_SSI1CLK 0x00040002
#define GPIO_PE0_CCP3 0x00040003
#define GPIO_PE0_EPI0S8 0x00040008
#define GPIO_PE0_USB0PFLT 0x00040009
//
// GPIO pin E1
//
#define GPIO_PE1_PWM5 0x00040401
#define GPIO_PE1_SSI1FSS 0x00040402
#define GPIO_PE1_FAULT0 0x00040403
#define GPIO_PE1_CCP2 0x00040404
#define GPIO_PE1_CCP6 0x00040405
#define GPIO_PE1_EPI0S9 0x00040408
//
// GPIO pin E2
//
#define GPIO_PE2_CCP4 0x00040801
#define GPIO_PE2_SSI1RX 0x00040802
#define GPIO_PE2_PHB1 0x00040803
#define GPIO_PE2_PHA0 0x00040804
#define GPIO_PE2_CCP2 0x00040805
#define GPIO_PE2_EPI0S24 0x00040808
//
// GPIO pin E3
//
#define GPIO_PE3_CCP1 0x00040c01
#define GPIO_PE3_SSI1TX 0x00040c02
#define GPIO_PE3_PHA1 0x00040c03
#define GPIO_PE3_PHB0 0x00040c04
#define GPIO_PE3_CCP7 0x00040c05
#define GPIO_PE3_EPI0S25 0x00040c08
//
// GPIO pin E4
//
#define GPIO_PE4_CCP3 0x00041001
#define GPIO_PE4_FAULT0 0x00041004
#define GPIO_PE4_U2TX 0x00041005
#define GPIO_PE4_CCP2 0x00041006
#define GPIO_PE4_I2S0TXWS 0x00041009
//
// GPIO pin E5
//
#define GPIO_PE5_CCP5 0x00041401
#define GPIO_PE5_I2S0TXSD 0x00041409
//
// GPIO pin E6
//
#define GPIO_PE6_PWM4 0x00041801
#define GPIO_PE6_C1O 0x00041802
#define GPIO_PE6_U1CTS 0x00041809
//
// GPIO pin E7
//
#define GPIO_PE7_PWM5 0x00041c01
#define GPIO_PE7_C2O 0x00041c02
#define GPIO_PE7_U1DCD 0x00041c09
//
// GPIO pin F0
//
#define GPIO_PF0_CAN1RX 0x00050001
#define GPIO_PF0_PHB0 0x00050002
#define GPIO_PF0_PWM0 0x00050003
#define GPIO_PF0_I2S0TXSD 0x00050008
#define GPIO_PF0_U1DSR 0x00050009
//
// GPIO pin F1
//
#define GPIO_PF1_CAN1TX 0x00050401
#define GPIO_PF1_IDX1 0x00050402
#define GPIO_PF1_PWM1 0x00050403
#define GPIO_PF1_I2S0TXMCLK 0x00050408
#define GPIO_PF1_U1RTS 0x00050409
#define GPIO_PF1_CCP3 0x0005040a
//
// GPIO pin F2
//
#define GPIO_PF2_LED1 0x00050801
#define GPIO_PF2_PWM4 0x00050802
#define GPIO_PF2_PWM2 0x00050804
#define GPIO_PF2_SSI1CLK 0x00050809
//
// GPIO pin F3
//
#define GPIO_PF3_LED0 0x00050c01
#define GPIO_PF3_PWM5 0x00050c02
#define GPIO_PF3_PWM3 0x00050c04
#define GPIO_PF3_SSI1FSS 0x00050c09
//
// GPIO pin F4
//
#define GPIO_PF4_CCP0 0x00051001
#define GPIO_PF4_C0O 0x00051002
#define GPIO_PF4_FAULT0 0x00051004
#define GPIO_PF4_EPI0S12 0x00051008
#define GPIO_PF4_SSI1RX 0x00051009
//
// GPIO pin F5
//
#define GPIO_PF5_CCP2 0x00051401
#define GPIO_PF5_C1O 0x00051402
#define GPIO_PF5_EPI0S15 0x00051408
#define GPIO_PF5_SSI1TX 0x00051409
//
// GPIO pin F6
//
#define GPIO_PF6_CCP1 0x00051801
#define GPIO_PF6_C2O 0x00051802
#define GPIO_PF6_PHA0 0x00051804
#define GPIO_PF6_I2S0TXMCLK 0x00051809
#define GPIO_PF6_U1RTS 0x0005180a
//
// GPIO pin F7
//
#define GPIO_PF7_CCP4 0x00051c01
#define GPIO_PF7_PHB0 0x00051c04
#define GPIO_PF7_EPI0S12 0x00051c08
#define GPIO_PF7_FAULT1 0x00051c09
//
// GPIO pin G0
//
#define GPIO_PG0_U2RX 0x00060001
#define GPIO_PG0_PWM0 0x00060002
#define GPIO_PG0_I2C1SCL 0x00060003
#define GPIO_PG0_PWM4 0x00060004
#define GPIO_PG0_USB0EPEN 0x00060007
#define GPIO_PG0_EPI0S13 0x00060008
//
// GPIO pin G1
//
#define GPIO_PG1_U2TX 0x00060401
#define GPIO_PG1_PWM1 0x00060402
#define GPIO_PG1_I2C1SDA 0x00060403
#define GPIO_PG1_PWM5 0x00060404
#define GPIO_PG1_EPI0S14 0x00060408
//
// GPIO pin G2
//
#define GPIO_PG2_PWM0 0x00060801
#define GPIO_PG2_FAULT0 0x00060804
#define GPIO_PG2_IDX1 0x00060808
#define GPIO_PG2_I2S0RXSD 0x00060809
//
// GPIO pin G3
//
#define GPIO_PG3_PWM1 0x00060c01
#define GPIO_PG3_FAULT2 0x00060c04
#define GPIO_PG3_FAULT0 0x00060c08
#define GPIO_PG3_I2S0RXMCLK 0x00060c09
//
// GPIO pin G4
//
#define GPIO_PG4_CCP3 0x00061001
#define GPIO_PG4_FAULT1 0x00061004
#define GPIO_PG4_EPI0S15 0x00061008
#define GPIO_PG4_PWM6 0x00061009
#define GPIO_PG4_U1RI 0x0006100a
//
// GPIO pin G5
//
#define GPIO_PG5_CCP5 0x00061401
#define GPIO_PG5_IDX0 0x00061404
#define GPIO_PG5_FAULT1 0x00061405
#define GPIO_PG5_PWM7 0x00061408
#define GPIO_PG5_I2S0RXSCK 0x00061409
#define GPIO_PG5_U1DTR 0x0006140a
//
// GPIO pin G6
//
#define GPIO_PG6_PHA1 0x00061801
#define GPIO_PG6_PWM6 0x00061804
#define GPIO_PG6_FAULT1 0x00061808
#define GPIO_PG6_I2S0RXWS 0x00061809
#define GPIO_PG6_U1RI 0x0006180a
//
// GPIO pin G7
//
#define GPIO_PG7_PHB1 0x00061c01
#define GPIO_PG7_PWM7 0x00061c04
#define GPIO_PG7_CCP5 0x00061c08
#define GPIO_PG7_EPI0S31 0x00061c09
//
// GPIO pin H0
//
#define GPIO_PH0_CCP6 0x00070001
#define GPIO_PH0_PWM2 0x00070002
#define GPIO_PH0_EPI0S6 0x00070008
#define GPIO_PH0_PWM4 0x00070009
//
// GPIO pin H1
//
#define GPIO_PH1_CCP7 0x00070401
#define GPIO_PH1_PWM3 0x00070402
#define GPIO_PH1_EPI0S7 0x00070408
#define GPIO_PH1_PWM5 0x00070409
//
// GPIO pin H2
//
#define GPIO_PH2_IDX1 0x00070801
#define GPIO_PH2_C1O 0x00070802
#define GPIO_PH2_FAULT3 0x00070804
#define GPIO_PH2_EPI0S1 0x00070808
//
// GPIO pin H3
//
#define GPIO_PH3_PHB0 0x00070c01
#define GPIO_PH3_FAULT0 0x00070c02
#define GPIO_PH3_USB0EPEN 0x00070c04
#define GPIO_PH3_EPI0S0 0x00070c08
//
// GPIO pin H4
//
#define GPIO_PH4_USB0PFLT 0x00071004
#define GPIO_PH4_EPI0S10 0x00071008
#define GPIO_PH4_SSI1CLK 0x0007100b
//
// GPIO pin H5
//
#define GPIO_PH5_EPI0S11 0x00071408
#define GPIO_PH5_FAULT2 0x0007140a
#define GPIO_PH5_SSI1FSS 0x0007140b
//
// GPIO pin H6
//
#define GPIO_PH6_EPI0S26 0x00071808
#define GPIO_PH6_PWM4 0x0007180a
#define GPIO_PH6_SSI1RX 0x0007180b
//
// GPIO pin H7
//
#define GPIO_PH7_EPI0S27 0x00071c08
#define GPIO_PH7_PWM5 0x00071c0a
#define GPIO_PH7_SSI1TX 0x00071c0b
//
// GPIO pin J0
//
#define GPIO_PJ0_EPI0S16 0x00080008
#define GPIO_PJ0_PWM0 0x0008000a
#define GPIO_PJ0_I2C1SCL 0x0008000b
//
// GPIO pin J1
//
#define GPIO_PJ1_EPI0S17 0x00080408
#define GPIO_PJ1_USB0PFLT 0x00080409
#define GPIO_PJ1_PWM1 0x0008040a
#define GPIO_PJ1_I2C1SDA 0x0008040b
//
// GPIO pin J2
//
#define GPIO_PJ2_EPI0S18 0x00080808
#define GPIO_PJ2_CCP0 0x00080809
#define GPIO_PJ2_FAULT0 0x0008080a
//
// GPIO pin J3
//
#define GPIO_PJ3_EPI0S19 0x00080c08
#define GPIO_PJ3_U1CTS 0x00080c09
#define GPIO_PJ3_CCP6 0x00080c0a
//
// GPIO pin J4
//
#define GPIO_PJ4_EPI0S28 0x00081008
#define GPIO_PJ4_U1DCD 0x00081009
#define GPIO_PJ4_CCP4 0x0008100a
//
// GPIO pin J5
//
#define GPIO_PJ5_EPI0S29 0x00081408
#define GPIO_PJ5_U1DSR 0x00081409
#define GPIO_PJ5_CCP2 0x0008140a
//
// GPIO pin J6
//
#define GPIO_PJ6_EPI0S30 0x00081808
#define GPIO_PJ6_U1RTS 0x00081809
#define GPIO_PJ6_CCP1 0x0008180a
//
// GPIO pin J7
//
#define GPIO_PJ7_U1DTR 0x00081c09
#define GPIO_PJ7_CCP0 0x00081c0a
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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bsp/lm3s/Libraries/driverlib/hibernate.c Normal file
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@ -0,0 +1,965 @@
//*****************************************************************************
//
// hibernate.c - Driver for the Hibernation module
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup hibernate_api
//! @{
//
//*****************************************************************************
#include "inc/hw_hibernate.h"
#include "inc/hw_ints.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/hibernate.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"
//*****************************************************************************
//
// The delay in microseconds for writing to the Hibernation module registers.
//
//*****************************************************************************
#define DELAY_USECS 95
//*****************************************************************************
//
// The number of processor cycles to execute one pass of the delay loop.
//
//*****************************************************************************
#define LOOP_CYCLES 3
//*****************************************************************************
//
// The calculated number of delay loops to achieve the write delay.
//
//*****************************************************************************
static unsigned long g_ulWriteDelay;
//*****************************************************************************
//
//! \internal
//!
//! Polls until the write complete (WRC) bit in the hibernate control register
//! is set.
//!
//! \param None.
//!
//! On non-Fury-class devices, the hibernate module provides an indication when
//! any write is completed. This is used to pace writes to the module. This
//! function merely polls this bit and returns as soon as it is set. At this
//! point, it is safe to perform another write to the module.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateWriteComplete(void)
{
//
// Spin until the write complete bit is set.
//
while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
{
}
}
//*****************************************************************************
//
//! Enables the Hibernation module for operation.
//!
//! \param ulHibClk is the rate of the clock supplied to the Hibernation
//! module.
//!
//! Enables the Hibernation module for operation. This function should be
//! called before any of the Hibernation module features are used.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//!
//! This function replaces the original HibernateEnable() API and performs the
//! same actions. A macro is provided in <tt>hibernate.h</tt> to map the
//! original API to this API.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateEnableExpClk(unsigned long ulHibClk)
{
//
// Turn on the clock enable bit.
//
HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;
//
// For Fury-class devices, compute the number of delay loops that must be
// used to achieve the desired delay for writes to the hibernation
// registers. This value will be used in calls to SysCtlDelay().
//
if(CLASS_IS_FURY)
{
g_ulWriteDelay = (((ulHibClk / 1000) * DELAY_USECS) /
(1000L * LOOP_CYCLES));
g_ulWriteDelay++;
}
}
//*****************************************************************************
//
//! Disables the Hibernation module for operation.
//!
//! Disables the Hibernation module for operation. After this function is
//! called, none of the Hibernation module features are available.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateDisable(void)
{
//
// Turn off the clock enable bit.
//
HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN;
}
//*****************************************************************************
//
//! Selects the clock input for the Hibernation module.
//!
//! \param ulClockInput specifies the clock input.
//!
//! Configures the clock input for the Hibernation module. The configuration
//! option chosen depends entirely on hardware design. The clock input for the
//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal.
//! The \e ulClockFlags parameter must be one of the following:
//!
//! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz
//! oscillator.
//! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the crystal input, divided by 128.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateClockSelect(unsigned long ulClockInput)
{
//
// Check the arguments.
//
ASSERT((ulClockInput == HIBERNATE_CLOCK_SEL_RAW) ||
(ulClockInput == HIBERNATE_CLOCK_SEL_DIV128));
//
// Set the clock selection bit according to the parameter.
//
HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL);
}
//*****************************************************************************
//
//! Enables the RTC feature of the Hibernation module.
//!
//! Enables the RTC in the Hibernation module. The RTC can be used to wake the
//! processor from hibernation at a certain time, or to generate interrupts at
//! certain times. This function must be called before using any of the RTC
//! features of the Hibernation module.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCEnable(void)
{
//
// Turn on the RTC enable bit.
//
HWREG(HIB_CTL) |= HIB_CTL_RTCEN;
}
//*****************************************************************************
//
//! Disables the RTC feature of the Hibernation module.
//!
//! Disables the RTC in the Hibernation module. After calling this function
//! the RTC features of the Hibernation module will not be available.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCDisable(void)
{
//
// Turn off the RTC enable bit.
//
HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN;
}
//*****************************************************************************
//
//! Configures the wake conditions for the Hibernation module.
//!
//! \param ulWakeFlags specifies which conditions should be used for waking.
//!
//! Enables the conditions under which the Hibernation module will wake. The
//! \e ulWakeFlags parameter is the logical OR of any combination of the
//! following:
//!
//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateWakeSet(unsigned long ulWakeFlags)
{
//
// Check the arguments.
//
ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
//
// Set the specified wake flags in the control register.
//
HWREG(HIB_CTL) = (ulWakeFlags |
(HWREG(HIB_CTL) &
~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
}
//*****************************************************************************
//
//! Gets the currently configured wake conditions for the Hibernation module.
//!
//! Returns the flags representing the wake configuration for the Hibernation
//! module. The return value will be a combination of the following flags:
//!
//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
//!
//! \return Returns flags indicating the configured wake conditions.
//
//*****************************************************************************
unsigned long
HibernateWakeGet(void)
{
//
// Read the wake bits from the control register and return
// those bits to the caller.
//
return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC));
}
//*****************************************************************************
//
//! Configures the low battery detection.
//!
//! \param ulLowBatFlags specifies behavior of low battery detection.
//!
//! Enables the low battery detection and whether hibernation is allowed if a
//! low battery is detected. If low battery detection is enabled, then a low
//! battery condition will be indicated in the raw interrupt status register,
//! and can also trigger an interrupt. Optionally, hibernation can be aborted
//! if a low battery is detected.
//!
//! The \e ulLowBatFlags parameter is one of the following values:
//!
//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
//! hibernation if low battery is detected.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateLowBatSet(unsigned long ulLowBatFlags)
{
//
// Check the arguments.
//
ASSERT((ulLowBatFlags == HIBERNATE_LOW_BAT_DETECT) ||
(ulLowBatFlags == HIBERNATE_LOW_BAT_ABORT));
//
// Set the low battery detect and abort bits in the control register,
// according to the parameter.
//
HWREG(HIB_CTL) = (ulLowBatFlags |
(HWREG(HIB_CTL) & ~HIBERNATE_LOW_BAT_ABORT));
}
//*****************************************************************************
//
//! Gets the currently configured low battery detection behavior.
//!
//! Returns a value representing the currently configured low battery detection
//! behavior. The return value will be one of the following:
//!
//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
//! hibernation if low battery is detected.
//!
//! \return Returns a value indicating the configured low battery detection.
//
//*****************************************************************************
unsigned long
HibernateLowBatGet(void)
{
//
// Read the low bat bits from the control register and return those bits to
// the caller.
//
return(HWREG(HIB_CTL) & HIBERNATE_LOW_BAT_ABORT);
}
//*****************************************************************************
//
//! Sets the value of the real time clock (RTC) counter.
//!
//! \param ulRTCValue is the new value for the RTC.
//!
//! Sets the value of the RTC. The RTC will count seconds if the hardware is
//! configured correctly. The RTC must be enabled by calling
//! HibernateRTCEnable() before calling this function.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCSet(unsigned long ulRTCValue)
{
//
// Write the new RTC value to the RTC load register.
//
HWREG(HIB_RTCLD) = ulRTCValue;
//
// Add a delay here to enforce the required delay between write accesses to
// certain Hibernation module registers.
//
if(CLASS_IS_FURY)
{
//
// Delay a fixed time on Fury-class devices
//
SysCtlDelay(g_ulWriteDelay);
}
else
{
//
// Wait for write complete to be signaled on later devices.
//
HibernateWriteComplete();
}
}
//*****************************************************************************
//
//! Gets the value of the real time clock (RTC) counter.
//!
//! Gets the value of the RTC and returns it to the caller.
//!
//! \return Returns the value of the RTC.
//
//*****************************************************************************
unsigned long
HibernateRTCGet(void)
{
//
// Return the value of the RTC counter register to the caller.
//
return(HWREG(HIB_RTCC));
}
//*****************************************************************************
//
//! Sets the value of the RTC match 0 register.
//!
//! \param ulMatch is the value for the match register.
//!
//! Sets the match 0 register for the RTC. The Hibernation module can be
//! configured to wake from hibernation, and/or generate an interrupt when the
//! value of the RTC counter is the same as the match register.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCMatch0Set(unsigned long ulMatch)
{
//
// Write the new match value to the match register.
//
HWREG(HIB_RTCM0) = ulMatch;
//
// Add a delay here to enforce the required delay between write accesses to
// certain Hibernation module registers.
//
if(CLASS_IS_FURY)
{
//
// Delay a fixed time on Fury-class devices
//
SysCtlDelay(g_ulWriteDelay);
}
else
{
//
// Wait for write complete to be signaled on later devices.
//
HibernateWriteComplete();
}
}
//*****************************************************************************
//
//! Gets the value of the RTC match 0 register.
//!
//! Gets the value of the match 0 register for the RTC.
//!
//! \return Returns the value of the match register.
//
//*****************************************************************************
unsigned long
HibernateRTCMatch0Get(void)
{
//
// Return the value of the match register to the caller.
//
return(HWREG(HIB_RTCM0));
}
//*****************************************************************************
//
//! Sets the value of the RTC match 1 register.
//!
//! \param ulMatch is the value for the match register.
//!
//! Sets the match 1 register for the RTC. The Hibernation module can be
//! configured to wake from hibernation, and/or generate an interrupt when the
//! value of the RTC counter is the same as the match register.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCMatch1Set(unsigned long ulMatch)
{
//
// Write the new match value to the match register.
//
HWREG(HIB_RTCM1) = ulMatch;
//
// Add a delay here to enforce the required delay between write accesses to
// certain Hibernation module registers.
//
if(CLASS_IS_FURY)
{
//
// Delay a fixed time on Fury-class devices
//
SysCtlDelay(g_ulWriteDelay);
}
else
{
//
// Wait for write complete to be signaled on later devices.
//
HibernateWriteComplete();
}
}
//*****************************************************************************
//
//! Gets the value of the RTC match 1 register.
//!
//! Gets the value of the match 1 register for the RTC.
//!
//! \return Returns the value of the match register.
//
//*****************************************************************************
unsigned long
HibernateRTCMatch1Get(void)
{
//
// Return the value of the match register to the caller.
//
return(HWREG(HIB_RTCM1));
}
//*****************************************************************************
//
//! Sets the value of the RTC predivider trim register.
//!
//! \param ulTrim is the new value for the pre-divider trim register.
//!
//! Sets the value of the pre-divider trim register. The input time source is
//! divided by the pre-divider to achieve a one-second clock rate. Once every
//! 64 seconds, the value of the pre-divider trim register is applied to the
//! predivider to allow fine-tuning of the RTC rate, in order to make
//! corrections to the rate. The software application can make adjustments to
//! the predivider trim register to account for variations in the accuracy of
//! the input time source. The nominal value is 0x7FFF, and it can be adjusted
//! up or down in order to fine-tune the RTC rate.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRTCTrimSet(unsigned long ulTrim)
{
//
// Check the arguments.
//
ASSERT(ulTrim < 0x10000);
//
// Write the new trim value to the trim register.
//
HWREG(HIB_RTCT) = ulTrim;
//
// Add a delay here to enforce the required delay between write accesses to
// certain Hibernation module registers.
//
if(CLASS_IS_FURY)
{
//
// Delay a fixed time on Fury-class devices
//
SysCtlDelay(g_ulWriteDelay);
}
else
{
//
// Wait for write complete to be signaled on later devices.
//
HibernateWriteComplete();
}
}
//*****************************************************************************
//
//! Gets the value of the RTC predivider trim register.
//!
//! Gets the value of the pre-divider trim register. This function can be used
//! to get the current value of the trim register prior to making an adjustment
//! by using the HibernateRTCTrimSet() function.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
HibernateRTCTrimGet(void)
{
//
// Return the value of the trim register to the caller.
//
return(HWREG(HIB_RTCT));
}
//*****************************************************************************
//
//! Stores data in the non-volatile memory of the Hibernation module.
//!
//! \param pulData points to the data that the caller wants to store in the
//! memory of the Hibernation module.
//! \param ulCount is the count of 32-bit words to store.
//!
//! Stores a set of data in the Hibernation module non-volatile memory. This
//! memory will be preserved when the power to the processor is turned off, and
//! can be used to store application state information which will be available
//! when the processor wakes. Up to 64 32-bit words can be stored in the
//! non-volatile memory. The data can be restored by calling the
//! HibernateDataGet() function.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateDataSet(unsigned long *pulData, unsigned long ulCount)
{
unsigned int uIdx;
//
// Check the arguments.
//
ASSERT(ulCount <= 64);
ASSERT(pulData != 0);
//
// Loop through all the words to be stored, storing one at a time.
//
for(uIdx = 0; uIdx < ulCount; uIdx++)
{
//
// Write a word to the non-volatile storage area.
//
HWREG(HIB_DATA + (uIdx * 4)) = pulData[uIdx];
//
// Add a delay between writes to the data area.
//
if(CLASS_IS_FURY)
{
//
// Delay a fixed time on Fury-class devices
//
SysCtlDelay(g_ulWriteDelay);
}
else
{
//
// Wait for write complete to be signaled on later devices.
//
HibernateWriteComplete();
}
}
}
//*****************************************************************************
//
//! Reads a set of data from the non-volatile memory of the Hibernation module.
//!
//! \param pulData points to a location where the data that is read from the
//! Hibernation module will be stored.
//! \param ulCount is the count of 32-bit words to read.
//!
//! Retrieves a set of data from the Hibernation module non-volatile memory
//! that was previously stored with the HibernateDataSet() function. The
//! caller must ensure that \e pulData points to a large enough memory block to
//! hold all the data that is read from the non-volatile memory.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateDataGet(unsigned long *pulData, unsigned long ulCount)
{
unsigned int uIdx;
//
// Check the arguments.
//
ASSERT(ulCount <= 64);
ASSERT(pulData != 0);
//
// Loop through all the words to be restored, reading one at a time.
//
for(uIdx = 0; uIdx < ulCount; uIdx++)
{
//
// Read a word from the non-volatile storage area. No delay is
// required between reads.
//
pulData[uIdx] = HWREG(HIB_DATA + (uIdx * 4));
}
}
//*****************************************************************************
//
//! Requests hibernation mode.
//!
//! This function requests the Hibernation module to disable the external
//! regulator, thus removing power from the processor and all peripherals. The
//! Hibernation module will remain powered from the battery or auxiliary power
//! supply.
//!
//! The Hibernation module will re-enable the external regulator when one of
//! the configured wake conditions occurs (such as RTC match or external
//! \b WAKE pin). When the power is restored the processor will go through a
//! normal power-on reset. The processor can retrieve saved state information
//! with the HibernateDataGet() function. Prior to calling the function to
//! request hibernation mode, the conditions for waking must have already been
//! set by using the HibernateWakeSet() function.
//!
//! Note that this function may return because some time may elapse before the
//! power is actually removed, or it may not be removed at all. For this
//! reason, the processor will continue to execute instructions for some time
//! and the caller should be prepared for this function to return. There are
//! various reasons why the power may not be removed. For example, if the
//! HibernateLowBatSet() function was used to configure an abort if low
//! battery is detected, then the power will not be removed if the battery
//! voltage is too low. There may be other reasons, related to the external
//! circuit design, that a request for hibernation may not actually occur.
//!
//! For all these reasons, the caller must be prepared for this function to
//! return. The simplest way to handle it is to just enter an infinite loop
//! and wait for the power to be removed.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateRequest(void)
{
//
// Set the bit in the control register to cut main power to the processor.
//
HWREG(HIB_CTL) |= HIB_CTL_HIBREQ;
}
//*****************************************************************************
//
//! Enables interrupts for the Hibernation module.
//!
//! \param ulIntFlags is the bit mask of the interrupts to be enabled.
//!
//! Enables the specified interrupt sources from the Hibernation module.
//!
//! The \e ulIntFlags parameter must be the logical OR of any combination of
//! the following:
//!
//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt
//! - \b HIBERNATE_INT_LOW_BAT - low battery interrupt
//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt
//! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt
//!
//! \return None.
//
//*****************************************************************************
void
HibernateIntEnable(unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
HIBERNATE_INT_RTC_MATCH_0 |
HIBERNATE_INT_RTC_MATCH_1)));
//
// Set the specified interrupt mask bits.
//
HWREG(HIB_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables interrupts for the Hibernation module.
//!
//! \param ulIntFlags is the bit mask of the interrupts to be disabled.
//!
//! Disables the specified interrupt sources from the Hibernation module.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to the HibernateIntEnable() function.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateIntDisable(unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
HIBERNATE_INT_RTC_MATCH_0 |
HIBERNATE_INT_RTC_MATCH_1)));
//
// Clear the specified interrupt mask bits.
//
HWREG(HIB_IM) &= ~ulIntFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for the Hibernation module interrupt.
//!
//! \param pfnHandler points to the function to be called when a hibernation
//! interrupt occurs.
//!
//! Registers the interrupt handler in the system interrupt controller. The
//! interrupt is enabled at the global level, but individual interrupt sources
//! must still be enabled with a call to HibernateIntEnable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_HIBERNATE, pfnHandler);
//
// Enable the hibernate module interrupt.
//
IntEnable(INT_HIBERNATE);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the Hibernation module interrupt.
//!
//! Unregisters the interrupt handler in the system interrupt controller. The
//! interrupt is disabled at the global level, and the interrupt handler will
//! no longer be called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
HibernateIntUnregister(void)
{
//
// Disable the hibernate interrupt.
//
IntDisable(INT_HIBERNATE);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_HIBERNATE);
}
//*****************************************************************************
//
//! Gets the current interrupt status of the Hibernation module.
//!
//! \param bMasked is false to retrieve the raw interrupt status, and true to
//! retrieve the masked interrupt status.
//!
//! Returns the interrupt status of the Hibernation module. The caller can use
//! this to determine the cause of a hibernation interrupt. Either the masked
//! or raw interrupt status can be returned.
//!
//! \return Returns the interrupt status as a bit field with the values as
//! described in the HibernateIntEnable() function.
//
//*****************************************************************************
unsigned long
HibernateIntStatus(tBoolean bMasked)
{
//
// Read and return the Hibernation module raw or masked interrupt status.
//
if(bMasked == true)
{
return(HWREG(HIB_MIS) & 0xf);
}
else
{
return(HWREG(HIB_RIS) & 0xf);
}
}
//*****************************************************************************
//
//! Clears pending interrupts from the Hibernation module.
//!
//! \param ulIntFlags is the bit mask of the interrupts to be cleared.
//!
//! Clears the specified interrupt sources. This must be done from within the
//! interrupt handler or else the handler will be called again upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to the HibernateIntEnable() function.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
HibernateIntClear(unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
HIBERNATE_INT_RTC_MATCH_0 |
HIBERNATE_INT_RTC_MATCH_1)));
//
// Write the specified interrupt bits into the interrupt clear register.
//
HWREG(HIB_IC) |= ulIntFlags;
}
//*****************************************************************************
//
//! Checks to see if the Hibernation module is already powered up.
//!
//! This function queries the control register to determine if the module is
//! already active. This function can be called at a power-on reset to help
//! determine if the reset is due to a wake from hibernation or a cold start.
//! If the Hibernation module is already active, then it does not need to be
//! re-enabled and its status can be queried immediately.
//!
//! The software application should also use the HibernateIntStatus() function
//! to read the raw interrupt status to determine the cause of the wake. The
//! HibernateDataGet() function can be used to restore state. These
//! combinations of functions can be used by the software to determine if the
//! processor is waking from hibernation and the appropriate action to take as
//! a result.
//!
//! \return Returns \b true if the module is already active, and \b false if
//! not.
//
//*****************************************************************************
unsigned int
HibernateIsActive(void)
{
//
// Read the control register, and return true if the module is enabled.
//
return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

130
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@ -0,0 +1,130 @@
//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HIBERNATE_H__
#define __HIBERNATE_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x04
#define HIBERNATE_CLOCK_SEL_DIV128 0x00
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x10
#define HIBERNATE_WAKE_RTC 0x08
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x20
#define HIBERNATE_LOW_BAT_ABORT 0xA0
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_PIN_WAKE 0x08
#define HIBERNATE_INT_LOW_BAT 0x04
#define HIBERNATE_INT_RTC_MATCH_0 0x01
#define HIBERNATE_INT_RTC_MATCH_1 0x02
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateEnableExpClk(unsigned long ulHibClk);
extern void HibernateDisable(void);
extern void HibernateClockSelect(unsigned long ulClockInput);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(unsigned long ulWakeFlags);
extern unsigned long HibernateWakeGet(void);
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
extern unsigned long HibernateLowBatGet(void);
extern void HibernateRTCSet(unsigned long ulRTCValue);
extern unsigned long HibernateRTCGet(void);
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch0Get(void);
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch1Get(void);
extern void HibernateRTCTrimSet(unsigned long ulTrim);
extern unsigned long HibernateRTCTrimGet(void);
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateRequest(void);
extern void HibernateIntEnable(unsigned long ulIntFlags);
extern void HibernateIntDisable(unsigned long ulIntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned int HibernateIsActive(void);
//*****************************************************************************
//
// Several Hibernate module APIs have been renamed, with the original function
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define HibernateEnable(a) \
HibernateEnableExpClk(a, SysCtlClockGet())
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HIBERNATE_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2CSlaveIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
//*****************************************************************************
//
// Several I2C APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define I2CMasterInit(a, b) \
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// i2s.h - Prototypes and macros for the I2S controller.
//
// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2S_H__
#define __I2S_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet()
//
//*****************************************************************************
#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP
#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP
#define I2S_CONFIG_FORMAT_LEFT_JUST \
0x00000000 // !JST, !DLY, !SCP, !LRP
#define I2S_CONFIG_FORMAT_RIGHT_JUST \
0x20000000 // JST, !DLY, !SCP, !LRP
#define I2S_CONFIG_SCLK_INVERT 0x08000000
#define I2S_CONFIG_MODE_MASK 0x03000000
#define I2S_CONFIG_MODE_DUAL 0x00000000
#define I2S_CONFIG_MODE_COMPACT_16 \
0x01000000
#define I2S_CONFIG_MODE_COMPACT_8 \
0x03000000
#define I2S_CONFIG_MODE_MONO 0x02000000
#define I2S_CONFIG_EMPTY_MASK 0x00800000
#define I2S_CONFIG_EMPTY_ZERO 0x00000000
#define I2S_CONFIG_EMPTY_REPEAT 0x00800000
#define I2S_CONFIG_CLK_MASK 0x00400000
#define I2S_CONFIG_CLK_MASTER 0x00400000
#define I2S_CONFIG_CLK_SLAVE 0x00000000
#define I2S_CONFIG_SAMPLE_SIZE_MASK \
0x0000FC00
#define I2S_CONFIG_SAMPLE_SIZE_32 \
0x00007C00
#define I2S_CONFIG_SAMPLE_SIZE_24 \
0x00005C00
#define I2S_CONFIG_SAMPLE_SIZE_20 \
0x00004C00
#define I2S_CONFIG_SAMPLE_SIZE_16 \
0x00003C00
#define I2S_CONFIG_SAMPLE_SIZE_8 \
0x00001C00
#define I2S_CONFIG_WIRE_SIZE_MASK \
0x000003F0
#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0
#define I2S_CONFIG_WIRE_SIZE_24 0x00000170
#define I2S_CONFIG_WIRE_SIZE_20 0x00000130
#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0
#define I2S_CONFIG_WIRE_SIZE_8 0x00000070
//*****************************************************************************
//
// Values that can be passed to I2SMasterClockSelect()
//
//*****************************************************************************
#define I2S_TX_MCLK_EXT 0x00000010
#define I2S_TX_MCLK_INT 0x00000000
#define I2S_RX_MCLK_EXT 0x00000020
#define I2S_RX_MCLK_INT 0x00000000
//*****************************************************************************
//
// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and
// I2SIntClear()
//
//*****************************************************************************
#define I2S_INT_RXERR 0x00000020
#define I2S_INT_RXREQ 0x00000010
#define I2S_INT_TXERR 0x00000002
#define I2S_INT_TXREQ 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void I2STxEnable(unsigned long ulBase);
extern void I2STxDisable(unsigned long ulBase);
extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData);
extern long I2STxDataPutNonBlocking(unsigned long ulBase,
unsigned long ulData);
extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase);
extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase);
extern void I2SRxEnable(unsigned long ulBase);
extern void I2SRxDisable(unsigned long ulBase);
extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData);
extern long I2SRxDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase);
extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase);
extern void I2STxRxEnable(unsigned long ulBase);
extern void I2STxRxDisable(unsigned long ulBase);
extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock);
extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2S_H__

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//*****************************************************************************
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/cpu.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
};
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// The processor vector table.
//
// This contains a list of the handlers for the various interrupt sources in
// the system. The layout of this list is defined by the hardware; assertion
// of an interrupt causes the processor to start executing directly at the
// address given in the corresponding location in this list.
//
//*****************************************************************************
#if defined(ewarm)
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#elif defined(sourcerygxx)
static __attribute__((section(".cs3.region-head.ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
return(CPUcpsie());
}
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
return(CPUcpsid());
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts;
//! some tool chains, such as the evaluation version of RV-MDK, do not support
//! linker scripts and therefore will not produce a valid executable. See the
//! discussion of compile-time versus run-time interrupt handler registration
//! in the introduction to this chapter.
//!
//! \return None.
//
//*****************************************************************************
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long ulIdx, ulValue;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Make sure that the RAM vector table is correctly aligned.
//
ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
//
// See if the RAM vector table has been initialized.
//
if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
{
//
// Copy the vector table from the beginning of FLASH to the RAM vector
// table.
//
ulValue = HWREG(NVIC_VTABLE);
for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
{
g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
ulValue);
}
//
// Point NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
//
// Save the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = pfnHandler;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
IntUnregister(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Reset the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
}
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the Stellaris family, three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
//! hardware priority mechanism on a future part. This arrangement allows
//! priorities to migrate to different NVIC implementations without changing
//! the gross prioritization of the interrupts.
//!
//! \return None.
//
//*****************************************************************************
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
}
}
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup mpu_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/mpu.h"
//*****************************************************************************
//
//! Enables and configures the MPU for use.
//!
//! \param ulMPUConfig is the logical OR of the possible configurations.
//!
//! This function enables the Cortex-M3 memory protection unit. It also
//! configures the default behavior when in privileged mode and while
//! handling a hard fault or NMI. Prior to enabling the MPU, at least one
//! region must be set by calling MPURegionSet() or else by enabling the
//! default region for privileged mode by passing the
//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
//! Once the MPU is enabled, a memory management fault will be generated
//! for any memory access violations.
//!
//! The \e ulMPUConfig parameter should be the logical OR of any of the
//! following:
//!
//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
//! privileged mode and when no other regions are defined. If this option
//! is not enabled, then there must be at least one valid region already
//! defined when the MPU is enabled.
//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
//! exception handler. If this option is not enabled, then the MPU is
//! disabled while in one of these exception handlers and the default
//! memory map is applied.
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
//! no default memory map is provided in privileged mode, and the MPU will
//! not be enabled in the fault handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUEnable(unsigned long ulMPUConfig)
{
//
// Check the arguments.
//
ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
MPU_CONFIG_HARDFLT_NMI)));
//
// Set the MPU control bits according to the flags passed by the user,
// and also set the enable bit.
//
HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the MPU for use.
//!
//! This function disables the Cortex-M3 memory protection unit. When the
//! MPU is disabled, the default memory map is used and memory management
//! faults are not generated.
//!
//! \return None.
//
//*****************************************************************************
void
MPUDisable(void)
{
//
// Turn off the MPU enable bit.
//
HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Gets the count of regions supported by the MPU.
//!
//! This function is used to get the number of regions that are supported by
//! the MPU. This is the total number that are supported, including regions
//! that are already programmed.
//!
//! \return The number of memory protection regions that are available
//! for programming using MPURegionSet().
//
//*****************************************************************************
unsigned long
MPURegionCountGet(void)
{
//
// Read the DREGION field of the MPU type register, and mask off
// the bits of interest to get the count of regions.
//
return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
>> NVIC_MPU_TYPE_DREGION_S);
}
//*****************************************************************************
//
//! Enables a specific region.
//!
//! \param ulRegion is the region number to enable.
//!
//! This function is used to enable a memory protection region. The region
//! should already be set up with the MPURegionSet() function. Once enabled,
//! the memory protection rules of the region will be applied and access
//! violations will cause a memory management fault.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionEnable(unsigned long ulRegion)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
//
// Select the region to modify.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Modify the enable bit in the region attributes.
//
HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
}
//*****************************************************************************
//
//! Disables a specific region.
//!
//! \param ulRegion is the region number to disable.
//!
//! This function is used to disable a previously enabled memory protection
//! region. The region will remain configured if it is not overwritten with
//! another call to MPURegionSet(), and can be enabled again by calling
//! MPURegionEnable().
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionDisable(unsigned long ulRegion)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
//
// Select the region to modify.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Modify the enable bit in the region attributes.
//
HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
}
//*****************************************************************************
//
//! Sets up the access rules for a specific region.
//!
//! \param ulRegion is the region number to set up.
//! \param ulAddr is the base address of the region. It must be aligned
//! according to the size of the region specified in ulFlags.
//! \param ulFlags is a set of flags to define the attributes of the region.
//!
//! This function sets up the protection rules for a region. The region has
//! a base address and a set of attributes including the size, which must
//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
//! according to the size.
//!
//! The \e ulFlags parameter is the logical OR of all of the attributes
//! of the region. It is a combination of choices for region size,
//! execute permission, read/write permissions, disabled sub-regions,
//! and a flag to determine if the region is enabled.
//!
//! The size flag determines the size of a region, and must be one of the
//! following:
//!
//! - \b MPU_RGN_SIZE_32B
//! - \b MPU_RGN_SIZE_64B
//! - \b MPU_RGN_SIZE_128B
//! - \b MPU_RGN_SIZE_256B
//! - \b MPU_RGN_SIZE_512B
//! - \b MPU_RGN_SIZE_1K
//! - \b MPU_RGN_SIZE_2K
//! - \b MPU_RGN_SIZE_4K
//! - \b MPU_RGN_SIZE_8K
//! - \b MPU_RGN_SIZE_16K
//! - \b MPU_RGN_SIZE_32K
//! - \b MPU_RGN_SIZE_64K
//! - \b MPU_RGN_SIZE_128K
//! - \b MPU_RGN_SIZE_256K
//! - \b MPU_RGN_SIZE_512K
//! - \b MPU_RGN_SIZE_1M
//! - \b MPU_RGN_SIZE_2M
//! - \b MPU_RGN_SIZE_4M
//! - \b MPU_RGN_SIZE_8M
//! - \b MPU_RGN_SIZE_16M
//! - \b MPU_RGN_SIZE_32M
//! - \b MPU_RGN_SIZE_64M
//! - \b MPU_RGN_SIZE_128M
//! - \b MPU_RGN_SIZE_256M
//! - \b MPU_RGN_SIZE_512M
//! - \b MPU_RGN_SIZE_1G
//! - \b MPU_RGN_SIZE_2G
//! - \b MPU_RGN_SIZE_4G
//!
//! The execute permission flag must be one of the following:
//!
//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
//!
//! The read/write access permissions are applied separately for the
//! privileged and user modes. The read/write access flags must be one
//! of the following:
//!
//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
//!
//! The region is automatically divided into 8 equally-sized sub-regions by
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
//! or larger. Any of these 8 sub-regions can be disabled. This allows
//! for creation of ``holes'' in a region which can be left open, or overlaid
//! by another region with different attributes. Any of the 8 sub-regions
//! can be disabled with a logical OR of any of the following flags:
//!
//! - \b MPU_SUB_RGN_DISABLE_0
//! - \b MPU_SUB_RGN_DISABLE_1
//! - \b MPU_SUB_RGN_DISABLE_2
//! - \b MPU_SUB_RGN_DISABLE_3
//! - \b MPU_SUB_RGN_DISABLE_4
//! - \b MPU_SUB_RGN_DISABLE_5
//! - \b MPU_SUB_RGN_DISABLE_6
//! - \b MPU_SUB_RGN_DISABLE_7
//!
//! Finally, the region can be initially enabled or disabled with one of
//! the following flags:
//!
//! - \b MPU_RGN_ENABLE
//! - \b MPU_RGN_DISABLE
//!
//! As an example, to set a region with the following attributes: size of
//! 32 KB, execution enabled, read-only for both privileged and user, one
//! sub-region disabled, and initially enabled; the \e ulFlags parameter would
//! have the following value:
//!
//! <code>
//! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
//! </code>
//!
//! \note This function will write to multiple registers and is not protected
//! from interrupts. It is possible that an interrupt which accesses a
//! region may occur while that region is in the process of being changed.
//! The safest way to handle this is to disable a region before changing it.
//! Refer to the discussion of this in the API Detailed Description section.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))
== ulAddr);
//
// Program the base address, use the region field to select the
// region at the same time.
//
HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID;
//
// Program the region attributes. Set the TEX field and the S, C,
// and B bits to fixed values that are suitable for all Stellaris
// memory.
//
HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M |
NVIC_MPU_ATTR_CACHEABLE)) |
NVIC_MPU_ATTR_SHAREABLE |
NVIC_MPU_ATTR_BUFFRABLE;
}
//*****************************************************************************
//
//! Gets the current settings for a specific region.
//!
//! \param ulRegion is the region number to get.
//! \param pulAddr points to storage for the base address of the region.
//! \param pulFlags points to the attribute flags for the region.
//!
//! This function retrieves the configuration of a specific region. The
//! meanings and format of the parameters is the same as that of the
//! MPURegionSet() function.
//!
//! This function can be used to save the configuration of a region for
//! later use with the MPURegionSet() function. The region's enable state
//! will be preserved in the attributes that are saved.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
unsigned long *pulFlags)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
ASSERT(pulAddr);
ASSERT(pulFlags);
//
// Select the region to get.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Read and store the base address for the region.
//
*pulAddr = HWREG(NVIC_MPU_BASE);
//
// Read and store the region attributes.
//
*pulFlags = HWREG(NVIC_MPU_ATTR);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the memory management fault.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! memory management fault occurs.
//!
//! This sets and enables the handler to be called when the MPU generates
//! a memory management fault due to a protection region access violation.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUIntRegister(void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(pfnHandler);
//
// Register the interrupt handler.
//
IntRegister(FAULT_MPU, pfnHandler);
//
// Enable the memory management fault.
//
IntEnable(FAULT_MPU);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the memory management fault.
//!
//! This function will disable and clear the handler to be called when a
//! memory management fault occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(FAULT_MPU);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_MPU);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __MPU_H__
#define __MPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Flags that can be passed to MPUEnable.
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT 4
#define MPU_CONFIG_HARDFLT_NMI 2
#define MPU_CONFIG_NONE 0
//*****************************************************************************
//
// Flags for the region size to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_SIZE_32B (4 << 1)
#define MPU_RGN_SIZE_64B (5 << 1)
#define MPU_RGN_SIZE_128B (6 << 1)
#define MPU_RGN_SIZE_256B (7 << 1)
#define MPU_RGN_SIZE_512B (8 << 1)
#define MPU_RGN_SIZE_1K (9 << 1)
#define MPU_RGN_SIZE_2K (10 << 1)
#define MPU_RGN_SIZE_4K (11 << 1)
#define MPU_RGN_SIZE_8K (12 << 1)
#define MPU_RGN_SIZE_16K (13 << 1)
#define MPU_RGN_SIZE_32K (14 << 1)
#define MPU_RGN_SIZE_64K (15 << 1)
#define MPU_RGN_SIZE_128K (16 << 1)
#define MPU_RGN_SIZE_256K (17 << 1)
#define MPU_RGN_SIZE_512K (18 << 1)
#define MPU_RGN_SIZE_1M (19 << 1)
#define MPU_RGN_SIZE_2M (20 << 1)
#define MPU_RGN_SIZE_4M (21 << 1)
#define MPU_RGN_SIZE_8M (22 << 1)
#define MPU_RGN_SIZE_16M (23 << 1)
#define MPU_RGN_SIZE_32M (24 << 1)
#define MPU_RGN_SIZE_64M (25 << 1)
#define MPU_RGN_SIZE_128M (26 << 1)
#define MPU_RGN_SIZE_256M (27 << 1)
#define MPU_RGN_SIZE_512M (28 << 1)
#define MPU_RGN_SIZE_1G (29 << 1)
#define MPU_RGN_SIZE_2G (30 << 1)
#define MPU_RGN_SIZE_4G (31 << 1)
//*****************************************************************************
//
// Flags for the permissions to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_PERM_EXEC 0x00000000
#define MPU_RGN_PERM_NOEXEC 0x10000000
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
//*****************************************************************************
//
// Flags for the sub-region to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_SUB_RGN_DISABLE_0 0x00000100
#define MPU_SUB_RGN_DISABLE_1 0x00000200
#define MPU_SUB_RGN_DISABLE_2 0x00000400
#define MPU_SUB_RGN_DISABLE_3 0x00000800
#define MPU_SUB_RGN_DISABLE_4 0x00001000
#define MPU_SUB_RGN_DISABLE_5 0x00002000
#define MPU_SUB_RGN_DISABLE_6 0x00004000
#define MPU_SUB_RGN_DISABLE_7 0x00008000
//*****************************************************************************
//
// Flags to enable or disable a region, to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_ENABLE 1
#define MPU_RGN_DISABLE 0
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void MPUEnable(unsigned long ulMPUConfig);
extern void MPUDisable(void);
extern unsigned long MPURegionCountGet(void);
extern void MPURegionEnable(unsigned long ulRegion);
extern void MPURegionDisable(unsigned long ulRegion);
extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
unsigned long ulFlags);
extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
unsigned long *pulFlags);
extern void MPUIntRegister(void (*pfnHandler)(void));
extern void MPUIntUnregister(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __MPU_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
#define PWM_GEN_MODE_FAULT_LATCHED \
0x00040000 // Fault is latched
#define PWM_GEN_MODE_FAULT_UNLATCHED \
0x00000000 // Fault is not latched
#define PWM_GEN_MODE_FAULT_MINPER \
0x00020000 // Enable min fault period
#define PWM_GEN_MODE_FAULT_NO_MINPER \
0x00000000 // Disable min fault period
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
#define PWM_GEN_MODE_FAULT_LEGACY \
0x00000000 // Disable extended fault support
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
// immediately
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
0x0000A800 // Deadband updates locally
// synchronized
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
0x0000FC00 // Deadband updates globally
// synchronized
#define PWM_GEN_MODE_GEN_NO_SYNC \
0x00000000 // Generator mode updates occur
// immediately
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
0x00000280 // Generator mode updates locally
// synchronized
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
0x000003C0 // Generator mode updates globally
// synchronized
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
#ifndef DEPRECATED
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
#endif
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
#define PWM_FAULT_FAULT0 0x00000001
#define PWM_FAULT_FAULT1 0x00000002
#define PWM_FAULT_FAULT2 0x00000004
#define PWM_FAULT_FAULT3 0x00000008
#define PWM_FAULT_ACMP0 0x00010000
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_1.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_1 1
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals
//
//*****************************************************************************
#define PWM_FAULT0_SENSE_HIGH 0x00000000
#define PWM_FAULT0_SENSE_LOW 0x00000001
#define PWM_FAULT1_SENSE_HIGH 0x00000000
#define PWM_FAULT1_SENSE_LOW 0x00000002
#define PWM_FAULT2_SENSE_HIGH 0x00000000
#define PWM_FAULT2_SENSE_LOW 0x00000004
#define PWM_FAULT3_SENSE_HIGH 0x00000000
#define PWM_FAULT3_SENSE_LOW 0x00000008
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFaultLevel(unsigned long ulBase,
unsigned long ulPWMOutBits,
tBoolean bDriveHigh);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultSuppress);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PWMFaultIntClearExt(unsigned long ulBase,
unsigned long ulFaultInts);
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulMinFaultPeriod,
unsigned long ulFaultSenses);
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.c - Driver for the Quadrature Encoder with Index.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup qei_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_qei.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/qei.h"
//*****************************************************************************
//
//! Enables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the quadrature encoder module. It must be
//! configured before it is enabled.
//!
//! \sa QEIConfigure()
//!
//! \return None.
//
//*****************************************************************************
void
QEIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;
}
//*****************************************************************************
//
//! Disables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the quadrature encoder module.
//!
//! \return None.
//
//*****************************************************************************
void
QEIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
}
//*****************************************************************************
//
//! Configures the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulConfig is the configuration for the quadrature encoder. See below
//! for a description of this parameter.
//! \param ulMaxPosition specifies the maximum position value.
//!
//! This will configure the operation of the quadrature encoder. The
//! \e ulConfig parameter provides the configuration of the encoder and is the
//! logical OR of several values:
//!
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
//! on channel A or on both channels A and B should be counted by the
//! position integrator and velocity accumulator.
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
//! position integrator should be reset when the index pulse is detected.
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
//! quadrature signals are being provided on ChA and ChB, or if a direction
//! signal and a clock are being provided instead.
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
//! provided on ChA and ChB should be swapped before being processed.
//!
//! \e ulMaxPosition is the maximum value of the position integrator, and is
//! the value used to reset the position capture when in index reset mode and
//! moving in the reverse (negative) direction.
//!
//! \return None.
//
//*****************************************************************************
void
QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Write the new configuration to the hardware.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
ulConfig);
//
// Set the maximum position.
//
HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;
}
//*****************************************************************************
//
//! Gets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current position of the encoder. Depending upon the
//! configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter will not be aligned with the index pulse yet).
//!
//! \return The current position of the encoder.
//
//*****************************************************************************
unsigned long
QEIPositionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the current position counter.
//
return(HWREG(ulBase + QEI_O_POS));
}
//*****************************************************************************
//
//! Sets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPosition is the new position for the encoder.
//!
//! This sets the current position of the encoder; the encoder position will
//! then be measured relative to this value.
//!
//! \return None.
//
//*****************************************************************************
void
QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Set the position counter.
//
HWREG(ulBase + QEI_O_POS) = ulPosition;
}
//*****************************************************************************
//
//! Gets the current direction of rotation.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current direction of rotation. In this case, current
//! means the most recently detected direction of the encoder; it may not be
//! presently moving but this is the direction it last moved before it stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
//
//*****************************************************************************
long
QEIDirectionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the direction of rotation.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
}
//*****************************************************************************
//
//! Gets the encoder error indicator.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the error indicator for the quadrature encoder. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
//*****************************************************************************
tBoolean
QEIErrorGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the error indicator.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
}
//*****************************************************************************
//
//! Enables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the velocity capture in the quadrature
//! encoder module. It must be configured before it is enabled. Velocity
//! capture will not occur if the quadrature encoder is not enabled.
//!
//! \sa QEIVelocityConfigure() and QEIEnable()
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;
}
//*****************************************************************************
//
//! Disables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the velocity capture in the quadrature
//! encoder module.
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
}
//*****************************************************************************
//
//! Configures the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPreDiv specifies the predivider applied to the input quadrature
//! signal before it is counted; can be one of \b QEI_VELDIV_1,
//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
//! \param ulPeriod specifies the number of clock ticks over which to measure
//! the velocity; must be non-zero.
//!
//! This will configure the operation of the velocity capture portion of the
//! quadrature encoder. The position increment signal is predivided as
//! specified by \e ulPreDiv before being accumulated by the velocity capture.
//! The divided signal is accumulated over \e ulPeriod system clock before
//! being saved and resetting the accumulator.
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));
ASSERT(ulPeriod != 0);
//
// Set the velocity predivider.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_VELDIV_M)) | ulPreDiv);
//
// Set the timer period.
//
HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the current encoder speed.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current speed of the encoder. The value returned is the
//! number of pulses detected in the specified time period; this number can be
//! multiplied by the number of time periods per second and divided by the
//! number of pulses per revolution to obtain the number of revolutions per
//! second.
//!
//! \return Returns the number of pulses captured in the given time period.
//
//*****************************************************************************
unsigned long
QEIVelocityGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the speed capture value.
//
return(HWREG(ulBase + QEI_O_SPEED));
}
//*****************************************************************************
//
//! Registers an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param pfnHandler is a pointer to the function to be called when the
//! quadrature encoder interrupt occurs.
//!
//! This sets the handler to be called when a quadrature encoder interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
//! It is the interrupt handler's responsibility to clear the interrupt source
//! via QEIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Determine the interrupt number based on the QEI module.
//
ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the quadrature encoder interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This function will clear the handler to be called when a quadrature encoder
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Determine the interrupt number based on the QEI module.
//
ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Enables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Enables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Disables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the quadrature encoder module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
//
//*****************************************************************************
unsigned long
QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + QEI_O_ISC));
}
else
{
return(HWREG(ulBase + QEI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! The specified quadrature encoder interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to keep
//! it from being called again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + QEI_O_ISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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This project will build the Stellaris Peripheral Driver Library.
-------------------------------------------------------------------------------
Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
Software License Agreement
Luminary Micro, Inc. (LMI) is supplying this software for use solely and
exclusively on LMI's microcontroller products.
The software is owned by LMI and/or its suppliers, and is protected under
applicable copyright laws. All rights are reserved. You may not combine
this software with "viral" open-source software in order to form a larger
program. Any use in violation of the foregoing restrictions may subject
the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 4694 of the Stellaris Peripheral Driver Library.

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//*****************************************************************************
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ssi_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ssi.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/ssi.h"
//*****************************************************************************
//
//! Configures the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
//! \param ulProtocol specifies the data transfer protocol.
//! \param ulMode specifies the mode of operation.
//! \param ulBitRate specifies the clock rate.
//! \param ulDataWidth specifies number of bits transferred per frame.
//!
//! This function configures the synchronous serial interface. It sets
//! the SSI protocol, mode of operation, bit rate, and data width.
//!
//! The \e ulProtocol parameter defines the data frame format. The
//! \e ulProtocol parameter can be one of the following values:
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
//! frame formats imply the following polarity and phase configurations:
//!
//! <pre>
//! Polarity Phase Mode
//! 0 0 SSI_FRF_MOTO_MODE_0
//! 0 1 SSI_FRF_MOTO_MODE_1
//! 1 0 SSI_FRF_MOTO_MODE_2
//! 1 1 SSI_FRF_MOTO_MODE_3
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if a slave, the SSI can be
//! configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SSI_MODE_MASTER,
//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSSI >= 2 * bit rate (master mode)
//! - FSSI >= 12 * bit rate (slave modes)
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The \e ulDataWidth parameter defines the width of the data transfers, and
//! can be a value between 4 and 16, inclusive.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//!
//! This function replaces the original SSIConfig() API and performs the same
//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
//! this API.
//!
//! \return None.
//
//*****************************************************************************
void
SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate, unsigned long ulDataWidth)
{
unsigned long ulMaxBitRate;
unsigned long ulRegVal;
unsigned long ulPreDiv;
unsigned long ulSCR;
unsigned long ulSPH_SPO;
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
(ulProtocol == SSI_FRF_MOTO_MODE_3) ||
(ulProtocol == SSI_FRF_TI) ||
(ulProtocol == SSI_FRF_NMW));
ASSERT((ulMode == SSI_MODE_MASTER) ||
(ulMode == SSI_MODE_SLAVE) ||
(ulMode == SSI_MODE_SLAVE_OD));
ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
//
// Set the mode.
//
ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
HWREG(ulBase + SSI_O_CR1) = ulRegVal;
//
// Set the clock predivider.
//
ulMaxBitRate = ulSSIClk / ulBitRate;
ulPreDiv = 0;
do
{
ulPreDiv += 2;
ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
}
while(ulSCR > 255);
HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
//
// Set protocol and clock rate.
//
ulSPH_SPO = ulProtocol << 6;
ulProtocol &= SSI_CR0_FRF_M;
ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
HWREG(ulBase + SSI_O_CR0) = ulRegVal;
}
//*****************************************************************************
//
//! Enables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This will enable operation of the synchronous serial interface. It must be
//! configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SSIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
}
//*****************************************************************************
//
//! Disables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This will disable operation of the synchronous serial interface.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an SSI interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
//! it is the interrupt handler's responsibility to clear the interrupt source
//! via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the synchronous serial interface interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function will clear the handler to be called when a SSI
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Enables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SSI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor. The \e ulIntFlags parameter can be any of the
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Enable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
//! values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Disable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the SSI module base address.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the SSI module. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
//
//*****************************************************************************
unsigned long
SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + SSI_O_MIS));
}
else
{
return(HWREG(ulBase + SSI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SSI interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to
//! keep it from being called again immediately upon exit.
//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
//! and \b SSI_RXOR values.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData data to be transmitted over the SSI interface.
//!
//! This function will place the supplied data into the transmit FIFO of
//! the specified SSI module.
//!
//! \note The upper 32 - N bits of the \e ulData will be discarded by the
//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
//! For example, if the interface is configured for 8-bit data width, the upper
//! 24 bits of \e ulData will be discarded.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Wait until there is space.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
{
}
//
// Write the data to the SSI.
//
HWREG(ulBase + SSI_O_DR) = ulData;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData data to be transmitted over the SSI interface.
//!
//! This function will place the supplied data into the transmit FIFO of
//! the specified SSI module. If there is no space in the FIFO, then this
//! function will return a zero.
//!
//! This function replaces the original SSIDataNonBlockingPut() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note The upper 32 - N bits of the \e ulData will be discarded by the
//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
//! For example, if the interface is configured for 8-bit data width, the upper
//! 24 bits of \e ulData will be discarded.
//!
//! \return Returns the number of elements written to the SSI transmit FIFO.
//
//*****************************************************************************
long
SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Check for space to write.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
{
HWREG(ulBase + SSI_O_DR) = ulData;
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData pointer to a storage location for data that was received
//! over the SSI interface.
//!
//! This function will get received data from the receive FIFO of the specified
//! SSI module, and place that data into the location specified by the
//! \e pulData parameter.
//!
//! \note Only the lower N bits of the value written to \e pulData will contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! will contain valid data.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Wait until there is data to be read.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
{
}
//
// Read data from SSI.
//
*pulData = HWREG(ulBase + SSI_O_DR);
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData pointer to a storage location for data that was received
//! over the SSI interface.
//!
//! This function will get received data from the receive FIFO of
//! the specified SSI module, and place that data into the location specified
//! by the \e ulData parameter. If there is no data in the FIFO, then this
//! function will return a zero.
//!
//! This function replaces the original SSIDataNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note Only the lower N bits of the value written to \e pulData will contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! will contain valid data.
//!
//! \return Returns the number of elements read from the SSI receive FIFO.
//
//*****************************************************************************
long
SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Check for data to read.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
{
*pulData = HWREG(ulBase + SSI_O_DR);
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Enable SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified SSI DMA features are enabled. The SSI can be
//! configured to use DMA for transmit and/or receive data transfers.
//! The \e ulDMAFlags parameter is the logical OR of any of the following
//! values:
//!
//! - SSI_DMA_RX - enable DMA for receive
//! - SSI_DMA_TX - enable DMA for transmit
//!
//! \note The uDMA controller must also be set up before DMA can be used
//! with the SSI.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Set the requested bits in the UART DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
}
//*****************************************************************************
//
//! Disable SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to disable.
//!
//! This function is used to disable SSI DMA features that were enabled
//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
//! \e ulDMAFlags parameter is the logical OR of any of the following values:
//!
//! - SSI_DMA_RX - disable DMA for receive
//! - SSI_DMA_TX - disable DMA for transmit
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
//
// Clear the requested bits in the UART DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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//*****************************************************************************
//
// systick.c - Driver for the SysTick timer in NVIC.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This will start the SysTick counter. If an interrupt handler has been
//! registered, it will be called when the SysTick counter rolls over.
//!
//! \note Calling this function will cause the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force this. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This will stop the SysTick counter. If an interrupt handler has been
//! registered, it will no longer be called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This sets the handler to be called when a SysTick interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function will clear the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function will enable the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler does not need to clear the SysTick
//! interrupt source as this is done automatically by NVIC when the interrupt
//! handler is called.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function will disable the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter; must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
//! the next clock after the SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter; this will
//! be a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
// instead to return the timer to its reset state.
//
//*****************************************************************************
#ifndef DEPRECATED
extern void TimerQuiesce(unsigned long ulBase);
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
// UARTHandshakeOutputGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
#define UART_OUTPUT_DTR 0x00000400
//*****************************************************************************
//
// Values that can be returned from UARTHandshakeInputsGet().
//
//*****************************************************************************
#define UART_INPUT_RI 0x00000100
#define UART_INPUT_DCD 0x00000004
#define UART_INPUT_DSR 0x00000002
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTSmartCardEnable(unsigned long ulBase);
extern void UARTSmartCardDisable(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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//*****************************************************************************
//
// udma.h - Prototypes and macros for the uDMA controller.
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UDMA_H__
#define __UDMA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
// fields are used by the uDMA controller and normally it is not necessary for
// software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
//
// The ending source address of the data transfer.
//
volatile void *pvSrcEndAddr;
//
// The ending destination address of the data transfer.
//
volatile void *pvDstEndAddr;
//
// The channel control mode.
//
volatile unsigned long ulControl;
//
// An unused location.
//
volatile unsigned long ulSpare;
}
tDMAControlTable;
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
//
//*****************************************************************************
#define UDMA_ATTR_USEBURST 0x00000001
#define UDMA_ATTR_ALTSELECT 0x00000002
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
#define UDMA_ATTR_REQMASK 0x00000008
#define UDMA_ATTR_ALL 0x0000000F
//*****************************************************************************
//
// DMA control modes that can be passed to uDMAModeSet() and returned
// uDMAModeGet().
//
//*****************************************************************************
#define UDMA_MODE_STOP 0x00000000
#define UDMA_MODE_BASIC 0x00000001
#define UDMA_MODE_AUTO 0x00000002
#define UDMA_MODE_PINGPONG 0x00000003
#define UDMA_MODE_MEM_SCATTER_GATHER \
0x00000004
#define UDMA_MODE_PER_SCATTER_GATHER \
0x00000006
#define UDMA_MODE_ALT_SELECT 0x00000001
//*****************************************************************************
//
// Channel configuration values that can be passed to uDMAControlSet().
//
//*****************************************************************************
#define UDMA_DST_INC_8 0x00000000
#define UDMA_DST_INC_16 0x40000000
#define UDMA_DST_INC_32 0x80000000
#define UDMA_DST_INC_NONE 0xc0000000
#define UDMA_SRC_INC_8 0x00000000
#define UDMA_SRC_INC_16 0x04000000
#define UDMA_SRC_INC_32 0x08000000
#define UDMA_SRC_INC_NONE 0x0c000000
#define UDMA_SIZE_8 0x00000000
#define UDMA_SIZE_16 0x11000000
#define UDMA_SIZE_32 0x22000000
#define UDMA_ARB_1 0x00000000
#define UDMA_ARB_2 0x00004000
#define UDMA_ARB_4 0x00008000
#define UDMA_ARB_8 0x0000c000
#define UDMA_ARB_16 0x00010000
#define UDMA_ARB_32 0x00014000
#define UDMA_ARB_64 0x00018000
#define UDMA_ARB_128 0x0001c000
#define UDMA_ARB_256 0x00020000
#define UDMA_ARB_512 0x00024000
#define UDMA_ARB_1024 0x00028000
#define UDMA_NEXT_USEBURST 0x00000008
//*****************************************************************************
//
// Channel numbers to be passed to API functions that require a channel number
// ID.
//
//*****************************************************************************
#define UDMA_CHANNEL_USBEP1RX 0
#define UDMA_CHANNEL_USBEP1TX 1
#define UDMA_CHANNEL_USBEP2RX 2
#define UDMA_CHANNEL_USBEP2TX 3
#define UDMA_CHANNEL_USBEP3RX 4
#define UDMA_CHANNEL_USBEP3TX 5
#define UDMA_CHANNEL_ETH0RX 6
#define UDMA_CHANNEL_ETH0TX 7
#define UDMA_CHANNEL_UART0RX 8
#define UDMA_CHANNEL_UART0TX 9
#define UDMA_CHANNEL_SSI0RX 10
#define UDMA_CHANNEL_SSI0TX 11
#define UDMA_CHANNEL_ADC0 14
#define UDMA_CHANNEL_ADC1 15
#define UDMA_CHANNEL_ADC2 16
#define UDMA_CHANNEL_ADC3 17
#define UDMA_CHANNEL_TMR0A 18
#define UDMA_CHANNEL_TMR0B 19
#define UDMA_CHANNEL_TMR1A 20
#define UDMA_CHANNEL_TMR1B 21
#define UDMA_CHANNEL_UART1RX 22
#define UDMA_CHANNEL_UART1TX 23
#define UDMA_CHANNEL_SSI1RX 24
#define UDMA_CHANNEL_SSI1TX 25
#define UDMA_CHANNEL_I2S0RX 28
#define UDMA_CHANNEL_I2S0TX 29
#define UDMA_CHANNEL_SW 30
//*****************************************************************************
//
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
// control structure should be used.
//
//*****************************************************************************
#define UDMA_PRI_SELECT 0x00000000
#define UDMA_ALT_SELECT 0x00000020
//*****************************************************************************
//
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
// uDMAIntUnregister().
//
//*****************************************************************************
#define UDMA_INT_SW 62
#define UDMA_INT_ERR 63
//*****************************************************************************
//
// Channel numbers to be passed to API functions that require a channel number
// ID. These are for secondary peripheral assignments.
//
//*****************************************************************************
#define UDMA_SEC_CHANNEL_UART2RX_0 \
0
#define UDMA_SEC_CHANNEL_UART2TX_1 \
1
#define UDMA_SEC_CHANNEL_TMR3A 2
#define UDMA_SEC_CHANNEL_TMR3B 3
#define UDMA_SEC_CHANNEL_TMR2A_4 \
4
#define UDMA_SEC_CHANNEL_TMR2B_5 \
5
#define UDMA_SEC_CHANNEL_TMR2A_6 \
6
#define UDMA_SEC_CHANNEL_TMR2B_7 \
7
#define UDMA_SEC_CHANNEL_UART1RX \
8
#define UDMA_SEC_CHANNEL_UART1TX \
9
#define UDMA_SEC_CHANNEL_SSI1RX 10
#define UDMA_SEC_CHANNEL_SSI1TX 11
#define UDMA_SEC_CHANNEL_UART2RX_12 \
12
#define UDMA_SEC_CHANNEL_UART2TX_13 \
13
#define UDMA_SEC_CHANNEL_TMR2A_14 \
14
#define UDMA_SEC_CHANNEL_TMR2B_15 \
15
#define UDMA_SEC_CHANNEL_TMR1A 18
#define UDMA_SEC_CHANNEL_TMR1B 19
#define UDMA_SEC_CHANNEL_EPI0RX 20
#define UDMA_SEC_CHANNEL_EPI0TX 21
#define UDMA_SEC_CHANNEL_ADC10 24
#define UDMA_SEC_CHANNEL_ADC11 25
#define UDMA_SEC_CHANNEL_ADC12 26
#define UDMA_SEC_CHANNEL_ADC13 27
#define UDMA_SEC_CHANNEL_SW 30
//*****************************************************************************
//
// uDMA default/secondary peripheral selections, to be passed to
// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
//
//*****************************************************************************
#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
0x00000001
#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
0x00000002
#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
0x00000004
#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
0x00000008
#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
0x00000010
#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
0x00000020
#define UDMA_DEF_ETH0RX_SEC_TMR2A \
0x00000040
#define UDMA_DEF_ETH0TX_SEC_TMR2B \
0x00000080
#define UDMA_DEF_UART0RX_SEC_UART1RX \
0x00000100
#define UDMA_DEF_UART0TX_SEC_UART1TX \
0x00000200
#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
0x00000400
#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
0x00000800
#define UDMA_DEF_RESERVED_SEC_UART2RX \
0x00001000
#define UDMA_DEF_RESERVED_SEC_UART2TX \
0x00002000
#define UDMA_DEF_ADC00_SEC_TMR2A \
0x00004000
#define UDMA_DEF_ADC01_SEC_TMR2B \
0x00008000
#define UDMA_DEF_ADC02_SEC_RESERVED \
0x00010000
#define UDMA_DEF_ADC03_SEC_RESERVED \
0x00020000
#define UDMA_DEF_TMR0A_SEC_TMR1A \
0x00040000
#define UDMA_DEF_TMR0B_SEC_TMR1B \
0x00080000
#define UDMA_DEF_TMR1A_SEC_EPI0RX \
0x00100000
#define UDMA_DEF_TMR1B_SEC_EPI0TX \
0x00200000
#define UDMA_DEF_UART1RX_SEC_RESERVED \
0x00400000
#define UDMA_DEF_UART1TX_SEC_RESERVED \
0x00800000
#define UDMA_DEF_SSI1RX_SEC_ADC10 \
0x01000000
#define UDMA_DEF_SSI1TX_SEC_ADC11 \
0x02000000
#define UDMA_DEF_RESERVED_SEC_ADC12 \
0x04000000
#define UDMA_DEF_RESERVED_SEC_ADC13 \
0x08000000
#define UDMA_DEF_I2S0RX_SEC_RESERVED \
0x10000000
#define UDMA_DEF_I2S0TX_SEC_RESERVED \
0x20000000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannel);
extern void uDMAChannelDisable(unsigned long ulChannel);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannel);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannel);
extern void uDMAChannelAttributeEnable(unsigned long ulChannel,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannel,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannel);
extern void uDMAChannelControlSet(unsigned long ulChannel,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannel,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannel);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannel);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UDMA_H__

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//*****************************************************************************
//
// usb.h - Prototypes for the USB Interface Driver.
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __USB_H__
#define __USB_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to USBIntEnable(),
// USBIntDisable(), and USBIntClear() as the ulIntFlags parameter, and which
// are returned from USBIntStatus().
//
//*****************************************************************************
#define USB_INT_ALL 0xFF030E0F // All Interrupt sources
#define USB_INT_STATUS 0xFF000000 // Status Interrupts
#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error
#define USB_INT_SESSION_START 0x40000000 // Session Start Detected
#define USB_INT_SESSION_END 0x20000000 // Session End Detected
#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected
#define USB_INT_CONNECT 0x10000000 // Device Connect Detected
#define USB_INT_SOF 0x08000000 // Start of Frame Detected
#define USB_INT_BABBLE 0x04000000 // Babble signaled
#define USB_INT_RESET 0x04000000 // Reset signaled
#define USB_INT_RESUME 0x02000000 // Resume detected
#define USB_INT_SUSPEND 0x01000000 // Suspend detected
#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid
#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected
#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts
#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts
#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt
#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt
#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt
#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt
#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt
#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt
#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts
#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts
#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt
#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt
#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt
#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt
#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt
#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt
#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt
//*****************************************************************************
//
// The following are values that are returned from USBSpeedGet().
//
//*****************************************************************************
#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
//*****************************************************************************
//
// The following are values that are returned from USBEndpointStatus(). The
// USB_HOST_* values are used when the USB controller is in host mode and the
// USB_DEV_* values are used when the USB controller is in device mode.
//
//*****************************************************************************
#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received
#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond
#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
// (ISOC Mode)
#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
// specified timeout period
#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
// device
#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
// specified timeout period
#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
// (ISOC mode)
#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
// device
#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
// specified timeout period
#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
// device
#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
// a full FIFO
#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
// to come
#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
// Data End seen
#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
//*****************************************************************************
//
// The following are values that can be passed to USBHostEndpointConfig() and
// USBDevEndpointConfig() as the ulFlags parameter.
//
//*****************************************************************************
#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
#define USB_EP_HOST_EP0 0x00002000 // Host endpoint 0
#define USB_EP_HOST_IN 0x00001000 // Host IN endpoint
#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
#define USB_EP_DEV_EP0 0x00002000 // Device endpoint 0
#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
#define USB_EP_DEV_OUT 0x00001000 // Device OUT endpoint
//*****************************************************************************
//
// The following are values that can be passed to USBHostPwrFaultConfig() as
// the ulFlags parameter.
//
//*****************************************************************************
#define USB_HOST_PWRFLT_LOW 0x00000010
#define USB_HOST_PWRFLT_HIGH 0x00000030
#define USB_HOST_PWRFLT_EP_NONE 0x00000000
#define USB_HOST_PWRFLT_EP_TRI 0x00000140
#define USB_HOST_PWRFLT_EP_LOW 0x00000240
#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
#define USB_HOST_PWREN_LOW 0x00000000
#define USB_HOST_PWREN_HIGH 0x00000001
#define USB_HOST_PWREN_VBLOW 0x00000002
#define USB_HOST_PWREN_VBHIGH 0x00000003
//*****************************************************************************
//
// The following are special values that can be passed to
// USBHostEndpointConfig() as the ulNAKPollInterval parameter.
//
//*****************************************************************************
#define MAX_NAK_LIMIT 31 // Maximum NAK interval
#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
//*****************************************************************************
//
// This value specifies the maximum size of transfers on endpoint 0 as 64
// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
//
//*****************************************************************************
#define MAX_PACKET_SIZE_EP0 64
//*****************************************************************************
//
// These values are used to indicate which endpoint to access.
//
//*****************************************************************************
#define USB_EP_0 0x00000000 // Endpoint 0
#define USB_EP_1 0x00000010 // Endpoint 1
#define USB_EP_2 0x00000020 // Endpoint 2
#define USB_EP_3 0x00000030 // Endpoint 3
#define USB_EP_4 0x00000040 // Endpoint 4
#define USB_EP_5 0x00000050 // Endpoint 5
#define USB_EP_6 0x00000060 // Endpoint 6
#define USB_EP_7 0x00000070 // Endpoint 7
#define USB_EP_8 0x00000080 // Endpoint 8
#define USB_EP_9 0x00000090 // Endpoint 9
#define USB_EP_10 0x000000A0 // Endpoint 10
#define USB_EP_11 0x000000B0 // Endpoint 11
#define USB_EP_12 0x000000C0 // Endpoint 12
#define USB_EP_13 0x000000D0 // Endpoint 13
#define USB_EP_14 0x000000E0 // Endpoint 14
#define USB_EP_15 0x000000F0 // Endpoint 15
#define NUM_USB_EP 16 // Number of supported endpoints
//*****************************************************************************
//
// These macros allow conversion between 0-based endpoint indices and the
// USB_EP_x values required when calling various USB APIs.
//
//*****************************************************************************
#define INDEX_TO_USB_EP(x) ((x) << 4)
#define USB_EP_TO_INDEX(x) ((x) >> 4)
//*****************************************************************************
//
// The following are values that can be passed to USBFIFOConfigSet() as the
// ulFIFOSize parameter.
//
//*****************************************************************************
#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO
#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO
// (occupying 16 bytes)
#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO
// (occupying 32 bytes)
#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO
// (occupying 64 bytes)
#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO
// (occupying 128 bytes)
#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO
// (occupying 256 bytes)
#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO
// (occupying 512 bytes)
#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO
// (occupying 1024 bytes)
#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO
// (occupying 2048 bytes)
#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO
// (occupying 4096 bytes)
//*****************************************************************************
//
// This macro allow conversion from a FIFO size label as defined above to
// a number of bytes
//
//*****************************************************************************
#define USB_FIFO_SIZE_DB_FLAG 0x00000010
#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
(((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
//*****************************************************************************
//
// The following are values that can be passed to USBEndpointDataSend() as the
// ulTransType parameter.
//
//*****************************************************************************
#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
#define USB_TRANS_IN 0x00000102 // Normal IN transaction
#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
// endpoint 0 in device mode)
#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
// 0)
#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
// 0)
//*****************************************************************************
//
// The following are values are returned by the USBModeGet function.
//
//*****************************************************************************
#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
// mode.
#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
// Device mode.
#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
// set.
#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long USBDevAddrGet(unsigned long ulBase);
extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
extern void USBDevConnect(unsigned long ulBase);
extern void USBDevDisconnect(unsigned long ulBase);
extern void USBDevEndpointConfig(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulMaxPacketSize,
unsigned long ulFlags);
extern void USBDevEndpointConfigGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long *pulMaxPacketSize,
unsigned long *pulFlags);
extern void USBDevEndpointDataAck(unsigned long ulBase,
unsigned long ulEndpoint,
tBoolean bIsLastPacket);
extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBDevEndpointStallClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBDevEndpointStatusClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBEndpointDataAvail(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBEndpointDMADisable(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned char *pucData, unsigned long *pulSize);
extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
unsigned char *pucData, unsigned long ulSize);
extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulTransType);
extern void USBEndpointDataToggleClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBEndpointStatus(unsigned long ulBase,
unsigned long ulEndpoint);
extern unsigned long USBFIFOAddrGet(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long *pulFIFOAddress,
unsigned long *pulFIFOSize,
unsigned long ulFlags);
extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFIFOAddress,
unsigned long ulFIFOSize, unsigned long ulFlags);
extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBFrameNumberGet(unsigned long ulBase);
extern unsigned long USBHostAddrGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulAddr, unsigned long ulFlags);
extern void USBHostEndpointConfig(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulMaxPacketSize,
unsigned long ulNAKPollInterval,
unsigned long ulTargetEndpoint,
unsigned long ulFlags);
extern void USBHostEndpointDataAck(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBHostEndpointDataToggle(unsigned long ulBase,
unsigned long ulEndpoint,
tBoolean bDataToggle,
unsigned long ulFlags);
extern void USBHostEndpointStatusClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBHostHubAddrGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulAddr, unsigned long ulFlags);
extern void USBHostPwrDisable(unsigned long ulBase);
extern void USBHostPwrEnable(unsigned long ulBase);
extern void USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags);
extern void USBHostPwrFaultDisable(unsigned long ulBase);
extern void USBHostPwrFaultEnable(unsigned long ulBase);
extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
extern void USBHostRequestStatus(unsigned long ulBase);
extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
extern unsigned long USBHostSpeedGet(unsigned long ulBase);
extern void USBHostSuspend(unsigned long ulBase);
extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long USBIntStatus(unsigned long ulBase);
extern void USBIntUnregister(unsigned long ulBase);
extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
extern unsigned long USBModeGet(unsigned long ulBase);
extern void USBEndpointDMAChannel(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulChannel);
extern void USBHostMode(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __USB_H__

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//*****************************************************************************
//
// watchdog.c - Driver for the Watchdog Timer Module.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup watchdog_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_watchdog.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/watchdog.h"
//*****************************************************************************
//
//! Determines if the watchdog timer is enabled.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! if it is not.
//
//*****************************************************************************
tBoolean
WatchdogRunning(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// See if the watchdog timer module is enabled, and return.
//
return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog timer module.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Enables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogResetEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
}
//*****************************************************************************
//
//! Disables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Disables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogResetDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogLock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
// register causes the lock to go into effect.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
}
//*****************************************************************************
//
//! Disables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogUnlock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Unlock watchdog register writes.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
}
//*****************************************************************************
//
//! Gets the state of the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
//
//*****************************************************************************
tBoolean
WatchdogLockState(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the lock state.
//
return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
}
//*****************************************************************************
//
//! Sets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value will be immediately loaded into the
//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
//! interrupt is immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Set the load register.
//
HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
}
//*****************************************************************************
//
//! Gets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function gets the value that is loaded into the watchdog timer when
//! the count reaches zero for the first time.
//!
//! \sa WatchdogReloadSet()
//!
//! \return None.
//
//*****************************************************************************
unsigned long
WatchdogReloadGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the load register.
//
return(HWREG(ulBase + WDT_O_LOAD));
}
//*****************************************************************************
//
//! Gets the current watchdog timer value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function reads the current value of the watchdog timer.
//!
//! \return Returns the current value of the watchdog timer.
//
//*****************************************************************************
unsigned long
WatchdogValueGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the current watchdog timer register value.
//
return(HWREG(ulBase + WDT_O_VALUE));
}
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Register the interrupt handler.
//
IntRegister(INT_WATCHDOG, pfnHandler);
//
// Enable the watchdog timer interrupt.
//
IntEnable(INT_WATCHDOG);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable the interrupt.
//
IntDisable(INT_WATCHDOG);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_WATCHDOG);
}
//*****************************************************************************
//
//! Enables the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the watchdog timer interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog interrupt.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Gets the current watchdog timer interrupt status.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, where a 1 indicates that the
//! watchdog interrupt is active, and a 0 indicates that it is not active.
//
//*****************************************************************************
unsigned long
WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + WDT_O_MIS));
}
else
{
return(HWREG(ulBase + WDT_O_RIS));
}
}
//*****************************************************************************
//
//! Clears the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Clear the interrupt source.
//
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
}
//*****************************************************************************
//
//! Disables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function disables the debug mode stall of the watchdog timer. By
//! doing so, the watchdog timer continues to count regardless of the processor
//! debug state.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

74
bsp/lm3s/Libraries/driverlib/watchdog.h Normal file
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@ -0,0 +1,74 @@
//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__