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add apm32 rtt sdio/flash/sdram driver (#7065) 

* add rtt sdio/flash/sdram driver

* formatting rtt drivers
This commit is contained in:
luobeihai 2023-03-20 12:04:18 +08:00 committed by GitHub
parent 4b8f518c48
commit 674c4d4ebc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
85 changed files with 3588 additions and 1335 deletions
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2
bsp/apm32/apm32f051r8-evalboard/README.md
View File

@ -15,7 +15,7 @@
APM32F051R8 EVAL BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
![image-20230114161253327](../../../../../abc/rt-thread/bsp/apm32/apm32f051r8-evalboard/figures/APM32F051R8-EVAL.png)
![APM32F051R8-EVAL](figures/APM32F051R8-EVAL.png)
- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)

22
bsp/apm32/apm32f072vb-miniboard/.config
View File

@ -58,6 +58,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
@ -207,6 +208,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -302,6 +304,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -378,12 +381,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -398,6 +395,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -505,6 +503,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
#
# peripheral libraries and drivers
@ -576,6 +575,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -714,6 +714,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -903,6 +904,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -932,10 +934,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -978,6 +987,7 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#

4
bsp/apm32/apm32f072vb-miniboard/board/Kconfig
View File

@ -199,6 +199,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT

1
bsp/apm32/apm32f072vb-miniboard/board/SConscript
View File

@ -12,6 +12,7 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB

6
bsp/apm32/apm32f072vb-miniboard/board/board.h
View File

@ -41,6 +41,12 @@
#include "apm32f0xx_iwdt.h"
#include "apm32f0xx_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f0xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f0xx_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

34
bsp/apm32/apm32f072vb-miniboard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 112 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 112 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

4
bsp/apm32/apm32f072vb-miniboard/project.uvoptx
View File

@ -356,7 +356,7 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -472,7 +472,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

2
bsp/apm32/apm32f072vb-miniboard/project.uvprojx
View File

@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F072xB</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension;.;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\ipc;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;board;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;applications;..\libraries\Drivers;board\ports;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\..\..\libcpu\arm\common;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>

5
bsp/apm32/apm32f072vb-miniboard/rtconfig.h
View File

@ -34,6 +34,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@ -140,9 +141,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -215,6 +213,7 @@
/* Other */
/* Signal IO */

31
bsp/apm32/apm32f091vc-miniboard/.config
View File

@ -146,13 +146,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@ -214,6 +208,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -386,12 +381,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -406,6 +395,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -585,6 +575,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -723,6 +714,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -912,6 +904,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -941,10 +934,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -984,11 +984,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_I2C is not set
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI1=y
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#

4
bsp/apm32/apm32f091vc-miniboard/board/Kconfig
View File

@ -199,6 +199,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT

1
bsp/apm32/apm32f091vc-miniboard/board/SConscript
View File

@ -12,6 +12,7 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB

6
bsp/apm32/apm32f091vc-miniboard/board/board.h
View File

@ -41,6 +41,12 @@
#include "apm32f0xx_iwdt.h"
#include "apm32f0xx_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f0xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f0xx_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

34
bsp/apm32/apm32f091vc-miniboard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

272
bsp/apm32/apm32f091vc-miniboard/project.uvoptx
View File

@ -73,7 +73,7 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
@ -175,7 +175,7 @@
</Target>
<Group>
<GroupName>ADT</GroupName>
<GroupName>Applications</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
@ -187,26 +187,6 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\utilities\libadt\avl.c</PathWithFileName>
<FilenameWithoutPath>avl.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Applications</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>applications\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@ -221,8 +201,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>3</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -233,8 +213,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>4</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -245,8 +225,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -257,8 +237,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>6</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -269,8 +249,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -281,8 +261,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -293,8 +273,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>9</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -305,8 +285,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -325,8 +305,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>11</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -337,8 +317,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>12</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -349,8 +329,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>13</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -361,8 +341,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>14</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -381,8 +361,8 @@
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<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<GroupNumber>4</GroupNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -393,8 +373,8 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@ -405,8 +385,8 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@ -417,8 +397,8 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@ -429,8 +409,8 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@ -441,8 +421,8 @@
<bShared>0</bShared>
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<GroupNumber>4</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -453,8 +433,8 @@
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<FileNumber>20</FileNumber>
<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -465,8 +445,8 @@
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<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -477,8 +457,8 @@
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<File>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -488,30 +468,6 @@
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<bShared>0</bShared>
</File>
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<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\spi\spi_core.c</PathWithFileName>
<FilenameWithoutPath>spi_core.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\spi\spi_dev.c</PathWithFileName>
<FilenameWithoutPath>spi_dev.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@ -521,8 +477,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>26</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -533,8 +489,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>27</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -545,8 +501,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -557,8 +513,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>29</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -569,20 +525,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\Drivers\drv_spi.c</PathWithFileName>
<FilenameWithoutPath>drv_spi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>31</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -601,8 +545,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>32</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -613,8 +557,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>33</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -625,8 +569,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>34</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -637,8 +581,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>35</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -657,8 +601,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>36</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -669,8 +613,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>37</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -681,8 +625,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>38</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -693,8 +637,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>39</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -705,8 +649,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>40</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -717,8 +661,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>41</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -729,8 +673,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>42</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -741,8 +685,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>43</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -753,8 +697,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>44</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -765,8 +709,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>45</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -777,8 +721,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>46</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -789,8 +733,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>47</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -801,8 +745,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>48</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -821,8 +765,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>49</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -833,20 +777,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_spi.c</PathWithFileName>
<FilenameWithoutPath>apm32f0xx_spi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>51</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -857,8 +789,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>52</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -869,8 +801,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>53</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>48</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -881,8 +813,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>54</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -893,8 +825,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>55</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -905,8 +837,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>56</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

32
bsp/apm32/apm32f091vc-miniboard/project.uvprojx
View File

@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, APM32F091xC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F0xx_Library\CMSIS\Include;..\libraries\Drivers\config;board;..\..\..\components\finsh;..\..\..\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\stdio;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\..\..\components\drivers\include;..\libraries\Drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\libcpu\arm\common;applications;..\..\..\components\libc\compilers\common\extension;.;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\utilities\libadt</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;board\ports;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\Drivers;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\..\..\libcpu\arm\common;..\libraries\APM32F0xx_Library\CMSIS\Include;applications;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -380,16 +380,6 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>ADT</GroupName>
<Files>
<File>
<FileName>avl.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\utilities\libadt\avl.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Applications</GroupName>
<Files>
@ -518,16 +508,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
<File>
<FileName>spi_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
</File>
<File>
<FileName>spi_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
</File>
</Files>
</Group>
<Group>
@ -553,11 +533,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_spi.c</FilePath>
</File>
<File>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
@ -668,11 +643,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_eint.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_spi.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_misc.c</FileName>
<FileType>1</FileType>

7
bsp/apm32/apm32f091vc-miniboard/rtconfig.h
View File

@ -80,7 +80,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SPI
/* Using USB */
@ -142,9 +141,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -217,6 +213,7 @@
/* Other */
/* Signal IO */
@ -236,8 +233,6 @@
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_SPI
#define BSP_USING_SPI1
/* Board extended module Drivers */

19
bsp/apm32/apm32f103vb-miniboard/.config
View File

@ -210,6 +210,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -382,12 +383,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -402,6 +397,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -581,6 +577,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -719,6 +716,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -908,6 +906,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -937,10 +936,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -979,4 +985,5 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set

4
bsp/apm32/apm32f103vb-miniboard/board/Kconfig
View File

@ -184,6 +184,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT

9
bsp/apm32/apm32f103vb-miniboard/board/SConscript
View File

@ -12,20 +12,21 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.S']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.S']
# APM32F10X_LD || APM32F10X_MD || APM32F10X_HD || APM32F10X_CL
# You can select chips from the list above
CPPDEFINES = ['APM32F10X_MD']
CPPDEFINES = ['APM32F10X_HD']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

6
bsp/apm32/apm32f103vb-miniboard/board/board.h
View File

@ -41,6 +41,12 @@
#include "apm32f10x_iwdt.h"
#include "apm32f10x_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

34
bsp/apm32/apm32f103vb-miniboard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

22
bsp/apm32/apm32f103vb-miniboard/project.uvoptx
View File

@ -183,7 +183,7 @@
<Group>
<GroupName>Applications</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -363,7 +363,7 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -479,7 +479,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -502,8 +502,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_md.s</PathWithFileName>
<FilenameWithoutPath>startup_apm32f10x_md.s</FilenameWithoutPath>
<PathWithFileName>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</PathWithFileName>
<FilenameWithoutPath>startup_apm32f10x_hd.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@ -843,6 +843,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</PathWithFileName>
<FilenameWithoutPath>apm32f10x_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

13
bsp/apm32/apm32f103vb-miniboard/project.uvprojx
View File

@ -337,9 +337,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>APM32F10X_MD, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F10X_HD</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;board;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\components\drivers\include;.</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\libcpu\arm\cortex-m3;board;..\..\..\components\libc\compilers\common\extension;.;board\ports;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -519,9 +519,9 @@
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>startup_apm32f10x_md.s</FileName>
<FileName>startup_apm32f10x_hd.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_md.s</FilePath>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
@ -668,6 +668,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath>
</File>
<File>
<FileName>apm32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>

4
bsp/apm32/apm32f103vb-miniboard/rtconfig.h
View File

@ -144,9 +144,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -219,6 +216,7 @@
/* Other */
/* Signal IO */

62
bsp/apm32/apm32f103xe-minibroard/.config
View File

@ -60,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
@ -122,7 +123,29 @@ CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
@ -158,7 +181,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=512
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -221,6 +250,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -316,6 +346,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -392,12 +423,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -412,6 +437,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -519,6 +545,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
#
# peripheral libraries and drivers
@ -590,6 +617,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -728,6 +756,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -917,6 +946,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -946,10 +976,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -974,6 +1011,11 @@ CONFIG_SOC_SERIES_APM32F1=y
#
CONFIG_SOC_APM32F103ZE=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
@ -984,10 +1026,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_RTC_USING_LSE is not set
# CONFIG_BSP_RTC_USING_LSI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set

21
bsp/apm32/apm32f103xe-minibroard/board/Kconfig
View File

@ -7,6 +7,17 @@ config SOC_APM32F103ZE
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
@ -170,6 +181,16 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT

4
bsp/apm32/apm32f103xe-minibroard/board/SConscript
View File

@ -11,7 +11,11 @@ src = Split('''
board.c
''')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB

20
bsp/apm32/apm32f103xe-minibroard/board/board.c
View File

@ -43,3 +43,23 @@ void apm32_usart_init(void)
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
#endif
}
void apm32_msp_sdio_init(void *Instance)
{
GPIO_Config_T GPIO_InitStructure;
/* Enable the GPIO and DMA2 Clock */
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC | RCM_APB2_PERIPH_GPIOD);
/* Enable the SDIO Clock */
RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_SDIO);
/* Configure the GPIO pin */
GPIO_InitStructure.pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
GPIO_InitStructure.mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.pin = GPIO_PIN_2;
GPIO_Config(GPIOD, &GPIO_InitStructure);
}

13
bsp/apm32/apm32f103xe-minibroard/board/board.h
View File

@ -21,6 +21,7 @@
#include "apm32f10x_rcm.h"
#include "apm32f10x_eint.h"
#include "apm32f10x_usart.h"
#include "apm32f10x_dma.h"
#if defined(RT_USING_ADC)
#include "apm32f10x_adc.h"
@ -42,6 +43,18 @@
#include "apm32f10x_iwdt.h"
#include "apm32f10x_wwdt.h"
#endif
#if defined(BSP_USING_SDCARD)
#include "apm32f10x_sdio.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#if defined(BSP_USING_SDRAM)
#include "apm32f10x_dmc.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

34
bsp/apm32/apm32f103xe-minibroard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 496 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 496* 1024 , 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

66
bsp/apm32/apm32f103xe-minibroard/board/ports/sdcard_port.c Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int apm32_sdcard_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
return RT_EOK;
}
INIT_APP_EXPORT(apm32_sdcard_mount);
#endif /* BSP_USING_SDCARD */

739
bsp/apm32/apm32f103xe-minibroard/project.uvoptx
View File

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -73,11 +73,11 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<CpuCode>0</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@ -171,746 +171,15 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
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289
bsp/apm32/apm32f103xe-minibroard/project.uvprojx
View File

@ -1,46 +1,43 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F103ZE</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F1xx_DFP.1.0.9</PackID>
<PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -52,9 +49,9 @@
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
@ -62,8 +59,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -72,8 +69,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
@ -83,14 +80,14 @@
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
<SVCSIdString />
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -104,8 +101,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<CustomArgument />
<IncludeLibraryModules />
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
@ -114,7 +111,7 @@
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDllArguments />
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
@ -138,11 +135,11 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -175,7 +172,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<RvctDeviceName />
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -185,7 +182,6 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -309,7 +305,7 @@
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
<RvctStartVector />
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -336,10 +332,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<MiscControls />
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F10X_HD</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\dfs\include;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;.</IncludePath>
<Undefine />
<IncludePath>board;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\dfs\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\ipc;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board\ports;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\..\..\components\libc\posix\io\stdio;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;applications;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -352,12 +348,12 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
</VariousControls>
</Aads>
<LDads>
@ -369,13 +365,13 @@
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<pXoBase />
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
</LDads>
</TargetArmAds>
</TargetOption>
@ -398,36 +394,50 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
</Files>
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<FileName>syscalls.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
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<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
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<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
@ -443,16 +453,22 @@
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
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<File>
<FileName>showmem.c</FileName>
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<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
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<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
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<Files>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
@ -468,41 +484,99 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
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<File>
<FileName>dataqueue.c</FileName>
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<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
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<FileName>pipe.c</FileName>
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<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
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<FileName>ringblk_buf.c</FileName>
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<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
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<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
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<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
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@ -518,21 +592,29 @@
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@ -544,26 +626,53 @@
<GroupName>Filesystem</GroupName>
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@ -573,21 +682,29 @@
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@ -603,61 +720,85 @@
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@ -667,47 +808,69 @@
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<FileName>apm32f10x_sdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_sdio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>system_apm32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_rcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_eint.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
<apis />
<components />
<files />
</RTE>
</Project>

29
bsp/apm32/apm32f103xe-minibroard/rtconfig.h
View File

@ -36,6 +36,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@ -78,6 +79,21 @@
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* Device Drivers */
@ -88,6 +104,12 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 512
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@ -149,9 +171,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -224,6 +243,7 @@
/* Other */
/* Signal IO */
@ -236,6 +256,9 @@
#define SOC_APM32F103ZE
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO

19
bsp/apm32/apm32f107vc-evalboard/.config
View File

@ -212,6 +212,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -384,12 +385,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -404,6 +399,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -583,6 +579,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -721,6 +718,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -910,6 +908,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -939,10 +938,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -988,6 +994,7 @@ CONFIG_BSP_USING_UART4=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#

4
bsp/apm32/apm32f107vc-evalboard/board/Kconfig
View File

@ -214,6 +214,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT

2
bsp/apm32/apm32f107vc-evalboard/board/board.c
View File

@ -150,7 +150,7 @@ void phy_reset(void)
/*
* GPIO Configuration for ETH
*/
void ETH_GPIO_Configuration(void)
void apm32_msp_eth_init(void *instance)
{
#ifdef BSP_USING_ETH
GPIO_Config_T GPIO_ConfigStruct;

6
bsp/apm32/apm32f107vc-evalboard/board/board.h
View File

@ -44,6 +44,12 @@
#if defined(BSP_USING_ETH)
#include "apm32f10x_eth.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

34
bsp/apm32/apm32f107vc-evalboard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

234
bsp/apm32/apm32f107vc-evalboard/project.uvoptx
View File

@ -182,8 +182,8 @@
</Target>
<Group>
<GroupName>ADT</GroupName>
<tvExp>1</tvExp>
<GroupName>Applications</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -191,27 +191,7 @@
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\utilities\libadt\avl.c</PathWithFileName>
<FilenameWithoutPath>avl.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Applications</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>applications\main.c</PathWithFileName>
@ -228,8 +208,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>3</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -240,8 +220,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>4</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -252,8 +232,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -264,8 +244,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>6</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -276,8 +256,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -288,8 +268,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -300,8 +280,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>9</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -312,8 +292,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -332,8 +312,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>11</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -344,8 +324,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>12</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -356,8 +336,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>13</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -368,8 +348,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>14</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -388,8 +368,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -400,8 +380,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>16</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -412,8 +392,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>17</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -424,8 +404,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>18</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -436,8 +416,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>19</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -448,8 +428,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>20</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -460,8 +440,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>21</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -472,8 +452,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>22</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -484,8 +464,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>23</FileNumber>
<GroupNumber>4</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -504,8 +484,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>24</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -516,8 +496,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>25</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -528,8 +508,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>26</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -540,8 +520,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>27</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -552,8 +532,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -572,8 +552,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>29</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -584,8 +564,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>30</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -596,8 +576,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>31</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -608,8 +588,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>32</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -628,8 +608,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>33</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -640,8 +620,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>34</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -652,8 +632,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>35</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -664,8 +644,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>36</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -676,8 +656,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>37</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -688,8 +668,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>38</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -700,8 +680,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>39</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -712,8 +692,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>40</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -724,8 +704,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>41</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -736,8 +716,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>42</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -748,8 +728,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>43</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -760,8 +740,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>44</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -772,8 +752,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>45</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -792,8 +772,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>46</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -804,8 +784,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>47</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -816,8 +796,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>48</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -828,8 +808,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>49</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>48</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -840,8 +820,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>50</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -852,8 +832,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>51</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -863,6 +843,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</PathWithFileName>
<FilenameWithoutPath>apm32f10x_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

17
bsp/apm32/apm32f107vc-evalboard/project.uvprojx
View File

@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>APM32F10X_CL, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\Drivers\config;board\ports;..\..\..\components\finsh;..\..\..\include;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;.;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\libraries\Drivers;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;board;applications;..\..\..\libcpu\arm\cortex-m3;..\..\..\libcpu\arm\common;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\utilities\libadt</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;.;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\drivers\include;board;applications;board\ports;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -380,16 +380,6 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>ADT</GroupName>
<Files>
<File>
<FileName>avl.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\utilities\libadt\avl.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Applications</GroupName>
<Files>
@ -678,6 +668,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath>
</File>
<File>
<FileName>apm32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>

4
bsp/apm32/apm32f107vc-evalboard/rtconfig.h
View File

@ -147,9 +147,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -222,6 +219,7 @@
/* Other */
/* Signal IO */

23
bsp/apm32/apm32f407zg-evalboard/.config
View File

@ -212,6 +212,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@ -384,12 +385,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@ -405,6 +400,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@ -584,6 +580,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@ -722,6 +719,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -911,6 +909,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@ -940,10 +939,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -973,6 +979,8 @@ CONFIG_SOC_APM32F407ZG=y
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_ETH is not set
#
@ -989,7 +997,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_DMC is not set
#
# Board extended module Drivers

26
bsp/apm32/apm32f407zg-evalboard/board/Kconfig
View File

@ -23,6 +23,18 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_SFDP
default n
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
select BSP_USING_DMC
default n
config BSP_USING_ETH
bool "Enable Ethernet"
default n
@ -242,11 +254,25 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_DMC
bool
default n
endmenu
menu "Board extended module Drivers"

6
bsp/apm32/apm32f407zg-evalboard/board/SConscript
View File

@ -14,6 +14,12 @@ board.c
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash_init.c')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
if GetDepend(['BSP_USING_SDRAM']):
src += Glob('ports/drv_sdram.c')
path = [cwd]
path += [cwd + '/ports']

37
bsp/apm32/apm32f407zg-evalboard/board/board.c
View File

@ -149,7 +149,7 @@ void phy_reset(void)
/*
* GPIO Configuration for ETH
*/
void ETH_GPIO_Configuration(void)
void apm32_msp_eth_init(void *instance)
{
#ifdef BSP_USING_ETH
GPIO_Config_T GPIO_ConfigStruct;
@ -202,3 +202,38 @@ void ETH_GPIO_Configuration(void)
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_7, GPIO_AF_ETH);
#endif
}
void apm32_msp_sdio_init(void *Instance)
{
GPIO_Config_T GPIO_InitStructure;
/* Enable the GPIO Clock */
RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOC | RCM_AHB1_PERIPH_GPIOD);
/* Enable the SDIO Clock */
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SDIO);
/* Enable the SDIO peripheral reset */
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SDIO);
/* Configure the GPIO pin */
GPIO_InitStructure.pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
GPIO_InitStructure.mode = GPIO_MODE_AF;
GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
GPIO_InitStructure.otype = GPIO_OTYPE_PP;
GPIO_InitStructure.pupd = GPIO_PUPD_UP;
GPIO_Config(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.pin = GPIO_PIN_2;
GPIO_Config(GPIOD, &GPIO_InitStructure);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_8, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_9, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_10, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_11, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_12, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOD,GPIO_PIN_SOURCE_2, GPIO_AF_SDIO);
/* Disable the SDIO peripheral reset */
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SDIO);
}

13
bsp/apm32/apm32f407zg-evalboard/board/board.h
View File

@ -21,6 +21,7 @@
#include "apm32f4xx_rcm.h"
#include "apm32f4xx_eint.h"
#include "apm32f4xx_usart.h"
#include "apm32f4xx_dma.h"
#if defined(RT_USING_ADC)
#include "apm32f4xx_adc.h"
@ -45,6 +46,18 @@
#if defined(BSP_USING_ETH)
#include "apm32f4xx_eth.h"
#endif
#if defined(BSP_USING_SDCARD)
#include "apm32f4xx_sdio.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f4xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f4xx_can.h"
#endif
#if defined(BSP_USING_SDRAM)
#include "apm32f4xx_dmc.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"

245
bsp/apm32/apm32f407zg-evalboard/board/ports/drv_sdram.c Normal file
View File

@ -0,0 +1,245 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#include <board.h>
#ifdef BSP_USING_SDRAM
#include "drv_sdram.h"
#define DRV_DEBUG
#define LOG_TAG "drv.sdram"
#include <drv_log.h>
/* SDRAM GPIO Clock */
#define RCM_SDRAM_GPIO_PERIPH (RCM_AHB1_PERIPH_GPIOA | \
RCM_AHB1_PERIPH_GPIOD | \
RCM_AHB1_PERIPH_GPIOF | \
RCM_AHB1_PERIPH_GPIOG | \
RCM_AHB1_PERIPH_GPIOH | \
RCM_AHB1_PERIPH_GPIOI )
#ifdef RT_USING_MEMHEAP_AS_HEAP
static struct rt_memheap system_heap;
#endif
/**
* @brief sdram gpio init
* @param None
* @retval None
*/
static void SDRAM_GPIO_Init(void)
{
GPIO_Config_T gpioConfig;
RCM_EnableAHB1PeriphClock(RCM_SDRAM_GPIO_PERIPH);
gpioConfig.speed = GPIO_SPEED_50MHz;
gpioConfig.mode = GPIO_MODE_AF;
gpioConfig.otype = GPIO_OTYPE_PP;
gpioConfig.pupd = GPIO_PUPD_NOPULL;
gpioConfig.pin = GPIO_PIN_10 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 |
GPIO_PIN_15;
GPIO_Config(GPIOD, &gpioConfig);
GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_12, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_13, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_14, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOD, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
gpioConfig.pin = GPIO_PIN_0 | GPIO_PIN_1 |
GPIO_PIN_2 | GPIO_PIN_3 |
GPIO_PIN_4 | GPIO_PIN_6 |
GPIO_PIN_7 | GPIO_PIN_8 |
GPIO_PIN_9 | GPIO_PIN_10 |
GPIO_PIN_11;
GPIO_Config(GPIOF, &gpioConfig);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_0, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_1, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_2, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_4, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_6, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_7, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_9, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOF, GPIO_PIN_SOURCE_11, GPIO_AF_FSMC);
gpioConfig.pin = GPIO_PIN_1 | GPIO_PIN_2 |
GPIO_PIN_3 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_6 |
GPIO_PIN_8 | GPIO_PIN_15;
GPIO_Config(GPIOG, &gpioConfig);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_1, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_2, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_4, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_5, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_6, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOG, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
gpioConfig.pin = GPIO_PIN_3 | GPIO_PIN_5 |
GPIO_PIN_8 | GPIO_PIN_10 |
GPIO_PIN_13 | GPIO_PIN_15;
GPIO_Config(GPIOH, &gpioConfig);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_5, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_13, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOH, GPIO_PIN_SOURCE_15, GPIO_AF_FSMC);
gpioConfig.pin = GPIO_PIN_3 | GPIO_PIN_7 |
GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_11;
GPIO_Config(GPIOI, &gpioConfig);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_3, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_7, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_8, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_9, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_10, GPIO_AF_FSMC);
GPIO_ConfigPinAF(GPIOI, GPIO_PIN_SOURCE_11, GPIO_AF_FSMC);
}
static int SDRAM_Init(void)
{
int result = RT_EOK;
DMC_Config_T dmc_init_config;
DMC_TimingConfig_T dmc_timing_config;
/* Config the SDRAM clock prescaler */
RCM_ConfigSDRAM(RCM_SDRAM_DIV_4);
/* enable sdram clock */
RCM->AHB3CLKEN |= BIT0;
/* sdram gpio init */
SDRAM_GPIO_Init();
/* dmc timing config */
dmc_timing_config.latencyCAS = DMC_CAS_LATENCY_3; //!< Configure CAS latency period
dmc_timing_config.tARP = DMC_AUTO_REFRESH_10; //!< Configure auto refresh period
dmc_timing_config.tRAS = DMC_RAS_MINIMUM_2; //!< Configure line activation and precharging minimum time
dmc_timing_config.tCMD = DMC_ATA_CMD_1; //!< Configure active to active period
dmc_timing_config.tRCD = DMC_DELAY_TIME_1; //!< Configure RAS To CAS delay Time
dmc_timing_config.tRP = DMC_PRECHARGE_1; //!< Configure precharge period
dmc_timing_config.tWR = DMC_NEXT_PRECHARGE_2; //!< Configure time between the Last Data and The Next Precharge for write
dmc_timing_config.tXSR = 3; //!< Configure XSR0
dmc_timing_config.tRFP = 0x2F9; //!< Configure refresh Cycle
#if SDRAM_TARGET_BANK == 1
dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width
#else
dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width
#endif
dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase
dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width
dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width
dmc_init_config.timing = dmc_timing_config;
DMC_Config(&dmc_init_config);
DMC_ConfigOpenBank(DMC_BANK_NUMBER_2);
DMC_EnableAccelerateModule();
DMC_Enable();
LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", SDRAM_BANK_ADDR, SDRAM_SIZE, SDRAM_DATA_WIDTH);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
#endif
return result;
}
INIT_BOARD_EXPORT(SDRAM_Init);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
int sdram_test(void)
{
int i = 0;
uint32_t start_time = 0, time_cast = 0;
#if SDRAM_DATA_WIDTH == 8
char data_width = 1;
uint8_t data = 0;
#elif SDRAM_DATA_WIDTH == 16
char data_width = 2;
uint16_t data = 0;
#else
char data_width = 4;
uint32_t data = 0;
#endif
/* write data */
LOG_D("Writing the %ld bytes data, waiting....", SDRAM_SIZE);
start_time = rt_tick_get();
for (i = 0; i < SDRAM_SIZE / data_width; i++)
{
#if SDRAM_DATA_WIDTH == 8
*(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100);
#elif SDRAM_DATA_WIDTH == 16
*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000);
#else
*(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000);
#endif
}
time_cast = rt_tick_get() - start_time;
LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
/* read data */
LOG_D("start Reading and verifying data, waiting....");
for (i = 0; i < SDRAM_SIZE / data_width; i++)
{
#if SDRAM_DATA_WIDTH == 8
data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
if (data != i % 100)
{
LOG_E("SDRAM test failed!");
break;
}
#elif SDRAM_DATA_WIDTH == 16
data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
if (data != i % 1000)
{
LOG_E("SDRAM test failed!");
break;
}
#else
data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
if (data != i % 1000)
{
LOG_E("SDRAM test failed!");
break;
}
#endif
}
if (i >= SDRAM_SIZE / data_width)
{
LOG_D("SDRAM test success!");
}
return RT_EOK;
}
MSH_CMD_EXPORT(sdram_test, sdram test)
#endif /* FINSH_USING_MSH */
#endif /* DRV_DEBUG */
#endif /* BSP_USING_SDRAM */

41
bsp/apm32/apm32f407zg-evalboard/board/ports/drv_sdram.h Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#ifndef __DRV_SDRAM_H__
#define __DRV_SDRAM_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* apm32f407 Bank Addr: 0x60000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0x60000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers */
#define SDRAM_COLUMN_BITS DMC_COL_WIDTH_8
/* row bit numbers */
#define SDRAM_ROW_BITS DMC_ROW_WIDTH_11
#define SDRAM_SIZE ((uint32_t)0x200000)
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif

49
bsp/apm32/apm32f407zg-evalboard/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024)
#define FLASH_SIZE_GRANULARITY_64K (64 * 1024)
#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024)
#define APM32_FLASH_START_ADRESS_16K APM32_FLASH_START_ADRESS
#define APM32_FLASH_START_ADRESS_64K (APM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K)
#define APM32_FLASH_START_ADRESS_128K (APM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K)
extern const struct fal_flash_dev apm32_onchip_flash_16k;
extern const struct fal_flash_dev apm32_onchip_flash_64k;
extern const struct fal_flash_dev apm32_onchip_flash_128k;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash_16k, \
&apm32_onchip_flash_64k, \
&apm32_onchip_flash_128k, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

66
bsp/apm32/apm32f407zg-evalboard/board/ports/sdcard_port.c Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int apm32_sdcard_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
return RT_EOK;
}
INIT_APP_EXPORT(apm32_sdcard_mount);
#endif /* BSP_USING_SDCARD */

18
bsp/apm32/apm32f407zg-evalboard/project.uvoptx
View File

@ -807,6 +807,18 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_dma.c</PathWithFileName>
<FilenameWithoutPath>apm32f4xx_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c</PathWithFileName>
<FilenameWithoutPath>apm32f4xx_eint.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@ -814,7 +826,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -826,7 +838,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>50</FileNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -838,7 +850,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileNumber>52</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

9
bsp/apm32/apm32f407zg-evalboard/project.uvprojx
View File

@ -10,7 +10,7 @@
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\io\poll;.;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F4xx_Library\CMSIS\Include;board;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;applications;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;board\ports;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc</IncludePath>
<IncludePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\Drivers;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\drivers\include;board\ports;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;.;applications;..\..\..\include;..\..\..\libcpu\arm\common;board;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -653,6 +653,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c</FilePath>
</File>
<File>
<FileName>apm32f4xx_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_dma.c</FilePath>
</File>
<File>
<FileName>apm32f4xx_eint.c</FileName>
<FileType>1</FileType>

4
bsp/apm32/apm32f407zg-evalboard/rtconfig.h
View File

@ -147,9 +147,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -222,6 +219,7 @@
/* Other */
/* Signal IO */

3
bsp/apm32/libraries/APM32F0xx_Library/SConscript
View File

@ -39,6 +39,9 @@ if GetDepend(['RT_USING_WDT']):
if GetDepend(['RT_USING_CAN']):
src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_fmc.c']
path = [cwd + '/Device/Geehy/APM32F0xx/Include',
cwd + '/APM32F0xx_StdPeriphDriver/inc',
cwd + '/CMSIS/Include']

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c
View File

@ -75,7 +75,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
uint32_t PCLK1 = 8000000, PCLK2 = 0;
uint16_t result = 0x04;
i2c->SWITCH = 0;
i2c->I2C_SWITCH = 0;
/* I2C CTRL2 Configuration */
RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
@ -399,7 +399,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
case I2C_REGISTER_RISETMAX:
return i2c->RISETMAX;
case I2C_REGISTER_SWITCH:
return i2c->SWITCH;
return i2c->I2C_SWITCH;
default:
return 0;
}

8
bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h
View File

@ -3351,11 +3351,11 @@ typedef struct
/* @brief I2C Switching register */
union
{
__IOM uint32_t SWITCH;
__IOM uint32_t I2C_SWITCH;
struct
{
__IOM uint32_t SWITCH : 1;
__IOM uint32_t I2C_SWITCH : 1;
__IM uint32_t RESERVED1 : 31;
} SWITCH_B;
};
@ -6111,11 +6111,11 @@ typedef struct
/* @brief Buffer table address register */
union
{
__IOM uint32_t SWITCH;
__IOM uint32_t USB_SWITCH;
struct
{
__IOM uint32_t SWITCH : 1;
__IOM uint32_t USB_SWITCH : 1;
__IM uint32_t RESERVED : 31;
} SWITCH_B;
};

13
bsp/apm32/libraries/APM32F10x_Library/SConscript
View File

@ -13,6 +13,7 @@ APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c
APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c
APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c
APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c
APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c
""")
if GetDepend(['RT_USING_ADC']):
@ -35,6 +36,18 @@ if GetDepend(['RT_USING_WDT']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c']
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c']
if GetDepend(['RT_USING_CAN']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_can.c']
if GetDepend(['RT_USING_SDIO']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c']
if GetDepend(['BSP_USING_SDRAM']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c']
if GetDepend(['BSP_USING_ETH']):
src += ['APM32F10x_ETH_Driver/src/apm32f10x_eth.c']

17
bsp/apm32/libraries/APM32F4xx_Library/SConscript
View File

@ -14,6 +14,7 @@ APM32F4xx_StdPeriphDriver/src/apm32f4xx_misc.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_rcm.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_usart.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_eint.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_dma.c
""")
if GetDepend(['RT_USING_ADC']):
@ -36,6 +37,18 @@ if GetDepend(['RT_USING_WDT']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_wwdt.c']
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_iwdt.c']
if GetDepend(['RT_USING_CAN']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_can.c']
if GetDepend(['RT_USING_SDIO']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_sdio.c']
if GetDepend(['BSP_USING_SDRAM']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_dmc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_fmc.c']
if GetDepend(['BSP_USING_ETH']):
src += ['APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c']
@ -45,6 +58,10 @@ path = [cwd + '/Device/Geehy/APM32F4xx/Include',
cwd + '/APM32F4xx_ETH_Driver/inc']
CPPDEFINES = ['USE_STDPERIPH_DRIVER']
if GetDepend(['BSP_USING_SDRAM']):
CPPDEFINES += ['DATA_IN_ExtSRAM']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

15
bsp/apm32/libraries/Drivers/SConscript
View File

@ -45,11 +45,26 @@ if GetDepend(['BSP_USING_WDT']):
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['BSP_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F0']):
src += ['drv_flash/drv_flash_f0.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F1']):
src += ['drv_flash/drv_flash_f1.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F4']):
src += ['drv_flash/drv_flash_f4.c']
src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [cwd + '/drv_flash']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

9
bsp/apm32/libraries/Drivers/drv_adc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -53,7 +53,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC2
@ -73,7 +72,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC3
@ -92,7 +90,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(F, 6),
GET_PIN(F, 7), GET_PIN(F, 8), GET_PIN(F, 9), GET_PIN(F, 10)
},
RT_NULL
},
#endif
};
@ -117,7 +114,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC2
@ -138,7 +134,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC3
@ -159,7 +154,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(F, 7), GET_PIN(F, 8), GET_PIN(F, 9), GET_PIN(F, 10), GET_PIN(F, 3),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
};
@ -184,7 +178,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4),
GET_PIN(C, 5)
},
RT_NULL
},
#endif
};

2
bsp/apm32/libraries/Drivers/drv_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_common.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

6
bsp/apm32/libraries/Drivers/drv_dac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if defined(BSP_USING_DAC1)
#define DBG_TAG "drv.dac"
#define DBG_LVL DBG_LOG//DBG_INFO
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
struct apm32_dac
@ -40,7 +40,6 @@ static struct apm32_dac dac_config[] =
DAC_WAVE_GENERATION_NONE,
DAC_TRIANGLEAMPLITUDE_4095,
},
RT_NULL,
#elif defined (SOC_SERIES_APM32F1) || defined (SOC_SERIES_APM32F4)
"dac1",
DAC,
@ -50,7 +49,6 @@ static struct apm32_dac dac_config[] =
DAC_WAVE_GENERATION_NONE,
DAC_TRIANGLE_AMPLITUDE_4095,
},
RT_NULL,
#endif
}
#endif

10
bsp/apm32/libraries/Drivers/drv_eth.c
View File

@ -471,7 +471,7 @@ rt_err_t rt_apm32_eth_tx( rt_device_t dev, struct pbuf* p)
/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
to = (uint8_t*)((DMATxDescToSet->Buffer1Addr) + offset);
memcpy(to, q->payload, q->len);
SMEMCPY(to, q->payload, q->len);
offset += q->len;
}
#ifdef ETH_TX_DUMP
@ -552,7 +552,7 @@ struct pbuf *rt_apm32_eth_rx(rt_device_t dev)
for (q = p; q != RT_NULL; q= q->next)
{
/* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
memcpy(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len);
SMEMCPY(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len);
offset += q->len;
}
#ifdef ETH_RX_DUMP
@ -724,11 +724,13 @@ static void phy_monitor_thread_entry(void *parameter)
static int rt_hw_apm32_eth_init(void)
{
/* reset phy */
extern void phy_reset(void);
phy_reset();
void ETH_GPIO_Configuration(void);
ETH_GPIO_Configuration();
/* apm32 eth gpio init */
extern void apm32_msp_eth_init(void *instance);
apm32_msp_eth_init(RT_NULL);
apm32_eth_device.ETH_Speed = ETH_SPEED_100M;
apm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;

2
bsp/apm32/libraries/Drivers/drv_eth.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

31
bsp/apm32/libraries/Drivers/drv_flash/drv_flash.h Normal file
View File

@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int apm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int apm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int apm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */

212
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f0.c Normal file
View File

@ -0,0 +1,212 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_flash.h"
#if defined(RT_USING_FAL)
#include "fal.h"
#endif
#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#if (defined(APM32F030x6) || defined(APM32F030x8) || defined(APM32F051))
#define FLASH_PAGE_SIZE 0x400U
#elif (defined(APM32F030xC) || defined(APM32F070xB) || defined(APM32F071) || defined(APM32F072) || defined(APM32F091))
#define FLASH_PAGE_SIZE 0x800U
#endif
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int apm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > APM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int apm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > APM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
FMC_Unlock();
while (addr < end_addr)
{
if (FMC_ProgramWord(addr, *((rt_uint32_t *)buf)) == FMC_STATE_COMPLETE)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
FMC_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* @brief erase data on flash .
* @note this operation is irreversible.
* @note this operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int apm32_flash_erase(rt_uint32_t addr, rt_uint32_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t start_addr = addr;
rt_uint32_t end_addr = addr + size;
rt_uint32_t page_addr = 0;
FMC_Unlock();
if ((end_addr) > APM32_FLASH_END_ADDRESS)
{
LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
/* clear program error flag */
if (FMC_ReadStatusFlag(FMC_FLAG_PE) == SET)
{
FMC_ClearStatusFlag(FMC_FLAG_PE);
}
while(addr < end_addr)
{
page_addr = GetPage(addr);
if(FMC_ErasePage(page_addr) != FMC_STATE_COMPLETE)
{
result = -RT_ERROR;
goto __exit;
}
addr += FLASH_PAGE_SIZE;
}
__exit:
FMC_Lock();
if(result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)start_addr, size);
return size;
}
#if defined(RT_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev apm32_onchip_flash = { "onchip_flash", APM32_FLASH_START_ADRESS, APM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return apm32_flash_read(apm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return apm32_flash_write(apm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return apm32_flash_erase(apm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */

212
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f1.c Normal file
View File

@ -0,0 +1,212 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_flash.h"
#if defined(RT_USING_FAL)
#include "fal.h"
#endif
#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#if (defined(APM32F10X_HD) || defined(APM32F10X_CL))
#define FLASH_PAGE_SIZE 0x800U
#elif (defined(APM32F10X_LD) || defined(APM32F10X_MD))
#define FLASH_PAGE_SIZE 0x400U
#endif
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int apm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > APM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int apm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > APM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
FMC_Unlock();
while (addr < end_addr)
{
if (FMC_ProgramWord(addr, *((rt_uint32_t *)buf)) == FMC_STATUS_COMPLETE)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
FMC_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* @brief erase data on flash .
* @note this operation is irreversible.
* @note this operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int apm32_flash_erase(rt_uint32_t addr, rt_uint32_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t start_addr = addr;
rt_uint32_t end_addr = addr + size;
rt_uint32_t page_addr = 0;
FMC_Unlock();
if ((end_addr) > APM32_FLASH_END_ADDRESS)
{
LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
/* clear program error flag */
if (FMC_ReadStatus() == FMC_STATUS_ERROR_PG)
{
FMC_ClearStatusFlag(FMC_FLAG_PE);
}
while(addr < end_addr)
{
page_addr = GetPage(addr);
if(FMC_ErasePage(page_addr) != FMC_STATUS_COMPLETE)
{
result = -RT_ERROR;
goto __exit;
}
addr += FLASH_PAGE_SIZE;
}
__exit:
FMC_Lock();
if(result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)start_addr, size);
return size;
}
#if defined(RT_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev apm32_onchip_flash = { "onchip_flash", APM32_FLASH_START_ADRESS, APM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return apm32_flash_read(apm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return apm32_flash_write(apm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return apm32_flash_erase(apm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */

384
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f4.c Normal file
View File

@ -0,0 +1,384 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_flash.h"
#if defined(RT_USING_FAL)
#include "fal.h"
#endif
#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/* Base address of the Flash sectors */
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
/**
* @brief Gets the sector of a given address
* @param None
* @retval The sector of a given address
*/
static rt_uint32_t GetSector(rt_uint32_t Address)
{
rt_uint32_t sector = 0;
if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FMC_SECTOR_0;
}
else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
{
sector = FMC_SECTOR_1;
}
else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
{
sector = FMC_SECTOR_2;
}
else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
{
sector = FMC_SECTOR_3;
}
else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
{
sector = FMC_SECTOR_4;
}
else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
{
sector = FMC_SECTOR_5;
}
else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
{
sector = FMC_SECTOR_6;
}
else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
{
sector = FMC_SECTOR_7;
}
else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
{
sector = FMC_SECTOR_8;
}
else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
{
sector = FMC_SECTOR_9;
}
else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
{
sector = FMC_SECTOR_10;
}
else if((Address < APM32_FLASH_END_ADDRESS) && (Address >= ADDR_FLASH_SECTOR_11))
{
sector = FMC_SECTOR_11;
}
return sector;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int apm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > APM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void*)(addr + size));
return -1;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int apm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
rt_uint32_t written_size = 0;
rt_uint32_t write_size = 0;
if ((end_addr) > APM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void*)(addr + size));
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
FMC_Unlock();
FMC_ClearStatusFlag(FMC_FLAG_ENDOP | FMC_FLAG_ERROP | FMC_FLAG_ERRWRP | FMC_FLAG_ERRPGA | FMC_FLAG_ERRPGP | FMC_FLAG_ERRPGS);
while (written_size < size)
{
if (((addr + written_size) % 4 == 0) && (size - written_size >= 4))
{
if (FMC_ProgramWord(addr + written_size, *((rt_uint32_t *)(buf + written_size))) == FMC_COMPLETE)
{
if (*(rt_uint32_t *)(addr + written_size) != *(rt_uint32_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 4;
}
else if (((addr + written_size) % 2 == 0) && (size - written_size >= 2))
{
if (FMC_ProgramHalfWord(addr + written_size, *((rt_uint16_t *)(buf + written_size))) == FMC_COMPLETE)
{
if (*(rt_uint16_t *)(addr + written_size) != *(rt_uint16_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 2;
}
else
{
if (FMC_ProgramByte(addr + written_size, *((rt_uint8_t *)(buf + written_size))) == FMC_COMPLETE)
{
if (*(rt_uint8_t *)(addr + written_size) != *(rt_uint8_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 1;
}
written_size += write_size;
}
FMC_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int apm32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t FirstSector = 0, NbOfSectors = 0;
rt_uint32_t index = 0;
if ((addr + size) > APM32_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
/* Unlock the Flash to enable the flash control register access */
FMC_Unlock();
FMC_ClearStatusFlag(FMC_FLAG_ENDOP | FMC_FLAG_ERROP | FMC_FLAG_ERRWRP | FMC_FLAG_ERRPGA | FMC_FLAG_ERRPGP | FMC_FLAG_ERRPGS);
/* Get the 1st sector to erase */
FirstSector = GetSector(addr) >> 3;
/* Get the number of sector to erase from 1st sector */
NbOfSectors = (GetSector(addr + size - 1) >> 3) - FirstSector + 1;
/* Erase by sector by sector to be done */
for (index = FirstSector; index < (FirstSector + NbOfSectors); index++)
{
if (FMC_EraseSector((FMC_SECTOR_T)(index << 3), FMC_VOLTAGE_3) != FMC_COMPLETE)
{
result = -RT_ERROR;
goto __exit;
}
}
__exit:
FMC_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void*)addr, size);
return size;
}
#if defined(RT_USING_FAL)
static int fal_flash_read_16k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_read_64k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write_16k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_write_64k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase_16k(long offset, size_t size);
static int fal_flash_erase_64k(long offset, size_t size);
static int fal_flash_erase_128k(long offset, size_t size);
const struct fal_flash_dev apm32_onchip_flash_16k =
{
"onchip_flash_16k",
APM32_FLASH_START_ADRESS_16K,
FLASH_SIZE_GRANULARITY_16K,
(16 * 1024),
{
NULL,
fal_flash_read_16k,
fal_flash_write_16k,
fal_flash_erase_16k,
},
8,
};
const struct fal_flash_dev apm32_onchip_flash_64k =
{
"onchip_flash_64k",
APM32_FLASH_START_ADRESS_64K,
FLASH_SIZE_GRANULARITY_64K,
(64 * 1024),
{
NULL,
fal_flash_read_64k,
fal_flash_write_64k,
fal_flash_erase_64k,
},
8,
};
const struct fal_flash_dev apm32_onchip_flash_128k =
{
"onchip_flash_128k",
APM32_FLASH_START_ADRESS_128K,
FLASH_SIZE_GRANULARITY_128K,
(128 * 1024),
{
NULL,
fal_flash_read_128k,
fal_flash_write_128k,
fal_flash_erase_128k,
},
8,
};
static int fal_flash_read_16k(long offset, rt_uint8_t *buf, size_t size)
{
return apm32_flash_read(apm32_onchip_flash_16k.addr + offset, buf, size);
}
static int fal_flash_read_64k(long offset, rt_uint8_t *buf, size_t size)
{
return apm32_flash_read(apm32_onchip_flash_64k.addr + offset, buf, size);
}
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
{
return apm32_flash_read(apm32_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_write_16k(long offset, const rt_uint8_t *buf, size_t size)
{
return apm32_flash_write(apm32_onchip_flash_16k.addr + offset, buf, size);
}
static int fal_flash_write_64k(long offset, const rt_uint8_t *buf, size_t size)
{
return apm32_flash_write(apm32_onchip_flash_64k.addr + offset, buf, size);
}
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
{
return apm32_flash_write(apm32_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_erase_16k(long offset, size_t size)
{
return apm32_flash_erase(apm32_onchip_flash_16k.addr + offset, size);
}
static int fal_flash_erase_64k(long offset, size_t size)
{
return apm32_flash_erase(apm32_onchip_flash_64k.addr + offset, size);
}
static int fal_flash_erase_128k(long offset, size_t size)
{
return apm32_flash_erase(apm32_onchip_flash_128k.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */

17
bsp/apm32/libraries/Drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,6 +8,7 @@
* 2020-08-20 Abbcc first version
* 2022-07-15 Aligagago add apm32F4 serie MCU support
* 2022-12-26 luobeihai add apm32F0 serie MCU support
* 2022-03-18 luobeihai fix warning about incompatible function pointer types
*/
#include <board.h>
@ -152,7 +153,7 @@ static rt_base_t apm32_pin_get(const char *name)
return pin;
}
static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
{
GPIO_T *gpio_port;
uint16_t gpio_pin;
@ -169,7 +170,7 @@ static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
}
}
static int apm32_pin_read(rt_device_t dev, rt_base_t pin)
static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_T *gpio_port;
uint16_t gpio_pin;
@ -185,7 +186,7 @@ static int apm32_pin_read(rt_device_t dev, rt_base_t pin)
return value;
}
static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
GPIO_Config_T gpioConfig;
@ -325,8 +326,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
return &pin_irq_map[mapindex];
};
static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
rt_uint8_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
@ -365,7 +366,7 @@ static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
return RT_EOK;
}
static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
@ -397,7 +398,7 @@ static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
}
static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
rt_uint8_t enabled)
{
const struct pin_irq_map *irqmap;
rt_base_t level;

2
bsp/apm32/libraries/Drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_log.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

24
bsp/apm32/libraries/Drivers/drv_rtc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,6 +8,7 @@
* 2022-03-04 stevetong459 first version
* 2022-07-15 Aligagago add apm32F4 serie MCU support
* 2022-12-26 luobeihai add apm32F0 serie MCU support
* 2023-03-18 luobeihai fix RT-Thread Studio compile error bug
*/
#include "board.h"
@ -131,7 +132,7 @@ static rt_err_t apm32_rtc_init(void)
*
* @return RT_EOK indicates successful initialize, other value indicates failed;
*/
static rt_err_t apm32_rtc_get_secs(time_t *sec)
static rt_err_t apm32_rtc_get_secs(void *args)
{
volatile rt_uint32_t counter = 0;
@ -143,12 +144,12 @@ static rt_err_t apm32_rtc_get_secs(time_t *sec)
}
}
*(timer_t *) sec = RTC_ReadCounter();
*(rt_uint32_t *) args = RTC_ReadCounter();
return RT_EOK;
}
static rt_err_t apm32_rtc_set_secs(time_t *sec)
static rt_err_t apm32_rtc_set_secs(void *args)
{
volatile rt_uint32_t counter = 0;
@ -165,13 +166,15 @@ static rt_err_t apm32_rtc_set_secs(time_t *sec)
}
}
RTC_ConfigCounter(*(rt_uint32_t *)sec);
RTC_ConfigCounter(*(rt_uint32_t *)args);
return RT_EOK;
}
#elif defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4)
static rt_err_t apm32_rtc_get_timeval(struct timeval *tv)
static rt_err_t apm32_rtc_get_timeval(void *args)
{
struct timeval *tv = (struct timeval *) args;
#if defined(SOC_SERIES_APM32F0)
RTC_TIME_T timeConfig;
RTC_DATE_T dateConfig;
@ -233,7 +236,6 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
#endif
dateConfig.year = tm.tm_year - 100;
RTC_ConfigTime(RTC_FORMAT_BIN, &timeConfig);
RTC_ConfigDate(RTC_FORMAT_BIN, &dateConfig);
@ -248,20 +250,20 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
*
* @return RT_EOK indicates successful initialize, other value indicates failed;
*/
static rt_err_t apm32_rtc_get_secs(time_t *sec)
static rt_err_t apm32_rtc_get_secs(void *args)
{
struct timeval tv;
apm32_rtc_get_timeval(&tv);
*(time_t *) sec = tv.tv_sec;
*(rt_uint32_t *) args = tv.tv_sec;
return RT_EOK;
}
static rt_err_t apm32_rtc_set_secs(time_t *sec)
static rt_err_t apm32_rtc_set_secs(void *args)
{
rt_err_t result = RT_EOK;
if (set_rtc_time_stamp(*sec))
if (set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}

882
bsp/apm32/libraries/Drivers/drv_sdio.c Normal file
View File

@ -0,0 +1,882 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-14 luobeihai first version
*/
#include "board.h"
#include "drv_sdio.h"
#ifdef BSP_USING_SDIO
//#define DRV_DEBUG
#define LOG_TAG "drv.sdio"
#include <drv_log.h>
static struct apm32_sdio_config sdio_config = SDIO_BUS_CONFIG;
static struct apm32_sdio_class sdio_obj;
static struct rt_mmcsd_host *host;
#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000)
#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
struct sdio_pkg
{
struct rt_mmcsd_cmd *cmd;
void *buff;
rt_uint32_t flag;
};
struct rthw_sdio
{
struct rt_mmcsd_host *host;
struct apm32_sdio_des sdio_des;
struct rt_event event;
struct rt_mutex mutex;
struct sdio_pkg *pkg;
};
rt_align(SDIO_ALIGN_LEN)
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
static rt_uint32_t apm32_sdio_clk_get(struct apm32_sdio *hw_sdio)
{
return SDIO_CLOCK_FREQ;
}
/**
* @brief This function get order from sdio.
* @param data
* @retval sdio order
*/
static int get_order(rt_uint32_t data)
{
int order = 0;
switch (data)
{
case 1:
order = 0;
break;
case 2:
order = 1;
break;
case 4:
order = 2;
break;
case 8:
order = 3;
break;
case 16:
order = 4;
break;
case 32:
order = 5;
break;
case 64:
order = 6;
break;
case 128:
order = 7;
break;
case 256:
order = 8;
break;
case 512:
order = 9;
break;
case 1024:
order = 10;
break;
case 2048:
order = 11;
break;
case 4096:
order = 12;
break;
case 8192:
order = 13;
break;
case 16384:
order = 14;
break;
default :
order = 0;
break;
}
return order;
}
/**
* @brief This function wait sdio completed.
* @param sdio rthw_sdio
* @retval None
*/
static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
{
rt_uint32_t status;
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait completed timeout");
cmd->err = -RT_ETIMEOUT;
return;
}
if (sdio->pkg == RT_NULL)
{
return;
}
cmd->resp[0] = hw_sdio->resp1;
cmd->resp[1] = hw_sdio->resp2;
cmd->resp[2] = hw_sdio->resp3;
cmd->resp[3] = hw_sdio->resp4;
if (status & HW_SDIO_ERRORS)
{
if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
{
cmd->err = RT_EOK;
}
else
{
cmd->err = -RT_ERROR;
}
if (status & HW_SDIO_IT_CTIMEOUT)
{
cmd->err = -RT_ETIMEOUT;
}
if (status & HW_SDIO_IT_DCRCFAIL)
{
data->err = -RT_ERROR;
}
if (status & HW_SDIO_IT_DTIMEOUT)
{
data->err = -RT_ETIMEOUT;
}
if (cmd->err == RT_EOK)
{
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
else
{
LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
status,
status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
status == 0 ? "NULL" : "",
cmd->cmd_code,
cmd->arg,
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0
);
}
}
else
{
cmd->err = RT_EOK;
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
}
/**
* @brief This function transfer data by dma.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_data *data;
int size;
void *buff;
struct apm32_sdio *hw_sdio;
if ((RT_NULL == pkg) || (RT_NULL == sdio))
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
data = pkg->cmd->data;
if (RT_NULL == data)
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
buff = pkg->buff;
if (RT_NULL == buff)
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
hw_sdio = sdio->sdio_des.hw_sdio;
size = data->blks * data->blksize;
if (data->flags & DATA_DIR_WRITE)
{
sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size);
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE;
}
else if (data->flags & DATA_DIR_READ)
{
sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size);
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE;
}
}
/**
* @brief This function send command.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t reg_cmd;
/* save pkg */
sdio->pkg = pkg;
LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
cmd->cmd_code,
cmd->arg,
resp_type(cmd) == RESP_NONE ? "NONE" : "",
resp_type(cmd) == RESP_R1 ? "R1" : "",
resp_type(cmd) == RESP_R1B ? "R1B" : "",
resp_type(cmd) == RESP_R2 ? "R2" : "",
resp_type(cmd) == RESP_R3 ? "R3" : "",
resp_type(cmd) == RESP_R4 ? "R4" : "",
resp_type(cmd) == RESP_R5 ? "R5" : "",
resp_type(cmd) == RESP_R6 ? "R6" : "",
resp_type(cmd) == RESP_R7 ? "R7" : "",
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0
);
/* config cmd reg */
reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE;
if (resp_type(cmd) == RESP_NONE)
reg_cmd |= HW_SDIO_RESPONSE_NO;
else if (resp_type(cmd) == RESP_R2)
reg_cmd |= HW_SDIO_RESPONSE_LONG;
else
reg_cmd |= HW_SDIO_RESPONSE_SHORT;
/* config data reg */
if (data != RT_NULL)
{
rt_uint32_t dir = 0;
rt_uint32_t size = data->blks * data->blksize;
int order;
hw_sdio->dctrl = 0;
hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
hw_sdio->dlen = size;
order = get_order(data->blksize);
dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir;
}
/* transfer config */
if (data != RT_NULL)
{
rthw_sdio_transfer_by_dma(sdio, pkg);
}
/* open irq */
hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS;
if (data != RT_NULL)
{
hw_sdio->mask |= HW_SDIO_IT_DATAEND;
}
/* send cmd */
hw_sdio->arg = cmd->arg;
hw_sdio->cmd = reg_cmd;
/* wait completed */
rthw_sdio_wait_completed(sdio);
/* Waiting for data to be sent to completion */
if (data != RT_NULL)
{
volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT)))
{
count--;
}
if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS))
{
cmd->err = -RT_ERROR;
}
}
/* close irq, keep sdio irq */
hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00;
/* clear pkg */
sdio->pkg = RT_NULL;
}
/**
* @brief This function send sdio request.
* @param host rt_mmcsd_host
* @param req request
* @retval None
*/
static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct sdio_pkg pkg;
struct rthw_sdio *sdio = host->private_data;
struct rt_mmcsd_data *data;
RTHW_SDIO_LOCK(sdio);
if (req->cmd != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
if (data != RT_NULL)
{
rt_uint32_t size = data->blks * data->blksize;
RT_ASSERT(size <= SDIO_BUFF_SIZE);
pkg.buff = data->buf;
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
{
pkg.buff = cache_buf;
if (data->flags & DATA_DIR_WRITE)
{
rt_memcpy(cache_buf, data->buf, size);
}
}
}
rthw_sdio_send_command(sdio, &pkg);
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
{
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
}
}
if (req->stop != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rthw_sdio_send_command(sdio, &pkg);
}
RTHW_SDIO_UNLOCK(sdio);
mmcsd_req_complete(sdio->host);
}
/**
* @brief This function config sdio.
* @param host rt_mmcsd_host
* @param io_cfg rt_mmcsd_io_cfg
* @retval None
*/
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t clkcr, div, clk_src;
rt_uint32_t clk = io_cfg->clock;
struct rthw_sdio *sdio = host->private_data;
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
if (clk_src < 400 * 1000)
{
LOG_E("The clock rate is too low! rata:%d", clk_src);
return;
}
if (clk > host->freq_max) clk = host->freq_max;
if (clk > clk_src)
{
LOG_W("Setting rate is greater than clock source rate.");
clk = clk_src;
}
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
clk,
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
);
RTHW_SDIO_LOCK(sdio);
div = clk_src / clk;
if ((clk == 0) || (div == 0))
{
clkcr = 0;
}
else
{
if (div < 2)
{
div = 2;
}
else if (div > 0xFF)
{
div = 0xFF;
}
div -= 2;
clkcr = div | HW_SDIO_CLK_ENABLE;
}
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
{
clkcr |= HW_SDIO_BUSWIDE_8B;
}
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
{
clkcr |= HW_SDIO_BUSWIDE_4B;
}
else
{
clkcr |= HW_SDIO_BUSWIDE_1B;
}
hw_sdio->clkcr = clkcr;
switch (io_cfg->power_mode)
{
case MMCSD_POWER_OFF:
hw_sdio->power = HW_SDIO_POWER_OFF;
break;
case MMCSD_POWER_UP:
hw_sdio->power = HW_SDIO_POWER_UP;
break;
case MMCSD_POWER_ON:
hw_sdio->power = HW_SDIO_POWER_ON;
break;
default:
LOG_W("unknown power_mode %d", io_cfg->power_mode);
break;
}
RTHW_SDIO_UNLOCK(sdio);
}
/**
* @brief This function update sdio interrupt.
* @param host rt_mmcsd_host
* @param enable
* @retval None
*/
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
{
struct rthw_sdio *sdio = host->private_data;
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
if (enable)
{
LOG_D("enable sdio irq");
hw_sdio->mask |= HW_SDIO_IT_SDIOIT;
}
else
{
LOG_D("disable sdio irq");
hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT;
}
}
/**
* @brief This function detect sdcard.
* @param host rt_mmcsd_host
* @retval 0x01
*/
static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
{
LOG_D("try to detect device");
return 0x01;
}
/**
* @brief This function interrupt process function.
* @param host rt_mmcsd_host
* @retval None
*/
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
{
int complete = 0;
struct rthw_sdio *sdio = host->private_data;
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t intstatus = hw_sdio->sta;
if (intstatus & HW_SDIO_ERRORS)
{
hw_sdio->icr = HW_SDIO_ERRORS;
complete = 1;
}
else
{
if (intstatus & HW_SDIO_IT_CMDREND)
{
hw_sdio->icr = HW_SDIO_IT_CMDREND;
if (sdio->pkg != RT_NULL)
{
if (!sdio->pkg->cmd->data)
{
complete = 1;
}
else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE))
{
hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE;
}
}
}
if (intstatus & HW_SDIO_IT_CMDSENT)
{
hw_sdio->icr = HW_SDIO_IT_CMDSENT;
if (resp_type(sdio->pkg->cmd) == RESP_NONE)
{
complete = 1;
}
}
if (intstatus & HW_SDIO_IT_DATAEND)
{
hw_sdio->icr = HW_SDIO_IT_DATAEND;
complete = 1;
}
}
if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT))
{
hw_sdio->icr = HW_SDIO_IT_SDIOIT;
sdio_irq_wakeup(host);
}
if (complete)
{
hw_sdio->mask &= ~HW_SDIO_ERRORS;
rt_event_send(&sdio->event, intstatus);
}
}
static const struct rt_mmcsd_host_ops ops =
{
rthw_sdio_request,
rthw_sdio_iocfg,
rthw_sd_detect,
rthw_sdio_irq_update,
};
/**
* @brief This function create mmcsd host.
* @param sdio_des apm32_sdio_des
* @retval rt_mmcsd_host
*/
struct rt_mmcsd_host *sdio_host_create(struct apm32_sdio_des *sdio_des)
{
struct rt_mmcsd_host *host;
struct rthw_sdio *sdio = RT_NULL;
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
{
LOG_E("L:%d F:%s %s %s %s",
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
);
return RT_NULL;
}
sdio = rt_malloc(sizeof(struct rthw_sdio));
if (sdio == RT_NULL)
{
LOG_E("L:%d F:%s malloc rthw_sdio fail");
return RT_NULL;
}
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
host = mmcsd_alloc_host();
if (host == RT_NULL)
{
LOG_E("L:%d F:%s mmcsd alloc host fail");
rt_free(sdio);
return RT_NULL;
}
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct apm32_sdio_des));
sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct apm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio);
sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? apm32_sdio_clk_get : sdio_des->clk_get);
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
/* set host defautl attributes */
host->ops = &ops;
host->freq_min = 400 * 1000;
host->freq_max = SDIO_MAX_FREQ;
host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
#ifndef SDIO_USING_1_BIT
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#else
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#endif
host->max_seg_size = SDIO_BUFF_SIZE;
host->max_dma_segs = 1;
host->max_blk_size = 512;
host->max_blk_count = 512;
/* link up host and sdio */
sdio->host = host;
host->private_data = sdio;
rthw_sdio_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
return host;
}
/**
* @brief This function configures the DMATX.
* @param BufferSRC: pointer to the source buffer
* @param BufferSize: buffer size
* @retval None
*/
void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
{
DMA_Config_T DMA_InitStructure;
static uint32_t size = 0;
size += BufferSize * 4;
sdio_obj.cfg = &sdio_config;
sdio_obj.dma.handle_tx = sdio_config.dma_tx.Instance;
#if defined (SOC_SERIES_APM32F1)
/* clear DMA flag */
DMA_ClearStatusFlag(DMA2_FLAG_GINT4 | DMA2_FLAG_TC4 | DMA2_FLAG_HT4 | DMA2_FLAG_TERR4);
/* Disable DMA */
DMA_Disable(sdio_obj.dma.handle_rx);
DMA_InitStructure.dir = DMA_DIR_PERIPHERAL_DST;
DMA_InitStructure.bufferSize = BufferSize;
DMA_InitStructure.memoryBaseAddr = (uint32_t)src;
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WOED;
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
DMA_InitStructure.peripheralBaseAddr = (uint32_t)dst;
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WOED;
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
DMA_InitStructure.M2M = DMA_M2MEN_DISABLE;
DMA_Config(sdio_obj.dma.handle_tx, &DMA_InitStructure);
DMA_Enable(sdio_obj.dma.handle_tx);
#elif defined (SOC_SERIES_APM32F4)
/* Wait DMA can be setting */
while (DMA_ReadCmdStatus(sdio_obj.dma.handle_tx) != DISABLE);
/* Clear all DMA intrrupt flag */
DMA_Reset(sdio_obj.dma.handle_tx);
DMA_InitStructure.channel = sdio_config.dma_tx.channel;
DMA_InitStructure.dir = DMA_DIR_MEMORYTOPERIPHERAL;
DMA_InitStructure.bufferSize = BufferSize;
DMA_InitStructure.memoryBaseAddr = (uint32_t)src;
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WORD;
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
DMA_InitStructure.memoryBurst = DMA_MEMORYBURST_INC4;
DMA_InitStructure.peripheralBaseAddr = (uint32_t)dst;
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WORD;
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
DMA_InitStructure.peripheralBurst = DMA_PERIPHERALBURST_INC4;
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
DMA_InitStructure.fifoMode = DMA_FIFOMODE_ENABLE;
DMA_InitStructure.fifoThreshold = DMA_FIFOTHRESHOLD_FULL;
DMA_Config(sdio_obj.dma.handle_tx, &DMA_InitStructure);
DMA_ConfigFlowController(sdio_obj.dma.handle_tx, DMA_FLOWCTRL_PERIPHERAL);
DMA_Enable(sdio_obj.dma.handle_tx);
#endif
}
/**
* @brief This function configures the DMARX.
* @param BufferDST: pointer to the destination buffer
* @param BufferSize: buffer size
* @retval None
*/
void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
{
DMA_Config_T DMA_InitStructure;
sdio_obj.cfg = &sdio_config;
sdio_obj.dma.handle_rx = sdio_config.dma_rx.Instance;
#if defined (SOC_SERIES_APM32F1)
/* clear DMA flag */
DMA_ClearStatusFlag(DMA2_FLAG_GINT4 | DMA2_FLAG_TC4 | DMA2_FLAG_HT4 | DMA2_FLAG_TERR4);
/* Disable DMA */
DMA_Disable(sdio_obj.dma.handle_rx);
DMA_InitStructure.dir = DMA_DIR_PERIPHERAL_SRC;
DMA_InitStructure.bufferSize = BufferSize;
DMA_InitStructure.memoryBaseAddr = (uint32_t)dst;
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WOED;
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
DMA_InitStructure.peripheralBaseAddr = (uint32_t)src;
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WOED;
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
DMA_InitStructure.M2M = DMA_M2MEN_DISABLE;
DMA_Config(sdio_obj.dma.handle_rx, &DMA_InitStructure);
DMA_Enable(sdio_obj.dma.handle_rx);
#elif defined (SOC_SERIES_APM32F4)
/* Wait DMA can be setting */
while (DMA_ReadCmdStatus(sdio_obj.dma.handle_rx) != DISABLE);
/* Clear all DMA intrrupt flag */
DMA_Reset(sdio_obj.dma.handle_rx);
DMA_InitStructure.channel = sdio_config.dma_rx.channel;
DMA_InitStructure.dir = DMA_DIR_PERIPHERALTOMEMORY;
DMA_InitStructure.bufferSize = BufferSize;
DMA_InitStructure.memoryBaseAddr = (uint32_t)dst;
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WORD;
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
DMA_InitStructure.memoryBurst = DMA_MEMORYBURST_INC4;
DMA_InitStructure.peripheralBaseAddr = (uint32_t)src;
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WORD;
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
DMA_InitStructure.peripheralBurst = DMA_PERIPHERALBURST_INC4;
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
DMA_InitStructure.fifoMode = DMA_FIFOMODE_ENABLE;
DMA_InitStructure.fifoThreshold = DMA_FIFOTHRESHOLD_FULL;
DMA_Config(sdio_obj.dma.handle_rx, &DMA_InitStructure);
DMA_ConfigFlowController(sdio_obj.dma.handle_rx, DMA_FLOWCTRL_PERIPHERAL);
DMA_Enable(sdio_obj.dma.handle_rx);
#endif
}
/**
* @brief This function get apm32 sdio clock.
* @param hw_sdio: apm32_sdio
* @retval PCLK2Freq
*/
static rt_uint32_t apm32_sdio_clock_get(struct apm32_sdio *hw_sdio)
{
return RCM_ReadHCLKFreq();
}
static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
{
SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
return RT_EOK;
}
static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
{
SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
return RT_EOK;
}
void SDIO_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* Process All SDIO Interrupt Sources */
rthw_sdio_irq_process(host);
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_sdio_init(void)
{
struct apm32_sdio_des sdio_des;
struct apm32_sdio_config hsd;
hsd.Instance = SDCARD_INSTANCE;
/* enable DMA clock */
#if defined (SOC_SERIES_APM32F1)
SET_BIT(RCM->AHBCLKEN, sdio_config.dma_rx.dma_rcm);
#elif defined (SOC_SERIES_APM32F4)
SET_BIT(RCM->AHB1CLKEN, sdio_config.dma_rx.dma_rcm);
#endif
NVIC_EnableIRQRequest(SDIO_IRQn, 2, 0);
/* apm32 sdio gpio init and enable clock */
extern void apm32_msp_sdio_init(void *Instance);
apm32_msp_sdio_init((void *)(hsd.Instance));
sdio_des.clk_get = apm32_sdio_clock_get;
sdio_des.hw_sdio = (struct apm32_sdio *)SDCARD_INSTANCE;
sdio_des.rxconfig = DMA_RxConfig;
sdio_des.txconfig = DMA_TxConfig;
host = sdio_host_create(&sdio_des);
if (host == RT_NULL)
{
LOG_E("host create fail");
return -1;
}
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
void apm32_mmcsd_change(void)
{
mmcsd_change(host);
}
#endif

228
bsp/apm32/libraries/Drivers/drv_sdio.h Normal file
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@ -0,0 +1,228 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-14 luobeihai first version
*/
#ifndef _DRV_SDIO_H
#define _DRV_SDIO_H
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <string.h>
#include <drivers/mmcsd_core.h>
#include <drivers/sdio.h>
#include "drv_common.h"
#include "board.h"
#define SDCARD_INSTANCE_TYPE SDIO_T
#define SDCARD_INSTANCE SDIO
#define SDIO_BUFF_SIZE 4096
#define SDIO_ALIGN_LEN 32
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (1000000)
#endif
#ifndef SDIO_BASE_ADDRESS
#define SDIO_BASE_ADDRESS (0x40012800U)
#endif
#ifndef SDIO_CLOCK_FREQ
#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
#endif
#ifndef SDIO_BUFF_SIZE
#define SDIO_BUFF_SIZE (4096)
#endif
#ifndef SDIO_ALIGN_LEN
#define SDIO_ALIGN_LEN (32)
#endif
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (24 * 1000 * 1000)
#endif
#define HW_SDIO_IT_CCRCFAIL (0x01U << 0)
#define HW_SDIO_IT_DCRCFAIL (0x01U << 1)
#define HW_SDIO_IT_CTIMEOUT (0x01U << 2)
#define HW_SDIO_IT_DTIMEOUT (0x01U << 3)
#define HW_SDIO_IT_TXUNDERR (0x01U << 4)
#define HW_SDIO_IT_RXOVERR (0x01U << 5)
#define HW_SDIO_IT_CMDREND (0x01U << 6)
#define HW_SDIO_IT_CMDSENT (0x01U << 7)
#define HW_SDIO_IT_DATAEND (0x01U << 8)
#define HW_SDIO_IT_STBITERR (0x01U << 9)
#define HW_SDIO_IT_DBCKEND (0x01U << 10)
#define HW_SDIO_IT_CMDACT (0x01U << 11)
#define HW_SDIO_IT_TXACT (0x01U << 12)
#define HW_SDIO_IT_RXACT (0x01U << 13)
#define HW_SDIO_IT_TXFIFOHE (0x01U << 14)
#define HW_SDIO_IT_RXFIFOHF (0x01U << 15)
#define HW_SDIO_IT_TXFIFOF (0x01U << 16)
#define HW_SDIO_IT_RXFIFOF (0x01U << 17)
#define HW_SDIO_IT_TXFIFOE (0x01U << 18)
#define HW_SDIO_IT_RXFIFOE (0x01U << 19)
#define HW_SDIO_IT_TXDAVL (0x01U << 20)
#define HW_SDIO_IT_RXDAVL (0x01U << 21)
#define HW_SDIO_IT_SDIOIT (0x01U << 22)
#define HW_SDIO_ERRORS \
(HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR)
#define HW_SDIO_POWER_OFF (0x00U)
#define HW_SDIO_POWER_UP (0x02U)
#define HW_SDIO_POWER_ON (0x03U)
#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
#define HW_SDIO_CLK_ENABLE (0x01U << 8)
#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
#define HW_SDIO_CPSM_ENABLE (0x01U << 10)
#define HW_SDIO_WAIT_END (0x01U << 9)
#define HW_SDIO_WAIT_INT (0x01U << 8)
#define HW_SDIO_RESPONSE_NO (0x00U << 6)
#define HW_SDIO_RESPONSE_SHORT (0x01U << 6)
#define HW_SDIO_RESPONSE_LONG (0x03U << 6)
#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
#define HW_SDIO_IO_ENABLE (0x01U << 11)
#define HW_SDIO_RWMOD_CK (0x01U << 10)
#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
#define HW_SDIO_DMA_ENABLE (0x01U << 3)
#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
#define HW_SDIO_TO_HOST (0x01U << 1)
#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
#define HW_SDIO_DATATIMEOUT (0xF0000000U)
#if defined (SOC_SERIES_APM32F1)
#define SDIO_BUS_CONFIG \
{ \
.Instance = SDIO, \
.dma_rx.dma_rcm = RCM_AHB_PERIPH_DMA2, \
.dma_tx.dma_rcm = RCM_AHB_PERIPH_DMA2, \
.dma_rx.Instance = DMA2_Channel4, \
.dma_rx.dma_irq = DMA2_Channel4_5_IRQn, \
.dma_tx.Instance = DMA2_Channel4, \
.dma_tx.dma_irq = DMA2_Channel4_5_IRQn, \
}
#elif defined (SOC_SERIES_APM32F4)
#define SDIO_BUS_CONFIG \
{ \
.Instance = SDIO, \
.dma_rx.dma_rcm = RCM_AHB1_PERIPH_DMA2, \
.dma_tx.dma_rcm = RCM_AHB1_PERIPH_DMA2, \
.dma_rx.Instance = DMA2_Stream3, \
.dma_rx.channel = DMA_CHANNEL_4, \
.dma_rx.dma_irq = DMA2_STR3_IRQn, \
.dma_tx.Instance = DMA2_Stream6, \
.dma_tx.channel = DMA_CHANNEL_4, \
.dma_tx.dma_irq = DMA2_STR6_IRQn, \
}
#endif /* SOC_SERIES_APM32F1 */
#if defined (SOC_SERIES_APM32F1)
#define DMA_INSTANCE_TYPE DMA_Channel_T
#elif defined (SOC_SERIES_APM32F4)
#define DMA_INSTANCE_TYPE DMA_Stream_T
#endif
struct apm32_sdio
{
volatile rt_uint32_t power;
volatile rt_uint32_t clkcr;
volatile rt_uint32_t arg;
volatile rt_uint32_t cmd;
volatile rt_uint32_t respcmd;
volatile rt_uint32_t resp1;
volatile rt_uint32_t resp2;
volatile rt_uint32_t resp3;
volatile rt_uint32_t resp4;
volatile rt_uint32_t dtimer;
volatile rt_uint32_t dlen;
volatile rt_uint32_t dctrl;
volatile rt_uint32_t dcount;
volatile rt_uint32_t sta;
volatile rt_uint32_t icr;
volatile rt_uint32_t mask;
volatile rt_uint32_t reserved0[2];
volatile rt_uint32_t fifocnt;
volatile rt_uint32_t reserved1[13];
volatile rt_uint32_t fifo;
};
typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_uint32_t (*sdio_clk_get)(struct apm32_sdio *hw_sdio);
struct dma_config {
DMA_INSTANCE_TYPE *Instance;
#if defined (SOC_SERIES_APM32F4)
DMA_CHANNEL_T channel;
#endif
rt_uint32_t dma_rcm;
IRQn_Type dma_irq;
};
struct apm32_sdio_des
{
struct apm32_sdio *hw_sdio;
dma_txconfig txconfig;
dma_rxconfig rxconfig;
sdio_clk_get clk_get;
};
struct apm32_sdio_config
{
SDCARD_INSTANCE_TYPE *Instance;
struct dma_config dma_rx, dma_tx;
};
/* apm32 sdio dirver class */
struct apm32_sdio_class
{
struct apm32_sdio_des *des;
const struct apm32_sdio_config *cfg;
struct rt_mmcsd_host host;
struct
{
DMA_INSTANCE_TYPE *handle_rx;
DMA_INSTANCE_TYPE *handle_tx;
} dma;
};
extern void apm32_mmcsd_change(void);
#endif

2
bsp/apm32/libraries/Drivers/drv_soft_i2c.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/apm32/libraries/Drivers/drv_spi.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -204,7 +204,7 @@ static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_
return RT_EOK;
}
static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
static rt_ssize_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);

2
bsp/apm32/libraries/Drivers/drv_spi.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_usart.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_usart.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/apm32/libraries/Drivers/drv_wdt.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*