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[bsp][nxp][rsoc] Fix compilation issues with bsp of nxp/lxp series

This commit is contained in:
hydevcode 2024-09-30 08:47:39 +08:00 committed by GitHub
parent e7e44ec7e8
commit 66d54ea8c0
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GPG Key ID: B5690EEEBB952194
17 changed files with 1336 additions and 1234 deletions
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4
.github/workflows/bsp_buildings.yml vendored
View File

@ -209,8 +209,8 @@ jobs:
- "nxp/lpc/lpc1114"
- "nxp/lpc/lpc2148"
- "nxp/lpc/lpc2478"
# - "nxp/lpc/lpc5410x"
# - "nxp/lpc/lpc54114-lite"
- "nxp/lpc/lpc5410x"
- "nxp/lpc/lpc54114-lite"
- "nxp/lpc/lpc176x"
#- "nxp/lpc/lpc43xx/M4"
- "nxp/imx/imx6sx/cortex-a9"

172
bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c
View File

@ -1,23 +1,9 @@
//*****************************************************************************
//
// Startup code for use with GNU tools.
//
//*****************************************************************************
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
/* Startup code for use with GNU tools.*/
/* Forward declaration of the default fault handlers.*/
static void Reset_Handler(void);
static void Default_Handler(void);
//*****************************************************************************
//
// External declaration for the interrupt handler used by the application.
//
//*****************************************************************************
/* External declaration for the interrupt handler used by the application.*/
void NMI_Handler(void) __attribute__((weak, alias("Default_Handler")));
void HardFault_Handler(void) __attribute__((weak, alias("Default_Handler")));
void MemManage_Handler(void) __attribute__((weak, alias("Default_Handler")));
@ -59,63 +45,51 @@ void ADC_SEQA_IRQHandler(void) __attribute__((weak, alias("Default_Handler"
void ADC_SEQB_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void ADC_THCMP_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void RTC_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void MAILBOX_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void GINT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT4_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT5_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT6_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT7_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void RIT_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved42_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved44_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
/* The entry point for the application.*/
extern int main(void);
//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
/* Reserve space for the system stack.*/
static unsigned long pulStack[512];
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
/* The vector table. Note that the proper constructs must be placed on this to*/
/* ensure that it ends up at physical address 0x0000.0000.*/
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
// The initial stack pointer
Reset_Handler, // Reset Handler
NMI_Handler, // NMI Handler
HardFault_Handler, // Hard Fault Handler
MemManage_Handler, // MPU Fault Handler
BusFault_Handler, // Bus Fault Handler
UsageFault_Handler, // Usage Fault Handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall Handler
DebugMon_Handler, // Debug Monitor Handler
0, // Reserved
PendSV_Handler, // PendSV Handler
SysTick_Handler, // SysTick Handler
/* The initial stack pointer*/
Reset_Handler, /* Reset Handler*/
NMI_Handler, /* NMI Handler*/
HardFault_Handler, /* Hard Fault Handler*/
MemManage_Handler, /* MPU Fault Handler*/
BusFault_Handler, /* Bus Fault Handler*/
UsageFault_Handler, /* Usage Fault Handler*/
0, /* Reserved*/
0, /* Reserved*/
0, /* Reserved*/
0, /* Reserved*/
SVC_Handler, /* SVCall Handler*/
DebugMon_Handler, /* Debug Monitor Handler*/
0, /* Reserved*/
PendSV_Handler, /* PendSV Handler*/
SysTick_Handler, /* SysTick Handler*/
// External Interrupts
/* External Interrupts*/
WDT_IRQHandler,
BOD_IRQHandler,
Reserved_IRQHandler,
@ -162,37 +136,30 @@ void (* const g_pfnVectors[])(void) =
Reserved43_IRQHandler,
Reserved44_IRQHandler,
};
//**RIT_IRQHandler ***************************************************************************
// Reserved41_IRQHandler
// TReserved42_IRQHandler he following are constructs created by the linker, indicating where the
// tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the
// fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.
//
//*****************************************************************************
/* RIT_IRQHandler */
/* Reserved41_IRQHandler*/
/* TReserved42_IRQHandler he following are constructs created by the linker, indicating where the*/
/* tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the*/
/* fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.*/
extern unsigned long _etext;
extern unsigned long _data;
extern unsigned long _edata;
extern unsigned long _bss;
extern unsigned long _ebss;
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
/* This is the code that gets called when the processor first starts execution*/
/* following a reset event. Only the absolutely necessary set is performed,*/
/* after which the application supplied entry() routine is called. Any fancy*/
/* actions (such as making decisions based on the reset cause register, and*/
/* resetting the bits in that register) are left solely in the hands of the*/
/* application.*/
static void Reset_Handler(void)
{
unsigned long *pulSrc, *pulDest;
//
// Copy the data segment initializers from flash to SRAM.
//
/* Copy the data segment initializers from flash to SRAM.*/
pulSrc = &_etext;
/* cppcheck-suppress comparePointers */
for(pulDest = &_data; pulDest < &_edata; )
{
*pulDest++ = *pulSrc++;
@ -200,41 +167,39 @@ static void Reset_Handler(void)
#if !defined (__USE_LPCOPEN)
// LPCOpen init code deals with FP and VTOR initialisation
/* LPCOpen init code deals with FP and VTOR initialisation*/
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// CPACR is located at address 0xE000ED88
/* CPACR is located at address 0xE000ED88*/
asm("LDR.W R0, =0xE000ED88");
// Read CPACR
/* Read CPACR*/
asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors
/* Set bits 20-23 to enable CP10 and CP11 coprocessors*/
asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR
/* Write back the modified value to the CPACR*/
asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
#endif /* (__VFP_FP__) && !(__SOFTFP__)*/
/* Check to see if we are running the code from a non-zero*/
/* address (eg RAM, external flash), in which case we need*/
/* to modify the VTOR register to tell the CPU that the*/
/* vector table is located at a non-0x0 address.*/
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
/* Note that we do not use the CMSIS register access mechanism,*/
/* as there is no guarantee that the project has been configured*/
/* to use CMSIS.*/
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000)
{
/* CMSIS : SCB->VTOR = <address of vector table>*/
*pSCB_VTOR = (unsigned int) g_pfnVectors;
}
#endif
//
// Zero fill the bss segment.
//
/* Zero fill the bss segment.*/
__asm(" ldr r0, =_bss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
@ -245,27 +210,20 @@ static void Reset_Handler(void)
" strlt r2, [r0], #4\n"
" blt zero_loop");
// call system init.
/* call system init.*/
extern void SystemInit(void);
SystemInit();
//
// Call the application's entry point.
//
/* Call the application's entry point.*/
main();
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
/* This is the code that gets called when the processor receives an unexpected*/
/* interrupt. This simply enters an infinite loop, preserving the system state*/
/* for examination by a debugger.*/
static void Default_Handler(void)
{
//
// Go into an infinite loop.
//
/* Go into an infinite loop.*/
while(1)
{
}

60
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c
View File

@ -49,7 +49,7 @@ typedef struct {
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
;
// **********************************************************
/* ********************************************************** */
uint32_t i2cmon_get_mem_size(void)
{
return sizeof(I2CMON_DATACONTEXT_T);
@ -61,7 +61,8 @@ ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit)
uint32_t reg;
/* Verify alignment is at least 4 bytes */
if (((uint32_t) mem & 0x3) != 0) {
if (((uint32_t) mem & 0x3) != 0)
{
return NULL;
}
@ -74,14 +75,16 @@ ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit)
/* Clear pending monitor statuses */
pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) {
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
{
/* Toss input data */
reg = pDrv->base->MONRXDAT;
}
/* Enable I2C monitor interface */
reg = pDrv->base->CFG | I2C_CFG_MONEN;
if (pInit->stretch != 0) {
if (pInit->stretch != 0)
{
reg |= I2C_CFG_MONCLKSTR;
}
pDrv->base->CFG = reg;
@ -93,10 +96,12 @@ void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, voi
{
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB) {
if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB)
{
pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB;
}
else if (cbIndex == ROM_I2CMON_DMASETUP_CB) {
else if (cbIndex == ROM_I2CMON_DMASETUP_CB)
{
pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB;
}
}
@ -106,12 +111,14 @@ ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
/* I2C master controller should be pending and idle */
if (pCap == NULL) {
if (pCap == NULL)
{
return ERR_I2C_PARAM;
}
/* Verify receive buffer alignment */
if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0)) {
if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0))
{
pCap->status = ERR_I2C_PARAM;
return ERR_I2C_PARAM;
}
@ -121,17 +128,21 @@ ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap
pDrv->pendingStatus = LPC_OK;
pCap->status = ERR_I2C_BUSY;
if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0) {
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) {
if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0)
{
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
{
/* Toss input data */
volatile uint32_t reg = pDrv->base->MONRXDAT;
(void)reg;
}
}
/* Clear controller state */
pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB)) {
if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB))
{
pDrv->pDmaSetupCB(pHandle, pCap);
/* Enable supported monitor interrupts */
@ -145,8 +156,10 @@ ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap
}
/* Is transfer blocking? */
if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0) {
while (pCap->status == ERR_I2C_BUSY) {
if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0)
{
while (pCap->status == ERR_I2C_BUSY)
{
i2cmon_transfer_handler(pHandle);
}
}
@ -154,8 +167,8 @@ ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap
return pCap->status;
}
// Otime = "optimize for speed of code execution"
// ...add this pragma 1 line above the interrupt service routine function.
/* Otime = "optimize for speed of code execution"*/
/* ...add this pragma 1 line above the interrupt service routine function.*/
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
{
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
@ -164,7 +177,8 @@ void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
uint32_t status = pDrv->base->STAT;
if (status & I2C_STAT_MONOV) {
if (status & I2C_STAT_MONOV)
{
/* Monitor data overflow */
data = pDrv->base->MONRXDAT;
pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
@ -172,12 +186,14 @@ void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
/* Clear Status Flags */
pDrv->base->STAT = I2C_STAT_MONOV;
}
else if (status & I2C_STAT_MONRDY) {
else if (status & I2C_STAT_MONRDY)
{
/* Monitor ready */
data = pDrv->base->MONRXDAT;
/* Enough room to place this data? */
if (pCap->capStartBuffSz >= pCap->startBuffSz) {
if (pCap->capStartBuffSz >= pCap->startBuffSz)
{
/* Data overflow */
pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
}
@ -190,11 +206,13 @@ void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
}
/* Capture complete? */
if ((status & I2C_INTSTAT_MONIDLE) != 0) {
if ((status & I2C_INTSTAT_MONIDLE) != 0)
{
pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV |
I2C_INTENCLR_MONIDLE);
pCap->status = pDrv->pendingStatus;
if (pDrv->pCapCompCB) {
if (pDrv->pCapCompCB)
{
pDrv->pCapCompCB(pHandle, pCap);
}
}
@ -205,4 +223,4 @@ uint32_t i2cmon_get_driver_version(void)
return DRVVERSION;
}
// *********************************************************
/* ********************************************************** */

220
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c
View File

@ -59,8 +59,10 @@ static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m)
static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict)
{
int32_t i, max = strict ? 16 : 5;
for (i = 16; i >= max; i--) {
if (!(val % i)) {
for (i = 16; i >= max; i--)
{
if (!(val % i))
{
return i;
}
}
@ -73,12 +75,14 @@ static ErrorCode_t _UART_Xfer(UART_DRIVER_T *pUART, void *buff, uint16_t len, ui
UART_DATA_T *xfr = &pUART->xfer[op];
/* Xfer of 0 bytes in a UART should always be successful */
if (!len) {
if (!len)
{
return LPC_OK;
}
/* Check if a Xfer is alredy in progress */
if (xfr->count > xfr->offset) {
if (xfr->count > xfr->offset)
{
return ERR_BUSY;
}
@ -86,7 +90,8 @@ static ErrorCode_t _UART_Xfer(UART_DRIVER_T *pUART, void *buff, uint16_t len, ui
xfr->count = len;
xfr->offset = 0;
xfr->state = UART_ST_BUSY;
if (!op) {
if (!op)
{
pUART->pREGS->INTENSET = UART_INT_TXRDY;
}
else {
@ -101,11 +106,13 @@ static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev)
{
uint32_t err = n - (n / d) * d;
uint32_t herr = ((n / d) + 1) * d - n;
if (herr < err) {
if (herr < err)
{
err = herr;
}
if (*prev <= err) {
if (*prev <= err)
{
return 0;
}
*prev = err;
@ -118,31 +125,37 @@ static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub)
int32_t i = 0;
uint32_t perr = ~0UL;
if (!ub->div) {
if (!ub->div)
{
i = ub->ovr ? ub->ovr : 16;
}
for (; i > 4; i--) {
for (; i > 4; i--)
{
int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
/* Continue when no improvement seen in err value */
if (!tmp) {
if (!tmp)
{
continue;
}
ub->div = tmp - 1;
if (ub->ovr == i) {
if (ub->ovr == i)
{
break;
}
ub->ovr = i;
}
if (!ub->ovr) {
if (!ub->ovr)
{
return ERR_UART_BAUDRATE;
}
ub->div += ub->clk / (ub->baud * ub->ovr);
if (!ub->div) {
if (!ub->div)
{
return ERR_UART_BAUDRATE;
}
@ -156,7 +169,8 @@ static void _UART_CalcMul(UART_BAUD_T *ub)
uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
/* If clock is UART's base clock calculate only the divider */
for (m = 0; m < 256; m++) {
for (m = 0; m < 256; m++)
{
uint32_t ov = ovr, x, v, tmp;
/* Get clock and calculate error */
@ -166,7 +180,8 @@ static void _UART_CalcMul(UART_BAUD_T *ub)
/* Update if new error is better than previous best */
if (!tmp || (ovr && (v % ovr)) ||
(!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) {
(!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0)))
{
continue;
}
@ -182,7 +197,8 @@ static void _UART_InvokeCB(UART_DRIVER_T *pUART, UART_EVENT_T event, void *arg)
{
void (*cbfn)(UART_HANDLE_T, UART_EVENT_T, void *);
cbfn = pUART->cbTable[(uint32_t) event >> 1];
if (cbfn != NULL) {
if (cbfn != NULL)
{
cbfn((UART_HANDLE_T) pUART, event, arg);
}
}
@ -196,9 +212,12 @@ static void _UART_HandleTxRx(UART_HANDLE_T hUART, UART_EVENT_T event, void *arg)
uint8_t *buf8 = dat->buf;
/* Transmit data */
if (event == UART_TX_DATA) {
while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_TXRDY)) {
if (dat->dwidth) {
if (event == UART_TX_DATA)
{
while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_TXRDY))
{
if (dat->dwidth)
{
pUART->pREGS->TXDAT = *buf16++;
}
else {
@ -210,8 +229,10 @@ static void _UART_HandleTxRx(UART_HANDLE_T hUART, UART_EVENT_T event, void *arg)
}
/* Receive data */
while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_RXRDY)) {
if (dat->dwidth) {
while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_RXRDY))
{
if (dat->dwidth)
{
*buf16++ = pUART->pREGS->RXDAT & 0x1FF;
}
else {
@ -228,29 +249,34 @@ static int32_t _UART_HandleXfer(UART_DRIVER_T *pUART, uint8_t op)
UART_DATA_T *xfr = &pUART->xfer[op];
/* See if the transfer is already complete */
if (xfr->offset >= xfr->count) {
if (xfr->offset >= xfr->count)
{
return 2;
}
/* Fill the buffer data structure */
dat.count = xfr->count - xfr->offset;
dat.dwidth = ((pUART->pREGS->CFG >> 2) & 3) > 1;
if (dat.dwidth) {
if (dat.dwidth)
{
dat.buf = &((uint16_t *) xfr->buf)[xfr->offset];
}
else {
dat.buf = &((uint8_t *) xfr->buf)[xfr->offset];
}
if (!xfr->offset && xfr->count) {
if (!xfr->offset && xfr->count)
{
_UART_InvokeCB(pUART, UART_TX_START, xfr);
}
pUART->cbTable[UART_CB_DATA]((UART_HANDLE_T) pUART, (UART_EVENT_T) (UART_TX_DATA + op), &dat);
xfr->offset = (xfr->count - dat.count);
if (xfr->offset >= xfr->count) {
if (!op) {
if (xfr->offset >= xfr->count)
{
if (!op)
{
pUART->pREGS->INTENCLR = UART_INT_TXRDY;
}
else {
@ -258,7 +284,8 @@ static int32_t _UART_HandleXfer(UART_DRIVER_T *pUART, uint8_t op)
}
_UART_InvokeCB(pUART, (UART_EVENT_T) (UART_TX_DONE + op), xfr);
if (xfr->state == UART_ST_BUSY) {
if (xfr->state == UART_ST_BUSY)
{
xfr->state = UART_ST_DONE;
}
return 1;
@ -273,7 +300,8 @@ static void _UART_StopRx(UART_HANDLE_T hUART)
UART_DATA_T *rx = &pUART->xfer[1];
volatile uint16_t *idx = (volatile uint16_t *) &rx->offset;
if (*idx >= rx->count) {
if (*idx >= rx->count)
{
return;
}
@ -292,7 +320,8 @@ uint32_t UART_GetMemSize(void)
/* EXPORTED API: Calculate UART Baudrate divisors */
ErrorCode_t UART_CalculateBaud(UART_BAUD_T *ub)
{
if (!ub->mul) {
if (!ub->mul)
{
_UART_CalcMul(ub);
}
@ -305,7 +334,8 @@ UART_HANDLE_T UART_Init(void *mem, uint32_t base_addr, void *args)
UART_DRIVER_T *pUART;
/* Check if the memory is word aligned */
if ((uint32_t) mem & 0x3) {
if ((uint32_t) mem & 0x3)
{
return NULL;
}
@ -329,16 +359,19 @@ ErrorCode_t UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *cfg)
UART_REGS_T *pREGS = pUART->pREGS;
if (((cfg->cfg & UART_PAR_MASK) == (1 << 4)) ||
( (cfg->cfg & UART_DATA_MASK) == (3 << 2)) ) {
( (cfg->cfg & UART_DATA_MASK) == (3 << 2)) )
{
return ERR_UART_PARAM;
}
/* Enable parity error when parity is enabled */
if ((cfg->cfg & UART_PAR_MASK) >> 4) {
if ((cfg->cfg & UART_PAR_MASK) >> 4)
{
pREGS->INTENSET = UART_INT_PARERR;
}
if (((int32_t) cfg->div <= 0) || ((int32_t) cfg->ovr <= 0)) {
if (((int32_t) cfg->div <= 0) || ((int32_t) cfg->ovr <= 0))
{
return ERR_UART_PARAM;
}
@ -347,18 +380,21 @@ ErrorCode_t UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *cfg)
pREGS->CFG = UART_CFG_ENABLE | (cfg->cfg & ~UART_CFG_RES);
/* Enabled RX of BREAK event */
if (cfg->cfg & UART_CFG_BRKRX) {
if (cfg->cfg & UART_CFG_BRKRX)
{
pREGS->INTENSET = UART_INT_BREAK;
}
/* Enable CTS interrupt if requested */
if (cfg->cfg & UART_CFG_CTSEV) {
if (cfg->cfg & UART_CFG_CTSEV)
{
pREGS->INTENSET = UART_INT_CTS;
}
#ifdef UART_IDLE_FIX
/* REMOVE: if/else block after H/W idle is fixed */
if (cfg->res > 224) {
if (cfg->res > 224)
{
pUART->dly = 3072 * (cfg->res - 224);
}
else {
@ -380,25 +416,32 @@ void UART_SetControl(UART_HANDLE_T hUART, uint32_t cfg)
dis = ((cfg >> 16) & ~(cfg & 0xFFFF)) << 1;
/* See if it is RX Stop request */
if (cfg & UART_RX_STOP) {
if (cfg & UART_RX_STOP)
{
_UART_StopRx(hUART);
}
/* See if any IDLEs are enabled */
if (cfg & (UART_IDLE_MASK << 16)) {
if (cfg & (UART_IDLE_MASK << 16))
{
pREGS->INTENSET = (en >> 1) & UART_IDLE_MASK;
pREGS->INTENCLR = (dis >> 1) & UART_IDLE_MASK;
}
/* See if it is a request BREAK after TX */
if (en & UART_CTL_TXDIS) {
if (en & UART_CTL_TXBRKEN) {
if (en & UART_CTL_TXDIS)
{
if (en & UART_CTL_TXBRKEN)
{
pREGS->CTL = (pREGS->CTL & ~UART_CTL_RES) | UART_CTL_TXDIS;
while (!(pREGS->STAT & UART_INT_TXDIS)) {}
while (!(pREGS->STAT & UART_INT_TXDIS))
{}
#ifdef UART_IDLE_FIX
if (1) {
if (1)
{
volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
while (dly--) {}/* Provide some idling time H/W does not do this */
while (dly--)
{}/* Provide some idling time H/W does not do this */
}
#endif
}
@ -408,18 +451,22 @@ void UART_SetControl(UART_HANDLE_T hUART, uint32_t cfg)
}
/* See if we are releasing break and resume TX operation */
if ((dis & UART_CTL_TXDIS) && (dis & UART_CTL_TXBRKEN)) {
if ((dis & UART_CTL_TXDIS) && (dis & UART_CTL_TXBRKEN))
{
pREGS->CTL = pREGS->CTL & ~(UART_CTL_RES | UART_CTL_TXBRKEN);
#ifdef UART_IDLE_FIX
if (1) {
if (1)
{
volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
while (dly--) {} /* Provide some idling time H/W does not do this */
while (dly--)
{} /* Provide some idling time H/W does not do this */
}
#endif
}
/* Check for autobaud and enable autobaud err interrupt */
if (en & UART_CTL_AUTOBAUD) {
if (en & UART_CTL_AUTOBAUD)
{
pREGS->INTENSET = UART_INT_ABAUDERR;
}
@ -431,7 +478,8 @@ ErrorCode_t UART_RegisterCB(UART_HANDLE_T hUART,
UART_CBINDEX_T idx,
void (*cb_func)(UART_HANDLE_T, UART_EVENT_T, void *))
{
if (idx < UART_CB_RESERVED) {
if (idx < UART_CB_RESERVED)
{
((UART_DRIVER_T *) hUART)->cbTable[idx] = cb_func;
}
else {
@ -439,7 +487,8 @@ ErrorCode_t UART_RegisterCB(UART_HANDLE_T hUART,
}
/* Restore internal data handlers when external ones are un-registered */
if ((idx == UART_CB_DATA) && (cb_func == NULL)) {
if ((idx == UART_CB_DATA) && (cb_func == NULL))
{
((UART_DRIVER_T *) hUART)->cbTable[idx] = _UART_HandleTxRx;
}
@ -452,85 +501,105 @@ void UART_Handler(UART_HANDLE_T hUART)
UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
uint32_t flags = pUART->pREGS->INTENSET & pUART->pREGS->INTSTAT;
if (flags & UART_INT_TXRDY) {
if (flags & UART_INT_TXRDY)
{
_UART_HandleXfer(pUART, 0);
}
if (flags & UART_INT_FRMERR) {
if (flags & UART_INT_FRMERR)
{
pUART->pREGS->STAT = UART_INT_FRMERR;
if (pUART->xfer[1].state == UART_ST_BUSY) {
if (pUART->xfer[1].state == UART_ST_BUSY)
{
pUART->xfer[1].state = UART_ST_ERRFRM;
}
_UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_FRAME);
}
if (flags & UART_INT_PARERR) {
if (flags & UART_INT_PARERR)
{
pUART->pREGS->STAT = UART_INT_PARERR;
if (pUART->xfer[1].state == UART_ST_BUSY) {
if (pUART->xfer[1].state == UART_ST_BUSY)
{
pUART->xfer[1].state = UART_ST_ERRPAR;
}
_UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_PARITY);
}
if (flags & UART_INT_ABAUDERR) {
if (flags & UART_INT_ABAUDERR)
{
pUART->pREGS->STAT = UART_INT_ABAUDERR;
if (pUART->xfer[1].state == UART_ST_BUSY) {
if (pUART->xfer[1].state == UART_ST_BUSY)
{
pUART->xfer[1].state = UART_ST_ERR;
}
_UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_AUTOBAUD);
}
if (flags & UART_INT_RXNOISE) {
if (flags & UART_INT_RXNOISE)
{
pUART->pREGS->STAT = UART_INT_RXNOISE;
if (pUART->xfer[1].state == UART_ST_BUSY) {
if (pUART->xfer[1].state == UART_ST_BUSY)
{
pUART->xfer[1].state = UART_ST_ERRNOISE;
}
_UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_RXNOISE);
}
if (flags & UART_INT_OVR) {
if (flags & UART_INT_OVR)
{
pUART->pREGS->STAT = UART_INT_OVR;
if (pUART->xfer[1].state == UART_ST_BUSY) {
if (pUART->xfer[1].state == UART_ST_BUSY)
{
pUART->xfer[1].state = UART_ST_ERROVR;
}
_UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_OVERRUN);
}
if (flags & UART_INT_RXRDY) {
if (flags & UART_INT_RXRDY)
{
_UART_HandleXfer(pUART, 1);
#ifdef UART_IDLE_FIX
if (1) {
if (1)
{
volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
while ((pUART->pREGS->STAT & UART_STAT_RXIDLE) && dly--) {}
while ((pUART->pREGS->STAT & UART_STAT_RXIDLE) && dly--)
{}
}
#else
while (pUART->pREGS->STAT & UART_STAT_RXIDLE) {}
while (pUART->pREGS->STAT & UART_STAT_RXIDLE)
{}
#endif
_UART_InvokeCB(pUART, (UART_EVENT_T) (UART_RX_INPROG + ((pUART->pREGS->STAT >> 1) & 1)), &pUART->xfer[1]);
}
if (flags & UART_INT_TXIDLE) {
if (flags & UART_INT_TXIDLE)
{
_UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXIDLE);
}
if (flags & UART_INT_TXDIS) {
if (flags & UART_INT_TXDIS)
{
pUART->pREGS->INTENCLR = UART_INT_TXDIS;/* Disable interrupt */
_UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXPAUSED);
}
if (flags & UART_INT_CTS) {
if (flags & UART_INT_CTS)
{
pUART->pREGS->STAT = UART_INT_CTS;
_UART_InvokeCB(pUART, UART_EV_EVENT,
(void *) ((pUART->pREGS->STAT & UART_STAT_CTS) ? UART_EVENT_CTSHI : UART_EVENT_CTSLO));
}
if (flags & UART_INT_BREAK) {
if (flags & UART_INT_BREAK)
{
pUART->pREGS->STAT = UART_INT_BREAK | UART_INT_FRMERR;
_UART_InvokeCB(pUART, UART_EV_EVENT,
(void *) ((pUART->pREGS->STAT & UART_STAT_BREAK) ? UART_EVENT_BREAK : UART_EVENT_NOBREAK));
}
if (flags & UART_INT_START) {
if (flags & UART_INT_START)
{
pUART->pREGS->STAT = UART_INT_START;
_UART_InvokeCB(pUART, UART_RX_START, &pUART->xfer[1]);
}
@ -552,7 +621,8 @@ ErrorCode_t UART_Rx(UART_HANDLE_T hUART, void *buff, uint16_t len)
/* EXPORTED API: Flush the TX buffer */
void UART_WaitTX(UART_HANDLE_T hUART)
{
while (!_UART_HandleXfer(hUART, 0)) {}
while (!_UART_HandleXfer(hUART, 0))
{}
}
/* EXPORTED API: Fetch the data from UART into RX buffer */
@ -560,13 +630,17 @@ void UART_WaitRX(UART_HANDLE_T hUART)
{
UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS;
/* See if the data needs to be discarded */
if (_UART_HandleXfer(hUART, 1) == 2) {
if (_UART_HandleXfer(hUART, 1) == 2)
{
volatile uint32_t dummy;
while ((pREGS->STAT & UART_INT_RXRDY) || !(pREGS->STAT & UART_STAT_RXIDLE)) {
while ((pREGS->STAT & UART_INT_RXRDY) || !(pREGS->STAT & UART_STAT_RXIDLE))
{
dummy = pREGS->RXDAT;
(void)dummy;
}
}
while (!_UART_HandleXfer(hUART, 1)) {}
while (!_UART_HandleXfer(hUART, 1))
{}
}
/* EXPORTED API: Function to Get the firmware Version */

226
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c
View File

@ -50,12 +50,12 @@
#define SYS_PLL_DIRECTI (1 << 19) /*!< PLL0 direct input enable */
#define SYS_PLL_DIRECTO (1 << 20) /*!< PLL0 direct output enable */
// #define FRAC_BITS_SELI (8) // For retaining fractions in divisions
#define PLL_SSCG0_MDEC_VAL_P (0) // MDEC is in bits 16 downto 0
#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) // NDEC is in bits 9 downto 0
#define PLL_NDEC_VAL_P (0) // NDEC is in bits 9:0
/* #define FRAC_BITS_SELI (8) // For retaining fractions in divisions*/
#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0*/
#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0*/
#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0*/
#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
#define PLL_PDEC_VAL_P (0) // PDEC is in bits 6:0
#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0*/
#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
#define PLL_MIN_CCO_FREQ_MHZ (75000000)
@ -64,20 +64,20 @@
#define PLL_MIN_IN_SSMODE (2000000)
#define PLL_MAX_IN_SSMODE (4000000)
// Middle of the range values for spread-spectrum
/* Middle of the range values for spread-spectrum*/
#define PLL_SSCG_MF_FREQ_VALUE 4
#define PLL_SSCG_MC_COMP_VALUE 2
#define PLL_SSCG_MR_DEPTH_VALUE 4
#define PLL_SSCG_DITHER_VALUE 0
// pll SYSPLLCTRL Bits
/* pll SYSPLLCTRL Bits*/
#define SYSCON_SYSPLLCTRL_SELR_P 0
#define SYSCON_SYSPLLCTRL_SELR_M (0xFUL << SYSCON_SYSPLLCTRL_SELR_P)
#define SYSCON_SYSPLLCTRL_SELI_P 4
#define SYSCON_SYSPLLCTRL_SELI_M (0x3FUL << SYSCON_SYSPLLCTRL_SELI_P)
#define SYSCON_SYSPLLCTRL_SELP_P 10
#define SYSCON_SYSPLLCTRL_SELP_M (0x1FUL << SYSCON_SYSPLLCTRL_SELP_P)
#define SYSCON_SYSPLLCTRL_BYPASS_P 15 // sys_pll150_ctrl
#define SYSCON_SYSPLLCTRL_BYPASS_P 15 /* sys_pll150_ctrl*/
#define SYSCON_SYSPLLCTRL_BYPASS (1UL << SYSCON_SYSPLLCTRL_BYPASS_P)
#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P 16
#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2 (1UL << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P)
@ -93,7 +93,7 @@
#define SYSCON_SYSPLLSTAT_LOCK_P 0
#define SYSCON_SYSPLLSTAT_LOCK (1UL << SYSCON_SYSPLLSTAT_LOCK_P)
#define PLL_CTRL_BYPASS_P 15 // sys_pll150_ctrl
#define PLL_CTRL_BYPASS_P 15 /* sys_pll150_ctrl*/
#define PLL_CTRL_BYPASS_FBDIV2_P 16
#define PLL_CTRL_UPLIMOFF_P 17
#define PLL_CTRL_BANDSEL_SSCGREG_N_P 18
@ -107,14 +107,14 @@
#define PLL_CTRL_BANDSEL_SSCGREG_N (1 << PLL_CTRL_BANDSEL_SSCGREG_N_P)
#define PLL_CTRL_BYPASS_FBDIV2 (1 << PLL_CTRL_BYPASS_FBDIV2_P)
// SSCG control[0]
// #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0
/* SSCG control[0]*/
/* #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0*/
#define PLL_SSCG0_MREQ_P 17
#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18
#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)
#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P)
// SSCG control[1]
/* SSCG control[1]*/
#define PLL_SSCG1_MD_REQ_P 19
#define PLL_SSCG1_MOD_PD_SSCGCLK_N_P 28
#define PLL_SSCG1_DITHER_P 29
@ -122,24 +122,24 @@
#define PLL_SSCG1_DITHER (1 << PLL_SSCG1_DITHER_P)
#define PLL_SSCG1_MD_REQ (1 << PLL_SSCG1_MD_REQ_P)
// PLL NDEC reg
/* PLL NDEC reg*/
#define PLL_NDEC_VAL_SET(value) (((unsigned long) (value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
#define PLL_NDEC_NREQ_P 10
#define PLL_NDEC_NREQ (1 << PLL_NDEC_NREQ_P)
// PLL PDEC reg
/* PLL PDEC reg*/
#define PLL_PDEC_VAL_SET(value) (((unsigned long) (value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
#define PLL_PDEC_PREQ_P 7
#define PLL_PDEC_PREQ (1 << PLL_PDEC_PREQ_P)
// SSCG control[0]
/* SSCG control[0]*/
#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long) (value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M)
#define PLL_SSCG0_MREQ_P 17
#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P)
#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18
#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)
// SSCG control[1]
/* SSCG control[1]*/
#define PLL_SSCG1_MD_FRACT_P 0
#define PLL_SSCG1_MD_INT_P 11
#define PLL_SSCG1_MF_P 20
@ -156,14 +156,17 @@
PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M)
#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long) (value) << \
PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M)
// #define PLL_SSCG1_MF_SET(value) (((unsigned long) (value) << \
// // PLL_SSCG1_MF_P) & PLL_SSCG1_MF_M)
// #define PLL_SSCG1_MC_SET(value) (((unsigned long) (value) << \
// // PLL_SSCG1_MC_P) & PLL_SSCG1_MC_M)
// #define PLL_SSCG1_MR_SET(value) (((unsigned long) (value) << \
// // PLL_SSCG1_MR_P) & PLL_SSCG1_MR_M)
/*
#define PLL_SSCG1_MF_SET(value) (((unsigned long) (value) << \
PLL_SSCG1_MF_P) & PLL_SSCG1_MF_M)
#define PLL_SSCG1_MC_SET(value) (((unsigned long) (value) << \
PLL_SSCG1_MC_P) & PLL_SSCG1_MC_M)
#define PLL_SSCG1_MR_SET(value) (((unsigned long) (value) << \
PLL_SSCG1_MR_P) & PLL_SSCG1_MR_M)
*/
/* Middle of the range values for spread-spectrum*/
// Middle of the range values for spread-spectrum
#define PLL0_SSCG_MF_FREQ_VALUE 4
#define PLL0_SSCG_MC_COMP_VALUE 2
#define PLL0_SSCG_MR_DEPTH_VALUE 4
@ -189,7 +192,8 @@ static uint32_t pllEncodeN(uint32_t N)
uint32_t x, i;
/* Find NDec */
switch (N) {
switch (N)
{
case 0:
x = 0xFFF;
break;
@ -204,7 +208,8 @@ static uint32_t pllEncodeN(uint32_t N)
default:
x = 0x080;
for (i = N; i <= NVALMAX; i++) {
for (i = N; i <= NVALMAX; i++)
{
x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
break;
@ -219,7 +224,8 @@ static uint32_t pllDecodeN(uint32_t NDEC)
uint32_t n, x, i;
/* Find NDec */
switch (NDEC) {
switch (NDEC)
{
case 0xFFF:
n = 0;
break;
@ -235,9 +241,11 @@ static uint32_t pllDecodeN(uint32_t NDEC)
default:
x = 0x080;
n = 0xFFFFFFFF;
for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) {
for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--)
{
x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) {
if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
{
/* Decoded value of NDEC */
n = i;
}
@ -254,7 +262,8 @@ static uint32_t pllEncodeP(uint32_t P)
uint32_t x, i;
/* Find PDec */
switch (P) {
switch (P)
{
case 0:
x = 0xFF;
break;
@ -269,7 +278,8 @@ static uint32_t pllEncodeP(uint32_t P)
default:
x = 0x10;
for (i = P; i <= PVALMAX; i++) {
for (i = P; i <= PVALMAX; i++)
{
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
}
break;
@ -284,7 +294,8 @@ static uint32_t pllDecodeP(uint32_t PDEC)
uint32_t p, x, i;
/* Find PDec */
switch (PDEC) {
switch (PDEC)
{
case 0xFF:
p = 0;
break;
@ -300,9 +311,11 @@ static uint32_t pllDecodeP(uint32_t PDEC)
default:
x = 0x10;
p = 0xFFFFFFFF;
for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) {
for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--)
{
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) {
if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
{
/* Decoded value of PDEC */
p = i;
}
@ -319,7 +332,8 @@ static uint32_t pllEncodeM(uint32_t M)
uint32_t i, x;
/* Find MDec */
switch (M) {
switch (M)
{
case 0:
x = 0xFFFFF;
break;
@ -334,7 +348,8 @@ static uint32_t pllEncodeM(uint32_t M)
default:
x = 0x04000;
for (i = M; i <= MVALMAX; i++) {
for (i = M; i <= MVALMAX; i++)
{
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
break;
@ -349,7 +364,8 @@ static uint32_t pllDecodeM(uint32_t MDEC)
uint32_t m, i, x;
/* Find MDec */
switch (MDEC) {
switch (MDEC)
{
case 0xFFFFF:
m = 0;
break;
@ -365,9 +381,11 @@ static uint32_t pllDecodeM(uint32_t MDEC)
default:
x = 0x04000;
m = 0xFFFFFFFF;
for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) {
for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--)
{
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) {
if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
{
/* Decoded value of MDEC */
m = i;
}
@ -382,12 +400,14 @@ static uint32_t pllDecodeM(uint32_t MDEC)
static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
{
/* Bypass divider? */
if (bypassFBDIV2) {
if (bypassFBDIV2)
{
M = M / 2;
}
/* bandwidth: compute selP from Multiplier */
if (M < 60) {
if (M < 60)
{
*pSelP = (M >> 1) + 1;
}
else {
@ -395,26 +415,32 @@ static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t
}
/* bandwidth: compute selI from Multiplier */
if (M > 16384) {
if (M > 16384)
{
*pSelI = 1;
}
else if (M > 8192) {
else if (M > 8192)
{
*pSelI = 2;
}
else if (M > 2048) {
else if (M > 2048)
{
*pSelI = 4;
}
else if (M >= 501) {
else if (M >= 501)
{
*pSelI = 8;
}
else if (M >= 60) {
else if (M >= 60)
{
*pSelI = 4 * (1024 / (M + 9));
}
else {
*pSelI = (M & 0x3C) + 4;
}
if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P)) {
if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P))
{
*pSelI = (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P);
}
@ -427,10 +453,12 @@ uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
uint32_t preDiv = 1;
/* Direct input is not used? */
if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0) {
if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0)
{
/* Decode NDEC value to get (N) pre divider */
preDiv = pllDecodeN(nDecReg & 0x3FF);
if (preDiv == 0) {
if (preDiv == 0)
{
preDiv = 1;
}
}
@ -445,10 +473,12 @@ uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
uint32_t postDiv = 1;
/* Direct input is not used? */
if ((ctrlReg & SYS_PLL_DIRECTO) == 0) {
if ((ctrlReg & SYS_PLL_DIRECTO) == 0)
{
/* Decode PDEC value to get (P) post divider */
postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
if (postDiv == 0) {
if (postDiv == 0)
{
postDiv = 2;
}
}
@ -466,11 +496,13 @@ uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
mMult = pllDecodeM(mDecReg & 0x1FFFF);
/* Extra divided by 2 needed? */
if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0) {
if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0)
{
mMult = mMult >> 1;
}
if (mMult == 0) {
if (mMult == 0)
{
mMult = 1;
}
@ -481,7 +513,8 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
{
uint32_t tmp;
while (n != 0) {
while (n != 0)
{
tmp = n;
n = m % n;
m = tmp;
@ -503,7 +536,8 @@ static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_
pllPreDivider = 1; /* 1 implies pre-divider will be disabled */
pllPostDivider = 0; /* 0 implies post-divider will be disabled */
pllDirectOutput = 1;
if (useFeedbackDiv2) {
if (useFeedbackDiv2)
{
/* Using feedback divider for M, so disable bypass */
pllBypassFBDIV2 = 0;
}
@ -513,32 +547,38 @@ static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_
multFccoDiv = (2 - pllBypassFBDIV2);
/* Verify output rate parameter */
if (foutHz > PLL_MAX_CCO_FREQ_MHZ) {
if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
{
/* Maximum PLL output with post divider=1 cannot go above this frequency */
return PLL_ERROR_OUTPUT_TOO_HIGH;
}
if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1))) {
if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1)))
{
/* Minmum PLL output with maximum post divider cannot go below this frequency */
return PLL_ERROR_OUTPUT_TOO_LOW;
}
/* If using SS mode, input clock needs to be between 2MHz and 4MHz */
if (useSS) {
if (useSS)
{
/* Verify input rate parameter */
if (finHz < PLL_MIN_IN_SSMODE) {
if (finHz < PLL_MIN_IN_SSMODE)
{
/* Input clock into the PLL cannot be lower than this */
return PLL_ERROR_INPUT_TOO_LOW;
}
/* PLL input in SS mode must be under 4MHz */
pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2);
if (pllPreDivider > NVALMAX) {
if (pllPreDivider > NVALMAX)
{
return PLL_ERROR_INPUT_TOO_HIGH;
}
}
else {
/* Verify input rate parameter */
if (finHz < PLL_LOWER_IN_LIMIT) {
if (finHz < PLL_LOWER_IN_LIMIT)
{
/* Input clock into the PLL cannot be lower than this */
return PLL_ERROR_INPUT_TOO_LOW;
}
@ -548,12 +588,14 @@ static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_
will keep it inside the PLL CCO range. This may require
tweaking the post-divider for the PLL. */
fccoHz = foutHz;
while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) {
while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
{
/* CCO output is less than minimum CCO range, so the CCO output
needs to be bumped up and the post-divider is used to bring
the PLL output back down. */
pllPostDivider++;
if (pllPostDivider > PVALMAX) {
if (pllPostDivider > PVALMAX)
{
return PLL_ERROR_OUTSIDE_INTLIMIT;
}
@ -563,19 +605,23 @@ static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_
}
/* Determine if a pre-divider is needed to get the best frequency */
if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) {
if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))
{
uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
if (a > 20000) {
if (a > 20000)
{
a = (multFccoDiv * finHz) / a;
if ((a != 0) && (a < PLL_MAX_N_DIV)) {
if ((a != 0) && (a < PLL_MAX_N_DIV))
{
pllPreDivider = a;
}
}
}
/* Bypass pre-divider hardware if pre-divider is 1 */
if (pllPreDivider > 1) {
if (pllPreDivider > 1)
{
pllDirectInput = 0;
}
else {
@ -587,9 +633,11 @@ static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_
pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
/* Find optimal values for filter */
if (useSS == false) {
if (useSS == false)
{
/* Will bumping up M by 1 get us closer to the desired CCO frequency? */
if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2)) {
if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2))
{
pllMultiplier++;
}
@ -660,7 +708,8 @@ uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
{
uint32_t clkRate = 0;
switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3)) {
switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3))
{
case SYSCON_PLLCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
@ -688,7 +737,8 @@ uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup)
uint64_t workRate;
inPllRate = Chip_Clock_GetSystemPLLInClockRate();
if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_P) == 0) {
if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_P) == 0)
{
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
prediv = findPllPreDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLNDEC);
postdiv = findPllPostDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLPDEC);
@ -697,7 +747,8 @@ uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup)
inPllRate = inPllRate / prediv;
/* If using the SS, use the multiplier */
if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N) {
if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N)
{
/* MDEC used for rate */
mMult = findPllMMult(pSetup->SYSPLLCTRL, pSetup->SYSPLLSSCTRL[0]);
workRate = (uint64_t) inPllRate * (uint64_t) mMult;
@ -730,7 +781,8 @@ uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute)
PLL_SETUP_T Setup;
uint32_t rate;
if ((recompute) || (curPllRate == 0)) {
if ((recompute) || (curPllRate == 0))
{
Setup.SYSPLLCTRL = LPC_SYSCON->SYSPLLCTRL;
Setup.SYSPLLNDEC = LPC_SYSCON->SYSPLLNDEC;
Setup.SYSPLLPDEC = LPC_SYSCON->SYSPLLPDEC;
@ -748,7 +800,8 @@ uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute)
/* Enables and disables PLL bypass mode */
void Chip_Clock_SetBypassPLL(bool bypass)
{
if (bypass) {
if (bypass)
{
LPC_SYSCON->SYSPLLCTRL |= SYSCON_SYSPLLCTRL_BYPASS_P;
}
else {
@ -764,7 +817,8 @@ PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup)
PLL_ERROR_T pllError;
/* Determine input rate for the PLL */
if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0) {
if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0)
{
inRate = pControl->InputRate;
}
else {
@ -773,11 +827,13 @@ PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup)
/* PLL flag options */
pllError = Chip_Clock_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS);
if ((useSS) && (pllError == PLL_ERROR_SUCCESS)) {
if ((useSS) && (pllError == PLL_ERROR_SUCCESS))
{
/* If using SS mode, then some tweaks are made to the generated setup */
pSetup->SYSPLLSSCTRL[1] |= (uint32_t) pControl->ss_mf | (uint32_t) pControl->ss_mr |
(uint32_t) pControl->ss_mc;
if (pControl->mfDither) {
if (pControl->mfDither)
{
pSetup->SYSPLLSSCTRL[1] |= PLL_SSCG1_DITHER;
}
}
@ -803,18 +859,22 @@ PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup)
LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1] | PLL_SSCG1_MD_REQ; /* latch */
/* Flags for lock or power on */
if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) {
if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
{
Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SYS_PLL);
}
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0) {
while (Chip_Clock_IsSystemPLLLocked() == false) {}
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0)
{
while (Chip_Clock_IsSystemPLLLocked() == false)
{}
}
/* Update current programmed PLL rate var */
Chip_Clock_GetSystemPLLOutFromSetupUpdate(pSetup);
/* System voltage adjustment, occurs prior to setting main system clock */
if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0) {
if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0)
{
Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, curPllRate);
}
@ -833,7 +893,8 @@ void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq)
uint32_t directo = SYS_PLL_DIRECTO;
while (cco_freq < 75000000) {
while (cco_freq < 75000000)
{
multiply_by <<= 1; /* double value in each iteration */
pdec <<= 1; /* correspondingly double pdec to cancel effect of double msel */
cco_freq = input_freq * multiply_by;
@ -842,7 +903,8 @@ void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq)
seli = (multiply_by & 0x3c) + 4;
selp = (multiply_by >> 1) + 1;
if (pdec > 1) {
if (pdec > 1)
{
directo = 0; /* use post divider */
pdec = pdec / 2; /* Account for minus 1 encoding */
/* Translate P value */

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bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib Normal file
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2
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h
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@ -123,7 +123,7 @@ typedef struct {
/**
* @brief LPC5410x IAP_ENTRY API function type
*/
static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4])
static INLINE void iap_entry(uint32_t cmd_param[5], uint32_t status_result[4])
{
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
}

2
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h
View File

@ -78,7 +78,7 @@ extern "C" {
#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */
/* IAP_ENTRY API function type */
typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]);
typedef void (*IAP_ENTRY_T)(uint32_t[5], uint32_t[4]);
/**
* @brief Prepare sector for write operation

11
bsp/nxp/lpc/lpc5410x/applications/board.h
View File

@ -25,21 +25,10 @@
#endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
#define RT_USING_UART2
// <string name="RT_CONSOLE_DEVICE_NAME" description="The name of console device" default="" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </RDTConfigurator>
#ifdef __CC_ARM

1
bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c
View File

@ -157,6 +157,7 @@ void UART0_IRQHandler(void)
break;
default :
tmp = LPC_USART0->INTSTAT;
RT_UNUSED(tmp);
break;
}
/* leave interrupt */

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bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib Normal file
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bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a Normal file
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2
bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c
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@ -128,7 +128,7 @@ static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configurat
return ret;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
spi_transfer_t transfer = {0};

4
components/drivers/include/drivers/adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -38,7 +38,7 @@
* if (adc_dev == RT_NULL)
* {
* rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
* return RT_ERROR;
* return -RT_ERROR;
* }
*
* ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);

4
components/drivers/include/drivers/dac.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -38,7 +38,7 @@
* if (dac_dev == RT_NULL)
* {
* rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME);
* return RT_ERROR;
* return -RT_ERROR;
* }
*
* ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL);