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[bsp][nxp][rsoc] Fix compilation issues with bsp of nxp/lxp series

This commit is contained in:
hydevcode 2024-09-30 08:47:39 +08:00 committed by GitHub
parent e7e44ec7e8
commit 66d54ea8c0
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GPG Key ID: B5690EEEBB952194
17 changed files with 1336 additions and 1234 deletions
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4
.github/workflows/bsp_buildings.yml vendored
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@ -209,8 +209,8 @@ jobs:
- "nxp/lpc/lpc1114" - "nxp/lpc/lpc1114"
- "nxp/lpc/lpc2148" - "nxp/lpc/lpc2148"
- "nxp/lpc/lpc2478" - "nxp/lpc/lpc2478"
# - "nxp/lpc/lpc5410x" - "nxp/lpc/lpc5410x"
# - "nxp/lpc/lpc54114-lite" - "nxp/lpc/lpc54114-lite"
- "nxp/lpc/lpc176x" - "nxp/lpc/lpc176x"
#- "nxp/lpc/lpc43xx/M4" #- "nxp/lpc/lpc43xx/M4"
- "nxp/imx/imx6sx/cortex-a9" - "nxp/imx/imx6sx/cortex-a9"

272
bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c
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@ -1,23 +1,9 @@
//***************************************************************************** /* Startup code for use with GNU tools.*/
// /* Forward declaration of the default fault handlers.*/
// Startup code for use with GNU tools.
//
//*****************************************************************************
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
static void Reset_Handler(void); static void Reset_Handler(void);
static void Default_Handler(void); static void Default_Handler(void);
//***************************************************************************** /* External declaration for the interrupt handler used by the application.*/
//
// External declaration for the interrupt handler used by the application.
//
//*****************************************************************************
void NMI_Handler(void) __attribute__((weak, alias("Default_Handler"))); void NMI_Handler(void) __attribute__((weak, alias("Default_Handler")));
void HardFault_Handler(void) __attribute__((weak, alias("Default_Handler"))); void HardFault_Handler(void) __attribute__((weak, alias("Default_Handler")));
void MemManage_Handler(void) __attribute__((weak, alias("Default_Handler"))); void MemManage_Handler(void) __attribute__((weak, alias("Default_Handler")));
@ -59,182 +45,161 @@ void ADC_SEQA_IRQHandler(void) __attribute__((weak, alias("Default_Handler"
void ADC_SEQB_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void ADC_SEQB_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void ADC_THCMP_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void ADC_THCMP_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void RTC_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void RTC_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); /*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void MAILBOX_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void MAILBOX_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void GINT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void GINT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT4_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void PIN_INT4_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT5_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void PIN_INT5_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT6_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void PIN_INT6_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT7_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void PIN_INT7_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); /*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); /*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); /*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void RIT_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void RIT_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved42_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void Reserved42_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved44_IRQHandler(void) __attribute__((weak, alias("Default_Handler"))); void Reserved44_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
//***************************************************************************** /* The entry point for the application.*/
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void); extern int main(void);
//***************************************************************************** /* Reserve space for the system stack.*/
//
// Reserve space for the system stack.
//
//*****************************************************************************
static unsigned long pulStack[512]; static unsigned long pulStack[512];
//***************************************************************************** /* The vector table. Note that the proper constructs must be placed on this to*/
// /* ensure that it ends up at physical address 0x0000.0000.*/
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
__attribute__ ((section(".isr_vector"))) __attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = void (* const g_pfnVectors[])(void) =
{ {
(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
// The initial stack pointer /* The initial stack pointer*/
Reset_Handler, // Reset Handler Reset_Handler, /* Reset Handler*/
NMI_Handler, // NMI Handler NMI_Handler, /* NMI Handler*/
HardFault_Handler, // Hard Fault Handler HardFault_Handler, /* Hard Fault Handler*/
MemManage_Handler, // MPU Fault Handler MemManage_Handler, /* MPU Fault Handler*/
BusFault_Handler, // Bus Fault Handler BusFault_Handler, /* Bus Fault Handler*/
UsageFault_Handler, // Usage Fault Handler UsageFault_Handler, /* Usage Fault Handler*/
0, // Reserved 0, /* Reserved*/
0, // Reserved 0, /* Reserved*/
0, // Reserved 0, /* Reserved*/
0, // Reserved 0, /* Reserved*/
SVC_Handler, // SVCall Handler SVC_Handler, /* SVCall Handler*/
DebugMon_Handler, // Debug Monitor Handler DebugMon_Handler, /* Debug Monitor Handler*/
0, // Reserved 0, /* Reserved*/
PendSV_Handler, // PendSV Handler PendSV_Handler, /* PendSV Handler*/
SysTick_Handler, // SysTick Handler SysTick_Handler, /* SysTick Handler*/
// External Interrupts /* External Interrupts*/
WDT_IRQHandler, WDT_IRQHandler,
BOD_IRQHandler, BOD_IRQHandler,
Reserved_IRQHandler, Reserved_IRQHandler,
DMA_IRQHandler, DMA_IRQHandler,
GINT0_IRQHandler, GINT0_IRQHandler,
PIN_INT0_IRQHandler, PIN_INT0_IRQHandler,
PIN_INT1_IRQHandler, PIN_INT1_IRQHandler,
PIN_INT2_IRQHandler, PIN_INT2_IRQHandler,
PIN_INT3_IRQHandler, PIN_INT3_IRQHandler,
UTICK_IRQHandler, UTICK_IRQHandler,
MRT_IRQHandler, MRT_IRQHandler,
CT32B0_IRQHandler, CT32B0_IRQHandler,
CT32B1_IRQHandler, CT32B1_IRQHandler,
CT32B2_IRQHandler, CT32B2_IRQHandler,
CT32B3_IRQHandler, CT32B3_IRQHandler,
CT32B4_IRQHandler, CT32B4_IRQHandler,
SCT0_IRQHandler, SCT0_IRQHandler,
UART0_IRQHandler, UART0_IRQHandler,
UART1_IRQHandler, UART1_IRQHandler,
UART2_IRQHandler, UART2_IRQHandler,
UART3_IRQHandler, UART3_IRQHandler,
I2C0_IRQHandler, I2C0_IRQHandler,
I2C1_IRQHandler, I2C1_IRQHandler,
I2C2_IRQHandler, I2C2_IRQHandler,
SPI0_IRQHandler, SPI0_IRQHandler,
SPI1_IRQHandler, SPI1_IRQHandler,
ADC_SEQA_IRQHandler, ADC_SEQA_IRQHandler,
ADC_SEQB_IRQHandler, ADC_SEQB_IRQHandler,
ADC_THCMP_IRQHandler, ADC_THCMP_IRQHandler,
RTC_IRQHandler, RTC_IRQHandler,
Reserved_IRQHandler, Reserved_IRQHandler,
MAILBOX_IRQHandler, MAILBOX_IRQHandler,
GINT1_IRQHandler, GINT1_IRQHandler,
PIN_INT4_IRQHandler, PIN_INT4_IRQHandler,
PIN_INT5_IRQHandler, PIN_INT5_IRQHandler,
PIN_INT6_IRQHandler, PIN_INT6_IRQHandler,
PIN_INT7_IRQHandler, PIN_INT7_IRQHandler,
Reserved_IRQHandler, Reserved_IRQHandler,
Reserved_IRQHandler, Reserved_IRQHandler,
Reserved_IRQHandler, Reserved_IRQHandler,
RIT_IRQHandler, RIT_IRQHandler,
Reserved41_IRQHandler, Reserved41_IRQHandler,
Reserved42_IRQHandler, Reserved42_IRQHandler,
Reserved43_IRQHandler, Reserved43_IRQHandler,
Reserved44_IRQHandler, Reserved44_IRQHandler,
}; };
//**RIT_IRQHandler *************************************************************************** /* RIT_IRQHandler */
// Reserved41_IRQHandler /* Reserved41_IRQHandler*/
// TReserved42_IRQHandler he following are constructs created by the linker, indicating where the /* TReserved42_IRQHandler he following are constructs created by the linker, indicating where the*/
// tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the /* tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the*/
// fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment. /* fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.*/
//
//*****************************************************************************
extern unsigned long _etext; extern unsigned long _etext;
extern unsigned long _data; extern unsigned long _data;
extern unsigned long _edata; extern unsigned long _edata;
extern unsigned long _bss; extern unsigned long _bss;
extern unsigned long _ebss; extern unsigned long _ebss;
//***************************************************************************** /* This is the code that gets called when the processor first starts execution*/
// /* following a reset event. Only the absolutely necessary set is performed,*/
// This is the code that gets called when the processor first starts execution /* after which the application supplied entry() routine is called. Any fancy*/
// following a reset event. Only the absolutely necessary set is performed, /* actions (such as making decisions based on the reset cause register, and*/
// after which the application supplied entry() routine is called. Any fancy /* resetting the bits in that register) are left solely in the hands of the*/
// actions (such as making decisions based on the reset cause register, and /* application.*/
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
static void Reset_Handler(void) static void Reset_Handler(void)
{ {
unsigned long *pulSrc, *pulDest; unsigned long *pulSrc, *pulDest;
// /* Copy the data segment initializers from flash to SRAM.*/
// Copy the data segment initializers from flash to SRAM.
//
pulSrc = &_etext; pulSrc = &_etext;
/* cppcheck-suppress comparePointers */
for(pulDest = &_data; pulDest < &_edata; ) for(pulDest = &_data; pulDest < &_edata; )
{ {
*pulDest++ = *pulSrc++; *pulDest++ = *pulSrc++;
} }
#if !defined (__USE_LPCOPEN) #if !defined (__USE_LPCOPEN)
// LPCOpen init code deals with FP and VTOR initialisation /* LPCOpen init code deals with FP and VTOR initialisation*/
#if defined (__VFP_FP__) && !defined (__SOFTFP__) #if defined (__VFP_FP__) && !defined (__SOFTFP__)
/* /*
* Code to enable the Cortex-M4 FPU only included * Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected. * if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/ */
// CPACR is located at address 0xE000ED88 /* CPACR is located at address 0xE000ED88*/
asm("LDR.W R0, =0xE000ED88"); asm("LDR.W R0, =0xE000ED88");
// Read CPACR /* Read CPACR*/
asm("LDR R1, [R0]"); asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors /* Set bits 20-23 to enable CP10 and CP11 coprocessors*/
asm(" ORR R1, R1, #(0xF << 20)"); asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR /* Write back the modified value to the CPACR*/
asm("STR R1, [R0]"); asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__) #endif /* (__VFP_FP__) && !(__SOFTFP__)*/
// ****************************** /* Check to see if we are running the code from a non-zero*/
// Check to see if we are running the code from a non-zero /* address (eg RAM, external flash), in which case we need*/
// address (eg RAM, external flash), in which case we need /* to modify the VTOR register to tell the CPU that the*/
// to modify the VTOR register to tell the CPU that the /* vector table is located at a non-0x0 address.*/
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism, /* Note that we do not use the CMSIS register access mechanism,*/
// as there is no guarantee that the project has been configured /* as there is no guarantee that the project has been configured*/
// to use CMSIS. /* to use CMSIS.*/
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) { if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000)
// CMSIS : SCB->VTOR = <address of vector table> {
/* CMSIS : SCB->VTOR = <address of vector table>*/
*pSCB_VTOR = (unsigned int) g_pfnVectors; *pSCB_VTOR = (unsigned int) g_pfnVectors;
} }
#endif #endif
// /* Zero fill the bss segment.*/
// Zero fill the bss segment.
//
__asm(" ldr r0, =_bss\n" __asm(" ldr r0, =_bss\n"
" ldr r1, =_ebss\n" " ldr r1, =_ebss\n"
" mov r2, #0\n" " mov r2, #0\n"
@ -245,28 +210,21 @@ static void Reset_Handler(void)
" strlt r2, [r0], #4\n" " strlt r2, [r0], #4\n"
" blt zero_loop"); " blt zero_loop");
// call system init. /* call system init.*/
SystemInit(); extern void SystemInit(void);
SystemInit();
// /* Call the application's entry point.*/
// Call the application's entry point.
//
main(); main();
} }
//***************************************************************************** /* This is the code that gets called when the processor receives an unexpected*/
// /* interrupt. This simply enters an infinite loop, preserving the system state*/
// This is the code that gets called when the processor receives an unexpected /* for examination by a debugger.*/
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void Default_Handler(void) static void Default_Handler(void)
{ {
// /* Go into an infinite loop.*/
// Go into an infinite loop.
//
while(1) while(1)
{ {
} }
} }

250
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c
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@ -38,171 +38,189 @@
/* Private data structure used for the I2C monitor driver, holds the driver and /* Private data structure used for the I2C monitor driver, holds the driver and
peripheral context */ peripheral context */
typedef struct { typedef struct {
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */ void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */ LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */
i2cMonCapReadyCB pCapCompCB; /*!< Capture complete callback */ i2cMonCapReadyCB pCapCompCB; /*!< Capture complete callback */
i2cMonSetupDMACB pDmaSetupCB; /*!< DMA setup callback */ i2cMonSetupDMACB pDmaSetupCB; /*!< DMA setup callback */
ROM_I2CMON_CAP_T *pCap; /*!< Pointer to current capture descriptor */ ROM_I2CMON_CAP_T *pCap; /*!< Pointer to current capture descriptor */
ErrorCode_t pendingStatus; /*!< Pending monitor transfer status before clocking transfer */ ErrorCode_t pendingStatus; /*!< Pending monitor transfer status before clocking transfer */
} I2CMON_DATACONTEXT_T; } I2CMON_DATACONTEXT_T;
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle) void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
; ;
// ********************************************************** /* ********************************************************** */
uint32_t i2cmon_get_mem_size(void) uint32_t i2cmon_get_mem_size(void)
{ {
return sizeof(I2CMON_DATACONTEXT_T); return sizeof(I2CMON_DATACONTEXT_T);
} }
ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit) ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit)
{ {
I2CMON_DATACONTEXT_T *pDrv; I2CMON_DATACONTEXT_T *pDrv;
uint32_t reg; uint32_t reg;
/* Verify alignment is at least 4 bytes */ /* Verify alignment is at least 4 bytes */
if (((uint32_t) mem & 0x3) != 0) { if (((uint32_t) mem & 0x3) != 0)
return NULL; {
} return NULL;
}
pDrv = (I2CMON_DATACONTEXT_T *) mem; pDrv = (I2CMON_DATACONTEXT_T *) mem;
memset(pDrv, 0, sizeof(I2CMON_DATACONTEXT_T)); memset(pDrv, 0, sizeof(I2CMON_DATACONTEXT_T));
/* Save base of peripheral and pointer to user data */ /* Save base of peripheral and pointer to user data */
pDrv->pUserData = pInit->pUserData; pDrv->pUserData = pInit->pUserData;
pDrv->base = (LPC_I2C_T *) pInit->base; pDrv->base = (LPC_I2C_T *) pInit->base;
/* Clear pending monitor statuses */ /* Clear pending monitor statuses */
pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV); pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) { while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
/* Toss input data */ {
reg = pDrv->base->MONRXDAT; /* Toss input data */
} reg = pDrv->base->MONRXDAT;
}
/* Enable I2C monitor interface */ /* Enable I2C monitor interface */
reg = pDrv->base->CFG | I2C_CFG_MONEN; reg = pDrv->base->CFG | I2C_CFG_MONEN;
if (pInit->stretch != 0) { if (pInit->stretch != 0)
reg |= I2C_CFG_MONCLKSTR; {
} reg |= I2C_CFG_MONCLKSTR;
pDrv->base->CFG = reg; }
pDrv->base->CFG = reg;
return pDrv; return pDrv;
} }
void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB) void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB)
{ {
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB) { if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB)
pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB; {
} pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB;
else if (cbIndex == ROM_I2CMON_DMASETUP_CB) { }
pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB; else if (cbIndex == ROM_I2CMON_DMASETUP_CB)
} {
pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB;
}
} }
ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap) ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap)
{ {
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
/* I2C master controller should be pending and idle */ /* I2C master controller should be pending and idle */
if (pCap == NULL) { if (pCap == NULL)
return ERR_I2C_PARAM; {
} return ERR_I2C_PARAM;
}
/* Verify receive buffer alignment */ /* Verify receive buffer alignment */
if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0)) { if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0))
pCap->status = ERR_I2C_PARAM; {
return ERR_I2C_PARAM; pCap->status = ERR_I2C_PARAM;
} return ERR_I2C_PARAM;
}
pDrv->pCap = pCap; pDrv->pCap = pCap;
pCap->capStartBuffSz = 0; pCap->capStartBuffSz = 0;
pDrv->pendingStatus = LPC_OK; pDrv->pendingStatus = LPC_OK;
pCap->status = ERR_I2C_BUSY; pCap->status = ERR_I2C_BUSY;
if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0) { if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0)
while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) { {
/* Toss input data */ while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
volatile uint32_t reg = pDrv->base->MONRXDAT; {
} /* Toss input data */
} volatile uint32_t reg = pDrv->base->MONRXDAT;
(void)reg;
}
}
/* Clear controller state */ /* Clear controller state */
pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV); pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB)) { if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB))
pDrv->pDmaSetupCB(pHandle, pCap); {
pDrv->pDmaSetupCB(pHandle, pCap);
/* Enable supported monitor interrupts */ /* Enable supported monitor interrupts */
pDrv->base->INTENSET = (I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE); pDrv->base->INTENSET = (I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
} }
else { else {
pCap->flags &= ~ROM_I2CMON_FLAG_DMARX; pCap->flags &= ~ROM_I2CMON_FLAG_DMARX;
/* Enable supported monitor interrupts */ /* Enable supported monitor interrupts */
pDrv->base->INTENSET = (I2C_INTENSET_MONRDY | I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE); pDrv->base->INTENSET = (I2C_INTENSET_MONRDY | I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
} }
/* Is transfer blocking? */ /* Is transfer blocking? */
if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0) { if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0)
while (pCap->status == ERR_I2C_BUSY) { {
i2cmon_transfer_handler(pHandle); while (pCap->status == ERR_I2C_BUSY)
} {
} i2cmon_transfer_handler(pHandle);
}
}
return pCap->status; return pCap->status;
} }
// Otime = "optimize for speed of code execution" /* Otime = "optimize for speed of code execution"*/
// ...add this pragma 1 line above the interrupt service routine function. /* ...add this pragma 1 line above the interrupt service routine function.*/
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle) void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
{ {
I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle; I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
ROM_I2CMON_CAP_T *pCap = pDrv->pCap; ROM_I2CMON_CAP_T *pCap = pDrv->pCap;
uint16_t data = 0, *pData; uint16_t data = 0, *pData;
uint32_t status = pDrv->base->STAT; uint32_t status = pDrv->base->STAT;
if (status & I2C_STAT_MONOV) { if (status & I2C_STAT_MONOV)
/* Monitor data overflow */ {
data = pDrv->base->MONRXDAT; /* Monitor data overflow */
pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; data = pDrv->base->MONRXDAT;
pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
/* Clear Status Flags */ /* Clear Status Flags */
pDrv->base->STAT = I2C_STAT_MONOV; pDrv->base->STAT = I2C_STAT_MONOV;
} }
else if (status & I2C_STAT_MONRDY) { else if (status & I2C_STAT_MONRDY)
/* Monitor ready */ {
data = pDrv->base->MONRXDAT; /* Monitor ready */
data = pDrv->base->MONRXDAT;
/* Enough room to place this data? */ /* Enough room to place this data? */
if (pCap->capStartBuffSz >= pCap->startBuffSz) { if (pCap->capStartBuffSz >= pCap->startBuffSz)
/* Data overflow */ {
pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW; /* Data overflow */
} pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
else { }
pData = (uint16_t *) pCap->startBuff; else {
pData = (uint16_t *) pCap->startBuff;
pData[pCap->capStartBuffSz] = data; pData[pCap->capStartBuffSz] = data;
pCap->capStartBuffSz++; pCap->capStartBuffSz++;
} }
} }
/* Capture complete? */ /* Capture complete? */
if ((status & I2C_INTSTAT_MONIDLE) != 0) { if ((status & I2C_INTSTAT_MONIDLE) != 0)
pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV | {
I2C_INTENCLR_MONIDLE); pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV |
pCap->status = pDrv->pendingStatus; I2C_INTENCLR_MONIDLE);
if (pDrv->pCapCompCB) { pCap->status = pDrv->pendingStatus;
pDrv->pCapCompCB(pHandle, pCap); if (pDrv->pCapCompCB)
} {
} pDrv->pCapCompCB(pHandle, pCap);
}
}
} }
uint32_t i2cmon_get_driver_version(void) uint32_t i2cmon_get_driver_version(void)
{ {
return DRVVERSION; return DRVVERSION;
} }
// ********************************************************* /* ********************************************************** */

814
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c
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bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c
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46
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h
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@ -63,27 +63,27 @@ extern "C" {
* @brief High level ROM API structure * @brief High level ROM API structure
*/ */
typedef struct { typedef struct {
const uint32_t reserved_usb; /*!< Reserved */ const uint32_t reserved_usb; /*!< Reserved */
const uint32_t reserved_clib; /*!< Reserved */ const uint32_t reserved_clib; /*!< Reserved */
const uint32_t reserved_can; /*!< Reserved */ const uint32_t reserved_can; /*!< Reserved */
const PWRD_API_T *pPWRD; /*!< Power API function table base address */ const PWRD_API_T *pPWRD; /*!< Power API function table base address */
const uint32_t reserved_div; /*!< Reserved */ const uint32_t reserved_div; /*!< Reserved */
const uint32_t reserved_i2cd; /*!< Reserved */ const uint32_t reserved_i2cd; /*!< Reserved */
const uint32_t reserved_dmad; /*!< Reserved */ const uint32_t reserved_dmad; /*!< Reserved */
const uint32_t reserved_spid; /*!< Reserved */ const uint32_t reserved_spid; /*!< Reserved */
const uint32_t reserved_adcd; /*!< Reserved */ const uint32_t reserved_adcd; /*!< Reserved */
const uint32_t reserved_uartd; /*!< Reserved */ const uint32_t reserved_uartd; /*!< Reserved */
const uint32_t reserved_vfifo; /*!< Reserved */ const uint32_t reserved_vfifo; /*!< Reserved */
const uint32_t reserved_usart; /*!< Reserved */ const uint32_t reserved_usart; /*!< Reserved */
/* v2 drivers - only present in some LPC5410x devices */ /* v2 drivers - only present in some LPC5410x devices */
const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */ const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */
const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */ const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */
const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */ const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */
const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */ const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */
const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */ const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */
const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */ const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */
const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */ const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */
const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */ const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */
} LPC_ROM_API_T; } LPC_ROM_API_T;
/* Pointer to ROM API function address */ /* Pointer to ROM API function address */
@ -123,9 +123,9 @@ typedef struct {
/** /**
* @brief LPC5410x IAP_ENTRY API function type * @brief LPC5410x IAP_ENTRY API function type
*/ */
static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4]) static INLINE void iap_entry(uint32_t cmd_param[5], uint32_t status_result[4])
{ {
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result); ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
} }
/** /**

2
bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h
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@ -78,7 +78,7 @@ extern "C" {
#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */ #define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */
/* IAP_ENTRY API function type */ /* IAP_ENTRY API function type */
typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]); typedef void (*IAP_ENTRY_T)(uint32_t[5], uint32_t[4]);
/** /**
* @brief Prepare sector for write operation * @brief Prepare sector for write operation

11
bsp/nxp/lpc/lpc5410x/applications/board.h
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@ -25,21 +25,10 @@
#endif #endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse"> // <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" /> // <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000 #define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" /> // <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000 #define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
#define RT_USING_UART2
// <string name="RT_CONSOLE_DEVICE_NAME" description="The name of console device" default="" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </RDTConfigurator> // </RDTConfigurator>
#ifdef __CC_ARM #ifdef __CC_ARM

1
bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c
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@ -157,6 +157,7 @@ void UART0_IRQHandler(void)
break; break;
default : default :
tmp = LPC_USART0->INTSTAT; tmp = LPC_USART0->INTSTAT;
RT_UNUSED(tmp);
break; break;
} }
/* leave interrupt */ /* leave interrupt */

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bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c
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@ -128,7 +128,7 @@ static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configurat
return ret; return ret;
} }
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{ {
spi_transfer_t transfer = {0}; spi_transfer_t transfer = {0};

30
components/drivers/include/drivers/adc.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2023, RT-Thread Development Team * Copyright (c) 2006-2024 RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -22,39 +22,39 @@
* *
* <b>Example</b> * <b>Example</b>
* @code {.c} * @code {.c}
* #define ADC_DEV_NAME "adc1" * #define ADC_DEV_NAME "adc1"
* #define ADC_DEV_CHANNEL 5 * #define ADC_DEV_CHANNEL 5
* #define REFER_VOLTAGE 330 * #define REFER_VOLTAGE 330
* #define CONVERT_BITS (1 << 12) * #define CONVERT_BITS (1 << 12)
* *
* static int adc_vol_sample(int argc, char *argv[]) * static int adc_vol_sample(int argc, char *argv[])
* { * {
* rt_adc_device_t adc_dev; * rt_adc_device_t adc_dev;
* rt_uint32_t value, vol; * rt_uint32_t value, vol;
* *
* rt_err_t ret = RT_EOK; * rt_err_t ret = RT_EOK;
* *
* adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); * adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
* if (adc_dev == RT_NULL) * if (adc_dev == RT_NULL)
* { * {
* rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); * rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
* return RT_ERROR; * return -RT_ERROR;
* } * }
* *
* ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); * ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
* *
* value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); * value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
* rt_kprintf("the value is :%d \n", value); * rt_kprintf("the value is :%d \n", value);
* *
* vol = value * REFER_VOLTAGE / CONVERT_BITS; * vol = value * REFER_VOLTAGE / CONVERT_BITS;
* rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
* *
* ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); * ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
* *
* return ret; * return ret;
* } * }
* MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); * MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
* *
* @endcode * @endcode
* *
* @ingroup Drivers * @ingroup Drivers

36
components/drivers/include/drivers/dac.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2023, RT-Thread Development Team * Copyright (c) 2006-2024 RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -19,47 +19,47 @@
* *
* <b>Example</b> * <b>Example</b>
* @code {.c} * @code {.c}
* *
* #include <rtthread.h> * #include <rtthread.h>
* #include <rtdevice.h> * #include <rtdevice.h>
* #include <stdlib.h> * #include <stdlib.h>
* #define DAC_DEV_NAME "dac1" * #define DAC_DEV_NAME "dac1"
* #define DAC_DEV_CHANNEL 1 * #define DAC_DEV_CHANNEL 1
* #define REFER_VOLTAGE 330 * #define REFER_VOLTAGE 330
* #define CONVERT_BITS (1 << 12) * #define CONVERT_BITS (1 << 12)
* *
* static int dac_vol_sample(int argc, char *argv[]) * static int dac_vol_sample(int argc, char *argv[])
* { * {
* rt_dac_device_t dac_dev; * rt_dac_device_t dac_dev;
* rt_uint32_t value, vol; * rt_uint32_t value, vol;
* rt_err_t ret = RT_EOK; * rt_err_t ret = RT_EOK;
* *
* dac_dev = (rt_dac_device_t)rt_device_find(DAC_DEV_NAME); * dac_dev = (rt_dac_device_t)rt_device_find(DAC_DEV_NAME);
* if (dac_dev == RT_NULL) * if (dac_dev == RT_NULL)
* { * {
* rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME); * rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME);
* return RT_ERROR; * return -RT_ERROR;
* } * }
* *
* ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL); * ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL);
* *
* value = atoi(argv[1]); * value = atoi(argv[1]);
* rt_dac_write(dac_dev, DAC_DEV_NAME, DAC_DEV_CHANNEL, value); * rt_dac_write(dac_dev, DAC_DEV_NAME, DAC_DEV_CHANNEL, value);
* rt_kprintf("the value is :%d \n", value); * rt_kprintf("the value is :%d \n", value);
* *
* vol = value * REFER_VOLTAGE / CONVERT_BITS; * vol = value * REFER_VOLTAGE / CONVERT_BITS;
* rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
* *
* rt_thread_mdelay(500); * rt_thread_mdelay(500);
* *
* ret = rt_dac_disable(dac_dev, DAC_DEV_CHANNEL); * ret = rt_dac_disable(dac_dev, DAC_DEV_CHANNEL);
* *
* return ret; * return ret;
* } * }
* MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample); * MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample);
* *
* @endcode * @endcode
* *
* @ingroup Drivers * @ingroup Drivers
*/ */
@ -80,7 +80,7 @@ struct rt_dac_ops
}; };
/** /**
* @brief DAC device structure * @brief DAC device structure
* *
*/ */
struct rt_dac_device struct rt_dac_device
{ {