[bsp] Add MB9BF618 porting.
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bernard
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33fed1b167
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66c2d28fbf
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;/************************************************************************/
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;/* (C) Fujitsu Semiconductor Europe GmbH */
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;/* */
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;/* The following software deliverable is intended for and must only be */
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;/* used for reference and in an evaluation laboratory environment. */
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;/* It is provided on an as-is basis without charge and is subject to */
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;/* alterations. */
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;/* It is the user’s obligation to fully test the software in its */
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;/* environment and to ensure proper functionality, qualification and */
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;/* compliance with component specifications. */
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;/* */
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;/* In the event the software deliverable includes the use of open */
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;/* source components, the provisions of the governing open source */
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;/* license agreement shall apply with respect to such software */
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;/* deliverable. */
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;/* FSEU does not warrant that the deliverables do not infringe any */
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;/* third party intellectual property right (IPR). In the event that */
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;/* the deliverables infringe a third party IPR it is the sole */
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;/* responsibility of the customer to obtain necessary licenses to */
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;/* continue the usage of the deliverable. */
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;/* */
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;/* To the maximum extent permitted by applicable law FSEU disclaims all */
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;/* warranties, whether express or implied, in particular, but not */
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;/* limited to, warranties of merchantability and fitness for a */
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;/* particular purpose for which the deliverable is not designated. */
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;/* */
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;/* To the maximum extent permitted by applicable law, FSEU's liability */
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;/* is restricted to intention and gross negligence. */
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;/* FSEU is not liable for consequential damages. */
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;/* */
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;/* (V1.4) */
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;/************************************************************************/
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;/* Startup for ARM */
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;/* Version V1.02 */
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;/* Date 2011-07-25 */
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;/* Target-mcu MB9B61x */
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;/************************************************************************/
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; Stack Configuration
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; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; Heap Configuration
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; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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DCD CSV_Handler ; 0: Clock Super Visor
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DCD SWDT_Handler ; 1: Software Watchdog Timer
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DCD LVD_Handler ; 2: Low Voltage Detector
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DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
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DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
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DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31
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DCD DT_Handler ; 6: Dual Timer / Quad Decoder
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DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
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DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
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DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
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DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
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DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
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DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
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DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
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DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
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DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
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DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
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DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
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DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
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DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
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DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
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DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
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DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
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DCD PPG_Handler ; 23: PPG
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DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
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DCD ADC0_IRQHandler ; 25: ADC0
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DCD ADC1_IRQHandler ; 26: ADC1
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DCD ADC2_IRQHandler ; 27: ADC2
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DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
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DCD MFT_IPC_IRQHandler ; 29: Input Capture
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DCD MFT_OPC_IRQHandler ; 30: Output Compare
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DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7
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DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0
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DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1
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DCD USB0F_Handler ; 34: USB0 Function
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DCD USB0_Handler ; 35: USB0 Function / USB0 HOST
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DCD USB1F_Handler ; 36: USB1 Function
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DCD USB1_Handler ; 37: USB1 Function / USB1 HOST
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DCD DMAC0_Handler ; 38: DMAC ch.0
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DCD DMAC1_Handler ; 39: DMAC ch.1
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DCD DMAC2_Handler ; 40: DMAC ch.2
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DCD DMAC3_Handler ; 41: DMAC ch.3
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DCD DMAC4_Handler ; 42: DMAC ch.4
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DCD DMAC5_Handler ; 43: DMAC ch.5
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DCD DMAC6_Handler ; 44: DMAC ch.6
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DCD DMAC7_Handler ; 45: DMAC ch.7
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DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15
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DCD DummyHandler ; 47: Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT CSV_Handler [WEAK]
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EXPORT SWDT_Handler [WEAK]
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EXPORT LVD_Handler [WEAK]
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EXPORT MFT_WG_IRQHandler [WEAK]
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EXPORT INT0_7_Handler [WEAK]
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EXPORT INT8_31_Handler [WEAK]
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EXPORT DT_Handler [WEAK]
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EXPORT MFS0RX_IRQHandler [WEAK]
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EXPORT MFS0TX_IRQHandler [WEAK]
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EXPORT MFS1RX_IRQHandler [WEAK]
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EXPORT MFS1TX_IRQHandler [WEAK]
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EXPORT MFS2RX_IRQHandler [WEAK]
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EXPORT MFS2TX_IRQHandler [WEAK]
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EXPORT MFS3RX_IRQHandler [WEAK]
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EXPORT MFS3TX_IRQHandler [WEAK]
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EXPORT MFS4RX_IRQHandler [WEAK]
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EXPORT MFS4TX_IRQHandler [WEAK]
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EXPORT MFS5RX_IRQHandler [WEAK]
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EXPORT MFS5TX_IRQHandler [WEAK]
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EXPORT MFS6RX_IRQHandler [WEAK]
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EXPORT MFS6TX_IRQHandler [WEAK]
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EXPORT MFS7RX_IRQHandler [WEAK]
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EXPORT MFS7TX_IRQHandler [WEAK]
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EXPORT PPG_Handler [WEAK]
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EXPORT TIM_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT ADC2_IRQHandler [WEAK]
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EXPORT MFT_FRT_IRQHandler [WEAK]
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EXPORT MFT_IPC_IRQHandler [WEAK]
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EXPORT MFT_OPC_IRQHandler [WEAK]
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EXPORT BT0_7_IRQHandler [WEAK]
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EXPORT ETHER_MAC0_IRQHandler [WEAK]
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EXPORT ETHER_MAC1_IRQHandler [WEAK]
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EXPORT USB0F_Handler [WEAK]
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EXPORT USB0_Handler [WEAK]
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EXPORT USB1F_Handler [WEAK]
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EXPORT USB1_Handler [WEAK]
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EXPORT DMAC0_Handler [WEAK]
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EXPORT DMAC1_Handler [WEAK]
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EXPORT DMAC2_Handler [WEAK]
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EXPORT DMAC3_Handler [WEAK]
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EXPORT DMAC4_Handler [WEAK]
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EXPORT DMAC5_Handler [WEAK]
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EXPORT DMAC6_Handler [WEAK]
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EXPORT DMAC7_Handler [WEAK]
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EXPORT BT8_15_IRQHandler [WEAK]
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EXPORT DummyHandler [WEAK]
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CSV_Handler
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SWDT_Handler
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LVD_Handler
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MFT_WG_IRQHandler
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INT0_7_Handler
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INT8_31_Handler
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DT_Handler
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MFS0RX_IRQHandler
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MFS0TX_IRQHandler
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MFS1RX_IRQHandler
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MFS1TX_IRQHandler
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MFS2RX_IRQHandler
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MFS2TX_IRQHandler
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MFS3RX_IRQHandler
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MFS3TX_IRQHandler
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MFS4RX_IRQHandler
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MFS4TX_IRQHandler
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MFS5RX_IRQHandler
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MFS5TX_IRQHandler
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MFS6RX_IRQHandler
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MFS6TX_IRQHandler
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MFS7RX_IRQHandler
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MFS7TX_IRQHandler
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PPG_Handler
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TIM_IRQHandler
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ADC0_IRQHandler
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ADC1_IRQHandler
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ADC2_IRQHandler
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MFT_FRT_IRQHandler
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MFT_IPC_IRQHandler
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MFT_OPC_IRQHandler
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BT0_7_IRQHandler
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DMAC0_Handler
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DMAC1_Handler
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DMAC2_Handler
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DMAC3_Handler
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DMAC4_Handler
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DMAC5_Handler
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DMAC6_Handler
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DMAC7_Handler
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ETHER_MAC0_IRQHandler
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ETHER_MAC1_IRQHandler
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USB0F_Handler
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USB0_Handler
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USB1F_Handler
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USB1_Handler
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BT8_15_IRQHandler
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DummyHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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@ -0,0 +1,244 @@
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/*
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****************************************************************************
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**
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** File : startup_mb9bf61x.c
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**
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** Abstract : This file contains interrupt vector and startup code.
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**
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** Functions : Reset_Handler
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**
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** Target : Fujitsu FM3 microcontrollers
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**
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** Environment : Atollic TrueSTUDIO(R)
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**
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** Distribution: The file is distributed “as is,” without any warranty
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** of any kind.
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**
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** (c)Copyright Atollic AB.
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** You may use this file as-is or modify it according to the needs of your
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** project. Distribution of this file (unmodified or modified) is not
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** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
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** rights to distribute the assembled, compiled & linked contents of this
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** file as part of an application binary file, provided that it is built
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** using the Atollic TrueSTUDIO(R) toolchain.
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**
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****************************************************************************
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*/
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/**
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**===========================================================================
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** Revisions
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**===========================================================================
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** Date Modification
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** 2011-08-18 First issue.
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**===========================================================================
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*/
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/**
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**===========================================================================
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** External declarations
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**===========================================================================
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*/
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extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector;
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extern unsigned long _estack;
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extern void __libc_init_array();
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extern void SystemInit();
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extern void main();
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/**
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**===========================================================================
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** Default interrupt handler
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**===========================================================================
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*/
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void Default_Handler()
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{
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/* Hang here */
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while(1)
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{
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}
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}
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/**
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**===========================================================================
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** Reset handler
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**===========================================================================
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*/
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__attribute__((naked)) void Reset_Handler()
|
||||||
|
{
|
||||||
|
/* Data and BSS variables */
|
||||||
|
unsigned long *srcdata, *dstdata, *sbss;
|
||||||
|
|
||||||
|
/* Set up the stack pointer */
|
||||||
|
asm("ldr sp,=_estack\n\t");
|
||||||
|
|
||||||
|
/* Set up vector table offset register */
|
||||||
|
dstdata = (unsigned long *)0xe000ed08;
|
||||||
|
*dstdata = (unsigned long)&_isr_vector;
|
||||||
|
|
||||||
|
srcdata = &_sidata;
|
||||||
|
dstdata = &_sdata;
|
||||||
|
sbss = &_sbss;
|
||||||
|
|
||||||
|
/* Copy data */
|
||||||
|
while(dstdata != &_edata)
|
||||||
|
{
|
||||||
|
*(dstdata++) = *(srcdata++);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear BSS */
|
||||||
|
while(sbss != &_ebss)
|
||||||
|
{
|
||||||
|
*(sbss++) = '\0';
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Run static constructors */
|
||||||
|
//__libc_init_array();
|
||||||
|
|
||||||
|
/* Call the clock system initialization function.*/
|
||||||
|
SystemInit();
|
||||||
|
|
||||||
|
/* Jump to main */
|
||||||
|
main();
|
||||||
|
|
||||||
|
/* In case main returns, use default handler */
|
||||||
|
Default_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
**===========================================================================
|
||||||
|
** Weak definitions of handlers point to Default_Handler if not implemented
|
||||||
|
**===========================================================================
|
||||||
|
*/
|
||||||
|
void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
|
||||||
|
void CSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void LVD_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DT_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void PPG_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void USB0_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void USB1_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
**===========================================================================
|
||||||
|
** Interrupt Vector Table
|
||||||
|
**===========================================================================
|
||||||
|
*/
|
||||||
|
void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = {
|
||||||
|
/* Processor exceptions */
|
||||||
|
(void (*)(void))&_estack, /* 0 - Stack pointer */
|
||||||
|
Reset_Handler, /* 1 - Reset */
|
||||||
|
NMI_Handler, /* 2 - NMI */
|
||||||
|
HardFault_Handler, /* 3 - Hard fault */
|
||||||
|
MemManage_Handler, /* 4 - Memory management fault */
|
||||||
|
BusFault_Handler, /* 5 - Bus fault */
|
||||||
|
UsageFault_Handler, /* 6 - Usage fault */
|
||||||
|
0, /* 7 - Reserved */
|
||||||
|
0, /* 8 - Reserved */
|
||||||
|
0, /* 9 - Reserved */
|
||||||
|
0, /* 10 - Reserved */
|
||||||
|
SVC_Handler, /* 11 - SVCall */
|
||||||
|
DebugMonitor_Handler, /* 12 - Reserved for Debug */
|
||||||
|
0, /* 13 - Reserved */
|
||||||
|
PendSV_Handler, /* 14 - PendSV */
|
||||||
|
SysTick_Handler, /* 15 - Systick */
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
CSV_Handler, /* 0: Clock Super Visor */
|
||||||
|
SWDT_Handler, /* 1: Software Watchdog Timer */
|
||||||
|
LVD_Handler, /* 2: Low Voltage Detector */
|
||||||
|
MFT_WG_IRQHandler, /* 3: Wave Form Generator / DTIF */
|
||||||
|
INT0_7_Handler, /* 4: External Interrupt Request ch.0 to ch.7 */
|
||||||
|
INT8_31_Handler, /* 5: External Interrupt Request ch.8 to ch.31 */
|
||||||
|
DT_Handler, /* 6: Dual Timer / Quad Decoder */
|
||||||
|
MFS0RX_IRQHandler, /* 7: MultiFunction Serial ch.0 */
|
||||||
|
MFS0TX_IRQHandler, /* 8: MultiFunction Serial ch.0 */
|
||||||
|
MFS1RX_IRQHandler, /* 9: MultiFunction Serial ch.1 */
|
||||||
|
MFS1TX_IRQHandler, /* 10: MultiFunction Serial ch.1 */
|
||||||
|
MFS2RX_IRQHandler, /* 11: MultiFunction Serial ch.2 */
|
||||||
|
MFS2TX_IRQHandler, /* 12: MultiFunction Serial ch.2 */
|
||||||
|
MFS3RX_IRQHandler, /* 13: MultiFunction Serial ch.3 */
|
||||||
|
MFS3TX_IRQHandler, /* 14: MultiFunction Serial ch.3 */
|
||||||
|
MFS4RX_IRQHandler, /* 15: MultiFunction Serial ch.4 */
|
||||||
|
MFS4TX_IRQHandler, /* 16: MultiFunction Serial ch.4 */
|
||||||
|
MFS5RX_IRQHandler, /* 17: MultiFunction Serial ch.5 */
|
||||||
|
MFS5TX_IRQHandler, /* 18: MultiFunction Serial ch.5 */
|
||||||
|
MFS6RX_IRQHandler, /* 19: MultiFunction Serial ch.6 */
|
||||||
|
MFS6TX_IRQHandler, /* 20: MultiFunction Serial ch.6 */
|
||||||
|
MFS7RX_IRQHandler, /* 21: MultiFunction Serial ch.7 */
|
||||||
|
MFS7TX_IRQHandler, /* 22: MultiFunction Serial ch.7 */
|
||||||
|
PPG_Handler, /* 23: PPG */
|
||||||
|
TIM_IRQHandler, /* 24: OSC / PLL / Watch Counter */
|
||||||
|
ADC0_IRQHandler, /* 25: ADC0 */
|
||||||
|
ADC1_IRQHandler, /* 26: ADC1 */
|
||||||
|
ADC2_IRQHandler, /* 27: ADC2 */
|
||||||
|
MFT_FRT_IRQHandler, /* 28: Free-run Timer */
|
||||||
|
MFT_IPC_IRQHandler, /* 29: Input Capture */
|
||||||
|
MFT_OPC_IRQHandler, /* 30: Output Compare */
|
||||||
|
BT0_7_IRQHandler, /* 31: Base Timer ch.0 to ch.7 */
|
||||||
|
ETHER_MAC0_IRQHandler, /* 32: Ethernet MAC ch.0 */
|
||||||
|
ETHER_MAC1_IRQHandler, /* 33: Ethernet MAC ch.1 */
|
||||||
|
USB0F_Handler, /* 34: USB0 Function */
|
||||||
|
USB0_Handler, /* 35: USB0 Function / USB0 HOST */
|
||||||
|
USB1F_Handler, /* 36: USB1 Function */
|
||||||
|
USB1_Handler, /* 37: USB1 Function / USB1 HOST */
|
||||||
|
DMAC0_Handler, /* 38: DMAC ch.0 */
|
||||||
|
DMAC1_Handler, /* 39: DMAC ch.1 */
|
||||||
|
DMAC2_Handler, /* 40: DMAC ch.2 */
|
||||||
|
DMAC3_Handler, /* 41: DMAC ch.3 */
|
||||||
|
DMAC4_Handler, /* 42: DMAC ch.4 */
|
||||||
|
DMAC5_Handler, /* 43: DMAC ch.5 */
|
||||||
|
DMAC6_Handler, /* 44: DMAC ch.6 */
|
||||||
|
DMAC7_Handler, /* 45: DMAC ch.7 */
|
||||||
|
BT8_15_IRQHandler, /* 46: Base Timer ch.8 to ch.15 */
|
||||||
|
Default_Handler /* 47: Reserved */
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,417 @@
|
||||||
|
;/************************************************************************/
|
||||||
|
;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
|
||||||
|
;/* */
|
||||||
|
;/* The following software deliverable is intended for and must only be */
|
||||||
|
;/* used for reference and in an evaluation laboratory environment. */
|
||||||
|
;/* It is provided on an as-is basis without charge and is subject to */
|
||||||
|
;/* alterations. */
|
||||||
|
;/* It is the user's obligation to fully test the software in its */
|
||||||
|
;/* environment and to ensure proper functionality, qualification and */
|
||||||
|
;/* compliance with component specifications. */
|
||||||
|
;/* */
|
||||||
|
;/* In the event the software deliverable includes the use of open */
|
||||||
|
;/* source components, the provisions of the governing open source */
|
||||||
|
;/* license agreement shall apply with respect to such software */
|
||||||
|
;/* deliverable. */
|
||||||
|
;/* FSEU does not warrant that the deliverables do not infringe any */
|
||||||
|
;/* third party intellectual property right (IPR). In the event that */
|
||||||
|
;/* the deliverables infringe a third party IPR it is the sole */
|
||||||
|
;/* responsibility of the customer to obtain necessary licenses to */
|
||||||
|
;/* continue the usage of the deliverable. */
|
||||||
|
;/* */
|
||||||
|
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
|
||||||
|
;/* warranties, whether express or implied, in particular, but not */
|
||||||
|
;/* limited to, warranties of merchantability and fitness for a */
|
||||||
|
;/* particular purpose for which the deliverable is not designated. */
|
||||||
|
;/* */
|
||||||
|
;/* To the maximum extent permitted by applicable law, FSEU's liability */
|
||||||
|
;/* is restricted to intentional misconduct and gross negligence. */
|
||||||
|
;/* FSEU is not liable for consequential damages. */
|
||||||
|
;/* */
|
||||||
|
;/* (V1.5) */
|
||||||
|
;/************************************************************************/
|
||||||
|
;/* Startup for IAR */
|
||||||
|
;/* Version V1.00 */
|
||||||
|
;/* Date 2011-07-25 */
|
||||||
|
;/* Target-mcu MB9B610 */
|
||||||
|
;/************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table DCD sfe(CSTACK) ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset
|
||||||
|
DCD NMI_Handler ; NMI
|
||||||
|
DCD HardFault_Handler ; Hard Fault
|
||||||
|
DCD MemManage_Handler ; MPU Fault
|
||||||
|
DCD BusFault_Handler ; Bus Fault
|
||||||
|
DCD UsageFault_Handler ; Usage Fault
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV
|
||||||
|
DCD SysTick_Handler ; SysTick
|
||||||
|
|
||||||
|
DCD CSV_Handler ; 0: Clock Super Visor
|
||||||
|
DCD SWDT_Handler ; 1: Software Watchdog Timer
|
||||||
|
DCD LVD_Handler ; 2: Low Voltage Detector
|
||||||
|
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
|
||||||
|
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
|
||||||
|
DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31
|
||||||
|
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
|
||||||
|
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
|
||||||
|
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
|
||||||
|
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
|
||||||
|
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
|
||||||
|
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
|
||||||
|
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
|
||||||
|
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
|
||||||
|
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
|
||||||
|
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
|
||||||
|
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
|
||||||
|
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
|
||||||
|
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
|
||||||
|
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
|
||||||
|
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
|
||||||
|
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
|
||||||
|
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
|
||||||
|
DCD PPG_Handler ; 23: PPG
|
||||||
|
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
|
||||||
|
DCD ADC0_IRQHandler ; 25: ADC0
|
||||||
|
DCD ADC1_IRQHandler ; 26: ADC1
|
||||||
|
DCD ADC2_IRQHandler ; 27: ADC2
|
||||||
|
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
|
||||||
|
DCD MFT_IPC_IRQHandler ; 29: Input Capture
|
||||||
|
DCD MFT_OPC_IRQHandler ; 30: Output Compare
|
||||||
|
DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7
|
||||||
|
DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0
|
||||||
|
DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1
|
||||||
|
DCD USB0F_Handler ; 34: USB0 Function
|
||||||
|
DCD USB0_Handler ; 35: USB0 Function / USB0 HOST
|
||||||
|
DCD USB1F_Handler ; 36: USB1 Function
|
||||||
|
DCD USB1_Handler ; 37: USB1 Function / USB1 HOST
|
||||||
|
DCD DMAC0_Handler ; 38: DMAC ch.0
|
||||||
|
DCD DMAC1_Handler ; 39: DMAC ch.1
|
||||||
|
DCD DMAC2_Handler ; 40: DMAC ch.2
|
||||||
|
DCD DMAC3_Handler ; 41: DMAC ch.3
|
||||||
|
DCD DMAC4_Handler ; 42: DMAC ch.4
|
||||||
|
DCD DMAC5_Handler ; 43: DMAC ch.5
|
||||||
|
DCD DMAC6_Handler ; 44: DMAC ch.6
|
||||||
|
DCD DMAC7_Handler ; 45: DMAC ch.7
|
||||||
|
DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15
|
||||||
|
DCD DummyHandler ; 47: Reserved
|
||||||
|
|
||||||
|
THUMB
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
PUBWEAK CSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CSV_Handler
|
||||||
|
B CSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SWDT_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SWDT_Handler
|
||||||
|
B SWDT_Handler
|
||||||
|
|
||||||
|
PUBWEAK LVD_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
LVD_Handler
|
||||||
|
B LVD_Handler
|
||||||
|
|
||||||
|
PUBWEAK MFT_WG_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFT_WG_IRQHandler
|
||||||
|
B MFT_WG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK INT0_7_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
INT0_7_Handler
|
||||||
|
B INT0_7_Handler
|
||||||
|
|
||||||
|
PUBWEAK INT8_31_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
INT8_31_Handler
|
||||||
|
B INT8_31_Handler
|
||||||
|
|
||||||
|
PUBWEAK DT_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DT_Handler
|
||||||
|
B DT_Handler
|
||||||
|
|
||||||
|
PUBWEAK MFS0RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS0RX_IRQHandler
|
||||||
|
B MFS0RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS0TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS0TX_IRQHandler
|
||||||
|
B MFS0TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS1RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS1RX_IRQHandler
|
||||||
|
B MFS1RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS1TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS1TX_IRQHandler
|
||||||
|
B MFS1TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS2RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS2RX_IRQHandler
|
||||||
|
B MFS2RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS2TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS2TX_IRQHandler
|
||||||
|
B MFS2TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS3RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS3RX_IRQHandler
|
||||||
|
B MFS3RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS3TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS3TX_IRQHandler
|
||||||
|
B MFS3TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS4RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS4RX_IRQHandler
|
||||||
|
B MFS4RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS4TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS4TX_IRQHandler
|
||||||
|
B MFS4TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS5RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS5RX_IRQHandler
|
||||||
|
B MFS5RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS5TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS5TX_IRQHandler
|
||||||
|
B MFS5TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS6RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS6RX_IRQHandler
|
||||||
|
B MFS6RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS6TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS6TX_IRQHandler
|
||||||
|
B MFS6TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS7RX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS7RX_IRQHandler
|
||||||
|
B MFS7RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFS7TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFS7TX_IRQHandler
|
||||||
|
B MFS7TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PPG_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PPG_Handler
|
||||||
|
B PPG_Handler
|
||||||
|
|
||||||
|
PUBWEAK TIM_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM_IRQHandler
|
||||||
|
B TIM_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC0_IRQHandler
|
||||||
|
B ADC0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC1_IRQHandler
|
||||||
|
B ADC1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC2_IRQHandler
|
||||||
|
B ADC2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFT_FRT_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFT_FRT_IRQHandler
|
||||||
|
B MFT_FRT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFT_IPC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFT_IPC_IRQHandler
|
||||||
|
B MFT_IPC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MFT_OPC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MFT_OPC_IRQHandler
|
||||||
|
B MFT_OPC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BT0_7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BT0_7_IRQHandler
|
||||||
|
B BT0_7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETHER_MAC0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ETHER_MAC0_IRQHandler
|
||||||
|
B ETHER_MAC0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETHER_MAC1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ETHER_MAC1_IRQHandler
|
||||||
|
B ETHER_MAC1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USB0F_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB0F_Handler
|
||||||
|
B USB0F_Handler
|
||||||
|
|
||||||
|
PUBWEAK USB0_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB0_Handler
|
||||||
|
B USB0_Handler
|
||||||
|
|
||||||
|
PUBWEAK USB1F_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB1F_Handler
|
||||||
|
B USB1F_Handler
|
||||||
|
|
||||||
|
PUBWEAK USB1_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB1_Handler
|
||||||
|
B USB1_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC0_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC0_Handler
|
||||||
|
B DMAC0_Handler
|
||||||
|
|
||||||
|
|
||||||
|
PUBWEAK DMAC1_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC1_Handler
|
||||||
|
B DMAC1_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC2_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC2_Handler
|
||||||
|
B DMAC2_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC3_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC3_Handler
|
||||||
|
B DMAC3_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC4_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC4_Handler
|
||||||
|
B DMAC4_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC5_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC5_Handler
|
||||||
|
B DMAC5_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC6_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC6_Handler
|
||||||
|
B DMAC6_Handler
|
||||||
|
|
||||||
|
PUBWEAK DMAC7_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMAC7_Handler
|
||||||
|
B DMAC7_Handler
|
||||||
|
|
||||||
|
PUBWEAK BT8_15_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BT8_15_IRQHandler
|
||||||
|
B BT8_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DummyHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DummyHandler
|
||||||
|
B DummyHandler
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,206 @@
|
||||||
|
/************************************************************************/
|
||||||
|
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
|
||||||
|
/* */
|
||||||
|
/* The following software deliverable is intended for and must only be */
|
||||||
|
/* used for reference and in an evaluation laboratory environment. */
|
||||||
|
/* It is provided on an as-is basis without charge and is subject to */
|
||||||
|
/* alterations. */
|
||||||
|
/* It is the user's obligation to fully test the software in its */
|
||||||
|
/* environment and to ensure proper functionality, qualification and */
|
||||||
|
/* compliance with component specifications. */
|
||||||
|
/* */
|
||||||
|
/* In the event the software deliverable includes the use of open */
|
||||||
|
/* source components, the provisions of the governing open source */
|
||||||
|
/* license agreement shall apply with respect to such software */
|
||||||
|
/* deliverable. */
|
||||||
|
/* FSEU does not warrant that the deliverables do not infringe any */
|
||||||
|
/* third party intellectual property right (IPR). In the event that */
|
||||||
|
/* the deliverables infringe a third party IPR it is the sole */
|
||||||
|
/* responsibility of the customer to obtain necessary licenses to */
|
||||||
|
/* continue the usage of the deliverable. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law FSEU disclaims all */
|
||||||
|
/* warranties, whether express or implied, in particular, but not */
|
||||||
|
/* limited to, warranties of merchantability and fitness for a */
|
||||||
|
/* particular purpose for which the deliverable is not designated. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law, FSEU's liability */
|
||||||
|
/* is restricted to intentional misconduct and gross negligence. */
|
||||||
|
/* FSEU is not liable for consequential damages. */
|
||||||
|
/* */
|
||||||
|
/* (V1.5) */
|
||||||
|
/************************************************************************/
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
/** \file system_mb9bf61x.c
|
||||||
|
**
|
||||||
|
** FM3 system initialization functions
|
||||||
|
** All adjustments can be done in belonging header file.
|
||||||
|
**
|
||||||
|
** History:
|
||||||
|
** 2011-07-07 V1.0 MWi original version
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** System Clock Frequency (Core Clock) Variable according CMSIS
|
||||||
|
******************************************************************************/
|
||||||
|
uint32_t SystemCoreClock = __HCLK;
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Update the System Core Clock with current core Clock retrieved from
|
||||||
|
** cpu registers.
|
||||||
|
** \param none
|
||||||
|
** \return none
|
||||||
|
******************************************************************************/
|
||||||
|
void SystemCoreClockUpdate (void) {
|
||||||
|
uint32_t masterClk;
|
||||||
|
uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
|
||||||
|
|
||||||
|
switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
|
||||||
|
case 0: /* internal High-speed Cr osc. */
|
||||||
|
masterClk = __CLKHC;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1: /* external main osc. */
|
||||||
|
masterClk = __CLKMO;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2: /* PLL clock */
|
||||||
|
// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
|
||||||
|
// violation:
|
||||||
|
// "Unordered accesses to a volatile location"
|
||||||
|
u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
|
||||||
|
masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4: /* internal Low-speed CR osc. */
|
||||||
|
masterClk = __CLKLC;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 5: /* external Sub osc. */
|
||||||
|
masterClk = __CLKSO;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
masterClk = 0Ul;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (FM3_CRG->BSC_PSR & 0x07) {
|
||||||
|
case 0:
|
||||||
|
SystemCoreClock = masterClk;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
SystemCoreClock = masterClk / 2;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
SystemCoreClock = masterClk / 3;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3:
|
||||||
|
SystemCoreClock = masterClk / 4;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
SystemCoreClock = masterClk / 6;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 5:
|
||||||
|
SystemCoreClock = masterClk /8;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 6:
|
||||||
|
SystemCoreClock = masterClk /16;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
SystemCoreClock = 0Ul;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Setup the microcontroller system. Initialize the System and update
|
||||||
|
** the SystemCoreClock variable.
|
||||||
|
**
|
||||||
|
** \param none
|
||||||
|
** \return none
|
||||||
|
******************************************************************************/
|
||||||
|
void SystemInit (void) {
|
||||||
|
|
||||||
|
static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance
|
||||||
|
|
||||||
|
#if (HWWD_DISABLE) /* HW Watchdog Disable */
|
||||||
|
FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
|
||||||
|
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
|
||||||
|
FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CLOCK_SETUP) /* Clock Setup */
|
||||||
|
FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
|
||||||
|
FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
|
||||||
|
FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
|
||||||
|
FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
|
||||||
|
FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
|
||||||
|
FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
|
||||||
|
|
||||||
|
FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
|
||||||
|
|
||||||
|
if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
|
||||||
|
FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
|
||||||
|
while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
|
||||||
|
FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
|
||||||
|
while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
|
||||||
|
}
|
||||||
|
|
||||||
|
FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
|
||||||
|
FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
|
||||||
|
FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
|
||||||
|
|
||||||
|
if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
|
||||||
|
FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
|
||||||
|
while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
|
||||||
|
}
|
||||||
|
|
||||||
|
FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
|
||||||
|
|
||||||
|
{
|
||||||
|
volatile unsigned int i;
|
||||||
|
for(i=0;i<200000;i++);
|
||||||
|
}
|
||||||
|
// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
|
||||||
|
// violations:
|
||||||
|
// "Unordered reads and writes to or from same location" and
|
||||||
|
// "Unordered accesses to a volatile location"
|
||||||
|
do
|
||||||
|
{
|
||||||
|
u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
|
||||||
|
}while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
|
||||||
|
#endif // (CLOCK_SETUP)
|
||||||
|
|
||||||
|
#if (CR_TRIM_SETUP)
|
||||||
|
/* CR Trimming Data */
|
||||||
|
if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
|
||||||
|
{
|
||||||
|
/* UnLock (MCR_FTRM) */
|
||||||
|
FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
|
||||||
|
/* Set MCR_FTRM */
|
||||||
|
FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
|
||||||
|
/* Lock (MCR_FTRM) */
|
||||||
|
FM3_CRTRIM->MCR_RLR = 0x00000000;
|
||||||
|
}
|
||||||
|
#endif // (CR_TRIM_SETUP)
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,678 @@
|
||||||
|
/************************************************************************/
|
||||||
|
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
|
||||||
|
/* */
|
||||||
|
/* The following software deliverable is intended for and must only be */
|
||||||
|
/* used for reference and in an evaluation laboratory environment. */
|
||||||
|
/* It is provided on an as-is basis without charge and is subject to */
|
||||||
|
/* alterations. */
|
||||||
|
/* It is the user's obligation to fully test the software in its */
|
||||||
|
/* environment and to ensure proper functionality, qualification and */
|
||||||
|
/* compliance with component specifications. */
|
||||||
|
/* */
|
||||||
|
/* In the event the software deliverable includes the use of open */
|
||||||
|
/* source components, the provisions of the governing open source */
|
||||||
|
/* license agreement shall apply with respect to such software */
|
||||||
|
/* deliverable. */
|
||||||
|
/* FSEU does not warrant that the deliverables do not infringe any */
|
||||||
|
/* third party intellectual property right (IPR). In the event that */
|
||||||
|
/* the deliverables infringe a third party IPR it is the sole */
|
||||||
|
/* responsibility of the customer to obtain necessary licenses to */
|
||||||
|
/* continue the usage of the deliverable. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law FSEU disclaims all */
|
||||||
|
/* warranties, whether express or implied, in particular, but not */
|
||||||
|
/* limited to, warranties of merchantability and fitness for a */
|
||||||
|
/* particular purpose for which the deliverable is not designated. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law, FSEU's liability */
|
||||||
|
/* is restricted to intentional misconduct and gross negligence. */
|
||||||
|
/* FSEU is not liable for consequential damages. */
|
||||||
|
/* */
|
||||||
|
/* (V1.5) */
|
||||||
|
/************************************************************************/
|
||||||
|
/** \file system_mb9bf61x.h
|
||||||
|
**
|
||||||
|
** Headerfile for FM3 system parameters
|
||||||
|
**
|
||||||
|
** User clock definitions can be done for the following clock settings:
|
||||||
|
** - CLOCK_SETUP : Execute the clock settings form the settings below in
|
||||||
|
** SystemInit()
|
||||||
|
** - __CLKMO : External clock frequency for main oscillion
|
||||||
|
** - __CLKSO : External clock frequency for sub oscillion
|
||||||
|
** - SCM_CTL : System Clock Mode Control Register
|
||||||
|
** - BSC_PSR : Base Clock Prescaler Register
|
||||||
|
** - APBC0_PSR : APB0 Prescaler Register
|
||||||
|
** - APBC1_PSR : APB1 Prescaler Register
|
||||||
|
** - APBC2_PSR : APB2 Prescaler Register
|
||||||
|
** - SWC_PSR : Software Watchdog Clock Prescaler Register
|
||||||
|
** - TTC_PSR : Trace Clock Prescaler Register
|
||||||
|
** - CSW_TMR : Clock Stabilization Wait Time Register
|
||||||
|
** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
|
||||||
|
** - PLL_CTL1 : PLL Control Register 1
|
||||||
|
** - PLL_CTL2 : PLL Control Register 2
|
||||||
|
**
|
||||||
|
** The register settings are check for correct values of reserved bits.
|
||||||
|
** Otherwise a preprocessor error is output and stops the build process.
|
||||||
|
** Furthermore the 'master clock' is retrieved from the register settings
|
||||||
|
** and the system clock (HCLK) is calculated from the Base Clock Prescaler
|
||||||
|
** Register (BSC_PSR). This value is used for the global CMSIS variable
|
||||||
|
** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
|
||||||
|
** is checked. Note that not all possible wrong setting are checked! The
|
||||||
|
** user has to take care to fulfill the settings stated in the according
|
||||||
|
** device's data sheet!
|
||||||
|
**
|
||||||
|
** User definition for Hardware Watchdog:
|
||||||
|
** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
|
||||||
|
**
|
||||||
|
** User definition for CR Trimming:
|
||||||
|
** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
|
||||||
|
**
|
||||||
|
** History:
|
||||||
|
** 2011-05-16 V1.0 MWi original version
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _SYSTEM_MB9BF61X_H_
|
||||||
|
#define _SYSTEM_MB9BF61X_H_
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Include files */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Global pre-processor symbols/macros ('define') */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* */
|
||||||
|
/* START OF USER SETTINGS HERE */
|
||||||
|
/* =========================== */
|
||||||
|
/* */
|
||||||
|
/* All lines with '<<<' can be set by user. */
|
||||||
|
/* */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Clock Setup Enable
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** - 0 = No clock setup done by system_mb9xfxxx.c
|
||||||
|
** - 1 = Clock setup done by system_mb9xfxxx.c
|
||||||
|
******************************************************************************/
|
||||||
|
#define CLOCK_SETUP 1 // <<< Define clock setup here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief External Main Clock Frequency (in Hz, [value]UL)
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief External Sub Clock Frequency (in Hz, [value]UL)
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief System Clock Mode Control Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** SCM_CTL
|
||||||
|
**
|
||||||
|
** Bit#7-5 : RCS[2:0]
|
||||||
|
** - 0 = Internal high-speed CR oscillation (default)
|
||||||
|
** - 1 = Main oscillation clock
|
||||||
|
** - 2 = PLL oscillation clock
|
||||||
|
** - 3 = (not allowed)
|
||||||
|
** - 4 = Internal low-speed CR oscillation
|
||||||
|
** - 5 = Sub clock oscillation
|
||||||
|
** - 6 = (not allowed)
|
||||||
|
** - 7 = (not allowed)
|
||||||
|
**
|
||||||
|
** Bit#4 : PLLE
|
||||||
|
** - 0 = Disable PLL (default)
|
||||||
|
** - 1 = Enable PLL
|
||||||
|
**
|
||||||
|
** Bit#3 : SOSCE
|
||||||
|
** - 0 = Disable sub oscillation (default)
|
||||||
|
** - 1 = Enable sub oscillation
|
||||||
|
**
|
||||||
|
** Bit#2 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#1 : MOSCE
|
||||||
|
** - 0 = Disable main oscillation (default)
|
||||||
|
** - 1 = Enable main oscillation
|
||||||
|
**
|
||||||
|
** Bit#0 : (reserved)
|
||||||
|
******************************************************************************/
|
||||||
|
#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Base Clock Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** BSC_PSR
|
||||||
|
**
|
||||||
|
** Bit#7-3 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#2-0 : BSR[2:0]
|
||||||
|
** - 0 = HCLK = Master Clock
|
||||||
|
** - 1 = HCLK = Master Clock / 2
|
||||||
|
** - 2 = HCLK = Master Clock / 3
|
||||||
|
** - 3 = HCLK = Master Clock / 4
|
||||||
|
** - 4 = HCLK = Master Clock / 6
|
||||||
|
** - 5 = HCLK = Master Clock / 8
|
||||||
|
** - 6 = HCLK = Master Clock / 16
|
||||||
|
** - 7 = (reserved)
|
||||||
|
******************************************************************************/
|
||||||
|
#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief APB0 Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** APBC0_PSR
|
||||||
|
**
|
||||||
|
** Bit#7-2 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#1-0 : BSR[2:0]
|
||||||
|
** - 0 = PCLK0 = HCLK
|
||||||
|
** - 1 = PCLK0 = HCLK / 2
|
||||||
|
** - 2 = PCLK0 = HCLK / 4
|
||||||
|
** - 3 = PCLK0 = HCLK / 8
|
||||||
|
******************************************************************************/
|
||||||
|
#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief APB1 Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** APBC1_PSR
|
||||||
|
**
|
||||||
|
** Bit#7 : APBC1EN
|
||||||
|
** - 0 = Disable PCLK1 output
|
||||||
|
** - 1 = Enables PCLK1 (default)
|
||||||
|
**
|
||||||
|
** Bit#6-5 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#4 : APBC1RST
|
||||||
|
** - 0 = APB1 bus reset, inactive (default)
|
||||||
|
** - 1 = APB1 bus reset, active
|
||||||
|
**
|
||||||
|
** Bit#3-2 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#1-0 : APBC1[2:0]
|
||||||
|
** - 0 = PCLK1 = HCLK
|
||||||
|
** - 1 = PCLK1 = HCLK / 2
|
||||||
|
** - 2 = PCLK1 = HCLK / 4
|
||||||
|
** - 3 = PCLK1 = HCLK / 8
|
||||||
|
******************************************************************************/
|
||||||
|
#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief APB2 Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** APBC2_PSR
|
||||||
|
**
|
||||||
|
** Bit#7 : APBC2EN
|
||||||
|
** - 0 = Disable PCLK2 output
|
||||||
|
** - 1 = Enables PCLK2 (default)
|
||||||
|
**
|
||||||
|
** Bit#6-5 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#4 : APBC2RST
|
||||||
|
** - 0 = APB2 bus reset, inactive (default)
|
||||||
|
** - 1 = APB2 bus reset, active
|
||||||
|
**
|
||||||
|
** Bit#3-2 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#1-0 : APBC2[1:0]
|
||||||
|
** - 0 = PCLK2 = HCLK
|
||||||
|
** - 1 = PCLK2 = HCLK / 2
|
||||||
|
** - 2 = PCLK2 = HCLK / 4
|
||||||
|
** - 3 = PCLK2 = HCLK / 8
|
||||||
|
******************************************************************************/
|
||||||
|
#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Software Watchdog Clock Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** SWC_PSR
|
||||||
|
**
|
||||||
|
** Bit#7 : TESTB
|
||||||
|
** - 0 = (not allowed)
|
||||||
|
** - 1 = (always write "1" to this bit)
|
||||||
|
**
|
||||||
|
** Bit#6-2 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#1-0 : SWDS[2:0]
|
||||||
|
** - 0 = SWDGOGCLK = PCLK0
|
||||||
|
** - 1 = SWDGOGCLK = PCLK0 / 2
|
||||||
|
** - 2 = SWDGOGCLK = PCLK0 / 4
|
||||||
|
** - 3 = SWDGOGCLK = PCLK0 / 8
|
||||||
|
******************************************************************************/
|
||||||
|
#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Trace Clock Prescaler Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** TTC_PSR
|
||||||
|
**
|
||||||
|
** Bit#7-1 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#0 : TTC
|
||||||
|
** - 0 = TPIUCLK = HCLK
|
||||||
|
** - 1 = TPIUCLK = HCLK / 2
|
||||||
|
******************************************************************************/
|
||||||
|
#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Clock Stabilization Wait Time Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** CSW_TMR
|
||||||
|
**
|
||||||
|
** Bit#7 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#6-4 : SOWT[2:0]
|
||||||
|
** - 0 = ~10.3 ms (default)
|
||||||
|
** - 1 = ~20.5 ms
|
||||||
|
** - 2 = ~41 ms
|
||||||
|
** - 3 = ~82 ms
|
||||||
|
** - 4 = ~164 ms
|
||||||
|
** - 5 = ~327 ms
|
||||||
|
** - 6 = ~655 ms
|
||||||
|
** - 7 = ~1.31 s
|
||||||
|
**
|
||||||
|
** Bit#3-0 : MOWT[3:0]
|
||||||
|
** - 0 = ~500 ns (default)
|
||||||
|
** - 1 = ~8 us
|
||||||
|
** - 2 = ~16 us
|
||||||
|
** - 3 = ~32 us
|
||||||
|
** - 4 = ~64 us
|
||||||
|
** - 5 = ~128 us
|
||||||
|
** - 6 = ~256 us
|
||||||
|
** - 7 = ~512 us
|
||||||
|
** - 8 = ~1.0 ms
|
||||||
|
** - 9 = ~2.0 ms
|
||||||
|
** - 10 = ~4.0 ms
|
||||||
|
** - 11 = ~8.0 ms
|
||||||
|
** - 12 = ~33.0 ms
|
||||||
|
** - 13 = ~131 ms
|
||||||
|
** - 14 = ~524 ms
|
||||||
|
** - 15 = ~2.0 s
|
||||||
|
******************************************************************************/
|
||||||
|
#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief PLL Clock Stabilization Wait Time Setup Register value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** PSW_TMR
|
||||||
|
**
|
||||||
|
** Bit#7-5 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#4 : PINC
|
||||||
|
** - 0 = Selects CLKMO (main oscillation) (default)
|
||||||
|
** - 1 = (setting diabled)
|
||||||
|
**
|
||||||
|
** Bit#3 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#2-0 : POWT[2:0]
|
||||||
|
** - 0 = ~128 us (default)
|
||||||
|
** - 1 = ~256 us
|
||||||
|
** - 2 = ~512 us
|
||||||
|
** - 3 = ~1.02 ms
|
||||||
|
** - 4 = ~2.05 ms
|
||||||
|
** - 5 = ~4.10 ms
|
||||||
|
** - 6 = ~8.20 ms
|
||||||
|
** - 7 = ~16.40 ms
|
||||||
|
******************************************************************************/
|
||||||
|
#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief PLL Control Register 1 value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** PLL_CTL1
|
||||||
|
**
|
||||||
|
** Bit#7-4 : PLLK[3:0]
|
||||||
|
** - 0 = Division(PLLK) = 1/1 (default)
|
||||||
|
** - 1 = Division(PLLK) = 1/2
|
||||||
|
** - 2 = Division(PLLK) = 1/3
|
||||||
|
** - . . .
|
||||||
|
** - 15 = Division(PLLK) = 1/16
|
||||||
|
**
|
||||||
|
** Bit#3-0 : PLLM[3:0]
|
||||||
|
** - 0 = Division(PLLM) = 1/1 (default)
|
||||||
|
** - 1 = Division(PLLM) = 1/2
|
||||||
|
** - 2 = Division(PLLM) = 1/3
|
||||||
|
** - . . .
|
||||||
|
** - 15 = Division(PLLM) = 1/16
|
||||||
|
******************************************************************************/
|
||||||
|
#define PLL_CTL1_Val 0x00000001 // <<< Define PLL_CTL1 here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief PLL Control Register 2 value definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** PLL_CTL2
|
||||||
|
**
|
||||||
|
** Bit#7-6 : (reserved)
|
||||||
|
**
|
||||||
|
** Bit#5-0 : PLLN[5:0]
|
||||||
|
** - 0 = Division(PLLN) = 1/1 (default)
|
||||||
|
** - 1 = Division(PLLN) = 1/2
|
||||||
|
** - 2 = Division(PLLN) = 1/3
|
||||||
|
** - . . .
|
||||||
|
** - 63 = Division(PLLN) = 1/64
|
||||||
|
******************************************************************************/
|
||||||
|
#define PLL_CTL2_Val 0x00000023 // <<< Define PLL_CTL2 here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Hardware Watchdog disable definition
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** - 0 = Hardware Watchdog enable
|
||||||
|
** - 1 = Hardware Watchdog disable
|
||||||
|
******************************************************************************/
|
||||||
|
#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Trimming CR
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
**
|
||||||
|
** - 0 = CR is not trimmed at startup
|
||||||
|
** - 1 = CR is trimmed at startup
|
||||||
|
******************************************************************************/
|
||||||
|
#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here
|
||||||
|
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* */
|
||||||
|
/* END OF USER SETTINGS HERE */
|
||||||
|
/* ========================= */
|
||||||
|
/* */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Device dependent System Clock absolute maximum ranges */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
|
||||||
|
** <i>(USER SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKMOMIN ( 4000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Maximum Main Clock frequency using external clock
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKMOMAX ( 50000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Any case minimum Sub Clock frequency
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKSOMIN ( 32000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Maximum Sub Clock frequency using external clock
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __CLKSOMAX ( 100000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Absolute minimum PLL input frequency
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLCLKINMIN ( 4000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Absolute maximum PLL input frequency
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLCLKINMAX ( 16000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Absolute minimum PLL oscillation frequency
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLCLKMIN (200000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Absolute maximum PLL oscillation frequency
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLCLKMAX (300000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Absolute maximum System Clock frequency (HCLK)
|
||||||
|
** <i>(DEVICE DEPENDENT SETTING)</i>
|
||||||
|
******************************************************************************/
|
||||||
|
#define __HCLKMAX (144000000UL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Preprocessor macro for checking range (clock settings)
|
||||||
|
******************************************************************************/
|
||||||
|
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Preprocessor macro for checking bits with mask (clock settings)
|
||||||
|
******************************************************************************/
|
||||||
|
#define CHECK_RSVD(val, mask) (val & mask)
|
||||||
|
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Check register settings */
|
||||||
|
/******************************************************************************/
|
||||||
|
#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
|
||||||
|
#error "SCM_CTL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
|
||||||
|
#error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
|
||||||
|
#error "CSW_TMR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
|
||||||
|
#if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
|
||||||
|
#error "PSW_TMR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
|
||||||
|
#error "PLL_CTL1: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
|
||||||
|
#error "PLL_CTL2: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
|
||||||
|
#error "BSC_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
|
||||||
|
#error "APBC0_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
|
||||||
|
#error "APBC1_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
|
||||||
|
#error "APBC2_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
|
||||||
|
#error "SWC_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
|
||||||
|
#error "TTC_PSR: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Define clocks with checking settings */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Calculate PLL K factor from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Calculate PLL N factor from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLN (((PLL_CTL2_Val ) & 0x3F) + 1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Calculate PLL M factor from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Calculate PLL output frequency from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Determine core clock frequency according to settings */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Define Master Clock from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
|
||||||
|
#define __MASTERCLK (__CLKHC)
|
||||||
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
|
||||||
|
#define __MASTERCLK (__CLKMO)
|
||||||
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
|
||||||
|
#define __MASTERCLK (__PLLCLK)
|
||||||
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
|
||||||
|
#define __MASTERCLK (__CLKLC)
|
||||||
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
|
||||||
|
#define __MASTERCLK (__CLKSO)
|
||||||
|
#else
|
||||||
|
#define __MASTERCLK (0UL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
** \brief Define System Clock Frequency (Core Clock) from settings
|
||||||
|
******************************************************************************/
|
||||||
|
#if ((BSC_PSR_Val & 0x07) == 0)
|
||||||
|
#define __HCLK (__MASTERCLK / 1)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 1)
|
||||||
|
#define __HCLK (__MASTERCLK / 2)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 2)
|
||||||
|
#define __HCLK (__MASTERCLK / 3)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 3)
|
||||||
|
#define __HCLK (__MASTERCLK / 4)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 4)
|
||||||
|
#define __HCLK (__MASTERCLK / 6)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 5)
|
||||||
|
#define __HCLK (__MASTERCLK / 8)
|
||||||
|
#elif ((BSC_PSR_Val & 0x07) == 6)
|
||||||
|
#define __HCLK (__MASTERCLK /16)
|
||||||
|
#else
|
||||||
|
#define __HCLK (0UL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* HCLK range check */
|
||||||
|
/******************************************************************************/
|
||||||
|
#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
|
||||||
|
#error "Main Oscillator Clock (CLKMO) out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
|
||||||
|
#error "Sub Oscillator Clock (CLKMO) out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
|
||||||
|
#error "PLL input frequency out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
|
||||||
|
#error "PLL oscillation frequency out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
|
||||||
|
#error "System Clock (HCLK) out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Global function prototypes ('extern', definition in C source) */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
|
||||||
|
|
||||||
|
extern void SystemInit (void); // Initialize the system
|
||||||
|
|
||||||
|
extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __SYSTEM_MB9BF61X_H */
|
||||||
|
|
@ -0,0 +1,93 @@
|
||||||
|
/* ----------------------------------------------------------------------
|
||||||
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* $Date: 17. January 2013
|
||||||
|
* $Revision: V1.4.1
|
||||||
|
*
|
||||||
|
* Project: CMSIS DSP Library
|
||||||
|
* Title: arm_common_tables.h
|
||||||
|
*
|
||||||
|
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||||
|
*
|
||||||
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* - Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
#ifndef _ARM_COMMON_TABLES_H
|
||||||
|
#define _ARM_COMMON_TABLES_H
|
||||||
|
|
||||||
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
extern const uint16_t armBitRevTable[1024];
|
||||||
|
extern const q15_t armRecipTableQ15[64];
|
||||||
|
extern const q31_t armRecipTableQ31[64];
|
||||||
|
extern const q31_t realCoefAQ31[1024];
|
||||||
|
extern const q31_t realCoefBQ31[1024];
|
||||||
|
extern const float32_t twiddleCoef_16[32];
|
||||||
|
extern const float32_t twiddleCoef_32[64];
|
||||||
|
extern const float32_t twiddleCoef_64[128];
|
||||||
|
extern const float32_t twiddleCoef_128[256];
|
||||||
|
extern const float32_t twiddleCoef_256[512];
|
||||||
|
extern const float32_t twiddleCoef_512[1024];
|
||||||
|
extern const float32_t twiddleCoef_1024[2048];
|
||||||
|
extern const float32_t twiddleCoef_2048[4096];
|
||||||
|
extern const float32_t twiddleCoef_4096[8192];
|
||||||
|
#define twiddleCoef twiddleCoef_4096
|
||||||
|
extern const q31_t twiddleCoefQ31[6144];
|
||||||
|
extern const q15_t twiddleCoefQ15[6144];
|
||||||
|
extern const float32_t twiddleCoef_rfft_32[32];
|
||||||
|
extern const float32_t twiddleCoef_rfft_64[64];
|
||||||
|
extern const float32_t twiddleCoef_rfft_128[128];
|
||||||
|
extern const float32_t twiddleCoef_rfft_256[256];
|
||||||
|
extern const float32_t twiddleCoef_rfft_512[512];
|
||||||
|
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||||
|
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||||
|
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||||
|
|
||||||
|
|
||||||
|
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||||
|
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||||
|
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||||
|
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||||
|
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||||
|
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||||
|
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||||
|
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||||
|
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||||
|
|
||||||
|
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||||
|
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||||
|
|
||||||
|
#endif /* ARM_COMMON_TABLES_H */
|
||||||
|
|
@ -0,0 +1,85 @@
|
||||||
|
/* ----------------------------------------------------------------------
|
||||||
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* $Date: 17. January 2013
|
||||||
|
* $Revision: V1.4.1
|
||||||
|
*
|
||||||
|
* Project: CMSIS DSP Library
|
||||||
|
* Title: arm_const_structs.h
|
||||||
|
*
|
||||||
|
* Description: This file has constant structs that are initialized for
|
||||||
|
* user convenience. For example, some can be given as
|
||||||
|
* arguments to the arm_cfft_f32() function.
|
||||||
|
*
|
||||||
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* - Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
#ifndef _ARM_CONST_STRUCTS_H
|
||||||
|
#define _ARM_CONST_STRUCTS_H
|
||||||
|
|
||||||
|
#include "arm_math.h"
|
||||||
|
#include "arm_common_tables.h"
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
|
||||||
|
16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
|
||||||
|
32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
|
||||||
|
64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
|
||||||
|
128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
|
||||||
|
256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
|
||||||
|
512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
|
||||||
|
1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
|
||||||
|
2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
|
||||||
|
4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,682 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm0.h
|
||||||
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 25. February 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_GENERIC
|
||||||
|
#define __CORE_CM0_H_GENERIC
|
||||||
|
|
||||||
|
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \ingroup Cortex_M0
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CMSIS CM0 definitions */
|
||||||
|
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
|
||||||
|
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h> /* standard types definitions */
|
||||||
|
#include <core_cmInstr.h> /* Core Instruction Access */
|
||||||
|
#include <core_cmFunc.h> /* Core Function Access */
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_DEPENDANT
|
||||||
|
#define __CORE_CM0_H_DEPENDANT
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM0_REV
|
||||||
|
#define __CM0_REV 0x0000
|
||||||
|
#warning "__CM0_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M0 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||||
|
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31];
|
||||||
|
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31];
|
||||||
|
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31];
|
||||||
|
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31];
|
||||||
|
uint32_t RESERVED4[64];
|
||||||
|
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
||||||
|
are only accessible over DAP and not via processor. Therefore
|
||||||
|
they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Cortex-M0 Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
|
||||||
|
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
|
||||||
|
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Enable External Interrupt
|
||||||
|
|
||||||
|
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable External Interrupt
|
||||||
|
|
||||||
|
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Pending Interrupt
|
||||||
|
|
||||||
|
The function reads the pending register in the NVIC and returns the pending bit
|
||||||
|
for the specified interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Pending Interrupt
|
||||||
|
|
||||||
|
The function sets the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Clear Pending Interrupt
|
||||||
|
|
||||||
|
The function clears the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Interrupt Priority
|
||||||
|
|
||||||
|
The function sets the priority of an interrupt.
|
||||||
|
|
||||||
|
\note The priority cannot be set for every core interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if(IRQn < 0) {
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
else {
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Interrupt Priority
|
||||||
|
|
||||||
|
The function reads the priority of an interrupt. The interrupt
|
||||||
|
number can be positive to specify an external (device specific)
|
||||||
|
interrupt, or negative to specify an internal (core) interrupt.
|
||||||
|
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority. Value is aligned automatically to the implemented
|
||||||
|
priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(IRQn < 0) {
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
|
||||||
|
else {
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief System Reset
|
||||||
|
|
||||||
|
The function initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
while(1); /* wait until reset */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (__Vendor_SysTickConfig == 0)
|
||||||
|
|
||||||
|
/** \brief System Tick Configuration
|
||||||
|
|
||||||
|
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||||
|
|
||||||
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,793 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm0plus.h
|
||||||
|
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 25. February 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||||
|
#define __CORE_CM0PLUS_H_GENERIC
|
||||||
|
|
||||||
|
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \ingroup Cortex-M0+
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CMSIS CM0P definitions */
|
||||||
|
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
|
||||||
|
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h> /* standard types definitions */
|
||||||
|
#include <core_cmInstr.h> /* Core Instruction Access */
|
||||||
|
#include <core_cmFunc.h> /* Core Function Access */
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||||
|
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM0PLUS_REV
|
||||||
|
#define __CM0PLUS_REV 0x0000
|
||||||
|
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __MPU_PRESENT
|
||||||
|
#define __MPU_PRESENT 0
|
||||||
|
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VTOR_PRESENT
|
||||||
|
#define __VTOR_PRESENT 0
|
||||||
|
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex-M0+ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
- Core MPU Register
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||||
|
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31];
|
||||||
|
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31];
|
||||||
|
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31];
|
||||||
|
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31];
|
||||||
|
uint32_t RESERVED4[64];
|
||||||
|
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
#if (__VTOR_PRESENT == 1)
|
||||||
|
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||||
|
#else
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
#endif
|
||||||
|
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
#if (__VTOR_PRESENT == 1)
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
|
||||||
|
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the Memory Protection Unit (MPU).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||||
|
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||||
|
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||||
|
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||||
|
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||||
|
} MPU_Type;
|
||||||
|
|
||||||
|
/* MPU Type Register */
|
||||||
|
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
||||||
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
|
||||||
|
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
||||||
|
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||||
|
|
||||||
|
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
||||||
|
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
|
||||||
|
|
||||||
|
/* MPU Control Register */
|
||||||
|
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
||||||
|
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||||
|
|
||||||
|
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
||||||
|
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||||
|
|
||||||
|
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
||||||
|
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* MPU Region Number Register */
|
||||||
|
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
||||||
|
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
|
||||||
|
|
||||||
|
/* MPU Region Base Address Register */
|
||||||
|
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
|
||||||
|
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||||
|
|
||||||
|
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
||||||
|
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||||
|
|
||||||
|
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
||||||
|
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
|
||||||
|
|
||||||
|
/* MPU Region Attribute and Size Register */
|
||||||
|
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
||||||
|
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
||||||
|
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
||||||
|
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
||||||
|
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
||||||
|
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
||||||
|
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
||||||
|
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
||||||
|
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
||||||
|
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
||||||
|
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_MPU */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
||||||
|
are only accessible over DAP and not via processor. Therefore
|
||||||
|
they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Cortex-M0+ Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
|
||||||
|
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
|
||||||
|
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Enable External Interrupt
|
||||||
|
|
||||||
|
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable External Interrupt
|
||||||
|
|
||||||
|
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Pending Interrupt
|
||||||
|
|
||||||
|
The function reads the pending register in the NVIC and returns the pending bit
|
||||||
|
for the specified interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Pending Interrupt
|
||||||
|
|
||||||
|
The function sets the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Clear Pending Interrupt
|
||||||
|
|
||||||
|
The function clears the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Interrupt Priority
|
||||||
|
|
||||||
|
The function sets the priority of an interrupt.
|
||||||
|
|
||||||
|
\note The priority cannot be set for every core interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if(IRQn < 0) {
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
else {
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Interrupt Priority
|
||||||
|
|
||||||
|
The function reads the priority of an interrupt. The interrupt
|
||||||
|
number can be positive to specify an external (device specific)
|
||||||
|
interrupt, or negative to specify an internal (core) interrupt.
|
||||||
|
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority. Value is aligned automatically to the implemented
|
||||||
|
priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(IRQn < 0) {
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
|
||||||
|
else {
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief System Reset
|
||||||
|
|
||||||
|
The function initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
while(1); /* wait until reset */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (__Vendor_SysTickConfig == 0)
|
||||||
|
|
||||||
|
/** \brief System Tick Configuration
|
||||||
|
|
||||||
|
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||||
|
|
||||||
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,673 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm4_simd.h
|
||||||
|
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 25. February 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM4_SIMD_H
|
||||||
|
#define __CORE_CM4_SIMD_H
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32) ) >> 32))
|
||||||
|
|
||||||
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __SSAT16(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __USAT16(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __SMLALD(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||||
|
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||||
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __SMLALDX(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||||
|
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||||
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __SMLSLD(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||||
|
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||||
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __SMLSLDX(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||||
|
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||||
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||||
|
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||||
|
if (ARG3 == 0) \
|
||||||
|
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||||
|
else \
|
||||||
|
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
|
||||||
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
/* not yet supported */
|
||||||
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_CM4_SIMD_H */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,636 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cmFunc.h
|
||||||
|
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 25. February 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CORE_CMFUNC_H
|
||||||
|
#define __CORE_CMFUNC_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/** \brief Get Control Register
|
||||||
|
|
||||||
|
This function returns the content of the Control Register.
|
||||||
|
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Control Register
|
||||||
|
|
||||||
|
This function writes the given value to the Control Register.
|
||||||
|
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get IPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the IPSR Register.
|
||||||
|
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get APSR Register
|
||||||
|
|
||||||
|
This function returns the content of the APSR Register.
|
||||||
|
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get xPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the xPSR Register.
|
||||||
|
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Process Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Process Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Main Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Main Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Priority Mask
|
||||||
|
|
||||||
|
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Priority Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Priority Mask Register.
|
||||||
|
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Enable FIQ
|
||||||
|
|
||||||
|
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable FIQ
|
||||||
|
|
||||||
|
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Base Priority
|
||||||
|
|
||||||
|
This function returns the current value of the Base Priority register.
|
||||||
|
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Base Priority
|
||||||
|
|
||||||
|
This function assigns the given value to the Base Priority register.
|
||||||
|
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xff);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Fault Mask
|
||||||
|
|
||||||
|
This function returns the current value of the Fault Mask register.
|
||||||
|
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Fault Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Fault Mask register.
|
||||||
|
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
This function returns the current value of the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set FPSCR
|
||||||
|
|
||||||
|
This function assigns the given value to the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/** \brief Enable IRQ Interrupts
|
||||||
|
|
||||||
|
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsie i" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable IRQ Interrupts
|
||||||
|
|
||||||
|
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsid i" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Control Register
|
||||||
|
|
||||||
|
This function returns the content of the Control Register.
|
||||||
|
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Control Register
|
||||||
|
|
||||||
|
This function writes the given value to the Control Register.
|
||||||
|
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get IPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the IPSR Register.
|
||||||
|
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get APSR Register
|
||||||
|
|
||||||
|
This function returns the content of the APSR Register.
|
||||||
|
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get xPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the xPSR Register.
|
||||||
|
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Process Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Process Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Main Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Main Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Priority Mask
|
||||||
|
|
||||||
|
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Priority Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Priority Mask Register.
|
||||||
|
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Enable FIQ
|
||||||
|
|
||||||
|
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsie f" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable FIQ
|
||||||
|
|
||||||
|
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsid f" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Base Priority
|
||||||
|
|
||||||
|
This function returns the current value of the Base Priority register.
|
||||||
|
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Base Priority
|
||||||
|
|
||||||
|
This function assigns the given value to the Base Priority register.
|
||||||
|
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Fault Mask
|
||||||
|
|
||||||
|
This function returns the current value of the Fault Mask register.
|
||||||
|
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Fault Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Fault Mask register.
|
||||||
|
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
This function returns the current value of the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
/* Empty asm statement works as a scheduling barrier */
|
||||||
|
__ASM volatile ("");
|
||||||
|
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||||
|
__ASM volatile ("");
|
||||||
|
return(result);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set FPSCR
|
||||||
|
|
||||||
|
This function assigns the given value to the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
/* Empty asm statement works as a scheduling barrier */
|
||||||
|
__ASM volatile ("");
|
||||||
|
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||||
|
__ASM volatile ("");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_CMFUNC_H */
|
||||||
|
|
@ -0,0 +1,688 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cmInstr.h
|
||||||
|
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 05. March 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CORE_CMINSTR_H
|
||||||
|
#define __CORE_CMINSTR_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief No Operation
|
||||||
|
|
||||||
|
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Interrupt
|
||||||
|
|
||||||
|
Wait For Interrupt is a hint instruction that suspends execution
|
||||||
|
until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Event
|
||||||
|
|
||||||
|
Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Send Event
|
||||||
|
|
||||||
|
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Instruction Synchronization Barrier
|
||||||
|
|
||||||
|
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or
|
||||||
|
memory, after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() __isb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Synchronization Barrier
|
||||||
|
|
||||||
|
This function acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() __dsb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Memory Barrier
|
||||||
|
|
||||||
|
This function ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() __dmb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (32 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in integer value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (16 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in two unsigned short values.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** \brief Reverse byte order in signed short value
|
||||||
|
|
||||||
|
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||||||
|
|
||||||
|
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\param [in] value Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Breakpoint
|
||||||
|
|
||||||
|
This function causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __breakpoint(value)
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
This function reverses the bit order of the given value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __RBIT __rbit
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Remove the exclusive lock
|
||||||
|
|
||||||
|
This function removes the exclusive lock which is created by LDREX.
|
||||||
|
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Signed Saturate
|
||||||
|
|
||||||
|
This function saturates a signed value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Unsigned Saturate
|
||||||
|
|
||||||
|
This function saturates an unsigned value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
|
This function counts the number of leading zeros of a data value.
|
||||||
|
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/* Define macros for porting to both thumb1 and thumb2.
|
||||||
|
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||||
|
* Otherwise, use general registers, specified by constrant "r" */
|
||||||
|
#if defined (__thumb__) && !defined (__thumb2__)
|
||||||
|
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||||
|
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||||
|
#else
|
||||||
|
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||||
|
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** \brief No Operation
|
||||||
|
|
||||||
|
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("nop");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Interrupt
|
||||||
|
|
||||||
|
Wait For Interrupt is a hint instruction that suspends execution
|
||||||
|
until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Event
|
||||||
|
|
||||||
|
Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("wfe");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Send Event
|
||||||
|
|
||||||
|
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("sev");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Instruction Synchronization Barrier
|
||||||
|
|
||||||
|
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or
|
||||||
|
memory, after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("isb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Synchronization Barrier
|
||||||
|
|
||||||
|
This function acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("dsb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Memory Barrier
|
||||||
|
|
||||||
|
This function ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("dmb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (32 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in integer value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||||
|
return __builtin_bswap32(value);
|
||||||
|
#else
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||||
|
return(result);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (16 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in two unsigned short values.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order in signed short value
|
||||||
|
|
||||||
|
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||||
|
{
|
||||||
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||||
|
return (short)__builtin_bswap16(value);
|
||||||
|
#else
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||||
|
return(result);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||||||
|
|
||||||
|
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\param [in] value Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << (32 - op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Breakpoint
|
||||||
|
|
||||||
|
This function causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
This function reverses the bit order of the given value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||||
|
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||||
|
#else
|
||||||
|
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||||
|
accepted by assembler. So has to use following less efficient pattern.
|
||||||
|
*/
|
||||||
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||||
|
#endif
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||||
|
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||||
|
#else
|
||||||
|
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||||
|
accepted by assembler. So has to use following less efficient pattern.
|
||||||
|
*/
|
||||||
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||||
|
#endif
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Remove the exclusive lock
|
||||||
|
|
||||||
|
This function removes the exclusive lock which is created by LDREX.
|
||||||
|
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("clrex" ::: "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Signed Saturate
|
||||||
|
|
||||||
|
This function saturates a signed value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Unsigned Saturate
|
||||||
|
|
||||||
|
This function saturates an unsigned value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
|
This function counts the number of leading zeros of a data value.
|
||||||
|
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
#endif /* __CORE_CMINSTR_H */
|
||||||
|
|
@ -0,0 +1,813 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_sc000.h
|
||||||
|
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||||
|
* @version V3.20
|
||||||
|
* @date 25. February 2013
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2013 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_SC000_H_GENERIC
|
||||||
|
#define __CORE_SC000_H_GENERIC
|
||||||
|
|
||||||
|
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \ingroup SC000
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CMSIS SC000 definitions */
|
||||||
|
#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
|
||||||
|
#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
|
||||||
|
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
|
||||||
|
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_SC (0) /*!< Cortex secure core */
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h> /* standard types definitions */
|
||||||
|
#include <core_cmInstr.h> /* Core Instruction Access */
|
||||||
|
#include <core_cmFunc.h> /* Core Function Access */
|
||||||
|
|
||||||
|
#endif /* __CORE_SC000_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_SC000_H_DEPENDANT
|
||||||
|
#define __CORE_SC000_H_DEPENDANT
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __SC000_REV
|
||||||
|
#define __SC000_REV 0x0000
|
||||||
|
#warning "__SC000_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __MPU_PRESENT
|
||||||
|
#define __MPU_PRESENT 0
|
||||||
|
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/*@} end of group SC000 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
- Core MPU Register
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
#if (__CORTEX_M != 0x04)
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
#else
|
||||||
|
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||||
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
|
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||||
|
#endif
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||||
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||||
|
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31];
|
||||||
|
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31];
|
||||||
|
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31];
|
||||||
|
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31];
|
||||||
|
uint32_t RESERVED4[64];
|
||||||
|
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||||
|
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED0[1];
|
||||||
|
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
uint32_t RESERVED1[154];
|
||||||
|
__IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
||||||
|
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/* SCB Security Features Register Definitions */
|
||||||
|
#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
|
||||||
|
#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
|
||||||
|
|
||||||
|
#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
|
||||||
|
#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2];
|
||||||
|
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
|
||||||
|
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** \brief Structure type to access the Memory Protection Unit (MPU).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||||
|
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||||
|
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||||
|
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||||
|
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||||
|
} MPU_Type;
|
||||||
|
|
||||||
|
/* MPU Type Register */
|
||||||
|
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
||||||
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
|
||||||
|
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
||||||
|
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||||
|
|
||||||
|
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
||||||
|
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
|
||||||
|
|
||||||
|
/* MPU Control Register */
|
||||||
|
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
||||||
|
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||||
|
|
||||||
|
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
||||||
|
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||||
|
|
||||||
|
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
||||||
|
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* MPU Region Number Register */
|
||||||
|
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
||||||
|
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
|
||||||
|
|
||||||
|
/* MPU Region Base Address Register */
|
||||||
|
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
|
||||||
|
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||||
|
|
||||||
|
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
||||||
|
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||||
|
|
||||||
|
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
||||||
|
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
|
||||||
|
|
||||||
|
/* MPU Region Attribute and Size Register */
|
||||||
|
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
||||||
|
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
||||||
|
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
||||||
|
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
||||||
|
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
||||||
|
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
||||||
|
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
||||||
|
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
||||||
|
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
||||||
|
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||||
|
|
||||||
|
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
||||||
|
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_MPU */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
||||||
|
are only accessible over DAP and not via processor. Therefore
|
||||||
|
they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/** \ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of SC000 Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
|
||||||
|
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
|
||||||
|
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Enable External Interrupt
|
||||||
|
|
||||||
|
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable External Interrupt
|
||||||
|
|
||||||
|
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Pending Interrupt
|
||||||
|
|
||||||
|
The function reads the pending register in the NVIC and returns the pending bit
|
||||||
|
for the specified interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Pending Interrupt
|
||||||
|
|
||||||
|
The function sets the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Clear Pending Interrupt
|
||||||
|
|
||||||
|
The function clears the pending bit of an external interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Interrupt Priority
|
||||||
|
|
||||||
|
The function sets the priority of an interrupt.
|
||||||
|
|
||||||
|
\note The priority cannot be set for every core interrupt.
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if(IRQn < 0) {
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
else {
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Interrupt Priority
|
||||||
|
|
||||||
|
The function reads the priority of an interrupt. The interrupt
|
||||||
|
number can be positive to specify an external (device specific)
|
||||||
|
interrupt, or negative to specify an internal (core) interrupt.
|
||||||
|
|
||||||
|
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority. Value is aligned automatically to the implemented
|
||||||
|
priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(IRQn < 0) {
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
|
||||||
|
else {
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief System Reset
|
||||||
|
|
||||||
|
The function initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
while(1); /* wait until reset */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (__Vendor_SysTickConfig == 0)
|
||||||
|
|
||||||
|
/** \brief System Tick Configuration
|
||||||
|
|
||||||
|
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||||
|
|
||||||
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_SC000_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,37 @@
|
||||||
|
* -------------------------------------------------------------------
|
||||||
|
* Copyright (C) 2011-2013 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* Date: 18 March 2013
|
||||||
|
* Revision: V3.20
|
||||||
|
*
|
||||||
|
* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
|
||||||
|
* Title: Release Note for CMSIS
|
||||||
|
*
|
||||||
|
* -------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
NOTE - Open the index.html file to access CMSIS documentation
|
||||||
|
|
||||||
|
|
||||||
|
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
|
||||||
|
Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
|
||||||
|
and reduces time-to-market for new embedded applications.
|
||||||
|
|
||||||
|
CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
|
||||||
|
Any user of the software package is bound to the terms and conditions of the end user license agreement.
|
||||||
|
|
||||||
|
|
||||||
|
You will find the following sub-directories:
|
||||||
|
|
||||||
|
Documentation - Contains CMSIS documentation.
|
||||||
|
|
||||||
|
DSP_Lib - MDK project files, Examples and source files etc.. to build the
|
||||||
|
CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
|
||||||
|
|
||||||
|
Include - CMSIS Core Support and CMSIS DSP Include Files.
|
||||||
|
|
||||||
|
Lib - CMSIS DSP Libraries.
|
||||||
|
|
||||||
|
RTOS - CMSIS RTOS API template header file.
|
||||||
|
|
||||||
|
SVD - CMSIS SVD Schema files and Conversion Utility.
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
Import('rtconfig')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c')
|
||||||
|
|
||||||
|
CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/']
|
||||||
|
|
||||||
|
# add for startup script
|
||||||
|
if rtconfig.CROSS_TOOL == 'gcc':
|
||||||
|
src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c']
|
||||||
|
elif rtconfig.CROSS_TOOL == 'keil':
|
||||||
|
src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S']
|
||||||
|
elif rtconfig.CROSS_TOOL == 'iar':
|
||||||
|
src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S']
|
||||||
|
|
||||||
|
CPPDEFINES = [rtconfig.FM3_TYPE]
|
||||||
|
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||||
|
|
||||||
|
Return('group')
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
# for module compiling
|
||||||
|
import os
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
|
||||||
|
cwd = str(Dir('#'))
|
||||||
|
objs = []
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
|
||||||
|
for d in list:
|
||||||
|
path = os.path.join(cwd, d)
|
||||||
|
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||||
|
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||||
|
|
||||||
|
Return('objs')
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
import rtconfig
|
||||||
|
|
||||||
|
if os.getenv('RTT_ROOT'):
|
||||||
|
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||||
|
else:
|
||||||
|
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
|
||||||
|
|
||||||
|
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||||
|
|
||||||
|
env = Environment(tools = ['mingw'],
|
||||||
|
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||||
|
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||||
|
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||||
|
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||||
|
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM == 'iar':
|
||||||
|
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||||
|
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
|
||||||
|
env.Replace(ARFLAGS = '')
|
||||||
|
|
||||||
|
Export('RTT_ROOT')
|
||||||
|
Export('rtconfig')
|
||||||
|
|
||||||
|
# prepare building environment
|
||||||
|
objs = PrepareBuilding(env, RTT_ROOT)
|
||||||
|
|
||||||
|
# make a building
|
||||||
|
DoBuilding(TARGET, objs)
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
Import('rtconfig')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||||
|
src = Glob('*.c')
|
||||||
|
CPPPATH = [cwd, str(Dir('#'))]
|
||||||
|
|
||||||
|
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
Return('group')
|
||||||
|
|
@ -0,0 +1,58 @@
|
||||||
|
/*
|
||||||
|
* File : application.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-05-24 Bernard the first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
#include <components.h>
|
||||||
|
#endif /* RT_USING_COMPONENTS_INIT */
|
||||||
|
|
||||||
|
void rt_init_thread_entry(void *parameter)
|
||||||
|
{
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
/* initialization RT-Thread Components */
|
||||||
|
rt_components_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_FINSH
|
||||||
|
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||||
|
#endif /* RT_USING_FINSH */
|
||||||
|
|
||||||
|
/**< init led device */
|
||||||
|
{
|
||||||
|
extern void rt_led_hw_init(void);
|
||||||
|
rt_led_hw_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
int rt_application_init()
|
||||||
|
{
|
||||||
|
rt_thread_t tid;
|
||||||
|
|
||||||
|
tid = rt_thread_create("init",
|
||||||
|
rt_init_thread_entry, RT_NULL,
|
||||||
|
2048, 8, 20);
|
||||||
|
if (tid != RT_NULL) rt_thread_startup(tid);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,88 @@
|
||||||
|
/*
|
||||||
|
* File : startup.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-24 Bernard first implementation
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
extern int rt_application_init(void);
|
||||||
|
|
||||||
|
#ifdef __CC_ARM
|
||||||
|
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
#elif __ICCARM__
|
||||||
|
#pragma section="HEAP"
|
||||||
|
#else
|
||||||
|
extern int __bss_end;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will startup RT-Thread RTOS.
|
||||||
|
*/
|
||||||
|
void rtthread_startup(void)
|
||||||
|
{
|
||||||
|
/* init board */
|
||||||
|
rt_hw_board_init();
|
||||||
|
|
||||||
|
/* show version */
|
||||||
|
rt_show_version();
|
||||||
|
|
||||||
|
#ifdef RT_USING_HEAP
|
||||||
|
#ifdef __CC_ARM
|
||||||
|
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
|
||||||
|
#elif __ICCARM__
|
||||||
|
rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
|
||||||
|
#else
|
||||||
|
/* init memory system */
|
||||||
|
rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* init scheduler system */
|
||||||
|
rt_system_scheduler_init();
|
||||||
|
|
||||||
|
/* init timer thread */
|
||||||
|
rt_system_timer_thread_init();
|
||||||
|
|
||||||
|
/* init application */
|
||||||
|
rt_application_init();
|
||||||
|
|
||||||
|
/* init idle thread */
|
||||||
|
rt_thread_idle_init();
|
||||||
|
|
||||||
|
/* start scheduler */
|
||||||
|
rt_system_scheduler_start();
|
||||||
|
|
||||||
|
/* never reach here */
|
||||||
|
return ;
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
/* disable interrupt first */
|
||||||
|
rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
/* startup RT-Thread RTOS */
|
||||||
|
rtthread_startup();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
Import('rtconfig')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = os.path.join(str(Dir('#')), 'drivers')
|
||||||
|
src = Glob('*.c')
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
|
||||||
|
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
Return('group')
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
/*
|
||||||
|
* File : board.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-24 Bernard first implementation
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
#include "serial.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
#include <components.h>
|
||||||
|
#endif /* RT_USING_COMPONENTS_INIT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This is the timer interrupt service routine.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
rt_tick_increase();
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This fucntion returns milliseconds since system passed
|
||||||
|
*/
|
||||||
|
rt_uint32_t rt_hw_tick_get_millisecond(void)
|
||||||
|
{
|
||||||
|
rt_tick_t tick;
|
||||||
|
rt_uint32_t value;
|
||||||
|
|
||||||
|
#define TICK_MS (1000/RT_TICK_PER_SECOND)
|
||||||
|
|
||||||
|
tick = rt_tick_get();
|
||||||
|
value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD;
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This fucntion returns microseconds since system passed
|
||||||
|
*/
|
||||||
|
rt_uint32_t rt_hw_tick_get_microsecond(void)
|
||||||
|
{
|
||||||
|
rt_tick_t tick;
|
||||||
|
rt_uint32_t value;
|
||||||
|
|
||||||
|
#define TICK_US (1000000/RT_TICK_PER_SECOND)
|
||||||
|
|
||||||
|
tick = rt_tick_get();
|
||||||
|
value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initial FM3 Easy Kit board.
|
||||||
|
*/
|
||||||
|
void rt_hw_board_init(void)
|
||||||
|
{
|
||||||
|
/* disable all analog input. */
|
||||||
|
FM3_GPIO->ADE = 0;
|
||||||
|
|
||||||
|
/* init systick */
|
||||||
|
SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
|
||||||
|
|
||||||
|
/* initialize UART device */
|
||||||
|
rt_hw_serial_init();
|
||||||
|
/* set console as UART device */
|
||||||
|
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||||
|
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
rt_components_board_init();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* File : board.h
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2009-09-22 Bernard add board.h to this bsp
|
||||||
|
* 2011-03-04 lgnq add board.h to FM3 bsp
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __BOARD_H__
|
||||||
|
#define __BOARD_H__
|
||||||
|
|
||||||
|
#if defined MB9B610S
|
||||||
|
# include <mb9b610s.h>
|
||||||
|
#elif defined MB9B610T
|
||||||
|
# include <mb9b610t.h>
|
||||||
|
#else
|
||||||
|
# warning "you must define CPU type. e.g: MB9B610S or MB9B610T"
|
||||||
|
# warning "define MB9B610S default"
|
||||||
|
# define MB9B610S /* default: MB9B610S */
|
||||||
|
# include <mb9b610s.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "serial.h"
|
||||||
|
|
||||||
|
//Internal SRAM memory size[Kbytes] <8-64>
|
||||||
|
//product MB9BFx16S/T MB9BFx17S/T MB9BFx18S/T
|
||||||
|
//FLASH : 512 768 1024
|
||||||
|
//SRAM0 : 32 48 64
|
||||||
|
//SRAM1 : 32 48 64
|
||||||
|
#define FM3_SRAM_SIZE 128
|
||||||
|
#define FM3_SRAM_END (0x1FFF0000 + FM3_SRAM_SIZE * 1024)
|
||||||
|
|
||||||
|
/* RT_USING_UART */
|
||||||
|
#define RT_USING_UART0
|
||||||
|
//#define RT_USING_UART2
|
||||||
|
//#define RT_USING_UART4
|
||||||
|
#define RT_UART_RX_BUFFER_SIZE 64
|
||||||
|
|
||||||
|
void rt_hw_board_init(void);
|
||||||
|
rt_uint32_t rt_hw_tick_get_millisecond(void);
|
||||||
|
rt_uint32_t rt_hw_tick_get_microsecond(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,157 @@
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */
|
||||||
|
|
||||||
|
#define LED_NUM 4
|
||||||
|
struct fm3_gpio_ctrl
|
||||||
|
{
|
||||||
|
uint32_t led_num;
|
||||||
|
volatile uint32_t * PDOR;
|
||||||
|
volatile uint32_t * PDIR;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct fm3_led
|
||||||
|
{
|
||||||
|
/* inherit from rt_device */
|
||||||
|
struct rt_device parent;
|
||||||
|
|
||||||
|
struct fm3_gpio_ctrl fm3_gpio_ctrl[LED_NUM];
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct fm3_led fm3_led;
|
||||||
|
|
||||||
|
static rt_err_t rt_led_init (rt_device_t dev)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
/* led0 : P54 */
|
||||||
|
FM3_GPIO->PFR5 &= ~((1<<7) | (1<<6) | (1<<5) |(1<<4)); /* set P54 fuction is GPIO. */
|
||||||
|
FM3_GPIO->DDR5 |= (1<<7) | (1<<6) | (1<<5) |(1<<4); /* set P54 output. */
|
||||||
|
|
||||||
|
/* LED0 */
|
||||||
|
i = 0;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].led_num = 4;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
|
||||||
|
|
||||||
|
/* LED1 */
|
||||||
|
i++;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].led_num = 5;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
|
||||||
|
|
||||||
|
/* LED2 */
|
||||||
|
i++;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].led_num = 6;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
|
||||||
|
|
||||||
|
/* LED3 */
|
||||||
|
i++;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].led_num = 7;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
|
||||||
|
fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
|
||||||
|
{
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_led_close(rt_device_t dev)
|
||||||
|
{
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer,
|
||||||
|
rt_size_t size)
|
||||||
|
{
|
||||||
|
rt_ubase_t index = 0;
|
||||||
|
rt_ubase_t nr = size;
|
||||||
|
rt_uint8_t * value = buffer;
|
||||||
|
|
||||||
|
RT_ASSERT(dev == &fm3_led.parent);
|
||||||
|
RT_ASSERT((pos+size) <= LED_NUM );
|
||||||
|
|
||||||
|
for(index=0; index<nr; index++)
|
||||||
|
{
|
||||||
|
if(*fm3_led.fm3_gpio_ctrl[pos+index].PDIR & 1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num)
|
||||||
|
{
|
||||||
|
*value = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*value = 1;
|
||||||
|
}
|
||||||
|
value++;
|
||||||
|
}
|
||||||
|
return index;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_led_write (rt_device_t dev, rt_off_t pos,
|
||||||
|
const void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
rt_ubase_t index = 0;
|
||||||
|
rt_ubase_t nw = size;
|
||||||
|
const rt_uint8_t * value = buffer;
|
||||||
|
|
||||||
|
RT_ASSERT(dev == &fm3_led.parent);
|
||||||
|
RT_ASSERT((pos+size) <= LED_NUM );
|
||||||
|
|
||||||
|
for(index=0; index<nw; index++)
|
||||||
|
{
|
||||||
|
if(*value++)
|
||||||
|
{
|
||||||
|
*fm3_led.fm3_gpio_ctrl[pos+index].PDOR &= ~(1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*fm3_led.fm3_gpio_ctrl[pos+index].PDOR |= (1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return index;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_led_control (rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||||
|
{
|
||||||
|
RT_ASSERT(dev == &fm3_led.parent);
|
||||||
|
|
||||||
|
if(cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
|
||||||
|
{
|
||||||
|
rt_uint32_t * led_num = args;
|
||||||
|
*led_num = LED_NUM;
|
||||||
|
}
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
void rt_led_hw_init(void)
|
||||||
|
{
|
||||||
|
fm3_led.parent.type = RT_Device_Class_Char;
|
||||||
|
fm3_led.parent.rx_indicate = RT_NULL;
|
||||||
|
fm3_led.parent.tx_complete = RT_NULL;
|
||||||
|
fm3_led.parent.init = rt_led_init;
|
||||||
|
fm3_led.parent.open = rt_led_open;
|
||||||
|
fm3_led.parent.close = rt_led_close;
|
||||||
|
fm3_led.parent.read = rt_led_read;
|
||||||
|
fm3_led.parent.write = rt_led_write;
|
||||||
|
fm3_led.parent.control = rt_led_control;
|
||||||
|
fm3_led.parent.user_data = RT_NULL;
|
||||||
|
|
||||||
|
/* register a character device */
|
||||||
|
rt_device_register(&fm3_led.parent, "led", RT_DEVICE_FLAG_RDWR);
|
||||||
|
/* init led device */
|
||||||
|
rt_led_init(&fm3_led.parent);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef RT_USING_FINSH
|
||||||
|
#include <finsh.h>
|
||||||
|
void led(rt_uint32_t led, rt_uint32_t value)
|
||||||
|
{
|
||||||
|
rt_uint8_t led_value = value;
|
||||||
|
rt_led_write(&fm3_led.parent, led, &led_value, 1);
|
||||||
|
}
|
||||||
|
FINSH_FUNCTION_EXPORT(led, e.g:led(0,100).)
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,437 @@
|
||||||
|
/*
|
||||||
|
* File : serial.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2006-03-13 Bernard first version
|
||||||
|
* 2011-05-15 lgnq modified according bernard's implementaion.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "serial.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3 MB9B610
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
/* RT-Thread Device Interface */
|
||||||
|
/**
|
||||||
|
* This function initializes serial
|
||||||
|
*/
|
||||||
|
static rt_err_t rt_serial_init (rt_device_t dev)
|
||||||
|
{
|
||||||
|
struct serial_device* uart = (struct serial_device*) dev->user_data;
|
||||||
|
|
||||||
|
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
|
||||||
|
{
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
|
{
|
||||||
|
rt_memset(uart->int_rx->rx_buffer, 0,
|
||||||
|
sizeof(uart->int_rx->rx_buffer));
|
||||||
|
uart->int_rx->read_index = uart->int_rx->save_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
|
||||||
|
{
|
||||||
|
rt_memset(uart->int_tx->tx_buffer, 0,
|
||||||
|
sizeof(uart->int_tx->tx_buffer));
|
||||||
|
uart->int_tx->write_index = uart->int_tx->save_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* save a char to serial buffer */
|
||||||
|
static void rt_serial_savechar(struct serial_device* uart, char ch)
|
||||||
|
{
|
||||||
|
rt_base_t level;
|
||||||
|
|
||||||
|
/* disable interrupt */
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
|
||||||
|
uart->int_rx->save_index ++;
|
||||||
|
if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
|
||||||
|
uart->int_rx->save_index = 0;
|
||||||
|
|
||||||
|
/* if the next position is read index, discard this 'read char' */
|
||||||
|
if (uart->int_rx->save_index == uart->int_rx->read_index)
|
||||||
|
{
|
||||||
|
uart->int_rx->read_index ++;
|
||||||
|
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
|
||||||
|
uart->int_rx->read_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable interrupt */
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
|
||||||
|
{
|
||||||
|
struct serial_device* uart;
|
||||||
|
|
||||||
|
RT_ASSERT(dev != RT_NULL);
|
||||||
|
uart = (struct serial_device*) dev->user_data;
|
||||||
|
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
|
{
|
||||||
|
/* enable interrupt */
|
||||||
|
UART_ENABLE_IRQ(uart->rx_irq);
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_serial_close(rt_device_t dev)
|
||||||
|
{
|
||||||
|
struct serial_device* uart;
|
||||||
|
|
||||||
|
RT_ASSERT(dev != RT_NULL);
|
||||||
|
uart = (struct serial_device*) dev->user_data;
|
||||||
|
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
|
{
|
||||||
|
/* disable interrupt */
|
||||||
|
UART_DISABLE_IRQ(uart->rx_irq);
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer,
|
||||||
|
rt_size_t size)
|
||||||
|
{
|
||||||
|
rt_uint8_t* ptr;
|
||||||
|
rt_err_t err_code;
|
||||||
|
struct serial_device* uart;
|
||||||
|
|
||||||
|
ptr = buffer;
|
||||||
|
err_code = RT_EOK;
|
||||||
|
uart = (struct serial_device*)dev->user_data;
|
||||||
|
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
|
{
|
||||||
|
rt_base_t level;
|
||||||
|
|
||||||
|
/* interrupt mode Rx */
|
||||||
|
while (size)
|
||||||
|
{
|
||||||
|
if (uart->int_rx->read_index != uart->int_rx->save_index)
|
||||||
|
{
|
||||||
|
*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
|
||||||
|
size --;
|
||||||
|
|
||||||
|
/* disable interrupt */
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
uart->int_rx->read_index ++;
|
||||||
|
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
|
||||||
|
uart->int_rx->read_index = 0;
|
||||||
|
|
||||||
|
/* enable interrupt */
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* set error code */
|
||||||
|
err_code = -RT_EEMPTY;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* polling mode */
|
||||||
|
while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
|
||||||
|
{
|
||||||
|
while (uart->uart_device->SSR & SSR_RDRF)
|
||||||
|
{
|
||||||
|
*ptr = uart->uart_device->RDR & 0xff;
|
||||||
|
ptr ++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set error code */
|
||||||
|
rt_set_errno(err_code);
|
||||||
|
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos,
|
||||||
|
const void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
rt_uint8_t* ptr;
|
||||||
|
rt_err_t err_code;
|
||||||
|
struct serial_device* uart;
|
||||||
|
|
||||||
|
err_code = RT_EOK;
|
||||||
|
ptr = (rt_uint8_t*)buffer;
|
||||||
|
uart = (struct serial_device*)dev->user_data;
|
||||||
|
|
||||||
|
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
|
||||||
|
{
|
||||||
|
/* interrupt mode Tx */
|
||||||
|
while (uart->int_tx->save_index != uart->int_tx->write_index)
|
||||||
|
{
|
||||||
|
/* save on tx buffer */
|
||||||
|
uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
|
||||||
|
|
||||||
|
-- size;
|
||||||
|
|
||||||
|
/* move to next position */
|
||||||
|
uart->int_tx->save_index ++;
|
||||||
|
|
||||||
|
/* wrap save index */
|
||||||
|
if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
|
||||||
|
uart->int_tx->save_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set error code */
|
||||||
|
if (size > 0)
|
||||||
|
err_code = -RT_EFULL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* polling mode */
|
||||||
|
while (size)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* to be polite with serial console add a line feed
|
||||||
|
* to the carriage return character
|
||||||
|
*/
|
||||||
|
if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
|
||||||
|
{
|
||||||
|
while (!(uart->uart_device->SSR & SSR_TDRE));
|
||||||
|
uart->uart_device->TDR = '\r';
|
||||||
|
}
|
||||||
|
|
||||||
|
while (!(uart->uart_device->SSR & SSR_TDRE));
|
||||||
|
uart->uart_device->TDR = (*ptr & 0x1FF);
|
||||||
|
|
||||||
|
++ptr;
|
||||||
|
--size;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set error code */
|
||||||
|
rt_set_errno(err_code);
|
||||||
|
|
||||||
|
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||||
|
{
|
||||||
|
RT_ASSERT(dev != RT_NULL);
|
||||||
|
|
||||||
|
switch (cmd)
|
||||||
|
{
|
||||||
|
case RT_DEVICE_CTRL_SUSPEND:
|
||||||
|
/* suspend device */
|
||||||
|
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case RT_DEVICE_CTRL_RESUME:
|
||||||
|
/* resume device */
|
||||||
|
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* serial register
|
||||||
|
*/
|
||||||
|
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
|
||||||
|
rt_uint32_t flag, struct serial_device *serial)
|
||||||
|
{
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
|
||||||
|
device->type = RT_Device_Class_Char;
|
||||||
|
device->rx_indicate = RT_NULL;
|
||||||
|
device->tx_complete = RT_NULL;
|
||||||
|
device->init = rt_serial_init;
|
||||||
|
device->open = rt_serial_open;
|
||||||
|
device->close = rt_serial_close;
|
||||||
|
device->read = rt_serial_read;
|
||||||
|
device->write = rt_serial_write;
|
||||||
|
device->control = rt_serial_control;
|
||||||
|
device->user_data = serial;
|
||||||
|
|
||||||
|
/* register a character device */
|
||||||
|
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ISR for serial interrupt */
|
||||||
|
void rt_hw_serial_isr(rt_device_t device)
|
||||||
|
{
|
||||||
|
struct serial_device* uart = (struct serial_device*) device->user_data;
|
||||||
|
|
||||||
|
/* interrupt mode receive */
|
||||||
|
RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
|
||||||
|
|
||||||
|
/* save on rx buffer */
|
||||||
|
while (uart->uart_device->SSR & SSR_RDRF)
|
||||||
|
{
|
||||||
|
rt_serial_savechar(uart, uart->uart_device->RDR & 0xff);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* invoke callback */
|
||||||
|
if (device->rx_indicate != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_size_t rx_length;
|
||||||
|
|
||||||
|
/* get rx length */
|
||||||
|
rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
|
||||||
|
UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
|
||||||
|
uart->int_rx->save_index - uart->int_rx->read_index;
|
||||||
|
|
||||||
|
device->rx_indicate(device, rx_length);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART0
|
||||||
|
/* UART0 device driver structure */
|
||||||
|
#define UART0 FM3_MFS0_UART
|
||||||
|
struct serial_int_rx uart0_int_rx;
|
||||||
|
struct serial_device uart0 =
|
||||||
|
{
|
||||||
|
UART0,
|
||||||
|
MFS0RX_IRQn,
|
||||||
|
MFS0TX_IRQn,
|
||||||
|
&uart0_int_rx,
|
||||||
|
RT_NULL
|
||||||
|
};
|
||||||
|
struct rt_device uart0_device;
|
||||||
|
|
||||||
|
void MFS0RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
rt_hw_serial_isr(&uart0_device);
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /**< #ifdef RT_USING_UART0 */
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART2
|
||||||
|
/* UART2 device driver structure */
|
||||||
|
#define UART2 FM3_MFS2_UART
|
||||||
|
struct serial_int_rx uart2_int_rx;
|
||||||
|
struct serial_device uart2 =
|
||||||
|
{
|
||||||
|
UART2,
|
||||||
|
MFS2RX_IRQn,
|
||||||
|
MFS2TX_IRQn,
|
||||||
|
&uart2_int_rx,
|
||||||
|
RT_NULL
|
||||||
|
};
|
||||||
|
struct rt_device uart2_device;
|
||||||
|
|
||||||
|
void MFS2RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
rt_hw_serial_isr(&uart2_device);
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /**< #ifdef RT_USING_UART2 */
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART4
|
||||||
|
/* UART4 device driver structure */
|
||||||
|
#define UART4 FM3_MFS4_UART
|
||||||
|
struct serial_int_rx uart4_int_rx;
|
||||||
|
struct serial_device uart4 =
|
||||||
|
{
|
||||||
|
(FM3_MFS03_UART_TypeDef*)UART4,
|
||||||
|
MFS4RX_IRQn,
|
||||||
|
MFS4TX_IRQn,
|
||||||
|
&uart4_int_rx,
|
||||||
|
RT_NULL
|
||||||
|
};
|
||||||
|
struct rt_device uart4_device;
|
||||||
|
|
||||||
|
void MFS4RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
rt_hw_serial_isr(&uart4_device);
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /**< #ifdef RT_USING_UART4 */
|
||||||
|
|
||||||
|
void rt_hw_serial_init(void)
|
||||||
|
{
|
||||||
|
uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART0
|
||||||
|
/* initialize UART0 */
|
||||||
|
/* Set Uart Ch0 Port, SIN0_0:P21, SOT0_0:P22 */
|
||||||
|
FM3_GPIO->ADE &= ~(1UL<<31); /* disable P22 AN31 function */
|
||||||
|
FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | (1<<1) | (1<<2);
|
||||||
|
FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 & ~(3<<4 | 3<<6) | (1<<4) | (1<<6);
|
||||||
|
|
||||||
|
uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
|
||||||
|
uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
|
||||||
|
uart0.uart_device->ESCR = ESCR_DATABITS_8;
|
||||||
|
uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
|
||||||
|
|
||||||
|
/* register UART0 device */
|
||||||
|
rt_hw_serial_register(&uart0_device,
|
||||||
|
"uart0",
|
||||||
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||||
|
&uart0);
|
||||||
|
#endif /**< #ifdef RT_USING_UART0 */
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART2
|
||||||
|
/* initialize UART2 */
|
||||||
|
/* Set Uart Ch2 Port, SIN2_2:P17, SOT2_2:P18 */
|
||||||
|
FM3_GPIO->ADE &= ~(1<<7 | 1<<8); /* disable P17 AN07 and P18 AN08 function */
|
||||||
|
FM3_GPIO->PFR1 = FM3_GPIO->PFR1 | (1<<7) | (1<<8) ;
|
||||||
|
FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | (3<<16) | (3<<18) ;
|
||||||
|
|
||||||
|
uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
|
||||||
|
uart2.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
|
||||||
|
uart2.uart_device->ESCR = ESCR_DATABITS_8;
|
||||||
|
uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
|
||||||
|
|
||||||
|
/* register UART2 device */
|
||||||
|
rt_hw_serial_register(&uart2_device,
|
||||||
|
"uart2",
|
||||||
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||||
|
&uart2);
|
||||||
|
#endif /**< #ifdef RT_USING_UART2 */
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART4
|
||||||
|
/* initialize UART4 */
|
||||||
|
/* Set Uart Ch4 Port, SIN4_2:P05, SOT4_2:P06 */
|
||||||
|
FM3_GPIO->PFR0 = FM3_GPIO->PFR0 | (1<<5) | (1<<6);
|
||||||
|
FM3_GPIO->EPFR08 = FM3_GPIO->EPFR08 | (3<<4) | (3<<6);
|
||||||
|
|
||||||
|
uart4.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
|
||||||
|
uart4.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
|
||||||
|
uart4.uart_device->ESCR = ESCR_DATABITS_8;
|
||||||
|
uart4.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
|
||||||
|
|
||||||
|
/* register UART4 device */
|
||||||
|
rt_hw_serial_register(&uart4_device,
|
||||||
|
"uart4",
|
||||||
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||||
|
&uart4);
|
||||||
|
#endif /**< #ifdef RT_USING_UART4 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,99 @@
|
||||||
|
/*
|
||||||
|
* File : serial.h
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2006-03-13 Bernard first version
|
||||||
|
* 2011-05-15 lgnq modified according bernard's implementaion.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __RT_HW_SERIAL_H__
|
||||||
|
#define __RT_HW_SERIAL_H__
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
#define SMR_SOE 0x01U
|
||||||
|
#define SMR_BDS 0x04U
|
||||||
|
#define SMR_SBL 0x08U
|
||||||
|
#define SMR_WUCR 0x10U
|
||||||
|
#define SMR_MD_UART 0x00U
|
||||||
|
#define SMR_MD_UART_MP 0x20U
|
||||||
|
#define SMR_MD_SIO 0x40U
|
||||||
|
#define SMR_MD_LIN 0x60U
|
||||||
|
#define SMR_MD_I2C 0x80U
|
||||||
|
|
||||||
|
#define SCR_TXE 0x01U
|
||||||
|
#define SCR_RXE 0x02U
|
||||||
|
#define SCR_TBIE 0x04U
|
||||||
|
#define SCR_TIE 0x08U
|
||||||
|
#define SCR_RIE 0x10U
|
||||||
|
#define SCR_UPGL 0x80U
|
||||||
|
|
||||||
|
#define SSR_TBI 0x01U
|
||||||
|
#define SSR_TDRE 0x02U
|
||||||
|
#define SSR_RDRF 0x04U
|
||||||
|
#define SSR_ORE 0x08U
|
||||||
|
#define SSR_FRE 0x10U
|
||||||
|
#define SSR_PE 0x20U
|
||||||
|
#define SSR_REC 0x80U
|
||||||
|
|
||||||
|
#define ESCR_P 0x08U
|
||||||
|
#define ESCR_PEN 0x10U
|
||||||
|
#define ESCR_INV 0x20U
|
||||||
|
#define ESCR_ESBL 0x40U
|
||||||
|
#define ESCR_FLWEN 0x80U
|
||||||
|
#define ESCR_DATABITS_8 0x00U
|
||||||
|
#define ESCR_DATABITS_5 0x01U
|
||||||
|
#define ESCR_DATABITS_6 0x02U
|
||||||
|
#define ESCR_DATABITS_7 0x03U
|
||||||
|
#define ESCR_DATABITS_9 0x04U
|
||||||
|
|
||||||
|
#define BPS 115200 /* serial baudrate */
|
||||||
|
|
||||||
|
#define UART_RX_BUFFER_SIZE 64
|
||||||
|
#define UART_TX_BUFFER_SIZE 64
|
||||||
|
|
||||||
|
struct serial_int_rx
|
||||||
|
{
|
||||||
|
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
|
||||||
|
rt_uint32_t read_index, save_index;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct serial_int_tx
|
||||||
|
{
|
||||||
|
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
|
||||||
|
rt_uint32_t write_index, save_index;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable/DISABLE Interrupt Controller
|
||||||
|
*/
|
||||||
|
/* deviation from MISRA-C:2004 Rule 19.7 */
|
||||||
|
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
|
||||||
|
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
|
||||||
|
|
||||||
|
struct serial_device
|
||||||
|
{
|
||||||
|
FM3_MFS03_UART_TypeDef* uart_device;
|
||||||
|
/* irq number */
|
||||||
|
IRQn_Type rx_irq, tx_irq;
|
||||||
|
|
||||||
|
/* rx structure */
|
||||||
|
struct serial_int_rx* int_rx;
|
||||||
|
/* tx structure */
|
||||||
|
struct serial_int_tx* int_tx;
|
||||||
|
};
|
||||||
|
|
||||||
|
void rt_hw_serial_isr(rt_device_t device);
|
||||||
|
void rt_hw_serial_init(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,74 @@
|
||||||
|
/* RT-Thread config file */
|
||||||
|
#ifndef __RTTHREAD_CFG_H__
|
||||||
|
#define __RTTHREAD_CFG_H__
|
||||||
|
|
||||||
|
/* RT_NAME_MAX*/
|
||||||
|
#define RT_NAME_MAX 8
|
||||||
|
|
||||||
|
/* RT_ALIGN_SIZE*/
|
||||||
|
#define RT_ALIGN_SIZE 4
|
||||||
|
|
||||||
|
/* PRIORITY_MAX */
|
||||||
|
#define RT_THREAD_PRIORITY_MAX 32
|
||||||
|
|
||||||
|
/* Tick per Second */
|
||||||
|
#define RT_TICK_PER_SECOND 100
|
||||||
|
|
||||||
|
/* SECTION: RT_DEBUG */
|
||||||
|
/* Thread Debug */
|
||||||
|
#define RT_DEBUG
|
||||||
|
#define RT_USING_OVERFLOW_CHECK
|
||||||
|
|
||||||
|
/* Using Hook */
|
||||||
|
#define RT_USING_HOOK
|
||||||
|
|
||||||
|
/* SECTION: IPC */
|
||||||
|
/* Using Semaphore */
|
||||||
|
#define RT_USING_SEMAPHORE
|
||||||
|
|
||||||
|
/* Using Mutex */
|
||||||
|
#define RT_USING_MUTEX
|
||||||
|
|
||||||
|
/* Using Event */
|
||||||
|
#define RT_USING_EVENT
|
||||||
|
|
||||||
|
/* Using MailBox */
|
||||||
|
#define RT_USING_MAILBOX
|
||||||
|
|
||||||
|
/* Using Message Queue */
|
||||||
|
#define RT_USING_MESSAGEQUEUE
|
||||||
|
|
||||||
|
/* SECTION: Memory Management */
|
||||||
|
/* Using Memory Pool Management*/
|
||||||
|
#define RT_USING_MEMPOOL
|
||||||
|
|
||||||
|
/* Using Dynamic Heap Management */
|
||||||
|
#define RT_USING_HEAP
|
||||||
|
|
||||||
|
/* Using Small MM */
|
||||||
|
#define RT_USING_SMALL_MEM
|
||||||
|
|
||||||
|
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
|
||||||
|
#define RT_USING_COMPONENTS_INIT
|
||||||
|
|
||||||
|
/* SECTION: Device System */
|
||||||
|
/* Using Device System */
|
||||||
|
#define RT_USING_DEVICE
|
||||||
|
|
||||||
|
/* SECTION: Console options */
|
||||||
|
/* #define RT_TINY_SIZE */
|
||||||
|
#define RT_USING_CONSOLE
|
||||||
|
/* the buffer size of console */
|
||||||
|
#define RT_CONSOLEBUF_SIZE 128
|
||||||
|
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
|
||||||
|
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||||
|
|
||||||
|
/* SECTION: finsh, a C-Express shell */
|
||||||
|
/* Using FinSH as Shell*/
|
||||||
|
#define RT_USING_FINSH
|
||||||
|
/* Using symbol table */
|
||||||
|
#define FINSH_USING_SYMTAB
|
||||||
|
#define FINSH_USING_DESCRIPTION
|
||||||
|
#define FINSH_THREAD_STACK_SIZE 1024
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,118 @@
|
||||||
|
# toolchains options
|
||||||
|
ARCH='arm'
|
||||||
|
CPU='cortex-m3'
|
||||||
|
CROSS_TOOL='keil'
|
||||||
|
|
||||||
|
#device options
|
||||||
|
# FM3_TYPE =
|
||||||
|
# 'MB9B610S','MB9B610T',
|
||||||
|
FM3_TYPE = 'MB9B610S'
|
||||||
|
|
||||||
|
# cross_tool provides the cross compiler
|
||||||
|
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||||
|
|
||||||
|
if CROSS_TOOL == 'gcc':
|
||||||
|
PLATFORM = 'gcc'
|
||||||
|
EXEC_PATH = r'F:\Program Files\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI_2013.05.23\bin'
|
||||||
|
elif CROSS_TOOL == 'keil':
|
||||||
|
PLATFORM = 'armcc'
|
||||||
|
EXEC_PATH = r'E:/Keil'
|
||||||
|
elif CROSS_TOOL == 'iar':
|
||||||
|
PLATFORM = 'iar'
|
||||||
|
IAR_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
|
||||||
|
|
||||||
|
BUILD = 'debug'
|
||||||
|
|
||||||
|
if PLATFORM == 'gcc':
|
||||||
|
# toolchains
|
||||||
|
PREFIX = 'arm-none-eabi-'
|
||||||
|
CC = PREFIX + 'gcc'
|
||||||
|
AS = PREFIX + 'gcc'
|
||||||
|
AR = PREFIX + 'ar'
|
||||||
|
LINK = PREFIX + 'gcc'
|
||||||
|
TARGET_EXT = 'axf'
|
||||||
|
SIZE = PREFIX + 'size'
|
||||||
|
OBJDUMP = PREFIX + 'objdump'
|
||||||
|
OBJCPY = PREFIX + 'objcopy'
|
||||||
|
|
||||||
|
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
|
||||||
|
CFLAGS = DEVICE
|
||||||
|
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||||
|
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-fm3.ld'
|
||||||
|
|
||||||
|
CPATH = ''
|
||||||
|
LPATH = ''
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' -O0 -gdwarf-2'
|
||||||
|
AFLAGS += ' -gdwarf-2'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -O2'
|
||||||
|
|
||||||
|
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||||
|
elif PLATFORM == 'armcc':
|
||||||
|
# toolchains
|
||||||
|
CC = 'armcc'
|
||||||
|
AS = 'armasm'
|
||||||
|
AR = 'armar'
|
||||||
|
LINK = 'armlink'
|
||||||
|
TARGET_EXT = 'axf'
|
||||||
|
|
||||||
|
DEVICE = ' --device DARMSTM'
|
||||||
|
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||||
|
AFLAGS = DEVICE
|
||||||
|
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread-fm3.sct'
|
||||||
|
|
||||||
|
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||||
|
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||||
|
|
||||||
|
EXEC_PATH += '/arm/bin40/'
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' -g -O0'
|
||||||
|
AFLAGS += ' -g'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -O2'
|
||||||
|
|
||||||
|
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||||
|
|
||||||
|
elif PLATFORM == 'iar':
|
||||||
|
# toolchains
|
||||||
|
CC = 'iccarm'
|
||||||
|
AS = 'iasmarm'
|
||||||
|
AR = 'iarchive'
|
||||||
|
LINK = 'ilinkarm'
|
||||||
|
TARGET_EXT = 'out'
|
||||||
|
|
||||||
|
CFLAGS = ''
|
||||||
|
CFLAGS += ' --diag_suppress Pa050'
|
||||||
|
CFLAGS += ' --no_cse'
|
||||||
|
CFLAGS += ' --no_unroll'
|
||||||
|
CFLAGS += ' --no_inline'
|
||||||
|
CFLAGS += ' --no_code_motion'
|
||||||
|
CFLAGS += ' --no_tbaa'
|
||||||
|
CFLAGS += ' --no_clustering'
|
||||||
|
CFLAGS += ' --no_scheduling'
|
||||||
|
CFLAGS += ' --debug'
|
||||||
|
CFLAGS += ' --endian=little'
|
||||||
|
CFLAGS += ' --cpu=Cortex-M3'
|
||||||
|
CFLAGS += ' -e'
|
||||||
|
CFLAGS += ' --fpu=None'
|
||||||
|
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||||
|
CFLAGS += ' -Ol'
|
||||||
|
CFLAGS += ' --use_c++_inline'
|
||||||
|
|
||||||
|
AFLAGS = ''
|
||||||
|
AFLAGS += ' -s+'
|
||||||
|
AFLAGS += ' -w+'
|
||||||
|
AFLAGS += ' -r'
|
||||||
|
AFLAGS += ' --cpu Cortex-M3'
|
||||||
|
AFLAGS += ' --fpu None'
|
||||||
|
AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
|
||||||
|
|
||||||
|
LFLAGS = ' --config mb9bf506.icf'
|
||||||
|
LFLAGS += ' --semihosting'
|
||||||
|
LFLAGS += ' --entry __iar_program_start'
|
||||||
|
|
||||||
|
EXEC_PATH = IAR_PATH + '/arm/bin/'
|
||||||
|
POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec'
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x0;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
keep { section FSymTab };
|
||||||
|
keep { section VSymTab };
|
||||||
|
keep { section .rti_fn* };
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite, block CSTACK, last block HEAP };
|
||||||
|
|
@ -0,0 +1,143 @@
|
||||||
|
/*
|
||||||
|
* linker script for Fujitsu with GNU ld
|
||||||
|
* aozima 2013-07-13
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 1M /* 1MB flash */
|
||||||
|
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram, 64KB SRAM0 + 64KB SRAM1 */
|
||||||
|
}
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
_system_stack_size = 0x400;
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_isr_vector = .; /* define isr_vector start address */
|
||||||
|
_stext = .;
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* remaining code */
|
||||||
|
*(.text.*) /* remaining code */
|
||||||
|
*(.rodata) /* read-only data (constants) */
|
||||||
|
*(.rodata*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.gnu.linkonce.t*)
|
||||||
|
|
||||||
|
/* section information for finsh shell */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__fsymtab_start = .;
|
||||||
|
KEEP(*(FSymTab))
|
||||||
|
__fsymtab_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
__vsymtab_start = .;
|
||||||
|
KEEP(*(VSymTab))
|
||||||
|
__vsymtab_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
/* section information for initial. */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__rt_init_start = .;
|
||||||
|
KEEP(*(SORT(.rti_fn*)))
|
||||||
|
__rt_init_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .;
|
||||||
|
} > CODE = 0
|
||||||
|
|
||||||
|
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_sidata = .;
|
||||||
|
} > CODE
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
/* .data section which is used for initialized data */
|
||||||
|
|
||||||
|
.data : AT (_sidata)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_sdata = . ;
|
||||||
|
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.gnu.linkonce.d*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_edata = . ;
|
||||||
|
} >DATA
|
||||||
|
|
||||||
|
.stack :
|
||||||
|
{
|
||||||
|
. = . + _system_stack_size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
_estack = .;
|
||||||
|
} >DATA
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .;
|
||||||
|
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_ebss = . ;
|
||||||
|
|
||||||
|
*(.bss.init)
|
||||||
|
} > DATA
|
||||||
|
__bss_end = .;
|
||||||
|
|
||||||
|
_end = .;
|
||||||
|
|
||||||
|
/* Stabs debugging sections. */
|
||||||
|
.stab 0 : { *(.stab) }
|
||||||
|
.stabstr 0 : { *(.stabstr) }
|
||||||
|
.stab.excl 0 : { *(.stab.excl) }
|
||||||
|
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||||
|
.stab.index 0 : { *(.stab.index) }
|
||||||
|
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||||
|
.comment 0 : { *(.comment) }
|
||||||
|
/* DWARF debug sections.
|
||||||
|
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||||
|
* of the section so we begin them at 0. */
|
||||||
|
/* DWARF 1 */
|
||||||
|
.debug 0 : { *(.debug) }
|
||||||
|
.line 0 : { *(.line) }
|
||||||
|
/* GNU DWARF 1 extensions */
|
||||||
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||||
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||||
|
/* DWARF 1.1 and DWARF 2 */
|
||||||
|
.debug_aranges 0 : { *(.debug_aranges) }
|
||||||
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||||
|
/* DWARF 2 */
|
||||||
|
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||||
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||||
|
.debug_line 0 : { *(.debug_line) }
|
||||||
|
.debug_frame 0 : { *(.debug_frame) }
|
||||||
|
.debug_str 0 : { *(.debug_str) }
|
||||||
|
.debug_loc 0 : { *(.debug_loc) }
|
||||||
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||||
|
/* SGI/MIPS DWARF 2 extensions */
|
||||||
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||||
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||||
|
.debug_typenames 0 : { *(.debug_typenames) }
|
||||||
|
.debug_varnames 0 : { *(.debug_varnames) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x1FFF0000 0x00020000 { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,394 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>rtthread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>MB9BF618S</Device>
|
||||||
|
<Vendor>Fujitsu Semiconductors</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000)</FlashDriverDll>
|
||||||
|
<DeviceId>6149</DeviceId>
|
||||||
|
<RegisterFile>mb9bf618s.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>SFD\Fujitsu\MB9BF610\MB9BF618S.SFR</SFDFile>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>Fujitsu\MB9BF610\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>Fujitsu\MB9BF610\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>rtthread-fm3</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>0</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments>-MPU</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments>-MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>0</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<RestoreTracepoints>0</RestoreTracepoints>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>7</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>Segger\JL2CM3.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4099</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>0</bUseTDR>
|
||||||
|
<Flash2>Segger\JL2CM3.dll</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>0</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x10000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x1fff0000</StartAddress>
|
||||||
|
<Size>0x20000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>0</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x08000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<ScatterFile>rtthread-fm3.sct</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
Loading…
Reference in New Issue