ping test e2000d pass
This commit is contained in:
lzh
Rbb666
parent
214f187821
commit
65b5735178
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@ -8,7 +8,7 @@ CONFIG_RT_NAME_MAX=16
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# CONFIG_RT_USING_NANO is not set
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# CONFIG_RT_USING_AMP is not set
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CONFIG_RT_USING_SMP=y
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CONFIG_RT_CPUS_NR=4
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CONFIG_RT_CPUS_NR=2
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CONFIG_RT_ALIGN_SIZE=4
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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@ -44,7 +44,7 @@ CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y
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CONFIG_RT_USING_DEBUG=y
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CONFIG_RT_DEBUGING_ASSERT=y
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CONFIG_RT_DEBUGING_COLOR=y
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CONFIG_RT_DEBUGING_CONTEXT=y
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# CONFIG_RT_DEBUGING_CONTEXT is not set
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# CONFIG_RT_DEBUGING_AUTO_INIT is not set
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# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
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# CONFIG_RT_DEBUGING_SPINLOCK is not set
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@ -91,7 +91,7 @@ CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x50200
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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CONFIG_RT_USING_STDC_ATOMIC=y
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CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
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# end of RT-Thread Kernel
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@ -204,7 +204,7 @@ CONFIG_RT_USING_SERIAL_V1=y
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CONFIG_RT_SERIAL_USING_DMA=y
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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CONFIG_RT_USING_CAN=y
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# CONFIG_RT_CAN_USING_HDR is not set
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CONFIG_RT_CAN_USING_HDR=y
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CONFIG_RT_CAN_USING_CANFD=y
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# CONFIG_RT_USING_CPUTIME is not set
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CONFIG_RT_USING_I2C=y
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@ -383,7 +383,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -1286,7 +1286,11 @@ CONFIG_RT_USING_SPIM0=y
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CONFIG_RT_USING_SPIM1=y
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CONFIG_RT_USING_SPIM2=y
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CONFIG_RT_USING_SPIM3=y
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# CONFIG_BSP_USING_CAN is not set
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CONFIG_BSP_USING_CAN=y
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CONFIG_RT_USING_CANFD=y
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# CONFIG_RT_USING_FILTER is not set
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CONFIG_RT_USING_CAN0=y
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# CONFIG_RT_USING_CAN1 is not set
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# CONFIG_BSP_USING_GPIO is not set
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CONFIG_BSP_USING_QSPI=y
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CONFIG_RT_USING_QSPI0=y
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@ -1294,20 +1298,12 @@ CONFIG_USING_QSPI_CHANNEL0=y
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# CONFIG_USING_QSPI_CHANNEL1 is not set
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CONFIG_BSP_USING_ETH=y
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CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
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CONFIG_BSP_USING_PWM=y
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# CONFIG_RT_USING_PWM0 is not set
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# CONFIG_RT_USING_PWM1 is not set
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CONFIG_RT_USING_PWM2=y
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# CONFIG_RT_USING_PWM3 is not set
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# CONFIG_RT_USING_PWM4 is not set
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# CONFIG_RT_USING_PWM5 is not set
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# CONFIG_RT_USING_PWM6 is not set
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# CONFIG_RT_USING_PWM7 is not set
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# CONFIG_BSP_USING_PWM is not set
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CONFIG_BSP_USING_I2C=y
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CONFIG_I2C_USE_MIO=y
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CONFIG_RT_USING_MIO0=y
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CONFIG_RT_USING_MIO1=y
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CONFIG_RT_USING_MIO2=y
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# CONFIG_RT_USING_MIO0 is not set
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# CONFIG_RT_USING_MIO1 is not set
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# CONFIG_RT_USING_MIO2 is not set
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# CONFIG_RT_USING_MIO3 is not set
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# CONFIG_RT_USING_MIO4 is not set
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# CONFIG_RT_USING_MIO5 is not set
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@ -1315,22 +1311,24 @@ CONFIG_RT_USING_MIO2=y
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# CONFIG_RT_USING_MIO7 is not set
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# CONFIG_RT_USING_MIO8 is not set
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# CONFIG_RT_USING_MIO9 is not set
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CONFIG_RT_USING_MIO10=y
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# CONFIG_RT_USING_MIO10 is not set
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# CONFIG_RT_USING_MIO11 is not set
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# CONFIG_RT_USING_MIO12 is not set
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# CONFIG_RT_USING_MIO13 is not set
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# CONFIG_RT_USING_MIO14 is not set
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# CONFIG_RT_USING_MIO15 is not set
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CONFIG_RT_USING_MIO15=y
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# CONFIG_I2C_USE_CONTROLLER is not set
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CONFIG_BSP_USING_SDIF=y
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CONFIG_BSP_USING_SDCARD_FATFS=y
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# CONFIG_USING_SDIF0 is not set
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CONFIG_USING_SDIF0=y
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# CONFIG_USE_SDIF0_TF is not set
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CONFIG_USE_SDIF0_EMMC=y
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CONFIG_USING_SDIF1=y
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CONFIG_USE_SDIF1_TF=y
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# CONFIG_USE_SDIF1_EMMC is not set
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CONFIG_BSP_USING_DC=y
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# CONFIG_RT_USING_DC_CHANNEL0 is not set
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# CONFIG_RT_USING_DC_CHANNEL1 is not set
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CONFIG_RT_USING_DC_CHANNEL1=y
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# CONFIG_BSP_USING_XHCI is not set
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# CONFIG_BSP_USING_PUSB2 is not set
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# end of On-chip Peripheral Drivers
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@ -1343,7 +1341,7 @@ CONFIG_BSP_USING_DC=y
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CONFIG_BSP_USING_GIC=y
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CONFIG_BSP_USING_GICV3=y
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CONFIG_PHYTIUM_ARCH_AARCH64=y
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CONFIG_ARM_SPI_BIND_CPU_ID=2
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CONFIG_ARM_SPI_BIND_CPU_ID=0
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#
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# Standalone Setting
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@ -1353,15 +1351,16 @@ CONFIG_TARGET_ARMV8_AARCH64=y
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#
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# Soc configuration
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#
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CONFIG_TARGET_PHYTIUMPI=y
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# CONFIG_TARGET_PHYTIUMPI is not set
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# CONFIG_TARGET_E2000Q is not set
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# CONFIG_TARGET_E2000D is not set
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CONFIG_TARGET_E2000D=y
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# CONFIG_TARGET_E2000S is not set
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# CONFIG_TARGET_FT2004 is not set
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# CONFIG_TARGET_D2000 is not set
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# CONFIG_TARGET_PD2308 is not set
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CONFIG_SOC_NAME="phytiumpi"
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CONFIG_SOC_CORE_NUM=4
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CONFIG_SOC_NAME="e2000"
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CONFIG_TARGET_TYPE_NAME="d"
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CONFIG_SOC_CORE_NUM=2
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CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
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CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
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CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000
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@ -1375,21 +1374,22 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
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#
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# Board Configuration
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#
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CONFIG_BOARD_NAME="firefly"
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CONFIG_E2000D_DEMO_BOARD=y
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CONFIG_BOARD_NAME="demo"
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#
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# IO mux configuration when board start up
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#
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# CONFIG_USE_SPI_IOPAD is not set
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# CONFIG_USE_GPIO_IOPAD is not set
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# CONFIG_USE_CAN_IOPAD is not set
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# CONFIG_USE_QSPI_IOPAD is not set
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# CONFIG_USE_PWM_IOPAD is not set
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# CONFIG_USE_ADC_IOPAD is not set
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# CONFIG_USE_MIO_IOPAD is not set
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# CONFIG_USE_TACHO_IOPAD is not set
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# CONFIG_USE_UART_IOPAD is not set
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# CONFIG_USE_THIRD_PARTY_IOPAD is not set
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CONFIG_FIREFLY_DEMO_BOARD=y
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#
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# IO mux configuration when board start up
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#
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# end of IO mux configuration when board start up
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# CONFIG_CUS_DEMO_BOARD is not set
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@ -394,7 +394,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -266,6 +266,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -91,7 +91,7 @@ CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x50200
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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CONFIG_RT_USING_STDC_ATOMIC=y
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CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
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# end of RT-Thread Kernel
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@ -383,7 +383,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -58,6 +58,7 @@
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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#define RT_VER_NUM 0x50200
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#define RT_USING_STDC_ATOMIC
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#define RT_BACKTRACE_LEVEL_MAX_NR 32
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/* end of RT-Thread Kernel */
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@ -246,6 +247,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -394,7 +394,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -266,6 +266,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -91,7 +91,7 @@ CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x50200
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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CONFIG_RT_USING_STDC_ATOMIC=y
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CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
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# end of RT-Thread Kernel
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@ -383,7 +383,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -58,6 +58,7 @@
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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#define RT_VER_NUM 0x50200
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#define RT_USING_STDC_ATOMIC
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#define RT_BACKTRACE_LEVEL_MAX_NR 32
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/* end of RT-Thread Kernel */
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@ -246,6 +247,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -394,7 +394,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -265,6 +265,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -91,7 +91,7 @@ CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x50200
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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CONFIG_RT_USING_STDC_ATOMIC=y
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CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
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# end of RT-Thread Kernel
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@ -383,7 +383,7 @@ CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
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CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
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CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
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CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
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# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
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CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
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CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
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CONFIG_LWIP_NETIF_LINK_CALLBACK=1
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CONFIG_RT_LWIP_NETIF_NAMESIZE=6
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@ -59,6 +59,7 @@
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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#define RT_VER_NUM 0x50200
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#define RT_USING_STDC_ATOMIC
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#define RT_BACKTRACE_LEVEL_MAX_NR 32
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/* end of RT-Thread Kernel */
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@ -246,6 +247,7 @@
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define RT_LWIP_REASSEMBLY_FRAG
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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@ -5,7 +5,7 @@
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#define RT_NAME_MAX 16
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#define RT_USING_SMP
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#define RT_CPUS_NR 4
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#define RT_CPUS_NR 2
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#define RT_ALIGN_SIZE 4
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#define RT_THREAD_PRIORITY_32
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#define RT_THREAD_PRIORITY_MAX 32
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@ -32,7 +32,6 @@
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#define RT_USING_DEBUG
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#define RT_DEBUGING_ASSERT
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#define RT_DEBUGING_COLOR
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#define RT_DEBUGING_CONTEXT
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/* Inter-Thread communication */
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@ -59,6 +58,7 @@
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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#define RT_VER_NUM 0x50200
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#define RT_USING_STDC_ATOMIC
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#define RT_BACKTRACE_LEVEL_MAX_NR 32
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/* end of RT-Thread Kernel */
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@ -141,6 +141,7 @@
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#define RT_SERIAL_USING_DMA
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#define RT_SERIAL_RB_BUFSZ 64
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#define RT_USING_CAN
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#define RT_CAN_USING_HDR
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#define RT_CAN_USING_CANFD
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#define RT_USING_I2C
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#define RT_USING_I2C_BITOPS
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@ -246,6 +247,7 @@
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|||
#define RT_LWIP_ETHTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
|
||||
#define RT_LWIP_REASSEMBLY_FRAG
|
||||
#define LWIP_NETIF_STATUS_CALLBACK 1
|
||||
#define LWIP_NETIF_LINK_CALLBACK 1
|
||||
#define RT_LWIP_NETIF_NAMESIZE 6
|
||||
|
|
@ -450,24 +452,25 @@
|
|||
#define RT_USING_SPIM1
|
||||
#define RT_USING_SPIM2
|
||||
#define RT_USING_SPIM3
|
||||
#define BSP_USING_CAN
|
||||
#define RT_USING_CANFD
|
||||
#define RT_USING_CAN0
|
||||
#define BSP_USING_QSPI
|
||||
#define RT_USING_QSPI0
|
||||
#define USING_QSPI_CHANNEL0
|
||||
#define BSP_USING_ETH
|
||||
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
|
||||
#define BSP_USING_PWM
|
||||
#define RT_USING_PWM2
|
||||
#define BSP_USING_I2C
|
||||
#define I2C_USE_MIO
|
||||
#define RT_USING_MIO0
|
||||
#define RT_USING_MIO1
|
||||
#define RT_USING_MIO2
|
||||
#define RT_USING_MIO10
|
||||
#define RT_USING_MIO15
|
||||
#define BSP_USING_SDIF
|
||||
#define BSP_USING_SDCARD_FATFS
|
||||
#define USING_SDIF0
|
||||
#define USE_SDIF0_EMMC
|
||||
#define USING_SDIF1
|
||||
#define USE_SDIF1_TF
|
||||
#define BSP_USING_DC
|
||||
#define RT_USING_DC_CHANNEL1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
|
@ -476,7 +479,7 @@
|
|||
#define BSP_USING_GIC
|
||||
#define BSP_USING_GICV3
|
||||
#define PHYTIUM_ARCH_AARCH64
|
||||
#define ARM_SPI_BIND_CPU_ID 2
|
||||
#define ARM_SPI_BIND_CPU_ID 0
|
||||
|
||||
/* Standalone Setting */
|
||||
|
||||
|
|
@ -484,9 +487,10 @@
|
|||
|
||||
/* Soc configuration */
|
||||
|
||||
#define TARGET_PHYTIUMPI
|
||||
#define SOC_NAME "phytiumpi"
|
||||
#define SOC_CORE_NUM 4
|
||||
#define TARGET_E2000D
|
||||
#define SOC_NAME "e2000"
|
||||
#define TARGET_TYPE_NAME "d"
|
||||
#define SOC_CORE_NUM 2
|
||||
#define F32BIT_MEMORY_ADDRESS 0x80000000
|
||||
#define F32BIT_MEMORY_LENGTH 0x80000000
|
||||
#define F64BIT_MEMORY_ADDRESS 0x2000000000
|
||||
|
|
@ -497,8 +501,8 @@
|
|||
|
||||
/* Board Configuration */
|
||||
|
||||
#define BOARD_NAME "firefly"
|
||||
#define FIREFLY_DEMO_BOARD
|
||||
#define E2000D_DEMO_BOARD
|
||||
#define BOARD_NAME "demo"
|
||||
|
||||
/* IO mux configuration when board start up */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue