Merge pull request #275 from aozima/pulls

Pulls

bsp/stm32f107/drivers/stm32_eth.c

@@ -23,10 +23,10 @@
 #include "stm32f10x_rcc.h"
 
 /* STM32F107 ETH dirver options */
-#define CHECKSUM_BY_HARDWARE
+#define CHECKSUM_BY_HARDWARE    1       /* 0: disable.  1: use hardware checksum. */
-#define MII_MODE          /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+#define RMII_MODE               0       /* 0: MII MODE, 1: RMII MODE. */
-//#define RMII_MODE       /* RMII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+#define STM32_ETH_IO_REMAP      1       /* 0: default,  1: remap RXD to PDx. */
-
+#define USE_MCO                 1       /* 0: disable,  1: PA8(MCO) out 25Mhz(MII) or 50Mhz(RMII). */
 
 /** @addtogroup STM32_ETH_Driver
   * @brief ETH driver modules
@@ -652,7 +652,8 @@ __IO uint32_t timeout = 0;
     {
         timeout++;
         tmpreg = ETH->MACMIIAR;
-  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
+    }
+    while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
     /* Return ERROR in case of timeout */
     if(timeout == PHY_READ_TO)
     {
@@ -701,7 +702,8 @@ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHY
     {
         timeout++;
         tmpreg = ETH->MACMIIAR;
-  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
+    }
+    while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
     /* Return ERROR in case of timeout */
     if(timeout == PHY_WRITE_TO)
     {
@@ -2836,7 +2838,8 @@ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTx
     do
     {
         timeout++;
-  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+    }
+    while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
     /* Return ERROR in case of timeout */
     if(timeout == PHY_READ_TO)
     {
@@ -2983,7 +2986,32 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
 #define STM32_ETH_TRACE	        rt_kprintf
 #else
 #define STM32_ETH_TRACE(...)
-#endif
+#endif /* ETH_DEBUG */
+
+#if defined(ETH_RX_DUMP) ||  defined(ETH_TX_DUMP)
+static void packet_dump(const char * msg, const struct pbuf* p)
+{
+    rt_uint32_t i;
+    rt_uint8_t *ptr = p->payload;
+
+    STM32_ETH_TRACE("%s %d byte\n", msg, p->tot_len);
+
+    for(i=0; i<p->tot_len; i++)
+    {
+        if( (i%8) == 0 )
+        {
+            STM32_ETH_TRACE("  ");
+        }
+        if( (i%16) == 0 )
+        {
+            STM32_ETH_TRACE("\r\n");
+        }
+        STM32_ETH_TRACE("%02x ",*ptr);
+        ptr++;
+    }
+    STM32_ETH_TRACE("\n\n");
+}
+#endif /* dump */
 
 #define ETH_RXBUFNB        	4
 #define ETH_TXBUFNB        	2
@@ -3086,9 +3114,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
     ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
     ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
-#ifdef CHECKSUM_BY_HARDWARE
+#if CHECKSUM_BY_HARDWARE
     ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
-#endif
+#endif /* CHECKSUM_BY_HARDWARE */
 
     /*------------------------   DMA   -----------------------------------*/
 
@@ -3202,26 +3230,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
     }
 
 #ifdef ETH_TX_DUMP
-    {
+    packet_dump("TX dump", p);
-        rt_uint32_t i;
-        rt_uint8_t *ptr = (rt_uint8_t*)(DMATxDescToSet->Buffer1Addr);
-
-        STM32_ETH_TRACE("tx_dump:");
-        for(i=0; i<p->tot_len; i++)
-        {
-            if( (i%8) == 0 )
-            {
-                STM32_ETH_TRACE("  ");
-            }
-            if( (i%16) == 0 )
-            {
-                STM32_ETH_TRACE("\r\n");
-            }
-            STM32_ETH_TRACE("%02x ",*ptr);
-            ptr++;
-        }
-        STM32_ETH_TRACE("\r\ndump done!\r\n");
-    }
 #endif
 
     /* Setting the Frame Length: bits[12:0] */
@@ -3230,7 +3239,8 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
     DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
     /* Enable TX Completion Interrupt */
     DMATxDescToSet->Status |= ETH_DMATxDesc_IC;
-#ifdef CHECKSUM_BY_HARDWARE
+
+#if CHECKSUM_BY_HARDWARE
     DMATxDescToSet->Status |= ETH_DMATxDesc_ChecksumTCPUDPICMPFull;
     /* clean ICMP checksum STM32F need */
     {
@@ -3247,7 +3257,8 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
             }
         }
     }
-#endif
+#endif /* CHECKSUM_BY_HARDWARE */
+
     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
     DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
     /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
@@ -3272,7 +3283,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
 struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
 {
     struct pbuf* p;
-    rt_uint32_t offset = 0, framelength = 0;
+    rt_uint32_t framelength = 0;
 
     /* init p pointer */
     p = RT_NULL;
@@ -3292,25 +3303,21 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
         if (p != RT_NULL)
         {
-            rt_uint8_t* ptr;
+            const char * from;
             struct pbuf* q;
-            rt_size_t len;
+
+            from = (const char *)(DMARxDescToGet->Buffer1Addr);
 
             for (q = p; q != RT_NULL; q= q->next)
             {
-                ptr = q->payload;
-                len = q->len;
-
                 /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
-                while (len)
+                memcpy(q->payload, from, q->len);
-                {
+                from += q->len;
-                    *ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+            }
 
-                    offset ++;
+#ifdef ETH_RX_DUMP
-                    ptr ++;
+            packet_dump("RX dump", p);
-                    len --;
+#endif /* ETH_RX_DUMP */
-                }
-            }
         }
     }
 
@@ -3375,24 +3382,175 @@ static void NVIC_Configuration(void)
 
 /*
  * GPIO Configuration for ETH
+    AF Output Push Pull:
+    - ETH_MDC   : PC1
+    - ETH_MDIO  : PA2
+    - ETH_TX_EN : PB11
+    - ETH_TXD0  : PB12
+    - ETH_TXD1  : PB13
+    - ETH_TXD2  : PC2
+    - ETH_TXD3  : PB8
+    - ETH_PPS_OUT / ETH_RMII_PPS_OUT: PB5
+
+    Input (Reset Value):
+    - ETH_MII_TX_CLK: PC3
+    - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
+    - ETH_MII_CRS: PA0
+    - ETH_MII_COL: PA3
+    - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PA7
+    - ETH_MII_RXD0: PC4
+    - ETH_MII_RXD1: PC5
+    - ETH_MII_RXD2: PB0
+    - ETH_MII_RXD3: PB1
+    - ETH_MII_RX_ER: PB10
+
+    ***************************************
+             For Remapped Ethernet pins
+    *******************************************
+    Input (Reset Value):
+    - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
+    - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
+    - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
+    - ETH_MII_RXD2: PD11
+    - ETH_MII_RXD3: PD12
  */
 static void GPIO_Configuration(void)
 {
     GPIO_InitTypeDef GPIO_InitStructure;
 
+#if STM32_ETH_IO_REMAP
     /* ETHERNET pins remapp in STM3210C-EVAL board: RX_DV and RxD[3:0] */
     GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
+#endif /* STM32_ETH_IO_REMAP */
 
     /* MII/RMII Media interface selection */
-#ifdef MII_MODE /* Mode MII with STM3210C-EVAL  */
+#if (RMII_MODE == 0) /* Mode MII. */
     GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
+#elif (RMII_MODE == 1)  /* Mode RMII. */
+    GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
+#endif /* RMII_MODE */
 
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+    /* MDIO */
+    {
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+        /* MDC */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+        GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+        /* MDIO */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+    } /* MDIO */
+
+    /* TXD */
+    {
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+        /* TX_EN */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+        /* TXD0 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+        /* TXD1 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#if (RMII_MODE == 0)
+        /* TXD2 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+        GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+        /* TXD3 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+        /* TX_CLK */
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+        GPIO_Init(GPIOC, &GPIO_InitStructure);
+#endif /* RMII_MODE */
+    } /* TXD */
+
+    /* RXD */
+    {
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+
+#if (STM32_ETH_IO_REMAP == 0)
+        /* RX_DV/CRS_DV */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* RXD0 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+        GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+        /* RXD1 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+        GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+#if (RMII_MODE == 0)
+        /* RXD2 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+        /* RXD3 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+#endif /* RMII_MODE */
+#else
+        /* RX_DV/CRS_DV */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+        GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+        /* RXD0 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+        GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+        /* RXD1 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+        GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+#if (RMII_MODE == 0)
+        /* RXD2 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+        GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+        /* RXD3 */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+        GPIO_Init(GPIOD, &GPIO_InitStructure);
+#endif /* RMII_MODE */
+#endif /* STM32_ETH_IO_REMAP */
+
+#if (RMII_MODE == 0)
+        /* CRS */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* COL */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* RX_CLK */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* RX_ER */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+        GPIO_Init(GPIOB, &GPIO_InitStructure);
+#endif /* RMII_MODE */
+    } /* RXD */
+
+#if (USE_MCO == 1)
+#if (RMII_MODE == 0) /* Mode MII. */
     /* Get HSE clock = 25MHz on PA8 pin(MCO) */
     RCC_MCOConfig(RCC_MCO_HSE);
-
+#elif (RMII_MODE == 1)  /* Mode RMII. */
-#elif defined RMII_MODE  /* Mode RMII with STM3210C-EVAL */
-	GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
-
     /* Get HSE clock = 25MHz on PA8 pin(MCO) */
     /* set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */
     RCC_PLL3Config(RCC_PLL3Mul_10);
@@ -3404,76 +3562,7 @@ static void GPIO_Configuration(void)
 
     /* Get clock PLL3 clock on PA8 pin */
     RCC_MCOConfig(RCC_MCO_PLL3CLK);
-#endif
+#endif /* RMII_MODE */
-
-	/* ETHERNET pins configuration */
-	/* AF Output Push Pull:
-	- ETH_MII_MDIO / ETH_RMII_MDIO: PA2
-	- ETH_MII_MDC / ETH_RMII_MDC: PC1
-	- ETH_MII_TXD2: PC2
-	- ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11
-	- ETH_MII_TXD0 / ETH_RMII_TXD0: PB12
-	- ETH_MII_TXD1 / ETH_RMII_TXD1: PB13
-	- ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5
-	- ETH_MII_TXD3: PB8 */
-
-	/* Configure PA2 as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-	/* Configure PC1, PC2 and PC3 as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-	/* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 |
-								  GPIO_Pin_12 | GPIO_Pin_13;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-	/**************************************************************/
-	/*               For Remapped Ethernet pins                   */
-	/*************************************************************/
-	/* Input (Reset Value):
-	- ETH_MII_CRS CRS: PA0
-	- ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
-	- ETH_MII_COL: PA3
-	- ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
-	- ETH_MII_TX_CLK: PC3
-	- ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
-	- ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
-	- ETH_MII_RXD2: PD11
-	- ETH_MII_RXD3: PD12
-	- ETH_MII_RX_ER: PB10 */
-
-	/* Configure PA0, PA1 and PA3 as input */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-	GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-	/* Configure PB10 as input */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-	GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-	/* Configure PC3 as input */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-	GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-	/* Configure PD8, PD9, PD10, PD11 and PD12 as input */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-	GPIO_Init(GPIOD, &GPIO_InitStructure); /**/
 
     /* MCO pin configuration------------------------------------------------- */
     /* Configure MCO (PA8) as alternate function push-pull */
@@ -3481,6 +3570,7 @@ static void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOA, &GPIO_InitStructure);
+#endif /* USE_MCO */
 }
 
 void rt_hw_stm32_eth_init()
@@ -3516,3 +3606,56 @@ void rt_hw_stm32_eth_init()
     eth_device_init(&(stm32_eth_device.parent), "e0");
 }
 
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void phy_search(void)
+{
+    int i;
+    int value;
+
+    for(i=0; i<32; i++)
+    {
+        value = ETH_ReadPHYRegister(i, 2);
+        rt_kprintf("addr %02d: %04X\n", i, value);
+    }
+}
+FINSH_FUNCTION_EXPORT(phy_search, search phy use MDIO);
+
+static void phy_dump(int addr)
+{
+    int i;
+    int value;
+
+    rt_kprintf("dump phy addr %d\n", addr);
+
+    for(i=0; i<32; i++)
+    {
+        value = ETH_ReadPHYRegister(addr, i);
+        rt_kprintf("reg %02d: %04X\n", i, value);
+    }
+}
+FINSH_FUNCTION_EXPORT(phy_dump, dump PHY register);
+
+static void phy_write(int addr, int reg, int value)
+{
+    ETH_WritePHYRegister(addr, reg ,value);
+}
+FINSH_FUNCTION_EXPORT(phy_write, write PHY register);
+
+static void emac_dump(int addr)
+{
+    int i;
+    int value;
+    int *p = (int *)ETH;
+
+    rt_kprintf("dump EAMC reg %d\n", addr);
+
+    for(i=0; i<sizeof(ETH_TypeDef)/4; i++)
+    {
+        value = *p++;
+        rt_kprintf("reg %04X: %08X\n", i*4, value);
+    }
+}
+FINSH_FUNCTION_EXPORT(emac_dump, dump EMAC register);
+
+#endif // RT_USING_FINSH