mirror of
https://github.com/RT-Thread/rt-thread.git
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Modify the indentation format
This commit is contained in:
jhb
parent
70cbbcb59a
commit
642aaa9496
@ -6,7 +6,7 @@
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******************************************************************************
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** This notice applies to any and all portions of this file
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* that are not between comment pairs USER CODE BEGIN and
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* USER CODE END. Other portions of this file, whether
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* USER CODE END. Other portions of this file, whether
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* inserted by the user or by software development tools
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* are owned by their respective copyright owners.
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*
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@ -103,47 +103,47 @@ static void MX_GFXMMU_Init(void);
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*/
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int main(void)
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{
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/* USER CODE BEGIN 1 */
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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/* USER CODE BEGIN Init */
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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/* Configure the system clock */
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SystemClock_Config();
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/* USER CODE BEGIN SysInit */
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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MX_USART3_UART_Init();
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MX_LTDC_Init();
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MX_FMC_Init();
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MX_DMA2D_Init();
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MX_DSIHOST_DSI_Init();
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MX_GFXMMU_Init();
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/* USER CODE BEGIN 2 */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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MX_USART3_UART_Init();
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MX_LTDC_Init();
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MX_FMC_Init();
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MX_DMA2D_Init();
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MX_DSIHOST_DSI_Init();
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MX_GFXMMU_Init();
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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{
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/* USER CODE END WHILE */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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{
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/* USER CODE END WHILE */
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/* USER CODE BEGIN 3 */
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}
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/* USER CODE END 3 */
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/* USER CODE BEGIN 3 */
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}
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/* USER CODE END 3 */
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}
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/**
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@ -152,60 +152,60 @@ int main(void)
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/**Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 2;
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RCC_OscInitStruct.PLL.PLLN = 30;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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/**Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 2;
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RCC_OscInitStruct.PLL.PLLN = 30;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI
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|RCC_PERIPHCLK_LTDC;
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PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY;
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PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
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PeriphClkInit.PLLSAI2.PLLSAI2M = 2;
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PeriphClkInit.PLLSAI2.PLLSAI2N = 8;
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PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI
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|RCC_PERIPHCLK_LTDC;
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PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY;
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PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
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PeriphClkInit.PLLSAI2.PLLSAI2M = 2;
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PeriphClkInit.PLLSAI2.PLLSAI2N = 8;
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PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2;
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PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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}
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/**
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@ -216,36 +216,36 @@ void SystemClock_Config(void)
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static void MX_DMA2D_Init(void)
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{
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/* USER CODE BEGIN DMA2D_Init 0 */
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/* USER CODE BEGIN DMA2D_Init 0 */
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/* USER CODE END DMA2D_Init 0 */
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/* USER CODE END DMA2D_Init 0 */
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/* USER CODE BEGIN DMA2D_Init 1 */
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/* USER CODE BEGIN DMA2D_Init 1 */
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/* USER CODE END DMA2D_Init 1 */
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hdma2d.Instance = DMA2D;
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hdma2d.Init.Mode = DMA2D_M2M;
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hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
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hdma2d.Init.OutputOffset = 0;
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hdma2d.Init.BytesSwap = DMA2D_BYTES_REGULAR;
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hdma2d.Init.LineOffsetMode = DMA2D_LOM_PIXELS;
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hdma2d.LayerCfg[1].InputOffset = 0;
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hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
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hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
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hdma2d.LayerCfg[1].InputAlpha = 0;
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hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA;
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hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR;
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if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN DMA2D_Init 2 */
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/* USER CODE END DMA2D_Init 1 */
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hdma2d.Instance = DMA2D;
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hdma2d.Init.Mode = DMA2D_M2M;
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hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
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hdma2d.Init.OutputOffset = 0;
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hdma2d.Init.BytesSwap = DMA2D_BYTES_REGULAR;
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hdma2d.Init.LineOffsetMode = DMA2D_LOM_PIXELS;
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hdma2d.LayerCfg[1].InputOffset = 0;
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hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
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hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
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hdma2d.LayerCfg[1].InputAlpha = 0;
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hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA;
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hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR;
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if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN DMA2D_Init 2 */
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/* USER CODE END DMA2D_Init 2 */
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/* USER CODE END DMA2D_Init 2 */
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}
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@ -257,85 +257,85 @@ static void MX_DMA2D_Init(void)
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static void MX_DSIHOST_DSI_Init(void)
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{
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/* USER CODE BEGIN DSIHOST_Init 0 */
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/* USER CODE BEGIN DSIHOST_Init 0 */
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/* USER CODE END DSIHOST_Init 0 */
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/* USER CODE END DSIHOST_Init 0 */
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DSI_PLLInitTypeDef PLLInit = {0};
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DSI_HOST_TimeoutTypeDef HostTimeouts = {0};
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DSI_PHY_TimerTypeDef PhyTimings = {0};
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DSI_LPCmdTypeDef LPCmd = {0};
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DSI_PLLInitTypeDef PLLInit = {0};
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DSI_HOST_TimeoutTypeDef HostTimeouts = {0};
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DSI_PHY_TimerTypeDef PhyTimings = {0};
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DSI_LPCmdTypeDef LPCmd = {0};
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/* USER CODE BEGIN DSIHOST_Init 1 */
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/* USER CODE BEGIN DSIHOST_Init 1 */
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/* USER CODE END DSIHOST_Init 1 */
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hdsi.Instance = DSI;
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hdsi.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE;
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hdsi.Init.TXEscapeCkdiv = 4;
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hdsi.Init.NumberOfLanes = DSI_ONE_DATA_LANE;
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PLLInit.PLLNDIV = 20;
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PLLInit.PLLIDF = DSI_PLL_IN_DIV1;
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PLLInit.PLLODF = DSI_PLL_OUT_DIV2;
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if (HAL_DSI_Init(&hdsi, &PLLInit) != HAL_OK)
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{
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Error_Handler();
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}
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HostTimeouts.TimeoutCkdiv = 1;
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HostTimeouts.HighSpeedTransmissionTimeout = 0;
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HostTimeouts.LowPowerReceptionTimeout = 0;
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HostTimeouts.HighSpeedReadTimeout = 0;
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HostTimeouts.LowPowerReadTimeout = 0;
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HostTimeouts.HighSpeedWriteTimeout = 0;
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HostTimeouts.HighSpeedWritePrespMode = DSI_HS_PM_DISABLE;
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HostTimeouts.LowPowerWriteTimeout = 0;
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HostTimeouts.BTATimeout = 0;
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if (HAL_DSI_ConfigHostTimeouts(&hdsi, &HostTimeouts) != HAL_OK)
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{
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Error_Handler();
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}
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PhyTimings.ClockLaneHS2LPTime = 17;
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PhyTimings.ClockLaneLP2HSTime = 12;
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PhyTimings.DataLaneHS2LPTime = 8;
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PhyTimings.DataLaneLP2HSTime = 8;
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PhyTimings.DataLaneMaxReadTime = 0;
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PhyTimings.StopWaitTime = 0;
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/* USER CODE END DSIHOST_Init 1 */
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hdsi.Instance = DSI;
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hdsi.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE;
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hdsi.Init.TXEscapeCkdiv = 4;
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hdsi.Init.NumberOfLanes = DSI_ONE_DATA_LANE;
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PLLInit.PLLNDIV = 20;
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PLLInit.PLLIDF = DSI_PLL_IN_DIV1;
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PLLInit.PLLODF = DSI_PLL_OUT_DIV2;
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if (HAL_DSI_Init(&hdsi, &PLLInit) != HAL_OK)
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{
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Error_Handler();
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}
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HostTimeouts.TimeoutCkdiv = 1;
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HostTimeouts.HighSpeedTransmissionTimeout = 0;
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HostTimeouts.LowPowerReceptionTimeout = 0;
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HostTimeouts.HighSpeedReadTimeout = 0;
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HostTimeouts.LowPowerReadTimeout = 0;
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HostTimeouts.HighSpeedWriteTimeout = 0;
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HostTimeouts.HighSpeedWritePrespMode = DSI_HS_PM_DISABLE;
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HostTimeouts.LowPowerWriteTimeout = 0;
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HostTimeouts.BTATimeout = 0;
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if (HAL_DSI_ConfigHostTimeouts(&hdsi, &HostTimeouts) != HAL_OK)
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{
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Error_Handler();
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}
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PhyTimings.ClockLaneHS2LPTime = 17;
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PhyTimings.ClockLaneLP2HSTime = 12;
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PhyTimings.DataLaneHS2LPTime = 8;
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PhyTimings.DataLaneLP2HSTime = 8;
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PhyTimings.DataLaneMaxReadTime = 0;
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PhyTimings.StopWaitTime = 0;
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if (HAL_DSI_ConfigPhyTimer(&hdsi, &PhyTimings) != HAL_OK)
|
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{
|
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Error_Handler();
|
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}
|
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if (HAL_DSI_ConfigFlowControl(&hdsi, DSI_FLOW_CONTROL_BTA) != HAL_OK)
|
||||
{
|
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Error_Handler();
|
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}
|
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if (HAL_DSI_SetLowPowerRXFilter(&hdsi, 10000) != HAL_OK)
|
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{
|
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Error_Handler();
|
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}
|
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if (HAL_DSI_ConfigErrorMonitor(&hdsi, HAL_DSI_ERROR_NONE) != HAL_OK)
|
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{
|
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Error_Handler();
|
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}
|
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LPCmd.LPGenShortWriteNoP = DSI_LP_GSW0P_DISABLE;
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LPCmd.LPGenShortWriteOneP = DSI_LP_GSW1P_DISABLE;
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LPCmd.LPGenShortWriteTwoP = DSI_LP_GSW2P_DISABLE;
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LPCmd.LPGenShortReadNoP = DSI_LP_GSR0P_DISABLE;
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LPCmd.LPGenShortReadOneP = DSI_LP_GSR1P_DISABLE;
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LPCmd.LPGenShortReadTwoP = DSI_LP_GSR2P_DISABLE;
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LPCmd.LPGenLongWrite = DSI_LP_GLW_DISABLE;
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LPCmd.LPDcsShortWriteNoP = DSI_LP_DSW0P_DISABLE;
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LPCmd.LPDcsShortWriteOneP = DSI_LP_DSW1P_DISABLE;
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LPCmd.LPDcsShortReadNoP = DSI_LP_DSR0P_DISABLE;
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LPCmd.LPDcsLongWrite = DSI_LP_DLW_DISABLE;
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LPCmd.LPMaxReadPacket = DSI_LP_MRDP_DISABLE;
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LPCmd.AcknowledgeRequest = DSI_ACKNOWLEDGE_DISABLE;
|
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if (HAL_DSI_ConfigCommand(&hdsi, &LPCmd) != HAL_OK)
|
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{
|
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Error_Handler();
|
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}
|
||||
/* USER CODE BEGIN DSIHOST_Init 2 */
|
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if (HAL_DSI_ConfigPhyTimer(&hdsi, &PhyTimings) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
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if (HAL_DSI_ConfigFlowControl(&hdsi, DSI_FLOW_CONTROL_BTA) != HAL_OK)
|
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{
|
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Error_Handler();
|
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}
|
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if (HAL_DSI_SetLowPowerRXFilter(&hdsi, 10000) != HAL_OK)
|
||||
{
|
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Error_Handler();
|
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}
|
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if (HAL_DSI_ConfigErrorMonitor(&hdsi, HAL_DSI_ERROR_NONE) != HAL_OK)
|
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{
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Error_Handler();
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}
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LPCmd.LPGenShortWriteNoP = DSI_LP_GSW0P_DISABLE;
|
||||
LPCmd.LPGenShortWriteOneP = DSI_LP_GSW1P_DISABLE;
|
||||
LPCmd.LPGenShortWriteTwoP = DSI_LP_GSW2P_DISABLE;
|
||||
LPCmd.LPGenShortReadNoP = DSI_LP_GSR0P_DISABLE;
|
||||
LPCmd.LPGenShortReadOneP = DSI_LP_GSR1P_DISABLE;
|
||||
LPCmd.LPGenShortReadTwoP = DSI_LP_GSR2P_DISABLE;
|
||||
LPCmd.LPGenLongWrite = DSI_LP_GLW_DISABLE;
|
||||
LPCmd.LPDcsShortWriteNoP = DSI_LP_DSW0P_DISABLE;
|
||||
LPCmd.LPDcsShortWriteOneP = DSI_LP_DSW1P_DISABLE;
|
||||
LPCmd.LPDcsShortReadNoP = DSI_LP_DSR0P_DISABLE;
|
||||
LPCmd.LPDcsLongWrite = DSI_LP_DLW_DISABLE;
|
||||
LPCmd.LPMaxReadPacket = DSI_LP_MRDP_DISABLE;
|
||||
LPCmd.AcknowledgeRequest = DSI_ACKNOWLEDGE_DISABLE;
|
||||
if (HAL_DSI_ConfigCommand(&hdsi, &LPCmd) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN DSIHOST_Init 2 */
|
||||
|
||||
/* USER CODE END DSIHOST_Init 2 */
|
||||
/* USER CODE END DSIHOST_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
@ -347,32 +347,32 @@ static void MX_DSIHOST_DSI_Init(void)
|
||||
static void MX_GFXMMU_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN GFXMMU_Init 0 */
|
||||
/* USER CODE BEGIN GFXMMU_Init 0 */
|
||||
|
||||
/* USER CODE END GFXMMU_Init 0 */
|
||||
/* USER CODE END GFXMMU_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN GFXMMU_Init 1 */
|
||||
/* USER CODE BEGIN GFXMMU_Init 1 */
|
||||
|
||||
/* USER CODE END GFXMMU_Init 1 */
|
||||
hgfxmmu.Instance = GFXMMU;
|
||||
hgfxmmu.Init.BlocksPerLine = GFXMMU_192BLOCKS;
|
||||
hgfxmmu.Init.DefaultValue = 0;
|
||||
hgfxmmu.Init.Buffers.Buf0Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf1Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf2Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf3Address = 0;
|
||||
hgfxmmu.Init.Interrupts.Activation = ENABLE;
|
||||
if (HAL_GFXMMU_Init(&hgfxmmu) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_GFXMMU_ConfigLut(&hgfxmmu, GFXMMU_LUT_FIRST, GFXMMU_LUT_SIZE, (uint32_t)gfxmmu_lut_config) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN GFXMMU_Init 2 */
|
||||
/* USER CODE END GFXMMU_Init 1 */
|
||||
hgfxmmu.Instance = GFXMMU;
|
||||
hgfxmmu.Init.BlocksPerLine = GFXMMU_192BLOCKS;
|
||||
hgfxmmu.Init.DefaultValue = 0;
|
||||
hgfxmmu.Init.Buffers.Buf0Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf1Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf2Address = 0;
|
||||
hgfxmmu.Init.Buffers.Buf3Address = 0;
|
||||
hgfxmmu.Init.Interrupts.Activation = ENABLE;
|
||||
if (HAL_GFXMMU_Init(&hgfxmmu) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_GFXMMU_ConfigLut(&hgfxmmu, GFXMMU_LUT_FIRST, GFXMMU_LUT_SIZE, (uint32_t)gfxmmu_lut_config) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN GFXMMU_Init 2 */
|
||||
|
||||
/* USER CODE END GFXMMU_Init 2 */
|
||||
/* USER CODE END GFXMMU_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
@ -384,85 +384,85 @@ static void MX_GFXMMU_Init(void)
|
||||
static void MX_LTDC_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN LTDC_Init 0 */
|
||||
/* USER CODE BEGIN LTDC_Init 0 */
|
||||
|
||||
/* USER CODE END LTDC_Init 0 */
|
||||
/* USER CODE END LTDC_Init 0 */
|
||||
|
||||
LTDC_LayerCfgTypeDef pLayerCfg = {0};
|
||||
LTDC_LayerCfgTypeDef pLayerCfg1 = {0};
|
||||
LTDC_LayerCfgTypeDef pLayerCfg = {0};
|
||||
LTDC_LayerCfgTypeDef pLayerCfg1 = {0};
|
||||
|
||||
/* USER CODE BEGIN LTDC_Init 1 */
|
||||
/* USER CODE BEGIN LTDC_Init 1 */
|
||||
|
||||
/* USER CODE END LTDC_Init 1 */
|
||||
hltdc.Instance = LTDC;
|
||||
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
||||
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
||||
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
||||
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
||||
hltdc.Init.HorizontalSync = 7;
|
||||
hltdc.Init.VerticalSync = 3;
|
||||
hltdc.Init.AccumulatedHBP = 14;
|
||||
hltdc.Init.AccumulatedVBP = 5;
|
||||
hltdc.Init.AccumulatedActiveW = 654;
|
||||
hltdc.Init.AccumulatedActiveH = 485;
|
||||
hltdc.Init.TotalWidth = 660;
|
||||
hltdc.Init.TotalHeigh = 487;
|
||||
hltdc.Init.Backcolor.Blue = 0;
|
||||
hltdc.Init.Backcolor.Green = 0;
|
||||
hltdc.Init.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
pLayerCfg.WindowX0 = 0;
|
||||
pLayerCfg.WindowX1 = 0;
|
||||
pLayerCfg.WindowY0 = 0;
|
||||
pLayerCfg.WindowY1 = 0;
|
||||
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
|
||||
pLayerCfg.Alpha = 0;
|
||||
pLayerCfg.Alpha0 = 0;
|
||||
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
|
||||
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
|
||||
pLayerCfg.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE;
|
||||
pLayerCfg.ImageWidth = 0;
|
||||
pLayerCfg.ImageHeight = 0;
|
||||
pLayerCfg.Backcolor.Blue = 0;
|
||||
pLayerCfg.Backcolor.Green = 0;
|
||||
pLayerCfg.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
pLayerCfg1.WindowX0 = 0;
|
||||
pLayerCfg1.WindowX1 = 0;
|
||||
pLayerCfg1.WindowY0 = 0;
|
||||
pLayerCfg1.WindowY1 = 0;
|
||||
pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
|
||||
pLayerCfg1.Alpha = 0;
|
||||
pLayerCfg1.Alpha0 = 0;
|
||||
pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
|
||||
pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
|
||||
pLayerCfg1.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE;
|
||||
pLayerCfg1.ImageWidth = 0;
|
||||
pLayerCfg1.ImageHeight = 0;
|
||||
pLayerCfg1.Backcolor.Blue = 0;
|
||||
pLayerCfg1.Backcolor.Green = 0;
|
||||
pLayerCfg1.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_LTDC_SetPitch(&hltdc, 768, 0) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_LTDC_SetPitch(&hltdc, 768, 1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN LTDC_Init 2 */
|
||||
/* USER CODE END LTDC_Init 1 */
|
||||
hltdc.Instance = LTDC;
|
||||
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
||||
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
||||
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
||||
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
||||
hltdc.Init.HorizontalSync = 7;
|
||||
hltdc.Init.VerticalSync = 3;
|
||||
hltdc.Init.AccumulatedHBP = 14;
|
||||
hltdc.Init.AccumulatedVBP = 5;
|
||||
hltdc.Init.AccumulatedActiveW = 654;
|
||||
hltdc.Init.AccumulatedActiveH = 485;
|
||||
hltdc.Init.TotalWidth = 660;
|
||||
hltdc.Init.TotalHeigh = 487;
|
||||
hltdc.Init.Backcolor.Blue = 0;
|
||||
hltdc.Init.Backcolor.Green = 0;
|
||||
hltdc.Init.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
pLayerCfg.WindowX0 = 0;
|
||||
pLayerCfg.WindowX1 = 0;
|
||||
pLayerCfg.WindowY0 = 0;
|
||||
pLayerCfg.WindowY1 = 0;
|
||||
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
|
||||
pLayerCfg.Alpha = 0;
|
||||
pLayerCfg.Alpha0 = 0;
|
||||
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
|
||||
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
|
||||
pLayerCfg.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE;
|
||||
pLayerCfg.ImageWidth = 0;
|
||||
pLayerCfg.ImageHeight = 0;
|
||||
pLayerCfg.Backcolor.Blue = 0;
|
||||
pLayerCfg.Backcolor.Green = 0;
|
||||
pLayerCfg.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
pLayerCfg1.WindowX0 = 0;
|
||||
pLayerCfg1.WindowX1 = 0;
|
||||
pLayerCfg1.WindowY0 = 0;
|
||||
pLayerCfg1.WindowY1 = 0;
|
||||
pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
|
||||
pLayerCfg1.Alpha = 0;
|
||||
pLayerCfg1.Alpha0 = 0;
|
||||
pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
|
||||
pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
|
||||
pLayerCfg1.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE;
|
||||
pLayerCfg1.ImageWidth = 0;
|
||||
pLayerCfg1.ImageHeight = 0;
|
||||
pLayerCfg1.Backcolor.Blue = 0;
|
||||
pLayerCfg1.Backcolor.Green = 0;
|
||||
pLayerCfg1.Backcolor.Red = 0;
|
||||
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_LTDC_SetPitch(&hltdc, 768, 0) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_LTDC_SetPitch(&hltdc, 768, 1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN LTDC_Init 2 */
|
||||
|
||||
/* USER CODE END LTDC_Init 2 */
|
||||
/* USER CODE END LTDC_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
@ -474,87 +474,87 @@ static void MX_LTDC_Init(void)
|
||||
static void MX_USART3_UART_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN USART3_Init 0 */
|
||||
/* USER CODE BEGIN USART3_Init 0 */
|
||||
|
||||
/* USER CODE END USART3_Init 0 */
|
||||
/* USER CODE END USART3_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN USART3_Init 1 */
|
||||
/* USER CODE BEGIN USART3_Init 1 */
|
||||
|
||||
/* USER CODE END USART3_Init 1 */
|
||||
huart3.Instance = USART3;
|
||||
huart3.Init.BaudRate = 115200;
|
||||
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
huart3.Init.StopBits = UART_STOPBITS_1;
|
||||
huart3.Init.Parity = UART_PARITY_NONE;
|
||||
huart3.Init.Mode = UART_MODE_TX_RX;
|
||||
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
if (HAL_UART_Init(&huart3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN USART3_Init 2 */
|
||||
/* USER CODE END USART3_Init 1 */
|
||||
huart3.Instance = USART3;
|
||||
huart3.Init.BaudRate = 115200;
|
||||
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
huart3.Init.StopBits = UART_STOPBITS_1;
|
||||
huart3.Init.Parity = UART_PARITY_NONE;
|
||||
huart3.Init.Mode = UART_MODE_TX_RX;
|
||||
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
if (HAL_UART_Init(&huart3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN USART3_Init 2 */
|
||||
|
||||
/* USER CODE END USART3_Init 2 */
|
||||
/* USER CODE END USART3_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/* FMC initialization function */
|
||||
static void MX_FMC_Init(void)
|
||||
{
|
||||
FMC_NORSRAM_TimingTypeDef Timing;
|
||||
FMC_NORSRAM_TimingTypeDef Timing;
|
||||
|
||||
/** Perform the SRAM1 memory initialization sequence
|
||||
*/
|
||||
hsram1.Instance = FMC_NORSRAM_DEVICE;
|
||||
hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
|
||||
/* hsram1.Init */
|
||||
hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
|
||||
hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
|
||||
hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
|
||||
hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
|
||||
hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
|
||||
hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
|
||||
hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
|
||||
hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_DISABLE;
|
||||
hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
|
||||
hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
|
||||
hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
|
||||
hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
|
||||
hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
|
||||
hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
|
||||
hsram1.Init.NBLSetupTime = 0;
|
||||
hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
|
||||
/* Timing */
|
||||
Timing.AddressSetupTime = 15;
|
||||
Timing.AddressHoldTime = 15;
|
||||
Timing.DataSetupTime = 255;
|
||||
Timing.DataHoldTime = 0;
|
||||
Timing.BusTurnAroundDuration = 15;
|
||||
Timing.CLKDivision = 16;
|
||||
Timing.DataLatency = 17;
|
||||
Timing.AccessMode = FMC_ACCESS_MODE_A;
|
||||
/* ExtTiming */
|
||||
/** Perform the SRAM1 memory initialization sequence
|
||||
*/
|
||||
hsram1.Instance = FMC_NORSRAM_DEVICE;
|
||||
hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
|
||||
/* hsram1.Init */
|
||||
hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
|
||||
hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
|
||||
hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
|
||||
hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
|
||||
hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
|
||||
hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
|
||||
hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
|
||||
hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_DISABLE;
|
||||
hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
|
||||
hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
|
||||
hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
|
||||
hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
|
||||
hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
|
||||
hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
|
||||
hsram1.Init.NBLSetupTime = 0;
|
||||
hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
|
||||
/* Timing */
|
||||
Timing.AddressSetupTime = 15;
|
||||
Timing.AddressHoldTime = 15;
|
||||
Timing.DataSetupTime = 255;
|
||||
Timing.DataHoldTime = 0;
|
||||
Timing.BusTurnAroundDuration = 15;
|
||||
Timing.CLKDivision = 16;
|
||||
Timing.DataLatency = 17;
|
||||
Timing.AccessMode = FMC_ACCESS_MODE_A;
|
||||
/* ExtTiming */
|
||||
|
||||
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
|
||||
{
|
||||
Error_Handler( );
|
||||
}
|
||||
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
|
||||
{
|
||||
Error_Handler( );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -566,15 +566,15 @@ static void MX_FMC_Init(void)
|
||||
static void MX_GPIO_Init(void)
|
||||
{
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
|
||||
}
|
||||
|
||||
@ -588,10 +588,10 @@ static void MX_GPIO_Init(void)
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler_Debug */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
/* USER CODE BEGIN Error_Handler_Debug */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
|
||||
/* USER CODE END Error_Handler_Debug */
|
||||
/* USER CODE END Error_Handler_Debug */
|
||||
}
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
@ -603,11 +603,11 @@ void Error_Handler(void)
|
||||
* @retval None
|
||||
*/
|
||||
void assert_failed(char *file, uint32_t line)
|
||||
{
|
||||
/* USER CODE BEGIN 6 */
|
||||
/* User can add his own implementation to report the file name and line number,
|
||||
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||
/* USER CODE END 6 */
|
||||
{
|
||||
/* USER CODE BEGIN 6 */
|
||||
/* User can add his own implementation to report the file name and line number,
|
||||
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||
/* USER CODE END 6 */
|
||||
}
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
@ -6,69 +6,62 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
* 2019-04-09 jhb
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||
|
||||
/**Configure the main internal regulator output voltage
|
||||
*/
|
||||
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 30;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
/**Configure the main internal regulator output voltage
|
||||
*/
|
||||
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 30;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI
|
||||
|RCC_PERIPHCLK_LTDC;
|
||||
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
||||
PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY;
|
||||
PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2M = 2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2N = 8;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC;
|
||||
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
||||
PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY;
|
||||
PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2M = 2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2N = 8;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2;
|
||||
PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
static SRAM_HandleTypeDef hsram;
|
||||
static FMC_NORSRAM_TimingTypeDef SRAM_Timing;
|
||||
#ifdef RT_USING_MEMHEAP_AS_HEAP
|
||||
static struct rt_memheap system_heap;
|
||||
static struct rt_memheap system_heap;
|
||||
#endif
|
||||
|
||||
static int SRAM_Init(void)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user