[bsp][nxp][mcxa153] add pwm driver
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-08-1 hywing Initial version.
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "fsl_ctimer.h"
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#ifdef RT_USING_PWM
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typedef struct
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{
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struct rt_device_pwm pwm_device;
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CTIMER_Type *ct_instance;
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uint32_t timerClock;
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const ctimer_match_t pwmPeriodChannel;
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ctimer_match_t matchChannel;
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char *name;
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} mcx_pwm_obj_t;
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static mcx_pwm_obj_t mcx_pwm_list[]=
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{
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#ifdef BSP_USING_PWM0
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{
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.ct_instance = CTIMER1,
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.timerClock = 0,
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.pwmPeriodChannel = kCTIMER_Match_3,
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.matchChannel = kCTIMER_Match_2,
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.name = "pwm0",
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}
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#endif
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};
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volatile uint32_t g_pwmPeriod = 0U;
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volatile uint32_t g_pulsePeriod = 0U;
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static rt_err_t mcx_drv_pwm_get(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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return RT_EOK;
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}
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status_t CTIMER_GetPwmPeriodValue(uint32_t pwmFreqHz, uint8_t dutyCyclePercent, uint32_t timerClock_Hz)
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{
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g_pwmPeriod = (timerClock_Hz / pwmFreqHz) - 1U;
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g_pulsePeriod = (g_pwmPeriod + 1U) * (100 - dutyCyclePercent) / 100;
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return kStatus_Success;
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}
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static rt_err_t mcx_drv_pwm_set(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_Type *ct = pwm->ct_instance;
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uint32_t pwmFreqHz = 1000000000 / configuration->period;
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uint8_t dutyCyclePercent = configuration->pulse * 100 / configuration->period;
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CTIMER_GetPwmPeriodValue(pwmFreqHz, dutyCyclePercent, pwm->timerClock);
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CTIMER_SetupPwmPeriod(ct, kCTIMER_Match_3, kCTIMER_Match_2, g_pwmPeriod, g_pulsePeriod, false);
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return 0;
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}
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static rt_err_t mcx_drv_pwm_enable(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_StartTimer(pwm->ct_instance);
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return 0;
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}
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static rt_err_t mcx_drv_pwm_disable(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_StopTimer(pwm->ct_instance);
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return 0;
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}
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static rt_err_t mcx_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *args)
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{
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mcx_pwm_obj_t *pwm = device->parent.user_data;
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)args;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return mcx_drv_pwm_enable(pwm, configuration);
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case PWM_CMD_DISABLE:
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return mcx_drv_pwm_disable(pwm, configuration);
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case PWM_CMD_SET:
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return mcx_drv_pwm_set(pwm, configuration);
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case PWM_CMD_GET:
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return mcx_drv_pwm_get(pwm, configuration);
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default:
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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static struct rt_pwm_ops mcx_pwm_ops =
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{
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.control = mcx_drv_pwm_control,
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};
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int mcx_pwm_init(void)
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{
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rt_err_t ret;
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char name_buf[8];
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ctimer_config_t config;
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CTIMER_GetDefaultConfig(&config);
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for (uint8_t i = 0; i < ARRAY_SIZE(mcx_pwm_list); i++)
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{
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mcx_pwm_list[i].timerClock = CLOCK_GetCTimerClkFreq(1U) / (config.prescale + 1);
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CTIMER_Init(mcx_pwm_list[i].ct_instance, &config);
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ret = rt_device_pwm_register(&mcx_pwm_list[i].pwm_device, mcx_pwm_list[i].name, &mcx_pwm_ops, &mcx_pwm_list[i]);
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if (ret != RT_EOK)
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{
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return ret;
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}
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(mcx_pwm_init);
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#endif /* RT_USING_PWM */
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-02-26 Yilin Sun Initial version.
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*/
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#ifndef __DRV_PWM_H__
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#define __DRV_PWM_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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int mcx_pwm_init(void);
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#endif
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@ -125,28 +125,12 @@ menu "On-chip Peripheral Drivers"
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config BSP_USING_PWM
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bool "Enable PWM"
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select RT_USING_PWM
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default y
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default N
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if BSP_USING_PWM
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config BSP_USING_CTIMER1_MAT0
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bool "Enable CIMER1 Match0 as PWM output"
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default y
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config BSP_USING_CTIMER2_MAT0
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bool "Enable CIMER2 Match0 as PWM output"
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default n
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config BSP_USING_CTIMER2_MAT1
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bool "Enable CIMER2 Match1 as PWM output"
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default n
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config BSP_USING_CTIMER2_MAT2
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bool "Enable CIMER2 Match2 as PWM output"
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default n
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config BSP_USING_CTIMER3_MAT2
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bool "Enable CIMER3 Match2 as PWM output"
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default n
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config BSP_USING_PWM0
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bool "Enable PWM0"
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default N
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endif
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endmenu
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@ -44,10 +44,15 @@ void BOARD_InitPins(void)
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CLOCK_EnableClock(kCLOCK_GateGPIO2);
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CLOCK_EnableClock(kCLOCK_GateGPIO3);
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CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u);
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CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
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RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kCTIMER1_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
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@ -107,4 +112,33 @@ void BOARD_InitPins(void)
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kPORT_UnlockRegister};
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/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
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PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
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#ifdef BSP_USING_PWM0
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ctimer_config_t config;
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CTIMER_Init(CTIMER1, &config);
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const port_pin_config_t port1_4_pin62_config = {/* Internal pull-up/down resistor is disabled */
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kPORT_PullDisable,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Normal drive strength is configured */
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kPORT_NormalDriveStrength,
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/* Pin is configured as CT1_MAT2 */
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kPORT_MuxAlt4,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT1_4 (pin 62) is configured as CT1_MAT2 */
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PORT_SetPinConfig(PORT1, 4U, &port1_4_pin62_config);
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#endif
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}
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