[libcpu] remove libcpu/risc-v
This commit is contained in:
liang yongxiang
parent
ae98804dfb
commit
5faae3350c
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@ -1,18 +0,0 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = str(Dir('#'))
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src = Glob('*.c')
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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group = DefineGroup('', src, depend = [''], CPPPATH = [])
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#objs += group
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Return('objs')
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@ -1,236 +0,0 @@
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;/*
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; * File : context_gcc.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * This program is free software; you can redistribute it and/or modify
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; * it under the terms of the GNU General Public License as published by
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; * the Free Software Foundation; either version 2 of the License, or
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; * (at your option) any later version.
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; *
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; * This program is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; * GNU General Public License for more details.
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; *
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; * You should have received a copy of the GNU General Public License along
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; * with this program; if not, write to the Free Software Foundation, Inc.,
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; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2017-07-16 zhangjun for hifive1
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; */
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#include "encoding.h"
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#include "sifive/bits.h"
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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addi sp, sp, -12
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sw a5, (sp)
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li a5, 0x800
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csrr a0, mie
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blt a0, a5, 1f
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/* interrupt is enable before disable it*/
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addi a0, a0, 1
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li a5, 0x1
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addi a5, a5, -2048
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csrrc a5, mie, a5
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/* csrrc a5, mie, 128*/
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j 2f
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/* interrupt is disabled before disable it*/
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1:
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li a0, 0
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2:
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lw a5, (sp)
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addi sp, sp, 12
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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addi sp, sp, -12
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sw a5, (sp)
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beqz a0, 1f
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li a5, 0x1
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addi a5, a5, -2048
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csrrs a5, mie, a5
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/* csrrs a5, mie, 128*/
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1:
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lw a5, (sp)
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addi sp, sp, 12
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ret
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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addi sp, sp, -32*REGBYTES
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STORE sp, (a0)
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STORE x30, 1*REGBYTES(sp)
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STORE x31, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x10, 29*REGBYTES(sp)
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STORE x1, 30*REGBYTES(sp)
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STORE x1, 31*REGBYTES(sp)
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csrr x10, mie
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STORE x10, 0*REGBYTES(sp)
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/*
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*Remain in M-mode after mret
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*enable interrupt in M-mode
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*/
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li t0, 136
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csrrs t0, mstatus, t0
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LOAD sp, (a1)
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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csrw mepc,x10
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LOAD x10, 0*REGBYTES(sp)
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csrw mie, x10
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* a0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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csrw mepc,a0
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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addi sp, sp, -16
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sw s0, 12(sp)
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sw a0, 8(sp)
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sw a5, 4(sp)
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la a0, rt_thread_switch_interrupt_flag
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lw a5, (a0)
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bnez a5, _reswitch
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li a5, 1
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sw a5, (a0)
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la a5, rt_interrupt_from_thread
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lw a0, 8(sp)
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sw a0, (a5)
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_reswitch:
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la a5, rt_interrupt_to_thread
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sw a1, (a5)
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lw a5, 4(sp)
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lw a0, 8(sp)
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lw s0, 12(sp)
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addi sp, sp, 16
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ret
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File diff suppressed because it is too large
Load Diff
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@ -1,81 +0,0 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_HIFIVE1_H
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#define _SIFIVE_HIFIVE1_H
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#include <stdint.h>
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/****************************************************************************
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* GPIO Connections
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*****************************************************************************/
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// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
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// These are also mapped to RGB LEDs on the Freedom E300 Arty
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// FPGA
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// Dev Kit.
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#define RED_LED_OFFSET 22
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#define GREEN_LED_OFFSET 19
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#define BLUE_LED_OFFSET 21
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// These are the GPIO bit offsets for the differen digital pins
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// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
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#define PIN_0_OFFSET 16
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#define PIN_1_OFFSET 17
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#define PIN_2_OFFSET 18
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#define PIN_3_OFFSET 19
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#define PIN_4_OFFSET 20
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#define PIN_5_OFFSET 21
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#define PIN_6_OFFSET 22
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#define PIN_7_OFFSET 23
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#define PIN_8_OFFSET 0
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#define PIN_9_OFFSET 1
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#define PIN_10_OFFSET 2
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#define PIN_11_OFFSET 3
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#define PIN_12_OFFSET 4
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#define PIN_13_OFFSET 5
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//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
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#define PIN_15_OFFSET 9
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#define PIN_16_OFFSET 10
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#define PIN_17_OFFSET 11
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#define PIN_18_OFFSET 12
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#define PIN_19_OFFSET 13
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// These are *PIN* numbers, not
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// GPIO Offset Numbers.
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#define PIN_SPI1_SCK (13u)
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#define PIN_SPI1_MISO (12u)
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#define PIN_SPI1_MOSI (11u)
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#define PIN_SPI1_SS0 (10u)
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#define PIN_SPI1_SS1 (14u)
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#define PIN_SPI1_SS2 (15u)
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#define PIN_SPI1_SS3 (16u)
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#define SS_PIN_TO_CS_ID(x) \
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((x==PIN_SPI1_SS0 ? 0 : \
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(x==PIN_SPI1_SS1 ? 1 : \
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(x==PIN_SPI1_SS2 ? 2 : \
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(x==PIN_SPI1_SS3 ? 3 : \
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-1)))))
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// These buttons are present only on the Freedom E300 Arty Dev Kit.
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#ifdef HAS_BOARD_BUTTONS
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#define BUTTON_0_OFFSET 15
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#define BUTTON_1_OFFSET 30
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#define BUTTON_2_OFFSET 31
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#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
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#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
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#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
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#endif
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#define HAS_HFXOSC 1
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#define HAS_LFROSC_BYPASS 1
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#define RTC_FREQ 32768
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void write_hex(int fd, unsigned long int hex);
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#endif /* _SIFIVE_HIFIVE1_H */
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@ -1,210 +0,0 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <unistd.h>
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#include "platform.h"
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#include "encoding.h"
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extern int main(int argc, char** argv);
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extern void trap_entry();
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static unsigned long mtime_lo(void)
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{
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return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
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}
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#ifdef __riscv32
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static uint32_t mtime_hi(void)
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{
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return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
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}
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uint64_t get_timer_value()
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{
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while (1) {
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uint32_t hi = mtime_hi();
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uint32_t lo = mtime_lo();
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if (hi == mtime_hi())
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return ((uint64_t)hi << 32) | lo;
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}
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}
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#else /* __riscv32 */
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uint64_t get_timer_value()
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{
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return mtime_lo();
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}
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#endif
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unsigned long get_timer_freq()
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{
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return 32768;
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}
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static void use_hfrosc(int div, int trim)
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{
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// Make sure the HFROSC is running at its default setting
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PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
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while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
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}
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static void use_pll(int refsel, int bypass, int r, int f, int q)
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{
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// Ensure that we aren't running off the PLL before we mess with it.
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if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
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// Make sure the HFROSC is running at its default setting
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use_hfrosc(4, 16);
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}
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// Set PLL Source to be HFXOSC if available.
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uint32_t config_value = 0;
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config_value |= PLL_REFSEL(refsel);
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if (bypass) {
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// Bypass
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config_value |= PLL_BYPASS(1);
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// If we don't have an HFXTAL, this doesn't really matter.
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// Set our Final output divide to divide-by-1:
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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} else {
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// In case we are executing from QSPI,
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// (which is quite likely) we need to
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// set the QSPI clock divider appropriately
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// before boosting the clock frequency.
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// Div = f_sck/2
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SPI0_REG(SPI_REG_SCKDIV) = 8;
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// Set DIV Settings for PLL
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// Both HFROSC and HFXOSC are modeled as ideal
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// 16MHz sources (assuming dividers are set properly for
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// HFROSC).
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// (Legal values of f_REF are 6-48MHz)
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// Set DIVR to divide-by-2 to get 8MHz frequency
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// (legal values of f_R are 6-12 MHz)
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config_value |= PLL_BYPASS(1);
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config_value |= PLL_R(r);
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// Set DIVF to get 512Mhz frequncy
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// There is an implied multiply-by-2, 16Mhz.
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// So need to write 32-1
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// (legal values of f_F are 384-768 MHz)
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config_value |= PLL_F(f);
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// Set DIVQ to divide-by-2 to get 256 MHz frequency
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// (legal values of f_Q are 50-400Mhz)
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config_value |= PLL_Q(q);
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// Set our Final output divide to divide-by-1:
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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PRCI_REG(PRCI_PLLCFG) = config_value;
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// Un-Bypass the PLL.
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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// Wait for PLL Lock
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// Note that the Lock signal can be glitchy.
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// Need to wait 100 us
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// RTC is running at 32kHz.
|
||||
// So wait 4 ticks of RTC.
|
||||
uint32_t now = mtime_lo();
|
||||
while (mtime_lo() - now < 4) ;
|
||||
|
||||
// Now it is safe to check for PLL Lock
|
||||
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
|
||||
}
|
||||
|
||||
// Switch over to PLL Clock source
|
||||
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
|
||||
}
|
||||
|
||||
static void use_default_clocks()
|
||||
{
|
||||
// Turn off the LFROSC
|
||||
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
|
||||
|
||||
// Use HFROSC
|
||||
use_hfrosc(4, 16);
|
||||
}
|
||||
|
||||
static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
|
||||
{
|
||||
unsigned long start_mtime, delta_mtime;
|
||||
unsigned long mtime_freq = get_timer_freq();
|
||||
|
||||
// Don't start measuruing until we see an mtime tick
|
||||
unsigned long tmp = mtime_lo();
|
||||
do {
|
||||
start_mtime = mtime_lo();
|
||||
} while (start_mtime == tmp);
|
||||
|
||||
unsigned long start_mcycle = read_csr(mcycle);
|
||||
|
||||
do {
|
||||
delta_mtime = mtime_lo() - start_mtime;
|
||||
} while (delta_mtime < n);
|
||||
|
||||
unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
|
||||
|
||||
return (delta_mcycle / delta_mtime) * mtime_freq
|
||||
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
|
||||
}
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
static uint32_t cpu_freq;
|
||||
|
||||
if (!cpu_freq) {
|
||||
// warm up I$
|
||||
measure_cpu_freq(1);
|
||||
// measure for real
|
||||
cpu_freq = measure_cpu_freq(10);
|
||||
}
|
||||
|
||||
return cpu_freq;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
|
||||
void _init()
|
||||
{
|
||||
|
||||
#ifndef NO_INIT
|
||||
use_default_clocks();
|
||||
use_pll(0, 0, 1, 31, 1);
|
||||
|
||||
|
||||
write_csr(mtvec, &trap_entry);
|
||||
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
|
||||
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
|
||||
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
#define MCAUSE_INT 0x80000000
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFF
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/aon.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/otp.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/prci.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define OTP_MEM_ADDR _AC(0x00020000,UL)
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_CTRL_ADDR _AC(0x10000000,UL)
|
||||
#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
|
||||
#define OTP_CTRL_ADDR _AC(0x10010000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF masks
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
#define SPI11_NUM_SS (4)
|
||||
#define IOF_SPI1_SS0 (2u)
|
||||
#define IOF_SPI1_SS1 (8u)
|
||||
#define IOF_SPI1_SS2 (9u)
|
||||
#define IOF_SPI1_SS3 (10u)
|
||||
#define IOF_SPI1_MOSI (3u)
|
||||
#define IOF_SPI1_MISO (4u)
|
||||
#define IOF_SPI1_SCK (5u)
|
||||
#define IOF_SPI1_DQ0 (3u)
|
||||
#define IOF_SPI1_DQ1 (4u)
|
||||
#define IOF_SPI1_DQ2 (6u)
|
||||
#define IOF_SPI1_DQ3 (7u)
|
||||
|
||||
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
|
||||
#define SPI2_NUM_SS (1)
|
||||
#define IOF_SPI2_SS0 (26u)
|
||||
#define IOF_SPI2_MOSI (27u)
|
||||
#define IOF_SPI2_MISO (28u)
|
||||
#define IOF_SPI2_SCK (29u)
|
||||
#define IOF_SPI2_DQ0 (27u)
|
||||
#define IOF_SPI2_DQ1 (28u)
|
||||
#define IOF_SPI2_DQ2 (30u)
|
||||
#define IOF_SPI2_DQ3 (31u)
|
||||
|
||||
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
|
||||
|
||||
#define IOF0_UART0_MASK _AC(0x00030000, UL)
|
||||
#define IOF_UART0_RX (16u)
|
||||
#define IOF_UART0_TX (17u)
|
||||
|
||||
#define IOF0_UART1_MASK _AC(0x03000000, UL)
|
||||
#define IOF_UART1_RX (24u)
|
||||
#define IOF_UART1_TX (25u)
|
||||
|
||||
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
|
||||
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
|
||||
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
|
||||
|
||||
// Interrupt numbers
|
||||
#define INT_RESERVED 0
|
||||
#define INT_WDOGCMP 1
|
||||
#define INT_RTCCMP 2
|
||||
#define INT_UART0_BASE 3
|
||||
#define INT_UART1_BASE 4
|
||||
#define INT_SPI0_BASE 5
|
||||
#define INT_SPI1_BASE 6
|
||||
#define INT_SPI2_BASE 7
|
||||
#define INT_GPIO_BASE 8
|
||||
#define INT_PWM0_BASE 40
|
||||
#define INT_PWM1_BASE 44
|
||||
#define INT_PWM2_BASE 48
|
||||
|
||||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define NUM_GPIO 32
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 52
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#include "hifive1.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _RISCV_BITS_H
|
||||
#define _RISCV_BITS_H
|
||||
|
||||
#define likely(x) __builtin_expect((x), 1)
|
||||
#define unlikely(x) __builtin_expect((x), 0)
|
||||
|
||||
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
|
||||
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
|
||||
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
|
||||
|
||||
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
|
||||
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
|
||||
|
||||
#define STR(x) XSTR(x)
|
||||
#define XSTR(x) #x
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
# define SLL32 sllw
|
||||
# define STORE sd
|
||||
# define LOAD ld
|
||||
# define LWU lwu
|
||||
# define LOG_REGBYTES 3
|
||||
#else
|
||||
# define SLL32 sll
|
||||
# define STORE sw
|
||||
# define LOAD lw
|
||||
# define LWU lw
|
||||
# define LOG_REGBYTES 2
|
||||
#endif
|
||||
#define REGBYTES (1 << LOG_REGBYTES)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
/* Derived from <linux/const.h> */
|
||||
|
||||
#ifndef _SIFIVE_CONST_H
|
||||
#define _SIFIVE_CONST_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define _AC(X,Y) X
|
||||
#define _AT(T,X) X
|
||||
#else
|
||||
#define _AC(X,Y) (X##Y)
|
||||
#define _AT(T,X) ((T)(X))
|
||||
#endif /* !__ASSEMBLER__*/
|
||||
|
||||
#define _BITUL(x) (_AC(1,UL) << (x))
|
||||
#define _BITULL(x) (_AC(1,ULL) << (x))
|
||||
|
||||
#endif /* _SIFIVE_CONST_H */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_AON_H
|
||||
#define _SIFIVE_AON_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define AON_WDOGCFG 0x000
|
||||
#define AON_WDOGCOUNT 0x008
|
||||
#define AON_WDOGS 0x010
|
||||
#define AON_WDOGFEED 0x018
|
||||
#define AON_WDOGKEY 0x01C
|
||||
#define AON_WDOGCMP 0x020
|
||||
|
||||
#define AON_RTCCFG 0x040
|
||||
#define AON_RTCLO 0x048
|
||||
#define AON_RTCHI 0x04C
|
||||
#define AON_RTCS 0x050
|
||||
#define AON_RTCCMP 0x060
|
||||
|
||||
#define AON_BACKUP0 0x080
|
||||
#define AON_BACKUP1 0x084
|
||||
#define AON_BACKUP2 0x088
|
||||
#define AON_BACKUP3 0x08C
|
||||
#define AON_BACKUP4 0x090
|
||||
#define AON_BACKUP5 0x094
|
||||
#define AON_BACKUP6 0x098
|
||||
#define AON_BACKUP7 0x09C
|
||||
#define AON_BACKUP8 0x0A0
|
||||
#define AON_BACKUP9 0x0A4
|
||||
#define AON_BACKUP10 0x0A8
|
||||
#define AON_BACKUP11 0x0AC
|
||||
#define AON_BACKUP12 0x0B0
|
||||
#define AON_BACKUP13 0x0B4
|
||||
#define AON_BACKUP14 0x0B8
|
||||
#define AON_BACKUP15 0x0BC
|
||||
|
||||
#define AON_PMUWAKEUPI0 0x100
|
||||
#define AON_PMUWAKEUPI1 0x104
|
||||
#define AON_PMUWAKEUPI2 0x108
|
||||
#define AON_PMUWAKEUPI3 0x10C
|
||||
#define AON_PMUWAKEUPI4 0x110
|
||||
#define AON_PMUWAKEUPI5 0x114
|
||||
#define AON_PMUWAKEUPI6 0x118
|
||||
#define AON_PMUWAKEUPI7 0x11C
|
||||
#define AON_PMUSLEEPI0 0x120
|
||||
#define AON_PMUSLEEPI1 0x124
|
||||
#define AON_PMUSLEEPI2 0x128
|
||||
#define AON_PMUSLEEPI3 0x12C
|
||||
#define AON_PMUSLEEPI4 0x130
|
||||
#define AON_PMUSLEEPI5 0x134
|
||||
#define AON_PMUSLEEPI6 0x138
|
||||
#define AON_PMUSLEEPI7 0x13C
|
||||
#define AON_PMUIE 0x140
|
||||
#define AON_PMUCAUSE 0x144
|
||||
#define AON_PMUSLEEP 0x148
|
||||
#define AON_PMUKEY 0x14C
|
||||
|
||||
#define AON_LFROSC 0x070
|
||||
/* Constants */
|
||||
|
||||
#define AON_WDOGKEY_VALUE 0x51F15E
|
||||
#define AON_WDOGFEED_VALUE 0xD09F00D
|
||||
|
||||
#define AON_WDOGCFG_SCALE 0x0000000F
|
||||
#define AON_WDOGCFG_RSTEN 0x00000100
|
||||
#define AON_WDOGCFG_ZEROCMP 0x00000200
|
||||
#define AON_WDOGCFG_ENALWAYS 0x00001000
|
||||
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
|
||||
#define AON_WDOGCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_RTCCFG_SCALE 0x0000000F
|
||||
#define AON_RTCCFG_ENALWAYS 0x00001000
|
||||
#define AON_RTCCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_WAKEUPCAUSE_RESET 0x00
|
||||
#define AON_WAKEUPCAUSE_RTC 0x01
|
||||
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
|
||||
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
|
||||
|
||||
#define AON_RESETCAUSE_POWERON 0x0000
|
||||
#define AON_RESETCAUSE_EXTERNAL 0x0100
|
||||
#define AON_RESETCAUSE_WATCHDOG 0x0200
|
||||
|
||||
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
|
||||
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
|
||||
|
||||
#endif /* _SIFIVE_AON_H */
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
// See LICENSE for license details
|
||||
|
||||
#ifndef _SIFIVE_CLINT_H
|
||||
#define _SIFIVE_CLINT_H
|
||||
|
||||
|
||||
#define CLINT_MSIP 0x0000
|
||||
#define CLINT_MSIP_size 0x4
|
||||
#define CLINT_MTIMECMP 0x4000
|
||||
#define CLINT_MTIMECMP_size 0x8
|
||||
#define CLINT_MTIME 0xBFF8
|
||||
#define CLINT_MTIME_size 0x8
|
||||
|
||||
#endif /* _SIFIVE_CLINT_H */
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_GPIO_H
|
||||
#define _SIFIVE_GPIO_H
|
||||
|
||||
#define GPIO_INPUT_VAL (0x00)
|
||||
#define GPIO_INPUT_EN (0x04)
|
||||
#define GPIO_OUTPUT_EN (0x08)
|
||||
#define GPIO_OUTPUT_VAL (0x0C)
|
||||
#define GPIO_PULLUP_EN (0x10)
|
||||
#define GPIO_DRIVE (0x14)
|
||||
#define GPIO_RISE_IE (0x18)
|
||||
#define GPIO_RISE_IP (0x1C)
|
||||
#define GPIO_FALL_IE (0x20)
|
||||
#define GPIO_FALL_IP (0x24)
|
||||
#define GPIO_HIGH_IE (0x28)
|
||||
#define GPIO_HIGH_IP (0x2C)
|
||||
#define GPIO_LOW_IE (0x30)
|
||||
#define GPIO_LOW_IP (0x34)
|
||||
#define GPIO_IOF_EN (0x38)
|
||||
#define GPIO_IOF_SEL (0x3C)
|
||||
#define GPIO_OUTPUT_XOR (0x40)
|
||||
|
||||
#endif /* _SIFIVE_GPIO_H */
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_OTP_H
|
||||
#define _SIFIVE_OTP_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define OTP_LOCK 0x00
|
||||
#define OTP_CK 0x04
|
||||
#define OTP_OE 0x08
|
||||
#define OTP_SEL 0x0C
|
||||
#define OTP_WE 0x10
|
||||
#define OTP_MR 0x14
|
||||
#define OTP_MRR 0x18
|
||||
#define OTP_MPP 0x1C
|
||||
#define OTP_VRREN 0x20
|
||||
#define OTP_VPPEN 0x24
|
||||
#define OTP_A 0x28
|
||||
#define OTP_D 0x2C
|
||||
#define OTP_Q 0x30
|
||||
#define OTP_READ_TIMINGS 0x34
|
||||
|
||||
#endif
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef PLIC_H
|
||||
#define PLIC_H
|
||||
|
||||
#include <sifive/const.h>
|
||||
|
||||
// 32 bits per source
|
||||
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
|
||||
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
|
||||
// 1 bit per source (1 address)
|
||||
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
|
||||
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
|
||||
|
||||
//0x80 per target
|
||||
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
|
||||
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
|
||||
|
||||
|
||||
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
|
||||
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
|
||||
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
|
||||
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
|
||||
|
||||
#define PLIC_MAX_SOURCE 1023
|
||||
#define PLIC_SOURCE_MASK 0x3FF
|
||||
|
||||
#define PLIC_MAX_TARGET 15871
|
||||
#define PLIC_TARGET_MASK 0x3FFF
|
||||
|
||||
#endif /* PLIC_H */
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PRCI_H
|
||||
#define _SIFIVE_PRCI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PRCI_HFROSCCFG (0x0000)
|
||||
#define PRCI_HFXOSCCFG (0x0004)
|
||||
#define PRCI_PLLCFG (0x0008)
|
||||
#define PRCI_PLLDIV (0x000C)
|
||||
#define PRCI_PROCMONCFG (0x00F0)
|
||||
|
||||
/* Fields */
|
||||
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
|
||||
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
|
||||
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
|
||||
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
|
||||
|
||||
#define XOSC_EN(x) (((x) & 0x1) << 30)
|
||||
#define XOSC_RDY(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R(x) (((x) & 0x7) << 0)
|
||||
// single reserved bit for F LSB.
|
||||
#define PLL_F(x) (((x) & 0x3F) << 4)
|
||||
#define PLL_Q(x) (((x) & 0x3) << 10)
|
||||
#define PLL_SEL(x) (((x) & 0x1) << 16)
|
||||
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
|
||||
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
|
||||
#define PLL_LOCK(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R_default 0x1
|
||||
#define PLL_F_default 0x1F
|
||||
#define PLL_Q_default 0x3
|
||||
|
||||
#define PLL_REFSEL_HFROSC 0x0
|
||||
#define PLL_REFSEL_HFXOSC 0x1
|
||||
|
||||
#define PLL_SEL_HFROSC 0x0
|
||||
#define PLL_SEL_PLL 0x1
|
||||
|
||||
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
|
||||
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
|
||||
|
||||
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
|
||||
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
|
||||
#define PROCMON_EN(x) (((x) & 0x1) << 16)
|
||||
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
|
||||
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
|
||||
|
||||
#define PROCMON_SEL_HFCLK 0
|
||||
#define PROCMON_SEL_HFXOSCIN 1
|
||||
#define PROCMON_SEL_PLLOUTDIV 2
|
||||
#define PROCMON_SEL_PROCMON 3
|
||||
|
||||
#endif // _SIFIVE_PRCI_H
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PWM_H
|
||||
#define _SIFIVE_PWM_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PWM_CFG 0x00
|
||||
#define PWM_COUNT 0x08
|
||||
#define PWM_S 0x10
|
||||
#define PWM_CMP0 0x20
|
||||
#define PWM_CMP1 0x24
|
||||
#define PWM_CMP2 0x28
|
||||
#define PWM_CMP3 0x2C
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define PWM_CFG_SCALE 0x0000000F
|
||||
#define PWM_CFG_STICKY 0x00000100
|
||||
#define PWM_CFG_ZEROCMP 0x00000200
|
||||
#define PWM_CFG_DEGLITCH 0x00000400
|
||||
#define PWM_CFG_ENALWAYS 0x00001000
|
||||
#define PWM_CFG_ONESHOT 0x00002000
|
||||
#define PWM_CFG_CMP0CENTER 0x00010000
|
||||
#define PWM_CFG_CMP1CENTER 0x00020000
|
||||
#define PWM_CFG_CMP2CENTER 0x00040000
|
||||
#define PWM_CFG_CMP3CENTER 0x00080000
|
||||
#define PWM_CFG_CMP0GANG 0x01000000
|
||||
#define PWM_CFG_CMP1GANG 0x02000000
|
||||
#define PWM_CFG_CMP2GANG 0x04000000
|
||||
#define PWM_CFG_CMP3GANG 0x08000000
|
||||
#define PWM_CFG_CMP0IP 0x10000000
|
||||
#define PWM_CFG_CMP1IP 0x20000000
|
||||
#define PWM_CFG_CMP2IP 0x40000000
|
||||
#define PWM_CFG_CMP3IP 0x80000000
|
||||
|
||||
#endif /* _SIFIVE_PWM_H */
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_SPI_H
|
||||
#define _SIFIVE_SPI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define SPI_REG_SCKDIV 0x00
|
||||
#define SPI_REG_SCKMODE 0x04
|
||||
#define SPI_REG_CSID 0x10
|
||||
#define SPI_REG_CSDEF 0x14
|
||||
#define SPI_REG_CSMODE 0x18
|
||||
|
||||
#define SPI_REG_DCSSCK 0x28
|
||||
#define SPI_REG_DSCKCS 0x2a
|
||||
#define SPI_REG_DINTERCS 0x2c
|
||||
#define SPI_REG_DINTERXFR 0x2e
|
||||
|
||||
#define SPI_REG_FMT 0x40
|
||||
#define SPI_REG_TXFIFO 0x48
|
||||
#define SPI_REG_RXFIFO 0x4c
|
||||
#define SPI_REG_TXCTRL 0x50
|
||||
#define SPI_REG_RXCTRL 0x54
|
||||
|
||||
#define SPI_REG_FCTRL 0x60
|
||||
#define SPI_REG_FFMT 0x64
|
||||
|
||||
#define SPI_REG_IE 0x70
|
||||
#define SPI_REG_IP 0x74
|
||||
|
||||
/* Fields */
|
||||
|
||||
#define SPI_SCK_POL 0x1
|
||||
#define SPI_SCK_PHA 0x2
|
||||
|
||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
||||
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
|
||||
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
|
||||
|
||||
/* TXCTRL register */
|
||||
#define SPI_TXWM(x) ((x) & 0xffff)
|
||||
/* RXCTRL register */
|
||||
#define SPI_RXWM(x) ((x) & 0xffff)
|
||||
|
||||
#define SPI_IP_TXWM 0x1
|
||||
#define SPI_IP_RXWM 0x2
|
||||
|
||||
#define SPI_FCTRL_EN 0x1
|
||||
|
||||
#define SPI_INSN_CMD_EN 0x1
|
||||
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
|
||||
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
|
||||
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
|
||||
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
|
||||
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
|
||||
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
|
||||
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
|
||||
|
||||
#define SPI_TXFIFO_FULL (1 << 31)
|
||||
#define SPI_RXFIFO_EMPTY (1 << 31)
|
||||
|
||||
/* Values */
|
||||
|
||||
#define SPI_CSMODE_AUTO 0
|
||||
#define SPI_CSMODE_HOLD 2
|
||||
#define SPI_CSMODE_OFF 3
|
||||
|
||||
#define SPI_DIR_RX 0
|
||||
#define SPI_DIR_TX 1
|
||||
|
||||
#define SPI_PROTO_S 0
|
||||
#define SPI_PROTO_D 1
|
||||
#define SPI_PROTO_Q 2
|
||||
|
||||
#define SPI_ENDIAN_MSB 0
|
||||
#define SPI_ENDIAN_LSB 1
|
||||
|
||||
|
||||
#endif /* _SIFIVE_SPI_H */
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_UART_H
|
||||
#define _SIFIVE_UART_H
|
||||
|
||||
/* Register offsets */
|
||||
#define UART_REG_TXFIFO 0x00
|
||||
#define UART_REG_RXFIFO 0x04
|
||||
#define UART_REG_TXCTRL 0x08
|
||||
#define UART_REG_RXCTRL 0x0c
|
||||
#define UART_REG_IE 0x10
|
||||
#define UART_REG_IP 0x14
|
||||
#define UART_REG_DIV 0x18
|
||||
|
||||
/* TXCTRL register */
|
||||
#define UART_TXEN 0x1
|
||||
#define UART_TXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* RXCTRL register */
|
||||
#define UART_RXEN 0x1
|
||||
#define UART_RXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* IP register */
|
||||
#define UART_IP_TXWM 0x1
|
||||
#define UART_IP_RXWM 0x2
|
||||
|
||||
#endif /* _SIFIVE_UART_H */
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
extern unsigned char _rom[];
|
||||
extern unsigned char _rom_end[];
|
||||
|
||||
extern unsigned char _ram[];
|
||||
extern unsigned char _ram_end[];
|
||||
|
||||
extern unsigned char _ftext[];
|
||||
extern unsigned char _etext[];
|
||||
extern unsigned char _fbss[];
|
||||
extern unsigned char _ebss[];
|
||||
extern unsigned char _end[];
|
||||
|
||||
#endif /* _SECTIONS_H */
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 42f
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-07-31 zhangjun copy from mini2440
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
|
||||
//stk = (rt_uint32_t*)stack_addr;
|
||||
stack_addr += sizeof(rt_uint32_t);
|
||||
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
|
||||
stk = (rt_uint32_t *)stack_addr;
|
||||
|
||||
*(--stk) = (rt_uint32_t)tentry; /* entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* ra */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* a0 */
|
||||
*(--stk) = 0xffffffff; /* a1 */
|
||||
*(--stk) = 0xffffffff; /* a2 */
|
||||
*(--stk) = 0xffffffff; /* a3 */
|
||||
*(--stk) = 0xffffffff; /* a4 */
|
||||
*(--stk) = 0xffffffff; /* a5 */
|
||||
*(--stk) = 0xffffffff; /* a6 */
|
||||
*(--stk) = 0xffffffff; /* a7 */
|
||||
*(--stk) = 0xffffffff; /* s0/fp */
|
||||
*(--stk) = 0xffffffff; /* s1 */
|
||||
*(--stk) = 0xffffffff; /* s2 */
|
||||
*(--stk) = 0xffffffff; /* s3 */
|
||||
*(--stk) = 0xffffffff; /* s4 */
|
||||
*(--stk) = 0xffffffff; /* s5 */
|
||||
*(--stk) = 0xffffffff; /* s6 */
|
||||
*(--stk) = 0xffffffff; /* s7 */
|
||||
*(--stk) = 0xffffffff; /* s8 */
|
||||
*(--stk) = 0xffffffff; /* s9 */
|
||||
*(--stk) = 0xffffffff; /* s10*/
|
||||
*(--stk) = 0xffffffff; /* s11*/
|
||||
*(--stk) = 0xffffffff; /* t0 */
|
||||
*(--stk) = 0xffffffff; /* t1 */
|
||||
*(--stk) = 0xffffffff; /* t2 */
|
||||
*(--stk) = 0xffffffff; /* t3 */
|
||||
*(--stk) = 0xffffffff; /* t4 */
|
||||
*(--stk) = 0xffffffff; /* t5 */
|
||||
*(--stk) = 0xffffffff; /* t6 */
|
||||
*(--stk) = 0xffffffff; /* tp */
|
||||
*(--stk) = 0xffffffff; /* gp */
|
||||
*(--stk) = 0x880; /* mie */
|
||||
// *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
|
@ -1,297 +0,0 @@
|
|||
;/*
|
||||
; * File : start_gcc.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * This program is free software; you can redistribute it and/or modify
|
||||
; * it under the terms of the GNU General Public License as published by
|
||||
; * the Free Software Foundation; either version 2 of the License, or
|
||||
; * (at your option) any later version.
|
||||
; *
|
||||
; * This program is distributed in the hope that it will be useful,
|
||||
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; * GNU General Public License for more details.
|
||||
; *
|
||||
; * You should have received a copy of the GNU General Public License along
|
||||
; * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2017-07-16 zhangjun for hifive1
|
||||
; */
|
||||
#include "sifive/smp.h"
|
||||
#define CLINT_CTRL_ADDR 0x02000000
|
||||
|
||||
.section .init
|
||||
.globl _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
.cfi_startproc
|
||||
.cfi_undefined ra
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
la sp, _sp
|
||||
/*
|
||||
*disable all interrupt at startup
|
||||
*/
|
||||
csrrc a5, mstatus, 0xb
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_pause(t0, t1)
|
||||
#endif
|
||||
|
||||
/* Load data section */
|
||||
la a0, _data_lma
|
||||
la a1, _data
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
|
||||
/* Clear bss section */
|
||||
la a0, __bss_start
|
||||
la a1, _end
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
|
||||
/* Call global constructors */
|
||||
la a0, __libc_fini_array
|
||||
call atexit
|
||||
call __libc_init_array
|
||||
/*call _init directly in rt-thread*/
|
||||
call _init
|
||||
|
||||
#ifndef __riscv_float_abi_soft
|
||||
/* Enable FPU */
|
||||
li t0, MSTATUS_FS
|
||||
csrs mstatus, t0
|
||||
csrr t1, mstatus
|
||||
and t1, t1, t0
|
||||
beqz t1, 1f
|
||||
fssr x0
|
||||
1:
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_resume(t0, t1)
|
||||
|
||||
csrr a0, mhartid
|
||||
bnez a0, 2f
|
||||
#endif
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
/* argc = argv = 0 */
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
call main
|
||||
tail exit
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
2:
|
||||
la t0, trap_entry
|
||||
csrw mtvec, t0
|
||||
|
||||
csrr a0, mhartid
|
||||
la t1, _sp
|
||||
slli t0, a0, 10
|
||||
sub sp, t1, t0
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
call secondary_main
|
||||
tail exit
|
||||
|
||||
1:
|
||||
j 1b
|
||||
#endif
|
||||
.cfi_endproc
|
||||
|
||||
#include "encoding.h"
|
||||
#include "sifive/bits.h"
|
||||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
addi sp, sp, -32*REGBYTES
|
||||
|
||||
STORE x30, 1*REGBYTES(sp)
|
||||
STORE x31, 2*REGBYTES(sp)
|
||||
STORE x3, 3*REGBYTES(sp)
|
||||
STORE x4, 4*REGBYTES(sp)
|
||||
STORE x5, 5*REGBYTES(sp)
|
||||
STORE x6, 6*REGBYTES(sp)
|
||||
STORE x7, 7*REGBYTES(sp)
|
||||
STORE x8, 8*REGBYTES(sp)
|
||||
STORE x9, 9*REGBYTES(sp)
|
||||
STORE x10, 10*REGBYTES(sp)
|
||||
STORE x11, 11*REGBYTES(sp)
|
||||
STORE x12, 12*REGBYTES(sp)
|
||||
STORE x13, 13*REGBYTES(sp)
|
||||
STORE x14, 14*REGBYTES(sp)
|
||||
STORE x15, 15*REGBYTES(sp)
|
||||
STORE x16, 16*REGBYTES(sp)
|
||||
STORE x17, 17*REGBYTES(sp)
|
||||
STORE x18, 18*REGBYTES(sp)
|
||||
STORE x19, 19*REGBYTES(sp)
|
||||
STORE x20, 20*REGBYTES(sp)
|
||||
STORE x21, 21*REGBYTES(sp)
|
||||
STORE x22, 22*REGBYTES(sp)
|
||||
STORE x23, 23*REGBYTES(sp)
|
||||
STORE x24, 24*REGBYTES(sp)
|
||||
STORE x25, 25*REGBYTES(sp)
|
||||
STORE x26, 26*REGBYTES(sp)
|
||||
STORE x27, 27*REGBYTES(sp)
|
||||
STORE x28, 28*REGBYTES(sp)
|
||||
STORE x10, 29*REGBYTES(sp)
|
||||
STORE x1, 30*REGBYTES(sp)
|
||||
csrr x10, mepc
|
||||
STORE x10, 31*REGBYTES(sp)
|
||||
csrr x10, mie
|
||||
STORE x10, 0*REGBYTES(sp)
|
||||
|
||||
|
||||
/*
|
||||
*Remain in M-mode after mret
|
||||
*enable interrupt in M-mode
|
||||
*/
|
||||
li t0, MSTATUS_MPP
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
call rt_interrupt_enter
|
||||
csrr a0, mcause
|
||||
lui a5, 0x80000
|
||||
not a5, a5
|
||||
and a5, a5, a0
|
||||
li a4, 11
|
||||
mv s1, a1
|
||||
/*Machine external interrupt*/
|
||||
bne a5, a4, 1f
|
||||
call rt_hw_trap_irq
|
||||
1:
|
||||
/*Machine timer interrupt*/
|
||||
li a4, 7
|
||||
bne a5, a4, 2f
|
||||
call rt_systick_handler
|
||||
2:
|
||||
call rt_interrupt_leave
|
||||
|
||||
la a0, rt_thread_switch_interrupt_flag
|
||||
lw a1, (a0)
|
||||
bnez a1, rt_hw_context_switch_interrupt_do
|
||||
|
||||
|
||||
LOAD x30, 1*REGBYTES(sp)
|
||||
LOAD x31, 2*REGBYTES(sp)
|
||||
LOAD x3, 3*REGBYTES(sp)
|
||||
LOAD x4, 4*REGBYTES(sp)
|
||||
LOAD x5, 5*REGBYTES(sp)
|
||||
LOAD x6, 6*REGBYTES(sp)
|
||||
LOAD x7, 7*REGBYTES(sp)
|
||||
LOAD x8, 8*REGBYTES(sp)
|
||||
LOAD x9, 9*REGBYTES(sp)
|
||||
LOAD x29, 10*REGBYTES(sp)
|
||||
LOAD x11, 11*REGBYTES(sp)
|
||||
LOAD x12, 12*REGBYTES(sp)
|
||||
LOAD x13, 13*REGBYTES(sp)
|
||||
LOAD x14, 14*REGBYTES(sp)
|
||||
LOAD x15, 15*REGBYTES(sp)
|
||||
LOAD x16, 16*REGBYTES(sp)
|
||||
LOAD x17, 17*REGBYTES(sp)
|
||||
LOAD x18, 18*REGBYTES(sp)
|
||||
LOAD x19, 19*REGBYTES(sp)
|
||||
LOAD x20, 20*REGBYTES(sp)
|
||||
LOAD x21, 21*REGBYTES(sp)
|
||||
LOAD x22, 22*REGBYTES(sp)
|
||||
LOAD x23, 23*REGBYTES(sp)
|
||||
LOAD x24, 24*REGBYTES(sp)
|
||||
LOAD x25, 25*REGBYTES(sp)
|
||||
LOAD x26, 26*REGBYTES(sp)
|
||||
LOAD x27, 27*REGBYTES(sp)
|
||||
LOAD x28, 28*REGBYTES(sp)
|
||||
LOAD x10, 31*REGBYTES(sp)
|
||||
csrw mepc,x10
|
||||
LOAD x10, 0*REGBYTES(sp)
|
||||
csrw mie, x10
|
||||
LOAD x10, 29*REGBYTES(sp)
|
||||
LOAD x1, 30*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 32*REGBYTES
|
||||
mret
|
||||
|
||||
rt_hw_context_switch_interrupt_do:
|
||||
/*clear rt_thread_switch_interrupt_flag*/
|
||||
la a0, rt_thread_switch_interrupt_flag
|
||||
li a5, 0
|
||||
sw a5, (a0)
|
||||
|
||||
LOAD a0, rt_interrupt_from_thread
|
||||
STORE sp, (a0)
|
||||
LOAD a0, rt_interrupt_to_thread
|
||||
LOAD sp, (a0)
|
||||
LOAD x30, 1*REGBYTES(sp)
|
||||
LOAD x31, 2*REGBYTES(sp)
|
||||
LOAD x3, 3*REGBYTES(sp)
|
||||
LOAD x4, 4*REGBYTES(sp)
|
||||
LOAD x5, 5*REGBYTES(sp)
|
||||
LOAD x6, 6*REGBYTES(sp)
|
||||
LOAD x7, 7*REGBYTES(sp)
|
||||
LOAD x8, 8*REGBYTES(sp)
|
||||
LOAD x9, 9*REGBYTES(sp)
|
||||
LOAD x29, 10*REGBYTES(sp)
|
||||
LOAD x11, 11*REGBYTES(sp)
|
||||
LOAD x12, 12*REGBYTES(sp)
|
||||
LOAD x13, 13*REGBYTES(sp)
|
||||
LOAD x14, 14*REGBYTES(sp)
|
||||
LOAD x15, 15*REGBYTES(sp)
|
||||
LOAD x16, 16*REGBYTES(sp)
|
||||
LOAD x17, 17*REGBYTES(sp)
|
||||
LOAD x18, 18*REGBYTES(sp)
|
||||
LOAD x19, 19*REGBYTES(sp)
|
||||
LOAD x20, 20*REGBYTES(sp)
|
||||
LOAD x21, 21*REGBYTES(sp)
|
||||
LOAD x22, 22*REGBYTES(sp)
|
||||
LOAD x23, 23*REGBYTES(sp)
|
||||
LOAD x24, 24*REGBYTES(sp)
|
||||
LOAD x25, 25*REGBYTES(sp)
|
||||
LOAD x26, 26*REGBYTES(sp)
|
||||
LOAD x27, 27*REGBYTES(sp)
|
||||
LOAD x28, 28*REGBYTES(sp)
|
||||
LOAD x10, 31*REGBYTES(sp)
|
||||
csrw mepc,x10
|
||||
LOAD x10, 0*REGBYTES(sp)
|
||||
csrw mie, x10
|
||||
LOAD x10, 29*REGBYTES(sp)
|
||||
LOAD x1, 30*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 32*REGBYTES
|
||||
mret
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <platform.h>
|
||||
#include <encoding.h>
|
||||
#include "interrupt.h"
|
||||
extern struct rt_irq_desc irq_desc[];
|
||||
extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
|
||||
void rt_hw_trap_irq()
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
rt_uint32_t irq;
|
||||
void *param;
|
||||
|
||||
/* get irq number */
|
||||
irq = rt_hw_interrupt_get_active(0);
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = irq_desc[irq].handler;
|
||||
param = irq_desc[irq].param;
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq, param);
|
||||
rt_hw_interrupt_ack(0, irq);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
irq_desc[irq].counter ++;
|
||||
#endif
|
||||
}
|
||||
void handle_m_ext_interrupt()
|
||||
{
|
||||
}
|
||||
void rt_systick_handler(void)
|
||||
{
|
||||
clear_csr(mie, MIP_MTIP);
|
||||
|
||||
// Reset the timer for 3s in the future.
|
||||
// This also clears the existing timer interrupt.
|
||||
|
||||
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
|
||||
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
|
||||
uint64_t now = *mtime;
|
||||
uint64_t then = now + 2 * RTC_FREQ/RT_TICK_PER_SECOND;
|
||||
*mtimecmp = then;
|
||||
rt_tick_increase();
|
||||
|
||||
// read the current value of the LEDS and invert them.
|
||||
/*
|
||||
GPIO_REG(GPIO_OUTPUT_VAL) ^= ((0x1 << RED_LED_OFFSET) |
|
||||
(0x1 << GREEN_LED_OFFSET) |
|
||||
(0x1 << BLUE_LED_OFFSET));
|
||||
*/
|
||||
|
||||
// Re-enable the timer interrupt.
|
||||
set_csr(mie, MIP_MTIP);
|
||||
}
|
||||
Loading…
Reference in New Issue