Merge pull request #1330 from balanceTWK/master
[BSP][i.mxrt1052] fix uart
This commit is contained in:
commit
5f81f8e771
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@ -78,9 +78,8 @@ static void BOARD_BootClockRUN(void)
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CLOCK_DeinitEnetPll();
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CLOCK_DeinitEnetPll();
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CLOCK_DeinitUsb2Pll();
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CLOCK_DeinitUsb2Pll();
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/* Configure UART divider to default */
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/* iomuxc clock (iomuxc_clk_enable): 0x03u */
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CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
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/* Update core clock */
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/* Update core clock */
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SystemCoreClockUpdate();
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SystemCoreClockUpdate();
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@ -191,13 +190,13 @@ void rt_hw_board_init()
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#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
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rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
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rt_system_heap_init((void *)SDRAM_BEGIN, (void*)SDRAM_END);
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rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END);
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
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rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
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#else
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#else
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_system_heap_init((void *)HEAP_BEGIN, (void*)HEAP_END);
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#endif
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#endif
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#endif
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@ -21,7 +21,6 @@
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#ifdef RT_USING_SERIAL
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#ifdef RT_USING_SERIAL
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/* GPIO外设时钟会在LPUART_Init中自动配置, 如果定义了以下宏则不会自动配置 */
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#endif
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#endif
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@ -41,10 +40,10 @@
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/* imxrt uart driver */
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/* imxrt uart driver */
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struct imxrt_uart
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struct imxrt_uart
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{
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{
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LPUART_Type * uart_base;
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LPUART_Type *uart_base;
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IRQn_Type irqn;
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IRQn_Type irqn;
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struct rt_serial_device * serial;
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struct rt_serial_device *serial;
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char *device_name;
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char *device_name;
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};
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};
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@ -129,7 +128,8 @@ void LPUART8_IRQHandler(void)
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#endif /* RT_USING_UART8 */
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#endif /* RT_USING_UART8 */
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static const struct imxrt_uart uarts[] = {
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static const struct imxrt_uart uarts[] =
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{
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#ifdef RT_USING_UART1
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#ifdef RT_USING_UART1
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{
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{
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LPUART1,
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LPUART1,
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@ -198,7 +198,7 @@ static const struct imxrt_uart uarts[] = {
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};
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};
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/* Get debug console frequency. */
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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uint32_t GetUartSrcFreq(void)
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{
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{
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uint32_t freq;
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uint32_t freq;
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@ -231,7 +231,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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if (uart->uart_base != RT_NULL)
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if (uart->uart_base != RT_NULL)
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{
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{
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#ifdef RT_USING_UART1
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#ifdef RT_USING_UART1
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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@ -261,7 +260,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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Hyst. Enable Field: Hysteresis Disabled */
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Hyst. Enable Field: Hysteresis Disabled */
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#endif
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#endif
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#ifdef RT_USING_UART2
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#ifdef RT_USING_UART2
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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@ -272,15 +270,12 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART3
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#ifdef RT_USING_UART3
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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@ -291,13 +286,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART4
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#ifdef RT_USING_UART4
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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@ -308,13 +301,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_01_LPUART4_RX,
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IOMUXC_GPIO_B1_01_LPUART4_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART5
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#ifdef RT_USING_UART5
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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@ -325,13 +316,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_13_LPUART5_RX,
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IOMUXC_GPIO_B1_13_LPUART5_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART6
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#ifdef RT_USING_UART6
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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@ -342,13 +331,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
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IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART7
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#ifdef RT_USING_UART7
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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@ -359,13 +346,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_EMC_32_LPUART7_RX,
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IOMUXC_GPIO_EMC_32_LPUART7_RX,
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0x10B0u);
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0x10B0u);
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#endif
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#endif
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#ifdef RT_USING_UART8
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#ifdef RT_USING_UART8
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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@ -376,7 +361,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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0x10B0u);
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
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IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
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0x10B0u);
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0x10B0u);
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@ -440,8 +424,7 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c
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config.enableTx = true;
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config.enableTx = true;
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config.enableRx = true;
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config.enableRx = true;
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LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq());
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LPUART_Init(uart->uart_base, &config, GetUartSrcFreq());
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return RT_EOK;
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return RT_EOK;
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}
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}
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@ -481,7 +464,7 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch)
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uart = (struct imxrt_uart *)serial->parent.user_data;
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uart = (struct imxrt_uart *)serial->parent.user_data;
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LPUART_WriteByte(uart->uart_base, ch);
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LPUART_WriteByte(uart->uart_base, ch);
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while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
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while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
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return 1;
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return 1;
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}
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}
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@ -546,16 +529,21 @@ static const struct rt_uart_ops imxrt_uart_ops =
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imxrt_getc,
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imxrt_getc,
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};
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};
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int imxrt_hw_usart_init(void)
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int imxrt_hw_uart_init(void)
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{
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{
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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int i;
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int i;
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/* Configure UART divider to default */
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CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
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for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
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for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
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{
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{
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uarts[i].serial->ops = &imxrt_uart_ops;
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uarts[i].serial->ops = &imxrt_uart_ops;
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uarts[i].serial->config = config;
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uarts[i].serial->config = config;
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/* register UART1 device */
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/* register UART device */
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rt_hw_serial_register(uarts[i].serial,
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rt_hw_serial_register(uarts[i].serial,
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uarts[i].device_name,
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uarts[i].device_name,
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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@ -564,6 +552,6 @@ int imxrt_hw_usart_init(void)
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return 0;
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return 0;
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}
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}
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INIT_BOARD_EXPORT(imxrt_hw_usart_init);
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INIT_BOARD_EXPORT(imxrt_hw_uart_init);
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#endif /*RT_USING_SERIAL */
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#endif /*RT_USING_SERIAL */
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@ -12,12 +12,11 @@
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* 2017-10-10 Tanek the first version
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* 2017-10-10 Tanek the first version
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*/
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*/
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#ifndef __DRV_USART_H__
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#ifndef __DRV_UART_H__
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#define __DRV_USART_H__
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#define __DRV_UART_H__
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#include <rthw.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtthread.h>
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int rt_hw_usart_init(void);
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#endif
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#endif
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