[bsp][renesas]Fix ek-ra8d1 spi binding error problem.
This commit is contained in:
parent
dbce35ba2b
commit
5d64ea1ed6
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@ -122,6 +122,16 @@ menu "Hardware Drivers Config"
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default n
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endif
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menuconfig BSP_USING_DAC
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bool "Enable DAC"
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default n
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select RT_USING_DAC
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if BSP_USING_DAC
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config BSP_USING_DAC0
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bool "Enable DAC0"
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default n
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endif
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menuconfig BSP_USING_SCI_SPI
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bool "Enable SCI SPI BUS"
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default n
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@ -621,7 +631,7 @@ menu "Hardware Drivers Config"
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if BSP_USING_RW007
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config RA_RW007_SPI_BUS_NAME
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string "RW007 BUS NAME"
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default "scpi2"
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default "sci2s"
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config RA_RW007_CS_PIN
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hex "(HEX)CS pin index"
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@ -1,8 +1,8 @@
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import os
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from building import *
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src = []
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objs = []
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src = Glob('*.c')
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cwd = GetCurrentDir()
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CPPPATH = [cwd]
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@ -0,0 +1,254 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-12 Rbb666 first version
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*/
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#include "r_ioport.h"
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#include "bsp_cfg.h"
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#include "bsp_pin_cfg.h"
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#include <rtthread.h>
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#define DRV_DEBUG
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#define LOG_TAG "drv_sdram"
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#include <drv_log.h>
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/* SDRAM size, in bytes */
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#define SDRAM_SIZE (64 * 1024 * 1024)
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/*
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* Set ACTIVE-to-PRECHARGE command (tRAS) timing
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* e.g. tRAS = 42ns -> 6cycles are needed at SDCLK 120MHz
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* tRAS = 37ns -> 5cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRAS (6U)
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/*
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* Set ACTIVE-to-READ or WRITE delay tRCD (tRCD) timing
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* e.g. tRCD = 18ns -> 3cycles are needed at SDCLK 120MHz
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* tRCD = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRCD (3U)
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/*
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* Set PRECHARGE command period (tRP) timing
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* e.g. tRP = 18ns -> 3cycles are needed at SDCLK 120MHz
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* tRP = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRP (3U)
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/*
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* Set WRITE recovery time (tWR) timing
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* e.g. tWR = 1CLK + 6ns -> 2cycles are needed at SDCLK 120MHz
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* tWR = 1CLK + 7ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TWR (2U)
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/*
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* Set CAS (READ) latency (CL) timing
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* e.g. CL = 18ns -> 3cycles are needed at SDCLK 120MHz
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* e.g. CL = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_CL (3U)
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/*
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* Set AUTO REFRESH period (tRFC) timing
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* e.g. tRFC = 60nS -> 8cycles are needed at SDCLK 120MHz
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* tRFC = 66nS -> 8cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRFC (8U)
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/*
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* Set Average Refresh period
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* e.g. tREF = 64ms/8192rows -> 7.8125us/each row. 937cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_REF_CMD_INTERVAL (937U)
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/*
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* Set Auto-Refresh issue times in initialization sequence needed for SDRAM device
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* Typical SDR SDRAM device needs twice of Auto-Refresh command issue
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*/
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#define BSP_PRV_SDRAM_SDIR_REF_TIMES (2U)
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/*
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* Set RAW address offset
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* Available settings are
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* 8 : 8-bit
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* 9 : 9-bit
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* 10 : 10-bit
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* 11 : 11-bit
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*/
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#define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET (10U)
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/*
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* Select endian mode for SDRAM address space
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* 0 : Endian of SDRAM address space is the same as the endian of operating mode
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* 1 : Endian of SDRAM address space is not the endian of operating mode
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*/
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#define BSP_PRV_SDRAM_ENDIAN_MODE (0U)
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/*
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* Select access mode
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* Typically Continuous access should be enabled to get better SDRAM bandwidth
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* 0: Continuous access is disabled
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* 1: Continuous access is enabled
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*/
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#define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE (1U)
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/*
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* Select bus width
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* 0: 16-bit
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* 1: 32-bit
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* 2: 8-bit
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*/
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#define BSP_PRV_SDRAM_BUS_WIDTH (0U)
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#if ((BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 8U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 9U) \
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&& (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 10U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET > 11U))
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#error "BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET must be either of 8,9,10 or 11"
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#endif
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#if ((BSP_PRV_SDRAM_BUS_WIDTH != 0) && (BSP_PRV_SDRAM_BUS_WIDTH != 1U) && (BSP_PRV_SDRAM_BUS_WIDTH != 2U))
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#error "BSP_PRV_SDRAM_BUS_WIDTH must be either of 0(16-bit) or 1(32-bit) or 2(8-bit)"
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#endif
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#if ((BSP_PRV_SDRAM_ENDIAN_MODE != 0) && (BSP_PRV_SDRAM_ENDIAN_MODE != 1))
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#error \
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"BSP_PRV_SDRAM_ENDIAN_MODE must be either of 0(same endian as operating mode) or 2(another endian against operating mode)"
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#endif
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#if ((BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 0) && (BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 1))
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#error \
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"BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE must be either of 0(continuous access is disabled) or 1(continuous access is enabled)"
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#endif
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#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */
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#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */
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#define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL (0U) /* MR.M3 Burst Type : Sequential */
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#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global variables (to be accessed by other files)
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Private global variables and functions
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**********************************************************************************************************************/
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void drv_sdram_init (void)
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{
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/** Setting for SDRAM initialization sequence */
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#if (BSP_PRV_SDRAM_TRP < 3)
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R_BUS->SDRAM.SDIR_b.PRC = 3U;
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#else
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R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
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#endif
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
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}
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R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES;
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
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}
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#if (BSP_PRV_SDRAM_TRFC < 3)
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R_BUS->SDRAM.SDIR_b.ARFI = 0U;
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#else
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R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
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#endif
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
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}
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/** Start SDRAM initialization sequence.
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* Following operation is automatically done when set SDICR.INIRQ bit.
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* Perform a PRECHARGE ALL command and wait at least tRP time.
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* Issue an AUTO REFRESH command and wait at least tRFC time.
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* Issue an AUTO REFRESH command and wait at least tRFC time.
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*/
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R_BUS->SDRAM.SDICR_b.INIRQ = 1U;
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while (R_BUS->SDRAM.SDSR_b.INIST)
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{
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/* Wait the end of initialization sequence. */
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}
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/** Setting for SDRAM controller */
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R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH; /* set SDRAM bus width */
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R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */
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R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
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}
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/** Using LMR command, program the mode register */
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R_BUS->SDRAM.SDMOD = ((((uint16_t) (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
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(uint16_t) (BSP_PRV_SDRAM_MR_OP_MODE << 7)) |
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(uint16_t) (BSP_PRV_SDRAM_CL << 4)) |
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(uint16_t) (BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) |
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(uint16_t) (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
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/** wait at least tMRD time */
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while (R_BUS->SDRAM.SDSR_b.MRSST)
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{
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/* Wait until Mode Register setting done. */
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}
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/** Set timing parameters for SDRAM */
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R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/
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R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */
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R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U; /* set PRECHARGE command period cycles */
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R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U; /* set write recovery cycles */
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R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */
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/** Set row address offset for target SDRAM */
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R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;
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R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t) (BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */
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R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U; /* set Auto-Refresh period */
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/** Start Auto-refresh */
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R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;
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/** Enable SDRAM access */
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R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
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}
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#ifdef BSP_USING_SDRAM
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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struct rt_memheap system_heap;
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#endif
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static int SDRAM_Init(void)
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{
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drv_sdram_init();
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LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", 0x68000000, BSP_USING_SDRAM_SIZE, 16);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sdram", (void *)0x68000000, BSP_USING_SDRAM_SIZE);
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#endif
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(SDRAM_Init);
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#endif
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@ -11,6 +11,7 @@
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#define _FAL_CFG_H_
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#include "hal_data.h"
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#include "rtconfig.h"
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extern const struct fal_flash_dev _onchip_flash_hp0;
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extern const struct fal_flash_dev _onchip_flash_hp1;
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@ -1,165 +0,0 @@
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#include <rtthread.h>
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#include "hal_data.h"
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#ifdef BSP_USING_FS
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#include <dfs_fs.h>
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#define DBG_TAG "app.filesystem"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifdef BSP_USING_ONCHIP_FS
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#include "fal.h"
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#define FS_PARTITION_NAME "disk"
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static void sd_mount(void)
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{
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struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
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if (flash_dev == NULL)
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{
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rt_kprintf("Can't create a block device on '%s' partition.\n", FS_PARTITION_NAME);
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}
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else
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{
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rt_kprintf("Create a block device on the %s partition of flash successful.\n", FS_PARTITION_NAME);
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}
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if(rt_device_find(FS_PARTITION_NAME) != RT_NULL)
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{
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dfs_mkfs("elm", FS_PARTITION_NAME);
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if (dfs_mount(FS_PARTITION_NAME, "/", "elm", 0, 0) == RT_EOK)
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{
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rt_kprintf("onchip elm filesystem mount to '/'\n");
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}
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else
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{
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rt_kprintf("onchip elm filesystem mount to '/' failed!\n");
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}
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}
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else
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{
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rt_kprintf("find filesystem portion failed\r\n");
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}
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}
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#elif defined(BSP_USING_SDCARD_FS)
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#include <drv_sdhi.h>
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/* SD Card hot plug detection pin */
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#define SD_CHECK_PIN "p405"
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static rt_base_t sd_check_pin = 0;
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static void _sdcard_mount(void)
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{
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rt_device_t device;
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device = rt_device_find("sd");
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rt_kprintf("rt_device_find %x \r\n", device);
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if (device == NULL)
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{
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mmcsd_wait_cd_changed(0);
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sdcard_change();
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mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
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device = rt_device_find("sd");
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}
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if (device != RT_NULL)
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{
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if (dfs_mount("sd", "/", "elm", 0, 0) == RT_EOK)
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{
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LOG_I("sd card mount to '/'");
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}
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else
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{
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LOG_W("sd card mount to '/' failed!");
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}
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}
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}
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static void _sdcard_unmount(void)
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{
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rt_thread_mdelay(200);
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dfs_unmount("/sdcard");
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LOG_I("Unmount \"/sdcard\"");
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mmcsd_wait_cd_changed(0);
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sdcard_change();
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mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
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}
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static void sd_auto_mount(void *parameter)
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{
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rt_uint8_t re_sd_check_pin = 1;
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rt_thread_mdelay(20);
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if (!rt_pin_read(sd_check_pin))
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{
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_sdcard_mount();
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}
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while (1)
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{
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rt_thread_mdelay(200);
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if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) == 0)
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{
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_sdcard_mount();
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}
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if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) != 0)
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{
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_sdcard_unmount();
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}
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}
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}
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static void sd_mount(void)
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{
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rt_thread_t tid;
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sd_check_pin = rt_pin_get(SD_CHECK_PIN);
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rt_pin_mode(sd_check_pin, PIN_MODE_INPUT_PULLUP);
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tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
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2048, RT_THREAD_PRIORITY_MAX - 2, 20);
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if (tid != RT_NULL)
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{
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rt_thread_startup(tid);
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}
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else
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{
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LOG_E("create sd_mount thread err!");
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return;
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}
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}
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#else
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#include <spi_msd.h>
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#include "drv_sci_spi.h"
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int sd_mount(void)
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{
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uint32_t cs_pin = BSP_IO_PORT_10_PIN_05;
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rt_hw_sci_spi_device_attach("scpi2", "scpi20", cs_pin);
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msd_init("sd0", "scpi20");
|
||||
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
|
||||
{
|
||||
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_W("sd card mount to '/' failed!");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* BSP_USING_SDCARD_FS */
|
||||
|
||||
int mount_init(void)
|
||||
{
|
||||
sd_mount();
|
||||
return RT_EOK;
|
||||
}
|
||||
// INIT_ENV_EXPORT(mount_init);
|
||||
#endif
|
|
@ -1,3 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-12 Rbb666 first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rtdbg.h>
|
||||
#ifdef BSP_USING_RW007
|
||||
|
|
Loading…
Reference in New Issue