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[bsp][renesas]Fix ek-ra8d1 spi binding error problem.

This commit is contained in:
Rbb666 2024-04-12 10:14:38 +08:00 committed by Meco Man
parent dbce35ba2b
commit 5d64ea1ed6
6 changed files with 276 additions and 167 deletions
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12
bsp/renesas/ra8d1-ek/board/Kconfig
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@ -122,6 +122,16 @@ menu "Hardware Drivers Config"
default n
endif
menuconfig BSP_USING_DAC
bool "Enable DAC"
default n
select RT_USING_DAC
if BSP_USING_DAC
config BSP_USING_DAC0
bool "Enable DAC0"
default n
endif
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
@ -621,7 +631,7 @@ menu "Hardware Drivers Config"
if BSP_USING_RW007
config RA_RW007_SPI_BUS_NAME
string "RW007 BUS NAME"
default "scpi2"
default "sci2s"
config RA_RW007_CS_PIN
hex "(HEX)CS pin index"

2
bsp/renesas/ra8d1-ek/board/ports/SConscript
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@ -1,8 +1,8 @@
import os
from building import *
src = []
objs = []
src = Glob('*.c')
cwd = GetCurrentDir()
CPPPATH = [cwd]

254
bsp/renesas/ra8d1-ek/board/ports/drv_sdram.c Normal file
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@ -0,0 +1,254 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-04-12 Rbb666 first version
*/
#include "r_ioport.h"
#include "bsp_cfg.h"
#include "bsp_pin_cfg.h"
#include <rtthread.h>
#define DRV_DEBUG
#define LOG_TAG "drv_sdram"
#include <drv_log.h>
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* SDRAM size, in bytes */
#define SDRAM_SIZE (64 * 1024 * 1024)
/*
* Set ACTIVE-to-PRECHARGE command (tRAS) timing
* e.g. tRAS = 42ns -> 6cycles are needed at SDCLK 120MHz
* tRAS = 37ns -> 5cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRAS (6U)
/*
* Set ACTIVE-to-READ or WRITE delay tRCD (tRCD) timing
* e.g. tRCD = 18ns -> 3cycles are needed at SDCLK 120MHz
* tRCD = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRCD (3U)
/*
* Set PRECHARGE command period (tRP) timing
* e.g. tRP = 18ns -> 3cycles are needed at SDCLK 120MHz
* tRP = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRP (3U)
/*
* Set WRITE recovery time (tWR) timing
* e.g. tWR = 1CLK + 6ns -> 2cycles are needed at SDCLK 120MHz
* tWR = 1CLK + 7ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TWR (2U)
/*
* Set CAS (READ) latency (CL) timing
* e.g. CL = 18ns -> 3cycles are needed at SDCLK 120MHz
* e.g. CL = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_CL (3U)
/*
* Set AUTO REFRESH period (tRFC) timing
* e.g. tRFC = 60nS -> 8cycles are needed at SDCLK 120MHz
* tRFC = 66nS -> 8cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRFC (8U)
/*
* Set Average Refresh period
* e.g. tREF = 64ms/8192rows -> 7.8125us/each row. 937cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_REF_CMD_INTERVAL (937U)
/*
* Set Auto-Refresh issue times in initialization sequence needed for SDRAM device
* Typical SDR SDRAM device needs twice of Auto-Refresh command issue
*/
#define BSP_PRV_SDRAM_SDIR_REF_TIMES (2U)
/*
* Set RAW address offset
* Available settings are
* 8 : 8-bit
* 9 : 9-bit
* 10 : 10-bit
* 11 : 11-bit
*/
#define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET (10U)
/*
* Select endian mode for SDRAM address space
* 0 : Endian of SDRAM address space is the same as the endian of operating mode
* 1 : Endian of SDRAM address space is not the endian of operating mode
*/
#define BSP_PRV_SDRAM_ENDIAN_MODE (0U)
/*
* Select access mode
* Typically Continuous access should be enabled to get better SDRAM bandwidth
* 0: Continuous access is disabled
* 1: Continuous access is enabled
*/
#define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE (1U)
/*
* Select bus width
* 0: 16-bit
* 1: 32-bit
* 2: 8-bit
*/
#define BSP_PRV_SDRAM_BUS_WIDTH (0U)
#if ((BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 8U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 9U) \
&& (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 10U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET > 11U))
#error "BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET must be either of 8,9,10 or 11"
#endif
#if ((BSP_PRV_SDRAM_BUS_WIDTH != 0) && (BSP_PRV_SDRAM_BUS_WIDTH != 1U) && (BSP_PRV_SDRAM_BUS_WIDTH != 2U))
#error "BSP_PRV_SDRAM_BUS_WIDTH must be either of 0(16-bit) or 1(32-bit) or 2(8-bit)"
#endif
#if ((BSP_PRV_SDRAM_ENDIAN_MODE != 0) && (BSP_PRV_SDRAM_ENDIAN_MODE != 1))
#error \
"BSP_PRV_SDRAM_ENDIAN_MODE must be either of 0(same endian as operating mode) or 2(another endian against operating mode)"
#endif
#if ((BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 0) && (BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 1))
#error \
"BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE must be either of 0(continuous access is disabled) or 1(continuous access is enabled)"
#endif
#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */
#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */
#define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL (0U) /* MR.M3 Burst Type : Sequential */
#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
void drv_sdram_init (void)
{
/** Setting for SDRAM initialization sequence */
#if (BSP_PRV_SDRAM_TRP < 3)
R_BUS->SDRAM.SDIR_b.PRC = 3U;
#else
R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
#endif
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
}
R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES;
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
}
#if (BSP_PRV_SDRAM_TRFC < 3)
R_BUS->SDRAM.SDIR_b.ARFI = 0U;
#else
R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
#endif
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
}
/** Start SDRAM initialization sequence.
* Following operation is automatically done when set SDICR.INIRQ bit.
* Perform a PRECHARGE ALL command and wait at least tRP time.
* Issue an AUTO REFRESH command and wait at least tRFC time.
* Issue an AUTO REFRESH command and wait at least tRFC time.
*/
R_BUS->SDRAM.SDICR_b.INIRQ = 1U;
while (R_BUS->SDRAM.SDSR_b.INIST)
{
/* Wait the end of initialization sequence. */
}
/** Setting for SDRAM controller */
R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH; /* set SDRAM bus width */
R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */
R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
}
/** Using LMR command, program the mode register */
R_BUS->SDRAM.SDMOD = ((((uint16_t) (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
(uint16_t) (BSP_PRV_SDRAM_MR_OP_MODE << 7)) |
(uint16_t) (BSP_PRV_SDRAM_CL << 4)) |
(uint16_t) (BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) |
(uint16_t) (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
/** wait at least tMRD time */
while (R_BUS->SDRAM.SDSR_b.MRSST)
{
/* Wait until Mode Register setting done. */
}
/** Set timing parameters for SDRAM */
R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/
R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */
R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U; /* set PRECHARGE command period cycles */
R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U; /* set write recovery cycles */
R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */
/** Set row address offset for target SDRAM */
R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;
R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t) (BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */
R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U; /* set Auto-Refresh period */
/** Start Auto-refresh */
R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;
/** Enable SDRAM access */
R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
}
#ifdef BSP_USING_SDRAM
#ifdef RT_USING_MEMHEAP_AS_HEAP
struct rt_memheap system_heap;
#endif
static int SDRAM_Init(void)
{
drv_sdram_init();
LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", 0x68000000, BSP_USING_SDRAM_SIZE, 16);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sdram", (void *)0x68000000, BSP_USING_SDRAM_SIZE);
#endif
return RT_EOK;
}
INIT_BOARD_EXPORT(SDRAM_Init);
#endif

1
bsp/renesas/ra8d1-ek/board/ports/fal_cfg.h
View File

@ -11,6 +11,7 @@
#define _FAL_CFG_H_
#include "hal_data.h"
#include "rtconfig.h"
extern const struct fal_flash_dev _onchip_flash_hp0;
extern const struct fal_flash_dev _onchip_flash_hp1;

165
bsp/renesas/ra8d1-ek/board/ports/mnt.c
View File

@ -1,165 +0,0 @@
#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_FS
#include <dfs_fs.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_ONCHIP_FS
#include "fal.h"
#define FS_PARTITION_NAME "disk"
static void sd_mount(void)
{
struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
if (flash_dev == NULL)
{
rt_kprintf("Can't create a block device on '%s' partition.\n", FS_PARTITION_NAME);
}
else
{
rt_kprintf("Create a block device on the %s partition of flash successful.\n", FS_PARTITION_NAME);
}
if(rt_device_find(FS_PARTITION_NAME) != RT_NULL)
{
dfs_mkfs("elm", FS_PARTITION_NAME);
if (dfs_mount(FS_PARTITION_NAME, "/", "elm", 0, 0) == RT_EOK)
{
rt_kprintf("onchip elm filesystem mount to '/'\n");
}
else
{
rt_kprintf("onchip elm filesystem mount to '/' failed!\n");
}
}
else
{
rt_kprintf("find filesystem portion failed\r\n");
}
}
#elif defined(BSP_USING_SDCARD_FS)
#include <drv_sdhi.h>
/* SD Card hot plug detection pin */
#define SD_CHECK_PIN "p405"
static rt_base_t sd_check_pin = 0;
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find("sd");
rt_kprintf("rt_device_find %x \r\n", device);
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find("sd");
}
if (device != RT_NULL)
{
if (dfs_mount("sd", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount("/sdcard");
LOG_I("Unmount \"/sdcard\"");
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
}
static void sd_auto_mount(void *parameter)
{
rt_uint8_t re_sd_check_pin = 1;
rt_thread_mdelay(20);
if (!rt_pin_read(sd_check_pin))
{
_sdcard_mount();
}
while (1)
{
rt_thread_mdelay(200);
if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) == 0)
{
_sdcard_mount();
}
if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) != 0)
{
_sdcard_unmount();
}
}
}
static void sd_mount(void)
{
rt_thread_t tid;
sd_check_pin = rt_pin_get(SD_CHECK_PIN);
rt_pin_mode(sd_check_pin, PIN_MODE_INPUT_PULLUP);
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
return;
}
}
#else
#include <spi_msd.h>
#include "drv_sci_spi.h"
int sd_mount(void)
{
uint32_t cs_pin = BSP_IO_PORT_10_PIN_05;
rt_hw_sci_spi_device_attach("scpi2", "scpi20", cs_pin);
msd_init("sd0", "scpi20");
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
return 0;
}
#endif /* BSP_USING_SDCARD_FS */
int mount_init(void)
{
sd_mount();
return RT_EOK;
}
// INIT_ENV_EXPORT(mount_init);
#endif

9
bsp/renesas/ra8d1-ek/board/ports/wifi/drv_rw007.c
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-04-12 Rbb666 first version
*/
#include <rtthread.h>
#include <rtdbg.h>
#ifdef BSP_USING_RW007