diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/main.c b/bsp/stm32/stm32f072-st-nucleo/applications/main.c
index 81b03091e1..486ed61283 100644
--- a/bsp/stm32/stm32f072-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f072-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.c b/bsp/stm32/stm32f072-st-nucleo/board/board.c
index 8adbcd7bdd..5f06e3253d 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f072-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-12-21     zylx         first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
@@ -25,7 +25,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.h b/bsp/stm32/stm32f072-st-nucleo/board/board.h
index bfd0371048..51a9f80edd 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f072-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f091-st-nucleo/applications/main.c b/bsp/stm32/stm32f091-st-nucleo/applications/main.c
index 421f897bc4..9783d01e55 100644
--- a/bsp/stm32/stm32f091-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f091-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.c b/bsp/stm32/stm32f091-st-nucleo/board/board.c
index db5c101a9d..ec74fe9af0 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f091-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-12-21     zylx         first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14
                               |RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE;
@@ -38,7 +38,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.h b/bsp/stm32/stm32f091-st-nucleo/board/board.h
index 7a78136471..a9ba91377d 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f091-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
index 78bf24d251..b9964e0154 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c
index 6d75fd13ce..be493624c1 100644
--- a/bsp/stm32/stm32f103-atk-nano/applications/main.c
+++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c
index bb35832bfa..de585efe32 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/board.c
+++ b/bsp/stm32/stm32f103-atk-nano/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h
index a33ef3cd5e..498459073e 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/board.h
+++ b/bsp/stm32/stm32f103-atk-nano/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
index 0ca9acb3ea..3eb4fd7c0d 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
index 43f726525b..7892489436 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
index 140fb13c73..55c2b62023 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
index 17bfd29f27..2dc4c9cabf 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
index 68ac34f5f7..80c80984bf 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
index c0b077e600..420785bc9e 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
index 06ee47cca2..f51d21c6fa 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
index a56e1bc35f..d56fb039d4 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-blue-pill/applications/main.c b/bsp/stm32/stm32f103-blue-pill/applications/main.c
index f1de7cf454..9be4cd59b1 100644
--- a/bsp/stm32/stm32f103-blue-pill/applications/main.c
+++ b/bsp/stm32/stm32f103-blue-pill/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.c b/bsp/stm32/stm32f103-blue-pill/board/board.c
index af6fb56470..22f1cc14f7 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/board.c
+++ b/bsp/stm32/stm32f103-blue-pill/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2019-03-08     obito0   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.h b/bsp/stm32/stm32f103-blue-pill/board/board.h
index fc435ee029..1be364929a 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/board.h
+++ b/bsp/stm32/stm32f103-blue-pill/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
index 7b7f00c8ee..0ec4930664 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
index 038725b78d..695510d1ac 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.c b/bsp/stm32/stm32f103-dofly-M3S/board/board.c
index 7b6a3ea947..d32a5096b6 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/board.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-11-06     SummerGift   first version
  * 2019-04-09     WillianChan  add stm32f103-dofly-M3S BSP
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -29,7 +29,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.h b/bsp/stm32/stm32f103-dofly-M3S/board/board.h
index 62f9030426..8662bff0f5 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/board.h
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
index 5ffa50ba1d..13d235b694 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
index 060c6d59b4..e22efac3c9 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
index 18dbaac95c..dc4e9cbb7e 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
+++ b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
index 9f1ba0ddab..8493439409 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
index ae6f2c67e8..8d8cc4643a 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
index 5f0f0db8ed..7ddaa5ee96 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
  */
- 
+
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
index 080a22ff49..abbc74be30 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include <rtthread.h>
 #include "board.h"
 
@@ -17,7 +17,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
index 968ac8e2e5..7aa3c0f703 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
index bf5f3e10a7..55baa2c263 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
index 96b2034f24..519080ae05 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
index 68348d2bac..378d8f8274 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
index 70f60f3f8b..bf9e60aae9 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
index 66a0c7f737..55faf0d89f 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 /**
@@ -19,7 +19,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
index 7f0ae67d48..cdb13091cd 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
index d0ab2cc6ed..096b4df406 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
index 0598b6af0d..779d731980 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
index fe3ea19e77..239f0afdd6 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
index 0de060a35a..f18b6318bb 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,6 +21,6 @@ int esp_02_device_init()
     rt_pin_write(ESP8266_CH_PD_Pin,PIN_HIGH) ;
     rt_pin_write(ESP8266_RST,PIN_HIGH) ;
 
-    return RT_EOK ;	
+    return RT_EOK ;
 }
 INIT_DEVICE_EXPORT(esp_02_device_init);
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
index be8978c63d..ae0660b29a 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
index a0174bbb0c..59d139a8ac 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
index 6d75fd13ce..be493624c1 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
+++ b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
index 258dd08e9d..5e045816b2 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
+++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include "board.h"
 
 /**
@@ -16,32 +16,32 @@
   */
 void SystemClock_Config(void)
 {
-	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-	/** Initializes the CPU, AHB and APB busses clocks 
-	*/
-	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
-	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
-	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-	{
-		Error_Handler();
-	}
-	/** Initializes the CPU, AHB and APB busses clocks 
-	*/
-	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-							  |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        Error_Handler();
+    }
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-	{
-		Error_Handler();
-	}
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+    {
+        Error_Handler();
+    }
 }
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
index 070ccbbb45..162925a4f3 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
+++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-yf-ufun/applications/main.c b/bsp/stm32/stm32f103-yf-ufun/applications/main.c
index 737c362b23..ffe4955e19 100644
--- a/bsp/stm32/stm32f103-yf-ufun/applications/main.c
+++ b/bsp/stm32/stm32f103-yf-ufun/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.c b/bsp/stm32/stm32f103-yf-ufun/board/board.c
index 4df20fbd48..5271b59c71 100644
--- a/bsp/stm32/stm32f103-yf-ufun/board/board.c
+++ b/bsp/stm32/stm32f103-yf-ufun/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.h b/bsp/stm32/stm32f103-yf-ufun/board/board.h
index 8c0aa1d769..738f37080a 100644
--- a/bsp/stm32/stm32f103-yf-ufun/board/board.h
+++ b/bsp/stm32/stm32f103-yf-ufun/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f107-uc-eval/applications/main.c b/bsp/stm32/stm32f107-uc-eval/applications/main.c
index 11587e49d0..9dca242b10 100644
--- a/bsp/stm32/stm32f107-uc-eval/applications/main.c
+++ b/bsp/stm32/stm32f107-uc-eval/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.c b/bsp/stm32/stm32f107-uc-eval/board/board.c
index a63b070167..f053579c2f 100644
--- a/bsp/stm32/stm32f107-uc-eval/board/board.c
+++ b/bsp/stm32/stm32f107-uc-eval/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.h b/bsp/stm32/stm32f107-uc-eval/board/board.h
index 98df6d51ff..44a96208c6 100644
--- a/bsp/stm32/stm32f107-uc-eval/board/board.h
+++ b/bsp/stm32/stm32f107-uc-eval/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/main.c b/bsp/stm32/stm32f401-st-nucleo/applications/main.c
index 86c4508d12..48009f1c78 100644
--- a/bsp/stm32/stm32f401-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f401-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.c b/bsp/stm32/stm32f401-st-nucleo/board/board.c
index 942d080c5b..9c33cdbba5 100644
--- a/bsp/stm32/stm32f401-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f401-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -34,7 +34,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.h b/bsp/stm32/stm32f401-st-nucleo/board/board.h
index 4c6f84d170..82647a83a4 100644
--- a/bsp/stm32/stm32f401-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f401-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
index 453681a90a..47358c8a61 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
index ef1f24cbb5..190ca080cf 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
index 5b30f605d9..844f5e35e6 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c
index e3ae33205f..2fc9307caf 100644
--- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c
+++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c
index c2c90a5e86..02a3a3d53f 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/board.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -37,7 +37,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h
index 70a4c0ed19..6d80e38f78 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/board.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
index 2b60a6d2cc..dba9ec5e29 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,11 +26,11 @@ static struct rt_memheap system_heap;
 static SRAM_HandleTypeDef hsram;
 
 static int rt_hw_sram_init(void)
-{ 
+{
     int result = RT_EOK;
 
     FSMC_NORSRAM_TimingTypeDef Timing = {0};
-    
+
     /** Perform the SRAM2 memory initialization sequence
     */
     hsram.Instance = FSMC_NORSRAM_DEVICE;
@@ -57,7 +57,7 @@ static int rt_hw_sram_init(void)
     hsram.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
     hsram.Init.PageSize = FSMC_PAGE_SIZE_NONE;
 
-    
+
     /* Timing */
     Timing.AddressSetupTime = 0;
     Timing.AddressHoldTime = 0;
@@ -81,7 +81,7 @@ static int rt_hw_sram_init(void)
         rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
 #endif
     }
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_sram_init);
@@ -153,7 +153,7 @@ static int sram_test(void)
         LOG_D("SRAM test success!");
     }
 
-    return RT_EOK;  
+    return RT_EOK;
 }
 MSH_CMD_EXPORT(sram_test, sram test);
 #endif /* FINSH_USING_MSH */
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
index 838216ffaa..ec5c61f1b0 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
index 0a9c36fd42..bc7e8b676e 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
index 4705cc0112..b92344fa43 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
index b40082267a..6238e611b1 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-st-discovery/applications/main.c b/bsp/stm32/stm32f407-st-discovery/applications/main.c
index c7ffc240cb..2651a75073 100644
--- a/bsp/stm32/stm32f407-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32f407-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.c b/bsp/stm32/stm32f407-st-discovery/board/board.c
index 8a3dbd9937..5fff5426fe 100644
--- a/bsp/stm32/stm32f407-st-discovery/board/board.c
+++ b/bsp/stm32/stm32f407-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.h b/bsp/stm32/stm32f407-st-discovery/board/board.h
index 7ba6c79dee..539e3abf45 100644
--- a/bsp/stm32/stm32f407-st-discovery/board/board.h
+++ b/bsp/stm32/stm32f407-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f410-st-nucleo/applications/main.c b/bsp/stm32/stm32f410-st-nucleo/applications/main.c
index 1305c03138..05ab0e2504 100644
--- a/bsp/stm32/stm32f410-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f410-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.c b/bsp/stm32/stm32f410-st-nucleo/board/board.c
index dffc7ffba0..3e64df40d7 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f410-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.h b/bsp/stm32/stm32f410-st-nucleo/board/board.h
index b9c9f8427f..72bd8a017c 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f410-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-atk-nano/applications/main.c b/bsp/stm32/stm32f411-atk-nano/applications/main.c
index 943b08cf15..df457f4760 100644
--- a/bsp/stm32/stm32f411-atk-nano/applications/main.c
+++ b/bsp/stm32/stm32f411-atk-nano/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.c b/bsp/stm32/stm32f411-atk-nano/board/board.c
index 2ca06e13bf..08158c2f96 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/board.c
+++ b/bsp/stm32/stm32f411-atk-nano/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -34,7 +34,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.h b/bsp/stm32/stm32f411-atk-nano/board/board.h
index 452aa7420c..2cbe75f5d9 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/board.h
+++ b/bsp/stm32/stm32f411-atk-nano/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
index 43f726525b..7892489436 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c
index b29630d930..0e109663ae 100644
--- a/bsp/stm32/stm32f411-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.c b/bsp/stm32/stm32f411-st-nucleo/board/board.c
index e9e6ffb5e7..1d83386719 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f411-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.h b/bsp/stm32/stm32f411-st-nucleo/board/board.h
index e05c785128..062038ffdb 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f411-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
index 729ae11bd6..be6a8af867 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
+++ b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
index a19a49af8e..7f27135a6b 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
index e05c785128..062038ffdb 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
index fe616d31cf..517d94f3ba 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/main.c b/bsp/stm32/stm32f412-st-nucleo/applications/main.c
index 317bc60514..2cf35c5bc6 100644
--- a/bsp/stm32/stm32f412-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f412-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.c b/bsp/stm32/stm32f412-st-nucleo/board/board.c
index 504407b161..b8f8168dfa 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f412-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.h b/bsp/stm32/stm32f412-st-nucleo/board/board.h
index 3e2d7384c8..5c463d04e8 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f412-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f413-st-nucleo/applications/main.c b/bsp/stm32/stm32f413-st-nucleo/applications/main.c
index 18b64457a9..799dc6797d 100644
--- a/bsp/stm32/stm32f413-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f413-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.c b/bsp/stm32/stm32f413-st-nucleo/board/board.c
index dffc5bba40..b36f973530 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f413-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,11 +20,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -40,7 +40,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.h b/bsp/stm32/stm32f413-st-nucleo/board/board.h
index cd5e86661c..634003f596 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f413-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/main.c b/bsp/stm32/stm32f427-robomaster-a/applications/main.c
index 7c21823832..6cef3cbb34 100644
--- a/bsp/stm32/stm32f427-robomaster-a/applications/main.c
+++ b/bsp/stm32/stm32f427-robomaster-a/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.c b/bsp/stm32/stm32f427-robomaster-a/board/board.c
index a0901feba9..780e089fcd 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/board.c
+++ b/bsp/stm32/stm32f427-robomaster-a/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,11 +19,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -37,13 +37,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.h b/bsp/stm32/stm32f427-robomaster-a/board/board.h
index 4c74f95682..a0ea5ca4bd 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/board.h
+++ b/bsp/stm32/stm32f427-robomaster-a/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
index b46537d311..6a79c83523 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/applications/main.c b/bsp/stm32/stm32f429-armfly-v6/applications/main.c
index 70c2a3b0f7..21b7c14ec0 100644
--- a/bsp/stm32/stm32f429-armfly-v6/applications/main.c
+++ b/bsp/stm32/stm32f429-armfly-v6/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,10 +18,10 @@ int main(void)
     int count = 1;
 
     HC574_SetPin(LED1,0);
-    HC574_SetPin(LED2,0);   
+    HC574_SetPin(LED2,0);
     HC574_SetPin(LED3,0);
     HC574_SetPin(LED4,0);
-    
+
     while (count++)
     {
         HC574_SetPin(LED1,1);
@@ -29,6 +29,6 @@ int main(void)
         HC574_SetPin(LED1,0);
         rt_thread_mdelay(500);
     }
-    
+
     return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.c b/bsp/stm32/stm32f429-armfly-v6/board/board.c
index f314b7c45a..2d37e631e3 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/board.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,12 +17,12 @@ void SystemClock_Config(void)
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-    
-    /**Configure the main internal regulator output voltage 
+
+    /**Configure the main internal regulator output voltage
     */
     __HAL_RCC_PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                                 |RCC_OSCILLATORTYPE_LSE;
@@ -39,13 +39,13 @@ void SystemClock_Config(void)
     {
       Error_Handler();
     }
-    /**Activate the Over-Drive mode 
+    /**Activate the Over-Drive mode
     */
     if (HAL_PWREx_EnableOverDrive() != HAL_OK)
     {
       Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                                 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -53,7 +53,7 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
     {
       Error_Handler();
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.h b/bsp/stm32/stm32f429-armfly-v6/board/board.h
index f0ea803bb0..c0d30df246 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/board.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
index 44a4a622c5..89fa42af5f 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,84 +17,84 @@
 #include <drv_log.h>
 
 #include "drv_ext_io.h"
-#define  HC574_PORT	 *(volatile rt_uint32_t *)0x64001000
+#define  HC574_PORT  *(volatile rt_uint32_t *)0x64001000
 
 volatile rt_uint32_t HC574_state = 0;
 
 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value)
 {
-	if (_value == 0)
-	{
-		HC574_state &= (~_pin);
-	}
-	else
-	{
-		HC574_state |= _pin;
-	}
-    
-	HC574_PORT = HC574_state;
+    if (_value == 0)
+    {
+        HC574_state &= (~_pin);
+    }
+    else
+    {
+        HC574_state |= _pin;
+    }
+
+    HC574_PORT = HC574_state;
 }
 
 rt_uint8_t HC574_GetPin(rt_uint32_t _pin)
 {
-	if (HC574_state & _pin)
-	{
-		return 1;
-	}
-	else
-	{
-		return 0;
-	}
+    if (HC574_state & _pin)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
 }
 
 static void HC574_Config_FMC(void)
 {
     FMC_NORSRAM_TimingTypeDef timing = {0};
     SRAM_HandleTypeDef sram2 = {0};
-    
-	/*
-		For LCD compatibility£¬select 3-0-6-1-0-0
-		3-0-5-1-0-0  : RD high level 75ns£¬low level 50ns. Read 8 channels of data into memory in 1us.
-		1-0-1-1-0-0  : RD high level 75ns£¬low level 12ns£¬trailing edge 12ns.
-	*/
-	/* FMC_Bank1_NORSRAM2 configuration */
-	timing.AddressSetupTime = 3;
-	timing.AddressHoldTime = 0;
-	timing.DataSetupTime = 6;
-	timing.BusTurnAroundDuration = 1;
-	timing.CLKDivision = 0;
-	timing.DataLatency = 0;
-	timing.AccessMode = FMC_ACCESS_MODE_A;
 
-	/*
-	 LCD configured as follow:
-	    - Data/Address MUX = Disable
-	    - Memory Type = SRAM
-	    - Data Width = 32bit
-	    - Write Operation = Enable
-	    - Extended Mode = Enable
-	    - Asynchronous Wait = Disable
-	*/
+    /*
+        For LCD compatibility，select 3-0-6-1-0-0
+        3-0-5-1-0-0  : RD high level 75ns，low level 50ns. Read 8 channels of data into memory in 1us.
+        1-0-1-1-0-0  : RD high level 75ns，low level 12ns，trailing edge 12ns.
+    */
+    /* FMC_Bank1_NORSRAM2 configuration */
+    timing.AddressSetupTime = 3;
+    timing.AddressHoldTime = 0;
+    timing.DataSetupTime = 6;
+    timing.BusTurnAroundDuration = 1;
+    timing.CLKDivision = 0;
+    timing.DataLatency = 0;
+    timing.AccessMode = FMC_ACCESS_MODE_A;
+
+    /*
+     LCD configured as follow:
+        - Data/Address MUX = Disable
+        - Memory Type = SRAM
+        - Data Width = 32bit
+        - Write Operation = Enable
+        - Extended Mode = Enable
+        - Asynchronous Wait = Disable
+    */
     sram2.Instance = FMC_NORSRAM_DEVICE;
     sram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
 
-	sram2.Init.NSBank = FMC_NORSRAM_BANK2;
-	sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
-	sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
-	sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
-	sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
-	sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
-	sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
-	sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
-	sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
-	sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
-	sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
-	sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
-	sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
-	sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
+    sram2.Init.NSBank = FMC_NORSRAM_BANK2;
+    sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
+    sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
+    sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
+    sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
+    sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
+    sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
+    sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
+    sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
+    sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
+    sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
+    sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
+    sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
+    sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
     sram2.Init.PageSize = FMC_PAGE_SIZE_1024;
 
-	if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
+    if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
     {
         LOG_E("extend IO init failed!");
     }
@@ -106,12 +106,12 @@ static void HC574_Config_FMC(void)
 
 static int stm32_ext_io_init(void)
 {
-	HC574_Config_FMC();
-	/* Set the chip select to high level */
-	HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
+    HC574_Config_FMC();
+    /* Set the chip select to high level */
+    HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
     /* Change IO state */
-	HC574_PORT = HC574_state;
-    
+    HC574_PORT = HC574_state;
+
     return RT_EOK;
 }
 INIT_BOARD_EXPORT(stm32_ext_io_init);
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
index 09740d3571..3f336dd7ab 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,64 +13,64 @@
 
 #include "rtthread.h"
 /*
-	armfly STM32-V6 Development board Extend IO
-	D0  - GPRS_RERM_ON
-	D1  - GPRS_RESET
-	D2  - NRF24L01_CE
-	D3  - NRF905_TX_EN
-	D4  - NRF905_TRX_CE/VS1053_XDCS
-	D5  - NRF905_PWR_UP
-	D6  - ESP8266_G0
-	D7  - ESP8266_G2
-	
-	D8  - LED1
-	D9  - LED2
-	D10 - LED3
-	D11 - LED4
-	D12 - TP_NRST
-	D13 - AD7606_OS0
-	D14 - AD7606_OS1
-	D15 - AD7606_OS2
-	
-	GPIO can output 5V 
-	D16  - Y50_0
-	D17  - Y50_1
-	D18  - Y50_2
-	D19  - Y50_3
-	D20  - Y50_4
-	D21  - Y50_5
-	D22  - Y50_6
-	D23  - Y50_7	
+    armfly STM32-V6 Development board Extend IO
+    D0  - GPRS_RERM_ON
+    D1  - GPRS_RESET
+    D2  - NRF24L01_CE
+    D3  - NRF905_TX_EN
+    D4  - NRF905_TRX_CE/VS1053_XDCS
+    D5  - NRF905_PWR_UP
+    D6  - ESP8266_G0
+    D7  - ESP8266_G2
 
-	GPIO can output 3.3V 
-	D24  - AD7606_RESET
-	D25  - AD7606_RAGE
-	D26  - Y33_2
-	D27  - Y33_3
-	D28  - Y33_4
-	D29  - Y33_5
-	D30  - Y33_6
-	D31  - Y33_7				
+    D8  - LED1
+    D9  - LED2
+    D10 - LED3
+    D11 - LED4
+    D12 - TP_NRST
+    D13 - AD7606_OS0
+    D14 - AD7606_OS1
+    D15 - AD7606_OS2
+
+    GPIO can output 5V
+    D16  - Y50_0
+    D17  - Y50_1
+    D18  - Y50_2
+    D19  - Y50_3
+    D20  - Y50_4
+    D21  - Y50_5
+    D22  - Y50_6
+    D23  - Y50_7
+
+    GPIO can output 3.3V
+    D24  - AD7606_RESET
+    D25  - AD7606_RAGE
+    D26  - Y33_2
+    D27  - Y33_3
+    D28  - Y33_4
+    D29  - Y33_5
+    D30  - Y33_6
+    D31  - Y33_7
 */
 
 #ifndef GPIO_Pin_0
-	#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
-	#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
-	#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
-	#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
-	#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
-	#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
-	#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
-	#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
-	#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
-	#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
-	#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
-	#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
-	#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
-	#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
-	#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
-	#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
-#endif	
+    #define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+    #define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+    #define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+    #define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+    #define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+    #define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+    #define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+    #define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+    #define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+    #define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+    #define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+    #define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+    #define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+    #define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+    #define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+    #define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#endif
 
 #define GPIO_Pin_16                 ((uint32_t)0x00010000)  /* Pin 0 selected */
 #define GPIO_Pin_17                 ((uint32_t)0x00020000)  /* Pin 1 selected */
@@ -90,42 +90,42 @@
 #define GPIO_Pin_31                 ((uint32_t)0x80000000)  /* Pin 15 selected */
 
 /* Rename the macro for the sake of memory */
-#define	GPRS_TERM_ON   GPIO_Pin_0
-#define	GPRS_RESET     GPIO_Pin_1
-#define	NRF24L01_CE    GPIO_Pin_2
-#define	NRF905_TX_EN   GPIO_Pin_3
-#define	NRF905_TRX_CE  GPIO_Pin_4
+#define GPRS_TERM_ON   GPIO_Pin_0
+#define GPRS_RESET     GPIO_Pin_1
+#define NRF24L01_CE    GPIO_Pin_2
+#define NRF905_TX_EN   GPIO_Pin_3
+#define NRF905_TRX_CE  GPIO_Pin_4
   #define VS1053_XDCS    GPIO_Pin_4
-#define	NRF905_PWR_UP  GPIO_Pin_5
-#define	ESP8266_G0     GPIO_Pin_6
-#define	ESP8266_G2     GPIO_Pin_7
-	
-#define	LED1           GPIO_Pin_8
-#define	LED2           GPIO_Pin_9
-#define	LED3           GPIO_Pin_10
-#define	LED4           GPIO_Pin_11
-#define	TP_NRST        GPIO_Pin_12
-#define	AD7606_OS0     GPIO_Pin_13
-#define	AD7606_OS1     GPIO_Pin_14
-#define	AD7606_OS2     GPIO_Pin_15
-	
-#define	Y50_0          GPIO_Pin_16
-#define	Y50_1          GPIO_Pin_17
-#define	Y50_2          GPIO_Pin_18
-#define	Y50_3          GPIO_Pin_19
-#define	Y50_4          GPIO_Pin_20
-#define	Y50_5          GPIO_Pin_21
-#define	Y50_6          GPIO_Pin_22
-#define	Y50_7          GPIO_Pin_23	
+#define NRF905_PWR_UP  GPIO_Pin_5
+#define ESP8266_G0     GPIO_Pin_6
+#define ESP8266_G2     GPIO_Pin_7
 
-#define	AD7606_RESET   GPIO_Pin_24
-#define	AD7606_RANGE   GPIO_Pin_25
-#define	Y33_2          GPIO_Pin_26
-#define	Y33_3          GPIO_Pin_27
-#define	Y33_4          GPIO_Pin_28
-#define	Y33_5          GPIO_Pin_29
-#define	Y33_6          GPIO_Pin_30
-#define	Y33_7          GPIO_Pin_31
+#define LED1           GPIO_Pin_8
+#define LED2           GPIO_Pin_9
+#define LED3           GPIO_Pin_10
+#define LED4           GPIO_Pin_11
+#define TP_NRST        GPIO_Pin_12
+#define AD7606_OS0     GPIO_Pin_13
+#define AD7606_OS1     GPIO_Pin_14
+#define AD7606_OS2     GPIO_Pin_15
+
+#define Y50_0          GPIO_Pin_16
+#define Y50_1          GPIO_Pin_17
+#define Y50_2          GPIO_Pin_18
+#define Y50_3          GPIO_Pin_19
+#define Y50_4          GPIO_Pin_20
+#define Y50_5          GPIO_Pin_21
+#define Y50_6          GPIO_Pin_22
+#define Y50_7          GPIO_Pin_23
+
+#define AD7606_RESET   GPIO_Pin_24
+#define AD7606_RANGE   GPIO_Pin_25
+#define Y33_2          GPIO_Pin_26
+#define Y33_3          GPIO_Pin_27
+#define Y33_4          GPIO_Pin_28
+#define Y33_5          GPIO_Pin_29
+#define Y33_6          GPIO_Pin_30
+#define Y33_7          GPIO_Pin_31
 
 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value);
 rt_uint8_t HC574_GetPin(rt_uint32_t _pin);
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
index 31e2b9a392..0fda729291 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
index 36296b486a..6d97b5a979 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
index b46537d311..6a79c83523 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
index 1e57acb19f..9b5a363b6f 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
index e8fd133824..ac58f66259 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c
index 487ddf44f6..6d19a46edb 100644
--- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c
index c13619f753..36d2ff17d3 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,11 +18,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -39,13 +39,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h
index 9173f50c46..077b0af713 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
index ce1021fb60..889c5b0dee 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -86,7 +86,7 @@ void SAIB_config_set(struct rt_audio_configure config)
     SAIB_samplerate_set(config.samplerate);
     SAIB_samplebits_set(config.samplebits);
 }
-		
+
 static void SAIB_config_init()
 {
     _sai_b.hsai.Instance = SAI1_Block_B;
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
index 8aeede498c..0cc55f7aa9 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,10 +8,10 @@
  * 2019-07-28     Ernest         the first version
  */
 
-#ifndef __DRV_MIC_H_ 
-#define __DRV_MIC_H_ 
+#ifndef __DRV_MIC_H_
+#define __DRV_MIC_H_
 
-#include <rtthread.h> 
+#include <rtthread.h>
 #include <rtdevice.h>
 
 #endif
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
index 4a51ef6347..f564cc1b84 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@
 #define DBG_LVL              DBG_INFO
 #include <rtdbg.h>
 
-#define	CODEC_I2C_NAME  ("i2c1")
+#define CODEC_I2C_NAME  ("i2c1")
 
 #define TX_DMA_FIFO_SIZE (2048)
 
@@ -49,7 +49,7 @@ void SAIA_samplerate_set(rt_uint32_t freq)
 {
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
     int i;
-    
+
     /* check frequence */
     for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++)
     {
@@ -60,12 +60,12 @@ void SAIA_samplerate_set(rt_uint32_t freq)
         LOG_E("Can not support this frequence: %d.", freq);
         return;
     }
-    
+
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1];
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2];
     PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1;
-    
+
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
     __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S);
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
index 216481444f..28a1ea210d 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
@@ -1,19 +1,19 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author         Notes
- * 2019-07-28     Ernest         the first version 
+ * 2019-07-28     Ernest         the first version
  */
 
-#ifndef __DRV_SOUND_H_ 
-#define __DRV_SOUND_H_ 
+#ifndef __DRV_SOUND_H_
+#define __DRV_SOUND_H_
 
-#include <rtthread.h> 
+#include <rtthread.h>
 #include <rtdevice.h>
-#include <board.h> 
+#include <board.h>
 
 #define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000)
 #define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
index 5c7b8084c4..0f650538f9 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -763,8 +763,8 @@ rt_err_t wm8978_init(struct rt_i2c_bus_device *dev)
 
     wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16);
     wm8978_mic_enabled(dev, 0);
-	
-  	return RT_EOK;
+
+    return RT_EOK;
 }
 
 void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
index d385255f9c..fe476ec0bb 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
index 666d053b25..826f8c7ded 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,8 +16,8 @@
 #include <drv_log.h>
 
 #define ETH_RESET_IO    7                //PHY RESET PIN
-#define I2C_BUS_NAME	"i2c1"
-#define PCF8574_ADDR 	0x20
+#define I2C_BUS_NAME    "i2c1"
+#define PCF8574_ADDR    0x20
 
 /* pcf8574 hardware init */
 pcf8574_device_t pcf8574_hw_init(char * dev_name, int addr)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
index 10d0655a3a..fe2595fa4b 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
index ff948cb61e..85697210fa 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
index 26a9b2d2a8..7e35a36c86 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c
index 1078b64286..64e40b75c8 100644
--- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c
+++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c
index ec47ab0d3a..5ca583d599 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/board.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h
index ab9e1733e9..c51f6a93cc 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/board.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
index 2660f3931b..8d297ec915 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
index 298dd14e29..8eaf6dcd5a 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
index d7b740ae47..01111ab4d3 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
index 72d7c8d06d..1e5978871b 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
index 5a1a4a2585..94a550cf37 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
index 277a754ae6..2660e6ef7c 100644
--- a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
+++ b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/applications/main.c b/bsp/stm32/stm32f429-st-disco/applications/main.c
index 8e6e8caef1..992f2b5d74 100644
--- a/bsp/stm32/stm32f429-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f429-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/board.c b/bsp/stm32/stm32f429-st-disco/board/board.c
index 0abc70267a..542681ae0b 100644
--- a/bsp/stm32/stm32f429-st-disco/board/board.c
+++ b/bsp/stm32/stm32f429-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -48,7 +48,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /*##-2- LTDC Clock Configuration ###########################################*/  
+  /*##-2- LTDC Clock Configuration ###########################################*/
   /* LCD clock configuration */
   /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
   /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */
@@ -58,5 +58,5 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
   PeriphClkInitStruct.PLLSAI.PLLSAIR = 4;
   PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); 
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 }
diff --git a/bsp/stm32/stm32f429-st-disco/board/board.h b/bsp/stm32/stm32f429-st-disco/board/board.h
index 69e3eb1fac..ce8f2cc591 100644
--- a/bsp/stm32/stm32f429-st-disco/board/board.h
+++ b/bsp/stm32/stm32f429-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
index 46ecb322c4..ac75718bc7 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0;
     &nor_flash0,                                                     \
 }
 
-#define ONCHIP_FLASH_PART_TABLE 
+#define ONCHIP_FLASH_PART_TABLE
 
 #define QSPI_FLASH_PART_TABLE \
     {FAL_PART_MAGIC_WROD, "qspiflash",  FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0},
@@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0;
     {FAL_PART_MAGIC_WROD, "param",      "onchip_flash_64k",  0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
     {FAL_PART_MAGIC_WROD, "app",        "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0},
 
-#define QSPI_FLASH_PART_TABLE 
+#define QSPI_FLASH_PART_TABLE
 
 #else
 
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
index 3829193b5c..eaab59c78d 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
@@ -25,28 +25,28 @@
 #include "stm32f4xx_hal.h"
 #include "ili9341.h"
 
-/** 
-  * @brief  LCD Control pin  
-  */ 
+/**
+  * @brief  LCD Control pin
+  */
 #define LCD_NCS_PIN                             GPIO_PIN_2
 #define LCD_NCS_GPIO_PORT                       GPIOC
 #define LCD_NCS_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOC_CLK_ENABLE()
 #define LCD_NCS_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOC_CLK_DISABLE()
 
-/** 
-  * @brief  LCD Command/data pin  
+/**
+  * @brief  LCD Command/data pin
   */
 #define LCD_WRX_PIN                             GPIO_PIN_13
 #define LCD_WRX_GPIO_PORT                       GPIOD
 #define LCD_WRX_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOD_CLK_ENABLE()
 #define LCD_WRX_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOD_CLK_DISABLE()
-  
+
 #define LCD_RDX_PIN                             GPIO_PIN_12
 #define LCD_RDX_GPIO_PORT                       GPIOD
 #define LCD_RDX_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOD_CLK_ENABLE()
 #define LCD_RDX_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOD_CLK_DISABLE()
 
-/* Maximum Timeout values for flags waiting loops */   
+/* Maximum Timeout values for flags waiting loops */
 #define SPIx_TIMEOUT_MAX              ((uint32_t)0x1000)
 
 /* Chip Select macro definition */
@@ -73,8 +73,8 @@ static void SPIx_Init(void)
   {
     /* SPI configuration -----------------------------------------------------*/
     SpiHandle.Instance = SPI5;
-    /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) 
-    */  
+    /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz)
+    */
     SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
 
     /* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */
@@ -90,9 +90,9 @@ static void SPIx_Init(void)
     SpiHandle.Init.NSS            = SPI_NSS_SOFT;
     SpiHandle.Init.TIMode         = SPI_TIMODE_DISABLED;
     SpiHandle.Init.Mode           = SPI_MODE_MASTER;
-  
+
     HAL_SPI_Init(&SpiHandle);
-  } 
+  }
 }
 
 /**
@@ -101,11 +101,11 @@ static void SPIx_Init(void)
 static void LCD_GPIO_Init(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
-  
+
   if(Is_LCD_IO_Initialized == 0)
   {
-    Is_LCD_IO_Initialized = 1; 
-    
+    Is_LCD_IO_Initialized = 1;
+
     /* Configure NCS in Output Push-Pull mode */
     LCD_WRX_GPIO_CLK_ENABLE();
     GPIO_InitStructure.Pin     = LCD_WRX_PIN;
@@ -113,28 +113,28 @@ static void LCD_GPIO_Init(void)
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure);
-    
+
     LCD_RDX_GPIO_CLK_ENABLE();
     GPIO_InitStructure.Pin     = LCD_RDX_PIN;
     GPIO_InitStructure.Mode    = GPIO_MODE_OUTPUT_PP;
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure);
-    
+
     /* Configure the LCD Control pins ----------------------------------------*/
     LCD_NCS_GPIO_CLK_ENABLE();
-    
+
     /* Configure NCS in Output Push-Pull mode */
     GPIO_InitStructure.Pin     = LCD_NCS_PIN;
     GPIO_InitStructure.Mode    = GPIO_MODE_OUTPUT_PP;
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-    
+
     /* Set or Reset the control line */
     LCD_CS_LOW();
     LCD_CS_HIGH();
-    
+
     SPIx_Init();
   }
 }
@@ -148,12 +148,12 @@ static void ili9341_write_data(uint16_t data)
 {
   /* Set WRX to send data */
   LCD_WRX_HIGH();
-  
-  /* Reset LCD control line(/CS) and Send data */  
+
+  /* Reset LCD control line(/CS) and Send data */
   LCD_CS_LOW();
-  
-	HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX);
-	
+
+    HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX);
+
   /* Deselect: Chip Select high */
   LCD_CS_HIGH();
 }
@@ -167,12 +167,12 @@ static void ili9341_write_register(uint8_t reg)
 {
   /* Reset WRX to send command */
   LCD_WRX_LOW();
-  
+
   /* Reset LCD control line(/CS) and Send command */
   LCD_CS_LOW();
-  
+
   HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &reg, 1, SPIx_TIMEOUT_MAX);
-  
+
   /* Deselect: Chip Select high */
   LCD_CS_HIGH();
 }
@@ -186,7 +186,7 @@ int ili9341_hw_init(void)
 {
   /* Initialize ILI9341 low level bus layer ----------------------------------*/
   LCD_GPIO_Init();
-  
+
   /* Configure LCD */
   ili9341_write_register(0xCA);
   ili9341_write_data(0xC3);
@@ -242,7 +242,7 @@ int ili9341_hw_init(void)
   ili9341_write_data(0xA7);
   ili9341_write_data(0x27);
   ili9341_write_data(0x04);
-  
+
   /* Colomn address set */
   ili9341_write_register(LCD_COLUMN_ADDR);
   ili9341_write_data(0x00);
@@ -259,13 +259,13 @@ int ili9341_hw_init(void)
   ili9341_write_data(0x01);
   ili9341_write_data(0x00);
   ili9341_write_data(0x06);
-  
+
   ili9341_write_register(LCD_GRAM);
   rt_thread_mdelay(20);
-  
+
   ili9341_write_register(LCD_GAMMA);
   ili9341_write_data(0x01);
-  
+
   ili9341_write_register(LCD_PGAMMA);
   ili9341_write_data(0x0F);
   ili9341_write_data(0x29);
@@ -298,14 +298,14 @@ int ili9341_hw_init(void)
   ili9341_write_data(0x28);
   ili9341_write_data(0x2F);
   ili9341_write_data(0x0F);
-  
+
   ili9341_write_register(LCD_SLEEP_OUT);
   rt_thread_mdelay(20);
   ili9341_write_register(LCD_DISPLAY_ON);
   /* GRAM start writing */
   ili9341_write_register(LCD_GRAM);
-	
-	return 0;
+
+    return 0;
 }
 INIT_DEVICE_EXPORT(ili9341_hw_init);
 
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
index b4c59e6ffa..895683be5c 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
@@ -26,16 +26,16 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 
-/** 
-  * @brief ILI9341 chip IDs  
-  */ 
+/**
+  * @brief ILI9341 chip IDs
+  */
 #define ILI9341_ID                  0x9341
 
-/** 
-  * @brief  ILI9341 Registers  
+/**
+  * @brief  ILI9341 Registers
   */
 
 /* Level 1 Commands */
@@ -57,32 +57,32 @@
 #define LCD_GAMMA               0x26   /* Gamma register */
 #define LCD_DISPLAY_OFF         0x28   /* Display off register */
 #define LCD_DISPLAY_ON          0x29   /* Display on register */
-#define LCD_COLUMN_ADDR         0x2A   /* Colomn address register */ 
-#define LCD_PAGE_ADDR           0x2B   /* Page address register */ 
-#define LCD_GRAM                0x2C   /* GRAM register */   
-#define LCD_RGBSET              0x2D   /* Color SET */   
-#define LCD_RAMRD               0x2E   /* Memory Read */   
-#define LCD_PLTAR               0x30   /* Partial Area */   
-#define LCD_VSCRDEF             0x33   /* Vertical Scrolling Definition */   
-#define LCD_TEOFF               0x34   /* Tearing Effect Line OFF */   
-#define LCD_TEON                0x35   /* Tearing Effect Line ON */   
+#define LCD_COLUMN_ADDR         0x2A   /* Colomn address register */
+#define LCD_PAGE_ADDR           0x2B   /* Page address register */
+#define LCD_GRAM                0x2C   /* GRAM register */
+#define LCD_RGBSET              0x2D   /* Color SET */
+#define LCD_RAMRD               0x2E   /* Memory Read */
+#define LCD_PLTAR               0x30   /* Partial Area */
+#define LCD_VSCRDEF             0x33   /* Vertical Scrolling Definition */
+#define LCD_TEOFF               0x34   /* Tearing Effect Line OFF */
+#define LCD_TEON                0x35   /* Tearing Effect Line ON */
 #define LCD_MAC                 0x36   /* Memory Access Control register*/
-#define LCD_VSCRSADD            0x37   /* Vertical Scrolling Start Address */   
-#define LCD_IDMOFF              0x38   /* Idle Mode OFF */   
-#define LCD_IDMON               0x39   /* Idle Mode ON */   
+#define LCD_VSCRSADD            0x37   /* Vertical Scrolling Start Address */
+#define LCD_IDMOFF              0x38   /* Idle Mode OFF */
+#define LCD_IDMON               0x39   /* Idle Mode ON */
 #define LCD_PIXEL_FORMAT        0x3A   /* Pixel Format register */
-#define LCD_WRITE_MEM_CONTINUE  0x3C   /* Write Memory Continue */   
-#define LCD_READ_MEM_CONTINUE   0x3E   /* Read Memory Continue */   
-#define LCD_SET_TEAR_SCANLINE   0x44   /* Set Tear Scanline */   
-#define LCD_GET_SCANLINE        0x45   /* Get Scanline */   
+#define LCD_WRITE_MEM_CONTINUE  0x3C   /* Write Memory Continue */
+#define LCD_READ_MEM_CONTINUE   0x3E   /* Read Memory Continue */
+#define LCD_SET_TEAR_SCANLINE   0x44   /* Set Tear Scanline */
+#define LCD_GET_SCANLINE        0x45   /* Get Scanline */
 #define LCD_WDB                 0x51   /* Write Brightness Display register */
-#define LCD_RDDISBV             0x52   /* Read Display Brightness */   
+#define LCD_RDDISBV             0x52   /* Read Display Brightness */
 #define LCD_WCD                 0x53   /* Write Control Display register*/
-#define LCD_RDCTRLD             0x54   /* Read CTRL Display */   
-#define LCD_WRCABC              0x55   /* Write Content Adaptive Brightness Control */   
-#define LCD_RDCABC              0x56   /* Read Content Adaptive Brightness Control */   
-#define LCD_WRITE_CABC          0x5E   /* Write CABC Minimum Brightness */   
-#define LCD_READ_CABC           0x5F   /* Read CABC Minimum Brightness */   
+#define LCD_RDCTRLD             0x54   /* Read CTRL Display */
+#define LCD_WRCABC              0x55   /* Write Content Adaptive Brightness Control */
+#define LCD_RDCABC              0x56   /* Read Content Adaptive Brightness Control */
+#define LCD_WRITE_CABC          0x5E   /* Write CABC Minimum Brightness */
+#define LCD_READ_CABC           0x5F   /* Read CABC Minimum Brightness */
 #define LCD_READ_ID1            0xDA   /* Read ID1 */
 #define LCD_READ_ID2            0xDB   /* Read ID2 */
 #define LCD_READ_ID3            0xDC   /* Read ID3 */
@@ -129,13 +129,13 @@
 /* Size of read registers */
 #define LCD_READ_ID4_SIZE        3      /* Size of Read ID4 */
 
-  
+
 /** @defgroup ILI9341_Exported_Functions
   * @{
-  */ 
+  */
 int ili9341_hw_init(void);
 
-      
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
index 6f8112cc1b..21801def62 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
index 77c80f58ff..5a9f83e7d6 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
index 8559b69f98..d70e444ef4 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -154,7 +154,7 @@ int32_t touch_get_state(struct touch_state *state)
     res = touch_read(STMPE811_TSC_CTRL, &val);
     if (res < 0) return -1;
     state->pressed = (val & (1 << 7)) ? 1 : 0;
-  
+
     if (state->pressed)
     {
         val = STMPE811_TSC_DATA;
@@ -218,7 +218,7 @@ static int rt_hw_touch_init(void)
 
     /* register touch device to RT-Thread */
     rt_device_register(&touch, "touch", RT_DEVICE_FLAG_RDWR);
-    
+
     return RT_EOK;
 }
 INIT_BOARD_EXPORT(rt_hw_touch_init);
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
index 68c8f92b7f..a7b6328f17 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f446-st-nucleo/applications/main.c b/bsp/stm32/stm32f446-st-nucleo/applications/main.c
index 0f283769a9..897c6eec1c 100644
--- a/bsp/stm32/stm32f446-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f446-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.c b/bsp/stm32/stm32f446-st-nucleo/board/board.c
index aba3df89e1..a2500ee68a 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f446-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,13 +35,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.h b/bsp/stm32/stm32f446-st-nucleo/board/board.h
index 1800e44079..8cb4438f8b 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f446-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
index 277a754ae6..2660e6ef7c 100644
--- a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
+++ b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/applications/main.c b/bsp/stm32/stm32f469-st-disco/applications/main.c
index 8feca19928..759572d376 100644
--- a/bsp/stm32/stm32f469-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f469-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/board.c b/bsp/stm32/stm32f469-st-disco/board/board.c
index 8c4c361dcc..fefb07fafd 100644
--- a/bsp/stm32/stm32f469-st-disco/board/board.c
+++ b/bsp/stm32/stm32f469-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -36,13 +36,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f469-st-disco/board/board.h b/bsp/stm32/stm32f469-st-disco/board/board.h
index 0880c1f384..607aa3877d 100644
--- a/bsp/stm32/stm32f469-st-disco/board/board.h
+++ b/bsp/stm32/stm32f469-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
index 84202f84c8..8fde3a56ae 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author         Notes
  * 2019-05-23     WillianChan    first version
  */
- 
+
 #include <board.h>
 #ifdef BSP_USING_LCD_OTM8009A
 extern DSI_HandleTypeDef hdsi;
@@ -93,9 +93,9 @@ const rt_uint8_t RDS49[] = {0xF5, 0x06};
 const rt_uint8_t RDS50[] = {0x00, 0xB1};
 const rt_uint8_t RDS51[] = {0xC6, 0x06};
 
-void otm8009a_reset(void) 
+void otm8009a_reset(void)
 {
-    rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); 
+    rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT);
     rt_pin_write(GET_PIN(H, 7), PIN_LOW);
     rt_thread_delay(rt_tick_from_millisecond(20));
     rt_pin_write(GET_PIN(H, 7), PIN_HIGH);
@@ -116,7 +116,7 @@ static void otm8009a_write_cmd(uint8_t *p, uint32_t num)
 
 static void otm8009a_delay(uint32_t d)
 {
-    rt_thread_delay(rt_tick_from_millisecond(d)); 
+    rt_thread_delay(rt_tick_from_millisecond(d));
 }
 
 static void otm8009a_config(rt_uint32_t pixel_format)
@@ -127,11 +127,11 @@ static void otm8009a_config(rt_uint32_t pixel_format)
     otm8009a_write_cmd((rt_uint8_t *)RDL02, 2);
     otm8009a_write_cmd((rt_uint8_t *)RDS02, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS03, 0);
-    otm8009a_delay(10); 
+    otm8009a_delay(10);
 
     otm8009a_write_cmd((rt_uint8_t *)RDS04, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS05, 0);
-    otm8009a_delay(10); 
+    otm8009a_delay(10);
 
     otm8009a_write_cmd((rt_uint8_t *)RDS06, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS07, 0);
@@ -215,8 +215,8 @@ static void otm8009a_config(rt_uint32_t pixel_format)
     otm8009a_write_cmd((rt_uint8_t *)RDS01, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDL04, 16);
     otm8009a_write_cmd((rt_uint8_t *)RDS36, 0);
-    otm8009a_delay(120); 
-    
+    otm8009a_delay(120);
+
     switch (pixel_format)
     {
     case RTGRAPHIC_PIXEL_FORMAT_RGB565:
@@ -248,7 +248,7 @@ void stm32_mipi_lcd_init(void)
 
 void stm32_mipi_lcd_config(rt_uint32_t pixel_format)
 {
-    otm8009a_config(pixel_format); 
+    otm8009a_config(pixel_format);
 }
 
 void stm32_mipi_display_on(void)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
index f5fe27d6e1..ff1b11e34c 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-11-27     zylx         first version
  * 2019-04-11     ZYH          port from stm32f7serial
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -64,7 +64,7 @@ void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL);
-    
+
     /* init n25qxx */
     if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10"))
     {
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
index cfe6f59e1e..9fd2d11fd4 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@
 static void _sdcard_mount(void)
 {
     rt_device_t device;
-    
+
     device = rt_device_find("sd0");
     if (device == NULL)
     {
@@ -56,7 +56,7 @@ static void _sdcard_unmount(void)
     rt_thread_mdelay(200);
     dfs_unmount("/");
     LOG_I("Unmount \"/\"");
-    
+
     mmcsd_wait_cd_changed(0);
     stm32_mmcsd_change();
     mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
@@ -65,7 +65,7 @@ static void _sdcard_unmount(void)
 static void sd_mount(void *parameter)
 {
     rt_uint8_t re_sd_check_pin = 1;
-    
+
     while (1)
     {
         rt_thread_mdelay(200);
@@ -73,7 +73,7 @@ static void sd_mount(void *parameter)
         {
             _sdcard_mount();
         }
-        
+
         if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
         {
             _sdcard_unmount();
@@ -84,7 +84,7 @@ static void sd_mount(void *parameter)
 int stm32_sdcard_mount(void)
 {
     rt_thread_t tid;
-    
+
     rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
 
     tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
index 46ecb322c4..ac75718bc7 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0;
     &nor_flash0,                                                     \
 }
 
-#define ONCHIP_FLASH_PART_TABLE 
+#define ONCHIP_FLASH_PART_TABLE
 
 #define QSPI_FLASH_PART_TABLE \
     {FAL_PART_MAGIC_WROD, "qspiflash",  FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0},
@@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0;
     {FAL_PART_MAGIC_WROD, "param",      "onchip_flash_64k",  0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
     {FAL_PART_MAGIC_WROD, "app",        "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0},
 
-#define QSPI_FLASH_PART_TABLE 
+#define QSPI_FLASH_PART_TABLE
 
 #else
 
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
index d5ee2b13b4..b23a970538 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,19 +7,19 @@
  * Date           Author         Notes
  * 2018-07-28     liu2guang      the first version for STM32F469NI-Discovery.
  */
- 
-#ifndef __DRV_LCD_H_ 
-#define __DRV_LCD_H_ 
 
-#include <rtthread.h> 
+#ifndef __DRV_LCD_H_
+#define __DRV_LCD_H_
+
+#include <rtthread.h>
 #include <rtdevice.h>
-#include <board.h> 
+#include <board.h>
 
 #define  LCD_WIDTH    (800U)
 #define  LCD_HEIGHT   (480U)
 
 #define  LCD_HSYNC    (1U)
-#define  LCD_HBP      (15U) 
+#define  LCD_HBP      (15U)
 #define  LCD_HFP      (16U)
 #define  LCD_VSYNC    (2U)
 #define  LCD_VBP      (34U)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
index f90b468463..5b311a391a 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
index 14d44f7115..7b33d36362 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
index 1ff29544ff..53437f34ef 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-02-08     Zhangyihong  the first version
  */
- 
+
 #include "drv_touch.h"
 #include <string.h>
 #ifdef BSP_USING_TOUCH
@@ -105,7 +105,7 @@ static void touch_thread_entry(void *parameter)
         {
             continue;
         }
-        
+
         while(touch->ops->read_point(&msg) == RT_EOK)
         {
             switch (msg.event)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
index a8fea21d54..21bea39f83 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-02-08     Zhangyihong  the first version
  */
- 
+
 #ifndef __DRV_TOUCH_H__
 #define __DRV_TOUCH_H__
 
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
index a7e9275441..e85e793573 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -109,7 +109,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     {
         return RT_ERROR;
     }
-    
+
     if (point_num == 0)
     {
         if (s_tp_down)
@@ -121,7 +121,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
         msg->event = TOUCH_EVENT_NONE;
         return RT_ERROR;
     }
-    
+
     ret = ft_read(ft_i2c_bus, 0x03, point, 6);
     if (ret < 0)
     {
@@ -130,7 +130,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
 
     msg->y = (point[0]&0x0F) << 8 | point[1];
     msg->x = (point[2]&0x0F) << 8 | point[3];
-    
+
     if (s_tp_down)
     {
         msg->event = TOUCH_EVENT_MOVE;
@@ -138,7 +138,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     }
     msg->event = TOUCH_EVENT_DOWN;
     s_tp_down = 1;
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32f746-st-disco/applications/main.c b/bsp/stm32/stm32f746-st-disco/applications/main.c
index 669d889e58..0024ce1c0a 100644
--- a/bsp/stm32/stm32f746-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f746-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/board.c b/bsp/stm32/stm32f746-st-disco/board/board.c
index bf92d115e7..da2564d515 100644
--- a/bsp/stm32/stm32f746-st-disco/board/board.c
+++ b/bsp/stm32/stm32f746-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f746-st-disco/board/board.h b/bsp/stm32/stm32f746-st-disco/board/board.h
index 98e3799e00..b0c120fb41 100644
--- a/bsp/stm32/stm32f746-st-disco/board/board.h
+++ b/bsp/stm32/stm32f746-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
index ca7641f866..4e37f4ec2f 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2019-01-26     jinsheng     first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -63,7 +63,7 @@ void n25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init n25q128 */
     if (RT_NULL == rt_sfud_flash_probe("n25q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
index c886dab45d..d7ce293475 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
index f534e50522..8ea00b0ed4 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
index 3d5f75c7f0..5825f775cc 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
index 0797f9326c..66e8dfefab 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
index 4c49e0f217..91bb91b01b 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/applications/main.c b/bsp/stm32/stm32f767-atk-apollo/applications/main.c
index 7d7440f05c..71e6132ea2 100644
--- a/bsp/stm32/stm32f767-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32f767-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.c b/bsp/stm32/stm32f767-atk-apollo/board/board.c
index d9959f9301..726b7783b7 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,15 +16,15 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -41,13 +41,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.h b/bsp/stm32/stm32f767-atk-apollo/board/board.h
index 3d986024ae..e91271055e 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
index 5cabc9d4d2..72e589aea4 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init W25Q256 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
index 891beb2010..5ddddaa2cd 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
index ca894bb045..156ba2e2cf 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
index d00e6c06e0..18bed5f8e4 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
index 0a9c36fd42..bc7e8b676e 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
index ff948cb61e..85697210fa 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c
index 9ed6529712..4cf67f2e9e 100644
--- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c
+++ b/bsp/stm32/stm32f767-fire-challenger/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.c b/bsp/stm32/stm32f767-fire-challenger/board/board.c
index f5b0c783c7..de621405e1 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/board.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -34,13 +34,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.h b/bsp/stm32/stm32f767-fire-challenger/board/board.h
index 1beb8c5f87..e9a1277849 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/board.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
index 36ecb754e9..a3091fd2eb 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init w25q128 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
index 891beb2010..5ddddaa2cd 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
index 2660f3931b..8d297ec915 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
index 298dd14e29..8eaf6dcd5a 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
index 615ad6e06e..f1a7b8c27f 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
index 0d9c7e6918..7f9485aa4a 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-st-nucleo/applications/main.c b/bsp/stm32/stm32f767-st-nucleo/applications/main.c
index ed3fc2c341..a0967c1326 100644
--- a/bsp/stm32/stm32f767-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f767-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,5 +30,5 @@ int main(void)
         rt_thread_mdelay(500);
     }
 
-    return RT_EOK;		
+    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.c b/bsp/stm32/stm32f767-st-nucleo/board/board.c
index 0c63bfe489..4e00f26886 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f767-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,14 +21,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.h b/bsp/stm32/stm32f767-st-nucleo/board/board.h
index 1d1e1d1106..1d82defe0d 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f767-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
index 8a833eec2a..79b8fecc16 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,6 @@ void phy_reset(void)
      * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin,
      * so no additional reset is required.
      */
-    
+
     return ;
 }
diff --git a/bsp/stm32/stm32f769-st-disco/applications/main.c b/bsp/stm32/stm32f769-st-disco/applications/main.c
index 14a2f68f81..d61afe14c3 100644
--- a/bsp/stm32/stm32f769-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f769-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f769-st-disco/board/board.c b/bsp/stm32/stm32f769-st-disco/board/board.c
index 97bbbe3076..55126435b1 100644
--- a/bsp/stm32/stm32f769-st-disco/board/board.c
+++ b/bsp/stm32/stm32f769-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f769-st-disco/board/board.h b/bsp/stm32/stm32f769-st-disco/board/board.h
index 85c900e4c8..813dd5b27e 100644
--- a/bsp/stm32/stm32f769-st-disco/board/board.h
+++ b/bsp/stm32/stm32f769-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
index ca76f6e337..0a4f3f5216 100644
--- a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,6 @@ void phy_reset(void)
      * The PHY reset pin of DISCO-F769NI is connected to the MCU reset pin,
      * so no additional reset is required.
      */
-    
+
     return ;
 }
diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/main.c b/bsp/stm32/stm32g070-st-nucleo/applications/main.c
index 8541bd3b9f..5f22fcae65 100644
--- a/bsp/stm32/stm32g070-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g070-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.c b/bsp/stm32/stm32g070-st-nucleo/board/board.c
index 0c907528d0..101f483d27 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g070-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.h b/bsp/stm32/stm32g070-st-nucleo/board/board.h
index f0345a1293..d36387892b 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g070-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
index ee65e188d9..277b98ba70 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g071-st-nucleo/applications/main.c b/bsp/stm32/stm32g071-st-nucleo/applications/main.c
index 8541bd3b9f..5f22fcae65 100644
--- a/bsp/stm32/stm32g071-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g071-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.c b/bsp/stm32/stm32g071-st-nucleo/board/board.c
index 5d634db15e..28d4e56e46 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g071-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,10 +16,10 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
@@ -48,7 +48,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the peripherals clocks 
+  /**Initializes the peripherals clocks
   */
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
   PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.h b/bsp/stm32/stm32g071-st-nucleo/board/board.h
index f0345a1293..d36387892b 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g071-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
index ee65e188d9..277b98ba70 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g431-st-nucleo/applications/main.c b/bsp/stm32/stm32g431-st-nucleo/applications/main.c
index aad9acb9b9..fa4fd35a6e 100644
--- a/bsp/stm32/stm32g431-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g431-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.c b/bsp/stm32/stm32g431-st-nucleo/board/board.c
index f025a3e234..7aeb088632 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g431-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,10 +17,10 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -49,7 +49,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the peripherals clocks 
+  /** Initializes the peripherals clocks
   */
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
   PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.h b/bsp/stm32/stm32g431-st-nucleo/board/board.h
index 9b91078b0f..6fd0c97890 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g431-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/applications/main.c b/bsp/stm32/stm32h743-atk-apollo/applications/main.c
index 19a43a12e6..376d3c78ff 100644
--- a/bsp/stm32/stm32h743-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32h743-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,9 +18,9 @@
 int main(void)
 {
     int count = 1;
-    /* set LED0 pin mode to output */	
-    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);	
-	
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.c b/bsp/stm32/stm32h743-atk-apollo/board/board.c
index 0ae3016460..a96ed203a7 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,22 +16,22 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Supply configuration update enable 
+  /** Supply configuration update enable
   */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Macro to configure the PLL clock source 
+  /** Macro to configure the PLL clock source
   */
   __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -52,7 +52,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.h b/bsp/stm32/stm32h743-atk-apollo/board/board.h
index ffb9772ee7..c9ec7a30d9 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
   #define LSI_VALUE  ((uint32_t)32000)
 #endif
 
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
index 5f4d8b1b80..929d317afa 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -55,7 +55,7 @@ int mpu_init(void)
     /* Enable CACHE */
     SCB_EnableICache();
     SCB_EnableDCache();
-    
+
     return 0;
 
 }
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
index 8a57c37e01..cc170ff945 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
index af519987dd..d40ffc6926 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
index 0ed9345156..95e5784654 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ struct rt_i2c_bus_device *i2c_bus  = RT_NULL;
 #define JPEG_LINE_SIZE  1 * 1024
 
 static pcf8574_device_t pcf_dev = RT_NULL;
-   
+
 static rt_uint32_t *jpeg_data_buf = RT_NULL;
 static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE];
 static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE];
@@ -454,7 +454,7 @@ rt_uint8_t ov2640_set_image_window_size(rt_uint16_t offx, rt_uint16_t offy, rt_u
    temp|=(offy>>4)&0X70;
    temp|=(hsize>>5)&0X08;
    temp|=(offx>>8)&0X07;
-   write_reg(i2c_bus, 0X55,temp); 
+   write_reg(i2c_bus, 0X55,temp);
    write_reg(i2c_bus, 0X57,(hsize>>2)&0X80);
    write_reg(i2c_bus, 0XE0,0X00);
    return 0;
@@ -550,36 +550,36 @@ int ov2640_pwdn_set(rt_uint8_t sta)
         return -1;
     }
     pcf8574_pin_write(pcf_dev, DCMI_PWDN_IO, sta);
-    
+
     return 0;
 }
 
 void sw_ov2640_mode(void)
-{  
+{
     GPIO_InitTypeDef GPIO_Initure = {0};
-    
+
     ov2640_pwdn_set(0);
-    
-    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;  
-    GPIO_Initure.Mode      = GPIO_MODE_AF_PP; 
-    GPIO_Initure.Pull      = GPIO_PULLUP;     
-    GPIO_Initure.Speed     = GPIO_SPEED_HIGH; 
-    GPIO_Initure.Alternate = GPIO_AF13_DCMI;    
-    HAL_GPIO_Init(GPIOC,&GPIO_Initure);  
-} 
+
+    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;
+    GPIO_Initure.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Initure.Pull      = GPIO_PULLUP;
+    GPIO_Initure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_Initure.Alternate = GPIO_AF13_DCMI;
+    HAL_GPIO_Init(GPIOC,&GPIO_Initure);
+}
 
 void sw_sdcard_mode(void)
 {
     GPIO_InitTypeDef GPIO_Initure = {0};
-    
-    ov2640_pwdn_set(1); /* OV2640 Power Down */ 
 
-    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;  
-    GPIO_Initure.Mode      = GPIO_MODE_AF_PP; 
+    ov2640_pwdn_set(1); /* OV2640 Power Down */
+
+    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;
+    GPIO_Initure.Mode      = GPIO_MODE_AF_PP;
     GPIO_Initure.Pull      = GPIO_PULLUP;
-    GPIO_Initure.Speed     = GPIO_SPEED_HIGH; 
-    GPIO_Initure.Alternate = GPIO_AF12_SDMMC1;   
-    HAL_GPIO_Init(GPIOC, &GPIO_Initure);   
+    GPIO_Initure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_Initure.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOC, &GPIO_Initure);
 }
 
 int rt_ov2640_init(void)
@@ -587,7 +587,7 @@ int rt_ov2640_init(void)
     rt_uint16_t i = 0;
     rt_err_t result = RT_EOK;
     rt_device_t dcmi_dev = RT_NULL;
-    
+
     sw_ov2640_mode();
     pcf_dev = pcf8574_init("i2c1", RT_NULL);
     if (pcf_dev == RT_NULL)
@@ -595,17 +595,17 @@ int rt_ov2640_init(void)
         LOG_E("can't find pcf8574, please check it");
         return -RT_ERROR;
     }
-    
+
     ov2640_pwdn_set(0);
-	rt_thread_delay(20);
-    
+    rt_thread_delay(20);
+
     /* ov2640 hard reset */
     rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
     rt_pin_write(RESET_PIN, PIN_LOW);
     rt_thread_delay(20);
     rt_pin_write(RESET_PIN, PIN_HIGH);
     rt_thread_delay(20);
-    
+
     i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
     if (i2c_bus == RT_NULL)
     {
@@ -687,7 +687,7 @@ int camera_sample(int argc, char **argv)
        rt_kprintf("camera_sample file.jpg\n");
        return -1;
    }
-   
+
    sw_ov2640_mode();
    DCMI_Start();
 
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
index 4ff948b0c6..e85e559421 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
index 5cabc9d4d2..72e589aea4 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init W25Q256 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10"))
     {
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
index 07776296f0..a2789227a6 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
index 63f193e848..276064ddad 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
index 64c244f095..ca0c7a01b9 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
index ca894bb045..156ba2e2cf 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
index 5784f79036..50804561eb 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-st-nucleo/applications/main.c b/bsp/stm32/stm32h743-st-nucleo/applications/main.c
index 2a4d35d4d8..9a8ac51bb5 100644
--- a/bsp/stm32/stm32h743-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32h743-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.c b/bsp/stm32/stm32h743-st-nucleo/board/board.c
index dc2e79d04f..b5a5a4245d 100644
--- a/bsp/stm32/stm32h743-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32h743-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.h b/bsp/stm32/stm32h743-st-nucleo/board/board.h
index 72d84ff29d..32eb25f147 100644
--- a/bsp/stm32/stm32h743-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32h743-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h747-st-discovery/applications/main.c b/bsp/stm32/stm32h747-st-discovery/applications/main.c
index 9840fc6618..3904f7b3bc 100644
--- a/bsp/stm32/stm32h747-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32h747-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.c b/bsp/stm32/stm32h747-st-discovery/board/board.c
index a7af6b13f8..73f2013e66 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/board.c
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.h b/bsp/stm32/stm32h747-st-discovery/board/board.h
index c3441d01b1..85196a7664 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/board.h
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
index 73691fa783..b19e338dc5 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
index 7783d407a8..6426138e1e 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,18 +20,18 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Supply configuration update enable 
+  /** Supply configuration update enable
   */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-  /** Macro to configure the PLL clock source 
+  /** Macro to configure the PLL clock source
   */
   __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -50,7 +50,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
index a0455aec76..b41ed17e43 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/main.c b/bsp/stm32/stm32l010-st-nucleo/applications/main.c
index 8541bd3b9f..5f22fcae65 100644
--- a/bsp/stm32/stm32l010-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l010-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.c b/bsp/stm32/stm32l010-st-nucleo/board/board.c
index 858d59660f..62621eed0a 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l010-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -56,11 +56,11 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.h b/bsp/stm32/stm32l010-st-nucleo/board/board.h
index 9ca68af470..67e4ad5ec0 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l010-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l053-st-nucleo/applications/main.c b/bsp/stm32/stm32l053-st-nucleo/applications/main.c
index 8541bd3b9f..5f22fcae65 100644
--- a/bsp/stm32/stm32l053-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l053-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.c b/bsp/stm32/stm32l053-st-nucleo/board/board.c
index 858d59660f..62621eed0a 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l053-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -56,11 +56,11 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.h b/bsp/stm32/stm32l053-st-nucleo/board/board.h
index 016e4ec4e3..f88ee51946 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l053-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/main.c b/bsp/stm32/stm32l412-st-nucleo/applications/main.c
index 2511e7a3bc..b22a9d1ba3 100644
--- a/bsp/stm32/stm32l412-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l412-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.c b/bsp/stm32/stm32l412-st-nucleo/board/board.c
index 70a17da702..1ac2bc2df9 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l412-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,13 +17,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -41,7 +41,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -62,22 +62,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.h b/bsp/stm32/stm32l412-st-nucleo/board/board.h
index e88c9168b4..1f1519158f 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l412-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l431-BearPi/applications/main.c b/bsp/stm32/stm32l431-BearPi/applications/main.c
index 8bda11b8cd..9222b842fc 100644
--- a/bsp/stm32/stm32l431-BearPi/applications/main.c
+++ b/bsp/stm32/stm32l431-BearPi/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l431-BearPi/board/board.c b/bsp/stm32/stm32l431-BearPi/board/board.c
index 368ab74da1..b1a9d3d860 100644
--- a/bsp/stm32/stm32l431-BearPi/board/board.c
+++ b/bsp/stm32/stm32l431-BearPi/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE
                               |RCC_OSCILLATORTYPE_MSI;
@@ -43,7 +43,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -65,22 +65,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l431-BearPi/board/board.h b/bsp/stm32/stm32l431-BearPi/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l431-BearPi/board/board.h
+++ b/bsp/stm32/stm32l431-BearPi/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l432-st-nucleo/applications/main.c b/bsp/stm32/stm32l432-st-nucleo/applications/main.c
index e1755ec81e..336347c11e 100644
--- a/bsp/stm32/stm32l432-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l432-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.c b/bsp/stm32/stm32l432-st-nucleo/board/board.c
index 79f7c0344f..93000dc18c 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l432-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,13 +17,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -42,7 +42,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -63,22 +63,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.h b/bsp/stm32/stm32l432-st-nucleo/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l432-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l433-st-nucleo/applications/main.c b/bsp/stm32/stm32l433-st-nucleo/applications/main.c
index 43c2522c51..056bad6689 100644
--- a/bsp/stm32/stm32l433-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l433-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.c b/bsp/stm32/stm32l433-st-nucleo/board/board.c
index 0cf319801f..284b759c59 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l433-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,11 +20,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -42,7 +42,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -65,13 +65,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Enable MSI Auto calibration 
+  /** Enable MSI Auto calibration
   */
   HAL_RCCEx_EnableMSIPLLMode();
 }
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.h b/bsp/stm32/stm32l433-st-nucleo/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l433-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l452-st-nucleo/applications/main.c b/bsp/stm32/stm32l452-st-nucleo/applications/main.c
index aad9acb9b9..fa4fd35a6e 100644
--- a/bsp/stm32/stm32l452-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l452-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.c b/bsp/stm32/stm32l452-st-nucleo/board/board.c
index 5ab9da967a..d6c090b6b8 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l452-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -55,7 +55,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.h b/bsp/stm32/stm32l452-st-nucleo/board/board.h
index 1ea1e6be9c..0c9006dc40 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l452-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
index db782a5991..09c420dae9 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,9 +20,9 @@ extern const struct fal_flash_dev stm32_onchip_flash;
 
 /* ========================= Device Configuration ========================== */
 #ifdef BSP_USING_ON_CHIP_FLASH
-#define ONCHIP_FLASH_DEV     &stm32_onchip_flash,  
+#define ONCHIP_FLASH_DEV     &stm32_onchip_flash,
 #else
-#define ONCHIP_FLASH_DEV    
+#define ONCHIP_FLASH_DEV
 #endif /* BSP_USING_ON_CHIP_FLASH */
 
 /* flash device table */
diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
index 3283560274..a89c5e0b9c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
+++ b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,30 +18,30 @@
 
 static int lcd_sample(void)
 {
-    /* ÇåÆÁ */
+    /* 清� */
     lcd_clear(WHITE);
 
-    /* ÏÔʾ RT-Thread logo */
+    /* 显示 RT-Thread logo */
     lcd_show_image(0, 0, 240, 69, image_rttlogo);
-    
-    /* ÉèÖñ³¾°É«ºÍÇ°¾°É« */
+
+    /* 设置背景色和�景色 */
     lcd_set_color(WHITE, BLACK);
 
-    /* ÔÚ LCD ÉÏÏÔʾ×Ö·û */
+    /* 在 LCD 上显示字符 */
     lcd_show_string(10, 69, 16, "Hello, RT-Thread!");
     lcd_show_string(10, 69+16, 24, "RT-Thread");
     lcd_show_string(10, 69+16+24, 32, "RT-Thread");
-    
-    /* ÔÚ LCD ÉÏ»­Ïß */
+
+    /* 在 LCD 上画线 */
     lcd_draw_line(0, 69+16+24+32, 240, 69+16+24+32);
-    
-    /* ÔÚ LCD ÉÏ»­Ò»¸öͬÐÄÔ² */
+
+    /* 在 LCD 上画一个�心圆 */
     lcd_draw_point(120, 194);
     for (int i = 0; i < 46; i += 4)
     {
         lcd_draw_circle(120, 194, i);
     }
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(lcd_sample);
diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c
index 97e08a7d42..dfad8c68c1 100644
--- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c
+++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c
index e97c6784ae..d711d2c3d6 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/board.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c
@@ -22,11 +22,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -44,7 +44,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -76,7 +76,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h
index ee516b50db..a1029a3e99 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/board.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
index fe115eb593..5d9844c6bd 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
index 472c844fca..ac758960f8 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
index c4ea570dd7..ac604875f0 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
index bccf9c62db..b19d584d3d 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
index 4dc76631c7..d573b0dee5 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
index 65bdcd85f9..f80ca3a4b2 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -955,7 +955,7 @@ rt_err_t lcd_show_qrcode(rt_uint16_t x, rt_uint16_t y, rt_uint8_t version, rt_ui
         {
             enlargement_factor = enlargement;
         }
-        
+
         /* malloc memory for quick display of qrcode */
         qrcode_buf = rt_malloc(qrcode.size * 2 * enlargement_factor * enlargement_factor);
         if (qrcode_buf == RT_NULL)
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
index ca4c28595f..394305012e 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author            Notes
  * 2018-08-14    flybreak           the first version
- * 2018-09-18    balanceTWK         add sleep mode function 
+ * 2018-09-18    balanceTWK         add sleep mode function
  */
 
 #ifndef __DRV_LCD_H__
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
index d73d3c4d62..a326936b7b 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
@@ -1,5 +1,5 @@
 #ifndef __DRV_LCD_FONT_H__
-#define __DRV_LCD_FONT_H__ 	   
+#define __DRV_LCD_FONT_H__
 #include <stdint.h>
 /* DejaVu Sans Mono */
 /*
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
index aef2226239..f866d2741c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init w25q128 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
index 92ec9d539b..c7f561e0b7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,10 +46,10 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CCR &= ~0x00000001;
 
     DMA2->IFCR = DMA_ISR_GIF1 << 4;
-    
+
     DMA2_CSELR->CSELR &= ~(0xf << (3 * 4));   // channel 4
-    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); 
-    
+    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4));
+
     DMA2_Channel4->CCR   = DMA_MEMORY_TO_PERIPH | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \
                            DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM;
     DMA2_Channel4->CNDTR = BufferSize;
@@ -57,7 +57,7 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CMAR = (uint32_t)src;
 
     DMA2_Channel4->CCR  |= 0x00000001;
-    
+
 //    HAL_DMA_Start(&SDTxDMAHandler, (uint32_t)src, (uint32_t)dst, BufferSize);
 }
 
@@ -73,9 +73,9 @@ void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CCR &= ~0x00000001;
 
     DMA2->IFCR = DMA_ISR_GIF1 << 4;
-    
+
     DMA2_CSELR->CSELR &= ~(0xf << (3 * 4));   // channel 4
-    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); 
+    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4));
 
     DMA2_Channel4->CCR   = DMA_PERIPH_TO_MEMORY | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \
                            DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM;
@@ -130,7 +130,7 @@ void SD_LowLevel_Init(void)
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
         HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-        
+
         GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_11
                               | GPIO_PIN_12;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
index 91ebb73e1e..5655b27237 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 
+ *
  */
 
 #include <easyflash.h>
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
index a6d43e21ba..25ed2c3ff7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
index 3f1e4776b4..fc9a1c7ada 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
index 76272c8de2..bf4babd15f 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
index d253cc179e..fac1209a63 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
index fc5d4759e9..7f0986e0d7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -200,7 +200,7 @@ static int read_cfg(void *buff, int len)
     {
         return 0;
     }
-    
+
     return len;
 }
 
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
index 35a0fc8956..ee8477d9be 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
index 6c56cbcf6f..431a18008c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
index 461c5f0e8d..e940dd99e2 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-st-discovery/applications/main.c b/bsp/stm32/stm32l475-st-discovery/applications/main.c
index 2c4ca35a6b..bddb8abe63 100644
--- a/bsp/stm32/stm32l475-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32l475-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.c b/bsp/stm32/stm32l475-st-discovery/board/board.c
index bdd1307a91..cd2f9a5989 100644
--- a/bsp/stm32/stm32l475-st-discovery/board/board.c
+++ b/bsp/stm32/stm32l475-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -51,7 +51,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.h b/bsp/stm32/stm32l475-st-discovery/board/board.h
index e49d71c68c..2b5f830eb9 100644
--- a/bsp/stm32/stm32l475-st-discovery/board/board.h
+++ b/bsp/stm32/stm32l475-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/main.c b/bsp/stm32/stm32l476-st-nucleo/applications/main.c
index e92ed8da71..b22a8b8e8d 100644
--- a/bsp/stm32/stm32l476-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l476-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.c b/bsp/stm32/stm32l476-st-nucleo/board/board.c
index 88600d4b4f..0d279e679a 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l476-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.h b/bsp/stm32/stm32l476-st-nucleo/board/board.h
index b59fe1b3b6..c0b6a905ff 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l476-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/applications/main.c b/bsp/stm32/stm32l496-ali-developer/applications/main.c
index d4926deb07..86d1cf72dd 100644
--- a/bsp/stm32/stm32l496-ali-developer/applications/main.c
+++ b/bsp/stm32/stm32l496-ali-developer/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.c b/bsp/stm32/stm32l496-ali-developer/board/board.c
index f9413f8f98..a0886582d4 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/board.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/board.c
@@ -20,11 +20,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE
                               |RCC_OSCILLATORTYPE_MSI;
@@ -44,7 +44,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -77,7 +77,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.h b/bsp/stm32/stm32l496-ali-developer/board/board.h
index 78cc07314b..6d99022522 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/board.h
+++ b/bsp/stm32/stm32l496-ali-developer/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
index e37a67f4a1..be6c2a5744 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include <board.h>
 #include <drv_spi.h>
 #include <rtdevice.h>
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
index d7a1db25e9..a0598e9d83 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
index 8a2c1cade7..6abc52c3ba 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-st-nucleo/applications/main.c b/bsp/stm32/stm32l496-st-nucleo/applications/main.c
index 20931cb3af..efe91875b9 100644
--- a/bsp/stm32/stm32l496-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l496-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.c b/bsp/stm32/stm32l496-st-nucleo/board/board.c
index 370b558be0..29f27a354f 100644
--- a/bsp/stm32/stm32l496-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l496-st-nucleo/board/board.c
@@ -22,11 +22,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -44,7 +44,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -71,13 +71,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Enable MSI Auto calibration 
+  /** Enable MSI Auto calibration
   */
   HAL_RCCEx_EnableMSIPLLMode();
 }
diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.h b/bsp/stm32/stm32l496-st-nucleo/board/board.h
index b215ae9ee8..f9edac21da 100644
--- a/bsp/stm32/stm32l496-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l496-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
index df59d02ff9..2dbb2b2c81 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,12 +19,12 @@
 /* defined the LED3 pin: PB14 */
 #define LED3_PIN    GET_PIN(B, 14)
 
-#define LED_RUN_PIN	LED3_PIN
+#define LED_RUN_PIN LED3_PIN
 
 int main(void)
 {
     int count = 1;
-		
+
     rt_pin_mode(LED_RUN_PIN, PIN_MODE_OUTPUT);
 
     while (count++)
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
index 7ab82ccd58..4b1fccdb4e 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -38,7 +38,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
index 095f503423..b90222c6e3 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
- * 2019-04-09	  jhb
+ * 2019-04-09     jhb
  */
 
 #ifndef __BOARD_H__
diff --git a/bsp/stm32/stm32l4r9-st-eval/applications/main.c b/bsp/stm32/stm32l4r9-st-eval/applications/main.c
index ee74c2edd2..c53f70fb97 100644
--- a/bsp/stm32/stm32l4r9-st-eval/applications/main.c
+++ b/bsp/stm32/stm32l4r9-st-eval/applications/main.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
- * 2019-04-09     jhb   			  
+ * 2019-04-09     jhb
  */
 
 #include <rtthread.h>
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c
index af69f12729..cf4231f00c 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/board.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
     if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
     {
         Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -37,7 +37,7 @@ void SystemClock_Config(void)
     {
         Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -63,5 +63,5 @@ void SystemClock_Config(void)
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
     {
         Error_Handler();
-    }	
+    }
 }
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h
index f9f8adbcf8..7d85022bb4 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/board.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
- * 2019-04-09	  jhb
+ * 2019-04-09     jhb
  */
 
 #ifndef __BOARD_H__
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
index 8e926d7e2d..e00616eaac 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -706,17 +706,17 @@ void line()
     lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi");
     rt_uint8_t *ptr = lcd->lcd_info.framebuffer;
 
-		/* red */
-		for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i <LCD_DSI_BUF_SIZE/4/2+390; i++)
-		{
-				ptr[4 * i] = 0x00;
-				ptr[4 * i + 1] = 0x00;
-				ptr[4 * i + 2] = 0xFF;
-				ptr[4 * i + 3] = 0xFF;
-		}
-		rt_device_control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+        /* red */
+        for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i <LCD_DSI_BUF_SIZE/4/2+390; i++)
+        {
+                ptr[4 * i] = 0x00;
+                ptr[4 * i + 1] = 0x00;
+                ptr[4 * i + 2] = 0xFF;
+                ptr[4 * i + 3] = 0xFF;
+        }
+        rt_device_control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+
 
-	
 }
 MSH_CMD_EXPORT(line, line);
 
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
index f77fa05aee..416e6863a7 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
index 314b1d707f..dc24066f51 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
index 726be84e0d..0d3904444f 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -119,7 +119,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     {
         return RT_ERROR;
     }
-    
+
     if (point_num == 0)
     {
         if (s_tp_down)
@@ -131,7 +131,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
         msg->event = TOUCH_EVENT_NONE;
         return RT_ERROR;
     }
-    
+
     ret = ft_read(ft_i2c_bus, 0x03, point, 6);
     if (ret < 0)
     {
@@ -147,7 +147,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     }
     msg->event = TOUCH_EVENT_DOWN;
     s_tp_down = 1;
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
index 0e0cfae502..b70dd3eb25 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
index fbc56b4a44..4d602fc344 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
index a5d89f1d80..f02a735dc4 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
index d8f61de87e..85d9d3ba89 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,19 +15,19 @@
 /* defined the LD7 pin: PH7 */
 #define LED7_PIN    GET_PIN(H, 7)
 
-int main(void) 
+int main(void)
 {
     int count = 1;
     /* set LD7 pin mode to output */
     rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT);
-    
+
     while (count++)
     {
         rt_pin_write(LED7_PIN, PIN_HIGH);
-        rt_thread_mdelay(500);    
+        rt_thread_mdelay(500);
         rt_pin_write(LED7_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    
+
     return RT_EOK;
 }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.c b/bsp/stm32/stm32mp157a-st-discovery/board/board.c
index cb44c09515..92180ecaa8 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/board.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2006-2018, RT-Thread Development Team
+* Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -20,13 +20,13 @@ void SystemClock_Config(void)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-    
+
     /**Configure LSE Drive Capability
     */
     HAL_PWR_EnableBkUpAccess();
     __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
-    
-    /**Initializes the CPU, AHB and APB busses clocks 
+
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI
                               |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE
@@ -39,7 +39,7 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.LSIState = RCC_LSI_ON;
   RCC_OscInitStruct.CSIState = RCC_CSI_ON;
   RCC_OscInitStruct.CSICalibrationValue = 0x10; /* Default reset value */
-    
+
     /**PLL1 Config
     */
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -53,7 +53,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL2 Config
     */
     RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
@@ -67,7 +67,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL3 Config
     */
     RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
@@ -82,7 +82,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL4 Config
     */
     RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
@@ -97,7 +97,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
     RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
         Error_Handler();
@@ -119,12 +119,12 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
     RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
     RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     /**Set the HSE division factor for RTC clock
     */
     __HAL_RCC_RTC_HSEDIV(24);
@@ -137,7 +137,7 @@ void SystemClock_Config(void)
 */
 void PeriphCommonClock_Config(void) {
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     /** Initializes the common periph clock
     */
     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
@@ -149,11 +149,11 @@ void PeriphCommonClock_Config(void) {
 
 extern void rt_hw_systick_init(void);
 extern int rt_hw_usart_init(void);
-void rt_hw_board_init() 
+void rt_hw_board_init()
 {
     /* HAL_Init() function is called at the beginning of the program */
     HAL_Init();
-    
+
     /* enable interrupt */
     __set_PRIMASK(0);
     /* Configure the system clock */
@@ -163,29 +163,29 @@ void rt_hw_board_init()
     }
     /* disable interrupt */
     __set_PRIMASK(1);
-    
+
     rt_hw_systick_init();
-    
+
     /* Heap initialization */
 #if defined(RT_USING_HEAP)
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-     
+
     /* Pin driver initialization is open by default */
 #ifdef RT_USING_PIN
     rt_hw_pin_init();
 #endif
-    
+
     /* USART driver initialization is open by default */
 #ifdef RT_USING_SERIAL
     rt_hw_usart_init();
 #endif
-    
+
     /* Set the shell console output device */
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-    
+
     /* Board underlying hardware initialization */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.h b/bsp/stm32/stm32mp157a-st-discovery/board/board.h
index 2472d96400..0b60c68af4 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/board.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,12 +22,12 @@
 extern "C" {
 #endif
 
-#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)  
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)
 #define STM32_FLASH_SIZE             (192 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
-  
+
 #define STM32_SRAM_SIZE           (64)
-#define STM32_SRAM_END            (0x10030000 + 64 * 1024)  	
+#define STM32_SRAM_END            (0x10030000 + 64 * 1024)
 
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
index 315f6320d5..2e045b016b 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 #include <rtdevice.h>
 #include <dfs_posix.h>
 
-#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC)  
+#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC)
 #define BUFSZ   1024
 #define SOUND_DEVICE_NAME    "sound0"
 static rt_device_t snd_dev;
@@ -217,7 +217,7 @@ int wavrecord_sample(int argc, char **argv)
     caps.main_type               = AUDIO_TYPE_INPUT;
     caps.sub_type                = AUDIO_DSP_PARAM;
     caps.udata.config.samplerate = RECORD_SAMPLERATE;
-    caps.udata.config.channels   = RECORD_CHANNEL; 
+    caps.udata.config.channels   = RECORD_CHANNEL;
     caps.udata.config.samplebits = 16;
     rt_device_control(mic_dev, AUDIO_CTL_CONFIGURE, &caps);
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
index e0ae5f1b5e..47ac5b0de2 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@
 /* CS42L51 address */
 #define CHIP_ADDRESS 0x4A
 /* reset pin, active low */
-#define CS42L51_RESET_PIN   GET_PIN(G, 9) 
+#define CS42L51_RESET_PIN   GET_PIN(G, 9)
 
 static uint16_t CS42L51_Device             = OUT_HEADPHONE;
 static struct rt_i2c_bus_device *audio_dev = RT_NULL;
@@ -31,12 +31,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8
     struct rt_i2c_msg msg[2] = {0, 0};
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     msg[0].addr  = CHIP_ADDRESS;    /* Slave address */
     msg[0].flags = RT_I2C_WR;        /* Write flag */
     msg[0].buf   = &reg;             /* Slave register address */
     msg[0].len   = 1;                /* Number of bytes sent */
-        
+
     msg[1].addr  = CHIP_ADDRESS;
     msg[1].flags = RT_I2C_RD;
     msg[1].len   = len;
@@ -57,8 +57,8 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint
     struct rt_i2c_msg msgs;
 
     RT_ASSERT(bus != RT_NULL);
-    
-    buf[0] = reg; 
+
+    buf[0] = reg;
     buf[1] = data;
 
     msgs.addr  = CHIP_ADDRESS;
@@ -119,10 +119,10 @@ static void cs42l51_lowlevel_init(void)
     /* Power off the cs42l51 */
     rt_pin_write(CS42L51_RESET_PIN, PIN_LOW);
 
-    /* wait until power supplies are stable */    
+    /* wait until power supplies are stable */
     rt_thread_mdelay(10);
 
-    /* Power on the cs42l51 */    
+    /* Power on the cs42l51 */
     rt_pin_write(CS42L51_RESET_PIN, PIN_HIGH);
 
     /* Wait at least 500ns after reset */
@@ -150,12 +150,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
     static uint8_t init_flag  = 0;
     rt_uint8_t temp = 0;
     rt_uint8_t value = 0;
-    
+
     /* check if codec is already initialized */
     if (init_flag == 0)
     {
         audio_dev = rt_i2c_bus_device_find(bus_name);
-        
+
         if (audio_dev == RT_NULL)
         {
             LOG_E("%s bus not found\n", bus_name);
@@ -172,7 +172,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
         write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F);
         read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp);
         write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E));
-        
+
         init_flag = 1;
     }
     else
@@ -187,7 +187,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
 
         /* Power control : Enter standby (PDN = 1) */
         read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp);
-        write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); 
+        write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01));
     }
     /* Mic Power and Speed Control : Auto detect on, Speed mode SSM, tri state off, MCLK divide by 2 off */
     read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp);
@@ -204,9 +204,9 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
     write_reg(audio_dev, CS42L51_DAC_OUT_CTL, 0xC3);
     /* DAC control : Signal processing to DAC, Freeze off, De-emphasis off, Analog output auto mute off, DAC soft ramp */
     write_reg(audio_dev, CS42L51_DAC_CTL, 0x42);
-    /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */  
+    /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */
     write_reg(audio_dev, CS42L51_ALC_PGA_CTL, 0xC0);
-    /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */  
+    /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */
     write_reg(audio_dev, CS42L51_ALC_PGB_CTL, 0xC0);
     /* ADCA Attenuator : 0dB */
     write_reg(audio_dev, CS42L51_ADCA_ATT, 0x00);
@@ -229,12 +229,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
         /* AOUTA volume control : AOUTA volume */
         write_reg(audio_dev, CS42L51_AOUTA_VOL, value);
         /* AOUTB volume control : AOUTB volume */
-        write_reg(audio_dev, CS42L51_AOUTB_VOL, value); 
+        write_reg(audio_dev, CS42L51_AOUTB_VOL, value);
     }
-    
+
     CS42L51_Device = device;
-    
-    return RT_EOK;  
+
+    return RT_EOK;
 }
 
 /**
@@ -271,7 +271,7 @@ static void cs42l51_deinit(void)
 }
 
 /**
-  * @brief Verify that we have a CS42L51.   
+  * @brief Verify that we have a CS42L51.
   * @retval 0 if correct communication, else wrong communication
   */
 
@@ -283,20 +283,20 @@ static uint32_t cs42l51_read_id(void)
     read_reg(audio_dev, CS42L51_CHIP_REV_ID, 1, &temp);
 
     if ((temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
-        (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) 
+        (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B)))
     {
-      LOG_E("device id : 0x%02x", temp);  
-        return RT_ERROR;     
+      LOG_E("device id : 0x%02x", temp);
+        return RT_ERROR;
     }
-    
-    LOG_D("device id : 0x%02x", temp);  
-    
+
+    LOG_D("device id : 0x%02x", temp);
+
     return RT_EOK;
 }
 
 /**
   * @brief Start the audio Codec play feature.
-  * @note For this codec no Play options are required.  
+  * @note For this codec no Play options are required.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_play(void)
@@ -316,7 +316,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F));
         break;
         }
-        
+
     case IN_LINE1:
         {
         /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN1A to PGAA, ADCB invert off, ADCA invert off, ADCB mute off, ADCA mute off */
@@ -326,7 +326,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F));
         break;
         }
-        
+
     case IN_MIC1:
         {
         /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN3A to PreAmp to PGAA, ADCB invert off, ADCA invert off, ADCB mute on, ADCA mute off */
@@ -339,7 +339,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF9));
         break;
         }
-        
+
     case IN_MIC2:
         {
          /* Power control 1 : PDN_PGAB, PDN_ADCB disable. */
@@ -350,7 +350,7 @@ static uint32_t cs42l51_play(void)
          write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF5));
          break;
         }
-        
+
     default:
         LOG_D("error audio play mode!");
         break;
@@ -365,11 +365,11 @@ static uint32_t cs42l51_play(void)
 
 /**
   * @brief Pause playing on the audio codec.
-  * @param audio_dev: Device address on communication Bus. 
+  * @param audio_dev: Device address on communication Bus.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_pause(void)
-{  
+{
 
   /* Pause the audio file playing */
   /* Mute the output first */
@@ -379,7 +379,7 @@ static uint32_t cs42l51_pause(void)
 
 /**
   * @brief Resume playing on the audio codec.
-  * @param audio_dev: Device address on communication Bus. 
+  * @param audio_dev: Device address on communication Bus.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_resume(void)
@@ -423,7 +423,7 @@ static uint32_t cs42l51_set_frequency(uint32_t AudioFreq)
 }
 
 /**
-  * @brief Set higher or lower the codec volume level.  
+  * @brief Set higher or lower the codec volume level.
   * @param Volume: output volume level (from 0 (-100dB) to 100 (0dB)).
   * @retval 0 if correct communication, else wrong communication
   */
@@ -440,23 +440,23 @@ static uint32_t cs42l51_set_volume(uint8_t Volume)
 }
 
 /**
-  * @brief get higher or lower the codec volume level.  
+  * @brief get higher or lower the codec volume level.
   * @retval value if correct communication
   */
 static uint32_t cs42l51_get_volume(void)
 {
     rt_uint8_t temp = 0;
-    
+
     /* AOUTA volume control : AOUTA volume */
     read_reg(audio_dev, CS42L51_AOUTA_VOL, 1, &temp);
 
     temp = VOLUME_INVERT(temp);
-    
+
     return temp;
 }
 
 /**
-* @brief Enable or disable the mute feature on the audio codec.  
+* @brief Enable or disable the mute feature on the audio codec.
 * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
 *             mute mode.
 * @retval 0 if correct communication, else wrong communication
@@ -464,7 +464,7 @@ static uint32_t cs42l51_get_volume(void)
 static uint32_t cs42l51_set_mute(uint32_t cmd)
 {
     rt_uint8_t temp = 0;
-    
+
     /* Read DAC output control register */
     read_reg(audio_dev, 0x08, 1, &temp);
 
@@ -484,10 +484,10 @@ static uint32_t cs42l51_set_mute(uint32_t cmd)
 }
 
 /**
-  * @brief Switch dynamically (while audio file is played) the output target 
+  * @brief Switch dynamically (while audio file is played) the output target
   *         (speaker, headphone, etc).
   * @note This function is currently not used (only headphone output device).
-  * @param Output: specifies the audio output device target. 
+  * @param Output: specifies the audio output device target.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_set_output_mode(uint8_t Output)
@@ -496,7 +496,7 @@ static uint32_t cs42l51_set_output_mode(uint8_t Output)
 }
 
 /**
-  * @brief Reset CS42L51 registers. 
+  * @brief Reset CS42L51 registers.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_reset(void)
@@ -508,8 +508,8 @@ static uint32_t cs42l51_reset(void)
     return RT_EOK;
 }
 
-/* Audio codec driver structure initialization */  
-AUDIO_DrvTypeDef cs42l51_drv = 
+/* Audio codec driver structure initialization */
+AUDIO_DrvTypeDef cs42l51_drv =
 {
   cs42l51_init,
   cs42l51_deinit,
@@ -518,12 +518,12 @@ AUDIO_DrvTypeDef cs42l51_drv =
   cs42l51_play,
   cs42l51_pause,
   cs42l51_resume,
-  cs42l51_stop,  
-  
-  cs42l51_set_frequency,  
+  cs42l51_stop,
+
+  cs42l51_set_frequency,
   cs42l51_set_volume,
   cs42l51_get_volume,
-  cs42l51_set_mute,  
+  cs42l51_set_mute,
   cs42l51_set_output_mode,
   cs42l51_reset,
 };
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
index b3d7f78dca..4447418a24 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
@@ -13,7 +13,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-    
+
 typedef struct
 {
   rt_err_t  (*init)(uint16_t , const char *, uint8_t);
@@ -34,137 +34,137 @@ typedef struct
 extern AUDIO_DrvTypeDef cs42l51_drv;
 
 /* CS42L51 register space */
-#define CS42L51_CHIP_ID			            0x1B
-#define CS42L51_CHIP_REV_A		            0x00
-#define CS42L51_CHIP_REV_B		            0x01
+#define CS42L51_CHIP_ID                     0x1B
+#define CS42L51_CHIP_REV_A                  0x00
+#define CS42L51_CHIP_REV_B                  0x01
 
-#define CS42L51_CHIP_REV_ID		            0x01
-#define CS42L51_MK_CHIP_REV(a, b)	        ((a)<<3|(b))
+#define CS42L51_CHIP_REV_ID                 0x01
+#define CS42L51_MK_CHIP_REV(a, b)           ((a)<<3|(b))
 
-#define CS42L51_POWER_CTL1		            0x02
-#define CS42L51_POWER_CTL1_PDN_DACB	        (1<<6)
-#define CS42L51_POWER_CTL1_PDN_DACA	        (1<<5)
-#define CS42L51_POWER_CTL1_PDN_PGAB	        (1<<4)
-#define CS42L51_POWER_CTL1_PDN_PGAA	        (1<<3)
-#define CS42L51_POWER_CTL1_PDN_ADCB	        (1<<2)
-#define CS42L51_POWER_CTL1_PDN_ADCA	        (1<<1)
-#define CS42L51_POWER_CTL1_PDN		        (1<<0)
+#define CS42L51_POWER_CTL1                  0x02
+#define CS42L51_POWER_CTL1_PDN_DACB         (1<<6)
+#define CS42L51_POWER_CTL1_PDN_DACA         (1<<5)
+#define CS42L51_POWER_CTL1_PDN_PGAB         (1<<4)
+#define CS42L51_POWER_CTL1_PDN_PGAA         (1<<3)
+#define CS42L51_POWER_CTL1_PDN_ADCB         (1<<2)
+#define CS42L51_POWER_CTL1_PDN_ADCA         (1<<1)
+#define CS42L51_POWER_CTL1_PDN              (1<<0)
 
-#define CS42L51_MIC_POWER_CTL		        0x03
-#define CS42L51_MIC_POWER_CTL_AUTO	        (1<<7)
-#define CS42L51_MIC_POWER_CTL_SPEED(x)	    (((x)&3)<<5)
-#define CS42L51_QSM_MODE		            3
-#define CS42L51_HSM_MODE		            2
-#define	CS42L51_SSM_MODE		            1
-#define CS42L51_DSM_MODE		            0
-#define CS42L51_MIC_POWER_CTL_3ST_SP	    (1<<4)
-#define CS42L51_MIC_POWER_CTL_PDN_MICB	    (1<<3)
-#define CS42L51_MIC_POWER_CTL_PDN_MICA	    (1<<2)
-#define CS42L51_MIC_POWER_CTL_PDN_BIAS	    (1<<1)
-#define CS42L51_MIC_POWER_CTL_MCLK_DIV2	    (1<<0)
+#define CS42L51_MIC_POWER_CTL               0x03
+#define CS42L51_MIC_POWER_CTL_AUTO          (1<<7)
+#define CS42L51_MIC_POWER_CTL_SPEED(x)      (((x)&3)<<5)
+#define CS42L51_QSM_MODE                    3
+#define CS42L51_HSM_MODE                    2
+#define CS42L51_SSM_MODE                    1
+#define CS42L51_DSM_MODE                    0
+#define CS42L51_MIC_POWER_CTL_3ST_SP        (1<<4)
+#define CS42L51_MIC_POWER_CTL_PDN_MICB      (1<<3)
+#define CS42L51_MIC_POWER_CTL_PDN_MICA      (1<<2)
+#define CS42L51_MIC_POWER_CTL_PDN_BIAS      (1<<1)
+#define CS42L51_MIC_POWER_CTL_MCLK_DIV2     (1<<0)
 
-#define CS42L51_INTF_CTL		            0x04
-#define CS42L51_INTF_CTL_LOOPBACK	        (1<<7)
-#define CS42L51_INTF_CTL_MASTER		        (1<<6)
-#define CS42L51_INTF_CTL_DAC_FORMAT(x)	    (((x)&7)<<3)
-#define CS42L51_DAC_DIF_LJ24		        0x00
-#define CS42L51_DAC_DIF_I2S		            0x01
-#define CS42L51_DAC_DIF_RJ24		        0x02
-#define CS42L51_DAC_DIF_RJ20		        0x03
-#define CS42L51_DAC_DIF_RJ18		        0x04
-#define CS42L51_DAC_DIF_RJ16		        0x05
-#define CS42L51_INTF_CTL_ADC_I2S	        (1<<2)
-#define CS42L51_INTF_CTL_DIGMIX		        (1<<1)
-#define CS42L51_INTF_CTL_MICMIX		        (1<<0)
+#define CS42L51_INTF_CTL                    0x04
+#define CS42L51_INTF_CTL_LOOPBACK           (1<<7)
+#define CS42L51_INTF_CTL_MASTER             (1<<6)
+#define CS42L51_INTF_CTL_DAC_FORMAT(x)      (((x)&7)<<3)
+#define CS42L51_DAC_DIF_LJ24                0x00
+#define CS42L51_DAC_DIF_I2S                 0x01
+#define CS42L51_DAC_DIF_RJ24                0x02
+#define CS42L51_DAC_DIF_RJ20                0x03
+#define CS42L51_DAC_DIF_RJ18                0x04
+#define CS42L51_DAC_DIF_RJ16                0x05
+#define CS42L51_INTF_CTL_ADC_I2S            (1<<2)
+#define CS42L51_INTF_CTL_DIGMIX             (1<<1)
+#define CS42L51_INTF_CTL_MICMIX             (1<<0)
 
-#define CS42L51_MIC_CTL			            0x05
-#define CS42L51_MIC_CTL_ADC_SNGVOL	        (1<<7)
-#define CS42L51_MIC_CTL_ADCD_DBOOST	        (1<<6)
-#define CS42L51_MIC_CTL_ADCA_DBOOST	        (1<<5)
-#define CS42L51_MIC_CTL_MICBIAS_SEL	        (1<<4)
-#define CS42L51_MIC_CTL_MICBIAS_LVL(x)	    (((x)&3)<<2)
-#define CS42L51_MIC_CTL_MICB_BOOST	        (1<<1)
-#define CS42L51_MIC_CTL_MICA_BOOST	        (1<<0)
+#define CS42L51_MIC_CTL                     0x05
+#define CS42L51_MIC_CTL_ADC_SNGVOL          (1<<7)
+#define CS42L51_MIC_CTL_ADCD_DBOOST         (1<<6)
+#define CS42L51_MIC_CTL_ADCA_DBOOST         (1<<5)
+#define CS42L51_MIC_CTL_MICBIAS_SEL         (1<<4)
+#define CS42L51_MIC_CTL_MICBIAS_LVL(x)      (((x)&3)<<2)
+#define CS42L51_MIC_CTL_MICB_BOOST          (1<<1)
+#define CS42L51_MIC_CTL_MICA_BOOST          (1<<0)
 
-#define CS42L51_ADC_CTL			            0x06
-#define CS42L51_ADC_CTL_ADCB_HPFEN	        (1<<7)
-#define CS42L51_ADC_CTL_ADCB_HPFRZ	        (1<<6)
-#define CS42L51_ADC_CTL_ADCA_HPFEN	        (1<<5)
-#define CS42L51_ADC_CTL_ADCA_HPFRZ	        (1<<4)
-#define CS42L51_ADC_CTL_SOFTB		        (1<<3)
-#define CS42L51_ADC_CTL_ZCROSSB		        (1<<2)
-#define CS42L51_ADC_CTL_SOFTA		        (1<<1)
-#define CS42L51_ADC_CTL_ZCROSSA		        (1<<0)
+#define CS42L51_ADC_CTL                     0x06
+#define CS42L51_ADC_CTL_ADCB_HPFEN          (1<<7)
+#define CS42L51_ADC_CTL_ADCB_HPFRZ          (1<<6)
+#define CS42L51_ADC_CTL_ADCA_HPFEN          (1<<5)
+#define CS42L51_ADC_CTL_ADCA_HPFRZ          (1<<4)
+#define CS42L51_ADC_CTL_SOFTB               (1<<3)
+#define CS42L51_ADC_CTL_ZCROSSB             (1<<2)
+#define CS42L51_ADC_CTL_SOFTA               (1<<1)
+#define CS42L51_ADC_CTL_ZCROSSA             (1<<0)
 
-#define CS42L51_ADC_INPUT		            0x07
-#define CS42L51_ADC_INPUT_AINB_MUX(x)	    (((x)&3)<<6)
-#define CS42L51_ADC_INPUT_AINA_MUX(x)	    (((x)&3)<<4)
-#define CS42L51_ADC_INPUT_INV_ADCB	        (1<<3)
-#define CS42L51_ADC_INPUT_INV_ADCA	        (1<<2)
-#define CS42L51_ADC_INPUT_ADCB_MUTE	        (1<<1)
-#define CS42L51_ADC_INPUT_ADCA_MUTE	        (1<<0)
+#define CS42L51_ADC_INPUT                   0x07
+#define CS42L51_ADC_INPUT_AINB_MUX(x)       (((x)&3)<<6)
+#define CS42L51_ADC_INPUT_AINA_MUX(x)       (((x)&3)<<4)
+#define CS42L51_ADC_INPUT_INV_ADCB          (1<<3)
+#define CS42L51_ADC_INPUT_INV_ADCA          (1<<2)
+#define CS42L51_ADC_INPUT_ADCB_MUTE         (1<<1)
+#define CS42L51_ADC_INPUT_ADCA_MUTE         (1<<0)
 
-#define CS42L51_DAC_OUT_CTL		            0x08
-#define CS42L51_DAC_OUT_CTL_HP_GAIN(x)	    (((x)&7)<<5)
-#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL	    (1<<4)
-#define CS42L51_DAC_OUT_CTL_INV_PCMB	    (1<<3)
-#define CS42L51_DAC_OUT_CTL_INV_PCMA	    (1<<2)
-#define CS42L51_DAC_OUT_CTL_DACB_MUTE	    (1<<1)
-#define CS42L51_DAC_OUT_CTL_DACA_MUTE	    (1<<0)
+#define CS42L51_DAC_OUT_CTL                 0x08
+#define CS42L51_DAC_OUT_CTL_HP_GAIN(x)      (((x)&7)<<5)
+#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL      (1<<4)
+#define CS42L51_DAC_OUT_CTL_INV_PCMB        (1<<3)
+#define CS42L51_DAC_OUT_CTL_INV_PCMA        (1<<2)
+#define CS42L51_DAC_OUT_CTL_DACB_MUTE       (1<<1)
+#define CS42L51_DAC_OUT_CTL_DACA_MUTE       (1<<0)
 
-#define CS42L51_DAC_CTL			            0x09
-#define CS42L51_DAC_CTL_DATA_SEL(x)	        (((x)&3)<<6)
-#define CS42L51_DAC_CTL_FREEZE		        (1<<5)
-#define CS42L51_DAC_CTL_DEEMPH		        (1<<3)
-#define CS42L51_DAC_CTL_AMUTE		        (1<<2)
-#define CS42L51_DAC_CTL_DACSZ(x)	        (((x)&3)<<0)
+#define CS42L51_DAC_CTL                     0x09
+#define CS42L51_DAC_CTL_DATA_SEL(x)         (((x)&3)<<6)
+#define CS42L51_DAC_CTL_FREEZE              (1<<5)
+#define CS42L51_DAC_CTL_DEEMPH              (1<<3)
+#define CS42L51_DAC_CTL_AMUTE               (1<<2)
+#define CS42L51_DAC_CTL_DACSZ(x)            (((x)&3)<<0)
 
-#define CS42L51_ALC_PGA_CTL		            0x0A
-#define CS42L51_ALC_PGB_CTL		            0x0B
-#define CS42L51_ALC_PGX_ALCX_SRDIS	        (1<<7)
-#define CS42L51_ALC_PGX_ALCX_ZCDIS	        (1<<6)
-#define CS42L51_ALC_PGX_PGX_VOL(x)	        (((x)&0x1f)<<0)
+#define CS42L51_ALC_PGA_CTL                 0x0A
+#define CS42L51_ALC_PGB_CTL                 0x0B
+#define CS42L51_ALC_PGX_ALCX_SRDIS          (1<<7)
+#define CS42L51_ALC_PGX_ALCX_ZCDIS          (1<<6)
+#define CS42L51_ALC_PGX_PGX_VOL(x)          (((x)&0x1f)<<0)
 
-#define CS42L51_ADCA_ATT		            0x0C
-#define CS42L51_ADCB_ATT		            0x0D
+#define CS42L51_ADCA_ATT                    0x0C
+#define CS42L51_ADCB_ATT                    0x0D
 
-#define CS42L51_ADCA_VOL		            0x0E
-#define CS42L51_ADCB_VOL		            0x0F
-#define CS42L51_PCMA_VOL		            0x10
-#define CS42L51_PCMB_VOL		            0x11
-#define CS42L51_MIX_MUTE_ADCMIX		        (1<<7)
-#define CS42L51_MIX_VOLUME(x)		        (((x)&0x7f)<<0)
+#define CS42L51_ADCA_VOL                    0x0E
+#define CS42L51_ADCB_VOL                    0x0F
+#define CS42L51_PCMA_VOL                    0x10
+#define CS42L51_PCMB_VOL                    0x11
+#define CS42L51_MIX_MUTE_ADCMIX             (1<<7)
+#define CS42L51_MIX_VOLUME(x)               (((x)&0x7f)<<0)
 
-#define CS42L51_BEEP_FREQ		            0x12
-#define CS42L51_BEEP_VOL		            0x13
-#define CS42L51_BEEP_CONF		            0x14
+#define CS42L51_BEEP_FREQ                   0x12
+#define CS42L51_BEEP_VOL                    0x13
+#define CS42L51_BEEP_CONF                   0x14
 
-#define CS42L51_TONE_CTL		            0x15
-#define CS42L51_TONE_CTL_TREB(x)	        (((x)&0xf)<<4)
-#define CS42L51_TONE_CTL_BASS(x)	        (((x)&0xf)<<0)
+#define CS42L51_TONE_CTL                    0x15
+#define CS42L51_TONE_CTL_TREB(x)            (((x)&0xf)<<4)
+#define CS42L51_TONE_CTL_BASS(x)            (((x)&0xf)<<0)
 
-#define CS42L51_AOUTA_VOL		            0x16
-#define CS42L51_AOUTB_VOL		            0x17
-#define CS42L51_PCM_MIXER		            0x18
-#define CS42L51_LIMIT_THRES_DIS		        0x19
-#define CS42L51_LIMIT_REL		            0x1A
-#define CS42L51_LIMIT_ATT		            0x1B
-#define CS42L51_ALC_EN			            0x1C
-#define CS42L51_ALC_REL			            0x1D
-#define CS42L51_ALC_THRES		            0x1E
-#define CS42L51_NOISE_CONF		            0x1F
+#define CS42L51_AOUTA_VOL                   0x16
+#define CS42L51_AOUTB_VOL                   0x17
+#define CS42L51_PCM_MIXER                   0x18
+#define CS42L51_LIMIT_THRES_DIS             0x19
+#define CS42L51_LIMIT_REL                   0x1A
+#define CS42L51_LIMIT_ATT                   0x1B
+#define CS42L51_ALC_EN                      0x1C
+#define CS42L51_ALC_REL                     0x1D
+#define CS42L51_ALC_THRES                   0x1E
+#define CS42L51_NOISE_CONF                  0x1F
 
-#define CS42L51_STATUS			            0x20
-#define CS42L51_STATUS_SP_CLKERR	        (1<<6)
-#define CS42L51_STATUS_SPEA_OVFL	        (1<<5)
-#define CS42L51_STATUS_SPEB_OVFL	        (1<<4)
-#define CS42L51_STATUS_PCMA_OVFL	        (1<<3)
-#define CS42L51_STATUS_PCMB_OVFL	        (1<<2)
-#define CS42L51_STATUS_ADCA_OVFL	        (1<<1)
-#define CS42L51_STATUS_ADCB_OVFL	        (1<<0)
+#define CS42L51_STATUS                      0x20
+#define CS42L51_STATUS_SP_CLKERR            (1<<6)
+#define CS42L51_STATUS_SPEA_OVFL            (1<<5)
+#define CS42L51_STATUS_SPEB_OVFL            (1<<4)
+#define CS42L51_STATUS_PCMA_OVFL            (1<<3)
+#define CS42L51_STATUS_PCMB_OVFL            (1<<2)
+#define CS42L51_STATUS_ADCA_OVFL            (1<<1)
+#define CS42L51_STATUS_ADCB_OVFL            (1<<0)
 
-#define CS42L51_CHARGE_FREQ		            0x21
-#define CS42L51_FIRSTREG	                0x01
+#define CS42L51_CHARGE_FREQ                 0x21
+#define CS42L51_FIRSTREG                    0x01
 
 enum play_type {
     NONE,
@@ -181,12 +181,12 @@ enum play_type {
  * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
  * 32 regs
  */
-#define CS42L51_LASTREG		                0x20
-#define CS42L51_NUMREGS		                (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
+#define CS42L51_LASTREG                     0x20
+#define CS42L51_NUMREGS                     (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
 
 #define VOLUME_CONVERT(Volume)              ((Volume >= 100) ? 0 : ((uint8_t)(((Volume * 2) + 56))))
 #define VOLUME_INVERT(Volume)               (((Volume) == 0U) ? 100U : ((uint8_t)(((Volume) - 56U) / 2U)))
-     
+
 /* MUTE commands */
 #define AUDIO_MUTE_ON                       1
 #define AUDIO_MUTE_OFF                      0
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
index 20e98d4826..45b0afe762 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -79,21 +79,21 @@ void SAIB_Init(void)
     hsai_BlockB2.FrameInit.FSDefinition      = SAI_FS_CHANNEL_IDENTIFICATION;
     hsai_BlockB2.FrameInit.FSPolarity        = SAI_FS_ACTIVE_LOW;
     hsai_BlockB2.FrameInit.FSOffset          = SAI_FS_BEFOREFIRSTBIT;
-    
+
     hsai_BlockB2.SlotInit.FirstBitOffset     = 0;
     hsai_BlockB2.SlotInit.SlotSize           = SAI_SLOTSIZE_32B;
     hsai_BlockB2.SlotInit.SlotNumber         = 2;
     hsai_BlockB2.SlotInit.SlotActive         = SAI_SLOTACTIVE_0|SAI_SLOTACTIVE_1;
-    
+
     /* DeInit SAI PDM input */
     HAL_SAI_DeInit(&hsai_BlockB2);
-    
+
     /* Init SAI PDM input */
     if(HAL_OK != HAL_SAI_Init(&hsai_BlockB2))
     {
         Error_Handler();
     }
-    
+
     /* Enable SAI to generate clock used by audio driver */
     __HAL_SAI_ENABLE(&hsai_BlockB2);
 }
@@ -299,7 +299,7 @@ static rt_err_t mic_init(struct rt_audio_device *audio)
 {
     struct mic_device *mic_dev;
     RT_ASSERT(audio != RT_NULL);
-    
+
     mic_dev = (struct mic_device *)audio->parent.user_data;
     SAIB_Init();
     /* set default params */
@@ -312,7 +312,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream)
 {
     struct mic_device *mic_dev;
     RT_ASSERT(audio != RT_NULL);
-    
+
     mic_dev = (struct mic_device *)audio->parent.user_data;
     if (stream == AUDIO_STREAM_RECORD)
     {
@@ -324,7 +324,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream)
         }
         /* supply clk */
         HAL_SAI_Transmit(&hsai_BlockA2, (uint8_t *)&zero_frame[0], 2, 0);
-        
+
         cs42l51_drv.play();
     }
 
@@ -358,7 +358,7 @@ int rt_hw_mic_init(void)
 {
     rt_err_t result = RT_EOK;
     struct rt_device *device;
-    
+
     rt_memset(MIC_RX_FIFO, 0, RX_FIFO_SIZE);
     mic_dev.rx_fifo = MIC_RX_FIFO;
 
@@ -373,15 +373,15 @@ int rt_hw_mic_init(void)
     /* register sound device */
     mic_dev.audio.ops = &mic_ops;
     result = rt_audio_register(&mic_dev.audio, "mic0", RT_DEVICE_FLAG_RDONLY, &mic_dev);
-    
+
     if (result != RT_EOK)
     {
-        device = &(mic_dev.audio.parent); 
+        device = &(mic_dev.audio.parent);
         rt_device_unregister(device);
         LOG_E("mic device init error!");
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
index 5d94bfc399..6a057fa72f 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         /* Peripheral clock enable */
         if(IS_ENGINEERING_BOOT_MODE())
         {
-            /** Initializes the peripherals clock 
+            /** Initializes the peripherals clock
             */
             PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
             PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
@@ -72,7 +72,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         __HAL_RCC_GPIOF_CLK_ENABLE();
         __HAL_RCC_SAI2_CLK_ENABLE();
 
-        /**SAI2_A_Block_A GPIO Configuration    
+        /**SAI2_A_Block_A GPIO Configuration
         PE0     ------> SAI2_MCLK_A
         PI7     ------> SAI2_FS_A
         PI5     ------> SAI2_SCK_A
@@ -106,7 +106,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         hdma_sai2_a.Init.Mode                = DMA_CIRCULAR;
         hdma_sai2_a.Init.Priority            = DMA_PRIORITY_HIGH;
         hdma_sai2_a.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
-        
+
         HAL_DMA_DeInit(&hdma_sai2_a);
         if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK)
         {
@@ -117,13 +117,13 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0);
         HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
     }
-    
+
     if(hsai->Instance==SAI2_Block_B)
     {
           /* Peripheral clock enable */
         if(IS_ENGINEERING_BOOT_MODE())
         {
-            /** Initializes the peripherals clock 
+            /** Initializes the peripherals clock
             */
             PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
             PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
@@ -135,9 +135,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         }
         __HAL_RCC_GPIOF_CLK_ENABLE();
         __HAL_RCC_SAI2_CLK_ENABLE();
-                
-        /**SAI2_B_Block_B GPIO Configuration    
-        PF11     ------> SAI2_SD_B 
+
+        /**SAI2_B_Block_B GPIO Configuration
+        PF11     ------> SAI2_SD_B
         */
         GPIO_InitStruct.Pin = GPIO_PIN_11;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -148,7 +148,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
 
         __HAL_RCC_DMAMUX_CLK_ENABLE();
         __HAL_RCC_DMA2_CLK_ENABLE();
-        
+
         /* Peripheral DMA init*/
         hdma_sai2_b.Instance                 = DMA2_Stream4;
         hdma_sai2_b.Init.Request             = DMA_REQUEST_SAI2_B;
@@ -163,7 +163,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         hdma_sai2_b.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
         hdma_sai2_b.Init.MemBurst            = DMA_MBURST_SINGLE;
         hdma_sai2_b.Init.PeriphBurst         = DMA_PBURST_SINGLE;
-		__HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
+        __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
         HAL_DMA_DeInit(&hdma_sai2_b);
         if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK)
         {
@@ -172,7 +172,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
         __HAL_DMA_ENABLE(&hdma_sai2_b);
         HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 2, 0);
-        HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); 
+        HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);
     }
 }
 
@@ -182,14 +182,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
     if(hsai->Instance==SAI2_Block_A)
     {
 
-        /* Peripheral clock disable */ 
+        /* Peripheral clock disable */
         __HAL_RCC_SAI2_CLK_DISABLE();
 
-        /**SAI2_A_Block_A GPIO Configuration    
+        /**SAI2_A_Block_A GPIO Configuration
         PE0     ------> SAI2_MCLK_A
         PI7     ------> SAI2_FS_A
         PI5     ------> SAI2_SCK_A
-        PI6     ------> SAI2_SD_A 
+        PI6     ------> SAI2_SD_A
         */
         HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0);
 
@@ -198,14 +198,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
         HAL_DMA_DeInit(hsai->hdmarx);
         HAL_DMA_DeInit(hsai->hdmatx);
     }
-    
+
     if(hsai->Instance==SAI2_Block_B)
     {
         /* Peripheral clock disable */
         __HAL_RCC_SAI2_CLK_DISABLE();
 
-        /**SAI2_B_Block_B GPIO Configuration    
-        PF11     ------> SAI2_SD_B 
+        /**SAI2_B_Block_B GPIO Configuration
+        PF11     ------> SAI2_SD_B
         */
         HAL_GPIO_DeInit(GPIOF, GPIO_PIN_11);
 
@@ -241,12 +241,12 @@ static void rt_hw_sai2a_init(void)
     hsai_BlockA2.FrameInit.FSDefinition      = SAI_FS_CHANNEL_IDENTIFICATION;
     hsai_BlockA2.FrameInit.FSPolarity        = SAI_FS_ACTIVE_LOW;
     hsai_BlockA2.FrameInit.FSOffset          = SAI_FS_BEFOREFIRSTBIT;
-    
+
     hsai_BlockA2.SlotInit.FirstBitOffset     = 0;
     hsai_BlockA2.SlotInit.SlotSize           = SAI_SLOTSIZE_32B;
     hsai_BlockA2.SlotInit.SlotNumber         = 2;
     hsai_BlockA2.SlotInit.SlotActive         = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1;
-    
+
     if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2))
     {
         Error_Handler();
@@ -383,7 +383,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap
 
     return result;
 }
-    
+
 static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
 {
     rt_err_t result = RT_EOK;
@@ -403,9 +403,9 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c
             rt_uint8_t volume = caps->udata.value;
 
             cs42l51_drv.set_volume(volume);
-            
+
             snd_dev->volume = volume;
-            
+
             LOG_D("set volume %d", volume);
             break;
         }
@@ -483,16 +483,16 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
     RT_ASSERT(audio != RT_NULL);
     snd_dev = (struct sound_device *)audio->parent.user_data;
 
-    cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40); 
-    
+    cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40);
+
     if (cs42l51_drv.read_id() != RT_EOK)
     {
         LOG_E("can't find low level audio device!");
         return RT_ERROR;
     }
-    
+
     rt_hw_sai2a_init();
-    
+
     /* set default params */
     SAIA_Frequency_Set(snd_dev->replay_config.samplerate);
     SAIA_Channels_Set(snd_dev->replay_config.channels);
@@ -510,10 +510,10 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
     if (stream == AUDIO_STREAM_REPLAY)
     {
         LOG_D("open sound device");
-        
+
         cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 60); /* set work mode */
         cs42l51_drv.play();
-        
+
         if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK)
         {
             return RT_ERROR;
@@ -589,12 +589,12 @@ int rt_hw_sound_init(void)
     result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
     if (result != RT_EOK)
     {
-        device = &(snd_dev.audio.parent); 
+        device = &(snd_dev.audio.parent);
         rt_device_unregister(device);
         LOG_E("sound device init error!");
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
index e3eb609559..439e6352cc 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -77,7 +77,7 @@ static void hw_crc_sample(uint8_t *temp, int size)
 {
     struct rt_hwcrypto_ctx *ctx;
     rt_uint32_t result = 0;
-    
+
     struct hwcrypto_crc_cfg cfg =
     {
         .last_val = 0xFFFFFFFF,
@@ -92,9 +92,9 @@ static void hw_crc_sample(uint8_t *temp, int size)
 
     result = rt_hwcrypto_crc_update(ctx, temp, size);
 
-    rt_kprintf("crc result: %x \n", result);                
+    rt_kprintf("crc result: %x \n", result);
 
-    rt_hwcrypto_crc_destroy(ctx);  
+    rt_hwcrypto_crc_destroy(ctx);
 }
 #endif
 
@@ -103,19 +103,19 @@ static void hw_hash_sample()
 {
     struct rt_hwcrypto_ctx *ctx = RT_NULL;
     const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).";
-    
+
     static uint8_t sha1_output[20];
-    static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, 
+    static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad,
                                     0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5,
                                     0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec};
-    
+
     static uint8_t md5_output[16];
-    static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, 
+    static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9,
                                    0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3,
                                    0xac, 0x8b};
-    
+
     static uint8_t sha224_output[28];
-    static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, 
+    static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6,
                                         0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91,
                                         0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3,
                                         0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42,
@@ -130,7 +130,7 @@ static void hw_hash_sample()
     rt_kprintf("======================== Hash Test start ========================\n");
     rt_kprintf("Hash Test string: \n");
     dump_hex(hash_input, sizeof(hash_input));
-    
+
     /* sh1 test*/
     rt_kprintf("\n============ SHA1 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1);
@@ -147,7 +147,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get sha1 result */
     rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output));
-    
+
     rt_kprintf("Actual sha1 result:\n");
     dump_hex(sha1_output, sizeof(sha1_output));
 
@@ -162,7 +162,7 @@ static void hw_hash_sample()
     /* deinit hash*/
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ SHA1 Test Over ============\n");
-      
+
     /* md5 test*/
     rt_kprintf("\n============ MD5 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5);
@@ -179,7 +179,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get md5 result */
     rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output));
-    
+
     rt_kprintf("Actual md5 result:\n");
     dump_hex(md5_output, sizeof(md5_output));
 
@@ -194,7 +194,7 @@ static void hw_hash_sample()
     /* deinit hash*/
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ MD5 Test Over ============\n");
-    
+
     /* sha224 test */
     rt_kprintf("\n============ SHA224 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224);
@@ -211,7 +211,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get sha224 result */
     rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output));
-    
+
     rt_kprintf("Actual sha224 result:\n");
     dump_hex(sha224_output, sizeof(sha224_output));
 
@@ -234,7 +234,7 @@ static void hw_hash_sample()
         rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256);
         return ;
     }
-    
+
     rt_kprintf("Create sha256 type success!\n");
     rt_kprintf("Except sha256 result:\n");
     dump_hex(sha256_except, sizeof(sha256_except));
@@ -246,7 +246,7 @@ static void hw_hash_sample()
 
     rt_kprintf("Actual sha256 result\n");
     dump_hex(sha256_output, sizeof(sha256_output));
-    
+
     if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0)
     {
         rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n");
@@ -258,7 +258,7 @@ static void hw_hash_sample()
     /* destory */
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ SHA256 Test Over ============\n");
-    rt_kprintf("======================== Hash Test over! ========================\n");    
+    rt_kprintf("======================== Hash Test over! ========================\n");
 }
 #endif
 
@@ -286,29 +286,29 @@ static void hw_cryp_sample()
     rt_uint8_t buf_in[32];
     rt_uint8_t buf_out[32];
     int i;
-    
+
     /* Populating test data */
     for (i = 0; i < sizeof(buf_in); i++)
     {
         buf_in[i] = i;
     }
-    
+
     /* dump primitive data */
     rt_kprintf("key : \n");
     dump_hex(cryp_key, sizeof(cryp_key));
     rt_kprintf("primitive data : \n");
     dump_hex(buf_in, sizeof(buf_in));
-    
+
     rt_memset(buf_out, 0, sizeof(buf_out));
-    
+
     /* encrypt */
     hw_aes_cbc(buf_in, buf_out, HWCRYPTO_MODE_ENCRYPT);
     /* dump encrypt data */
     rt_kprintf("AES-enc : \n");
     dump_hex(buf_out, sizeof(buf_out));
-  
+
     rt_memset(buf_in, 0, sizeof(buf_in));
-    
+
     /* decrypt */
     hw_aes_cbc(buf_out, buf_in, HWCRYPTO_MODE_DECRYPT);
 
@@ -323,7 +323,7 @@ static int crypto(int argc, char **argv)
     int result = RT_EOK;
     static rt_device_t device = RT_NULL;
     char *result_str;
-    
+
     if (argc > 1)
     {
         if (!strcmp(argv[1], "probe"))
@@ -362,7 +362,7 @@ static int crypto(int argc, char **argv)
                 {
                     rt_kprintf("rng <number>        - generate <number> digital\n");
                 }
-                
+
 #else
                 rt_kprintf("please enable RNG first!\n");
 #endif
@@ -370,7 +370,7 @@ static int crypto(int argc, char **argv)
             else if (!strcmp(argv[1], "crc"))
             {
 #if defined (BSP_USING_CRC)
-                int size = 0, i = 0; 
+                int size = 0, i = 0;
                 if (argc > 3)
                 {
                     size = argc - 2;
@@ -381,7 +381,7 @@ static int crypto(int argc, char **argv)
                         {
                             data[i] = strtol(argv[2 + i], NULL, 0);
                         }
-                        hw_crc_sample(data, size);  
+                        hw_crc_sample(data, size);
                         rt_free(data);
                     }
                     else
@@ -402,31 +402,31 @@ static int crypto(int argc, char **argv)
 #if defined (BSP_USING_HASH)
                 if (argc == 3)
                 {
-                    hw_hash_sample(); 
+                    hw_hash_sample();
                 }
                 else
                 {
-                    rt_kprintf("crypto hash sample          - hash use sample\n");    
+                    rt_kprintf("crypto hash sample          - hash use sample\n");
                 }
 #else
-         rt_kprintf("please enable CRC first!\n");       
-#endif    
+         rt_kprintf("please enable CRC first!\n");
+#endif
             }
             else if (!strcmp(argv[1], "cryp"))
             {
 #if defined (BSP_USING_CRYP)
                 if (argc == 3)
                 {
-                    hw_cryp_sample(); 
+                    hw_cryp_sample();
                 }
                 else
                 {
-                    rt_kprintf("crypto cryp sample          - encrypt and decrypt data sample\n");    
+                    rt_kprintf("crypto cryp sample          - encrypt and decrypt data sample\n");
                 }
 #else
-         rt_kprintf("please enable CRYP first!\n");       
-#endif    
-            }            
+         rt_kprintf("please enable CRYP first!\n");
+#endif
+            }
             else
             {
                 rt_kprintf("Unknown command. Please enter 'crypto' for help\n");
@@ -443,7 +443,7 @@ static int crypto(int argc, char **argv)
         rt_kprintf("crypto cryp sample                          - encrypt and decrypt data\n");
         result = -RT_ERROR;
     }
-    
+
     return result;
 }
 MSH_CMD_EXPORT(crypto, crypto function);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
index b2fbc3561b..229c3e585e 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -156,7 +156,7 @@ static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_v
             return -RT_ETIMEOUT;
         }
     }
-    
+
     return RT_EOK;
 }
 
@@ -165,7 +165,7 @@ static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
     uint16_t reg_value = 0;
     uint32_t status = 0;
     volatile uint32_t tickstart = 0;
-    
+
     /* Take care not to alter MDC clock configuration */
     status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
     /* Set up a read operation */
@@ -238,10 +238,10 @@ static void HAL_ETH_MspInit(void)
 {
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     if(IS_ENGINEERING_BOOT_MODE())
     {
-        /** Initializes the peripherals clock 
+        /** Initializes the peripherals clock
         */
         PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH;
         PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4;
@@ -250,10 +250,10 @@ static void HAL_ETH_MspInit(void)
             Error_Handler();
         }
     }
-  
+
     /* Enable SYSCFG clock */
     __HAL_RCC_SYSCFG_CLK_ENABLE();
-    
+
     /* Enable GPIO clocks */
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
@@ -263,12 +263,12 @@ static void HAL_ETH_MspInit(void)
 
     /* Select RGMII interface mode */
     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII);
-    
+
     /* Enable Ethernet MAC clock */
     __HAL_RCC_ETH1MAC_CLK_ENABLE();
     __HAL_RCC_ETH1TX_CLK_ENABLE();
     __HAL_RCC_ETH1RX_CLK_ENABLE();
-    
+
     /**ETH1 GPIO Configuration
     PA1     ------>  ETH1_RX_CLK
     PA7     ------>  ETH1_RX_CTL
@@ -303,12 +303,12 @@ static void HAL_ETH_MspInit(void)
     HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
     GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14;
-    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
     /* ETH interrupt Init */
     HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00);
     HAL_NVIC_EnableIRQ(ETH1_IRQn);
-    
+
     /* Configure PHY_RST (PG0) */
     GPIO_InitStruct.Pin = GPIO_PIN_0;
     GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -326,11 +326,11 @@ static void HAL_ETH_MspInit(void)
 static rt_err_t rt_stm32_eth_init(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     rt_uint32_t status, i;
     volatile rt_uint32_t tickstart = 0;
     rt_uint8_t  *macAddr = &stm32_eth_device.dev_addr[0];
-    
+
     /* Initialize TX descriptor index */
     txIndex = 0;
     /* Initialize RX descriptor index */
@@ -372,30 +372,30 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     ETH->MACA2HR = 0;
     ETH->MACA3LR = 0;
     ETH->MACA3HR = 0;
-    
+
     /* Initialize hash table */
     ETH->MACHT0R = 0;
     ETH->MACHT1R = 0;
-    
+
     /* Configure the receive filter */
     ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
-    
+
     /* Disable flow control */
     ETH->MACQ0TXFCR = 0;
     ETH->MACRXFCR   = 0;
-    
+
     /* Enable the first RX queue */
     ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1);
-    
+
     /* Configure DMA operating mode */
     ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0);
-    
+
     /* Configure system bus mode */
     ETH->DMASBMR |= ETH_DMASBMR_AAL;
-    
+
     /* The DMA takes the descriptor table as contiguous */
     ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0);
-    
+
     /* Configure TX features */
     ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1);
 
@@ -427,12 +427,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         rxDmaDesc[i].rdes2 = 0;
         rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
     }
-    
+
     /* Set Transmit Descriptor List Address Register */
     ETH->DMAC0TXDLAR = (uint32_t) &txDmaDesc[0];
     /* Length of the transmit descriptor ring */
     ETH->DMAC0TXRLR = ETH_TXBUFNB - 1;
-    
+
     /* Set Receive Descriptor List Address Register */
     ETH->DMAC0RXDLAR = (uint32_t) &rxDmaDesc[0];
     /* Length of the receive descriptor ring */
@@ -441,24 +441,24 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     /* Prevent interrupts from being generated when the transmit statistic
      * counters reach half their maximum value */
     ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
-    
+
     /* Prevent interrupts from being generated when the receive statistic
      * counters reach half their maximum value */
     ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
-   
+
     /* Disable MAC interrupts */
     ETH->MACIER = 0;
-    
+
     /* Enable the desired DMA interrupts */
     ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
-    
+
     /* Enable MAC transmission and reception */
     ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
-   
+
     /* Enable DMA transmission and reception */
     ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
     ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
-   
+
     /* Reset PHY transceiver */
     phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR, RTL8211F_BMCR_RESET);
     status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
@@ -474,9 +474,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         else
         {
             status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
-        } 
+        }
     }
-    
+
     /* The PHY will generate interrupts when link status changes are detected */
     phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_INER, RTL8211F_INER_AN_COMPLETE | RTL8211F_INER_LINK_STATUS);
 
@@ -515,11 +515,11 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
     {
     case NIOCTL_GADDR:
         /* get mac address */
-        if (args) 
+        if (args)
         {
             rt_memcpy(args, stm32_eth_device.dev_addr, 6);
         }
-        else 
+        else
         {
             return -RT_ERROR;
         }
@@ -536,7 +536,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
 {
     uint32_t framelen = 0;
     struct pbuf *q = RT_NULL;
-    
+
     /* Copy user data to the transmit buffer */
     for (q = p; q != NULL; q = q->next)
     {
@@ -546,12 +546,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             LOG_D("buffer not valid");
             return ERR_USE;
         }
-        
+
         level = rt_hw_interrupt_disable();
         rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len);
         framelen += q->len;
         rt_hw_interrupt_enable(level);
-        
+
         /* Check the frame length */
         if (framelen > ETH_TX_BUF_SIZE - 1)
         {
@@ -559,7 +559,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             return ERR_USE;
         }
     }
-    
+
 #ifdef ETH_TX_DUMP
         rt_kprintf("Tx dump, len= %d\r\n", framelen);
         dump_hex(txBuffer[txIndex], framelen);
@@ -579,7 +579,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
     ETH->DMAC0SR = ETH_DMAC0SR_TBU;
     /* Instruct the DMA to poll the transmit descriptor list */
     ETH->DMAC0TXDTPR = 0;
-    
+
     if (++txIndex > ETH_TXBUFNB - 1)
     {
         txIndex = 0;
@@ -595,7 +595,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
     struct pbuf *p = RT_NULL, *q = RT_NULL;
 
     /* The current buffer is available for reading */
-    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) 
+    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN))
     {
         /* FD and LD flags should be set */
         if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD))
@@ -617,7 +617,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                             rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len);
                             framelen += q->len;
                             rt_hw_interrupt_enable(level);
-                            
+
                             if (framelen > framelength)
                             {
                                 LOG_E("frame len is too long!");
@@ -632,7 +632,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                     LOG_D("the received packet contains an error!");
                     return RT_NULL;
                 }
-                
+
             }
         else
         {
@@ -645,7 +645,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex];
         /* Give the ownership of the descriptor back to the DMA */
         rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
-        
+
 #ifdef ETH_RX_DUMP
         rt_kprintf("Rx dump, len= %d\r\n", framelen);
         dump_hex(rxBuffer[rxIndex], framelen);
@@ -660,14 +660,14 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         /* Instruct the DMA to poll the receive descriptor list */
         ETH->DMAC0RXDTPR = 0;
     }
-    
+
     return p;
 }
 
 void ETH1_IRQHandler(void)
 {
     rt_uint32_t status = 0;
-    
+
     /* enter interrupt */
     rt_interrupt_enter();
     /* Read DMA status register */
@@ -683,7 +683,7 @@ void ETH1_IRQHandler(void)
     {
         /* Disable RIE interrupt */
         ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE;
-        
+
         rt_event_send(&rx_event, status);
     }
     /* ETH DMA Error */
@@ -694,7 +694,7 @@ void ETH1_IRQHandler(void)
     }
     /* Clear the interrupt flags */
     ETH->DMAC0SR = ETH_DMAC0SR_NIS;
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 
@@ -704,19 +704,19 @@ static void phy_linkchange()
 {
     rt_uint32_t status = 0;
 
-	/* Read status register to acknowledge the interrupt */
+    /* Read status register to acknowledge the interrupt */
     status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_INSR);
-	
+
 
     if (status & (RTL8211F_BMSR_LINK_STATUS | RTL8211F_INSR_AN_COMPLETE))
     {
-	    status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
-    	status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+        status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+        status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
         if (status & RTL8211F_BMSR_LINK_STATUS)
         {
-            LOG_D("link up");  
+            LOG_D("link up");
 
-			status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR);
+            status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR);
             switch (status & RTL8211F_PHYSR_SPEED)
             {
             case RTL8211F_PHYSR_SPEED_10MBPS:
@@ -725,25 +725,25 @@ static void phy_linkchange()
                 stm32_eth_device.eth_speed |= PHY_10M;
               }
             break;
-            
+
             case RTL8211F_PHYSR_SPEED_100MBPS:
               {
                 LOG_D("speed: 100M");
                 stm32_eth_device.eth_speed |= PHY_100M;
               }
             break;
-            
+
             case RTL8211F_PHYSR_SPEED_1000MBPS:
               {
                 LOG_D("speed: 1000M");
                 stm32_eth_device.eth_speed |= PHY_1000M;
               }
             break;
-            
+
             /* Unknown speed */
             default:
                 rt_kprintf("Invalid speed.");
-            break;    
+            break;
             }
 
             stm32_eth_device.eth_mode = (status & RTL8211F_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX ;
@@ -812,9 +812,9 @@ static void phy_monitor_thread_entry(void *parameter)
                     eth_device_ready(&(stm32_eth_device.parent));
                 }
             }
-            
+
             /* enable DMA interrupts */
-            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; 
+            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
         }
     }
 }
@@ -823,7 +823,7 @@ static void phy_monitor_thread_entry(void *parameter)
 static int rt_hw_stm32_eth_init(void)
 {
     rt_err_t state = RT_EOK;
-    
+
     /* OUI 00-80-E1 STMICROELECTRONICS. */
     stm32_eth_device.dev_addr[0] = 0x00;
     stm32_eth_device.dev_addr[1] = 0x80;
@@ -845,7 +845,7 @@ static int rt_hw_stm32_eth_init(void)
     stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
 
     rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO);
-    
+
     /* register eth device */
     state = eth_device_init(&(stm32_eth_device.parent), "e0");
     if (RT_EOK == state)
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
index 40d7db8353..a85651be72 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
index d3d118fd9f..caaf002aa9 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ static int exti_sample(void)
     rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP);
     rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL);
     rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE);
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(exti_sample);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
index 82f66e9916..0e479b6ae6 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@ void LPTIM1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_LPTIM_IRQHandler(&hlptim1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -41,9 +41,9 @@ void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
     {
         HAL_GPIO_TogglePin(GPIOH, GPIO_PIN_7);
     }
-    
+
     /* All level of ITs can interrupt */
-    __set_BASEPRI(0U); 
+    __set_BASEPRI(0U);
 
     lptim_stop();
     rt_kprintf("system returns to normal!\n");
@@ -53,12 +53,12 @@ static int lptim_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hlptim1.Instance->CFGR &= ~(7 << 9);      /* clear PRESC[2:0] */
     hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0]  */
     rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value);
-    
+
     return RT_EOK;
 }
 
@@ -70,9 +70,9 @@ int lptim_start(void)
         LOG_D("lptim1 start counting failed!\n");
         return -RT_ERROR;
     }
-    
+
     LOG_D("lptim1 start counting success!\n");
-        
+
     return RT_EOK;
 }
 
@@ -83,16 +83,16 @@ int lptim_stop(void)
         LOG_D("lptim1 stop failed!\n");
         return -RT_ERROR;
    }
-   
-   LOG_D("lptim1 stop counting success!\n"); 
-   
+
+   LOG_D("lptim1 stop counting success!\n");
+
    return RT_EOK;
 }
 
 int lptim_init(void)
 {
     rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT);
-        
+
     hlptim1.Instance = LPTIM1;
     hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
     hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8;
@@ -110,7 +110,7 @@ int lptim_init(void)
         return -RT_ERROR;
     }
     LOG_D("lptim init success!\n");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(lptim_init);
@@ -120,7 +120,7 @@ static int lptim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "start"))
-        { 
+        {
            lptim_start();
            return RT_EOK;
         }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
index c5f26596cc..2915d7dcb2 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,12 +29,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8
     struct rt_i2c_msg msg[2] = {0, 0};
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     msg[0].addr  = STPMU1_I2C_ADDRESS;     /* Slave address */
     msg[0].flags = RT_I2C_WR;              /* Write flag */
     msg[0].buf   = &reg;                   /* Slave register address */
     msg[0].len   = 1;                      /* Number of bytes sent */
-        
+
     msg[1].addr  = STPMU1_I2C_ADDRESS;
     msg[1].flags = RT_I2C_RD;
     msg[1].len   = len;
@@ -55,7 +55,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint
     struct rt_i2c_msg msgs;
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     buf[0] = reg; //cmd
     buf[1] = data;
 
@@ -85,7 +85,7 @@ static rt_err_t stpmu1_read_reg(uint8_t register_id)
     {
         Error_Handler();
     }
-    
+
     return result;
 }
 
@@ -93,7 +93,7 @@ static void stpmu1_write_reg(uint8_t register_id, uint8_t value)
 {
     uint32_t status = RT_EOK;
     uint8_t readval = 0;
-    
+
     status = write_reg(pmic_dev, register_id, (rt_uint8_t)value);
 
     /* Check the communication status */
@@ -120,7 +120,7 @@ static uint32_t BSP_PMIC_MspInit(void)
     __HAL_RCC_GPIOA_CLK_ENABLE();
     GPIO_InitStruct.Pin       = GPIO_PIN_0;
     GPIO_InitStruct.Mode      = GPIO_MODE_IT_FALLING;
-    GPIO_InitStruct.Pull      = GPIO_PULLUP; 
+    GPIO_InitStruct.Pull      = GPIO_PULLUP;
     GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
     GPIO_InitStruct.Alternate = 0 ;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -619,7 +619,7 @@ static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t miliv
     uint8_t i;
     for ( i = 0 ; i < regul->voltage_table_size ; i++)
     {
-        if ( regul->voltage_table[i] == milivolts ) 
+        if ( regul->voltage_table[i] == milivolts )
         {
           LOG_D("idx:%d for %dmV\n\r", (int)i, (int)milivolts);
           return i;
@@ -716,7 +716,7 @@ void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn)
     LOG_I(" Interrupt received\n\r");
 }
 
-void STPMU1_INTn_Callback(PMIC_IRQn IRQn) 
+void STPMU1_INTn_Callback(PMIC_IRQn IRQn)
 {
     BSP_PMIC_INTn_Callback(IRQn);
 }
@@ -846,15 +846,15 @@ static rt_err_t rt_hw_pmic_init_register(void)
 static rt_err_t rt_hw_pmic_init(const char *bus_name)
 {
     PMIC_IRQn irq;
-    
+
     pmic_dev = rt_i2c_bus_device_find(bus_name);
-    
+
     if (pmic_dev == RT_NULL)
     {
         LOG_E("%s bus not found\n", bus_name);
         return -RT_ERROR;
     }
-    
+
     if (stpmu1_read_reg(VERSION_STATUS_REG) != PMIC_VERSION_ID)
     {
         return -RT_EIO;
@@ -863,7 +863,7 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
     STPMU1_Enable_Interrupt(IT_PONKEY_R);
     STPMU1_Enable_Interrupt(IT_PONKEY_F);
     /* enable all irqs  */
-    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) 
+    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++)
     {
         STPMU1_Enable_Interrupt(irq);
     }
@@ -874,18 +874,18 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
 static rt_err_t rt_hw_pmic_deinit(void)
 {
     BSP_PMIC_MspDeInit();
-    
+
     return RT_EOK;
 }
 
 static int pmic_init(void)
 {
     rt_err_t result = RT_EOK;
-    
+
     if (IS_ENGINEERING_BOOT_MODE())
     {
         BSP_PMIC_MspInit();
-        
+
         result = rt_hw_pmic_init(I2C_NAME);
         if(result != RT_EOK)
         {
@@ -893,16 +893,16 @@ static int pmic_init(void)
             rt_hw_pmic_deinit();
             return RT_ERROR;
         }
-        
+
         rt_hw_pmic_init_register();
-        
+
         __HAL_RCC_VREF_CLK_ENABLE();
         HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
         HAL_SYSCFG_EnableVREFBUF();
     }
 
     LOG_I("stpmic init success!");
-        
+
     return RT_EOK;
 }
 INIT_PREV_EXPORT(pmic_init);
@@ -910,12 +910,12 @@ INIT_PREV_EXPORT(pmic_init);
 static int i2c_sample(int argc, char *argv[])
 {
     rt_uint8_t id = 0;
-    
+
     if (argc > 1)
     {
         if (!rt_strcmp(argv[1], "read"))
-        { 
-           rt_kprintf("i2c read pmic version id\n"); 
+        {
+           rt_kprintf("i2c read pmic version id\n");
            id = stpmu1_read_reg(VERSION_STATUS_REG);
            rt_kprintf("version id : 0x%02x\n", id);
            return RT_EOK;
@@ -930,7 +930,7 @@ _exit:
         rt_kprintf("Usage:\n");
         rt_kprintf("i2c_sample read          - read pmic verison id\n");
     }
-    
+
     return RT_ERROR;
 }
 MSH_CMD_EXPORT(i2c_sample, i2c sample);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
index b24ccaeaf3..72c4af3a49 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
@@ -6,11 +6,11 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
+  * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                       opensource.org/licenses/BSD-3-Clause
   *
@@ -98,7 +98,7 @@ typedef struct {
 
 /* Those define should reflect NVM_USER section
  * For ES Eval Configuration this is specified as
- * 	0xF7,
+ *  0xF7,
  0x92,
  0xC0,
  0x02,
@@ -146,12 +146,12 @@ typedef struct {
 
  *
  */
-#define OTP_VINOK_HYST  	((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) 	// nvm_vinok_hyst
-#define OTP_VINOK		  	((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) 	// nvm_vinok
-#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) 	// Otp_ldo4_forced
-#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)	// nvm_longkeypress
-#define OTP_AUTOTURNON  	((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)	// nvm_autoturnon
-#define OTP_CC_KEEPOFF  	((NVM_SECTOR3_REGISTER_0 & 0x01))		// nvm_cc_keepoff
+#define OTP_VINOK_HYST      ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6)  // nvm_vinok_hyst
+#define OTP_VINOK           ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4)  // nvm_vinok
+#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3)  // Otp_ldo4_forced
+#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)  // nvm_longkeypress
+#define OTP_AUTOTURNON      ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)  // nvm_autoturnon
+#define OTP_CC_KEEPOFF      ((NVM_SECTOR3_REGISTER_0 & 0x01))       // nvm_cc_keepoff
 
 /*
  * nvm_rank_buck4:
@@ -176,10 +176,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_BUCK4  	((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) 	// nvm_rank_buck4
-#define OTP_RANK_BUCK3		((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) 	// nvm_rank_buck3
-#define OTP_RANK_BUCK2     	((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) 	// nvm_rank_buck2
-#define OTP_RANK_BUCK1  	((NVM_SECTOR3_REGISTER_1 & 0x03))		// nvm_rank_buck1
+#define OTP_RANK_BUCK4      ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6)  // nvm_rank_buck4
+#define OTP_RANK_BUCK3      ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4)  // nvm_rank_buck3
+#define OTP_RANK_BUCK2      ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2)  // nvm_rank_buck2
+#define OTP_RANK_BUCK1      ((NVM_SECTOR3_REGISTER_1 & 0x03))       // nvm_rank_buck1
 
 
 /*
@@ -205,10 +205,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_LDO4  		((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) 	// nvm_rank_ldo4
-#define OTP_RANK_LDO3		((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) 	// nvm_rank_ldo3
-#define OTP_RANK_LDO2     	((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) 	// nvm_rank_ldo2
-#define OTP_RANK_LDO1  		((NVM_SECTOR3_REGISTER_2 & 0x03))		// nvm_rank_ldo1
+#define OTP_RANK_LDO4       ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6)  // nvm_rank_ldo4
+#define OTP_RANK_LDO3       ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4)  // nvm_rank_ldo3
+#define OTP_RANK_LDO2       ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2)  // nvm_rank_ldo2
+#define OTP_RANK_LDO1       ((NVM_SECTOR3_REGISTER_2 & 0x03))       // nvm_rank_ldo1
 
 /*
  * nvm_clamp_output_buck: Clamp output value to 1.3V max
@@ -238,11 +238,11 @@ nvm_rank_ldo5:
  11:  rank3
  *
  */
-#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) 	// nvm_clamp_output_buck4
-#define OTP_BYPASS_MODE_LDO3  	((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) 	// nvm_bypass_mode_ldo3
-#define OTP_RANK_VREFDDR		((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) 	// nvm_rank_vrefddr
-#define OTP_RANK_LDO6     		((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) 	// nvm_rank_ldo6
-#define OTP_RANK_LDO5  			((NVM_SECTOR3_REGISTER_3 & 0x03))		// nvm_rank_ldo5
+#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7)  // nvm_clamp_output_buck4
+#define OTP_BYPASS_MODE_LDO3    ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6)  // nvm_bypass_mode_ldo3
+#define OTP_RANK_VREFDDR        ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4)  // nvm_rank_vrefddr
+#define OTP_RANK_LDO6           ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2)  // nvm_rank_ldo6
+#define OTP_RANK_LDO5           ((NVM_SECTOR3_REGISTER_3 & 0x03))       // nvm_rank_ldo5
 
 /*
  * nvm_output_buck4: Buck4 default output selection
@@ -267,31 +267,31 @@ nvm_rank_ldo5:
  11:  1.25V
  *
  */
-#define OTP_OUTPUT_BUCK4  		((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) 	// nvm_output_buck4
-#define OTP_OUTPUT_BUCK3		((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) 	// nvm_output_buck3
-#define OTP_OUTPUT_BUCK2     	((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) 	// nvm_output_buck2
-#define OTP_OUTPUT_BUCK1  		((NVM_SECTOR3_REGISTER_4 & 0x03))		// nvm_output_buck1
+#define OTP_OUTPUT_BUCK4        ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6)  // nvm_output_buck4
+#define OTP_OUTPUT_BUCK3        ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4)  // nvm_output_buck3
+#define OTP_OUTPUT_BUCK2        ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2)  // nvm_output_buck2
+#define OTP_OUTPUT_BUCK1        ((NVM_SECTOR3_REGISTER_4 & 0x03))       // nvm_output_buck1
 
 /*
- * [7]	OTP_SWOFF_BY_BOOST_OVP:
+ * [7]  OTP_SWOFF_BY_BOOST_OVP:
  0 -> SWOUT will not turnoff bu boost OVP
  1 -> SWOUT will be turnoff by BOOST OVP
 
- [6]	reserved
+ [6]    reserved
 
- [5:4]	nvm_output_ldo3: LDO3 default output selection
+ [5:4]  nvm_output_ldo3: LDO3 default output selection
  00:  1.8V
  01:  2.5V
  10:  3.3V
  11:  output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog)
 
- [3:2]	nvm_output_ldo2: LDO2 default output selection
+ [3:2]  nvm_output_ldo2: LDO2 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
  11: 3.3V
 
- [1:0]	nvm_output_ldo1: LDO1 default output selection
+ [1:0]  nvm_output_ldo1: LDO1 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
@@ -299,21 +299,21 @@ nvm_rank_ldo5:
 
  *
  */
-#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) 	// OTP_SWOFF_BY_BOOST_OVP
-#define OTP_OUTPUT_LDO3			((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) 	// nvm_output_ldo3
-#define OTP_OUTPUT_LDO2     	((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) 	// nvm_output_ldo2
-#define OTP_OUTPUT_LDO1  		((NVM_SECTOR3_REGISTER_5 & 0x03))		// nvm_output_ldo1
+#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7)  // OTP_SWOFF_BY_BOOST_OVP
+#define OTP_OUTPUT_LDO3         ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4)  // nvm_output_ldo3
+#define OTP_OUTPUT_LDO2         ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2)  // nvm_output_ldo2
+#define OTP_OUTPUT_LDO1         ((NVM_SECTOR3_REGISTER_5 & 0x03))       // nvm_output_ldo1
 
 /*
- * 	[7:4]	reserved
+ *  [7:4]   reserved
  *
- [3:2]	nvm_output_ldo6: LDO6 default output selection
+ [3:2]  nvm_output_ldo6: LDO6 default output selection
  00:  1.0V
  01:  1.2V
  10:  1.8V
  11:  3.3V
 
- [1:0]	nvm_output_ldo5: LDO5 default output selection
+ [1:0]  nvm_output_ldo5: LDO5 default output selection
  00:  1.8V
  01:  2.5V
  10:  2.9V
@@ -321,8 +321,8 @@ nvm_rank_ldo5:
  *
  */
 
-#define OTP_OUTPUT_LDO6     	((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) 	// nvm_output_ldo6
-#define OTP_OUTPUT_LDO5  		((NVM_SECTOR3_REGISTER_6 & 0x03))		// nvm_output_ldo5
+#define OTP_OUTPUT_LDO6         ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2)  // nvm_output_ldo6
+#define OTP_OUTPUT_LDO5         ((NVM_SECTOR3_REGISTER_6 & 0x03))       // nvm_output_ldo5
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define BIT(_x)  (1<<(_x))
@@ -417,7 +417,7 @@ nvm_rank_ldo5:
 #define LDO_BUCK_PULL_DOWN_MASK     0x03
 
 
-/* Main PMIC Control Register 
+/* Main PMIC Control Register
  * MAIN_CONTROL_REG
  * Address : 0x10
  * */
@@ -427,7 +427,7 @@ nvm_rank_ldo5:
 #define RESTART_REQUEST_ENABLED     BIT(1)
 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
 
-/* Main PMIC PADS Control Register 
+/* Main PMIC PADS Control Register
  * PADS_PULL_REG
  * Address : 0x11
  * */
@@ -438,7 +438,7 @@ nvm_rank_ldo5:
 #define PONKEY_PU_ACTIVE            BIT(0)
 
 
-/* Main PMIC VINLOW Control Register 
+/* Main PMIC VINLOW Control Register
  * VIN_CONTROL_REGC DMSC
  * Address : 0x15
  * */
@@ -452,7 +452,7 @@ nvm_rank_ldo5:
 #define VINLOW_CTRL_REG_MASK        0xFF
 
 
-/* USB Control Register 
+/* USB Control Register
  * Address : 0x40
  * */
 #define BOOST_OVP_DISABLED          BIT(7)
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
index 3aac57603d..a98b280f1b 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
index 8c6f45ad91..442bc14d9c 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@ static int rcc_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "enable"))
-        { 
+        {
            enable_clock();
            return RT_EOK;
         }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
index 44eba3be91..78475ec7e8 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ static rt_err_t rs485_output(rt_device_t dev, void * buffer)
 static rt_err_t rs485_input(rt_device_t dev, rt_size_t size)
 {
     rt_sem_release(&rx_sem);
-    
+
     return RT_EOK;
 }
 
@@ -38,13 +38,13 @@ int rs485_send_data(char *tbuf, rt_uint16_t t_len)
 {
     /* change rs485 mode */
     RS485_OUT;
-    
+
     /* send data */
     rt_device_write(serial, 0, tbuf, t_len);
-    
+
     /* change rs485 mode */
     RS485_IN;
-    
+
     return RT_EOK;
 }
 
@@ -59,10 +59,10 @@ static void rs485_thread_entry(void *parameter)
         {
             rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
         }
-        
+
         /* The data read through the serial port output dislocation */
         ch = ch + 1;
-        
+
         /* send char */
         rs485_send_data(&ch, 1);
     }
@@ -77,20 +77,20 @@ static int rs485_init(void)
     {
         rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME);
         return RT_ERROR;
-    }  
+    }
 
     rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
 
     /* set receive data callback function */
     rt_device_set_rx_indicate(serial, rs485_input);
-    
+
     /* set the send completion callback function */
     rt_device_set_tx_complete(serial, rs485_output);
-        
+
     rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT);
-    
+
     RS485_IN;
-    
+
     rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
     /* create rs485 thread */
     rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10);
@@ -103,8 +103,8 @@ static int rs485_init(void)
     {
         return RT_ERROR;
     }
-    
-    return RT_EOK;    
+
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rs485_init);
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
index 01edf84ae8..0d9767ac04 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@ extern "C" {
 
 #define RS485_SEND_MODE      0
 #define RS485_RECV_MODE      1
-    
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
index 45de04328f..df1ca92691 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -60,7 +60,7 @@ __attribute__((at(SDCARD_ADDR))) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
 #elif defined ( __GNUC__ )
 static rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection")));
 #elif defined(__ICCARM__)
-#pragma location = SDCARD_ADDR 
+#pragma location = SDCARD_ADDR
 __no_init static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
 #endif
 
@@ -151,7 +151,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
     {
         return;
     }
-    
+
     cmd->resp[0] = hw_sdio->resp1;
     cmd->resp[1] = hw_sdio->resp2;
     cmd->resp[2] = hw_sdio->resp3;
@@ -167,22 +167,22 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
         {
             cmd->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_CTIMEOUT)
         {
             cmd->err = -RT_ETIMEOUT;
         }
-        
+
         if (status & SDMMC_STA_DCRCFAIL)
         {
             data->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_DTIMEOUT)
         {
             data->err = -RT_ETIMEOUT;
         }
-        
+
         if (cmd->err == RT_EOK)
         {
             LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
@@ -205,7 +205,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
                   data ? data->blksize : 0
                  );
         }
-        
+
     }
     else
     {
@@ -226,7 +226,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
     struct rt_mmcsd_data *data = cmd->data;
     struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
     rt_uint32_t reg_cmd;
-    
+
     sdio->pkg = pkg;
 
     LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
@@ -254,9 +254,9 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
         reg_cmd |= SDMMC_RESPONSE_LONG;
     else
         reg_cmd |= SDMMC_RESPONSE_SHORT;
-    
+
     hw_sdio->mask |= SDIO_MASKR_ALL;
-        
+
     /* data pre configuration */
     if (data != RT_NULL)
     {
@@ -292,7 +292,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 
     /* close irq, keep sdio irq */
     hw_sdio->mask = hw_sdio->mask & SDMMC_IT_SDIOIT ? SDMMC_IT_SDIOIT : 0x00;
-    
+
     /* data post configuration */
     if (data != RT_NULL)
     {
@@ -316,7 +316,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     struct rt_mmcsd_data *data;
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     if (req->cmd != RT_NULL)
     {
         rt_memset(&pkg, 0, sizeof(pkg));
@@ -346,7 +346,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     }
 
     RTHW_SDIO_UNLOCK(sdio);
-    
+
     mmcsd_req_complete(sdio->host);
 }
 
@@ -392,7 +392,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
          );
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     clk_src = SDIO_CLOCK_FREQ;
 
     if (clk > 0)
@@ -425,7 +425,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
 
     if (io_cfg->power_mode == MMCSD_POWER_ON)
         hw_sdio->power |= SDMMC_POWER_PWRCTRL;
-    
+
     RTHW_SDIO_UNLOCK(sdio);
 }
 
@@ -513,7 +513,7 @@ err:
     {
         rt_free(sdio);
     }
-    
+
     return RT_NULL;
 }
 
@@ -522,7 +522,7 @@ void SDMMC1_IRQHandler(void)
     rt_interrupt_enter();
     /* Process All SDIO Interrupt Sources */
     rthw_sdio_irq_process(host1);
-    
+
     rt_interrupt_leave();
 }
 
@@ -577,7 +577,7 @@ int rt_hw_sdio_init(void)
         return RT_NULL;
     }
 #endif
-    
+
 #ifdef BSP_USING_SDIO2
     MX_RTC_Init();
     LBEE5KL1DX_init();
@@ -591,7 +591,7 @@ int rt_hw_sdio_init(void)
     {
         LOG_E("host2 create fail");
         return RT_NULL;
-    }    
+    }
 #endif
     return RT_EOK;
 }
@@ -601,7 +601,7 @@ INIT_DEVICE_EXPORT(rt_hw_sdio_init);
 int mnt_init(void)
 {
     rt_device_t sd = RT_NULL;
-    
+
     rt_thread_delay(RT_TICK_PER_SECOND);
 
     sd = rt_device_find("sd0");
@@ -610,7 +610,7 @@ int mnt_init(void)
         rt_kprintf("can't find sd0 device!\n");
         return RT_ERROR;
     }
-    
+
     if (dfs_mount("sd0", "/", "elm", 0, 0) != 0)
     {
         rt_kprintf("file system mount failed!\n");
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
index da70bf1257..9383e812e4 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -90,7 +90,7 @@ struct stm32_sdio
     volatile rt_uint32_t idmalar;
     volatile rt_uint32_t idmabar;
     volatile rt_uint32_t reserved2[5];
-    volatile rt_uint32_t fifo;          
+    volatile rt_uint32_t fifo;
     volatile rt_uint32_t reserved3[220];
     volatile rt_uint32_t verr;
     volatile rt_uint32_t ipidr;
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
index 4e9910aa95..77bde7d7b7 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,15 +22,15 @@
 #define LED5_PIN  GET_PIN(A, 14)
 
 static rt_uint8_t feed_flag = 0;
-static WWDG_HandleTypeDef hwwdg1;  
+static WWDG_HandleTypeDef hwwdg1;
 
 void WWDG1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_WWDG_IRQHandler(&hwwdg1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -50,18 +50,18 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
 static void wwdg_init()
 {
     rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
-        
+
     hwwdg1.Instance       = WWDG1;
     hwwdg1.Init.Prescaler = WWDG_PRESCALER_8;
     hwwdg1.Init.Window    = 0X5F;
     hwwdg1.Init.Counter   = 0x7F;
     hwwdg1.Init.EWIMode   = WWDG_EWI_ENABLE;
-      
+
     if (HAL_WWDG_Init(&hwwdg1) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     feed_flag = 1;
 }
 
@@ -69,10 +69,10 @@ static void wwdg_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hwwdg1.Instance->CFR &= ~(7 << 11);     /* clear WDGTB[2:0] */
-    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */	
+    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */
 }
 
 static void wwdg_stop(void)
@@ -85,7 +85,7 @@ static int wwdg_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "run"))
-        { 
+        {
             wwdg_init();
         }
         else if (!strcmp(argv[1], "set"))
@@ -93,7 +93,7 @@ static int wwdg_sample(int argc, char *argv[])
             if (argc > 2)
             {
                 wwdg_control(atoi(argv[2]));
-            }     
+            }
         }
         else if (!strcmp(argv[1], "stop"))
         {
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
index 1a4c91ac24..36a441d62f 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@ static int rt_spi_device_init(void)
     cfg.max_hz = 1 *1000 *1000;
 
     spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
-    
+
     if (RT_NULL == spi_dev)
     {
         rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
         return RT_ERROR;
     }
-    
+
     rt_spi_configure(spi_dev, &cfg);
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(rt_spi_device_init);
@@ -44,22 +44,22 @@ INIT_APP_EXPORT(rt_spi_device_init);
 /* spi5 loopback mode test case */
 static int spi_sample(int argc, char **argv)
 {
-    rt_uint8_t t_buf[8], r_buf[8];     
-    int i = 0; 
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
     static struct rt_spi_message msg1;
-    
+
     if (argc != 9)
     {
         rt_kprintf("Usage:\n");
         rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
         return -RT_ERROR;
     }
-    
+
     for (i = 0; i < 8; i++)
     {
         t_buf[i] = atoi(argv[i+1]);
     }
-    
+
     msg1.send_buf   = &t_buf;
     msg1.recv_buf   = &r_buf;
     msg1.length     = sizeof(t_buf);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
index fdbc721c8d..0f4df63bd3 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,11 +26,11 @@ static rt_adc_device_t adc_dev = RT_NULL;
 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
 {
     rt_uint32_t value = 0 , vol = 0;
-    
+
     /* read adc value */
     value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
     rt_kprintf("the value is :%d \n", value);
-    
+
     vol = value * REFER_VOLTAGE / CONVERT_BITS;
     rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
 
@@ -55,21 +55,21 @@ static int hwtimer_stop(void)
         rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME);
         return ret;
     }
-    
+
     /* close adc channel */
     ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
 static int hwtimer_start(void)
 {
     rt_err_t ret = RT_EOK;
-    rt_hwtimerval_t timeout_s;     
+    rt_hwtimerval_t timeout_s;
     rt_device_t hw_dev = RT_NULL;
-    
+
     rt_hwtimer_mode_t mode;
-        
+
     hw_dev = rt_device_find(HWTIMER_DEV_NAME);
     if (hw_dev == RT_NULL)
     {
@@ -84,7 +84,7 @@ static int hwtimer_start(void)
         rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME);
         return RT_ERROR;
     }
-    
+
     /* Open the device in read/write mode */
     ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
     if (ret != RT_EOK)
@@ -118,10 +118,10 @@ static int hwtimer_start(void)
 
     rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
     rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
-    
+
     /* enable adc channel */
     ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
@@ -130,8 +130,8 @@ static int tim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!rt_strcmp(argv[1], "start"))
-        { 
-           rt_kprintf("tim14 will start\n"); 
+        {
+           rt_kprintf("tim14 will start\n");
            hwtimer_start();
            return RT_EOK;
         }
@@ -152,7 +152,7 @@ _exit:
         rt_kprintf("tim_sample start         - start TIM14 \n");
         rt_kprintf("tim_sample stop          - stop TIM14 \n");
     }
-    
+
     return RT_ERROR;
 }
 MSH_CMD_EXPORT(tim_sample, tim sample);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c
index b38732f066..6e70b83927 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,19 +15,19 @@
 /* defined the LD4 pin: PD8 */
 #define LED4_PIN    GET_PIN(D, 8)
 
-int main(void) 
+int main(void)
 {
     int count = 1;
     /* set LD8 pin mode to output */
     rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT);
-    
+
     while (count++)
     {
         rt_pin_write(LED4_PIN, PIN_HIGH);
-        rt_thread_mdelay(500);    
+        rt_thread_mdelay(500);
         rt_pin_write(LED4_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    
+
     return RT_EOK;
 }
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.c b/bsp/stm32/stm32mp157a-st-ev1/board/board.c
index 362250de22..52475b9240 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/board.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2006-2018, RT-Thread Development Team
+* Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -21,13 +21,13 @@ void SystemClock_Config(void)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-    
+
     /**Configure LSE Drive Capability
     */
     HAL_PWR_EnableBkUpAccess();
     __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
-    
-    /**Initializes the CPU, AHB and APB busses clocks 
+
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
         |RCC_OSCILLATORTYPE_LSE;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.HSIState = RCC_HSI_ON;
     RCC_OscInitStruct.HSICalibrationValue = 16;
     RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
-    
+
     /**PLL1 Config
     */
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -50,7 +50,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL2 Config
     */
     RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
@@ -64,7 +64,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL3 Config
     */
     RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
@@ -79,7 +79,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL4 Config
     */
     RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
@@ -94,7 +94,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
     RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
         Error_Handler();
@@ -116,16 +116,16 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
     RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
     RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     /**Set the HSE division factor for RTC clock
     */
     __HAL_RCC_RTC_HSEDIV(24);
-    
+
     /* Configure the peripherals common clocks */
     if(IS_ENGINEERING_BOOT_MODE())
     {
@@ -140,7 +140,7 @@ void SystemClock_Config(void)
 */
 void PeriphCommonClock_Config(void) {
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     /** Initializes the common periph clock
     */
     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
@@ -152,11 +152,11 @@ void PeriphCommonClock_Config(void) {
 
 extern void rt_hw_systick_init(void);
 extern int rt_hw_usart_init(void);
-void rt_hw_board_init() 
+void rt_hw_board_init()
 {
     /* HAL_Init() function is called at the beginning of the program */
     HAL_Init();
-    
+
     /* enable interrupt */
     __set_PRIMASK(0);
     /* Configure the system clock */
@@ -166,29 +166,29 @@ void rt_hw_board_init()
     }
     /* disable interrupt */
     __set_PRIMASK(1);
-    
+
     rt_hw_systick_init();
-    
+
     /* Heap initialization */
 #if defined(RT_USING_HEAP)
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-    
+
     /* Pin driver initialization is open by default */
 #ifdef RT_USING_PIN
     rt_hw_pin_init();
 #endif
-    
+
     /* USART driver initialization is open by default */
 #ifdef RT_USING_SERIAL
     rt_hw_usart_init();
 #endif
-    
+
     /* Set the shell console output device */
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-    
+
     /* Board underlying hardware initialization */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.h b/bsp/stm32/stm32mp157a-st-ev1/board/board.h
index 334eea4f5c..0406e49952 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/board.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,13 +22,13 @@
 extern "C" {
 #endif
 
-#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)  
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)
 #define STM32_FLASH_SIZE             (192 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
 
 
 #define STM32_SRAM_SIZE           (64)
-#define STM32_SRAM_END            (0x10030000 + 64 * 1024)  	
+#define STM32_SRAM_END            (0x10030000 + 64 * 1024)
 
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c
index 12651efa1a..cee0c38d79 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ static VIRT_UART_HandleTypeDef huart0;
 
 static rt_uint8_t rx_buffer[MAX_BUFFER_SIZE];
 static rt_uint8_t tx_buffer[MAX_BUFFER_SIZE];
-  
+
 struct rthw_openamp
 {
     struct rt_device  parent;
@@ -36,41 +36,41 @@ struct rthw_openamp
 };
 static struct rthw_openamp  dev_openamp;
 
-void IPCC_RX1_IRQHandler(void) 
+void IPCC_RX1_IRQHandler(void)
 {
     rt_interrupt_enter();
-    
+
     HAL_IPCC_RX_IRQHandler(&hipcc);
-    
+
     rt_interrupt_leave();
 }
 
 void IPCC_TX1_IRQHandler(void)
 {
     rt_interrupt_enter();
-        
+
     HAL_IPCC_TX_IRQHandler(&hipcc);
-    
+
     rt_interrupt_leave();
 }
 
-void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) 
-{  
+void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart)
+{
     rt_uint16_t rx_size = 0, i = 0;
     rt_size_t count, size, offset;
     rt_uint8_t *buf = RT_NULL;
-    
+
     struct rthw_openamp  *device;
     device = (struct rthw_openamp *)rt_device_find("openamp");
     RT_ASSERT(device != RT_NULL);
-   
-    buf    = device->serial.rbuf; 
+
+    buf    = device->serial.rbuf;
     count  = device->serial.rbuf_count;
     size   = device->serial.rbuf_size;
     offset = device->serial.rbuf_start + count;
-   
+
     rt_sem_take(&device->sema, RT_WAITING_FOREVER);
-        
+
     rx_size = (huart->RxXferSize < MAX_BUFFER_SIZE) ? huart->RxXferSize : MAX_BUFFER_SIZE - 1;
 
     if (count < size)
@@ -79,7 +79,7 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart)
         {
             offset -= size;
         }
-        
+
         for (i = 0; i < rx_size; i++)
         {
            buf[offset++] = huart->pRxBuffPtr[i];
@@ -88,16 +88,16 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart)
     }
 
     device->serial.rbuf_count = count;
-    
+
     rt_sem_release(&device->sema);
 }
- 
+
 static rt_err_t _init(struct rt_device *dev)
 {
     struct rthw_openamp  *device;
     device = (struct rthw_openamp *)dev;
     RT_ASSERT(device != RT_NULL);
-    
+
     device->serial.rbuf_start  = 0;
     device->serial.rbuf_count  = 0;
     device->serial.tbuf_start  = 0;
@@ -106,79 +106,79 @@ static rt_err_t _init(struct rt_device *dev)
     device->serial.tbuf_size   = MAX_BUFFER_SIZE;
     device->serial.rbuf        = rx_buffer;
     device->serial.tbuf        = tx_buffer;
-  
+
     if (rt_sem_init(&device->sema, "openamplock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
     {
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
 static rt_size_t _read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
     rt_size_t count, rbsize, offset;
-    rt_uint8_t *buf     = RT_NULL; 
+    rt_uint8_t *buf     = RT_NULL;
     rt_uint8_t *pBuffer = RT_NULL;
     rt_uint16_t i = 0;
-    
+
     struct rthw_openamp  *device;
     device = (struct rthw_openamp *)dev;
     RT_ASSERT(device != RT_NULL);
-    
+
     pBuffer = (unsigned char*)buffer;
     count   = device->serial.rbuf_count;
     buf     = device->serial.rbuf;
-    
+
     if (count == 0)
     {
         return -RT_ERROR;
     }
-    
+
     rt_sem_take(&device->sema, RT_WAITING_FOREVER);
-    
+
     if (count >= size)
     {
         count = size;
-    } 
+    }
 
     offset = device->serial.rbuf_start;
     rbsize = device->serial.rbuf_size;
- 
+
     for (i = 0; i < count; i++)
     {
         *pBuffer++ = buf[offset++];
         if (offset > rbsize)
         {
-           offset = 0;  
+           offset = 0;
         }
     }
 
     device->serial.rbuf_start  = offset;
     device->serial.rbuf_count -= count;
-    
+
     rt_sem_release(&device->sema);
-    
+
     return count;
 }
- 
+
 static rt_size_t _write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
     rt_err_t result = VIRT_UART_OK;
-    
+
     struct rthw_openamp  *device;
     device = (struct rthw_openamp *)dev;
     RT_ASSERT(device != RT_NULL);
-    
+
     rt_sem_take(&device->sema, RT_WAITING_FOREVER);
-    result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size); 
+    result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size);
     rt_sem_release(&device->sema);
-        
+
     if (result != VIRT_UART_OK)
     {
         return -RT_ERROR;
     }
-    
+
     return size;
 }
 
@@ -206,7 +206,7 @@ static rt_err_t rt_hw_openamp_register(struct rthw_openamp  *openamp, const char
 }
 
 static int openamp_init(void)
-{  
+{
     extern int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb);
 
     /* IPCC init */
@@ -217,25 +217,25 @@ static int openamp_init(void)
     }
     /* openamp slave device */
     MX_OPENAMP_Init(RPMSG_REMOTE, NULL);
-    
-    if (VIRT_UART_Init(&huart0) != VIRT_UART_OK) 
+
+    if (VIRT_UART_Init(&huart0) != VIRT_UART_OK)
     {
         return RT_ERROR;
     }
-    if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK) 
+    if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK)
     {
         return RT_ERROR;
     }
-    
-    return RT_EOK;    
+
+    return RT_EOK;
 }
 
 int rt_hw_openamp_init(void)
 {
     openamp_init();
-    
+
     rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL);
-    
+
     if (RT_CONSOLE_DEVICE_NAME == "openamp")
     {
         rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
@@ -245,27 +245,27 @@ int rt_hw_openamp_init(void)
 }
 INIT_PREV_EXPORT(rt_hw_openamp_init);
 
-static void openamp_thread_entry(void *parameter) 
+static void openamp_thread_entry(void *parameter)
 {
     rt_size_t size = 0;
     struct rthw_openamp  *device = RT_NULL;
-    
+
     device = (struct rthw_openamp *)rt_device_find("openamp");
     RT_ASSERT(device != RT_NULL);
-    
-    for (;;) 
+
+    for (;;)
     {
         OPENAMP_check_for_message();
 
         size = device->serial.rbuf_count;
         if (size > 0)
         {
-            if (device->parent.rx_indicate != RT_NULL) 
+            if (device->parent.rx_indicate != RT_NULL)
             {
                 device->parent.rx_indicate(&device->parent, size);
             }
         }
-        
+
         rt_thread_mdelay(1);
     }
 }
@@ -273,22 +273,22 @@ static void openamp_thread_entry(void *parameter)
 static int creat_openamp_thread(void)
 {
     rt_thread_t tid = RT_NULL;
-    
-    tid = rt_thread_create("OpenAMP", 
-                        openamp_thread_entry, 
-                        RT_NULL, 
-                        OPENAMP_THREAD_STACK_SIZE, 
-                        OPENAMP_THREAD_PRIORITY, 
+
+    tid = rt_thread_create("OpenAMP",
+                        openamp_thread_entry,
+                        RT_NULL,
+                        OPENAMP_THREAD_STACK_SIZE,
+                        OPENAMP_THREAD_PRIORITY,
                         OPENAMP_THREAD_TIMESLICE);
-    
-    if (tid == RT_NULL) 
+
+    if (tid == RT_NULL)
     {
         LOG_E("openamp thread create failed!");
         return RT_ERROR;
-    } 
-    
+    }
+
     rt_thread_startup(tid);
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(creat_openamp_thread);
@@ -298,7 +298,7 @@ INIT_APP_EXPORT(creat_openamp_thread);
 static int console(int argc, char **argv)
 {
     rt_err_t result = RT_EOK;
-    
+
     if (argc > 1)
     {
         if (!strcmp(argv[1], "set"))
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h
index df1533b38b..20538a999d 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,22 +18,22 @@ extern "C" {
 
 struct rt_openamp
 {
-    rt_uint8_t   *rbuf; 
-    rt_uint8_t   *tbuf;          
-    volatile rt_uint16_t  rbuf_size;      
+    rt_uint8_t   *rbuf;
+    rt_uint8_t   *tbuf;
+    volatile rt_uint16_t  rbuf_size;
     volatile rt_uint16_t  tbuf_size;
     volatile rt_uint16_t  rbuf_start;
     volatile rt_uint16_t  rbuf_count;
     volatile rt_uint16_t  tbuf_start;
     volatile rt_uint16_t  tbuf_count;
 };
-    
+
 #define OPENAMP_THREAD_STACK_SIZE   512
 #define OPENAMP_THREAD_PRIORITY     5
 #define OPENAMP_THREAD_TIMESLICE    10
 
 #define MAX_BUFFER_SIZE             256
-  
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c
index 23cc195046..4a269bf936 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -83,9 +83,9 @@ static int uart_dma_sample(int argc, char *argv[])
     }
 
     rt_mq_init(&rx_mq, "rx_mq",
-               msg_pool,                 
-               sizeof(struct rx_msg),    
-               sizeof(msg_pool), 
+               msg_pool,
+               sizeof(struct rx_msg),
+               sizeof(msg_pool),
                RT_IPC_FLAG_FIFO);
 
     ret = rt_device_open(serial, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX);
@@ -94,14 +94,14 @@ static int uart_dma_sample(int argc, char *argv[])
         rt_kprintf("serial device open fail!.\n");
         return -RT_ERROR;
     }
-    
+
     ret = rt_device_set_rx_indicate(serial, uart_input);
     if (ret != RT_EOK)
     {
         rt_kprintf("set rx indicate fail!.\n");
         return -RT_ERROR;
     }
-    
+
     rt_device_write(serial, 0, str, (sizeof(str) - 1));
 
     rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c
index def5dfd461..1accaced7c 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -110,7 +110,7 @@ void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	jpeg_data_process();
+    jpeg_data_process();
     __HAL_DCMI_ENABLE_IT(&dcmi,DCMI_IT_FRAME);
     /* leave interrupt */
     rt_interrupt_leave();
@@ -127,7 +127,7 @@ void DMA1_Stream3_IRQHandler(void)
         __HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF3_7);
         rt_hw_camera_rx_callback();
     }
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h
index 39fe3bdd26..d83c739a83 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c
index 38678dbdce..61600fbd00 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -67,7 +67,7 @@ void DMA2_Stream2_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_dfsdm1_flt1);
 
     /* leave interrupt */
@@ -78,9 +78,9 @@ void DMA2_Stream1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_dfsdm1_flt0);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -122,15 +122,15 @@ static int rt_hw_dfsdm_init(void)
     hdfsdm1_channel1.Init.Input.Pins               = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
     hdfsdm1_channel1.Init.SerialInterface.Type     = DFSDM_CHANNEL_SPI_RISING ;   /* left */
     hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
-    hdfsdm1_channel1.Init.Awd.FilterOrder          = DFSDM_CHANNEL_FASTSINC_ORDER; 
-    hdfsdm1_channel1.Init.Awd.Oversampling         = 10; 
+    hdfsdm1_channel1.Init.Awd.FilterOrder          = DFSDM_CHANNEL_FASTSINC_ORDER;
+    hdfsdm1_channel1.Init.Awd.Oversampling         = 10;
     hdfsdm1_channel1.Init.Offset                   = 0;
     hdfsdm1_channel1.Init.RightBitShift            = 2;
     if(HAL_OK != HAL_DFSDM_ChannelInit(&hdfsdm1_channel1))
     {
         return RT_ERROR;
     }
-    
+
     /* DATAIN1_RIGHT */
     __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&hdfsdm1_channel0);
     hdfsdm1_channel0.Instance                      = DFSDM1_Channel0;
@@ -138,7 +138,7 @@ static int rt_hw_dfsdm_init(void)
     hdfsdm1_channel0.Init.OutputClock.Selection    = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
     hdfsdm1_channel0.Init.OutputClock.Divider      = 74;  /* 209/74 = 2.82MHZ*/
     hdfsdm1_channel0.Init.Input.Multiplexer        = DFSDM_CHANNEL_EXTERNAL_INPUTS;
-    hdfsdm1_channel0.Init.Input.DataPacking        = DFSDM_CHANNEL_STANDARD_MODE; 
+    hdfsdm1_channel0.Init.Input.DataPacking        = DFSDM_CHANNEL_STANDARD_MODE;
     hdfsdm1_channel0.Init.Input.Pins               = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
     hdfsdm1_channel0.Init.SerialInterface.Type     = DFSDM_CHANNEL_SPI_FALLING;   /* right */
     hdfsdm1_channel0.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
@@ -159,7 +159,7 @@ static int rt_hw_dfsdm_init(void)
     hdfsdm1_filter0.Init.RegularParam.DmaMode         = ENABLE;
     hdfsdm1_filter0.Init.InjectedParam.Trigger        = DFSDM_FILTER_SW_TRIGGER;
     hdfsdm1_filter0.Init.InjectedParam.ScanMode       = DISABLE;
-    hdfsdm1_filter0.Init.InjectedParam.DmaMode        = DISABLE; 
+    hdfsdm1_filter0.Init.InjectedParam.DmaMode        = DISABLE;
     hdfsdm1_filter0.Init.FilterParam.SincOrder        = DFSDM_FILTER_SINC3_ORDER;
     hdfsdm1_filter0.Init.FilterParam.Oversampling     = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/
     hdfsdm1_filter0.Init.FilterParam.IntOversampling  = 1;
@@ -174,9 +174,9 @@ static int rt_hw_dfsdm_init(void)
     hdfsdm1_filter1.Init.RegularParam.Trigger         = DFSDM_FILTER_SW_TRIGGER;
     hdfsdm1_filter1.Init.RegularParam.FastMode        = ENABLE;
     hdfsdm1_filter1.Init.RegularParam.DmaMode         = ENABLE;
-    hdfsdm1_filter1.Init.InjectedParam.Trigger        = DFSDM_FILTER_SW_TRIGGER; 
-    hdfsdm1_filter1.Init.InjectedParam.ScanMode       = DISABLE; 
-    hdfsdm1_filter1.Init.InjectedParam.DmaMode        = DISABLE; 
+    hdfsdm1_filter1.Init.InjectedParam.Trigger        = DFSDM_FILTER_SW_TRIGGER;
+    hdfsdm1_filter1.Init.InjectedParam.ScanMode       = DISABLE;
+    hdfsdm1_filter1.Init.InjectedParam.DmaMode        = DISABLE;
     hdfsdm1_filter1.Init.FilterParam.SincOrder        = DFSDM_FILTER_SINC3_ORDER;
     hdfsdm1_filter1.Init.FilterParam.Oversampling     = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/
     hdfsdm1_filter1.Init.FilterParam.IntOversampling  = 1;
@@ -221,7 +221,7 @@ static rt_err_t rt_hw_dfsdm_open(void)
 static rt_err_t _init(rt_device_t dev)
 {
    RT_ASSERT(dev != RT_NULL);
-   
+
    rt_hw_dfsdm_init();
 
    return RT_EOK;
@@ -230,7 +230,7 @@ static rt_err_t _init(rt_device_t dev)
 static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag)
 {
    RT_ASSERT(dev != RT_NULL);
-   
+
    rt_hw_dfsdm_open();
 
    return RT_EOK;
@@ -239,10 +239,10 @@ static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag)
 static rt_err_t _close(rt_device_t dev)
 {
    RT_ASSERT(dev != RT_NULL);
-   
+
    HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter0);
    HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter1);
-    
+
    return RT_EOK;
 }
 
@@ -252,7 +252,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si
     rt_uint32_t i = 0;
     rt_int16_t *p = RT_NULL;
     p = (rt_int16_t *)buffer;
-    
+
     if (!pos)
     {
         for (i = 0; i < 512; i++)
@@ -267,7 +267,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si
         {
             p[2*i]     = (int16_t)SaturaLH((FILTER0_FIFO[i] >> 8), -32768, 32767);
             p[(2*i)+1] = (int16_t)SaturaLH((FILTER1_FIFO[i] >> 8), -32768, 32767);
-        } 
+        }
     }
 
     return size;
@@ -276,7 +276,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si
 static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
    RT_ASSERT(dev != RT_NULL);
-   
+
    return RT_EOK;
 }
 
@@ -299,9 +299,9 @@ int dfsdm_init(void)
     dfsdm_dev.user_data = RT_NULL;
 
     rt_device_register(&dfsdm_dev, "dfsdm1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
-    
+
     LOG_I("dfsdm1 init success!");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(dfsdm_init);
@@ -314,38 +314,38 @@ static int dfsdm_sample(int argc, char **argv)
         rt_kprintf("dfsdm_sample\n");
         return -1;
     }
-    
-    static struct rt_device *dfsdm_dev = RT_NULL;  
-    static struct rt_device *sound_dev = RT_NULL; 
+
+    static struct rt_device *dfsdm_dev = RT_NULL;
+    static struct rt_device *sound_dev = RT_NULL;
     rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE;
     rt_uint16_t tickstart = 0;
-    
+
     extern SAI_HandleTypeDef hsai_BlockA2;
-    
+
     dfsdm_dev = rt_device_find("dfsdm1");
     if (dfsdm_dev == RT_NULL)
     {
         rt_kprintf("no dfsdm device!");
         return RT_ERROR;
     }
-    
+
     sound_dev = rt_device_find("decoder");
     if (sound_dev == RT_NULL)
     {
         rt_kprintf("no decoder device!");
-        return RT_ERROR;    
+        return RT_ERROR;
     }
 
     /* open dfsdm device */
     rt_device_open(dfsdm_dev, RT_DEVICE_OFLAG_RDWR);
     /* open sound device */
     rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY);
-    
+
     rt_device_control(sound_dev, SET_PLAY_TYPE, &play_type);
     rt_device_control(sound_dev, START_PLAY, RT_NULL);
-    
+
     rt_memset(PLAY_BUF, 0, PALY_SIZE);
-    
+
     tickstart = rt_tick_get();
     if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, (uint8_t *)PLAY_BUF, PALY_SIZE) != HAL_OK)
     {
@@ -353,7 +353,7 @@ static int dfsdm_sample(int argc, char **argv)
         return RT_ERROR;
     }
     rt_kprintf("dfsdm audio record test begin!\n");
-    
+
     while (1)
     {
         if ((rt_tick_get() - tickstart) > 0x1000)
@@ -375,9 +375,9 @@ static int dfsdm_sample(int argc, char **argv)
             DmaRightRecBuffCplt = 0;
         }
     }
-    
+
     rt_kprintf("dfsdm audio record test end!\n");
-    
+
     return RT_EOK;
 }
 MSH_CMD_EXPORT(dfsdm_sample, dfsdm audiorecord test);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h
index bf40fbf2f8..7b73c85638 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,7 +18,7 @@ extern "C" {
 #endif
 
 #define SaturaLH(N, L, H) (((N)<(L))?(L):(((N)>(H))?(H):(N)))
-    
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c
index 54af52e5e0..3e1913bb94 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -172,7 +172,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
     {
         return;
     }
-    
+
     cmd->resp[0] = hw_sdio->resp1;
     cmd->resp[1] = hw_sdio->resp2;
     cmd->resp[2] = hw_sdio->resp3;
@@ -188,22 +188,22 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
         {
             cmd->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_CTIMEOUT)
         {
             cmd->err = -RT_ETIMEOUT;
         }
-        
+
         if (status & SDMMC_STA_DCRCFAIL)
         {
             data->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_DTIMEOUT)
         {
             data->err = -RT_ETIMEOUT;
         }
-        
+
         if (cmd->err == RT_EOK)
         {
             LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
@@ -226,7 +226,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
                   data ? data->blksize : 0
                  );
         }
-        
+
     }
     else
     {
@@ -247,7 +247,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
     struct rt_mmcsd_data *data = cmd->data;
     struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
     rt_uint32_t reg_cmd;
-    
+
     sdio->pkg = pkg;
 
     LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
@@ -282,7 +282,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
         reg_cmd |= SDMMC_RESPONSE_SHORT;
     }
     hw_sdio->mask |= SDIO_MASKR_ALL;
-        
+
     /* data pre configuration */
     if (data != RT_NULL)
     {
@@ -324,7 +324,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 #if defined(EMMC_RX_DUMP)
             rt_kprintf("\nEMMC Rx:\n");
             dump_hex(cache_buf, data->blks * data->blksize);
-#endif            
+#endif
             rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
         }
     }
@@ -343,7 +343,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     struct rt_mmcsd_data *data;
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     if (req->cmd != RT_NULL)
     {
         rt_memset(&pkg, 0, sizeof(pkg));
@@ -361,7 +361,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
 #if defined(EMMC_TX_DUMP)
             rt_kprintf("\nEMMC Tx:\n");
             dump_hex(cache_buf, data->blks * data->blksize);
-#endif   
+#endif
                 rt_memcpy(cache_buf, data->buf, size);
             }
         }
@@ -377,7 +377,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     }
 
     RTHW_SDIO_UNLOCK(sdio);
-    
+
     mmcsd_req_complete(sdio->host);
 }
 
@@ -423,7 +423,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
          );
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     clk_src = EMMC_CLOCK_FREQ;
 
     if (clk > 0)
@@ -451,12 +451,12 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
     {
         temp |= SDMMC_BUS_WIDE_1B;
     }
-    
+
     hw_sdio->clkcr = temp;
 
     if (io_cfg->power_mode == MMCSD_POWER_ON)
         hw_sdio->power |= SDMMC_POWER_PWRCTRL;
-    
+
     RTHW_SDIO_UNLOCK(sdio);
 }
 
@@ -529,7 +529,7 @@ err:
     {
         rt_free(sdio);
     }
-    
+
     return RT_NULL;
 }
 
@@ -538,14 +538,14 @@ void SDMMC2_IRQHandler(void)
     rt_interrupt_enter();
     /* Process All SDIO Interrupt Sources */
     rthw_sdio_irq_process(host);
-    
+
     rt_interrupt_leave();
 }
 
 int rt_hw_sdio_init(void)
 {
     struct stm32_sdio_des sdio_des;
-    
+
     hsd.Instance = SDMMC2;
     HAL_SD_MspInit(&hsd);
 
@@ -563,20 +563,20 @@ INIT_DEVICE_EXPORT(rt_hw_sdio_init);
 int mnt_init(void)
 {
     rt_device_t sd = RT_NULL;
-    
+
 #if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP)
     rt_thread_delay(3000);
 #else
     rt_thread_delay(RT_TICK_PER_SECOND);
 #endif
-    
+
     sd = rt_device_find("sd0");
     if (sd == RT_NULL)
     {
         rt_kprintf("can't find emmc device!\n");
         return RT_ERROR;
     }
-    
+
     if (dfs_mount("sd0", "/", "elm", 0, 0) != 0)
     {
         rt_kprintf("file system mount failed!\n");
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h
index bd385cbb14..7f3e8c1dc8 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -76,7 +76,7 @@ struct stm32_sdio
     volatile rt_uint32_t idmalar;
     volatile rt_uint32_t idmabar;
     volatile rt_uint32_t reserved2[5];
-    volatile rt_uint32_t fifo;          
+    volatile rt_uint32_t fifo;
     volatile rt_uint32_t reserved3[220];
     volatile rt_uint32_t verr;
     volatile rt_uint32_t ipidr;
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c
index d3d118fd9f..caaf002aa9 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ static int exti_sample(void)
     rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP);
     rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL);
     rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE);
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(exti_sample);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c
index 78c18e8594..494d8e399f 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h
index ab4280d360..764a69105f 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c
index 195345c19d..34a8ae0593 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@ void LPTIM1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_LPTIM_IRQHandler(&hlptim1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -41,10 +41,10 @@ void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
     {
         HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9);
     }
-    
+
 #if defined(BSP_USING_PWR)
     /* All level of ITs can interrupt */
-    __set_BASEPRI(0U); 
+    __set_BASEPRI(0U);
 
     lptim_stop();
     rt_kprintf("system returns to normal!\n");
@@ -55,12 +55,12 @@ static int lptim_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hlptim1.Instance->CFGR &= ~(7 << 9);      /* clear PRESC[2:0] */
     hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0]  */
     rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value);
-    
+
     return RT_EOK;
 }
 
@@ -72,9 +72,9 @@ int lptim_start(void)
         LOG_D("lptim1 start counting failed!\n");
         return -RT_ERROR;
     }
-    
+
     LOG_D("lptim1 start counting success!\n");
-        
+
     return RT_EOK;
 }
 
@@ -85,16 +85,16 @@ int lptim_stop(void)
         LOG_D("lptim1 stop failed!\n");
         return -RT_ERROR;
    }
-   
-   LOG_D("lptim1 stop counting success!\n"); 
-   
+
+   LOG_D("lptim1 stop counting success!\n");
+
    return RT_EOK;
 }
 
 int lptim_init(void)
 {
     rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
-        
+
     hlptim1.Instance = LPTIM1;
     hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
     hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8;
@@ -112,7 +112,7 @@ int lptim_init(void)
         return -RT_ERROR;
     }
     LOG_D("lptim init success!\n");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(lptim_init);
@@ -122,7 +122,7 @@ static int lptim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "start"))
-        { 
+        {
            lptim_start();
            return RT_EOK;
         }
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c
index 071f833a10..c92145f378 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@
 
 struct st_mfx
 {
-    struct rt_device dev; 
+    struct rt_device dev;
     struct rt_i2c_bus_device *i2c_bus;
     rt_uint8_t id;
     rt_uint16_t type;
@@ -31,7 +31,7 @@ static IO_DrvTypeDef *IoDrv = NULL;
 static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint16_t len, rt_uint8_t *buf)
 {
     struct rt_i2c_msg msg[2] = {0, 0};
-    
+
     RT_ASSERT(bus != RT_NULL);
 
     msg[0].addr  = CHIP_ADDRESS;
@@ -134,11 +134,11 @@ RT_WEAK void MFX_IO_Delay(rt_uint32_t Delay)
     rt_thread_delay(Delay);
 }
 
-RT_WEAK void MFX_IO_Wakeup(void) 
+RT_WEAK void MFX_IO_Wakeup(void)
 {
 }
 
-RT_WEAK void MFX_IO_EnableWakeupPin(void) 
+RT_WEAK void MFX_IO_EnableWakeupPin(void)
 {
 }
 
@@ -172,7 +172,7 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear)
 
 /**
   * @brief  Configures the IO pin(s) according to IO mode structure value.
-  * @param  IoPin: IO pin(s) to be configured. 
+  * @param  IoPin: IO pin(s) to be configured.
   *          This parameter can be one of the following values:
   *            @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
   * @param  IoMode: IO pin mode to configure
@@ -182,7 +182,7 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear)
   *            @arg  IO_MODE_IT_RISING_EDGE
   *            @arg  IO_MODE_IT_FALLING_EDGE
   *            @arg  IO_MODE_IT_LOW_LEVEL
-  *            @arg  IO_MODE_IT_HIGH_LEVEL            
+  *            @arg  IO_MODE_IT_HIGH_LEVEL
   *            @arg  IO_MODE_ANALOG
   *            @arg  IO_MODE_OFF
   *            @arg  IO_MODE_INPUT_PU,
@@ -201,20 +201,20 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear)
   *            @arg  IO_MODE_IT_FALLING_EDGE_PD
   *            @arg  IO_MODE_IT_LOW_LEVEL_PD
   *            @arg  IO_MODE_IT_HIGH_LEVEL_PD
-  * @retval RT_EOK if all initializations are OK. Other value if error.  
+  * @retval RT_EOK if all initializations are OK. Other value if error.
   */
 rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode)
 {
     /* Configure the selected IO pin(s) mode */
     IoDrv->Config(0, IoPin, IoMode);
 
-    return RT_EOK;  
+    return RT_EOK;
 }
 
 /**
   * @brief  Sets the IRQ_OUT pin polarity and type
   * @param  IoIrqOutPinPolarity: High/Low
-  * @param  IoIrqOutPinType:     OpenDrain/PushPull 
+  * @param  IoIrqOutPinType:     OpenDrain/PushPull
   * @retval OK
   */
 rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType)
@@ -231,9 +231,9 @@ rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOut
 
 /**
   * @brief  Sets the selected pins state.
-  * @param  IoPin: Selected pins to write. 
-  *          This parameter can be any combination of the IO pins. 
-  * @param  PinState: New pins state to write  
+  * @param  IoPin: Selected pins to write.
+  *          This parameter can be any combination of the IO pins.
+  * @param  PinState: New pins state to write
   * @retval None
   */
 void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState)
@@ -244,9 +244,9 @@ void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState)
 
 /**
   * @brief  Gets the selected pins current state.
-  * @param  IoPin: Selected pins to read. 
-  *          This parameter can be any combination of the IO pins. 
-  * @retval The current pins state 
+  * @param  IoPin: Selected pins to read.
+  *          This parameter can be any combination of the IO pins.
+  * @retval The current pins state
   */
 rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin)
 {
@@ -255,9 +255,9 @@ rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin)
 
 /**
   * @brief  Toggles the selected pins state.
-  * @param  IoPin: Selected pins to toggle. 
-  *          This parameter can be any combination of the IO pins.  
-  * @note   This function is only used to toggle one pin in the same time  
+  * @param  IoPin: Selected pins to toggle.
+  *          This parameter can be any combination of the IO pins.
+  * @note   This function is only used to toggle one pin in the same time
   * @retval None
   */
 void rt_mfx_pin_toggle(rt_uint32_t IoPin)
@@ -270,7 +270,7 @@ void rt_mfx_pin_toggle(rt_uint32_t IoPin)
     else
     {
         IoDrv->WritePin(0, IoPin, 1); /* Set */
-    } 
+    }
 }
 
 int rt_mfx_init(void)
@@ -285,13 +285,13 @@ int rt_mfx_init(void)
         /* Initialize MFX */
         IoDrv->Init(0);
         IoDrv->Start(0, IO_PIN_ALL);
-        
+
         LOG_I("mfx init success, id: 0x%x", rt_mfx.id);
-        
+
         return RT_EOK;
     }
     LOG_I("mfx init error, id: 0x%x", rt_mfx.id);
-    
+
     return RT_ERROR;
 }
 INIT_DEVICE_EXPORT(rt_mfx_init);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h
index a0cf46777c..9816c8c335 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c
index 84e93e2926..f92dd09afb 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,8 +21,8 @@
 
 #define NAND_RB_PIN GET_PIN(D, 6)
 
-static rt_uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];	
-static rt_uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];	
+static rt_uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];
+static rt_uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];
 struct rthw_fmc
 {
     rt_uint32_t id;
@@ -193,11 +193,11 @@ static rt_uint8_t rt_hw_nand_ecc_check(rt_uint32_t generatedEcc, rt_uint32_t rea
 
     syndrome = (generatedEcc ^ readEcc) & ECC_MASK28;
 
-    if (syndrome == 0)   
+    if (syndrome == 0)
     {
         return (RT_EOK);                     /* No errors in data. */
     }
-     
+
     eccPn = syndrome & ECC_MASK;              /* Get 14 odd parity bits.  */
     eccP  = (syndrome >> 1) & ECC_MASK;       /* Get 14 even parity bits. */
 
@@ -255,13 +255,13 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
     rt_uint32_t index, i, tickstart, eccnum;
     rt_err_t result;
     rt_uint8_t *p = RT_NULL;
-    
+
     page = page + device->block_start * device->pages_per_block;
     if (page / device->pages_per_block > device->block_end)
     {
         return -RT_EIO;
     }
-    
+
     rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);
     if (data && data_len)
     {
@@ -272,9 +272,9 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
         NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
         NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
         NAND_CMD_AREA  = NAND_AREA_TRUE1;
-        
+
         rt_hw_nand_delay(10);
-        
+
         /* not an integer multiple of NAND ECC SECTOR SIZE, no ECC checks*/
         if (data_len % NAND_ECC_SECTOR_SIZE)
         {
@@ -285,16 +285,16 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
         }
         else
         {
-            eccnum = data_len/NAND_ECC_SECTOR_SIZE;			
+            eccnum = data_len/NAND_ECC_SECTOR_SIZE;
             p = data;
             for (index = 0; index < 4; index++)
             {
-                FMC_Bank3_R->PCR |= 1<<6;	/* enable ecc */ 
-            
-                for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)				
+                FMC_Bank3_R->PCR |= 1<<6;   /* enable ecc */
+
+                for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)
                 {
                     *data++ = NAND_ADDR_AREA;
-                }		
+                }
                 /* Get tick */
                 tickstart = rt_tick_get();
                 /* Wait until FIFO is empty */
@@ -307,25 +307,25 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
                         goto _exit;
                     }
                 }
-                ecc_hdbuf[index] = FMC_Bank3_R->HECCR;	/* read hardware ecc */
-                FMC_Bank3_R->PCR &= ~(1<<6);		    /* disable ecc */
+                ecc_hdbuf[index] = FMC_Bank3_R->HECCR;  /* read hardware ecc */
+                FMC_Bank3_R->PCR &= ~(1<<6);            /* disable ecc */
             }
             i = device->page_size + 0x10;
-            
+
             rt_hw_nand_delay(10);
-            
+
             NAND_CMD_AREA  = 0x05;
             NAND_DATA_AREA = (rt_uint8_t)i;
             NAND_DATA_AREA = (rt_uint8_t)(i>>8);
             NAND_CMD_AREA  = 0xE0;
-            
+
             rt_hw_nand_delay(10);
-            
-            data =(rt_uint8_t*)&ecc_rdbuf[0]; 
+
+            data =(rt_uint8_t*)&ecc_rdbuf[0];
             for (i = 0; i < 4*eccnum; i++)
             {
                 *data++ = NAND_ADDR_AREA;
-            }		
+            }
             /* check ecc */
             for(i  = 0;  i< eccnum; i++)
             {
@@ -336,10 +336,10 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
                     {
                         goto _exit;
                     }
-                } 
+                }
             }
         }
-    }    
+    }
     if (spare && spare_len)
     {
         NAND_CMD_AREA  = NAND_AREA_A;
@@ -356,7 +356,7 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device,
             *spare++ = NAND_ADDR_AREA;
         }
     }
-    
+
     if (rt_hw_nand_wait_ready() != RT_EOK)
     {
         result = RT_ETIMEOUT;
@@ -400,11 +400,11 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device,
         NAND_DATA_AREA = (rt_uint8_t)(page & 0xFF);
         NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
         NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
-        
+
         rt_hw_nand_delay(10);
-        
+
         if (data_len % NAND_ECC_SECTOR_SIZE)
-        { 
+        {
             /* read nand flash */
             for (i = 0; i < data_len; i++)
             {
@@ -413,15 +413,15 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device,
         }
         else
         {
-            eccnum   = data_len/NAND_ECC_SECTOR_SIZE;	
+            eccnum   = data_len/NAND_ECC_SECTOR_SIZE;
             for (index = 0; index < eccnum; index++)
             {
-                FMC_Bank3_R->PCR |= 1<<6;				/* enable ecc */ 
-                
-                for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)				
+                FMC_Bank3_R->PCR |= 1<<6;               /* enable ecc */
+
+                for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)
                 {
                     NAND_ADDR_AREA = *data++;
-                }		
+                }
                 /* Get tick */
                 tickstart = rt_tick_get();
                 /* Wait until FIFO is empty */
@@ -434,26 +434,26 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device,
                         goto _exit;
                     }
                 }
-                ecc_hdbuf[index] = FMC_Bank3_R->HECCR;	/* read hardware ecc */
-                FMC_Bank3_R->PCR &= ~(1<<6);			/* disable ecc */
+                ecc_hdbuf[index] = FMC_Bank3_R->HECCR;  /* read hardware ecc */
+                FMC_Bank3_R->PCR &= ~(1<<6);            /* disable ecc */
             }
-            
+
             i = device->page_size + 0x10;
             rt_hw_nand_delay(10);
             NAND_CMD_AREA  = 0x85;
             NAND_DATA_AREA = (rt_uint8_t)i;
             NAND_DATA_AREA = (rt_uint8_t)(i>>8);
             rt_hw_nand_delay(10);
-            
+
             data = (uint8_t*)&ecc_hdbuf[0];
 
-            for (index = 0; index < eccnum; index++)		
-            { 
-                for (i = 0; i < 4; i++)				 
+            for (index = 0; index < eccnum; index++)
+            {
+                for (i = 0; i < 4; i++)
                 {
                     NAND_ADDR_AREA = *data++;
                 }
-            }              
+            }
         }
     }
     NAND_CMD_AREA = NAND_WRITE_TURE1;
@@ -462,7 +462,7 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device,
         result = -RT_EIO;
         goto _exit;
     }
-        
+
     if (spare && spare_len)
     {
         NAND_CMD_AREA = NAND_WRITE0;
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h
index 609a5e2aae..094635ebfb 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c
index 30eb0e4ad7..da4d602a67 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -39,10 +39,10 @@ __no_init static rt_int32_t JPEG_DATA_BUF[JPEG_BUF_SIZE];
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 __attribute__((at(0x2FFDC000))) static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE];
 #elif defined(__GNUC__)
-static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]  __attribute__((section(".Dcmi1Section")));            
+static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]  __attribute__((section(".Dcmi1Section")));
 #elif defined(__ICCARM__)
 #pragma location = 0x2FFDC000
-__no_init static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; 
+__no_init static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE];
 #endif
 
 volatile rt_uint32_t jpeg_data_len = 0;
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h
index d005150482..d2daa32bd6 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h
@@ -1,6 +1,6 @@
 
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,9 +16,9 @@
 extern "C" {
 #endif
 
-/** 
-  * @brief  OV5640 ID  
-  */  
+/**
+  * @brief  OV5640 ID
+  */
 #define  OV5640_ID                                 0x5640U
 
 /* JPEG picture size table */
@@ -40,611 +40,611 @@ static const unsigned short jpeg_picture_size[][2] =
 
 /* camera light mode */
 static const unsigned char OV5640_LIGHTMODE_TBL[5][7]=
-{ 
-	0x04,0X00,0X04,0X00,0X04,0X00,0X00,     /* Auto */
-	0x06,0X1C,0X04,0X00,0X04,0XF3,0X01,     /* Sunny */
-	0x05,0X48,0X04,0X00,0X07,0XCF,0X01,     /* Office */
-	0x06,0X48,0X04,0X00,0X04,0XD3,0X01,     /* Cloudy */ 
-	0x04,0X10,0X04,0X00,0X08,0X40,0X01,     /* Home */
-}; 
+{
+    0x04,0X00,0X04,0X00,0X04,0X00,0X00,     /* Auto */
+    0x06,0X1C,0X04,0X00,0X04,0XF3,0X01,     /* Sunny */
+    0x05,0X48,0X04,0X00,0X07,0XCF,0X01,     /* Office */
+    0x06,0X48,0X04,0X00,0X04,0XD3,0X01,     /* Cloudy */
+    0x04,0X10,0X04,0X00,0X08,0X40,0X01,     /* Home */
+};
 
 /* Table of color saturation setting parameters */
 static const unsigned char OV5640_SATURATION_TBL[7][6]=
-{ 
-	0X0C,0x30,0X3D,0X3E,0X3D,0X01,      /* -3 */
-	0X10,0x3D,0X4D,0X4E,0X4D,0X01,      /* -2 */	
-	0X15,0x52,0X66,0X68,0X66,0X02,      /* -1 */	
-	0X1A,0x66,0X80,0X82,0X80,0X02,      /* 0 */	
-	0X1F,0x7A,0X9A,0X9C,0X9A,0X02,      /* 1 */	
-	0X24,0x8F,0XB3,0XB6,0XB3,0X03,      /* 2 */
- 	0X2B,0xAB,0XD6,0XDA,0XD6,0X04,      /* 3 */
+{
+    0X0C,0x30,0X3D,0X3E,0X3D,0X01,      /* -3 */
+    0X10,0x3D,0X4D,0X4E,0X4D,0X01,      /* -2 */
+    0X15,0x52,0X66,0X68,0X66,0X02,      /* -1 */
+    0X1A,0x66,0X80,0X82,0X80,0X02,      /* 0 */
+    0X1F,0x7A,0X9A,0X9C,0X9A,0X02,      /* 1 */
+    0X24,0x8F,0XB3,0XB6,0XB3,0X03,      /* 2 */
+    0X2B,0xAB,0XD6,0XDA,0XD6,0X04,      /* 3 */
 };
 
 static const unsigned short OV5640_jpeg_reg_tbl[][2]=
 {
-	0x4300, 0x30, // YUV 422, YUYV
-	0x501f, 0x00, // YUV 422
-	// Input clock = 24Mhz
-	0x3035, 0x21, // PLL  
-	0x3036, 0x69, // PLL 
-	0x3c07, 0x07, // lightmeter 1 threshold[7:0] 
-	0x3820, 0x46, // flip
-	0x3821, 0x20, // mirror									 
-	0x3814, 0x11, // timing X inc 
-	0x3815, 0x11, // timing Y inc 
-	0x3800, 0x00, // HS 
-	0x3801, 0x00, // HS 
-	0x3802, 0x00, // VS 
-	0x3803, 0x00, // VS 
-	0x3804, 0x0a, // HW (HE)		 
-	0x3805, 0x3f, // HW (HE)
-	0x3806, 0x07, // VH (VE)		 
-	0x3807, 0x9f, // VH (VE) 
-	
-	0x3808, 0x02, // DVPHO 	   
-	0x3809, 0x80, // DVPHO 
-	0x380a, 0x01, // DVPVO 		
-	0x380b, 0xe0, // DVPVO
+    0x4300, 0x30, // YUV 422, YUYV
+    0x501f, 0x00, // YUV 422
+    // Input clock = 24Mhz
+    0x3035, 0x21, // PLL
+    0x3036, 0x69, // PLL
+    0x3c07, 0x07, // lightmeter 1 threshold[7:0]
+    0x3820, 0x46, // flip
+    0x3821, 0x20, // mirror
+    0x3814, 0x11, // timing X inc
+    0x3815, 0x11, // timing Y inc
+    0x3800, 0x00, // HS
+    0x3801, 0x00, // HS
+    0x3802, 0x00, // VS
+    0x3803, 0x00, // VS
+    0x3804, 0x0a, // HW (HE)
+    0x3805, 0x3f, // HW (HE)
+    0x3806, 0x07, // VH (VE)
+    0x3807, 0x9f, // VH (VE)
 
-	0x380c, 0x0b, // HTS 		//
-	0x380d, 0x1c, // HTS 
-	0x380e, 0x07, // VTS 		//
-	0x380f, 0xb0, // VTS 
-	0x3813, 0x04, // timing V offset   04
-	0x3618, 0x04,
-	0x3612, 0x2b,
-	0x3709, 0x12,
-	0x370c, 0x00, 
-	
-	0x4004, 0x06, // BLC line number 
-	0x3002, 0x00, // enable JFIFO, SFIFO, JPG 
-	0x3006, 0xff, // enable clock of JPEG2x, JPEG
-	0x4713, 0x03, // JPEG mode 3
-	0x4407, 0x01, // Quantization sacle 
-	0x460b, 0x35,
-	0x460c, 0x22,
-	0x4837, 0x16, // MIPI global timing 
-	0x3824, 0x02, // PCLK manual divider 
-	0x5001, 0xA3, // SDE on, Scaling on, CMX on, AWB on 
-	0x3503, 0x00, // AEC/AGC on	
+    0x3808, 0x02, // DVPHO
+    0x3809, 0x80, // DVPHO
+    0x380a, 0x01, // DVPVO
+    0x380b, 0xe0, // DVPVO
+
+    0x380c, 0x0b, // HTS        //
+    0x380d, 0x1c, // HTS
+    0x380e, 0x07, // VTS        //
+    0x380f, 0xb0, // VTS
+    0x3813, 0x04, // timing V offset   04
+    0x3618, 0x04,
+    0x3612, 0x2b,
+    0x3709, 0x12,
+    0x370c, 0x00,
+
+    0x4004, 0x06, // BLC line number
+    0x3002, 0x00, // enable JFIFO, SFIFO, JPG
+    0x3006, 0xff, // enable clock of JPEG2x, JPEG
+    0x4713, 0x03, // JPEG mode 3
+    0x4407, 0x01, // Quantization sacle
+    0x460b, 0x35,
+    0x460c, 0x22,
+    0x4837, 0x16, // MIPI global timing
+    0x3824, 0x02, // PCLK manual divider
+    0x5001, 0xA3, // SDE on, Scaling on, CMX on, AWB on
+    0x3503, 0x00, // AEC/AGC on
 };
 
 /* RGB565 configuration, 15 frames */
 static const unsigned short ov5640_rgb565_reg_tbl[][2]=
 {
-	0x4300, 0X6F,
-	0X501F, 0x01,
-	// 1280x800, 15fps
-	// input clock 24Mhz, PCLK 42Mhz
-	0x3035, 0x41, // PLL
-	0x3036, 0x69, // PLL
-	0x3c07, 0x07, // lightmeter 1 threshold[7:0]
-	0x3820, 0x46, // flip
-	0x3821, 0x00, // mirror
-	0x3814, 0x31, // timing X inc
-	0x3815, 0x31, // timing Y inc
-	0x3800, 0x00, // HS
-	0x3801, 0x00, // HS
-	0x3802, 0x00, // VS
-	0x3803, 0x00, // VS
-	0x3804, 0x0a, // HW (HE)
-	0x3805, 0x3f, // HW (HE)
-	0x3806, 0x06, // VH (VE)
-	0x3807, 0xa9, // VH (VE)
-	0x3808, 0x05, // DVPHO
-	0x3809, 0x00, // DVPHO
-	0x380a, 0x02, // DVPVO
-	0x380b, 0xd0, // DVPVO
-	0x380c, 0x05, // HTS
-	0x380d, 0xF8, // HTS
-	0x380e, 0x03, // VTS
-	0x380f, 0x84, // VTS
-	0x3813, 0x04, // timing V offset
-	0x3618, 0x00,
-	0x3612, 0x29,
-	0x3709, 0x52,
-	0x370c, 0x03,
-	0x3a02, 0x02, // 60Hz max exposure
-	0x3a03, 0xe0, // 60Hz max exposure 
- 
-	0x3a14, 0x02, // 50Hz max exposure
-	0x3a15, 0xe0, // 50Hz max exposure
-	0x4004, 0x02, // BLC line number
-	0x3002, 0x1c, // reset JFIFO, SFIFO, JPG
-	0x3006, 0xc3, // disable clock of JPEG2x, JPEG
-	0x4713, 0x03, // JPEG mode 3
-	0x4407, 0x04, // Quantization scale
-	0x460b, 0x37,
-	0x460c, 0x20,
-	0x4837, 0x16, // MIPI global timing
-	0x3824, 0x04, // PCLK manual divider
-	0x5001, 0xA3, // SDE on, scale on, UV average off, color matrix on, AWB on
-	0x3503, 0x00, // AEC/AGC on
-}; 
+    0x4300, 0X6F,
+    0X501F, 0x01,
+    // 1280x800, 15fps
+    // input clock 24Mhz, PCLK 42Mhz
+    0x3035, 0x41, // PLL
+    0x3036, 0x69, // PLL
+    0x3c07, 0x07, // lightmeter 1 threshold[7:0]
+    0x3820, 0x46, // flip
+    0x3821, 0x00, // mirror
+    0x3814, 0x31, // timing X inc
+    0x3815, 0x31, // timing Y inc
+    0x3800, 0x00, // HS
+    0x3801, 0x00, // HS
+    0x3802, 0x00, // VS
+    0x3803, 0x00, // VS
+    0x3804, 0x0a, // HW (HE)
+    0x3805, 0x3f, // HW (HE)
+    0x3806, 0x06, // VH (VE)
+    0x3807, 0xa9, // VH (VE)
+    0x3808, 0x05, // DVPHO
+    0x3809, 0x00, // DVPHO
+    0x380a, 0x02, // DVPVO
+    0x380b, 0xd0, // DVPVO
+    0x380c, 0x05, // HTS
+    0x380d, 0xF8, // HTS
+    0x380e, 0x03, // VTS
+    0x380f, 0x84, // VTS
+    0x3813, 0x04, // timing V offset
+    0x3618, 0x00,
+    0x3612, 0x29,
+    0x3709, 0x52,
+    0x370c, 0x03,
+    0x3a02, 0x02, // 60Hz max exposure
+    0x3a03, 0xe0, // 60Hz max exposure
+
+    0x3a14, 0x02, // 50Hz max exposure
+    0x3a15, 0xe0, // 50Hz max exposure
+    0x4004, 0x02, // BLC line number
+    0x3002, 0x1c, // reset JFIFO, SFIFO, JPG
+    0x3006, 0xc3, // disable clock of JPEG2x, JPEG
+    0x4713, 0x03, // JPEG mode 3
+    0x4407, 0x04, // Quantization scale
+    0x460b, 0x37,
+    0x460c, 0x20,
+    0x4837, 0x16, // MIPI global timing
+    0x3824, 0x04, // PCLK manual divider
+    0x5001, 0xA3, // SDE on, scale on, UV average off, color matrix on, AWB on
+    0x3503, 0x00, // AEC/AGC on
+};
 
 static const unsigned short RGB565_Init[][2]=
-{ 
-	/* 24MHz input clock, 24MHz PCLK */
-	0x3008, 0x42, // software power down, bit[6]
-	0x3103, 0x03, // system clock from PLL, bit[1]
-	0x3017, 0xff, // FREX, Vsync, HREF, PCLK, D[9:6] output enable
-	0x3018, 0xff, // D[5:0], GPIO[1:0] output enable
-	0x3034, 0x1a, // MIPI 10-bit
-	0x3037, 0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0]
-	0x3108, 0x01, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2]
+{
+    /* 24MHz input clock, 24MHz PCLK */
+    0x3008, 0x42, // software power down, bit[6]
+    0x3103, 0x03, // system clock from PLL, bit[1]
+    0x3017, 0xff, // FREX, Vsync, HREF, PCLK, D[9:6] output enable
+    0x3018, 0xff, // D[5:0], GPIO[1:0] output enable
+    0x3034, 0x1a, // MIPI 10-bit
+    0x3037, 0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0]
+    0x3108, 0x01, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2]
 
-	// SCLK root divider, bit[1:0]
-	0x3630, 0x36,
-	0x3631, 0x0e,
-	0x3632, 0xe2,
-	0x3633, 0x12,
-	0x3621, 0xe0,
-	0x3704, 0xa0,
-	0x3703, 0x5a,
-	0x3715, 0x78,
-	0x3717, 0x01,
-	0x370b, 0x60,
-	0x3705, 0x1a,
-	0x3905, 0x02,
-	0x3906, 0x10,
-	0x3901, 0x0a,
-	0x3731, 0x12,
-	0x3600, 0x08, // VCM control
-	0x3601, 0x33, // VCM control
-	0x302d, 0x60, // system control
-	0x3620, 0x52,
-	0x371b, 0x20,
-	0x471c, 0x50,
-	0x3a13, 0x43, // pre-gain = 1.047x
-	0x3a18, 0x00, // gain ceiling
-	0x3a19, 0xf8, // gain ceiling = 15.5x
-	0x3635, 0x13,
-	0x3636, 0x03,
-	0x3634, 0x40,
-	0x3622, 0x01,
-	// 50/60Hz detection 50/60Hz
-	0x3c01, 0x34, // Band auto, bit[7]
-	0x3c04, 0x28, // threshold low sum
-	0x3c05, 0x98, // threshold high sum
-	0x3c06, 0x00, // light meter 1 threshold[15:8]
-	0x3c07, 0x08, // light meter 1 threshold[7:0]
-	0x3c08, 0x00, // light meter 2 threshold[15:8]
-	0x3c09, 0x1c, // light meter 2 threshold[7:0]
-	0x3c0a, 0x9c, // sample number[15:8]
-	0x3c0b, 0x40, // sample number[7:0]
-	0x3810, 0x00, // Timing Hoffset[11:8]
-	0x3811, 0x10, // Timing Hoffset[7:0]
-	0x3812, 0x00, // Timing Voffset[10:8]
-	0x3708, 0x64,
-	0x4001, 0x02, // BLC start from line 2
-	0x4005, 0x1a, // BLC always update
-	0x3000, 0x00, // enable blocks
-	0x3004, 0xff, // enable clocks
-	0x300e, 0x58, // MIPI power down, DVP enable
-	0x302e, 0x00,
-	0x4300, 0x30, // YUV 422, YUYV
-	0x501f, 0x00, // YUV 422
-	0x440e, 0x00,
-	0x5000, 0xa7, // Lenc on, raw gamma on, BPC on, WPC on, CIP on
-	// AEC target
-	0x3a0f, 0x30, // stable range in high
-	0x3a10, 0x28, // stable range in low
-	0x3a1b, 0x30, // stable range out high
-	0x3a1e, 0x26, // stable range out low
-	0x3a11, 0x60, // fast zone high
-	0x3a1f, 0x14, // fast zone low
-	// Lens correction
-	0x5800, 0x23,
-	0x5801, 0x14,
-	0x5802, 0x0f,
-	0x5803, 0x0f,
-	0x5804, 0x12,
-	0x5805, 0x26,
-	0x5806, 0x0c,
-	0x5807, 0x08,
-	0x5808, 0x05,
-	0x5809, 0x05,
-	0x580a, 0x08,
+    // SCLK root divider, bit[1:0]
+    0x3630, 0x36,
+    0x3631, 0x0e,
+    0x3632, 0xe2,
+    0x3633, 0x12,
+    0x3621, 0xe0,
+    0x3704, 0xa0,
+    0x3703, 0x5a,
+    0x3715, 0x78,
+    0x3717, 0x01,
+    0x370b, 0x60,
+    0x3705, 0x1a,
+    0x3905, 0x02,
+    0x3906, 0x10,
+    0x3901, 0x0a,
+    0x3731, 0x12,
+    0x3600, 0x08, // VCM control
+    0x3601, 0x33, // VCM control
+    0x302d, 0x60, // system control
+    0x3620, 0x52,
+    0x371b, 0x20,
+    0x471c, 0x50,
+    0x3a13, 0x43, // pre-gain = 1.047x
+    0x3a18, 0x00, // gain ceiling
+    0x3a19, 0xf8, // gain ceiling = 15.5x
+    0x3635, 0x13,
+    0x3636, 0x03,
+    0x3634, 0x40,
+    0x3622, 0x01,
+    // 50/60Hz detection 50/60Hz
+    0x3c01, 0x34, // Band auto, bit[7]
+    0x3c04, 0x28, // threshold low sum
+    0x3c05, 0x98, // threshold high sum
+    0x3c06, 0x00, // light meter 1 threshold[15:8]
+    0x3c07, 0x08, // light meter 1 threshold[7:0]
+    0x3c08, 0x00, // light meter 2 threshold[15:8]
+    0x3c09, 0x1c, // light meter 2 threshold[7:0]
+    0x3c0a, 0x9c, // sample number[15:8]
+    0x3c0b, 0x40, // sample number[7:0]
+    0x3810, 0x00, // Timing Hoffset[11:8]
+    0x3811, 0x10, // Timing Hoffset[7:0]
+    0x3812, 0x00, // Timing Voffset[10:8]
+    0x3708, 0x64,
+    0x4001, 0x02, // BLC start from line 2
+    0x4005, 0x1a, // BLC always update
+    0x3000, 0x00, // enable blocks
+    0x3004, 0xff, // enable clocks
+    0x300e, 0x58, // MIPI power down, DVP enable
+    0x302e, 0x00,
+    0x4300, 0x30, // YUV 422, YUYV
+    0x501f, 0x00, // YUV 422
+    0x440e, 0x00,
+    0x5000, 0xa7, // Lenc on, raw gamma on, BPC on, WPC on, CIP on
+    // AEC target
+    0x3a0f, 0x30, // stable range in high
+    0x3a10, 0x28, // stable range in low
+    0x3a1b, 0x30, // stable range out high
+    0x3a1e, 0x26, // stable range out low
+    0x3a11, 0x60, // fast zone high
+    0x3a1f, 0x14, // fast zone low
+    // Lens correction
+    0x5800, 0x23,
+    0x5801, 0x14,
+    0x5802, 0x0f,
+    0x5803, 0x0f,
+    0x5804, 0x12,
+    0x5805, 0x26,
+    0x5806, 0x0c,
+    0x5807, 0x08,
+    0x5808, 0x05,
+    0x5809, 0x05,
+    0x580a, 0x08,
 
-	0x580b, 0x0d,
-	0x580c, 0x08,
-	0x580d, 0x03,
-	0x580e, 0x00,
-	0x580f, 0x00,
-	0x5810, 0x03,
-	0x5811, 0x09,
-	0x5812, 0x07,
-	0x5813, 0x03,
-	0x5814, 0x00,
-	0x5815, 0x01,
-	0x5816, 0x03,
-	0x5817, 0x08,
-	0x5818, 0x0d,
-	0x5819, 0x08,
-	0x581a, 0x05,
-	0x581b, 0x06,
-	0x581c, 0x08,
-	0x581d, 0x0e,
-	0x581e, 0x29,
-	0x581f, 0x17,
-	0x5820, 0x11,
-	0x5821, 0x11,
-	0x5822, 0x15,
-	0x5823, 0x28,
-	0x5824, 0x46,
-	0x5825, 0x26,
-	0x5826, 0x08,
-	0x5827, 0x26,
-	0x5828, 0x64,
-	0x5829, 0x26,
-	0x582a, 0x24,
-	0x582b, 0x22,
-	0x582c, 0x24,
-	0x582d, 0x24,
-	0x582e, 0x06,
-	0x582f, 0x22,
-	0x5830, 0x40,
-	0x5831, 0x42,
-	0x5832, 0x24,
-	0x5833, 0x26,
-	0x5834, 0x24,
-	0x5835, 0x22,
-	0x5836, 0x22,
-	0x5837, 0x26,
-	0x5838, 0x44,
-	0x5839, 0x24,
-	0x583a, 0x26,
-	0x583b, 0x28,
-	0x583c, 0x42,
-	0x583d, 0xce, // lenc BR offset
-	// AWB
-	0x5180, 0xff, // AWB B block
-	0x5181, 0xf2, // AWB control
-	0x5182, 0x00, // [7:4] max local counter, [3:0] max fast counter
-	0x5183, 0x14, // AWB advanced
-	0x5184, 0x25,
-	0x5185, 0x24,
-	0x5186, 0x09,
-	0x5187, 0x09,
-	0x5188, 0x09,
-	0x5189, 0x75,
-	0x518a, 0x54,
-	0x518b, 0xe0,
-	0x518c, 0xb2,
-	0x518d, 0x42,
-	0x518e, 0x3d,
-	0x518f, 0x56,
-	0x5190, 0x46,
-	0x5191, 0xf8, // AWB top limit
-	0x5192, 0x04, // AWB bottom limit
-	0x5193, 0x70, // red limit
-	0x5194, 0xf0, // green limit
-	0x5195, 0xf0, // blue limit
-	0x5196, 0x03, // AWB control
-	0x5197, 0x01, // local limit
-	0x5198, 0x04,
-	0x5199, 0x12,
-	0x519a, 0x04,
-	0x519b, 0x00,
-	0x519c, 0x06,
-	0x519d, 0x82,
-	0x519e, 0x38, // AWB control
-	// Gamma
-	0x5480, 0x01, // Gamma bias plus on, bit[0]
-	0x5481, 0x08,
-	0x5482, 0x14,
-	0x5483, 0x28,
-	0x5484, 0x51,
-	0x5485, 0x65,
-	0x5486, 0x71,
-	0x5487, 0x7d,
-	0x5488, 0x87,
-	0x5489, 0x91,
-	0x548a, 0x9a,
-	0x548b, 0xaa,
-	0x548c, 0xb8,
-	0x548d, 0xcd,
-	0x548e, 0xdd,
-	0x548f, 0xea,
-	0x5490, 0x1d,
-	// color matrix
-	0x5381, 0x1e, // CMX1 for Y
-	0x5382, 0x5b, // CMX2 for Y
-	0x5383, 0x08, // CMX3 for Y
-	0x5384, 0x0a, // CMX4 for U
-	0x5385, 0x7e, // CMX5 for U
-	0x5386, 0x88, // CMX6 for U
-	0x5387, 0x7c, // CMX7 for V
-	0x5388, 0x6c, // CMX8 for V
-	0x5389, 0x10, // CMX9 for V
-	0x538a, 0x01, // sign[9]
-	0x538b, 0x98, // sign[8:1]
-	// UV adjust UV
-	0x5580, 0x06, // saturation on, bit[1]
-	0x5583, 0x40,
-	0x5584, 0x10, 
-	0x5589, 0x10,
-	0x558a, 0x00,
-	0x558b, 0xf8,
-	0x501d, 0x40, // enable manual offset of contrast
-	// CIP
-	0x5300, 0x08, // CIP sharpen MT threshold 1
-	0x5301, 0x30, // CIP sharpen MT threshold 2
-	0x5302, 0x10, // CIP sharpen MT offset 1
-	0x5303, 0x00, // CIP sharpen MT offset 2
-	0x5304, 0x08, // CIP DNS threshold 1
-	0x5305, 0x30, // CIP DNS threshold 2
-	0x5306, 0x08, // CIP DNS offset 1
-	0x5307, 0x16, // CIP DNS offset 2
-	0x5309, 0x08, // CIP sharpen TH threshold 1
-	0x530a, 0x30, // CIP sharpen TH threshold 2
-	0x530b, 0x04, // CIP sharpen TH offset 1
-	0x530c, 0x06, // CIP sharpen TH offset 2
-	0x5025, 0x00, 
-	0x3008, 0x02, // wake up from standby, bit[6]
+    0x580b, 0x0d,
+    0x580c, 0x08,
+    0x580d, 0x03,
+    0x580e, 0x00,
+    0x580f, 0x00,
+    0x5810, 0x03,
+    0x5811, 0x09,
+    0x5812, 0x07,
+    0x5813, 0x03,
+    0x5814, 0x00,
+    0x5815, 0x01,
+    0x5816, 0x03,
+    0x5817, 0x08,
+    0x5818, 0x0d,
+    0x5819, 0x08,
+    0x581a, 0x05,
+    0x581b, 0x06,
+    0x581c, 0x08,
+    0x581d, 0x0e,
+    0x581e, 0x29,
+    0x581f, 0x17,
+    0x5820, 0x11,
+    0x5821, 0x11,
+    0x5822, 0x15,
+    0x5823, 0x28,
+    0x5824, 0x46,
+    0x5825, 0x26,
+    0x5826, 0x08,
+    0x5827, 0x26,
+    0x5828, 0x64,
+    0x5829, 0x26,
+    0x582a, 0x24,
+    0x582b, 0x22,
+    0x582c, 0x24,
+    0x582d, 0x24,
+    0x582e, 0x06,
+    0x582f, 0x22,
+    0x5830, 0x40,
+    0x5831, 0x42,
+    0x5832, 0x24,
+    0x5833, 0x26,
+    0x5834, 0x24,
+    0x5835, 0x22,
+    0x5836, 0x22,
+    0x5837, 0x26,
+    0x5838, 0x44,
+    0x5839, 0x24,
+    0x583a, 0x26,
+    0x583b, 0x28,
+    0x583c, 0x42,
+    0x583d, 0xce, // lenc BR offset
+    // AWB
+    0x5180, 0xff, // AWB B block
+    0x5181, 0xf2, // AWB control
+    0x5182, 0x00, // [7:4] max local counter, [3:0] max fast counter
+    0x5183, 0x14, // AWB advanced
+    0x5184, 0x25,
+    0x5185, 0x24,
+    0x5186, 0x09,
+    0x5187, 0x09,
+    0x5188, 0x09,
+    0x5189, 0x75,
+    0x518a, 0x54,
+    0x518b, 0xe0,
+    0x518c, 0xb2,
+    0x518d, 0x42,
+    0x518e, 0x3d,
+    0x518f, 0x56,
+    0x5190, 0x46,
+    0x5191, 0xf8, // AWB top limit
+    0x5192, 0x04, // AWB bottom limit
+    0x5193, 0x70, // red limit
+    0x5194, 0xf0, // green limit
+    0x5195, 0xf0, // blue limit
+    0x5196, 0x03, // AWB control
+    0x5197, 0x01, // local limit
+    0x5198, 0x04,
+    0x5199, 0x12,
+    0x519a, 0x04,
+    0x519b, 0x00,
+    0x519c, 0x06,
+    0x519d, 0x82,
+    0x519e, 0x38, // AWB control
+    // Gamma
+    0x5480, 0x01, // Gamma bias plus on, bit[0]
+    0x5481, 0x08,
+    0x5482, 0x14,
+    0x5483, 0x28,
+    0x5484, 0x51,
+    0x5485, 0x65,
+    0x5486, 0x71,
+    0x5487, 0x7d,
+    0x5488, 0x87,
+    0x5489, 0x91,
+    0x548a, 0x9a,
+    0x548b, 0xaa,
+    0x548c, 0xb8,
+    0x548d, 0xcd,
+    0x548e, 0xdd,
+    0x548f, 0xea,
+    0x5490, 0x1d,
+    // color matrix
+    0x5381, 0x1e, // CMX1 for Y
+    0x5382, 0x5b, // CMX2 for Y
+    0x5383, 0x08, // CMX3 for Y
+    0x5384, 0x0a, // CMX4 for U
+    0x5385, 0x7e, // CMX5 for U
+    0x5386, 0x88, // CMX6 for U
+    0x5387, 0x7c, // CMX7 for V
+    0x5388, 0x6c, // CMX8 for V
+    0x5389, 0x10, // CMX9 for V
+    0x538a, 0x01, // sign[9]
+    0x538b, 0x98, // sign[8:1]
+    // UV adjust UV
+    0x5580, 0x06, // saturation on, bit[1]
+    0x5583, 0x40,
+    0x5584, 0x10,
+    0x5589, 0x10,
+    0x558a, 0x00,
+    0x558b, 0xf8,
+    0x501d, 0x40, // enable manual offset of contrast
+    // CIP
+    0x5300, 0x08, // CIP sharpen MT threshold 1
+    0x5301, 0x30, // CIP sharpen MT threshold 2
+    0x5302, 0x10, // CIP sharpen MT offset 1
+    0x5303, 0x00, // CIP sharpen MT offset 2
+    0x5304, 0x08, // CIP DNS threshold 1
+    0x5305, 0x30, // CIP DNS threshold 2
+    0x5306, 0x08, // CIP DNS offset 1
+    0x5307, 0x16, // CIP DNS offset 2
+    0x5309, 0x08, // CIP sharpen TH threshold 1
+    0x530a, 0x30, // CIP sharpen TH threshold 2
+    0x530b, 0x04, // CIP sharpen TH offset 1
+    0x530c, 0x06, // CIP sharpen TH offset 2
+    0x5025, 0x00,
+    0x3008, 0x02, // wake up from standby, bit[6]
 
-	0x4740, 0X21, //VSYNC 
-}; 
+    0x4740, 0X21, //VSYNC
+};
 
-/* Autofocus initialization configuration  */ 
+/* Autofocus initialization configuration  */
 const unsigned char OV5640_AF_Config[] =
 {
-	0x02, 0x0f, 0xd6, 0x02, 0x0a, 0x39, 0xc2, 0x01, 0x22, 0x22, 0x00, 0x02, 0x0f, 0xb2, 0xe5, 0x1f, //0x8000,
-	0x70, 0x72, 0xf5, 0x1e, 0xd2, 0x35, 0xff, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe4, 0xf6, 0x08, //0x8010,
-	0xf6, 0x0f, 0xbf, 0x34, 0xf2, 0x90, 0x0e, 0x93, 0xe4, 0x93, 0xff, 0xe5, 0x4b, 0xc3, 0x9f, 0x50, //0x8020,
-	0x04, 0x7f, 0x05, 0x80, 0x02, 0x7f, 0xfb, 0x78, 0xbd, 0xa6, 0x07, 0x12, 0x0f, 0x04, 0x40, 0x04, //0x8030,
-	0x7f, 0x03, 0x80, 0x02, 0x7f, 0x30, 0x78, 0xbc, 0xa6, 0x07, 0xe6, 0x18, 0xf6, 0x08, 0xe6, 0x78, //0x8040,
-	0xb9, 0xf6, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xbf, 0x76, 0x33, 0xe4, 0x08, 0xf6, 0x78, //0x8050,
-	0xb8, 0x76, 0x01, 0x75, 0x4a, 0x02, 0x78, 0xb6, 0xf6, 0x08, 0xf6, 0x74, 0xff, 0x78, 0xc1, 0xf6, //0x8060,
-	0x08, 0xf6, 0x75, 0x1f, 0x01, 0x78, 0xbc, 0xe6, 0x75, 0xf0, 0x05, 0xa4, 0xf5, 0x4b, 0x12, 0x0a, //0x8070,
-	0xff, 0xc2, 0x37, 0x22, 0x78, 0xb8, 0xe6, 0xd3, 0x94, 0x00, 0x40, 0x02, 0x16, 0x22, 0xe5, 0x1f, //0x8080,
-	0xb4, 0x05, 0x23, 0xe4, 0xf5, 0x1f, 0xc2, 0x01, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x78, //0x8090,
-	0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x90, 0x30, 0x28, 0xf0, //0x80a0,
-	0x75, 0x1e, 0x10, 0xd2, 0x35, 0x22, 0xe5, 0x4b, 0x75, 0xf0, 0x05, 0x84, 0x78, 0xbc, 0xf6, 0x90, //0x80b0,
-	0x0e, 0x8c, 0xe4, 0x93, 0xff, 0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x78, //0x80c0,
-	0xbc, 0xe6, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0xef, 0x12, 0x0f, 0x0b, //0x80d0,
-	0xd3, 0x78, 0xb7, 0x96, 0xee, 0x18, 0x96, 0x40, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xb9, 0xf6, 0x78, //0x80e0,
-	0xb6, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x8c, 0xe4, 0x93, 0x12, 0x0f, 0x0b, 0xc3, 0x78, //0x80f0,
-	0xc2, 0x96, 0xee, 0x18, 0x96, 0x50, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xc1, 0xa6, //0x8100,
-	0x06, 0x08, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xc3, 0x78, 0xc2, 0x96, 0xff, 0xee, //0x8110,
-	0x18, 0x96, 0x78, 0xc3, 0xf6, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x95, 0xe4, 0x18, 0x12, 0x0e, 0xe9, //0x8120,
-	0x40, 0x02, 0xd2, 0x37, 0x78, 0xbc, 0xe6, 0x08, 0x26, 0x08, 0xf6, 0xe5, 0x1f, 0x64, 0x01, 0x70, //0x8130,
-	0x4a, 0xe6, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xdf, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, 0x39, 0x12, //0x8140,
-	0x0f, 0x02, 0x40, 0x04, 0x7f, 0xfe, 0x80, 0x02, 0x7f, 0x02, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, //0x8150,
-	0xe6, 0x24, 0x03, 0x78, 0xbf, 0xf6, 0x78, 0xb9, 0xe6, 0x24, 0xfd, 0x78, 0xc0, 0xf6, 0x12, 0x0f, //0x8160,
-	0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8170,
-	0x07, 0x75, 0x1f, 0x02, 0x78, 0xb8, 0x76, 0x01, 0x02, 0x02, 0x4a, 0xe5, 0x1f, 0x64, 0x02, 0x60, //0x8180,
-	0x03, 0x02, 0x02, 0x2a, 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x08, //0x8190,
-	0x12, 0x0e, 0xda, 0x50, 0x03, 0x02, 0x02, 0x28, 0x12, 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xff, 0x80, //0x81a0,
-	0x02, 0x7f, 0x01, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, 0xe6, 0x04, 0x78, 0xbf, 0xf6, 0x78, 0xb9, //0x81b0,
-	0xe6, 0x14, 0x78, 0xc0, 0xf6, 0x18, 0x12, 0x0f, 0x04, 0x40, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, //0x81c0,
-	0x00, 0x78, 0xbf, 0xa6, 0x07, 0xd3, 0x08, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x40, 0x04, 0xe6, 0xff, //0x81d0,
-	0x80, 0x02, 0x7f, 0x00, 0x78, 0xc0, 0xa6, 0x07, 0xc3, 0x18, 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, //0x81e0,
-	0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbf, 0xa6, 0x07, 0xc3, 0x08, 0xe6, 0x64, 0x80, //0x81f0,
-	0x94, 0xb3, 0x50, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xc0, 0xa6, 0x07, 0x12, 0x0f, //0x8200,
-	0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8210,
-	0x07, 0x75, 0x1f, 0x03, 0x78, 0xb8, 0x76, 0x01, 0x80, 0x20, 0xe5, 0x1f, 0x64, 0x03, 0x70, 0x26, //0x8220,
-	0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, //0x8230,
-	0x09, 0x78, 0xb9, 0xe6, 0x78, 0xbe, 0xf6, 0x75, 0x1f, 0x04, 0x78, 0xbe, 0xe6, 0x75, 0xf0, 0x05, //0x8240,
-	0xa4, 0xf5, 0x4b, 0x02, 0x0a, 0xff, 0xe5, 0x1f, 0xb4, 0x04, 0x10, 0x90, 0x0e, 0x94, 0xe4, 0x78, //0x8250,
-	0xc3, 0x12, 0x0e, 0xe9, 0x40, 0x02, 0xd2, 0x37, 0x75, 0x1f, 0x05, 0x22, 0x30, 0x01, 0x03, 0x02, //0x8260,
-	0x04, 0xc0, 0x30, 0x02, 0x03, 0x02, 0x04, 0xc0, 0x90, 0x51, 0xa5, 0xe0, 0x78, 0x93, 0xf6, 0xa3, //0x8270,
-	0xe0, 0x08, 0xf6, 0xa3, 0xe0, 0x08, 0xf6, 0xe5, 0x1f, 0x70, 0x3c, 0x75, 0x1e, 0x20, 0xd2, 0x35, //0x8280,
-	0x12, 0x0c, 0x7a, 0x78, 0x7e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xa6, 0x09, 0x18, 0x76, //0x8290,
-	0x01, 0x12, 0x0c, 0x5b, 0x78, 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xe6, 0x78, 0x6e, //0x82a0,
-	0xf6, 0x75, 0x1f, 0x01, 0x78, 0x93, 0xe6, 0x78, 0x90, 0xf6, 0x78, 0x94, 0xe6, 0x78, 0x91, 0xf6, //0x82b0,
-	0x78, 0x95, 0xe6, 0x78, 0x92, 0xf6, 0x22, 0x79, 0x90, 0xe7, 0xd3, 0x78, 0x93, 0x96, 0x40, 0x05, //0x82c0,
-	0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x93, 0xe7, 0x78, 0x90, 0x96, 0xff, 0x78, 0x88, 0x76, //0x82d0,
-	0x00, 0x08, 0xa6, 0x07, 0x79, 0x91, 0xe7, 0xd3, 0x78, 0x94, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, //0x82e0,
-	0x80, 0x08, 0xc3, 0x79, 0x94, 0xe7, 0x78, 0x91, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x79, 0x92, 0xe7, //0x82f0,
-	0xd3, 0x78, 0x95, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x95, 0xe7, 0x78, //0x8300,
-	0x92, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x12, 0x0c, 0x5b, 0x78, 0x8a, 0xe6, 0x25, 0xe0, 0x24, 0x4e, //0x8310,
-	0xf8, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8a, 0xe6, 0x24, 0x6e, 0xf8, 0xa6, 0x09, 0x78, 0x8a, //0x8320,
-	0xe6, 0x24, 0x01, 0xff, 0xe4, 0x33, 0xfe, 0xd3, 0xef, 0x94, 0x0f, 0xee, 0x64, 0x80, 0x94, 0x80, //0x8330,
-	0x40, 0x04, 0x7f, 0x00, 0x80, 0x05, 0x78, 0x8a, 0xe6, 0x04, 0xff, 0x78, 0x8a, 0xa6, 0x07, 0xe5, //0x8340,
-	0x1f, 0xb4, 0x01, 0x0a, 0xe6, 0x60, 0x03, 0x02, 0x04, 0xc0, 0x75, 0x1f, 0x02, 0x22, 0x12, 0x0c, //0x8350,
-	0x7a, 0x78, 0x80, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x12, 0x0c, 0x7a, 0x78, 0x82, 0xa6, 0x06, 0x08, //0x8360,
-	0xa6, 0x07, 0x78, 0x6e, 0xe6, 0x78, 0x8c, 0xf6, 0x78, 0x6e, 0xe6, 0x78, 0x8d, 0xf6, 0x7f, 0x01, //0x8370,
-	0xef, 0x25, 0xe0, 0x24, 0x4f, 0xf9, 0xc3, 0x78, 0x81, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x50, //0x8380,
-	0x0a, 0x12, 0x0c, 0x82, 0x78, 0x80, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, //0x8390,
-	0x8c, 0xe6, 0xc3, 0x97, 0x50, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8c, 0xf6, 0xef, 0x25, //0x83a0,
-	0xe0, 0x24, 0x4f, 0xf9, 0xd3, 0x78, 0x83, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x40, 0x0a, 0x12, //0x83b0,
-	0x0c, 0x82, 0x78, 0x82, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, 0x8d, 0xe6, //0x83c0,
-	0xd3, 0x97, 0x40, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8d, 0xf6, 0x0f, 0xef, 0x64, 0x10, //0x83d0,
-	0x70, 0x9e, 0xc3, 0x79, 0x81, 0xe7, 0x78, 0x83, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0x78, 0x84, //0x83e0,
-	0xf6, 0x08, 0xa6, 0x07, 0xc3, 0x79, 0x8c, 0xe7, 0x78, 0x8d, 0x96, 0x08, 0xf6, 0xd3, 0x79, 0x81, //0x83f0,
-	0xe7, 0x78, 0x7f, 0x96, 0x19, 0xe7, 0x18, 0x96, 0x40, 0x05, 0x09, 0xe7, 0x08, 0x80, 0x06, 0xc3, //0x8400,
-	0x79, 0x7f, 0xe7, 0x78, 0x81, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0xfe, 0x78, 0x86, 0xa6, 0x06, //0x8410,
-	0x08, 0xa6, 0x07, 0x79, 0x8c, 0xe7, 0xd3, 0x78, 0x8b, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, //0x8420,
-	0x08, 0xc3, 0x79, 0x8b, 0xe7, 0x78, 0x8c, 0x96, 0xff, 0x78, 0x8f, 0xa6, 0x07, 0xe5, 0x1f, 0x64, //0x8430,
-	0x02, 0x70, 0x69, 0x90, 0x0e, 0x91, 0x93, 0xff, 0x18, 0xe6, 0xc3, 0x9f, 0x50, 0x72, 0x12, 0x0c, //0x8440,
-	0x4a, 0x12, 0x0c, 0x2f, 0x90, 0x0e, 0x8e, 0x12, 0x0c, 0x38, 0x78, 0x80, 0x12, 0x0c, 0x6b, 0x7b, //0x8450,
-	0x04, 0x12, 0x0c, 0x1d, 0xc3, 0x12, 0x06, 0x45, 0x50, 0x56, 0x90, 0x0e, 0x92, 0xe4, 0x93, 0xff, //0x8460,
-	0x78, 0x8f, 0xe6, 0x9f, 0x40, 0x02, 0x80, 0x11, 0x90, 0x0e, 0x90, 0xe4, 0x93, 0xff, 0xd3, 0x78, //0x8470,
-	0x89, 0xe6, 0x9f, 0x18, 0xe6, 0x94, 0x00, 0x40, 0x03, 0x75, 0x1f, 0x05, 0x12, 0x0c, 0x4a, 0x12, //0x8480,
-	0x0c, 0x2f, 0x90, 0x0e, 0x8f, 0x12, 0x0c, 0x38, 0x78, 0x7e, 0x12, 0x0c, 0x6b, 0x7b, 0x40, 0x12, //0x8490,
-	0x0c, 0x1d, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x18, 0x75, 0x1f, 0x05, 0x22, 0xe5, 0x1f, 0xb4, 0x05, //0x84a0,
-	0x0f, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0xd2, 0x36, //0x84b0,
-	0x22, 0xef, 0x8d, 0xf0, 0xa4, 0xa8, 0xf0, 0xcf, 0x8c, 0xf0, 0xa4, 0x28, 0xce, 0x8d, 0xf0, 0xa4, //0x84c0,
-	0x2e, 0xfe, 0x22, 0xbc, 0x00, 0x0b, 0xbe, 0x00, 0x29, 0xef, 0x8d, 0xf0, 0x84, 0xff, 0xad, 0xf0, //0x84d0,
-	0x22, 0xe4, 0xcc, 0xf8, 0x75, 0xf0, 0x08, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xec, 0x33, 0xfc, //0x84e0,
-	0xee, 0x9d, 0xec, 0x98, 0x40, 0x05, 0xfc, 0xee, 0x9d, 0xfe, 0x0f, 0xd5, 0xf0, 0xe9, 0xe4, 0xce, //0x84f0,
-	0xfd, 0x22, 0xed, 0xf8, 0xf5, 0xf0, 0xee, 0x84, 0x20, 0xd2, 0x1c, 0xfe, 0xad, 0xf0, 0x75, 0xf0, //0x8500,
-	0x08, 0xef, 0x2f, 0xff, 0xed, 0x33, 0xfd, 0x40, 0x07, 0x98, 0x50, 0x06, 0xd5, 0xf0, 0xf2, 0x22, //0x8510,
-	0xc3, 0x98, 0xfd, 0x0f, 0xd5, 0xf0, 0xea, 0x22, 0xe8, 0x8f, 0xf0, 0xa4, 0xcc, 0x8b, 0xf0, 0xa4, //0x8520,
-	0x2c, 0xfc, 0xe9, 0x8e, 0xf0, 0xa4, 0x2c, 0xfc, 0x8a, 0xf0, 0xed, 0xa4, 0x2c, 0xfc, 0xea, 0x8e, //0x8530,
-	0xf0, 0xa4, 0xcd, 0xa8, 0xf0, 0x8b, 0xf0, 0xa4, 0x2d, 0xcc, 0x38, 0x25, 0xf0, 0xfd, 0xe9, 0x8f, //0x8540,
-	0xf0, 0xa4, 0x2c, 0xcd, 0x35, 0xf0, 0xfc, 0xeb, 0x8e, 0xf0, 0xa4, 0xfe, 0xa9, 0xf0, 0xeb, 0x8f, //0x8550,
-	0xf0, 0xa4, 0xcf, 0xc5, 0xf0, 0x2e, 0xcd, 0x39, 0xfe, 0xe4, 0x3c, 0xfc, 0xea, 0xa4, 0x2d, 0xce, //0x8560,
-	0x35, 0xf0, 0xfd, 0xe4, 0x3c, 0xfc, 0x22, 0x75, 0xf0, 0x08, 0x75, 0x82, 0x00, 0xef, 0x2f, 0xff, //0x8570,
-	0xee, 0x33, 0xfe, 0xcd, 0x33, 0xcd, 0xcc, 0x33, 0xcc, 0xc5, 0x82, 0x33, 0xc5, 0x82, 0x9b, 0xed, //0x8580,
-	0x9a, 0xec, 0x99, 0xe5, 0x82, 0x98, 0x40, 0x0c, 0xf5, 0x82, 0xee, 0x9b, 0xfe, 0xed, 0x9a, 0xfd, //0x8590,
-	0xec, 0x99, 0xfc, 0x0f, 0xd5, 0xf0, 0xd6, 0xe4, 0xce, 0xfb, 0xe4, 0xcd, 0xfa, 0xe4, 0xcc, 0xf9, //0x85a0,
-	0xa8, 0x82, 0x22, 0xb8, 0x00, 0xc1, 0xb9, 0x00, 0x59, 0xba, 0x00, 0x2d, 0xec, 0x8b, 0xf0, 0x84, //0x85b0,
-	0xcf, 0xce, 0xcd, 0xfc, 0xe5, 0xf0, 0xcb, 0xf9, 0x78, 0x18, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, //0x85c0,
-	0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xeb, 0x33, 0xfb, 0x10, 0xd7, 0x03, 0x99, 0x40, 0x04, 0xeb, //0x85d0,
-	0x99, 0xfb, 0x0f, 0xd8, 0xe5, 0xe4, 0xf9, 0xfa, 0x22, 0x78, 0x18, 0xef, 0x2f, 0xff, 0xee, 0x33, //0x85e0,
-	0xfe, 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xc9, 0x33, 0xc9, 0x10, 0xd7, 0x05, 0x9b, 0xe9, 0x9a, //0x85f0,
-	0x40, 0x07, 0xec, 0x9b, 0xfc, 0xe9, 0x9a, 0xf9, 0x0f, 0xd8, 0xe0, 0xe4, 0xc9, 0xfa, 0xe4, 0xcc, //0x8600,
-	0xfb, 0x22, 0x75, 0xf0, 0x10, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd, 0xcc, 0x33, //0x8610,
-	0xcc, 0xc8, 0x33, 0xc8, 0x10, 0xd7, 0x07, 0x9b, 0xec, 0x9a, 0xe8, 0x99, 0x40, 0x0a, 0xed, 0x9b, //0x8620,
-	0xfd, 0xec, 0x9a, 0xfc, 0xe8, 0x99, 0xf8, 0x0f, 0xd5, 0xf0, 0xda, 0xe4, 0xcd, 0xfb, 0xe4, 0xcc, //0x8630,
-	0xfa, 0xe4, 0xc8, 0xf9, 0x22, 0xeb, 0x9f, 0xf5, 0xf0, 0xea, 0x9e, 0x42, 0xf0, 0xe9, 0x9d, 0x42, //0x8640,
-	0xf0, 0xe8, 0x9c, 0x45, 0xf0, 0x22, 0xe8, 0x60, 0x0f, 0xec, 0xc3, 0x13, 0xfc, 0xed, 0x13, 0xfd, //0x8650,
-	0xee, 0x13, 0xfe, 0xef, 0x13, 0xff, 0xd8, 0xf1, 0x22, 0xe8, 0x60, 0x0f, 0xef, 0xc3, 0x33, 0xff, //0x8660,
-	0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xd8, 0xf1, 0x22, 0xe4, 0x93, 0xfc, 0x74, //0x8670,
-	0x01, 0x93, 0xfd, 0x74, 0x02, 0x93, 0xfe, 0x74, 0x03, 0x93, 0xff, 0x22, 0xe6, 0xfb, 0x08, 0xe6, //0x8680,
-	0xf9, 0x08, 0xe6, 0xfa, 0x08, 0xe6, 0xcb, 0xf8, 0x22, 0xec, 0xf6, 0x08, 0xed, 0xf6, 0x08, 0xee, //0x8690,
-	0xf6, 0x08, 0xef, 0xf6, 0x22, 0xa4, 0x25, 0x82, 0xf5, 0x82, 0xe5, 0xf0, 0x35, 0x83, 0xf5, 0x83, //0x86a0,
-	0x22, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3, //0x86b0,
-	0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82, 0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68, //0x86c0,
-	0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0x90, 0x38, 0x04, 0x78, 0x52, 0x12, 0x0b, 0xfd, 0x90, //0x86d0,
-	0x38, 0x00, 0xe0, 0xfe, 0xa3, 0xe0, 0xfd, 0xed, 0xff, 0xc3, 0x12, 0x0b, 0x9e, 0x90, 0x38, 0x10, //0x86e0,
-	0x12, 0x0b, 0x92, 0x90, 0x38, 0x06, 0x78, 0x54, 0x12, 0x0b, 0xfd, 0x90, 0x38, 0x02, 0xe0, 0xfe, //0x86f0,
-	0xa3, 0xe0, 0xfd, 0xed, 0xff, 0xc3, 0x12, 0x0b, 0x9e, 0x90, 0x38, 0x12, 0x12, 0x0b, 0x92, 0xa3, //0x8700,
-	0xe0, 0xb4, 0x31, 0x07, 0x78, 0x52, 0x79, 0x52, 0x12, 0x0c, 0x13, 0x90, 0x38, 0x14, 0xe0, 0xb4, //0x8710,
-	0x71, 0x15, 0x78, 0x52, 0xe6, 0xfe, 0x08, 0xe6, 0x78, 0x02, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, //0x8720,
-	0xf9, 0x79, 0x53, 0xf7, 0xee, 0x19, 0xf7, 0x90, 0x38, 0x15, 0xe0, 0xb4, 0x31, 0x07, 0x78, 0x54, //0x8730,
-	0x79, 0x54, 0x12, 0x0c, 0x13, 0x90, 0x38, 0x15, 0xe0, 0xb4, 0x71, 0x15, 0x78, 0x54, 0xe6, 0xfe, //0x8740,
-	0x08, 0xe6, 0x78, 0x02, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0x79, 0x55, 0xf7, 0xee, 0x19, //0x8750,
-	0xf7, 0x79, 0x52, 0x12, 0x0b, 0xd9, 0x09, 0x12, 0x0b, 0xd9, 0xaf, 0x47, 0x12, 0x0b, 0xb2, 0xe5, //0x8760,
-	0x44, 0xfb, 0x7a, 0x00, 0xfd, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x5a, 0xa6, 0x06, 0x08, 0xa6, //0x8770,
-	0x07, 0xaf, 0x45, 0x12, 0x0b, 0xb2, 0xad, 0x03, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x56, 0xa6, //0x8780,
-	0x06, 0x08, 0xa6, 0x07, 0xaf, 0x48, 0x78, 0x54, 0x12, 0x0b, 0xb4, 0xe5, 0x43, 0xfb, 0xfd, 0x7c, //0x8790,
-	0x00, 0x12, 0x04, 0xd3, 0x78, 0x5c, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xaf, 0x46, 0x7e, 0x00, 0x78, //0x87a0,
-	0x54, 0x12, 0x0b, 0xb6, 0xad, 0x03, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x58, 0xa6, 0x06, 0x08, //0x87b0,
-	0xa6, 0x07, 0xc3, 0x78, 0x5b, 0xe6, 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05, 0x76, 0x00, //0x87c0,
-	0x08, 0x76, 0x08, 0xc3, 0x78, 0x5d, 0xe6, 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05, 0x76, //0x87d0,
-	0x00, 0x08, 0x76, 0x08, 0x78, 0x5a, 0x12, 0x0b, 0xc6, 0xff, 0xd3, 0x78, 0x57, 0xe6, 0x9f, 0x18, //0x87e0,
-	0xe6, 0x9e, 0x40, 0x0e, 0x78, 0x5a, 0xe6, 0x13, 0xfe, 0x08, 0xe6, 0x78, 0x57, 0x12, 0x0c, 0x08, //0x87f0,
-	0x80, 0x04, 0x7e, 0x00, 0x7f, 0x00, 0x78, 0x5e, 0x12, 0x0b, 0xbe, 0xff, 0xd3, 0x78, 0x59, 0xe6, //0x8800,
-	0x9f, 0x18, 0xe6, 0x9e, 0x40, 0x0e, 0x78, 0x5c, 0xe6, 0x13, 0xfe, 0x08, 0xe6, 0x78, 0x59, 0x12, //0x8810,
-	0x0c, 0x08, 0x80, 0x04, 0x7e, 0x00, 0x7f, 0x00, 0xe4, 0xfc, 0xfd, 0x78, 0x62, 0x12, 0x06, 0x99, //0x8820,
-	0x78, 0x5a, 0x12, 0x0b, 0xc6, 0x78, 0x57, 0x26, 0xff, 0xee, 0x18, 0x36, 0xfe, 0x78, 0x66, 0x12, //0x8830,
-	0x0b, 0xbe, 0x78, 0x59, 0x26, 0xff, 0xee, 0x18, 0x36, 0xfe, 0xe4, 0xfc, 0xfd, 0x78, 0x6a, 0x12, //0x8840,
-	0x06, 0x99, 0x12, 0x0b, 0xce, 0x78, 0x66, 0x12, 0x06, 0x8c, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x08, //0x8850,
-	0x12, 0x0b, 0xce, 0x78, 0x66, 0x12, 0x06, 0x99, 0x78, 0x54, 0x12, 0x0b, 0xd0, 0x78, 0x6a, 0x12, //0x8860,
-	0x06, 0x8c, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x0a, 0x78, 0x54, 0x12, 0x0b, 0xd0, 0x78, 0x6a, 0x12, //0x8870,
-	0x06, 0x99, 0x78, 0x61, 0xe6, 0x90, 0x60, 0x01, 0xf0, 0x78, 0x65, 0xe6, 0xa3, 0xf0, 0x78, 0x69, //0x8880,
-	0xe6, 0xa3, 0xf0, 0x78, 0x55, 0xe6, 0xa3, 0xf0, 0x7d, 0x01, 0x78, 0x61, 0x12, 0x0b, 0xe9, 0x24, //0x8890,
-	0x01, 0x12, 0x0b, 0xa6, 0x78, 0x65, 0x12, 0x0b, 0xe9, 0x24, 0x02, 0x12, 0x0b, 0xa6, 0x78, 0x69, //0x88a0,
-	0x12, 0x0b, 0xe9, 0x24, 0x03, 0x12, 0x0b, 0xa6, 0x78, 0x6d, 0x12, 0x0b, 0xe9, 0x24, 0x04, 0x12, //0x88b0,
-	0x0b, 0xa6, 0x0d, 0xbd, 0x05, 0xd4, 0xc2, 0x0e, 0xc2, 0x06, 0x22, 0x85, 0x08, 0x41, 0x90, 0x30, //0x88c0,
-	0x24, 0xe0, 0xf5, 0x3d, 0xa3, 0xe0, 0xf5, 0x3e, 0xa3, 0xe0, 0xf5, 0x3f, 0xa3, 0xe0, 0xf5, 0x40, //0x88d0,
-	0xa3, 0xe0, 0xf5, 0x3c, 0xd2, 0x34, 0xe5, 0x41, 0x12, 0x06, 0xb1, 0x09, 0x31, 0x03, 0x09, 0x35, //0x88e0,
-	0x04, 0x09, 0x3b, 0x05, 0x09, 0x3e, 0x06, 0x09, 0x41, 0x07, 0x09, 0x4a, 0x08, 0x09, 0x5b, 0x12, //0x88f0,
-	0x09, 0x73, 0x18, 0x09, 0x89, 0x19, 0x09, 0x5e, 0x1a, 0x09, 0x6a, 0x1b, 0x09, 0xad, 0x80, 0x09, //0x8900,
-	0xb2, 0x81, 0x0a, 0x1d, 0x8f, 0x0a, 0x09, 0x90, 0x0a, 0x1d, 0x91, 0x0a, 0x1d, 0x92, 0x0a, 0x1d, //0x8910,
-	0x93, 0x0a, 0x1d, 0x94, 0x0a, 0x1d, 0x98, 0x0a, 0x17, 0x9f, 0x0a, 0x1a, 0xec, 0x00, 0x00, 0x0a, //0x8920,
-	0x38, 0x12, 0x0f, 0x74, 0x22, 0x12, 0x0f, 0x74, 0xd2, 0x03, 0x22, 0xd2, 0x03, 0x22, 0xc2, 0x03, //0x8930,
-	0x22, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x02, 0x0a, 0x1d, 0xc2, 0x01, 0xc2, 0x02, 0xc2, 0x03, //0x8940,
-	0x12, 0x0d, 0x0d, 0x75, 0x1e, 0x70, 0xd2, 0x35, 0x02, 0x0a, 0x1d, 0x02, 0x0a, 0x04, 0x85, 0x40, //0x8950,
-	0x4a, 0x85, 0x3c, 0x4b, 0x12, 0x0a, 0xff, 0x02, 0x0a, 0x1d, 0x85, 0x4a, 0x40, 0x85, 0x4b, 0x3c, //0x8960,
-	0x02, 0x0a, 0x1d, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x85, 0x40, 0x31, 0x85, 0x3f, 0x30, 0x85, 0x3e, //0x8970,
-	0x2f, 0x85, 0x3d, 0x2e, 0x12, 0x0f, 0x46, 0x80, 0x1f, 0x75, 0x22, 0x00, 0x75, 0x23, 0x01, 0x74, //0x8980,
-	0xff, 0xf5, 0x2d, 0xf5, 0x2c, 0xf5, 0x2b, 0xf5, 0x2a, 0x12, 0x0f, 0x46, 0x85, 0x2d, 0x40, 0x85, //0x8990,
-	0x2c, 0x3f, 0x85, 0x2b, 0x3e, 0x85, 0x2a, 0x3d, 0xe4, 0xf5, 0x3c, 0x80, 0x70, 0x12, 0x0f, 0x16, //0x89a0,
-	0x80, 0x6b, 0x85, 0x3d, 0x45, 0x85, 0x3e, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xe5, 0x45, 0xc3, //0x89b0,
-	0x9f, 0x50, 0x02, 0x8f, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, 0xe5, 0x46, 0xc3, 0x9f, 0x50, 0x02, //0x89c0,
-	0x8f, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xfd, 0xe5, 0x45, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, //0x89d0,
-	0x44, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, 0x44, 0x9f, 0xf5, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, //0x89e0,
-	0xfd, 0xe5, 0x46, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, 0x43, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, //0x89f0,
-	0x43, 0x9f, 0xf5, 0x46, 0x12, 0x06, 0xd7, 0x80, 0x14, 0x85, 0x40, 0x48, 0x85, 0x3f, 0x47, 0x85, //0x8a00,
-	0x3e, 0x46, 0x85, 0x3d, 0x45, 0x80, 0x06, 0x02, 0x06, 0xd7, 0x12, 0x0d, 0x7e, 0x90, 0x30, 0x24, //0x8a10,
-	0xe5, 0x3d, 0xf0, 0xa3, 0xe5, 0x3e, 0xf0, 0xa3, 0xe5, 0x3f, 0xf0, 0xa3, 0xe5, 0x40, 0xf0, 0xa3, //0x8a20,
-	0xe5, 0x3c, 0xf0, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0xc0, //0x8a30,
-	0xd0, 0x90, 0x3f, 0x0c, 0xe0, 0xf5, 0x32, 0xe5, 0x32, 0x30, 0xe3, 0x74, 0x30, 0x36, 0x66, 0x90, //0x8a40,
-	0x60, 0x19, 0xe0, 0xf5, 0x0a, 0xa3, 0xe0, 0xf5, 0x0b, 0x90, 0x60, 0x1d, 0xe0, 0xf5, 0x14, 0xa3, //0x8a50,
-	0xe0, 0xf5, 0x15, 0x90, 0x60, 0x21, 0xe0, 0xf5, 0x0c, 0xa3, 0xe0, 0xf5, 0x0d, 0x90, 0x60, 0x29, //0x8a60,
-	0xe0, 0xf5, 0x0e, 0xa3, 0xe0, 0xf5, 0x0f, 0x90, 0x60, 0x31, 0xe0, 0xf5, 0x10, 0xa3, 0xe0, 0xf5, //0x8a70,
-	0x11, 0x90, 0x60, 0x39, 0xe0, 0xf5, 0x12, 0xa3, 0xe0, 0xf5, 0x13, 0x30, 0x01, 0x06, 0x30, 0x33, //0x8a80,
-	0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x09, 0x30, 0x02, 0x06, 0x30, 0x33, 0x03, 0xd3, 0x80, 0x01, //0x8a90,
-	0xc3, 0x92, 0x0a, 0x30, 0x33, 0x0c, 0x30, 0x03, 0x09, 0x20, 0x02, 0x06, 0x20, 0x01, 0x03, 0xd3, //0x8aa0,
-	0x80, 0x01, 0xc3, 0x92, 0x0b, 0x90, 0x30, 0x01, 0xe0, 0x44, 0x40, 0xf0, 0xe0, 0x54, 0xbf, 0xf0, //0x8ab0,
-	0xe5, 0x32, 0x30, 0xe1, 0x14, 0x30, 0x34, 0x11, 0x90, 0x30, 0x22, 0xe0, 0xf5, 0x08, 0xe4, 0xf0, //0x8ac0,
-	0x30, 0x00, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x08, 0xe5, 0x32, 0x30, 0xe5, 0x12, 0x90, 0x56, //0x8ad0,
-	0xa1, 0xe0, 0xf5, 0x09, 0x30, 0x31, 0x09, 0x30, 0x05, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x0d, //0x8ae0,
-	0x90, 0x3f, 0x0c, 0xe5, 0x32, 0xf0, 0xd0, 0xd0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, //0x8af0,
-	0x0e, 0x7e, 0xe4, 0x93, 0xfe, 0x74, 0x01, 0x93, 0xff, 0xc3, 0x90, 0x0e, 0x7c, 0x74, 0x01, 0x93, //0x8b00,
-	0x9f, 0xff, 0xe4, 0x93, 0x9e, 0xfe, 0xe4, 0x8f, 0x3b, 0x8e, 0x3a, 0xf5, 0x39, 0xf5, 0x38, 0xab, //0x8b10,
-	0x3b, 0xaa, 0x3a, 0xa9, 0x39, 0xa8, 0x38, 0xaf, 0x4b, 0xfc, 0xfd, 0xfe, 0x12, 0x05, 0x28, 0x12, //0x8b20,
-	0x0d, 0xe1, 0xe4, 0x7b, 0xff, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0xb3, 0x12, 0x0d, 0xe1, 0x90, 0x0e, //0x8b30,
-	0x69, 0xe4, 0x12, 0x0d, 0xf6, 0x12, 0x0d, 0xe1, 0xe4, 0x85, 0x4a, 0x37, 0xf5, 0x36, 0xf5, 0x35, //0x8b40,
-	0xf5, 0x34, 0xaf, 0x37, 0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0xa3, 0x12, 0x0d, 0xf6, 0x8f, 0x37, //0x8b50,
-	0x8e, 0x36, 0x8d, 0x35, 0x8c, 0x34, 0xe5, 0x3b, 0x45, 0x37, 0xf5, 0x3b, 0xe5, 0x3a, 0x45, 0x36, //0x8b60,
-	0xf5, 0x3a, 0xe5, 0x39, 0x45, 0x35, 0xf5, 0x39, 0xe5, 0x38, 0x45, 0x34, 0xf5, 0x38, 0xe4, 0xf5, //0x8b70,
-	0x22, 0xf5, 0x23, 0x85, 0x3b, 0x31, 0x85, 0x3a, 0x30, 0x85, 0x39, 0x2f, 0x85, 0x38, 0x2e, 0x02, //0x8b80,
-	0x0f, 0x46, 0xe0, 0xa3, 0xe0, 0x75, 0xf0, 0x02, 0xa4, 0xff, 0xae, 0xf0, 0xc3, 0x08, 0xe6, 0x9f, //0x8b90,
-	0xf6, 0x18, 0xe6, 0x9e, 0xf6, 0x22, 0xff, 0xe5, 0xf0, 0x34, 0x60, 0x8f, 0x82, 0xf5, 0x83, 0xec, //0x8ba0,
-	0xf0, 0x22, 0x78, 0x52, 0x7e, 0x00, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x02, 0x04, 0xc1, 0xe4, 0xfc, //0x8bb0,
-	0xfd, 0x12, 0x06, 0x99, 0x78, 0x5c, 0xe6, 0xc3, 0x13, 0xfe, 0x08, 0xe6, 0x13, 0x22, 0x78, 0x52, //0x8bc0,
-	0xe6, 0xfe, 0x08, 0xe6, 0xff, 0xe4, 0xfc, 0xfd, 0x22, 0xe7, 0xc4, 0xf8, 0x54, 0xf0, 0xc8, 0x68, //0x8bd0,
-	0xf7, 0x09, 0xe7, 0xc4, 0x54, 0x0f, 0x48, 0xf7, 0x22, 0xe6, 0xfc, 0xed, 0x75, 0xf0, 0x04, 0xa4, //0x8be0,
-	0x22, 0x12, 0x06, 0x7c, 0x8f, 0x48, 0x8e, 0x47, 0x8d, 0x46, 0x8c, 0x45, 0x22, 0xe0, 0xfe, 0xa3, //0x8bf0,
-	0xe0, 0xfd, 0xee, 0xf6, 0xed, 0x08, 0xf6, 0x22, 0x13, 0xff, 0xc3, 0xe6, 0x9f, 0xff, 0x18, 0xe6, //0x8c00,
-	0x9e, 0xfe, 0x22, 0xe6, 0xc3, 0x13, 0xf7, 0x08, 0xe6, 0x13, 0x09, 0xf7, 0x22, 0xad, 0x39, 0xac, //0x8c10,
-	0x38, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0x28, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0xab, //0x8c20,
-	0x37, 0xaa, 0x36, 0xa9, 0x35, 0xa8, 0x34, 0x22, 0x93, 0xff, 0xe4, 0xfc, 0xfd, 0xfe, 0x12, 0x05, //0x8c30,
-	0x28, 0x8f, 0x37, 0x8e, 0x36, 0x8d, 0x35, 0x8c, 0x34, 0x22, 0x78, 0x84, 0xe6, 0xfe, 0x08, 0xe6, //0x8c40,
-	0xff, 0xe4, 0x8f, 0x37, 0x8e, 0x36, 0xf5, 0x35, 0xf5, 0x34, 0x22, 0x90, 0x0e, 0x8c, 0xe4, 0x93, //0x8c50,
-	0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe6, 0xfe, 0x08, 0xe6, 0xff, //0x8c60,
-	0xe4, 0x8f, 0x3b, 0x8e, 0x3a, 0xf5, 0x39, 0xf5, 0x38, 0x22, 0x78, 0x4e, 0xe6, 0xfe, 0x08, 0xe6, //0x8c70,
-	0xff, 0x22, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x22, 0x78, 0x89, //0x8c80,
-	0xef, 0x26, 0xf6, 0x18, 0xe4, 0x36, 0xf6, 0x22, 0x75, 0x89, 0x03, 0x75, 0xa8, 0x01, 0x75, 0xb8, //0x8c90,
-	0x04, 0x75, 0x34, 0xff, 0x75, 0x35, 0x0e, 0x75, 0x36, 0x15, 0x75, 0x37, 0x0d, 0x12, 0x0e, 0x9a, //0x8ca0,
-	0x12, 0x00, 0x09, 0x12, 0x0f, 0x16, 0x12, 0x00, 0x06, 0xd2, 0x00, 0xd2, 0x34, 0xd2, 0xaf, 0x75, //0x8cb0,
-	0x34, 0xff, 0x75, 0x35, 0x0e, 0x75, 0x36, 0x49, 0x75, 0x37, 0x03, 0x12, 0x0e, 0x9a, 0x30, 0x08, //0x8cc0,
-	0x09, 0xc2, 0x34, 0x12, 0x08, 0xcb, 0xc2, 0x08, 0xd2, 0x34, 0x30, 0x0b, 0x09, 0xc2, 0x36, 0x12, //0x8cd0,
-	0x02, 0x6c, 0xc2, 0x0b, 0xd2, 0x36, 0x30, 0x09, 0x09, 0xc2, 0x36, 0x12, 0x00, 0x0e, 0xc2, 0x09, //0x8ce0,
-	0xd2, 0x36, 0x30, 0x0e, 0x03, 0x12, 0x06, 0xd7, 0x30, 0x35, 0xd3, 0x90, 0x30, 0x29, 0xe5, 0x1e, //0x8cf0,
-	0xf0, 0xb4, 0x10, 0x05, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0xc2, 0x35, 0x80, 0xc1, 0xe4, 0xf5, 0x4b, //0x8d00,
-	0x90, 0x0e, 0x7a, 0x93, 0xff, 0xe4, 0x8f, 0x37, 0xf5, 0x36, 0xf5, 0x35, 0xf5, 0x34, 0xaf, 0x37, //0x8d10,
-	0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0x90, 0x0e, 0x6a, 0x12, 0x0d, 0xf6, 0x8f, 0x37, 0x8e, 0x36, //0x8d20,
-	0x8d, 0x35, 0x8c, 0x34, 0x90, 0x0e, 0x72, 0x12, 0x06, 0x7c, 0xef, 0x45, 0x37, 0xf5, 0x37, 0xee, //0x8d30,
-	0x45, 0x36, 0xf5, 0x36, 0xed, 0x45, 0x35, 0xf5, 0x35, 0xec, 0x45, 0x34, 0xf5, 0x34, 0xe4, 0xf5, //0x8d40,
-	0x22, 0xf5, 0x23, 0x85, 0x37, 0x31, 0x85, 0x36, 0x30, 0x85, 0x35, 0x2f, 0x85, 0x34, 0x2e, 0x12, //0x8d50,
-	0x0f, 0x46, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x72, 0x12, 0x0d, 0xea, 0x12, 0x0f, 0x46, //0x8d60,
-	0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x6e, 0x12, 0x0d, 0xea, 0x02, 0x0f, 0x46, 0xe5, 0x40, //0x8d70,
-	0x24, 0xf2, 0xf5, 0x37, 0xe5, 0x3f, 0x34, 0x43, 0xf5, 0x36, 0xe5, 0x3e, 0x34, 0xa2, 0xf5, 0x35, //0x8d80,
-	0xe5, 0x3d, 0x34, 0x28, 0xf5, 0x34, 0xe5, 0x37, 0xff, 0xe4, 0xfe, 0xfd, 0xfc, 0x78, 0x18, 0x12, //0x8d90,
-	0x06, 0x69, 0x8f, 0x40, 0x8e, 0x3f, 0x8d, 0x3e, 0x8c, 0x3d, 0xe5, 0x37, 0x54, 0xa0, 0xff, 0xe5, //0x8da0,
-	0x36, 0xfe, 0xe4, 0xfd, 0xfc, 0x78, 0x07, 0x12, 0x06, 0x56, 0x78, 0x10, 0x12, 0x0f, 0x9a, 0xe4, //0x8db0,
-	0xff, 0xfe, 0xe5, 0x35, 0xfd, 0xe4, 0xfc, 0x78, 0x0e, 0x12, 0x06, 0x56, 0x12, 0x0f, 0x9d, 0xe4, //0x8dc0,
-	0xff, 0xfe, 0xfd, 0xe5, 0x34, 0xfc, 0x78, 0x18, 0x12, 0x06, 0x56, 0x78, 0x08, 0x12, 0x0f, 0x9a, //0x8dd0,
-	0x22, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0x22, 0x12, 0x06, 0x7c, 0x8f, 0x31, 0x8e, //0x8de0,
-	0x30, 0x8d, 0x2f, 0x8c, 0x2e, 0x22, 0x93, 0xf9, 0xf8, 0x02, 0x06, 0x69, 0x00, 0x00, 0x00, 0x00, //0x8df0,
-	0x12, 0x01, 0x17, 0x08, 0x31, 0x15, 0x53, 0x54, 0x44, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x01, //0x8e00,
-	0x10, 0x01, 0x56, 0x40, 0x1a, 0x30, 0x29, 0x7e, 0x00, 0x30, 0x04, 0x20, 0xdf, 0x30, 0x05, 0x40, //0x8e10,
-	0xbf, 0x50, 0x03, 0x00, 0xfd, 0x50, 0x27, 0x01, 0xfe, 0x60, 0x00, 0x11, 0x00, 0x3f, 0x05, 0x30, //0x8e20,
-	0x00, 0x3f, 0x06, 0x22, 0x00, 0x3f, 0x01, 0x2a, 0x00, 0x3f, 0x02, 0x00, 0x00, 0x36, 0x06, 0x07, //0x8e30,
-	0x00, 0x3f, 0x0b, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x40, 0xbf, 0x30, 0x01, 0x00, //0x8e40,
-	0xbf, 0x30, 0x29, 0x70, 0x00, 0x3a, 0x00, 0x00, 0xff, 0x3a, 0x00, 0x00, 0xff, 0x36, 0x03, 0x36, //0x8e50,
-	0x02, 0x41, 0x44, 0x58, 0x20, 0x18, 0x10, 0x0a, 0x04, 0x04, 0x00, 0x03, 0xff, 0x64, 0x00, 0x00, //0x8e60,
-	0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x06, 0x06, 0x00, 0x03, 0x51, 0x00, 0x7a, //0x8e70,
-	0x50, 0x3c, 0x28, 0x1e, 0x10, 0x10, 0x50, 0x2d, 0x28, 0x16, 0x10, 0x10, 0x02, 0x00, 0x10, 0x0c, //0x8e80,
-	0x10, 0x04, 0x0c, 0x6e, 0x06, 0x05, 0x00, 0xa5, 0x5a, 0x00, 0xae, 0x35, 0xaf, 0x36, 0xe4, 0xfd, //0x8e90,
-	0xed, 0xc3, 0x95, 0x37, 0x50, 0x33, 0x12, 0x0f, 0xe2, 0xe4, 0x93, 0xf5, 0x38, 0x74, 0x01, 0x93, //0x8ea0,
-	0xf5, 0x39, 0x45, 0x38, 0x60, 0x23, 0x85, 0x39, 0x82, 0x85, 0x38, 0x83, 0xe0, 0xfc, 0x12, 0x0f, //0x8eb0,
-	0xe2, 0x74, 0x03, 0x93, 0x52, 0x04, 0x12, 0x0f, 0xe2, 0x74, 0x02, 0x93, 0x42, 0x04, 0x85, 0x39, //0x8ec0,
-	0x82, 0x85, 0x38, 0x83, 0xec, 0xf0, 0x0d, 0x80, 0xc7, 0x22, 0x78, 0xbe, 0xe6, 0xd3, 0x08, 0xff, //0x8ed0,
-	0xe6, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80, 0x98, 0x22, 0x93, 0xff, 0x7e, 0x00, 0xe6, 0xfc, 0x08, //0x8ee0,
-	0xe6, 0xfd, 0x12, 0x04, 0xc1, 0x78, 0xc1, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0xd3, 0xef, 0x9d, 0xee, //0x8ef0,
-	0x9c, 0x22, 0x78, 0xbd, 0xd3, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x22, 0x25, 0xe0, 0x24, 0x0a, 0xf8, //0x8f00,
-	0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe5, 0x3c, 0xd3, 0x94, 0x00, 0x40, 0x0b, 0x90, 0x0e, 0x88, //0x8f10,
-	0x12, 0x0b, 0xf1, 0x90, 0x0e, 0x86, 0x80, 0x09, 0x90, 0x0e, 0x82, 0x12, 0x0b, 0xf1, 0x90, 0x0e, //0x8f20,
-	0x80, 0xe4, 0x93, 0xf5, 0x44, 0xa3, 0xe4, 0x93, 0xf5, 0x43, 0xd2, 0x06, 0x30, 0x06, 0x03, 0xd3, //0x8f30,
-	0x80, 0x01, 0xc3, 0x92, 0x0e, 0x22, 0xa2, 0xaf, 0x92, 0x32, 0xc2, 0xaf, 0xe5, 0x23, 0x45, 0x22, //0x8f40,
-	0x90, 0x0e, 0x5d, 0x60, 0x0e, 0x12, 0x0f, 0xcb, 0xe0, 0xf5, 0x2c, 0x12, 0x0f, 0xc8, 0xe0, 0xf5, //0x8f50,
-	0x2d, 0x80, 0x0c, 0x12, 0x0f, 0xcb, 0xe5, 0x30, 0xf0, 0x12, 0x0f, 0xc8, 0xe5, 0x31, 0xf0, 0xa2, //0x8f60,
-	0x32, 0x92, 0xaf, 0x22, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, //0x8f70,
-	0x33, 0xd2, 0x36, 0xd2, 0x01, 0xc2, 0x02, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0x22, //0x8f80,
-	0xfb, 0xd3, 0xed, 0x9b, 0x74, 0x80, 0xf8, 0x6c, 0x98, 0x22, 0x12, 0x06, 0x69, 0xe5, 0x40, 0x2f, //0x8f90,
-	0xf5, 0x40, 0xe5, 0x3f, 0x3e, 0xf5, 0x3f, 0xe5, 0x3e, 0x3d, 0xf5, 0x3e, 0xe5, 0x3d, 0x3c, 0xf5, //0x8fa0,
-	0x3d, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0x90, 0x3f, 0x0d, 0xe0, 0xf5, 0x33, 0xe5, 0x33, //0x8fb0,
-	0xf0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, 0x0e, 0x5f, 0xe4, 0x93, 0xfe, 0x74, 0x01, //0x8fc0,
-	0x93, 0xf5, 0x82, 0x8e, 0x83, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8, 0xfd, 0x75, 0x81, 0xcd, 0x02, //0x8fd0,
-	0x0c, 0x98, 0x8f, 0x82, 0x8e, 0x83, 0x75, 0xf0, 0x04, 0xed, 0x02, 0x06, 0xa5,                   //0x8fe0
-}; 
+    0x02, 0x0f, 0xd6, 0x02, 0x0a, 0x39, 0xc2, 0x01, 0x22, 0x22, 0x00, 0x02, 0x0f, 0xb2, 0xe5, 0x1f, //0x8000,
+    0x70, 0x72, 0xf5, 0x1e, 0xd2, 0x35, 0xff, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe4, 0xf6, 0x08, //0x8010,
+    0xf6, 0x0f, 0xbf, 0x34, 0xf2, 0x90, 0x0e, 0x93, 0xe4, 0x93, 0xff, 0xe5, 0x4b, 0xc3, 0x9f, 0x50, //0x8020,
+    0x04, 0x7f, 0x05, 0x80, 0x02, 0x7f, 0xfb, 0x78, 0xbd, 0xa6, 0x07, 0x12, 0x0f, 0x04, 0x40, 0x04, //0x8030,
+    0x7f, 0x03, 0x80, 0x02, 0x7f, 0x30, 0x78, 0xbc, 0xa6, 0x07, 0xe6, 0x18, 0xf6, 0x08, 0xe6, 0x78, //0x8040,
+    0xb9, 0xf6, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xbf, 0x76, 0x33, 0xe4, 0x08, 0xf6, 0x78, //0x8050,
+    0xb8, 0x76, 0x01, 0x75, 0x4a, 0x02, 0x78, 0xb6, 0xf6, 0x08, 0xf6, 0x74, 0xff, 0x78, 0xc1, 0xf6, //0x8060,
+    0x08, 0xf6, 0x75, 0x1f, 0x01, 0x78, 0xbc, 0xe6, 0x75, 0xf0, 0x05, 0xa4, 0xf5, 0x4b, 0x12, 0x0a, //0x8070,
+    0xff, 0xc2, 0x37, 0x22, 0x78, 0xb8, 0xe6, 0xd3, 0x94, 0x00, 0x40, 0x02, 0x16, 0x22, 0xe5, 0x1f, //0x8080,
+    0xb4, 0x05, 0x23, 0xe4, 0xf5, 0x1f, 0xc2, 0x01, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x78, //0x8090,
+    0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x90, 0x30, 0x28, 0xf0, //0x80a0,
+    0x75, 0x1e, 0x10, 0xd2, 0x35, 0x22, 0xe5, 0x4b, 0x75, 0xf0, 0x05, 0x84, 0x78, 0xbc, 0xf6, 0x90, //0x80b0,
+    0x0e, 0x8c, 0xe4, 0x93, 0xff, 0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x78, //0x80c0,
+    0xbc, 0xe6, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0xef, 0x12, 0x0f, 0x0b, //0x80d0,
+    0xd3, 0x78, 0xb7, 0x96, 0xee, 0x18, 0x96, 0x40, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xb9, 0xf6, 0x78, //0x80e0,
+    0xb6, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x8c, 0xe4, 0x93, 0x12, 0x0f, 0x0b, 0xc3, 0x78, //0x80f0,
+    0xc2, 0x96, 0xee, 0x18, 0x96, 0x50, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xc1, 0xa6, //0x8100,
+    0x06, 0x08, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xc3, 0x78, 0xc2, 0x96, 0xff, 0xee, //0x8110,
+    0x18, 0x96, 0x78, 0xc3, 0xf6, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x95, 0xe4, 0x18, 0x12, 0x0e, 0xe9, //0x8120,
+    0x40, 0x02, 0xd2, 0x37, 0x78, 0xbc, 0xe6, 0x08, 0x26, 0x08, 0xf6, 0xe5, 0x1f, 0x64, 0x01, 0x70, //0x8130,
+    0x4a, 0xe6, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xdf, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, 0x39, 0x12, //0x8140,
+    0x0f, 0x02, 0x40, 0x04, 0x7f, 0xfe, 0x80, 0x02, 0x7f, 0x02, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, //0x8150,
+    0xe6, 0x24, 0x03, 0x78, 0xbf, 0xf6, 0x78, 0xb9, 0xe6, 0x24, 0xfd, 0x78, 0xc0, 0xf6, 0x12, 0x0f, //0x8160,
+    0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8170,
+    0x07, 0x75, 0x1f, 0x02, 0x78, 0xb8, 0x76, 0x01, 0x02, 0x02, 0x4a, 0xe5, 0x1f, 0x64, 0x02, 0x60, //0x8180,
+    0x03, 0x02, 0x02, 0x2a, 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x08, //0x8190,
+    0x12, 0x0e, 0xda, 0x50, 0x03, 0x02, 0x02, 0x28, 0x12, 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xff, 0x80, //0x81a0,
+    0x02, 0x7f, 0x01, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, 0xe6, 0x04, 0x78, 0xbf, 0xf6, 0x78, 0xb9, //0x81b0,
+    0xe6, 0x14, 0x78, 0xc0, 0xf6, 0x18, 0x12, 0x0f, 0x04, 0x40, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, //0x81c0,
+    0x00, 0x78, 0xbf, 0xa6, 0x07, 0xd3, 0x08, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x40, 0x04, 0xe6, 0xff, //0x81d0,
+    0x80, 0x02, 0x7f, 0x00, 0x78, 0xc0, 0xa6, 0x07, 0xc3, 0x18, 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, //0x81e0,
+    0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbf, 0xa6, 0x07, 0xc3, 0x08, 0xe6, 0x64, 0x80, //0x81f0,
+    0x94, 0xb3, 0x50, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xc0, 0xa6, 0x07, 0x12, 0x0f, //0x8200,
+    0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8210,
+    0x07, 0x75, 0x1f, 0x03, 0x78, 0xb8, 0x76, 0x01, 0x80, 0x20, 0xe5, 0x1f, 0x64, 0x03, 0x70, 0x26, //0x8220,
+    0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, //0x8230,
+    0x09, 0x78, 0xb9, 0xe6, 0x78, 0xbe, 0xf6, 0x75, 0x1f, 0x04, 0x78, 0xbe, 0xe6, 0x75, 0xf0, 0x05, //0x8240,
+    0xa4, 0xf5, 0x4b, 0x02, 0x0a, 0xff, 0xe5, 0x1f, 0xb4, 0x04, 0x10, 0x90, 0x0e, 0x94, 0xe4, 0x78, //0x8250,
+    0xc3, 0x12, 0x0e, 0xe9, 0x40, 0x02, 0xd2, 0x37, 0x75, 0x1f, 0x05, 0x22, 0x30, 0x01, 0x03, 0x02, //0x8260,
+    0x04, 0xc0, 0x30, 0x02, 0x03, 0x02, 0x04, 0xc0, 0x90, 0x51, 0xa5, 0xe0, 0x78, 0x93, 0xf6, 0xa3, //0x8270,
+    0xe0, 0x08, 0xf6, 0xa3, 0xe0, 0x08, 0xf6, 0xe5, 0x1f, 0x70, 0x3c, 0x75, 0x1e, 0x20, 0xd2, 0x35, //0x8280,
+    0x12, 0x0c, 0x7a, 0x78, 0x7e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xa6, 0x09, 0x18, 0x76, //0x8290,
+    0x01, 0x12, 0x0c, 0x5b, 0x78, 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xe6, 0x78, 0x6e, //0x82a0,
+    0xf6, 0x75, 0x1f, 0x01, 0x78, 0x93, 0xe6, 0x78, 0x90, 0xf6, 0x78, 0x94, 0xe6, 0x78, 0x91, 0xf6, //0x82b0,
+    0x78, 0x95, 0xe6, 0x78, 0x92, 0xf6, 0x22, 0x79, 0x90, 0xe7, 0xd3, 0x78, 0x93, 0x96, 0x40, 0x05, //0x82c0,
+    0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x93, 0xe7, 0x78, 0x90, 0x96, 0xff, 0x78, 0x88, 0x76, //0x82d0,
+    0x00, 0x08, 0xa6, 0x07, 0x79, 0x91, 0xe7, 0xd3, 0x78, 0x94, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, //0x82e0,
+    0x80, 0x08, 0xc3, 0x79, 0x94, 0xe7, 0x78, 0x91, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x79, 0x92, 0xe7, //0x82f0,
+    0xd3, 0x78, 0x95, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x95, 0xe7, 0x78, //0x8300,
+    0x92, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x12, 0x0c, 0x5b, 0x78, 0x8a, 0xe6, 0x25, 0xe0, 0x24, 0x4e, //0x8310,
+    0xf8, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8a, 0xe6, 0x24, 0x6e, 0xf8, 0xa6, 0x09, 0x78, 0x8a, //0x8320,
+    0xe6, 0x24, 0x01, 0xff, 0xe4, 0x33, 0xfe, 0xd3, 0xef, 0x94, 0x0f, 0xee, 0x64, 0x80, 0x94, 0x80, //0x8330,
+    0x40, 0x04, 0x7f, 0x00, 0x80, 0x05, 0x78, 0x8a, 0xe6, 0x04, 0xff, 0x78, 0x8a, 0xa6, 0x07, 0xe5, //0x8340,
+    0x1f, 0xb4, 0x01, 0x0a, 0xe6, 0x60, 0x03, 0x02, 0x04, 0xc0, 0x75, 0x1f, 0x02, 0x22, 0x12, 0x0c, //0x8350,
+    0x7a, 0x78, 0x80, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x12, 0x0c, 0x7a, 0x78, 0x82, 0xa6, 0x06, 0x08, //0x8360,
+    0xa6, 0x07, 0x78, 0x6e, 0xe6, 0x78, 0x8c, 0xf6, 0x78, 0x6e, 0xe6, 0x78, 0x8d, 0xf6, 0x7f, 0x01, //0x8370,
+    0xef, 0x25, 0xe0, 0x24, 0x4f, 0xf9, 0xc3, 0x78, 0x81, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x50, //0x8380,
+    0x0a, 0x12, 0x0c, 0x82, 0x78, 0x80, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, //0x8390,
+    0x8c, 0xe6, 0xc3, 0x97, 0x50, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8c, 0xf6, 0xef, 0x25, //0x83a0,
+    0xe0, 0x24, 0x4f, 0xf9, 0xd3, 0x78, 0x83, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x40, 0x0a, 0x12, //0x83b0,
+    0x0c, 0x82, 0x78, 0x82, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, 0x8d, 0xe6, //0x83c0,
+    0xd3, 0x97, 0x40, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8d, 0xf6, 0x0f, 0xef, 0x64, 0x10, //0x83d0,
+    0x70, 0x9e, 0xc3, 0x79, 0x81, 0xe7, 0x78, 0x83, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0x78, 0x84, //0x83e0,
+    0xf6, 0x08, 0xa6, 0x07, 0xc3, 0x79, 0x8c, 0xe7, 0x78, 0x8d, 0x96, 0x08, 0xf6, 0xd3, 0x79, 0x81, //0x83f0,
+    0xe7, 0x78, 0x7f, 0x96, 0x19, 0xe7, 0x18, 0x96, 0x40, 0x05, 0x09, 0xe7, 0x08, 0x80, 0x06, 0xc3, //0x8400,
+    0x79, 0x7f, 0xe7, 0x78, 0x81, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0xfe, 0x78, 0x86, 0xa6, 0x06, //0x8410,
+    0x08, 0xa6, 0x07, 0x79, 0x8c, 0xe7, 0xd3, 0x78, 0x8b, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, //0x8420,
+    0x08, 0xc3, 0x79, 0x8b, 0xe7, 0x78, 0x8c, 0x96, 0xff, 0x78, 0x8f, 0xa6, 0x07, 0xe5, 0x1f, 0x64, //0x8430,
+    0x02, 0x70, 0x69, 0x90, 0x0e, 0x91, 0x93, 0xff, 0x18, 0xe6, 0xc3, 0x9f, 0x50, 0x72, 0x12, 0x0c, //0x8440,
+    0x4a, 0x12, 0x0c, 0x2f, 0x90, 0x0e, 0x8e, 0x12, 0x0c, 0x38, 0x78, 0x80, 0x12, 0x0c, 0x6b, 0x7b, //0x8450,
+    0x04, 0x12, 0x0c, 0x1d, 0xc3, 0x12, 0x06, 0x45, 0x50, 0x56, 0x90, 0x0e, 0x92, 0xe4, 0x93, 0xff, //0x8460,
+    0x78, 0x8f, 0xe6, 0x9f, 0x40, 0x02, 0x80, 0x11, 0x90, 0x0e, 0x90, 0xe4, 0x93, 0xff, 0xd3, 0x78, //0x8470,
+    0x89, 0xe6, 0x9f, 0x18, 0xe6, 0x94, 0x00, 0x40, 0x03, 0x75, 0x1f, 0x05, 0x12, 0x0c, 0x4a, 0x12, //0x8480,
+    0x0c, 0x2f, 0x90, 0x0e, 0x8f, 0x12, 0x0c, 0x38, 0x78, 0x7e, 0x12, 0x0c, 0x6b, 0x7b, 0x40, 0x12, //0x8490,
+    0x0c, 0x1d, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x18, 0x75, 0x1f, 0x05, 0x22, 0xe5, 0x1f, 0xb4, 0x05, //0x84a0,
+    0x0f, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0xd2, 0x36, //0x84b0,
+    0x22, 0xef, 0x8d, 0xf0, 0xa4, 0xa8, 0xf0, 0xcf, 0x8c, 0xf0, 0xa4, 0x28, 0xce, 0x8d, 0xf0, 0xa4, //0x84c0,
+    0x2e, 0xfe, 0x22, 0xbc, 0x00, 0x0b, 0xbe, 0x00, 0x29, 0xef, 0x8d, 0xf0, 0x84, 0xff, 0xad, 0xf0, //0x84d0,
+    0x22, 0xe4, 0xcc, 0xf8, 0x75, 0xf0, 0x08, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xec, 0x33, 0xfc, //0x84e0,
+    0xee, 0x9d, 0xec, 0x98, 0x40, 0x05, 0xfc, 0xee, 0x9d, 0xfe, 0x0f, 0xd5, 0xf0, 0xe9, 0xe4, 0xce, //0x84f0,
+    0xfd, 0x22, 0xed, 0xf8, 0xf5, 0xf0, 0xee, 0x84, 0x20, 0xd2, 0x1c, 0xfe, 0xad, 0xf0, 0x75, 0xf0, //0x8500,
+    0x08, 0xef, 0x2f, 0xff, 0xed, 0x33, 0xfd, 0x40, 0x07, 0x98, 0x50, 0x06, 0xd5, 0xf0, 0xf2, 0x22, //0x8510,
+    0xc3, 0x98, 0xfd, 0x0f, 0xd5, 0xf0, 0xea, 0x22, 0xe8, 0x8f, 0xf0, 0xa4, 0xcc, 0x8b, 0xf0, 0xa4, //0x8520,
+    0x2c, 0xfc, 0xe9, 0x8e, 0xf0, 0xa4, 0x2c, 0xfc, 0x8a, 0xf0, 0xed, 0xa4, 0x2c, 0xfc, 0xea, 0x8e, //0x8530,
+    0xf0, 0xa4, 0xcd, 0xa8, 0xf0, 0x8b, 0xf0, 0xa4, 0x2d, 0xcc, 0x38, 0x25, 0xf0, 0xfd, 0xe9, 0x8f, //0x8540,
+    0xf0, 0xa4, 0x2c, 0xcd, 0x35, 0xf0, 0xfc, 0xeb, 0x8e, 0xf0, 0xa4, 0xfe, 0xa9, 0xf0, 0xeb, 0x8f, //0x8550,
+    0xf0, 0xa4, 0xcf, 0xc5, 0xf0, 0x2e, 0xcd, 0x39, 0xfe, 0xe4, 0x3c, 0xfc, 0xea, 0xa4, 0x2d, 0xce, //0x8560,
+    0x35, 0xf0, 0xfd, 0xe4, 0x3c, 0xfc, 0x22, 0x75, 0xf0, 0x08, 0x75, 0x82, 0x00, 0xef, 0x2f, 0xff, //0x8570,
+    0xee, 0x33, 0xfe, 0xcd, 0x33, 0xcd, 0xcc, 0x33, 0xcc, 0xc5, 0x82, 0x33, 0xc5, 0x82, 0x9b, 0xed, //0x8580,
+    0x9a, 0xec, 0x99, 0xe5, 0x82, 0x98, 0x40, 0x0c, 0xf5, 0x82, 0xee, 0x9b, 0xfe, 0xed, 0x9a, 0xfd, //0x8590,
+    0xec, 0x99, 0xfc, 0x0f, 0xd5, 0xf0, 0xd6, 0xe4, 0xce, 0xfb, 0xe4, 0xcd, 0xfa, 0xe4, 0xcc, 0xf9, //0x85a0,
+    0xa8, 0x82, 0x22, 0xb8, 0x00, 0xc1, 0xb9, 0x00, 0x59, 0xba, 0x00, 0x2d, 0xec, 0x8b, 0xf0, 0x84, //0x85b0,
+    0xcf, 0xce, 0xcd, 0xfc, 0xe5, 0xf0, 0xcb, 0xf9, 0x78, 0x18, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, //0x85c0,
+    0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xeb, 0x33, 0xfb, 0x10, 0xd7, 0x03, 0x99, 0x40, 0x04, 0xeb, //0x85d0,
+    0x99, 0xfb, 0x0f, 0xd8, 0xe5, 0xe4, 0xf9, 0xfa, 0x22, 0x78, 0x18, 0xef, 0x2f, 0xff, 0xee, 0x33, //0x85e0,
+    0xfe, 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xc9, 0x33, 0xc9, 0x10, 0xd7, 0x05, 0x9b, 0xe9, 0x9a, //0x85f0,
+    0x40, 0x07, 0xec, 0x9b, 0xfc, 0xe9, 0x9a, 0xf9, 0x0f, 0xd8, 0xe0, 0xe4, 0xc9, 0xfa, 0xe4, 0xcc, //0x8600,
+    0xfb, 0x22, 0x75, 0xf0, 0x10, 0xef, 0x2f, 0xff, 0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd, 0xcc, 0x33, //0x8610,
+    0xcc, 0xc8, 0x33, 0xc8, 0x10, 0xd7, 0x07, 0x9b, 0xec, 0x9a, 0xe8, 0x99, 0x40, 0x0a, 0xed, 0x9b, //0x8620,
+    0xfd, 0xec, 0x9a, 0xfc, 0xe8, 0x99, 0xf8, 0x0f, 0xd5, 0xf0, 0xda, 0xe4, 0xcd, 0xfb, 0xe4, 0xcc, //0x8630,
+    0xfa, 0xe4, 0xc8, 0xf9, 0x22, 0xeb, 0x9f, 0xf5, 0xf0, 0xea, 0x9e, 0x42, 0xf0, 0xe9, 0x9d, 0x42, //0x8640,
+    0xf0, 0xe8, 0x9c, 0x45, 0xf0, 0x22, 0xe8, 0x60, 0x0f, 0xec, 0xc3, 0x13, 0xfc, 0xed, 0x13, 0xfd, //0x8650,
+    0xee, 0x13, 0xfe, 0xef, 0x13, 0xff, 0xd8, 0xf1, 0x22, 0xe8, 0x60, 0x0f, 0xef, 0xc3, 0x33, 0xff, //0x8660,
+    0xee, 0x33, 0xfe, 0xed, 0x33, 0xfd, 0xec, 0x33, 0xfc, 0xd8, 0xf1, 0x22, 0xe4, 0x93, 0xfc, 0x74, //0x8670,
+    0x01, 0x93, 0xfd, 0x74, 0x02, 0x93, 0xfe, 0x74, 0x03, 0x93, 0xff, 0x22, 0xe6, 0xfb, 0x08, 0xe6, //0x8680,
+    0xf9, 0x08, 0xe6, 0xfa, 0x08, 0xe6, 0xcb, 0xf8, 0x22, 0xec, 0xf6, 0x08, 0xed, 0xf6, 0x08, 0xee, //0x8690,
+    0xf6, 0x08, 0xef, 0xf6, 0x22, 0xa4, 0x25, 0x82, 0xf5, 0x82, 0xe5, 0xf0, 0x35, 0x83, 0xf5, 0x83, //0x86a0,
+    0x22, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3, //0x86b0,
+    0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82, 0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68, //0x86c0,
+    0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0x90, 0x38, 0x04, 0x78, 0x52, 0x12, 0x0b, 0xfd, 0x90, //0x86d0,
+    0x38, 0x00, 0xe0, 0xfe, 0xa3, 0xe0, 0xfd, 0xed, 0xff, 0xc3, 0x12, 0x0b, 0x9e, 0x90, 0x38, 0x10, //0x86e0,
+    0x12, 0x0b, 0x92, 0x90, 0x38, 0x06, 0x78, 0x54, 0x12, 0x0b, 0xfd, 0x90, 0x38, 0x02, 0xe0, 0xfe, //0x86f0,
+    0xa3, 0xe0, 0xfd, 0xed, 0xff, 0xc3, 0x12, 0x0b, 0x9e, 0x90, 0x38, 0x12, 0x12, 0x0b, 0x92, 0xa3, //0x8700,
+    0xe0, 0xb4, 0x31, 0x07, 0x78, 0x52, 0x79, 0x52, 0x12, 0x0c, 0x13, 0x90, 0x38, 0x14, 0xe0, 0xb4, //0x8710,
+    0x71, 0x15, 0x78, 0x52, 0xe6, 0xfe, 0x08, 0xe6, 0x78, 0x02, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, //0x8720,
+    0xf9, 0x79, 0x53, 0xf7, 0xee, 0x19, 0xf7, 0x90, 0x38, 0x15, 0xe0, 0xb4, 0x31, 0x07, 0x78, 0x54, //0x8730,
+    0x79, 0x54, 0x12, 0x0c, 0x13, 0x90, 0x38, 0x15, 0xe0, 0xb4, 0x71, 0x15, 0x78, 0x54, 0xe6, 0xfe, //0x8740,
+    0x08, 0xe6, 0x78, 0x02, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0x79, 0x55, 0xf7, 0xee, 0x19, //0x8750,
+    0xf7, 0x79, 0x52, 0x12, 0x0b, 0xd9, 0x09, 0x12, 0x0b, 0xd9, 0xaf, 0x47, 0x12, 0x0b, 0xb2, 0xe5, //0x8760,
+    0x44, 0xfb, 0x7a, 0x00, 0xfd, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x5a, 0xa6, 0x06, 0x08, 0xa6, //0x8770,
+    0x07, 0xaf, 0x45, 0x12, 0x0b, 0xb2, 0xad, 0x03, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x56, 0xa6, //0x8780,
+    0x06, 0x08, 0xa6, 0x07, 0xaf, 0x48, 0x78, 0x54, 0x12, 0x0b, 0xb4, 0xe5, 0x43, 0xfb, 0xfd, 0x7c, //0x8790,
+    0x00, 0x12, 0x04, 0xd3, 0x78, 0x5c, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xaf, 0x46, 0x7e, 0x00, 0x78, //0x87a0,
+    0x54, 0x12, 0x0b, 0xb6, 0xad, 0x03, 0x7c, 0x00, 0x12, 0x04, 0xd3, 0x78, 0x58, 0xa6, 0x06, 0x08, //0x87b0,
+    0xa6, 0x07, 0xc3, 0x78, 0x5b, 0xe6, 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05, 0x76, 0x00, //0x87c0,
+    0x08, 0x76, 0x08, 0xc3, 0x78, 0x5d, 0xe6, 0x94, 0x08, 0x18, 0xe6, 0x94, 0x00, 0x50, 0x05, 0x76, //0x87d0,
+    0x00, 0x08, 0x76, 0x08, 0x78, 0x5a, 0x12, 0x0b, 0xc6, 0xff, 0xd3, 0x78, 0x57, 0xe6, 0x9f, 0x18, //0x87e0,
+    0xe6, 0x9e, 0x40, 0x0e, 0x78, 0x5a, 0xe6, 0x13, 0xfe, 0x08, 0xe6, 0x78, 0x57, 0x12, 0x0c, 0x08, //0x87f0,
+    0x80, 0x04, 0x7e, 0x00, 0x7f, 0x00, 0x78, 0x5e, 0x12, 0x0b, 0xbe, 0xff, 0xd3, 0x78, 0x59, 0xe6, //0x8800,
+    0x9f, 0x18, 0xe6, 0x9e, 0x40, 0x0e, 0x78, 0x5c, 0xe6, 0x13, 0xfe, 0x08, 0xe6, 0x78, 0x59, 0x12, //0x8810,
+    0x0c, 0x08, 0x80, 0x04, 0x7e, 0x00, 0x7f, 0x00, 0xe4, 0xfc, 0xfd, 0x78, 0x62, 0x12, 0x06, 0x99, //0x8820,
+    0x78, 0x5a, 0x12, 0x0b, 0xc6, 0x78, 0x57, 0x26, 0xff, 0xee, 0x18, 0x36, 0xfe, 0x78, 0x66, 0x12, //0x8830,
+    0x0b, 0xbe, 0x78, 0x59, 0x26, 0xff, 0xee, 0x18, 0x36, 0xfe, 0xe4, 0xfc, 0xfd, 0x78, 0x6a, 0x12, //0x8840,
+    0x06, 0x99, 0x12, 0x0b, 0xce, 0x78, 0x66, 0x12, 0x06, 0x8c, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x08, //0x8850,
+    0x12, 0x0b, 0xce, 0x78, 0x66, 0x12, 0x06, 0x99, 0x78, 0x54, 0x12, 0x0b, 0xd0, 0x78, 0x6a, 0x12, //0x8860,
+    0x06, 0x8c, 0xd3, 0x12, 0x06, 0x45, 0x40, 0x0a, 0x78, 0x54, 0x12, 0x0b, 0xd0, 0x78, 0x6a, 0x12, //0x8870,
+    0x06, 0x99, 0x78, 0x61, 0xe6, 0x90, 0x60, 0x01, 0xf0, 0x78, 0x65, 0xe6, 0xa3, 0xf0, 0x78, 0x69, //0x8880,
+    0xe6, 0xa3, 0xf0, 0x78, 0x55, 0xe6, 0xa3, 0xf0, 0x7d, 0x01, 0x78, 0x61, 0x12, 0x0b, 0xe9, 0x24, //0x8890,
+    0x01, 0x12, 0x0b, 0xa6, 0x78, 0x65, 0x12, 0x0b, 0xe9, 0x24, 0x02, 0x12, 0x0b, 0xa6, 0x78, 0x69, //0x88a0,
+    0x12, 0x0b, 0xe9, 0x24, 0x03, 0x12, 0x0b, 0xa6, 0x78, 0x6d, 0x12, 0x0b, 0xe9, 0x24, 0x04, 0x12, //0x88b0,
+    0x0b, 0xa6, 0x0d, 0xbd, 0x05, 0xd4, 0xc2, 0x0e, 0xc2, 0x06, 0x22, 0x85, 0x08, 0x41, 0x90, 0x30, //0x88c0,
+    0x24, 0xe0, 0xf5, 0x3d, 0xa3, 0xe0, 0xf5, 0x3e, 0xa3, 0xe0, 0xf5, 0x3f, 0xa3, 0xe0, 0xf5, 0x40, //0x88d0,
+    0xa3, 0xe0, 0xf5, 0x3c, 0xd2, 0x34, 0xe5, 0x41, 0x12, 0x06, 0xb1, 0x09, 0x31, 0x03, 0x09, 0x35, //0x88e0,
+    0x04, 0x09, 0x3b, 0x05, 0x09, 0x3e, 0x06, 0x09, 0x41, 0x07, 0x09, 0x4a, 0x08, 0x09, 0x5b, 0x12, //0x88f0,
+    0x09, 0x73, 0x18, 0x09, 0x89, 0x19, 0x09, 0x5e, 0x1a, 0x09, 0x6a, 0x1b, 0x09, 0xad, 0x80, 0x09, //0x8900,
+    0xb2, 0x81, 0x0a, 0x1d, 0x8f, 0x0a, 0x09, 0x90, 0x0a, 0x1d, 0x91, 0x0a, 0x1d, 0x92, 0x0a, 0x1d, //0x8910,
+    0x93, 0x0a, 0x1d, 0x94, 0x0a, 0x1d, 0x98, 0x0a, 0x17, 0x9f, 0x0a, 0x1a, 0xec, 0x00, 0x00, 0x0a, //0x8920,
+    0x38, 0x12, 0x0f, 0x74, 0x22, 0x12, 0x0f, 0x74, 0xd2, 0x03, 0x22, 0xd2, 0x03, 0x22, 0xc2, 0x03, //0x8930,
+    0x22, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x02, 0x0a, 0x1d, 0xc2, 0x01, 0xc2, 0x02, 0xc2, 0x03, //0x8940,
+    0x12, 0x0d, 0x0d, 0x75, 0x1e, 0x70, 0xd2, 0x35, 0x02, 0x0a, 0x1d, 0x02, 0x0a, 0x04, 0x85, 0x40, //0x8950,
+    0x4a, 0x85, 0x3c, 0x4b, 0x12, 0x0a, 0xff, 0x02, 0x0a, 0x1d, 0x85, 0x4a, 0x40, 0x85, 0x4b, 0x3c, //0x8960,
+    0x02, 0x0a, 0x1d, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x85, 0x40, 0x31, 0x85, 0x3f, 0x30, 0x85, 0x3e, //0x8970,
+    0x2f, 0x85, 0x3d, 0x2e, 0x12, 0x0f, 0x46, 0x80, 0x1f, 0x75, 0x22, 0x00, 0x75, 0x23, 0x01, 0x74, //0x8980,
+    0xff, 0xf5, 0x2d, 0xf5, 0x2c, 0xf5, 0x2b, 0xf5, 0x2a, 0x12, 0x0f, 0x46, 0x85, 0x2d, 0x40, 0x85, //0x8990,
+    0x2c, 0x3f, 0x85, 0x2b, 0x3e, 0x85, 0x2a, 0x3d, 0xe4, 0xf5, 0x3c, 0x80, 0x70, 0x12, 0x0f, 0x16, //0x89a0,
+    0x80, 0x6b, 0x85, 0x3d, 0x45, 0x85, 0x3e, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xe5, 0x45, 0xc3, //0x89b0,
+    0x9f, 0x50, 0x02, 0x8f, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, 0xe5, 0x46, 0xc3, 0x9f, 0x50, 0x02, //0x89c0,
+    0x8f, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xfd, 0xe5, 0x45, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, //0x89d0,
+    0x44, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, 0x44, 0x9f, 0xf5, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, //0x89e0,
+    0xfd, 0xe5, 0x46, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, 0x43, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, //0x89f0,
+    0x43, 0x9f, 0xf5, 0x46, 0x12, 0x06, 0xd7, 0x80, 0x14, 0x85, 0x40, 0x48, 0x85, 0x3f, 0x47, 0x85, //0x8a00,
+    0x3e, 0x46, 0x85, 0x3d, 0x45, 0x80, 0x06, 0x02, 0x06, 0xd7, 0x12, 0x0d, 0x7e, 0x90, 0x30, 0x24, //0x8a10,
+    0xe5, 0x3d, 0xf0, 0xa3, 0xe5, 0x3e, 0xf0, 0xa3, 0xe5, 0x3f, 0xf0, 0xa3, 0xe5, 0x40, 0xf0, 0xa3, //0x8a20,
+    0xe5, 0x3c, 0xf0, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0xc0, //0x8a30,
+    0xd0, 0x90, 0x3f, 0x0c, 0xe0, 0xf5, 0x32, 0xe5, 0x32, 0x30, 0xe3, 0x74, 0x30, 0x36, 0x66, 0x90, //0x8a40,
+    0x60, 0x19, 0xe0, 0xf5, 0x0a, 0xa3, 0xe0, 0xf5, 0x0b, 0x90, 0x60, 0x1d, 0xe0, 0xf5, 0x14, 0xa3, //0x8a50,
+    0xe0, 0xf5, 0x15, 0x90, 0x60, 0x21, 0xe0, 0xf5, 0x0c, 0xa3, 0xe0, 0xf5, 0x0d, 0x90, 0x60, 0x29, //0x8a60,
+    0xe0, 0xf5, 0x0e, 0xa3, 0xe0, 0xf5, 0x0f, 0x90, 0x60, 0x31, 0xe0, 0xf5, 0x10, 0xa3, 0xe0, 0xf5, //0x8a70,
+    0x11, 0x90, 0x60, 0x39, 0xe0, 0xf5, 0x12, 0xa3, 0xe0, 0xf5, 0x13, 0x30, 0x01, 0x06, 0x30, 0x33, //0x8a80,
+    0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x09, 0x30, 0x02, 0x06, 0x30, 0x33, 0x03, 0xd3, 0x80, 0x01, //0x8a90,
+    0xc3, 0x92, 0x0a, 0x30, 0x33, 0x0c, 0x30, 0x03, 0x09, 0x20, 0x02, 0x06, 0x20, 0x01, 0x03, 0xd3, //0x8aa0,
+    0x80, 0x01, 0xc3, 0x92, 0x0b, 0x90, 0x30, 0x01, 0xe0, 0x44, 0x40, 0xf0, 0xe0, 0x54, 0xbf, 0xf0, //0x8ab0,
+    0xe5, 0x32, 0x30, 0xe1, 0x14, 0x30, 0x34, 0x11, 0x90, 0x30, 0x22, 0xe0, 0xf5, 0x08, 0xe4, 0xf0, //0x8ac0,
+    0x30, 0x00, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x08, 0xe5, 0x32, 0x30, 0xe5, 0x12, 0x90, 0x56, //0x8ad0,
+    0xa1, 0xe0, 0xf5, 0x09, 0x30, 0x31, 0x09, 0x30, 0x05, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x0d, //0x8ae0,
+    0x90, 0x3f, 0x0c, 0xe5, 0x32, 0xf0, 0xd0, 0xd0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, //0x8af0,
+    0x0e, 0x7e, 0xe4, 0x93, 0xfe, 0x74, 0x01, 0x93, 0xff, 0xc3, 0x90, 0x0e, 0x7c, 0x74, 0x01, 0x93, //0x8b00,
+    0x9f, 0xff, 0xe4, 0x93, 0x9e, 0xfe, 0xe4, 0x8f, 0x3b, 0x8e, 0x3a, 0xf5, 0x39, 0xf5, 0x38, 0xab, //0x8b10,
+    0x3b, 0xaa, 0x3a, 0xa9, 0x39, 0xa8, 0x38, 0xaf, 0x4b, 0xfc, 0xfd, 0xfe, 0x12, 0x05, 0x28, 0x12, //0x8b20,
+    0x0d, 0xe1, 0xe4, 0x7b, 0xff, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0xb3, 0x12, 0x0d, 0xe1, 0x90, 0x0e, //0x8b30,
+    0x69, 0xe4, 0x12, 0x0d, 0xf6, 0x12, 0x0d, 0xe1, 0xe4, 0x85, 0x4a, 0x37, 0xf5, 0x36, 0xf5, 0x35, //0x8b40,
+    0xf5, 0x34, 0xaf, 0x37, 0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0xa3, 0x12, 0x0d, 0xf6, 0x8f, 0x37, //0x8b50,
+    0x8e, 0x36, 0x8d, 0x35, 0x8c, 0x34, 0xe5, 0x3b, 0x45, 0x37, 0xf5, 0x3b, 0xe5, 0x3a, 0x45, 0x36, //0x8b60,
+    0xf5, 0x3a, 0xe5, 0x39, 0x45, 0x35, 0xf5, 0x39, 0xe5, 0x38, 0x45, 0x34, 0xf5, 0x38, 0xe4, 0xf5, //0x8b70,
+    0x22, 0xf5, 0x23, 0x85, 0x3b, 0x31, 0x85, 0x3a, 0x30, 0x85, 0x39, 0x2f, 0x85, 0x38, 0x2e, 0x02, //0x8b80,
+    0x0f, 0x46, 0xe0, 0xa3, 0xe0, 0x75, 0xf0, 0x02, 0xa4, 0xff, 0xae, 0xf0, 0xc3, 0x08, 0xe6, 0x9f, //0x8b90,
+    0xf6, 0x18, 0xe6, 0x9e, 0xf6, 0x22, 0xff, 0xe5, 0xf0, 0x34, 0x60, 0x8f, 0x82, 0xf5, 0x83, 0xec, //0x8ba0,
+    0xf0, 0x22, 0x78, 0x52, 0x7e, 0x00, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x02, 0x04, 0xc1, 0xe4, 0xfc, //0x8bb0,
+    0xfd, 0x12, 0x06, 0x99, 0x78, 0x5c, 0xe6, 0xc3, 0x13, 0xfe, 0x08, 0xe6, 0x13, 0x22, 0x78, 0x52, //0x8bc0,
+    0xe6, 0xfe, 0x08, 0xe6, 0xff, 0xe4, 0xfc, 0xfd, 0x22, 0xe7, 0xc4, 0xf8, 0x54, 0xf0, 0xc8, 0x68, //0x8bd0,
+    0xf7, 0x09, 0xe7, 0xc4, 0x54, 0x0f, 0x48, 0xf7, 0x22, 0xe6, 0xfc, 0xed, 0x75, 0xf0, 0x04, 0xa4, //0x8be0,
+    0x22, 0x12, 0x06, 0x7c, 0x8f, 0x48, 0x8e, 0x47, 0x8d, 0x46, 0x8c, 0x45, 0x22, 0xe0, 0xfe, 0xa3, //0x8bf0,
+    0xe0, 0xfd, 0xee, 0xf6, 0xed, 0x08, 0xf6, 0x22, 0x13, 0xff, 0xc3, 0xe6, 0x9f, 0xff, 0x18, 0xe6, //0x8c00,
+    0x9e, 0xfe, 0x22, 0xe6, 0xc3, 0x13, 0xf7, 0x08, 0xe6, 0x13, 0x09, 0xf7, 0x22, 0xad, 0x39, 0xac, //0x8c10,
+    0x38, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0x28, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0xab, //0x8c20,
+    0x37, 0xaa, 0x36, 0xa9, 0x35, 0xa8, 0x34, 0x22, 0x93, 0xff, 0xe4, 0xfc, 0xfd, 0xfe, 0x12, 0x05, //0x8c30,
+    0x28, 0x8f, 0x37, 0x8e, 0x36, 0x8d, 0x35, 0x8c, 0x34, 0x22, 0x78, 0x84, 0xe6, 0xfe, 0x08, 0xe6, //0x8c40,
+    0xff, 0xe4, 0x8f, 0x37, 0x8e, 0x36, 0xf5, 0x35, 0xf5, 0x34, 0x22, 0x90, 0x0e, 0x8c, 0xe4, 0x93, //0x8c50,
+    0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe6, 0xfe, 0x08, 0xe6, 0xff, //0x8c60,
+    0xe4, 0x8f, 0x3b, 0x8e, 0x3a, 0xf5, 0x39, 0xf5, 0x38, 0x22, 0x78, 0x4e, 0xe6, 0xfe, 0x08, 0xe6, //0x8c70,
+    0xff, 0x22, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x22, 0x78, 0x89, //0x8c80,
+    0xef, 0x26, 0xf6, 0x18, 0xe4, 0x36, 0xf6, 0x22, 0x75, 0x89, 0x03, 0x75, 0xa8, 0x01, 0x75, 0xb8, //0x8c90,
+    0x04, 0x75, 0x34, 0xff, 0x75, 0x35, 0x0e, 0x75, 0x36, 0x15, 0x75, 0x37, 0x0d, 0x12, 0x0e, 0x9a, //0x8ca0,
+    0x12, 0x00, 0x09, 0x12, 0x0f, 0x16, 0x12, 0x00, 0x06, 0xd2, 0x00, 0xd2, 0x34, 0xd2, 0xaf, 0x75, //0x8cb0,
+    0x34, 0xff, 0x75, 0x35, 0x0e, 0x75, 0x36, 0x49, 0x75, 0x37, 0x03, 0x12, 0x0e, 0x9a, 0x30, 0x08, //0x8cc0,
+    0x09, 0xc2, 0x34, 0x12, 0x08, 0xcb, 0xc2, 0x08, 0xd2, 0x34, 0x30, 0x0b, 0x09, 0xc2, 0x36, 0x12, //0x8cd0,
+    0x02, 0x6c, 0xc2, 0x0b, 0xd2, 0x36, 0x30, 0x09, 0x09, 0xc2, 0x36, 0x12, 0x00, 0x0e, 0xc2, 0x09, //0x8ce0,
+    0xd2, 0x36, 0x30, 0x0e, 0x03, 0x12, 0x06, 0xd7, 0x30, 0x35, 0xd3, 0x90, 0x30, 0x29, 0xe5, 0x1e, //0x8cf0,
+    0xf0, 0xb4, 0x10, 0x05, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0xc2, 0x35, 0x80, 0xc1, 0xe4, 0xf5, 0x4b, //0x8d00,
+    0x90, 0x0e, 0x7a, 0x93, 0xff, 0xe4, 0x8f, 0x37, 0xf5, 0x36, 0xf5, 0x35, 0xf5, 0x34, 0xaf, 0x37, //0x8d10,
+    0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0x90, 0x0e, 0x6a, 0x12, 0x0d, 0xf6, 0x8f, 0x37, 0x8e, 0x36, //0x8d20,
+    0x8d, 0x35, 0x8c, 0x34, 0x90, 0x0e, 0x72, 0x12, 0x06, 0x7c, 0xef, 0x45, 0x37, 0xf5, 0x37, 0xee, //0x8d30,
+    0x45, 0x36, 0xf5, 0x36, 0xed, 0x45, 0x35, 0xf5, 0x35, 0xec, 0x45, 0x34, 0xf5, 0x34, 0xe4, 0xf5, //0x8d40,
+    0x22, 0xf5, 0x23, 0x85, 0x37, 0x31, 0x85, 0x36, 0x30, 0x85, 0x35, 0x2f, 0x85, 0x34, 0x2e, 0x12, //0x8d50,
+    0x0f, 0x46, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x72, 0x12, 0x0d, 0xea, 0x12, 0x0f, 0x46, //0x8d60,
+    0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x6e, 0x12, 0x0d, 0xea, 0x02, 0x0f, 0x46, 0xe5, 0x40, //0x8d70,
+    0x24, 0xf2, 0xf5, 0x37, 0xe5, 0x3f, 0x34, 0x43, 0xf5, 0x36, 0xe5, 0x3e, 0x34, 0xa2, 0xf5, 0x35, //0x8d80,
+    0xe5, 0x3d, 0x34, 0x28, 0xf5, 0x34, 0xe5, 0x37, 0xff, 0xe4, 0xfe, 0xfd, 0xfc, 0x78, 0x18, 0x12, //0x8d90,
+    0x06, 0x69, 0x8f, 0x40, 0x8e, 0x3f, 0x8d, 0x3e, 0x8c, 0x3d, 0xe5, 0x37, 0x54, 0xa0, 0xff, 0xe5, //0x8da0,
+    0x36, 0xfe, 0xe4, 0xfd, 0xfc, 0x78, 0x07, 0x12, 0x06, 0x56, 0x78, 0x10, 0x12, 0x0f, 0x9a, 0xe4, //0x8db0,
+    0xff, 0xfe, 0xe5, 0x35, 0xfd, 0xe4, 0xfc, 0x78, 0x0e, 0x12, 0x06, 0x56, 0x12, 0x0f, 0x9d, 0xe4, //0x8dc0,
+    0xff, 0xfe, 0xfd, 0xe5, 0x34, 0xfc, 0x78, 0x18, 0x12, 0x06, 0x56, 0x78, 0x08, 0x12, 0x0f, 0x9a, //0x8dd0,
+    0x22, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0x22, 0x12, 0x06, 0x7c, 0x8f, 0x31, 0x8e, //0x8de0,
+    0x30, 0x8d, 0x2f, 0x8c, 0x2e, 0x22, 0x93, 0xf9, 0xf8, 0x02, 0x06, 0x69, 0x00, 0x00, 0x00, 0x00, //0x8df0,
+    0x12, 0x01, 0x17, 0x08, 0x31, 0x15, 0x53, 0x54, 0x44, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x01, //0x8e00,
+    0x10, 0x01, 0x56, 0x40, 0x1a, 0x30, 0x29, 0x7e, 0x00, 0x30, 0x04, 0x20, 0xdf, 0x30, 0x05, 0x40, //0x8e10,
+    0xbf, 0x50, 0x03, 0x00, 0xfd, 0x50, 0x27, 0x01, 0xfe, 0x60, 0x00, 0x11, 0x00, 0x3f, 0x05, 0x30, //0x8e20,
+    0x00, 0x3f, 0x06, 0x22, 0x00, 0x3f, 0x01, 0x2a, 0x00, 0x3f, 0x02, 0x00, 0x00, 0x36, 0x06, 0x07, //0x8e30,
+    0x00, 0x3f, 0x0b, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x40, 0xbf, 0x30, 0x01, 0x00, //0x8e40,
+    0xbf, 0x30, 0x29, 0x70, 0x00, 0x3a, 0x00, 0x00, 0xff, 0x3a, 0x00, 0x00, 0xff, 0x36, 0x03, 0x36, //0x8e50,
+    0x02, 0x41, 0x44, 0x58, 0x20, 0x18, 0x10, 0x0a, 0x04, 0x04, 0x00, 0x03, 0xff, 0x64, 0x00, 0x00, //0x8e60,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x06, 0x06, 0x00, 0x03, 0x51, 0x00, 0x7a, //0x8e70,
+    0x50, 0x3c, 0x28, 0x1e, 0x10, 0x10, 0x50, 0x2d, 0x28, 0x16, 0x10, 0x10, 0x02, 0x00, 0x10, 0x0c, //0x8e80,
+    0x10, 0x04, 0x0c, 0x6e, 0x06, 0x05, 0x00, 0xa5, 0x5a, 0x00, 0xae, 0x35, 0xaf, 0x36, 0xe4, 0xfd, //0x8e90,
+    0xed, 0xc3, 0x95, 0x37, 0x50, 0x33, 0x12, 0x0f, 0xe2, 0xe4, 0x93, 0xf5, 0x38, 0x74, 0x01, 0x93, //0x8ea0,
+    0xf5, 0x39, 0x45, 0x38, 0x60, 0x23, 0x85, 0x39, 0x82, 0x85, 0x38, 0x83, 0xe0, 0xfc, 0x12, 0x0f, //0x8eb0,
+    0xe2, 0x74, 0x03, 0x93, 0x52, 0x04, 0x12, 0x0f, 0xe2, 0x74, 0x02, 0x93, 0x42, 0x04, 0x85, 0x39, //0x8ec0,
+    0x82, 0x85, 0x38, 0x83, 0xec, 0xf0, 0x0d, 0x80, 0xc7, 0x22, 0x78, 0xbe, 0xe6, 0xd3, 0x08, 0xff, //0x8ed0,
+    0xe6, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80, 0x98, 0x22, 0x93, 0xff, 0x7e, 0x00, 0xe6, 0xfc, 0x08, //0x8ee0,
+    0xe6, 0xfd, 0x12, 0x04, 0xc1, 0x78, 0xc1, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0xd3, 0xef, 0x9d, 0xee, //0x8ef0,
+    0x9c, 0x22, 0x78, 0xbd, 0xd3, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x22, 0x25, 0xe0, 0x24, 0x0a, 0xf8, //0x8f00,
+    0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe5, 0x3c, 0xd3, 0x94, 0x00, 0x40, 0x0b, 0x90, 0x0e, 0x88, //0x8f10,
+    0x12, 0x0b, 0xf1, 0x90, 0x0e, 0x86, 0x80, 0x09, 0x90, 0x0e, 0x82, 0x12, 0x0b, 0xf1, 0x90, 0x0e, //0x8f20,
+    0x80, 0xe4, 0x93, 0xf5, 0x44, 0xa3, 0xe4, 0x93, 0xf5, 0x43, 0xd2, 0x06, 0x30, 0x06, 0x03, 0xd3, //0x8f30,
+    0x80, 0x01, 0xc3, 0x92, 0x0e, 0x22, 0xa2, 0xaf, 0x92, 0x32, 0xc2, 0xaf, 0xe5, 0x23, 0x45, 0x22, //0x8f40,
+    0x90, 0x0e, 0x5d, 0x60, 0x0e, 0x12, 0x0f, 0xcb, 0xe0, 0xf5, 0x2c, 0x12, 0x0f, 0xc8, 0xe0, 0xf5, //0x8f50,
+    0x2d, 0x80, 0x0c, 0x12, 0x0f, 0xcb, 0xe5, 0x30, 0xf0, 0x12, 0x0f, 0xc8, 0xe5, 0x31, 0xf0, 0xa2, //0x8f60,
+    0x32, 0x92, 0xaf, 0x22, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, //0x8f70,
+    0x33, 0xd2, 0x36, 0xd2, 0x01, 0xc2, 0x02, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0x22, //0x8f80,
+    0xfb, 0xd3, 0xed, 0x9b, 0x74, 0x80, 0xf8, 0x6c, 0x98, 0x22, 0x12, 0x06, 0x69, 0xe5, 0x40, 0x2f, //0x8f90,
+    0xf5, 0x40, 0xe5, 0x3f, 0x3e, 0xf5, 0x3f, 0xe5, 0x3e, 0x3d, 0xf5, 0x3e, 0xe5, 0x3d, 0x3c, 0xf5, //0x8fa0,
+    0x3d, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0x90, 0x3f, 0x0d, 0xe0, 0xf5, 0x33, 0xe5, 0x33, //0x8fb0,
+    0xf0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, 0x0e, 0x5f, 0xe4, 0x93, 0xfe, 0x74, 0x01, //0x8fc0,
+    0x93, 0xf5, 0x82, 0x8e, 0x83, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8, 0xfd, 0x75, 0x81, 0xcd, 0x02, //0x8fd0,
+    0x0c, 0x98, 0x8f, 0x82, 0x8e, 0x83, 0x75, 0xf0, 0x04, 0xed, 0x02, 0x06, 0xa5,                   //0x8fe0
+};
 
 #ifdef __cplusplus
 }
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c
index 174fd3bdac..3d4e2f18b8 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,12 +29,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8
     struct rt_i2c_msg msg[2] = {0, 0};
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     msg[0].addr  = STPMU1_I2C_ADDRESS;     /* Slave address */
     msg[0].flags = RT_I2C_WR;              /* Write flag */
     msg[0].buf   = &reg;                   /* Slave register address */
     msg[0].len   = 1;                      /* Number of bytes sent */
-        
+
     msg[1].addr  = STPMU1_I2C_ADDRESS;
     msg[1].flags = RT_I2C_RD;
     msg[1].len   = len;
@@ -55,7 +55,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint
     struct rt_i2c_msg msgs;
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     buf[0] = reg; //cmd
     buf[1] = data;
 
@@ -85,7 +85,7 @@ static rt_err_t stpmu1_read_reg(uint8_t register_id)
     {
         Error_Handler();
     }
-    
+
     return result;
 }
 
@@ -93,7 +93,7 @@ static void stpmu1_write_reg(uint8_t register_id, uint8_t value)
 {
     uint32_t status = RT_EOK;
     uint8_t readval = 0;
-    
+
     status = write_reg(pmic_dev, register_id, (rt_uint8_t)value);
 
     /* Check the communication status */
@@ -120,7 +120,7 @@ static uint32_t BSP_PMIC_MspInit(void)
     __HAL_RCC_GPIOA_CLK_ENABLE();
     GPIO_InitStruct.Pin       = GPIO_PIN_0;
     GPIO_InitStruct.Mode      = GPIO_MODE_IT_FALLING;
-    GPIO_InitStruct.Pull      = GPIO_PULLUP; 
+    GPIO_InitStruct.Pull      = GPIO_PULLUP;
     GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
     GPIO_InitStruct.Alternate = 0 ;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -619,7 +619,7 @@ static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t miliv
     uint8_t i;
     for ( i = 0 ; i < regul->voltage_table_size ; i++)
     {
-        if ( regul->voltage_table[i] == milivolts ) 
+        if ( regul->voltage_table[i] == milivolts )
         {
           LOG_D("idx:%d for %dmV\n\r", (int)i, (int)milivolts);
           return i;
@@ -716,7 +716,7 @@ void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn)
     LOG_I(" Interrupt received\n\r");
 }
 
-void STPMU1_INTn_Callback(PMIC_IRQn IRQn) 
+void STPMU1_INTn_Callback(PMIC_IRQn IRQn)
 {
     BSP_PMIC_INTn_Callback(IRQn);
 }
@@ -846,15 +846,15 @@ static rt_err_t rt_hw_pmic_init_register(void)
 static rt_err_t rt_hw_pmic_init(const char *bus_name)
 {
     PMIC_IRQn irq;
-    
+
     pmic_dev = rt_i2c_bus_device_find(bus_name);
-    
+
     if (pmic_dev == RT_NULL)
     {
         LOG_E("%s bus not found\n", bus_name);
         return -RT_ERROR;
     }
-    
+
     if (stpmu1_read_reg(VERSION_STATUS_REG) != PMIC_VERSION_ID)
     {
         return -RT_EIO;
@@ -863,7 +863,7 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
     STPMU1_Enable_Interrupt(IT_PONKEY_R);
     STPMU1_Enable_Interrupt(IT_PONKEY_F);
     /* enable all irqs  */
-    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) 
+    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++)
     {
         STPMU1_Enable_Interrupt(irq);
     }
@@ -874,18 +874,18 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
 static rt_err_t rt_hw_pmic_deinit(void)
 {
     BSP_PMIC_MspDeInit();
-    
+
     return RT_EOK;
 }
 
 static int pmic_init(void)
 {
     rt_err_t result = RT_EOK;
-    
+
     if (IS_ENGINEERING_BOOT_MODE())
     {
         BSP_PMIC_MspInit();
-        
+
         result = rt_hw_pmic_init(I2C_NAME);
         if(result != RT_EOK)
         {
@@ -893,12 +893,12 @@ static int pmic_init(void)
             rt_hw_pmic_deinit();
             return RT_ERROR;
         }
-        
+
         rt_hw_pmic_init_register();
     }
-    
+
     LOG_I("stpmic init success!");
-        
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h
index b24ccaeaf3..72c4af3a49 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h
@@ -6,11 +6,11 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
+  * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                       opensource.org/licenses/BSD-3-Clause
   *
@@ -98,7 +98,7 @@ typedef struct {
 
 /* Those define should reflect NVM_USER section
  * For ES Eval Configuration this is specified as
- * 	0xF7,
+ *  0xF7,
  0x92,
  0xC0,
  0x02,
@@ -146,12 +146,12 @@ typedef struct {
 
  *
  */
-#define OTP_VINOK_HYST  	((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) 	// nvm_vinok_hyst
-#define OTP_VINOK		  	((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) 	// nvm_vinok
-#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) 	// Otp_ldo4_forced
-#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)	// nvm_longkeypress
-#define OTP_AUTOTURNON  	((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)	// nvm_autoturnon
-#define OTP_CC_KEEPOFF  	((NVM_SECTOR3_REGISTER_0 & 0x01))		// nvm_cc_keepoff
+#define OTP_VINOK_HYST      ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6)  // nvm_vinok_hyst
+#define OTP_VINOK           ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4)  // nvm_vinok
+#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3)  // Otp_ldo4_forced
+#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)  // nvm_longkeypress
+#define OTP_AUTOTURNON      ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)  // nvm_autoturnon
+#define OTP_CC_KEEPOFF      ((NVM_SECTOR3_REGISTER_0 & 0x01))       // nvm_cc_keepoff
 
 /*
  * nvm_rank_buck4:
@@ -176,10 +176,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_BUCK4  	((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) 	// nvm_rank_buck4
-#define OTP_RANK_BUCK3		((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) 	// nvm_rank_buck3
-#define OTP_RANK_BUCK2     	((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) 	// nvm_rank_buck2
-#define OTP_RANK_BUCK1  	((NVM_SECTOR3_REGISTER_1 & 0x03))		// nvm_rank_buck1
+#define OTP_RANK_BUCK4      ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6)  // nvm_rank_buck4
+#define OTP_RANK_BUCK3      ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4)  // nvm_rank_buck3
+#define OTP_RANK_BUCK2      ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2)  // nvm_rank_buck2
+#define OTP_RANK_BUCK1      ((NVM_SECTOR3_REGISTER_1 & 0x03))       // nvm_rank_buck1
 
 
 /*
@@ -205,10 +205,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_LDO4  		((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) 	// nvm_rank_ldo4
-#define OTP_RANK_LDO3		((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) 	// nvm_rank_ldo3
-#define OTP_RANK_LDO2     	((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) 	// nvm_rank_ldo2
-#define OTP_RANK_LDO1  		((NVM_SECTOR3_REGISTER_2 & 0x03))		// nvm_rank_ldo1
+#define OTP_RANK_LDO4       ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6)  // nvm_rank_ldo4
+#define OTP_RANK_LDO3       ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4)  // nvm_rank_ldo3
+#define OTP_RANK_LDO2       ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2)  // nvm_rank_ldo2
+#define OTP_RANK_LDO1       ((NVM_SECTOR3_REGISTER_2 & 0x03))       // nvm_rank_ldo1
 
 /*
  * nvm_clamp_output_buck: Clamp output value to 1.3V max
@@ -238,11 +238,11 @@ nvm_rank_ldo5:
  11:  rank3
  *
  */
-#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) 	// nvm_clamp_output_buck4
-#define OTP_BYPASS_MODE_LDO3  	((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) 	// nvm_bypass_mode_ldo3
-#define OTP_RANK_VREFDDR		((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) 	// nvm_rank_vrefddr
-#define OTP_RANK_LDO6     		((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) 	// nvm_rank_ldo6
-#define OTP_RANK_LDO5  			((NVM_SECTOR3_REGISTER_3 & 0x03))		// nvm_rank_ldo5
+#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7)  // nvm_clamp_output_buck4
+#define OTP_BYPASS_MODE_LDO3    ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6)  // nvm_bypass_mode_ldo3
+#define OTP_RANK_VREFDDR        ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4)  // nvm_rank_vrefddr
+#define OTP_RANK_LDO6           ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2)  // nvm_rank_ldo6
+#define OTP_RANK_LDO5           ((NVM_SECTOR3_REGISTER_3 & 0x03))       // nvm_rank_ldo5
 
 /*
  * nvm_output_buck4: Buck4 default output selection
@@ -267,31 +267,31 @@ nvm_rank_ldo5:
  11:  1.25V
  *
  */
-#define OTP_OUTPUT_BUCK4  		((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) 	// nvm_output_buck4
-#define OTP_OUTPUT_BUCK3		((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) 	// nvm_output_buck3
-#define OTP_OUTPUT_BUCK2     	((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) 	// nvm_output_buck2
-#define OTP_OUTPUT_BUCK1  		((NVM_SECTOR3_REGISTER_4 & 0x03))		// nvm_output_buck1
+#define OTP_OUTPUT_BUCK4        ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6)  // nvm_output_buck4
+#define OTP_OUTPUT_BUCK3        ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4)  // nvm_output_buck3
+#define OTP_OUTPUT_BUCK2        ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2)  // nvm_output_buck2
+#define OTP_OUTPUT_BUCK1        ((NVM_SECTOR3_REGISTER_4 & 0x03))       // nvm_output_buck1
 
 /*
- * [7]	OTP_SWOFF_BY_BOOST_OVP:
+ * [7]  OTP_SWOFF_BY_BOOST_OVP:
  0 -> SWOUT will not turnoff bu boost OVP
  1 -> SWOUT will be turnoff by BOOST OVP
 
- [6]	reserved
+ [6]    reserved
 
- [5:4]	nvm_output_ldo3: LDO3 default output selection
+ [5:4]  nvm_output_ldo3: LDO3 default output selection
  00:  1.8V
  01:  2.5V
  10:  3.3V
  11:  output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog)
 
- [3:2]	nvm_output_ldo2: LDO2 default output selection
+ [3:2]  nvm_output_ldo2: LDO2 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
  11: 3.3V
 
- [1:0]	nvm_output_ldo1: LDO1 default output selection
+ [1:0]  nvm_output_ldo1: LDO1 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
@@ -299,21 +299,21 @@ nvm_rank_ldo5:
 
  *
  */
-#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) 	// OTP_SWOFF_BY_BOOST_OVP
-#define OTP_OUTPUT_LDO3			((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) 	// nvm_output_ldo3
-#define OTP_OUTPUT_LDO2     	((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) 	// nvm_output_ldo2
-#define OTP_OUTPUT_LDO1  		((NVM_SECTOR3_REGISTER_5 & 0x03))		// nvm_output_ldo1
+#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7)  // OTP_SWOFF_BY_BOOST_OVP
+#define OTP_OUTPUT_LDO3         ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4)  // nvm_output_ldo3
+#define OTP_OUTPUT_LDO2         ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2)  // nvm_output_ldo2
+#define OTP_OUTPUT_LDO1         ((NVM_SECTOR3_REGISTER_5 & 0x03))       // nvm_output_ldo1
 
 /*
- * 	[7:4]	reserved
+ *  [7:4]   reserved
  *
- [3:2]	nvm_output_ldo6: LDO6 default output selection
+ [3:2]  nvm_output_ldo6: LDO6 default output selection
  00:  1.0V
  01:  1.2V
  10:  1.8V
  11:  3.3V
 
- [1:0]	nvm_output_ldo5: LDO5 default output selection
+ [1:0]  nvm_output_ldo5: LDO5 default output selection
  00:  1.8V
  01:  2.5V
  10:  2.9V
@@ -321,8 +321,8 @@ nvm_rank_ldo5:
  *
  */
 
-#define OTP_OUTPUT_LDO6     	((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) 	// nvm_output_ldo6
-#define OTP_OUTPUT_LDO5  		((NVM_SECTOR3_REGISTER_6 & 0x03))		// nvm_output_ldo5
+#define OTP_OUTPUT_LDO6         ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2)  // nvm_output_ldo6
+#define OTP_OUTPUT_LDO5         ((NVM_SECTOR3_REGISTER_6 & 0x03))       // nvm_output_ldo5
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define BIT(_x)  (1<<(_x))
@@ -417,7 +417,7 @@ nvm_rank_ldo5:
 #define LDO_BUCK_PULL_DOWN_MASK     0x03
 
 
-/* Main PMIC Control Register 
+/* Main PMIC Control Register
  * MAIN_CONTROL_REG
  * Address : 0x10
  * */
@@ -427,7 +427,7 @@ nvm_rank_ldo5:
 #define RESTART_REQUEST_ENABLED     BIT(1)
 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
 
-/* Main PMIC PADS Control Register 
+/* Main PMIC PADS Control Register
  * PADS_PULL_REG
  * Address : 0x11
  * */
@@ -438,7 +438,7 @@ nvm_rank_ldo5:
 #define PONKEY_PU_ACTIVE            BIT(0)
 
 
-/* Main PMIC VINLOW Control Register 
+/* Main PMIC VINLOW Control Register
  * VIN_CONTROL_REGC DMSC
  * Address : 0x15
  * */
@@ -452,7 +452,7 @@ nvm_rank_ldo5:
 #define VINLOW_CTRL_REG_MASK        0xFF
 
 
-/* USB Control Register 
+/* USB Control Register
  * Address : 0x40
  * */
 #define BOOST_OVP_DISABLED          BIT(7)
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c
index 3aac57603d..a98b280f1b 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c
index 70fa977359..7f716c1dae 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2020-07-07     thread-liu   first version
  */
- 
+
 #include <board.h>
 #include <drv_qspi.h>
 #include <rtdevice.h>
@@ -29,7 +29,7 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
 {
   GPIO_InitTypeDef GPIO_InitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-  
+
   if(hqspi->Instance==QUADSPI)
   {
   /* USER CODE BEGIN QUADSPI_MspInit 0 */
@@ -45,16 +45,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
    /* USER CODE END QUADSPI_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_QSPI_CLK_ENABLE();
-  
+
     __HAL_RCC_GPIOF_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**QUADSPI GPIO Configuration    
+    /**QUADSPI GPIO Configuration
     PF6     ------> QUADSPI_BK1_IO3
     PF7     ------> QUADSPI_BK1_IO2
     PF8     ------> QUADSPI_BK1_IO0
     PF9     ------> QUADSPI_BK1_IO1
     PF10     ------> QUADSPI_CLK
-    PB6     ------> QUADSPI_BK1_NCS 
+    PB6     ------> QUADSPI_BK1_NCS
     */
     GPIO_InitStruct.Pin = GPIO_PIN_10;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -62,14 +62,14 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
     GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
     HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
-    
+
     GPIO_InitStruct.Pin = GPIO_PIN_6;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_PULLUP;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
     GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-    
+
     GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_6;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -104,14 +104,14 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
     GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
     HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-    
+
     GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
     GPIO_InitStruct.Alternate = GPIO_AF11_QUADSPI;
     HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-    
+
   /* USER CODE BEGIN QUADSPI_MspInit 1 */
 
   /* USER CODE END QUADSPI_MspInit 1 */
@@ -133,8 +133,8 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
   /* USER CODE END QUADSPI_MspDeInit 0 */
     /* Peripheral clock disable */
     __HAL_RCC_QSPI_CLK_DISABLE();
-  
-    /**QUADSPI GPIO Configuration    
+
+    /**QUADSPI GPIO Configuration
     PC0     ------> QUADSPI_BK2_NCS
     PF10     ------> QUADSPI_CLK
     PB6     ------> QUADSPI_BK1_NCS
@@ -145,10 +145,10 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
     PF6     ------> QUADSPI_BK1_IO3
     PH2     ------> QUADSPI_BK2_IO0
     PF8     ------> QUADSPI_BK1_IO0
-    PF9     ------> QUADSPI_BK1_IO1 
+    PF9     ------> QUADSPI_BK1_IO1
     */
     HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
-    
+
     HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10);
 
     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
@@ -156,7 +156,7 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
     HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2);
 
     HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_10);
-    
+
   /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
 
   /* USER CODE END QUADSPI_MspDeInit 1 */
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c
index 44eba3be91..78475ec7e8 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ static rt_err_t rs485_output(rt_device_t dev, void * buffer)
 static rt_err_t rs485_input(rt_device_t dev, rt_size_t size)
 {
     rt_sem_release(&rx_sem);
-    
+
     return RT_EOK;
 }
 
@@ -38,13 +38,13 @@ int rs485_send_data(char *tbuf, rt_uint16_t t_len)
 {
     /* change rs485 mode */
     RS485_OUT;
-    
+
     /* send data */
     rt_device_write(serial, 0, tbuf, t_len);
-    
+
     /* change rs485 mode */
     RS485_IN;
-    
+
     return RT_EOK;
 }
 
@@ -59,10 +59,10 @@ static void rs485_thread_entry(void *parameter)
         {
             rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
         }
-        
+
         /* The data read through the serial port output dislocation */
         ch = ch + 1;
-        
+
         /* send char */
         rs485_send_data(&ch, 1);
     }
@@ -77,20 +77,20 @@ static int rs485_init(void)
     {
         rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME);
         return RT_ERROR;
-    }  
+    }
 
     rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
 
     /* set receive data callback function */
     rt_device_set_rx_indicate(serial, rs485_input);
-    
+
     /* set the send completion callback function */
     rt_device_set_tx_complete(serial, rs485_output);
-        
+
     rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT);
-    
+
     RS485_IN;
-    
+
     rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
     /* create rs485 thread */
     rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10);
@@ -103,8 +103,8 @@ static int rs485_init(void)
     {
         return RT_ERROR;
     }
-    
-    return RT_EOK;    
+
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rs485_init);
 
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h
index 01edf84ae8..0d9767ac04 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@ extern "C" {
 
 #define RS485_SEND_MODE      0
 #define RS485_RECV_MODE      1
-    
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c
index 3ef28f4e85..bb6e92584f 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ struct stm32_sd
     struct rt_semaphore sd_lock;
     volatile rt_uint8_t write_flage;
     volatile rt_uint8_t read_flage;
-    volatile rt_base_t level;    
+    volatile rt_base_t level;
 };
 static struct stm32_sd sd_device;
 
@@ -47,7 +47,7 @@ __attribute__((at(SDCARD_ADDR))) static rt_uint32_t cache_buf[SDIO_BUFF_SIZE];
 #elif defined ( __GNUC__ )
 static rt_uint32_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection")));
 #elif defined(__ICCARM__)
-#pragma location = SDCARD_ADDR 
+#pragma location = SDCARD_ADDR
 __no_init static rt_uint32_t cache_buf[SDIO_BUFF_SIZE];
 #endif
 
@@ -79,7 +79,7 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
 
 static rt_err_t rt_hw_sd_is_detected(void)
 {
-   return rt_pin_read(DETECT_PIN); 
+   return rt_pin_read(DETECT_PIN);
 }
 
 static rt_err_t rt_hw_sd_init(void)
@@ -94,46 +94,46 @@ static rt_err_t rt_hw_sd_init(void)
         LOG_E("can't find sd card!");
         return RT_ERROR;
     }
-    
+
     SDCARD_Handler.Instance = SDMMC1;
     HAL_SD_DeInit(&SDCARD_Handler);
-    
+
   /* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock
-     else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV]. 
+     else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV].
      SDMMC Kernel Clock = 99MHz, SDMMC Clock frequency = 50MHz  */
-    
+
     SDCARD_Handler.Init.ClockDiv             = 1;
-    SDCARD_Handler.Init.ClockPowerSave       = SDMMC_CLOCK_POWER_SAVE_DISABLE;      
-    SDCARD_Handler.Init.ClockEdge            = SDMMC_CLOCK_EDGE_FALLING;             
-    SDCARD_Handler.Init.HardwareFlowControl  = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 
-    SDCARD_Handler.Init.BusWide              = SDMMC_BUS_WIDE_4B;                                    
-    
+    SDCARD_Handler.Init.ClockPowerSave       = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+    SDCARD_Handler.Init.ClockEdge            = SDMMC_CLOCK_EDGE_FALLING;
+    SDCARD_Handler.Init.HardwareFlowControl  = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+    SDCARD_Handler.Init.BusWide              = SDMMC_BUS_WIDE_4B;
+
     if (HAL_SD_Init(&SDCARD_Handler) != RT_EOK)
     {
         LOG_E("sd device init error!");
-        return RT_ERROR; 
+        return RT_ERROR;
     }
 
     if (HAL_SD_ConfigWideBusOperation(&SDCARD_Handler, SDMMC_BUS_WIDE_4B) != RT_EOK)
     {
         LOG_E("sd bus config error!");
-        return RT_ERROR;   
+        return RT_ERROR;
     }
 
     if (HAL_SD_GetCardInfo(&SDCARD_Handler, &SDCardInfo) != RT_EOK)
     {
         LOG_E("sd get card info error!");
-        return RT_ERROR;    
+        return RT_ERROR;
     }
-    
+
     rt_thread_mdelay(100);
-    
+
     if(HAL_SD_GetCardState(&SDCARD_Handler) != HAL_SD_CARD_TRANSFER)
     {
         LOG_E("sd get card state error!");
-        return RT_ERROR; 
+        return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
@@ -145,7 +145,7 @@ static void rt_hw_sd_deinit(void)
 static rt_err_t sdcard_wait_ok(void)
 {
     rt_uint32_t tick_start = 0;
-    
+
     tick_start = rt_tick_get();
     while ((rt_tick_get() - tick_start) < SD_TIMEOUT)
     {
@@ -166,19 +166,19 @@ void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
     else
     {
         rt_pin_write(LDO_PIN, PIN_LOW);
-    } 
+    }
 }
 
 static rt_err_t rt_sdcard_init(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
     struct stm32_sd *sd = (struct stm32_sd *)dev;
-    
+
     if (rt_sem_init(&sd->sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
     {
         LOG_E("init sd lock semaphore failed\n");
     }
-    
+
     return RT_EOK;
 }
 
@@ -207,24 +207,24 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer,
 {
     RT_ASSERT(dev != RT_NULL);
     struct stm32_sd *sd = (struct stm32_sd *)dev;
-    
+
     rt_uint8_t ret = RT_EOK;
     volatile uint32_t tickstart = 0;
     sd->read_flage  = 0;
-    
+
     rt_memset(cache_buf, 0x00, BLOCKSIZE * count);
-    
+
     ret = sdcard_wait_ok();
     if (ret != RT_EOK)
     {
         LOG_D("sdmmc busy!");
         return 0;
     }
-    
+
     rt_sem_take(&sd->sd_lock, RT_WAITING_FOREVER);
     ret = HAL_SD_ReadBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (uint32_t)sector, count);
     rt_sem_release(&sd->sd_lock);
-    
+
     /* Wait that writing process is completed or a timeout occurs */
     tickstart = rt_tick_get();
     if (ret == HAL_OK)
@@ -247,7 +247,7 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer,
               {
                  sd->level=rt_hw_interrupt_disable();
                  rt_memcpy((rt_uint8_t *)(buffer), cache_buf, BLOCKSIZE * count);
-                 rt_hw_interrupt_enable(sd->level); 
+                 rt_hw_interrupt_enable(sd->level);
 #if defined(SDMMC_RX_DUMP)
                 rt_kprintf("\nsd rx: \n");
                 dump_hex(cache_buf, BLOCKSIZE * count);
@@ -257,7 +257,7 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer,
           }
         }
     }
-    
+
     return 0;
 }
 
@@ -275,14 +275,14 @@ static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *b
     struct stm32_sd *sd = (struct stm32_sd *)dev;
     rt_uint32_t i = 0;
     rt_uint8_t ret = RT_EOK;
-    
+
     for (i = 0; i < count; i++)
     {
         sd->level = rt_hw_interrupt_disable();
         rt_memset(cache_buf, 0x00, BLOCKSIZE);
         rt_memcpy(cache_buf, (rt_uint32_t *)((uintptr_t)buffer + BLOCKSIZE * i), BLOCKSIZE);
         rt_hw_interrupt_enable(sd->level);
-        
+
 #if defined(SDMMC_TX_DUMP)
         rt_kprintf("\nsd tx: \n");
         dump_hex(cache_buf, BLOCKSIZE);
@@ -303,14 +303,14 @@ static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *b
         rt_completion_wait(&tx_comp,RT_WAITING_FOREVER);
 
     }
-    
+
     return count;
 }
 
 static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
     {
         struct rt_device_blk_geometry *geometry;
@@ -372,9 +372,9 @@ int rt_hw_sdcard_init(void)
     sd_device.sdcard.user_data = &SDCardInfo;
 
     rt_device_register(&sd_device.sdcard, "sd_card", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
-    
+
     LOG_I("sd card init success!");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rt_hw_sdcard_init);
@@ -383,7 +383,7 @@ INIT_DEVICE_EXPORT(rt_hw_sdcard_init);
 int mnt_init(void)
 {
     rt_device_t sd_dev = RT_NULL;
-    
+
     LOG_I("init sd card file system.");
 #if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP)
     rt_thread_delay(3000);
@@ -396,7 +396,7 @@ int mnt_init(void)
         LOG_E("can't find sd deivce name!");
         return RT_ERROR;
     }
-    
+
     if (dfs_mount("sd_card", "/", "elm", 0, 0) != 0)
     {
         rt_kprintf("file system mount failed!\n");
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c
index 14efc094e5..4aee045825 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -35,7 +35,7 @@ struct sound_device
 {
     struct rt_audio_device audio;
     struct rt_audio_configure replay_config;
-    rt_device_t decoder; 
+    rt_device_t decoder;
     rt_uint8_t *tx_fifo;
     rt_uint8_t volume;
 };
@@ -70,7 +70,7 @@ static void rt_hw_sai2a_init(void)
     hsai_BlockA2.FrameInit.FSDefinition      = SAI_FS_CHANNEL_IDENTIFICATION;
     hsai_BlockA2.FrameInit.FSPolarity        = SAI_FS_ACTIVE_LOW;
     hsai_BlockA2.FrameInit.FSOffset          = SAI_FS_BEFOREFIRSTBIT;
-    
+
     hsai_BlockA2.SlotInit.FirstBitOffset     = 0;
     hsai_BlockA2.SlotInit.SlotSize           = SAI_SLOTSIZE_DATASIZE;
     hsai_BlockA2.SlotInit.SlotNumber         = 2;
@@ -218,7 +218,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap
 
     return result;
 }
-    
+
 static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
 {
     rt_err_t result = RT_EOK;
@@ -238,9 +238,9 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c
             rt_uint8_t volume = caps->udata.value;
 
             rt_device_control(snd_dev->decoder, SET_VOLUME, &volume);
-            
+
             snd_dev->volume = volume;
-            
+
             LOG_D("set volume %d", volume);
             break;
         }
@@ -315,16 +315,16 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
     rt_err_t result = RT_EOK;
     struct sound_device *snd_dev;
     rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE;
-    
+
     RT_ASSERT(audio != RT_NULL);
     snd_dev = (struct sound_device *)audio->parent.user_data;
-    
+
     rt_hw_sai2a_init();
-    
+
     /* set default params */
     SAIA_Frequency_Set(snd_dev->replay_config.samplerate);
     SAIA_Channels_Set(snd_dev->replay_config.channels);
-    
+
     /* set audio play type */
     rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type);
     /* open lowlevel audio device */
@@ -337,7 +337,7 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
         LOG_E("can't find low level audio device!");
         return RT_ERROR;
     }
- 
+
     return result;
 }
 
@@ -345,17 +345,17 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
 {
     struct sound_device *snd_dev;
     rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE;
-    
+
     RT_ASSERT(audio != RT_NULL);
     snd_dev = (struct sound_device *)audio->parent.user_data;
-    
+
     if (stream == AUDIO_STREAM_REPLAY)
     {
         LOG_D("open sound device");
-        
+
         rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type);
         rt_device_control(snd_dev->decoder, START_PLAY, RT_NULL);
-        
+
         if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK)
         {
             return RT_ERROR;
@@ -368,7 +368,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
 static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
 {
     RT_ASSERT(audio != RT_NULL);
-    
+
     if (stream == AUDIO_STREAM_REPLAY)
     {
         HAL_SAI_DMAStop(&hsai_BlockA2);
@@ -385,7 +385,7 @@ static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf
 
     RT_ASSERT(audio != RT_NULL);
     device = (struct sound_device *)audio->parent.user_data;
-    
+
     info->buffer      = device->tx_fifo;
     info->total_size  = TX_FIFO_SIZE;
     info->block_size  = TX_FIFO_SIZE / 2;
@@ -407,7 +407,7 @@ int rt_hw_sound_init(void)
 {
     rt_err_t result = RT_EOK;
     struct rt_device *device = RT_NULL;
-    
+
     rt_memset(AUDIO_TX_FIFO, 0, TX_FIFO_SIZE);
     snd_dev.tx_fifo = AUDIO_TX_FIFO;
 
@@ -416,7 +416,7 @@ int rt_hw_sound_init(void)
     snd_dev.replay_config.channels   = 2;
     snd_dev.replay_config.samplebits = 16;
     snd_dev.volume                   = 55;
-    
+
     /* find lowlevel decoder device*/
     snd_dev.decoder = rt_device_find("decoder");
     if (snd_dev.decoder == RT_NULL)
@@ -424,19 +424,19 @@ int rt_hw_sound_init(void)
         LOG_E("cant't find lowlevel decoder deivce!");
         return RT_ERROR;
     }
-    
+
     /* register sound device */
     snd_dev.audio.ops = &snd_ops;
     result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
     /* check sound device register success or not */
     if (result != RT_EOK)
     {
-        device = &(snd_dev.audio.parent); 
+        device = &(snd_dev.audio.parent);
         rt_device_unregister(device);
         LOG_E("sound device init error!");
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
@@ -485,7 +485,7 @@ int wavplay_sample(int argc, char **argv)
 #define BUFSZ   1024
 #define SOUND_DEVICE_NAME    "sound0"
 static rt_device_t sound_dev;
-    
+
     int fd = -1;
     uint8_t *buffer = NULL;
     struct wav_info *info = NULL;
@@ -528,9 +528,9 @@ static rt_device_t sound_dev;
 
     rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY);
 
-    caps.main_type               = AUDIO_TYPE_OUTPUT;                          
+    caps.main_type               = AUDIO_TYPE_OUTPUT;
     caps.sub_type                = AUDIO_DSP_PARAM;
-    caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; 
+    caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec;
     caps.udata.config.channels   = info->fmt_block.wav_format.Channels;
     caps.udata.config.samplebits = 16;
     rt_device_control(sound_dev, AUDIO_CTL_CONFIGURE, &caps);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c
index 6230b49a4f..7d0e665f64 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,7 +19,7 @@
 
 struct stm32_spdifrx
 {
-    struct rt_device dev;  
+    struct rt_device dev;
     SPDIFRX_HandleTypeDef spdifrx;
     SAI_HandleTypeDef sai4;
     volatile rt_uint8_t complate;
@@ -46,7 +46,7 @@ static void sai4a_init(SAI_HandleTypeDef* sai)
     sai->Init.DataSize            = SAI_DATASIZE_24;
     sai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
     sai->Init.ClockStrobing       = SAI_CLOCKSTROBING_FALLINGEDGE;
-    
+
     sai->FrameInit.FrameLength       = 64;
     sai->FrameInit.ActiveFrameLength = 32;
     sai->FrameInit.FSDefinition      = SAI_FS_STARTFRAME;
@@ -57,7 +57,7 @@ static void sai4a_init(SAI_HandleTypeDef* sai)
     sai->SlotInit.SlotSize       = SAI_SLOTSIZE_DATASIZE;
     sai->SlotInit.SlotNumber     = 4;
     sai->SlotInit.SlotActive     = SAI_SLOTACTIVE_ALL;
-    
+
     if (HAL_SAI_Init(sai) != HAL_OK)
     {
         Error_Handler();
@@ -65,12 +65,12 @@ static void sai4a_init(SAI_HandleTypeDef* sai)
 }
 
 void DMA1_Stream7_IRQHandler(void)
-{ 
+{
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_spdifrx_rx);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -79,9 +79,9 @@ void DMA1_Stream2_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_sai4_a);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -95,10 +95,10 @@ static rt_err_t _init(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
     struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev;
-    
+
     device->spdifrx.Instance = SPDIFRX;
-    HAL_SPDIFRX_DeInit(&device->spdifrx); 
-    
+    HAL_SPDIFRX_DeInit(&device->spdifrx);
+
     device->spdifrx.Init.InputSelection     = SPDIFRX_INPUT_IN1;
     device->spdifrx.Init.Retries            = SPDIFRX_MAXRETRIES_15;
     device->spdifrx.Init.WaitForActivity    = SPDIFRX_WAITFORACTIVITY_ON;
@@ -106,53 +106,53 @@ static rt_err_t _init(rt_device_t dev)
     device->spdifrx.Init.DataFormat         = SPDIFRX_DATAFORMAT_MSB;
     device->spdifrx.Init.StereoMode         = SPDIFRX_STEREOMODE_ENABLE;
     device->spdifrx.Init.PreambleTypeMask   = SPDIFRX_PREAMBLETYPEMASK_ON;
-    device->spdifrx.Init.ChannelStatusMask  = SPDIFRX_CHANNELSTATUS_ON;  
-    
+    device->spdifrx.Init.ChannelStatusMask  = SPDIFRX_CHANNELSTATUS_ON;
+
     if (HAL_SPDIFRX_Init(&device->spdifrx) != HAL_OK)
     {
         return RT_ERROR;
     }
-    
+
     sai4a_init(&device->sai4);
-    
+
     rt_spdifrx.complate = RESET;
-    
+
     return RT_EOK;
 }
 
 static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     return RT_EOK;
 }
 
 static rt_err_t _close(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     return RT_EOK;
 }
 
 static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
     rt_uint32_t tickstart = 0;
-    
+
     RT_ASSERT(dev != RT_NULL);
     struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev;
     rt_err_t result = RT_EOK;
-    
+
     result = HAL_SPDIFRX_ReceiveDataFlow_DMA(&device->spdifrx, (uint32_t *)buffer, size);
     if (result != HAL_OK)
     {
         return 0;
     }
-    
+
     if(device->spdifrx.ErrorCode != HAL_SPDIFRX_ERROR_NONE)
     {
         return 0;
     }
-    
+
     tickstart = rt_tick_get();
     while (rt_spdifrx.complate == RESET)
     {
@@ -161,9 +161,9 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si
             return 0;
         }
     }
-    
+
     rt_spdifrx.complate = RESET;
-    
+
     return size;
 }
 
@@ -173,13 +173,13 @@ static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_si
 
     struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev;
     rt_err_t result = RT_EOK;
-    
+
     result = HAL_SAI_Transmit_DMA(&device->sai4, (rt_uint8_t *)buffer, size);
     if (result != HAL_OK)
     {
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
@@ -203,10 +203,10 @@ int spdifrx_init(void)
 
     rt_device_register(&rt_spdifrx.dev, "spdifrx", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
     rt_device_init(&rt_spdifrx.dev);
-    
+
     LOG_I("spdifrx init success!");
-    
-    return RT_EOK; 
+
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(spdifrx_init);
 
@@ -247,8 +247,8 @@ static int spdifrx_sample(int argc, char **argv)
         rt_kprintf("spdifrx_sample\n");
         return -1;
     }
-    
-    /* 16 bit Data Buffer for Transmission */ 
+
+    /* 16 bit Data Buffer for Transmission */
     static rt_uint16_t tx_buffer[64] = {
     0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C, 0x5D5E, 0x5F60,
     0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70,
@@ -258,11 +258,11 @@ static int spdifrx_sample(int argc, char **argv)
     0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70,
     0x7172, 0x7374, 0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
     0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C, 0x8D8E, 0x8F90};
-    
+
     static rt_uint32_t *rx_buffer = NULL;
     rt_uint8_t size = 64;
     struct rt_device *dev = RT_NULL;
-    
+
     dev = rt_device_find("spdifrx");
     if (dev == RT_NULL)
     {
@@ -270,31 +270,31 @@ static int spdifrx_sample(int argc, char **argv)
     }
 
     rt_device_open(dev, RT_DEVICE_OFLAG_RDWR);
-    
+
     rt_kprintf("spdifrx test tx data : \n");
     dump_hex((rt_uint8_t *)tx_buffer, size);
-    
+
     rx_buffer = (rt_uint32_t *)rt_malloc(size);
-    
+
     rt_device_write(dev, 0, tx_buffer, size);
     rt_device_read(dev, 0, rx_buffer, size);
-    
-    /* Compare the received data with the expected one */    
+
+    /* Compare the received data with the expected one */
     while (size--)
     {
         if (((rx_buffer[size] & 0x00ffff00) >>  8) != (tx_buffer[size]))
         {
             rt_kprintf("spdirex loopback mode test failed!\n");
-            
+
             return RT_ERROR;
         }
     }
-    
+
     rt_kprintf("spdifrx rx : \n");
     dump_hex((rt_uint8_t *)rx_buffer, size);
-    
+
     rt_kprintf("spdirex loopback mode test success!\n");
-    
+
     return RT_EOK;
 }
 MSH_CMD_EXPORT(spdifrx_sample, spdifrx loopback test);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c
index b162d76b0f..cea18205fd 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,7 +22,7 @@
 
 struct wm8994_dev
 {
-    struct rt_device dev; 
+    struct rt_device dev;
     struct rt_i2c_bus_device *i2c_bus;
     rt_uint16_t id;
     rt_uint16_t type;
@@ -34,12 +34,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint
 {
     struct rt_i2c_msg msg[2] = {0, 0};
     static rt_uint8_t i2c_reg[2] = {0, 0};
-    
+
     RT_ASSERT(bus != RT_NULL);
-    
+
     i2c_reg[0] = ((uint16_t)(reg >> 8) & 0xFF);
     i2c_reg[1] = ((uint16_t)(reg) & 0xFF);
-    
+
     msg[0].addr  = CHIP_ADDRESS;
     msg[0].flags = RT_I2C_WR;
     msg[0].buf   = i2c_reg;
@@ -68,7 +68,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uin
 
     buf[0] = ((uint16_t)(reg >> 8) & 0xFF);
     buf[1] = ((uint16_t)(reg) & 0xFF);
-    
+
     buf[2] = ((uint16_t)(data >> 8) & 0xFF);
     buf[3] = ((uint16_t)(data) & 0xFF);
 
@@ -247,14 +247,14 @@ static rt_err_t wm8994_set_input_mode(struct rt_i2c_bus_device *bus, rt_uint16_t
         /* Actually, no other input devices supported */
         break;
     }
-    
+
     return RT_EOK;
 }
 
 static rt_err_t _wm8994_init(struct wm8994_dev *dev)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     /* wm8994 Errata Work-Arounds */
     write_reg(dev->i2c_bus, 0x0102, 0x0003);
     write_reg(dev->i2c_bus, 0x0817, 0x0000);
@@ -275,7 +275,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev)
         write_reg(dev->i2c_bus, 0x0001, 0x0003);
     }
     rt_thread_mdelay(50);
-    
+
     if ((dev->type & 0x000F) != 0 )
     {
         /* Path Configurations for output */
@@ -297,7 +297,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev)
         /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
         write_reg(dev->i2c_bus, 0x0300, 0x4010);
     }
-    
+
     /* slave mode */
     write_reg(dev->i2c_bus, 0x0302, 0x0000);
 
@@ -308,7 +308,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev)
     write_reg(dev->i2c_bus, 0x0200, 0x0001);
 
     /* Audio output selected */
-    if ((dev->type & 0x000F) != 0 ) 
+    if ((dev->type & 0x000F) != 0 )
     {
         if (dev->type & OUTPUT_DEVICE_HEADPHONE)
         {
@@ -409,7 +409,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev)
     }
 
     /* Audio input selected */
-    if ((dev->type & 0x01F0) != 0 ) 
+    if ((dev->type & 0x01F0) != 0 )
     {
         if ((dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_2))
         {
@@ -449,17 +449,17 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev)
             write_reg(dev->i2c_bus, 0x0410, 0x1800);
         }
     }
-    
+
     /* Return communication control value */
     return RT_EOK;
-    
+
 }
 
 static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id)
 {
     rt_uint8_t read_value[2];
-        
-    read_reg(bus, 0x0000, 2, read_value); 
+
+    read_reg(bus, 0x0000, 2, read_value);
     *id  = ((uint16_t)(read_value[0] << 8) & 0xFF00);
     *id |= ((uint16_t)(read_value[1])& 0x00FF);
 
@@ -468,9 +468,9 @@ static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id)
         LOG_E("error id: 0x%04x", *id);
         return RT_ERROR;
     }
-    
+
     LOG_I("wm8994 init success, id: %04x", *id);
-        
+
     return RT_EOK;
 }
 
@@ -493,7 +493,7 @@ static rt_err_t _set_mute(struct rt_i2c_bus_device *bus, uint32_t cmd)
         /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
         write_reg(bus, 0x422, 0x0010);
     }
-    
+
     return RT_EOK;
 }
 
@@ -507,7 +507,7 @@ static rt_err_t _play(struct rt_i2c_bus_device *bus)
 static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_uint8_t volume)
 {
     rt_uint8_t convertedvol = VOLUME_CONVERT(volume);
-    
+
     if (type & 0x000F)
     {
         /* Output volume */
@@ -575,9 +575,9 @@ static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_
 static rt_err_t _get_volume(struct rt_i2c_bus_device *bus, rt_uint32_t *value)
 {
     rt_uint8_t read_value[2];
-    
+
     read_reg(bus, 0x001C, 2, read_value);
-    
+
     *value  = ((uint16_t)(read_value[0] << 8) & 0xFF00);
     *value |= ((uint16_t)(read_value[1])& 0x00FF);
 
@@ -618,11 +618,11 @@ static rt_err_t _set_frequency(struct rt_i2c_bus_device *bus, rt_uint32_t freq)
 
         case AUDIO_FREQUENCY_44K:
             write_reg(bus, 0x210, 0x0073);
-        break; 
+        break;
 
         default:
             write_reg(bus, 0x210, 0x0083);
-        break; 
+        break;
     }
 
     return RT_EOK;
@@ -641,36 +641,36 @@ static rt_err_t rt_wm8994_init(rt_device_t dev)
     RT_ASSERT(dev != RT_NULL);
     rt_err_t result = RT_EOK;
     static rt_uint16_t old_type = DEVICE_NONE;
-        
+
     struct wm8994_dev *device = (struct wm8994_dev *)dev;
-    
+
     if (old_type == device->type)
     {
         return RT_EOK;
     }
-    
+
     old_type = device->type;
-    
+
     device->i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
     if (device->i2c_bus == RT_NULL)
     {
         LOG_E("can't find %c deivce", I2C_NAME);
         return RT_ERROR;
     }
-    
+
     result = _wm8994_init(device);
     /* set volume */
     _set_volume(device->i2c_bus, device->type, VOLUME_CONVERT(100));
     /* set frequency */
     _set_frequency(device->i2c_bus, AUDIO_FREQUENCY_44K);
-    
+
     return result;
 }
 
 static rt_err_t rt_wm8994_open(rt_device_t dev, rt_uint16_t oflag)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     return RT_EOK;
 }
 
@@ -678,7 +678,7 @@ static rt_err_t rt_wm8994_close(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
     struct wm8994_dev *device = (struct wm8994_dev *)dev;
-    
+
     _set_mute(device->i2c_bus, AUDIO_MUTE_ON);
 
     /* Mute the AIF1 Timeslot 0 DAC1 path */
@@ -721,19 +721,19 @@ static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args)
         case GET_ID:
             result = _read_id(device->i2c_bus, (rt_uint16_t*)args);
             break;
-        
+
         case SET_FREQUENCE:
             result = _set_frequency(device->i2c_bus, (*(rt_uint32_t *)args));
             break;
-        
+
         case SET_VOLUME:
             result = _set_volume(device->i2c_bus, device->type, (*(rt_uint8_t*)args));
             break;
-        
+
         case GET_VOLUME:
             result = _get_volume(device->i2c_bus, (rt_uint32_t *)args);
             break;
-        
+
         case SET_MUTE:
             result = _set_mute(device->i2c_bus, (*(rt_uint32_t*)args));
             break;
@@ -741,23 +741,23 @@ static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args)
         case SET_RESET:
             result = _reset(device->i2c_bus);
             break;
-        
+
         case START_PLAY:
             result = _play(device->i2c_bus);
             break;
-        
+
         case SET_PLAY_TYPE:
             device->type = 0;
             device->type = *(rt_uint32_t *)args;
             rt_wm8994_init(dev);
             break;
-        
+
         default:
             LOG_D("not support cmd");
             break;
     }
-    
-    return result;  
+
+    return result;
 }
 
 int wm8994_init(void)
@@ -772,9 +772,9 @@ int wm8994_init(void)
     rt_wm8994.dev.user_data = RT_NULL;
 
     rt_device_register(&rt_wm8994.dev, "decoder", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
-    
+
     LOG_I("lowlevel decoder device init success!");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(wm8994_init);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h
index 872e02b162..73921ffaa1 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-    
+
 enum{
     GET_ID,
     SET_FREQUENCE,
@@ -65,7 +65,7 @@ enum{
 #define AUDIO_FREQUENCY_22K           ((uint32_t)22050)
 #define AUDIO_FREQUENCY_16K           ((uint32_t)16000)
 #define AUDIO_FREQUENCY_11K           ((uint32_t)11025)
-#define AUDIO_FREQUENCY_8K            ((uint32_t)8000)  
+#define AUDIO_FREQUENCY_8K            ((uint32_t)8000)
 
 #define VOLUME_CONVERT(Volume)        (((Volume) > 100)? 100:((uint8_t)(((Volume) * 63) / 100)))
 #define VOLUME_IN_CONVERT(Volume)     (((Volume) >= 100)? 239:((uint8_t)(((Volume) * 240) / 100)))
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c
index 4e9910aa95..77bde7d7b7 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,15 +22,15 @@
 #define LED5_PIN  GET_PIN(A, 14)
 
 static rt_uint8_t feed_flag = 0;
-static WWDG_HandleTypeDef hwwdg1;  
+static WWDG_HandleTypeDef hwwdg1;
 
 void WWDG1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_WWDG_IRQHandler(&hwwdg1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -50,18 +50,18 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
 static void wwdg_init()
 {
     rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
-        
+
     hwwdg1.Instance       = WWDG1;
     hwwdg1.Init.Prescaler = WWDG_PRESCALER_8;
     hwwdg1.Init.Window    = 0X5F;
     hwwdg1.Init.Counter   = 0x7F;
     hwwdg1.Init.EWIMode   = WWDG_EWI_ENABLE;
-      
+
     if (HAL_WWDG_Init(&hwwdg1) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     feed_flag = 1;
 }
 
@@ -69,10 +69,10 @@ static void wwdg_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hwwdg1.Instance->CFR &= ~(7 << 11);     /* clear WDGTB[2:0] */
-    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */	
+    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */
 }
 
 static void wwdg_stop(void)
@@ -85,7 +85,7 @@ static int wwdg_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "run"))
-        { 
+        {
             wwdg_init();
         }
         else if (!strcmp(argv[1], "set"))
@@ -93,7 +93,7 @@ static int wwdg_sample(int argc, char *argv[])
             if (argc > 2)
             {
                 wwdg_control(atoi(argv[2]));
-            }     
+            }
         }
         else if (!strcmp(argv[1], "stop"))
         {
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c
index 42aec448f8..670a00e35e 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -146,7 +146,7 @@ static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_v
             return RT_ETIMEOUT;
         }
     }
-    
+
     return RT_EOK;
 }
 
@@ -155,7 +155,7 @@ static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
     uint16_t reg_value = 0;
     uint32_t status = 0;
     volatile uint32_t tickstart = 0;
-    
+
     /* Take care not to alter MDC clock configuration */
     status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
     /* Set up a read operation */
@@ -228,10 +228,10 @@ static void HAL_ETH_MspInit(void)
 {
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     if(IS_ENGINEERING_BOOT_MODE())
     {
-        /** Initializes the peripherals clock 
+        /** Initializes the peripherals clock
         */
         PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH;
         PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4;
@@ -240,10 +240,10 @@ static void HAL_ETH_MspInit(void)
             Error_Handler();
         }
     }
-  
+
     /* Enable SYSCFG clock */
     __HAL_RCC_SYSCFG_CLK_ENABLE();
-    
+
     /* Enable GPIO clocks */
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
@@ -254,21 +254,21 @@ static void HAL_ETH_MspInit(void)
 
     /* Select RGMII interface mode */
     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII);
-    
+
     /* Enable Ethernet MAC clock */
     __HAL_RCC_ETH1MAC_CLK_ENABLE();
     __HAL_RCC_ETH1TX_CLK_ENABLE();
     __HAL_RCC_ETH1RX_CLK_ENABLE();
-    
+
     /**ETH1 GPIO Configuration
     PA1     ------>  ETH1_RX_CLK
-    PA2     ------>  ETH1_MDIO    
+    PA2     ------>  ETH1_MDIO
     PA7     ------>  ETH1_RX_CTL
     PB0     ------>  ETH1_RXD2
-    PB1     ------>  ETH1_RXD3    
-    PB11    ------>  ETH1_TX_CTL   
+    PB1     ------>  ETH1_RXD3
+    PB11    ------>  ETH1_TX_CTL
     PC1     ------>  ETH1_MDC
-    PC2     ------>  ETH1_TXD2    
+    PC2     ------>  ETH1_TXD2
     PC4     ------>  ETH1_RXD0
     PC5     ------>  ETH1_RXD1
     PE2     ------>  ETH1_TXD3
@@ -294,12 +294,12 @@ static void HAL_ETH_MspInit(void)
     HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
     GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14;
-    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
     /* ETH interrupt Init */
     HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00);
     HAL_NVIC_EnableIRQ(ETH1_IRQn);
-    
+
     /* Configure PHY_RST (PD10) */
     GPIO_InitStruct.Pin = GPIO_PIN_10;
     GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -317,12 +317,12 @@ static void HAL_ETH_MspInit(void)
 static rt_err_t rt_stm32_eth_init(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     rt_uint32_t status;
     int i = 0 ;
     volatile uint32_t tickstart = 0;
     uint8_t  *macAddr = &stm32_eth_device.dev_addr[0];
-    
+
     /* Initialize RX/TX descriptor index */
     rxIndex = txIndex = 0;
 
@@ -362,30 +362,30 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     ETH->MACA2HR = 0;
     ETH->MACA3LR = 0;
     ETH->MACA3HR = 0;
-    
+
     /* Initialize hash table */
     ETH->MACHT0R = 0;
     ETH->MACHT1R = 0;
-    
+
     /* Configure the receive filter */
     ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
-    
+
     /* Disable flow control */
     ETH->MACQ0TXFCR = 0;
     ETH->MACRXFCR   = 0;
-    
+
     /* Enable the first RX queue */
     ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1);
-    
+
     /* Configure DMA operating mode */
     ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0);
-    
+
     /* Configure system bus mode */
     ETH->DMASBMR |= ETH_DMASBMR_AAL;
-    
+
     /* The DMA takes the descriptor table as contiguous */
     ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0);
-    
+
     /* Configure TX features */
     ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1);
 
@@ -417,12 +417,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         rxDmaDesc[i].rdes2 = 0;
         rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
     }
-    
+
     /* Set Transmit Descriptor List Address Register */
     ETH->DMAC0TXDLAR = (uint32_t)&txDmaDesc[0];
     /* Length of the transmit descriptor ring */
     ETH->DMAC0TXRLR = ETH_TXBUFNB - 1;
-    
+
     /* Set Receive Descriptor List Address Register */
     ETH->DMAC0RXDLAR = (uint32_t)&rxDmaDesc[0];
     /* Length of the receive descriptor ring */
@@ -431,24 +431,24 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     /* Prevent interrupts from being generated when the transmit statistic
      * counters reach half their maximum value */
     ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
-    
+
     /* Prevent interrupts from being generated when the receive statistic
      * counters reach half their maximum value */
     ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
-   
+
     /* Disable MAC interrupts */
     ETH->MACIER = 0;
-    
+
     /* Enable the desired DMA interrupts */
     ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
-    
+
     /* Enable MAC transmission and reception */
     ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
-   
+
     /* Enable DMA transmission and reception */
     ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
     ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
-   
+
     /* Reset PHY transceiver */
     phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR, RTL8211E_BMCR_RESET);
     status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR);
@@ -464,9 +464,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         else
         {
             status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR);
-        } 
+        }
     }
-    
+
     /* The PHY will generate interrupts when link status changes are detected */
     phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_INER, RTL8211E_INER_AN_COMPLETE | RTL8211E_INER_LINK_STATUS);
 
@@ -505,11 +505,11 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
     {
     case NIOCTL_GADDR:
         /* get mac address */
-        if (args) 
+        if (args)
         {
             rt_memcpy(args, stm32_eth_device.dev_addr, 6);
         }
-        else 
+        else
         {
             return -RT_ERROR;
         }
@@ -526,7 +526,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
 {
     uint32_t framelen = 0;
     struct pbuf *q = RT_NULL;
-    
+
     /* Copy user data to the transmit buffer */
     for (q = p; q != NULL; q = q->next)
     {
@@ -536,12 +536,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             LOG_D("buffer not valid");
             return ERR_USE;
         }
-        
+
         level = rt_hw_interrupt_disable();
         rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len);
         framelen += q->len;
         rt_hw_interrupt_enable(level);
-        
+
         /* Check the frame length */
         if (framelen > ETH_TX_BUF_SIZE - 1)
         {
@@ -549,12 +549,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             return ERR_USE;
         }
     }
-    
+
 #ifdef ETH_TX_DUMP
         rt_kprintf("Tx dump, len= %d\r\n", framelen);
         dump_hex(txBuffer[txIndex], framelen);
 #endif
-    
+
     /* Set the start address of the buffer */
     txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex];
     /* Write the number of bytes to send */
@@ -569,7 +569,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
     ETH->DMAC0SR = ETH_DMAC0SR_TBU;
     /* Instruct the DMA to poll the transmit descriptor list */
     ETH->DMAC0TXDTPR = 0;
-    
+
     if (++txIndex > ETH_TXBUFNB - 1)
     {
         txIndex = 0;
@@ -585,7 +585,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
     struct pbuf *p = RT_NULL, *q = RT_NULL;
 
     /* The current buffer is available for reading */
-    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) 
+    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN))
     {
         /* FD and LD flags should be set */
         if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD))
@@ -594,7 +594,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                 if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES))
                 {
                     /* Retrieve the length of the frame */
-                    framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL;                   
+                    framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL;
                     /* check the frame length */
                     framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength;
                     p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
@@ -606,7 +606,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                             rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len);
                             framelen += q->len;
                             rt_hw_interrupt_enable(level);
-                            
+
                             if (framelen > framelength)
                             {
                                 LOG_E("frame len is too long!");
@@ -621,7 +621,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                     LOG_D("the received packet contains an error!");
                     return RT_NULL;
                 }
-                
+
             }
         else
         {
@@ -648,14 +648,14 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         /* Instruct the DMA to poll the receive descriptor list */
         ETH->DMAC0RXDTPR = 0;
     }
-    
+
     return p;
 }
 
 void ETH1_IRQHandler(void)
 {
     rt_uint32_t status = 0;
-    
+
     /* enter interrupt */
     rt_interrupt_enter();
     /* Read DMA status register */
@@ -671,7 +671,7 @@ void ETH1_IRQHandler(void)
     {
         /* Disable RIE interrupt */
         ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE;
-        
+
         rt_event_send(&rx_event, status);
     }
     /* ETH DMA Error */
@@ -682,7 +682,7 @@ void ETH1_IRQHandler(void)
     }
     /* Clear the interrupt flags */
     ETH->DMAC0SR = ETH_DMAC0SR_NIS;
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -693,18 +693,18 @@ static void phy_linkchange()
 
     /* Read status register to acknowledge the interrupt */
     status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_INSR);
-    
+
     if (status & (RTL8211E_INSR_AN_COMPLETE | RTL8211E_INSR_LINK_STATUS))
     {
         status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR);
         status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR);
-            
+
         if (status & RTL8211E_BMSR_LINK_STATUS)
         {
-            LOG_D("link up");  
-        
+            LOG_D("link up");
+
             status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_PHYSR);
-        
+
             switch (status & RTL8211E_PHYSR_SPEED)
             {
             case RTL8211E_PHYSR_SPEED_10MBPS:
@@ -713,25 +713,25 @@ static void phy_linkchange()
                 stm32_eth_device.eth_speed |= PHY_10M;
             break;
             }
-            
+
             case RTL8211E_PHYSR_SPEED_100MBPS:
             {
                 LOG_D("speed: 100M");
                 stm32_eth_device.eth_speed |= PHY_100M;
             break;
             }
-            
+
             case RTL8211E_PHYSR_SPEED_1000MBPS:
             {
                 LOG_D("speed: 1000M");
                 stm32_eth_device.eth_speed |= PHY_1000M;
             break;
             }
-            
+
             /* Unknown speed */
             default:
                 rt_kprintf("Invalid speed.");
-            break;    
+            break;
             }
 
             stm32_eth_device.eth_mode  = (status & RTL8211E_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX;
@@ -762,7 +762,7 @@ static void eth_phy_isr(void *args)
 static void phy_monitor_thread_entry(void *parameter)
 {
     rt_uint32_t status = 0;
-    
+
     phy_linkchange();
 #ifdef PHY_USING_INTERRUPT_MODE
     /* configuration intterrupt pin */
@@ -800,9 +800,9 @@ static void phy_monitor_thread_entry(void *parameter)
                     eth_device_ready(&(stm32_eth_device.parent));
                 }
             }
-            
+
             /* enable DMA interrupts */
-            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; 
+            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
         }
     }
 }
@@ -811,7 +811,7 @@ static void phy_monitor_thread_entry(void *parameter)
 static int rt_hw_stm32_eth_init(void)
 {
     rt_err_t state = RT_EOK;
-    
+
     /* OUI 00-80-E1 STMICROELECTRONICS. */
     stm32_eth_device.dev_addr[0] = 0x00;
     stm32_eth_device.dev_addr[1] = 0x80;
@@ -831,9 +831,9 @@ static int rt_hw_stm32_eth_init(void)
 
     stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
     stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
-    
+
     rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO);
-    
+
     /* register eth device */
     state = eth_device_init(&(stm32_eth_device.parent), "e0");
     if (RT_EOK == state)
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h
index 9529d778a0..08612249ed 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -368,7 +368,7 @@ enum {
 #define RTL8211E_INSR_FALSE_CARRIER           0x0100
 #define RTL8211E_INSR_JABBER                  0x0001
 
-/* Link Down Power Saving register */ 
+/* Link Down Power Saving register */
 #define RTL8211E_LDPSR_POWER_SAVE_MODE        0x0001
 
 /* Extension Page Select register */
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c
index ca31b0aa47..075476294b 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,15 +29,15 @@ static int rt_spi_device_init(void)
     cfg.max_hz = 1 *1000 *1000;
 
     spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
-    
+
     if (RT_NULL == spi_dev)
     {
         rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
         return RT_ERROR;
     }
-    
+
     rt_spi_configure(spi_dev, &cfg);
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(rt_spi_device_init);
@@ -45,22 +45,22 @@ INIT_APP_EXPORT(rt_spi_device_init);
 /* spi5 loopback mode test case */
 static int spi_sample(int argc, char **argv)
 {
-    rt_uint8_t t_buf[8], r_buf[8];     
-    int i = 0; 
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
     static struct rt_spi_message msg1;
-    
+
     if (argc != 9)
     {
         rt_kprintf("Usage:\n");
         rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
         return -RT_ERROR;
     }
-    
+
     for (i = 0; i < 8; i++)
     {
         t_buf[i] = atoi(argv[i+1]);
     }
-    
+
     msg1.send_buf   = &t_buf;
     msg1.recv_buf   = &r_buf;
     msg1.length     = sizeof(t_buf);
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c
index fdbc721c8d..0f4df63bd3 100644
--- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c
+++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,11 +26,11 @@ static rt_adc_device_t adc_dev = RT_NULL;
 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
 {
     rt_uint32_t value = 0 , vol = 0;
-    
+
     /* read adc value */
     value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
     rt_kprintf("the value is :%d \n", value);
-    
+
     vol = value * REFER_VOLTAGE / CONVERT_BITS;
     rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
 
@@ -55,21 +55,21 @@ static int hwtimer_stop(void)
         rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME);
         return ret;
     }
-    
+
     /* close adc channel */
     ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
 static int hwtimer_start(void)
 {
     rt_err_t ret = RT_EOK;
-    rt_hwtimerval_t timeout_s;     
+    rt_hwtimerval_t timeout_s;
     rt_device_t hw_dev = RT_NULL;
-    
+
     rt_hwtimer_mode_t mode;
-        
+
     hw_dev = rt_device_find(HWTIMER_DEV_NAME);
     if (hw_dev == RT_NULL)
     {
@@ -84,7 +84,7 @@ static int hwtimer_start(void)
         rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME);
         return RT_ERROR;
     }
-    
+
     /* Open the device in read/write mode */
     ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
     if (ret != RT_EOK)
@@ -118,10 +118,10 @@ static int hwtimer_start(void)
 
     rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
     rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
-    
+
     /* enable adc channel */
     ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
@@ -130,8 +130,8 @@ static int tim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!rt_strcmp(argv[1], "start"))
-        { 
-           rt_kprintf("tim14 will start\n"); 
+        {
+           rt_kprintf("tim14 will start\n");
            hwtimer_start();
            return RT_EOK;
         }
@@ -152,7 +152,7 @@ _exit:
         rt_kprintf("tim_sample start         - start TIM14 \n");
         rt_kprintf("tim_sample stop          - stop TIM14 \n");
     }
-    
+
     return RT_ERROR;
 }
 MSH_CMD_EXPORT(tim_sample, tim sample);
diff --git a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c
index ce87056796..f6e244c12c 100644
--- a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       			Notes
+ * Date           Author                Notes
  * 2020-09-29     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/board.c b/bsp/stm32/stm32wb55-st-nucleo/board/board.c
index 1fa13eb975..13796c442c 100644
--- a/bsp/stm32/stm32wb55-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32wb55-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/board.h b/bsp/stm32/stm32wb55-st-nucleo/board/board.h
index d77bf172ba..366ef99b50 100644
--- a/bsp/stm32/stm32wb55-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32wb55-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h
index 3cf64a01de..e3c93996e7 100644
--- a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       			Notes
+ * Date           Author                Notes
  * 2020-09-29     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c
index ecd955ef8e..57385ad74c 100644
--- a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h
index 3fe6b19b9a..07da513450 100644
--- a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h
+++ b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h
@@ -28,7 +28,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wlxx_nucleo_errno.h"
 #include "stm32wlxx_nucleo_conf.h"
-   
+
 #if (USE_BSP_COM_FEATURE > 0)
   #if (USE_COM_LOG > 0)
     #ifndef __GNUC__
@@ -36,7 +36,7 @@
     #endif
   #endif
 #endif
-   
+
 /** @addtogroup BSP
   * @{
   */
@@ -52,7 +52,7 @@
 /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types
   * @{
   */
-typedef enum 
+typedef enum
 {
   LED1 = 0,
   LED2 = 1,
@@ -63,15 +63,15 @@ typedef enum
   LED_RED    = LED3
 }Led_TypeDef;
 
-typedef enum 
-{  
+typedef enum
+{
   BUTTON_SW1 = 0,
   BUTTON_SW2 = 1,
   BUTTON_SW3 = 2,
 }Button_TypeDef;
 
-typedef enum 
-{  
+typedef enum
+{
   BUTTON_MODE_GPIO = 0,
   BUTTON_MODE_EXTI = 1
 }ButtonMode_TypeDef;
@@ -129,18 +129,18 @@ typedef struct
 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */
 #endif /* (USE_BSP_COM_FEATURE > 0) */
 
-typedef enum 
+typedef enum
 {
   ABSENT  = 0,
   PRESENT = 1,
 }Presence_TypeDef;
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants
   * @{
-  */ 
+  */
 
 /**
   * @brief STM32WLXX NUCLEO BSP Driver version number
@@ -148,15 +148,15 @@ typedef enum
 #define __STM32WLXX_NUCLEO_BSP_VERSION_MAIN   (0x00U) /*!< [31:24] main version */
 #define __STM32WLXX_NUCLEO_BSP_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
 #define __STM32WLXX_NUCLEO_BSP_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
-#define __STM32WLXX_NUCLEO_BSP_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */ 
+#define __STM32WLXX_NUCLEO_BSP_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WLXX_NUCLEO_BSP_VERSION        ((__STM32WLXX_NUCLEO_BSP_VERSION_MAIN << 24)\
                                               |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB1 << 16)\
                                               |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB2 << 8 )\
                                               |(__STM32WLXX_NUCLEO_BSP_VERSION_RC))
 
-/** 
-  * @brief Define for STM32WLXX_NUCLEO board  
-  */ 
+/**
+  * @brief Define for STM32WLXX_NUCLEO board
+  */
 #if !defined (USE_STM32WLXX_NUCLEO)
  #define USE_STM32WLXX_NUCLEO
 #endif
@@ -185,11 +185,11 @@ typedef enum
 #define LEDx_GPIO_CLK_DISABLE(__INDEX__)        __HAL_RCC_GPIOB_CLK_ENABLE() /* All Led on same port */
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON Constants
   * @{
-  */  
+  */
 #define BUTTONn                                 3
 
 /**
@@ -239,11 +239,11 @@ typedef enum
 /**
   * @}
   */
-  
+
 #if (USE_BSP_COM_FEATURE > 0)
 /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM Port Constants
   * @{
-  */  
+  */
 #define COM1_UART                             LPUART1
 #define COM1_CLK_ENABLE()                     __HAL_RCC_LPUART1_CLK_ENABLE()
 #define COM1_CLK_DISABLE()                    __HAL_RCC_LPUART1_CLK_DISABLE()
@@ -315,7 +315,7 @@ void             BSP_PB_IRQHandler(Button_TypeDef Button);
 #if (USE_BSP_COM_FEATURE > 0)
 /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM_Functions LOW LEVEL COM Port Functions
   * @{
-  */  
+  */
 int32_t  BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init);
 int32_t  BSP_COM_DeInit(COM_TypeDef COM);
 #if (USE_COM_LOG > 0)
diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/board.c b/bsp/stm32/stm32wl55-st-nucleo/board/board.c
index d99a819d39..994aedfce4 100644
--- a/bsp/stm32/stm32wl55-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32wl55-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.LSEState = RCC_LSE_OFF;  
+  RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
   RCC_OscInitStruct.HSICalibrationValue = 70;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -32,8 +32,8 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  
-  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers 
+
+  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
   */
   RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK3);
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/board.h b/bsp/stm32/stm32wl55-st-nucleo/board/board.h
index e8268b970a..c6ba5988ff 100644
--- a/bsp/stm32/stm32wl55-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32wl55-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *