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https://github.com/RT-Thread/rt-thread.git
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[bsp][gd32]添加 立创开发板 GD32F470 的 SDRAM驱动，从STM32的drv_sdram.c修改而来
This commit is contained in:
yuanzihao
Meco Man
parent
348c1fcecd
commit
5b36522b48
@ -230,6 +230,11 @@ menu "On-chip Peripheral Drivers"
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endif
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endif
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config BSP_USING_SDRAM
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bool "Enable SDRAM"
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select RT_USING_SDRAM
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default n
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source "../libraries/gd32_drivers/Kconfig"
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endmenu
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@ -75,9 +75,7 @@ void rt_hw_board_init()
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef BSP_USING_SDRAM
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rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
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#else
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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}
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@ -48,6 +48,10 @@ if GetDepend(['RT_USING_SDIO']):
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src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c']
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src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c']
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if GetDepend(['BSP_USING_SDRAM']):
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src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c']
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src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c']
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path = [
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cwd + '/CMSIS/GD/GD32F4xx/Include',
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cwd + '/CMSIS',
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@ -53,6 +53,10 @@ if GetDepend('RT_USING_SDIO'):
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if GetDepend('RT_USING_PWM'):
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src += ['drv_pwm.c']
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# add sdram drivers.
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if GetDepend('BSP_USING_SDRAM'):
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src += ['drv_sdram.c']
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path = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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328
bsp/gd32/arm/libraries/gd32_drivers/drv_sdram.c
Normal file
328
bsp/gd32/arm/libraries/gd32_drivers/drv_sdram.c
Normal file
@ -0,0 +1,328 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-04 zylx first version
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* 2023-08-20 yuanzihao adapter gd32f4xx
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*/
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#include <board.h>
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#ifdef BSP_USING_SDRAM
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#include <sdram_port.h>
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#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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static exmc_sdram_parameter_struct sdram_init_struct;
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static exmc_sdram_command_parameter_struct sdram_command_init_struct;
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static exmc_sdram_timing_parameter_struct sdram_timing_init_struct;
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap system_heap;
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#endif
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static void SDRAM_Initialization_GPIO(void)
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{
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/* enable EXMC clock*/
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rcu_periph_clock_enable(RCU_EXMC);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOC);
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rcu_periph_clock_enable(RCU_GPIOD);
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rcu_periph_clock_enable(RCU_GPIOE);
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rcu_periph_clock_enable(RCU_GPIOF);
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rcu_periph_clock_enable(RCU_GPIOG);
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rcu_periph_clock_enable(RCU_GPIOH);
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/* common GPIO configuration */
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/* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */
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gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
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gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
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gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
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/* D2(PD0),D3(PD1),D13(PD8),D14(PD9),D15(PD10),D0(PD14),D1(PD15) pin configuration */
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gpio_af_set(GPIOD, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_output_options_set(GPIOD, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
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/* NBL0(PE0),NBL1(PE1),D4(PE7),D5(PE8),D6(PE9),D7(PE10),D8(PE11),D9(PE12),D10(PE13),D11(PE14),D12(PE15) pin configuration */
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gpio_af_set(GPIOE, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_mode_set(GPIOE, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_output_options_set(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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/* A0(PF0),A1(PF1),A2(PF2),A3(PF3),A4(PF4),A5(PF5),NRAS(PF11),A6(PF12),A7(PF13),A8(PF14),A9(PF15) pin configuration */
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gpio_af_set(GPIOF, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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gpio_output_options_set(GPIOF, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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/* A10(PG0),A11(PG1),A12(PG2),A14(PG4),A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */
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gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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}
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/**
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* @brief Perform the SDRAM exernal memory inialization sequence
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* @param hsdram: SDRAM handle
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* @param Command: Pointer to SDRAM command structure
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* @retval None
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*/
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static rt_err_t SDRAM_Initialization_Sequence(exmc_sdram_parameter_struct *hsdram, exmc_sdram_command_parameter_struct *Command)
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{
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__IO uint32_t tmpmrd = 0;
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uint32_t target_bank = 0;
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uint32_t sdram_device = EXMC_SDRAM_DEVICE0;
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uint32_t command_content = 0;
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uint32_t timeout = SDRAM_TIMEOUT;
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#if SDRAM_TARGET_BANK == 1
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target_bank = EXMC_SDRAM_DEVICE0_SELECT;
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#else
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target_bank = EXMC_SDRAM_DEVICE1_SELECT;
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#endif
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SDRAM_Initialization_GPIO();
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/* EXMC SDRAM device initialization sequence --------------------------------*/
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/* Step 1 : configure SDRAM timing registers --------------------------------*/
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/* LMRD: 2 clock cycles */
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sdram_timing_init_struct.load_mode_register_delay = LOADTOACTIVEDELAY;
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/* XSRD: min = 75ns */
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sdram_timing_init_struct.exit_selfrefresh_delay = EXITSELFREFRESHDELAY;
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/* RASD: min=44ns , max=120k (ns) */
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sdram_timing_init_struct.row_address_select_delay = ROWCYCLEDELAY;
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/* ARFD: min=66ns */
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sdram_timing_init_struct.auto_refresh_delay = SELFREFRESHTIME;
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/* WRD: min=1 Clock cycles +7.5ns */
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sdram_timing_init_struct.write_recovery_delay = WRITERECOVERYTIME;
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/* RPD: min=20ns */
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sdram_timing_init_struct.row_precharge_delay = RPDELAY;
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/* RCD: min=20ns */
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sdram_timing_init_struct.row_to_column_delay = RCDDELAY;
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/* step 2 : configure SDRAM control registers ---------------------------------*/
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sdram_init_struct.sdram_device = sdram_device;
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sdram_init_struct.column_address_width = SDRAM_COLUMN_BITS;
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sdram_init_struct.row_address_width = SDRAM_ROW_BITS;
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sdram_init_struct.data_width = SDRAM_DATA_WIDTH;
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sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
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sdram_init_struct.cas_latency = SDRAM_CAS_LATENCY;
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sdram_init_struct.write_protection = DISABLE;
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sdram_init_struct.sdclock_config = SDCLOCK_PERIOD;
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sdram_init_struct.burst_read_switch = ENABLE;
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sdram_init_struct.pipeline_read_delay = SDRAM_RPIPE_DELAY;
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sdram_init_struct.timing = &sdram_timing_init_struct;
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/* EXMC SDRAM bank initialization */
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exmc_sdram_init(&sdram_init_struct);
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/* step 3 : configure CKE high command---------------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_CLOCK_ENABLE;
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sdram_command_init_struct.bank_select = target_bank;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_2_SDCLK;
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sdram_command_init_struct.mode_register_content = 0;
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/* wait until the SDRAM controller is ready */
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
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timeout--;
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}
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if(0 == timeout) {
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return RT_ERROR;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 4 : insert 10ms delay----------------------------------------------*/
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// rt_thread_mdelay(10);
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/* step 5 : configure precharge all command----------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_PRECHARGE_ALL;
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sdram_command_init_struct.bank_select = target_bank;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_2_SDCLK;
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sdram_command_init_struct.mode_register_content = 0;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
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timeout--;
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}
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if(0 == timeout) {
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return RT_ERROR;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 6 : configure Auto-Refresh command-----------------------------------*/
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sdram_command_init_struct.command = EXMC_SDRAM_AUTO_REFRESH;
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sdram_command_init_struct.bank_select = target_bank;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_9_SDCLK;
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sdram_command_init_struct.mode_register_content = 0;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
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timeout--;
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}
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if(0 == timeout) {
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return RT_ERROR;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 7 : configure load mode register command-----------------------------*/
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/* program mode register */
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command_content = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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sdram_command_init_struct.command = EXMC_SDRAM_LOAD_MODE_REGISTER;
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sdram_command_init_struct.bank_select = target_bank;
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sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_2_SDCLK;
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sdram_command_init_struct.mode_register_content = command_content;
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
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timeout--;
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}
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if(0 == timeout) {
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return RT_ERROR;
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}
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/* send the command */
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exmc_sdram_command_config(&sdram_command_init_struct);
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/* step 8 : set the auto-refresh rate counter--------------------------------*/
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/* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
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/* SDCLK_Freq = SYS_Freq/2 */
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/* (7.81 us * SDCLK_Freq) - 20 */
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exmc_sdram_refresh_count_set(761);
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/* wait until the SDRAM controller is ready */
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timeout = SDRAM_TIMEOUT;
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while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
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timeout--;
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}
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if(0 == timeout) {
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return RT_ERROR;
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}
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return RT_EOK;
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}
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static int SDRAM_Init(void)
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{
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int result = RT_EOK;
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/* Initialize the SDRAM controller */
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if (SDRAM_Initialization_Sequence(&sdram_init_struct, &sdram_command_init_struct) != RT_EOK)
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{
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LOG_E("SDRAM init failed!");
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result = -RT_ERROR;
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}
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else
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{
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rt_kprintf("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", SDRAM_BANK_ADDR, SDRAM_SIZE, SDRAM_DATA_WIDTH);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
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#endif
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}
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return result;
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}
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INIT_BOARD_EXPORT(SDRAM_Init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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int sdram_test(void)
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{
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int i = 0;
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uint32_t start_time = 0, time_cast = 0;
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#if SDRAM_DATA_WIDTH_IN_NUMBER == 8
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char data_width = 1;
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uint8_t data = 0;
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#elif SDRAM_DATA_WIDTH_IN_NUMBER == 16
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char data_width = 2;
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uint16_t data = 0;
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#else
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char data_width = 4;
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uint32_t data = 0;
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#endif
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/* write data */
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LOG_D("Writing the %ld bytes data, waiting....", SDRAM_SIZE);
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start_time = rt_tick_get();
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH_IN_NUMBER == 8
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*(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
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#elif SDRAM_DATA_WIDTH_IN_NUMBER == 16
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*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
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#else
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*(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
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#endif
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}
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time_cast = rt_tick_get() - start_time;
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LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
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time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
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/* read data */
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LOG_D("start Reading and verifying data, waiting....");
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH_IN_NUMBER == 8
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data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != 0x55)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#elif SDRAM_DATA_WIDTH_IN_NUMBER == 16
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data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != 0x5555)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#else
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data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != 0x55555555)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#endif
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}
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if (i >= SDRAM_SIZE / data_width)
|
||||
{
|
||||
LOG_D("SDRAM test success!");
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
MSH_CMD_EXPORT(sdram_test, sdram test)
|
||||
#endif /* FINSH_USING_MSH */
|
||||
#endif /* DRV_DEBUG */
|
||||
#endif /* BSP_USING_SDRAM */
|
||||
69
bsp/gd32/arm/libraries/gd32_drivers/sdram_port.h
Normal file
69
bsp/gd32/arm/libraries/gd32_drivers/sdram_port.h
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-04 zylx The first version for STM32F4xx
|
||||
* 2023-08-20 yuanzihao adapter gd32f4xx
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
#define SDRAM_DEVICE EXMC_SDRAM_DEVICE0
|
||||
/* Bank1 or Bank2 */
|
||||
#define SDRAM_TARGET_BANK 1
|
||||
/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
|
||||
/* data width: 8, 16, 32 */
|
||||
#define SDRAM_DATA_WIDTH_IN_NUMBER 16
|
||||
#define SDRAM_DATA_WIDTH EXMC_SDRAM_DATABUS_WIDTH_16B
|
||||
/* column bit numbers: 8, 9, 10, 11 */
|
||||
#define SDRAM_COLUMN_BITS EXMC_SDRAM_COW_ADDRESS_9
|
||||
/* row bit numbers: 11, 12, 13 */
|
||||
#define SDRAM_ROW_BITS EXMC_SDRAM_ROW_ADDRESS_13
|
||||
/* cas latency clock number: 1, 2, 3 */
|
||||
#define SDRAM_CAS_LATENCY EXMC_CAS_LATENCY_3_SDCLK
|
||||
/* read pipe delay: 0, 1, 2 */
|
||||
#define SDRAM_RPIPE_DELAY EXMC_PIPELINE_DELAY_2_HCLK
|
||||
/* clock divid: 2, 3 */
|
||||
#define SDCLOCK_PERIOD EXMC_SDCLK_PERIODS_3_HCLK
|
||||
/* refresh rate counter */
|
||||
#define SDRAM_REFRESH_COUNT ((uint32_t)0x02A5)
|
||||
#define SDRAM_SIZE ((uint32_t)0x2000000)
|
||||
#define SDRAM_TIMEOUT ((uint32_t)0x0000FFFF)
|
||||
|
||||
/* Timing configuration for W9825G6KH-6 */
|
||||
/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
|
||||
/* TMRD: 2 Clock cycles */
|
||||
#define LOADTOACTIVEDELAY 2
|
||||
/* TXSR: 8x10ns */
|
||||
#define EXITSELFREFRESHDELAY 8
|
||||
/* TRAS: 5x10ns */
|
||||
#define SELFREFRESHTIME 7
|
||||
/* TRC: 7x10ns */
|
||||
#define ROWCYCLEDELAY 5
|
||||
/* TWR: 2 Clock cycles */
|
||||
#define WRITERECOVERYTIME 2
|
||||
/* TRP: 2x10ns */
|
||||
#define RPDELAY 3
|
||||
/* TRCD: 2x10ns */
|
||||
#define RCDDELAY 3
|
||||
|
||||
/* memory mode register */
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user