mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-01-31 17:10:25 +08:00
[components][drivers]:fix spi bug and add software spi (#9944)
* fix:spi bus issue * [components][drivers]add software SPI bus support
This commit is contained in:
CYFS
GitHub
parent
9be28dbc67
commit
599cefe834
@ -14,6 +14,183 @@ config RT_USING_SPI
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default n
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endif
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menuconfig RT_USING_SOFT_SPI
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bool "Use GPIO to soft simulate SPI"
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default n
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select RT_USING_PIN
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select RT_USING_SPI_BITOPS
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if RT_USING_SOFT_SPI
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menuconfig RT_USING_SOFT_SPI0
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bool "Enable SPI0 Bus (software simulation)"
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default y
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if RT_USING_SOFT_SPI0
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config RT_SOFT_SPI0_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 1
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config RT_SOFT_SPI0_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 2
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config RT_SOFT_SPI0_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 3
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config RT_SOFT_SPI0_BUS_NAME
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string "Bus name"
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default "spi0"
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config RT_SOFT_SPI0_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI1
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bool "Enable SPI1 Bus (software simulation)"
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default y
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if RT_USING_SOFT_SPI1
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config RT_SOFT_SPI1_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 4
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config RT_SOFT_SPI1_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 5
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config RT_SOFT_SPI1_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 6
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config RT_SOFT_SPI1_BUS_NAME
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string "Bus name"
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default "spi1"
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config RT_SOFT_SPI1_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI2
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bool "Enable SPI2 Bus (software simulation)"
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default n
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if RT_USING_SOFT_SPI2
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config RT_SOFT_SPI2_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 7
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config RT_SOFT_SPI2_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 8
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config RT_SOFT_SPI2_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 9
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config RT_SOFT_SPI2_BUS_NAME
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string "Bus name"
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default "spi2"
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config RT_SOFT_SPI2_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI3
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bool "Enable SPI3 Bus (software simulation)"
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default n
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if RT_USING_SOFT_SPI3
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config RT_SOFT_SPI3_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 10
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config RT_SOFT_SPI3_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 11
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config RT_SOFT_SPI3_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 12
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config RT_SOFT_SPI3_BUS_NAME
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string "Bus name"
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default "spi3"
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config RT_SOFT_SPI3_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI4
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bool "Enable SPI4 Bus (software simulation)"
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default n
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if RT_USING_SOFT_SPI4
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config RT_SOFT_SPI4_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 13
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config RT_SOFT_SPI4_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 14
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config RT_SOFT_SPI4_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 15
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config RT_SOFT_SPI4_BUS_NAME
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string "Bus name"
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default "spi4"
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config RT_SOFT_SPI4_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI5
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bool "Enable SPI5 Bus (software simulation)"
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default n
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if RT_USING_SOFT_SPI5
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config RT_SOFT_SPI5_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 16
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config RT_SOFT_SPI5_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 17
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config RT_SOFT_SPI5_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 18
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config RT_SOFT_SPI5_BUS_NAME
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string "Bus name"
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default "spi5"
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config RT_SOFT_SPI5_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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menuconfig RT_USING_SOFT_SPI6
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bool "Enable SPI6 Bus (software simulation)"
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default n
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if RT_USING_SOFT_SPI6
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config RT_SOFT_SPI6_SCK_PIN
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int "SCK pin number"
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range 0 32767
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default 19
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config RT_SOFT_SPI6_MISO_PIN
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int "MISO pin number"
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range 0 32767
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default 20
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config RT_SOFT_SPI6_MOSI_PIN
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int "MOSI pin number"
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range 0 32767
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default 21
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config RT_SOFT_SPI6_BUS_NAME
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string "Bus name"
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default "spi6"
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config RT_SOFT_SPI6_TIMING_DELAY
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int "Timing delay (us)"
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range 0 32767
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default 1
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endif
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endif
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config RT_USING_QSPI
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bool "Enable QSPI mode"
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default n
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@ -10,6 +10,9 @@ LOCAL_CFLAGS = ''
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if GetDepend('RT_USING_SPI_BITOPS'):
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src += ['dev_spi_bit_ops.c']
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if GetDepend('RT_USING_SOFT_SPI'):
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src += ['dev_soft_spi.c']
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if GetDepend('RT_USING_QSPI'):
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src += ['dev_qspi_core.c']
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269
components/drivers/spi/dev_soft_spi.c
Normal file
269
components/drivers/spi/dev_soft_spi.c
Normal file
@ -0,0 +1,269 @@
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/*
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* Copyright (c) 2006-2025 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-01-23 CYFS first version
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include <dev_spi_bit_ops.h>
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#ifdef RT_USING_SOFT_SPI
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#if !defined(RT_USING_SOFT_SPI0) &&\
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!defined(RT_USING_SOFT_SPI1) && !defined(RT_USING_SOFT_SPI2) &&\
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!defined(RT_USING_SOFT_SPI3) && !defined(RT_USING_SOFT_SPI4) &&\
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!defined(RT_USING_SOFT_SPI5) && !defined(RT_USING_SOFT_SPI6)
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#error "Please define at least one RT_USING_SOFT_SPIx"
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/*
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This driver can be disabled at:
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menuconfig -> RT-Thread Components -> Device Drivers -> Using I2C device drivers
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*/
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#endif
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#define DBG_ENABLE
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#define DBG_TAG "SPI_S"
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#ifdef RT_SPI_BITOPS_DEBUG
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#define DBG_LEVEL DBG_LOG
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#endif
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#include <rtdbg.h>
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/* spi config class */
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struct rt_soft_spi_config
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{
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rt_base_t sck;
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rt_base_t miso;
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rt_base_t mosi;
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rt_uint32_t timing_delay;
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const char *bus_name;
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};
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/* spi dirver class */
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struct rt_soft_spi
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{
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struct rt_spi_bit_obj spi;
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struct rt_spi_bit_ops ops;
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struct rt_soft_spi_config *cfg;
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};
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static struct rt_soft_spi_config soft_spi_config[] =
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{
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#ifdef RT_USING_SOFT_SPI0
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{
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.sck = RT_SOFT_SPI0_SCK_PIN,
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.miso = RT_SOFT_SPI0_MISO_PIN,
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.mosi = RT_SOFT_SPI0_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI0_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI0_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI0*/
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#ifdef RT_USING_SOFT_SPI1
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{
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.sck = RT_SOFT_SPI1_SCK_PIN,
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.miso = RT_SOFT_SPI1_MISO_PIN,
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.mosi = RT_SOFT_SPI1_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI1_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI1_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI1*/
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#ifdef RT_USING_SOFT_SPI2
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{
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.sck = RT_SOFT_SPI2_SCK_PIN,
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.miso = RT_SOFT_SPI2_MISO_PIN,
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.mosi = RT_SOFT_SPI2_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI2_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI2_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI2*/
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#ifdef RT_USING_SOFT_SPI3
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{
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.sck = RT_SOFT_SPI3_SCK_PIN,
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.miso = RT_SOFT_SPI3_MISO_PIN,
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.mosi = RT_SOFT_SPI3_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI3_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI3_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI3*/
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#ifdef RT_USING_SOFT_SPI4
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{
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.sck = RT_SOFT_SPI4_SCK_PIN,
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.miso = RT_SOFT_SPI4_MISO_PIN,
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.mosi = RT_SOFT_SPI4_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI4_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI4_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI4*/
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#ifdef RT_USING_SOFT_SPI5
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{
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.sck = RT_SOFT_SPI5_SCK_PIN,
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.miso = RT_SOFT_SPI5_MISO_PIN,
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.mosi = RT_SOFT_SPI5_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI5_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI5_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI5*/
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#ifdef RT_USING_SOFT_SPI6
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{
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.sck = RT_SOFT_SPI6_SCK_PIN,
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.miso = RT_SOFT_SPI6_MISO_PIN,
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.mosi = RT_SOFT_SPI6_MOSI_PIN,
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.timing_delay = RT_SOFT_SPI6_TIMING_DELAY,
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.bus_name = RT_SOFT_SPI6_BUS_NAME,
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},
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#endif /*RT_USING_SOFT_SPI6*/
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};
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static struct rt_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])];
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static void spi_soft_pin_init(struct rt_soft_spi * soft_spi)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)soft_spi->cfg;
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rt_pin_mode(cfg->sck, PIN_MODE_OUTPUT);
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rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
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rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
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rt_pin_write(cfg->miso, PIN_HIGH);
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rt_pin_write(cfg->sck, PIN_HIGH);
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rt_pin_write(cfg->mosi, PIN_HIGH);
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}
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static void spi_soft_tog_sclk(void *data)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if(rt_pin_read(cfg->sck) == PIN_HIGH)
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{
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rt_pin_write(cfg->sck, PIN_LOW);
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}
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else
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{
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rt_pin_write(cfg->sck, PIN_HIGH);
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}
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}
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static void spi_soft_set_sclk(void *data, rt_int32_t state)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if (state)
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{
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rt_pin_write(cfg->sck, PIN_HIGH);
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}
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else
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{
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rt_pin_write(cfg->sck, PIN_LOW);
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}
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}
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static void spi_soft_set_mosi(void *data, rt_int32_t state)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if (state)
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{
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rt_pin_write(cfg->mosi, PIN_HIGH);
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}
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else
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{
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rt_pin_write(cfg->mosi, PIN_LOW);
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}
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}
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static void spi_soft_set_miso(void *data, rt_int32_t state)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if (state)
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{
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rt_pin_write(cfg->miso, PIN_HIGH);
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}
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else
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{
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rt_pin_write(cfg->miso, PIN_LOW);
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}
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}
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static rt_int32_t spi_soft_get_sclk(void *data)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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return rt_pin_read(cfg->sck);
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}
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static rt_int32_t spi_soft_get_mosi(void *data)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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return rt_pin_read(cfg->mosi);
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}
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static rt_int32_t spi_soft_get_miso(void *data)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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return rt_pin_read(cfg->miso);
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}
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static void spi_soft_dir_mosi(void *data, rt_int32_t state)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if (state)
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{
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rt_pin_mode(cfg->mosi, PIN_MODE_INPUT);
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}
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else
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{
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rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
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}
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}
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static void spi_soft_dir_miso(void *data, rt_int32_t state)
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{
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struct rt_soft_spi_config *cfg = (struct rt_soft_spi_config *)data;
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if (state)
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{
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rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
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}
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else
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{
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rt_pin_mode(cfg->miso, PIN_MODE_OUTPUT);
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}
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}
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static struct rt_spi_bit_ops soft_spi_ops=
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{
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.data = RT_NULL,
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.pin_init = RT_NULL,
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.tog_sclk = spi_soft_tog_sclk,
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.set_sclk = spi_soft_set_sclk,
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.set_mosi = spi_soft_set_mosi,
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.set_miso = spi_soft_set_miso,
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.get_sclk = spi_soft_get_sclk,
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.get_mosi = spi_soft_get_mosi,
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.get_miso = spi_soft_get_miso,
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.dir_mosi = spi_soft_dir_mosi,
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.dir_miso = spi_soft_dir_miso,
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.udelay = rt_hw_us_delay,
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};
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/* Soft SPI initialization function */
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int rt_soft_spi_init(void)
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{
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rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct rt_soft_spi);
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rt_err_t result;
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for (rt_size_t i = 0; i < obj_num; i++)
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{
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rt_memcpy(&spi_obj[i].ops, &soft_spi_ops, sizeof(struct rt_spi_bit_ops));
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spi_obj[i].ops.data = (void *)&soft_spi_config[i];
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spi_obj[i].spi.ops = &soft_spi_ops;
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spi_obj[i].cfg = (void *)&soft_spi_config[i];
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spi_soft_pin_init(&spi_obj[i]);
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spi_obj[i].spi.ops->delay_us = soft_spi_config[i].timing_delay;
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result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &spi_obj[i].ops);
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RT_ASSERT(result == RT_EOK);
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}
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return RT_EOK;
|
||||
}
|
||||
INIT_PREV_EXPORT(rt_soft_spi_init);
|
||||
|
||||
#endif /* RT_USING_SOFT_SPI */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2025 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@ -87,11 +87,23 @@ rt_inline rt_ssize_t spi_xfer_4line_data8(struct rt_spi_bit_ops *ops,
|
||||
|
||||
TOG_SCLK(ops);
|
||||
|
||||
if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x01; }
|
||||
else { rx_data >>= 1; bit = 0x80; }
|
||||
if (config->mode & RT_SPI_MSB)
|
||||
{
|
||||
rx_data <<= 1; bit = 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data >>= 1; bit = 0x80;
|
||||
}
|
||||
|
||||
if (GET_MISO(ops)) { rx_data |= bit; }
|
||||
else { rx_data &= ~bit; }
|
||||
if (GET_MISO(ops))
|
||||
{
|
||||
rx_data |= bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data &= ~bit;
|
||||
}
|
||||
|
||||
spi_delay2(ops);
|
||||
|
||||
@ -150,11 +162,23 @@ rt_inline rt_ssize_t spi_xfer_4line_data16(struct rt_spi_bit_ops *ops,
|
||||
|
||||
TOG_SCLK(ops);
|
||||
|
||||
if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x0001; }
|
||||
else { rx_data >>= 1; bit = 0x8000; }
|
||||
if (config->mode & RT_SPI_MSB)
|
||||
{
|
||||
rx_data <<= 1; bit = 0x0001;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data >>= 1; bit = 0x8000;
|
||||
}
|
||||
|
||||
if (GET_MISO(ops)) { rx_data |= bit; }
|
||||
else { rx_data &= ~bit; }
|
||||
if (GET_MISO(ops))
|
||||
{
|
||||
rx_data |= bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data &= ~bit;
|
||||
}
|
||||
|
||||
spi_delay2(ops);
|
||||
|
||||
@ -244,11 +268,23 @@ rt_inline rt_ssize_t spi_xfer_3line_data8(struct rt_spi_bit_ops *ops,
|
||||
|
||||
TOG_SCLK(ops);
|
||||
|
||||
if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x01; }
|
||||
else { rx_data >>= 1; bit = 0x80; }
|
||||
if (config->mode & RT_SPI_MSB)
|
||||
{
|
||||
rx_data <<= 1; bit = 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data >>= 1; bit = 0x80;
|
||||
}
|
||||
|
||||
if (GET_MOSI(ops)) { rx_data |= bit; }
|
||||
else { rx_data &= ~bit; }
|
||||
if (GET_MOSI(ops))
|
||||
{
|
||||
rx_data |= bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data &= ~bit;
|
||||
}
|
||||
|
||||
spi_delay2(ops);
|
||||
|
||||
@ -345,11 +381,23 @@ rt_inline rt_ssize_t spi_xfer_3line_data16(struct rt_spi_bit_ops *ops,
|
||||
|
||||
TOG_SCLK(ops);
|
||||
|
||||
if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x0001; }
|
||||
else { rx_data >>= 1; bit = 0x8000; }
|
||||
if (config->mode & RT_SPI_MSB)
|
||||
{
|
||||
rx_data <<= 1; bit = 0x0001;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data >>= 1; bit = 0x8000;
|
||||
}
|
||||
|
||||
if (GET_MOSI(ops)) { rx_data |= bit; }
|
||||
else { rx_data &= ~bit; }
|
||||
if (GET_MOSI(ops))
|
||||
{
|
||||
rx_data |= bit;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_data &= ~bit;
|
||||
}
|
||||
|
||||
spi_delay2(ops);
|
||||
|
||||
@ -456,15 +504,14 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
|
||||
rt_pin_write(cs_pin, PIN_LOW);
|
||||
}
|
||||
spi_delay(ops);
|
||||
}
|
||||
|
||||
/* spi phase */
|
||||
if (config->mode & RT_SPI_CPHA)
|
||||
if ((config->mode & RT_SPI_CPHA))
|
||||
{
|
||||
spi_delay(ops);
|
||||
TOG_SCLK(ops);
|
||||
}
|
||||
}
|
||||
|
||||
if (config->mode & RT_SPI_3WIRE)
|
||||
{
|
||||
if (config->data_width <= 8)
|
||||
@ -487,10 +534,15 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
|
||||
length = spi_xfer_4line_data16(ops, config, message->send_buf, message->recv_buf, message->length);
|
||||
}
|
||||
}
|
||||
|
||||
/* release CS */
|
||||
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (cs_pin != PIN_NONE))
|
||||
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (cs_pin != PIN_NONE))
|
||||
{
|
||||
|
||||
if ((config->mode & RT_SPI_CPOL) && !GET_SCLK(ops))
|
||||
{
|
||||
spi_delay(ops);
|
||||
TOG_SCLK(ops);
|
||||
}
|
||||
spi_delay(ops);
|
||||
if (device->config.mode & RT_SPI_CS_HIGH)
|
||||
{
|
||||
@ -501,6 +553,7 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
|
||||
rt_pin_write(cs_pin, PIN_HIGH);
|
||||
}
|
||||
LOG_I("spi release cs\n");
|
||||
|
||||
}
|
||||
|
||||
return length;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2025 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@ -140,7 +140,7 @@ rt_err_t rt_spi_bus_configure(struct rt_spi_device *device)
|
||||
result = rt_mutex_take(&(device->bus->lock), RT_WAITING_FOREVER);
|
||||
if (result == RT_EOK)
|
||||
{
|
||||
if (device->bus->owner == device)
|
||||
if (device->bus->owner == RT_NULL || device->bus->owner == device)
|
||||
{
|
||||
/* current device is using, re-configure SPI bus */
|
||||
result = device->bus->ops->configure(device, &device->config);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user