Update uart.c
This commit is contained in:
Bernard Xiong
parent
bb5f57f91c
commit
59653699b2
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@ -17,308 +17,309 @@
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#include <rtthread.h>
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#include "LPC17xx.h"
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#define IER_RBR 0x01
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#define IER_THRE 0x02
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#define IER_RLS 0x04
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#define IER_RBR 0x01
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#define IER_THRE 0x02
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#define IER_RLS 0x04
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#define IIR_PEND 0x01
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#define IIR_RLS 0x03
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#define IIR_RDA 0x02
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#define IIR_CTI 0x06
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#define IIR_THRE 0x01
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#define IIR_PEND 0x01
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#define IIR_RLS 0x03
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#define IIR_RDA 0x02
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#define IIR_CTI 0x06
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#define IIR_THRE 0x01
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#define LSR_RDR 0x01
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#define LSR_OE 0x02
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#define LSR_PE 0x04
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#define LSR_FE 0x08
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#define LSR_BI 0x10
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#define LSR_THRE 0x20
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#define LSR_TEMT 0x40
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#define LSR_RXFE 0x80
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#define LSR_RDR 0x01
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#define LSR_OE 0x02
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#define LSR_PE 0x04
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#define LSR_FE 0x08
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#define LSR_BI 0x10
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#define LSR_THRE 0x20
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#define LSR_TEMT 0x40
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#define LSR_RXFE 0x80
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/**
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* @addtogroup LPC11xx
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* @addtogroup LPC176x
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*/
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/*@{*/
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#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE)
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#define UART_BAUDRATE 115200
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#define LPC_UART LPC_UART0
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#define UART_IRQn UART0_IRQn
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#define LPC_UART LPC_UART0
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#define UART_IRQn UART0_IRQn
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struct rt_uart_lpc
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{
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struct rt_device parent;
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struct rt_device parent;
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/* buffer for reception */
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rt_uint8_t read_index, save_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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}uart_device;
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/* buffer for reception */
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rt_uint8_t read_index, save_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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} uart_device;
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void UART0_IRQHandler(void)
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{
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rt_ubase_t level, iir;
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struct rt_uart_lpc* uart = &uart_device;
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rt_ubase_t level, iir;
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struct rt_uart_lpc *uart = &uart_device;
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/* read IIR and clear it */
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iir = LPC_UART->IIR;
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iir = LPC_UART->IIR;
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iir >>= 1; /* skip pending bit in IIR */
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iir &= 0x07; /* check bit 1~3, interrupt identification */
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iir >>= 1; /* skip pending bit in IIR */
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iir &= 0x07; /* check bit 1~3, interrupt identification */
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if (iir == IIR_RDA) /* Receive Data Available */
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{
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/* Receive Data Available */
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if (iir == IIR_RDA) /* Receive Data Available */
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{
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/* Receive Data Available */
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uart->rx_buffer[uart->save_index] = LPC_UART->RBR;
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level = rt_hw_interrupt_disable();
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uart->save_index ++;
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uart->save_index ++;
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if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
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uart->save_index = 0;
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rt_hw_interrupt_enable(level);
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/* invoke callback */
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if(uart->parent.rx_indicate != RT_NULL)
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{
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rt_size_t length;
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if (uart->read_index > uart->save_index)
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/* invoke callback */
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if (uart->parent.rx_indicate != RT_NULL)
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{
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rt_size_t length;
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if (uart->read_index > uart->save_index)
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length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
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else
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length = uart->save_index - uart->read_index;
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uart->parent.rx_indicate(&uart->parent, length);
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}
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}else if(iir == IIR_RLS)
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{
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iir = LPC_Uart->LSR; //oe pe fe oe read for clear interrupt
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}
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}
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}
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else if (iir == IIR_RLS)
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{
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iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt
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}
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return;
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return;
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}
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static rt_err_t rt_uart_init (rt_device_t dev)
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static rt_err_t rt_uart_init(rt_device_t dev)
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{
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rt_uint32_t Fdiv;
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rt_uint32_t pclkdiv, pclk;
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rt_uint32_t Fdiv;
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rt_uint32_t pclkdiv, pclk;
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/* Init UART Hardware */
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if (LPC_UART == LPC_UART0)
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{
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LPC_PINCON->PINSEL0 &= ~0x000000F0;
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LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
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/* By default, the PCLKSELx value is zero, thus, the PCLK for
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all the peripherals is 1/4 of the SystemFrequency. */
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/* Bit 6~7 is for UART0 */
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pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
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switch ( pclkdiv )
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{
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case 0x00:
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default:
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pclk = SystemCoreClock/4;
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break;
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case 0x01:
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pclk = SystemCoreClock;
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break;
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case 0x02:
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pclk = SystemCoreClock/2;
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break;
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case 0x03:
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pclk = SystemCoreClock/8;
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break;
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}
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/* Init UART Hardware */
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if (LPC_UART == LPC_UART0)
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{
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LPC_PINCON->PINSEL0 &= ~0x000000F0;
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LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
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/* By default, the PCLKSELx value is zero, thus, the PCLK for
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all the peripherals is 1/4 of the SystemFrequency. */
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/* Bit 6~7 is for UART0 */
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pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
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switch (pclkdiv)
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{
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case 0x00:
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default:
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pclk = SystemCoreClock / 4;
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break;
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case 0x01:
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pclk = SystemCoreClock;
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break;
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case 0x02:
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pclk = SystemCoreClock / 2;
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break;
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case 0x03:
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pclk = SystemCoreClock / 8;
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break;
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}
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LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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Fdiv = ( pclk / 16 ) / UART_BAUDRATE; /*baud rate */
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LPC_UART0->DLM = Fdiv / 256;
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LPC_UART0->DLL = Fdiv % 256;
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LPC_UART0->LCR = 0x03; /* DLAB = 0 */
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LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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}
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else if ((LPC_UART1_TypeDef*)LPC_UART == LPC_UART1)
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{
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LPC_PINCON->PINSEL4 &= ~0x0000000F;
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LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
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LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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Fdiv = (pclk / 16) / UART_BAUDRATE; /*baud rate */
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LPC_UART0->DLM = Fdiv / 256;
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LPC_UART0->DLL = Fdiv % 256;
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LPC_UART0->LCR = 0x03; /* DLAB = 0 */
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LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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}
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else if ((LPC_UART1_TypeDef *)LPC_UART == LPC_UART1)
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{
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LPC_PINCON->PINSEL4 &= ~0x0000000F;
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LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
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/* By default, the PCLKSELx value is zero, thus, the PCLK for
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all the peripherals is 1/4 of the SystemFrequency. */
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/* Bit 8,9 are for UART1 */
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pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
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switch ( pclkdiv )
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{
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case 0x00:
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default:
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pclk = SystemCoreClock/4;
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break;
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case 0x01:
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pclk = SystemCoreClock;
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break;
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case 0x02:
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pclk = SystemCoreClock/2;
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break;
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case 0x03:
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pclk = SystemCoreClock/8;
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break;
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}
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/* By default, the PCLKSELx value is zero, thus, the PCLK for
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all the peripherals is 1/4 of the SystemFrequency. */
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/* Bit 8,9 are for UART1 */
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pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
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switch (pclkdiv)
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{
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case 0x00:
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default:
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pclk = SystemCoreClock / 4;
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break;
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case 0x01:
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pclk = SystemCoreClock;
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break;
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case 0x02:
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pclk = SystemCoreClock / 2;
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break;
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case 0x03:
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pclk = SystemCoreClock / 8;
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break;
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}
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LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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Fdiv = ( pclk / 16 ) / UART_BAUDRATE ; /*baud rate */
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LPC_UART1->DLM = Fdiv / 256;
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LPC_UART1->DLL = Fdiv % 256;
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LPC_UART1->LCR = 0x03; /* DLAB = 0 */
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LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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}
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LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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Fdiv = (pclk / 16) / UART_BAUDRATE ; /*baud rate */
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LPC_UART1->DLM = Fdiv / 256;
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LPC_UART1->DLL = Fdiv % 256;
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LPC_UART1->LCR = 0x03; /* DLAB = 0 */
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LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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}
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/* Ensure a clean start, no data in either TX or RX FIFO. */
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while (( LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
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while ( LPC_UART->LSR & LSR_RDR )
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{
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Fdiv = LPC_UART->RBR; /* Dump data from RX FIFO */
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}
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LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
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/* Ensure a clean start, no data in either TX or RX FIFO. */
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while ((LPC_UART->LSR & (LSR_THRE | LSR_TEMT)) != (LSR_THRE | LSR_TEMT));
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while (LPC_UART->LSR & LSR_RDR)
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{
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Fdiv = LPC_UART->RBR; /* Dump data from RX FIFO */
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}
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LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
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return RT_EOK;
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return RT_EOK;
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}
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static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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RT_ASSERT(dev != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable the UART Interrupt */
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NVIC_EnableIRQ(UART_IRQn);
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}
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RT_ASSERT(dev != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable the UART Interrupt */
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NVIC_EnableIRQ(UART_IRQn);
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}
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return RT_EOK;
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return RT_EOK;
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}
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static rt_err_t rt_uart_close(rt_device_t dev)
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{
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RT_ASSERT(dev != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Disable the UART Interrupt */
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NVIC_DisableIRQ(UART_IRQn);
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}
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RT_ASSERT(dev != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Disable the UART Interrupt */
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NVIC_DisableIRQ(UART_IRQn);
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}
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return RT_EOK;
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return RT_EOK;
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}
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static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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rt_uint8_t* ptr;
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struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
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RT_ASSERT(uart != RT_NULL);
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rt_uint8_t *ptr;
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struct rt_uart_lpc *uart = (struct rt_uart_lpc *)dev;
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RT_ASSERT(uart != RT_NULL);
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/* point to buffer */
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ptr = (rt_uint8_t*) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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while (size)
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{
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/* interrupt receive */
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rt_base_t level;
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/* point to buffer */
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ptr = (rt_uint8_t *) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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while (size)
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{
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/* interrupt receive */
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (uart->read_index != uart->save_index)
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{
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*ptr = uart->rx_buffer[uart->read_index];
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (uart->read_index != uart->save_index)
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{
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*ptr = uart->rx_buffer[uart->read_index];
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uart->read_index ++;
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if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
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uart->read_index = 0;
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}
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else
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{
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/* no data in rx buffer */
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uart->read_index ++;
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if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
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uart->read_index = 0;
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}
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else
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{
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/* no data in rx buffer */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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ptr ++;
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size --;
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}
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ptr ++;
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size --;
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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return 0;
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return 0;
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}
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static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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char *ptr;
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ptr = (char*)buffer;
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char *ptr;
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ptr = (char *)buffer;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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/* THRE status, contain valid data */
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while ( !(LPC_UART->LSR & LSR_THRE) );
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/* write data */
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LPC_UART->THR = '\r';
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}
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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/* THRE status, contain valid data */
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while (!(LPC_UART->LSR & LSR_THRE));
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/* write data */
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LPC_UART->THR = '\r';
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}
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/* THRE status, contain valid data */
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while ( !(LPC_UART->LSR & LSR_THRE) );
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/* write data */
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LPC_UART->THR = *ptr;
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/* THRE status, contain valid data */
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while (!(LPC_UART->LSR & LSR_THRE));
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/* write data */
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LPC_UART->THR = *ptr;
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ptr ++;
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size --;
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}
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}
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else
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{
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while ( size != 0 )
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{
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/* THRE status, contain valid data */
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while ( !(LPC_UART->LSR & LSR_THRE) );
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ptr ++;
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size --;
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}
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}
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else
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{
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while (size != 0)
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{
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/* THRE status, contain valid data */
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while (!(LPC_UART->LSR & LSR_THRE));
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/* write data */
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LPC_UART->THR = *ptr;
|
||||
/* write data */
|
||||
LPC_UART->THR = *ptr;
|
||||
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct rt_uart_lpc* uart;
|
||||
struct rt_uart_lpc *uart;
|
||||
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.user_data = RT_NULL;
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&uart->parent,
|
||||
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
rt_device_register(&uart->parent,
|
||||
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
#endif /* end of UART */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue