commit
578067a64a
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@ -1346,12 +1346,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
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address = (uint32_t)curBuffDescrip->buffer;
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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{
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memcpy((void *)address, data, length);
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// Change SDK to reduce memory copy
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extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len);
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pbuf2mem(data, (void *)address, length);
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}
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//memcpy((void *)address, data, length);
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/* Set data length. */
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/* Set data length. */
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curBuffDescrip->length = length;
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curBuffDescrip->length = length;
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#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
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#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
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@ -27,7 +27,7 @@ i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器,以下是具
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### 3.1 配置工程
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### 3.1 配置工程
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i.MX RT1052 BSP支持多块开发板,包括官方开发板MIMXRT1050-EVK,野火的i.MX RT1052开发板。如果不是基于官方开发板,那么重新配置并生成工程:
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i.MX RT1052 BSP支持多块开发板,包括官方开发板MIMXRT1050-EVK,野火的i.MX RT1052开发板等。如果不是基于官方开发板,那么需要重新配置并生成工程:
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- 在bsp下打开env工具
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- 在bsp下打开env工具
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- 输入`menuconfig`命令,`RT1052 Board select (***)-->`选择正确的开发板。
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- 输入`menuconfig`命令,`RT1052 Board select (***)-->`选择正确的开发板。
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@ -37,15 +37,31 @@ i.MX RT1052 BSP支持多块开发板,包括官方开发板MIMXRT1050-EVK,野
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#### 3.2.1 MIMXRT1050-EVK
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#### 3.2.1 MIMXRT1050-EVK
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EVK开发板有板载OpenSDA仿真器,仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28),就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口就可以看到shell输出
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EVK开发板有板载OpenSDA仿真器,仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28),就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口。
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#### 3.2.2 野火开发板
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#### 3.2.2 野火开发板
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连接外置仿真器(野火DAP仿真器或者Jlink)后,就可以进行下载和下载。使用USB线连接开发板底板的USB转串口,在终端工具里打开相应的串口。
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### 3.3 运行结果
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### 3.3 运行结果
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如果编译 & 烧写无误,当复位设备后,会在串口上(PuTTY)看到RT-Thread的启动logo信息:
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如果编译 & 烧写无误,当复位设备后,会在串口上看到RT-Thread的启动logo信息:
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TODO
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 3.0.4 build May 2 2018
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2006 - 2018 Copyright by rt-thread team
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lwIP-2.0.2 initialized!
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using armcc, version: 5060750
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build time: May 2 2018 21:52:40
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msh />[PHY] wait autonegotiation complete...
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SD card capacity 123904 KB
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probe mmcsd block device!
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found part[0], begin: 32256, size: 120.992MB
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File System initialized!
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[PHY] wait autonegotiation complete...
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```
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## 4. 驱动支持情况及计划
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## 4. 驱动支持情况及计划
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@ -23,6 +23,7 @@
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#include "fsl_gpio.h"
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#include "fsl_gpio.h"
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#include "fsl_iomuxc.h"
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#include "fsl_iomuxc.h"
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#include "fsl_phy.h"
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#include "fsl_phy.h"
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#include "fsl_cache.h"
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#ifdef RT_USING_LWIP
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#ifdef RT_USING_LWIP
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@ -479,6 +480,188 @@ static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
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return RT_EOK;
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return RT_EOK;
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}
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}
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static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
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{
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assert(ringId < FSL_FEATURE_ENET_QUEUE);
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switch (ringId)
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{
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case 0:
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base->TDAR = ENET_TDAR_TDAR_MASK;
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break;
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#if FSL_FEATURE_ENET_QUEUE > 1
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case kENET_Ring1:
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base->TDAR1 = ENET_TDAR1_TDAR_MASK;
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break;
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case kENET_Ring2:
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base->TDAR2 = ENET_TDAR2_TDAR_MASK;
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break;
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#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
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default:
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base->TDAR = ENET_TDAR_TDAR_MASK;
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break;
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}
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}
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static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length)
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{
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assert(handle);
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assert(data);
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volatile enet_tx_bd_struct_t *curBuffDescrip;
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uint32_t len = 0;
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uint32_t sizeleft = 0;
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uint32_t address;
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/* Check the frame length. */
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if (length > ENET_FRAME_MAX_FRAMELEN)
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{
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return kStatus_ENET_TxFrameOverLen;
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}
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/* Check if the transmit buffer is ready. */
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curBuffDescrip = handle->txBdCurrent[0];
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if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
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{
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return kStatus_ENET_TxFrameBusy;
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}
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#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
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bool isPtpEventMessage = false;
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/* Check PTP message with the PTP header. */
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isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true);
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#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
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/* One transmit buffer is enough for one frame. */
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if (handle->txBuffSizeAlign[0] >= length)
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{
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/* Copy data to the buffer for uDMA transfer. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
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#else
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0);
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/* Set data length. */
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curBuffDescrip->length = length;
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#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
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/* For enable the timestamp. */
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if (isPtpEventMessage)
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{
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curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
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}
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else
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{
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curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
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}
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#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
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curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK);
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/* Increase the buffer descriptor address. */
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if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
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{
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handle->txBdCurrent[0] = handle->txBdBase[0];
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}
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else
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{
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handle->txBdCurrent[0]++;
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}
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#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
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/* Add the cache clean maintain. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
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#else
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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DCACHE_CleanByRange(address, length);
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#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
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/* Active the transmit buffer descriptor. */
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_ENET_ActiveSend(base, 0);
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return kStatus_Success;
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}
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else
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{
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/* One frame requires more than one transmit buffers. */
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do
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{
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#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
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/* For enable the timestamp. */
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if (isPtpEventMessage)
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{
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curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
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}
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else
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{
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curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
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}
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#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
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/* Increase the buffer descriptor address. */
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if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
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{
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handle->txBdCurrent[0] = handle->txBdBase[0];
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}
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else
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{
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handle->txBdCurrent[0]++;
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}
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/* update the size left to be transmit. */
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sizeleft = length - len;
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if (sizeleft > handle->txBuffSizeAlign[0])
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{
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/* Data copy. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
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#else
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
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/* Data length update. */
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curBuffDescrip->length = handle->txBuffSizeAlign[0];
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len += handle->txBuffSizeAlign[0];
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/* Sets the control flag. */
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curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
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curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
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/* Active the transmit buffer descriptor*/
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_ENET_ActiveSend(base, 0);
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}
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else
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{
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
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#else
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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memcpy((void *)address, data + len, sizeleft);
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curBuffDescrip->length = sizeleft;
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/* Set Last buffer wrap flag. */
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curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
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#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
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/* Add the cache clean maintain. */
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#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
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address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
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#else
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address = (uint32_t)curBuffDescrip->buffer;
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#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
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DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
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#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
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/* Active the transmit buffer descriptor. */
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_ENET_ActiveSend(base, 0);
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return kStatus_Success;
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}
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/* Get the current buffer descriptor address. */
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curBuffDescrip = handle->txBdCurrent[0];
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} while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
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return kStatus_ENET_TxFrameBusy;
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}
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}
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/* ethernet device interface */
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/* ethernet device interface */
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/* transmit packet. */
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/* transmit packet. */
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rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
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rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
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@ -497,7 +680,7 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
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do
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do
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{
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{
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result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
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result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
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if (result == kStatus_ENET_TxFrameBusy)
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if (result == kStatus_ENET_TxFrameBusy)
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{
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{
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@ -511,11 +694,6 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
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return RT_EOK;
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return RT_EOK;
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}
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}
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void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len)
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{
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pbuf_copy_partial((const struct pbuf *)data, dataptr, len, 0);
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}
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/* reception packet. */
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/* reception packet. */
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struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
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struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
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{
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{
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@ -56,7 +56,7 @@ static int enable_log = 1;
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#define IMXRT_MAX_FREQ (50UL * 1000UL * 1000UL)
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#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL)
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
|
||||||
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Loading…
Reference in New Issue