greedyhao
parent
ec060312b7
commit
54c880e979
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@ -23,7 +23,18 @@ CONFIG_IDLE_THREAD_STACK_SIZE=1024
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CONFIG_RT_USING_TIMER_SOFT=y
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CONFIG_RT_TIMER_THREAD_PRIO=4
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CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
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# CONFIG_RT_DEBUG is not set
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CONFIG_RT_DEBUG=y
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# CONFIG_RT_DEBUG_COLOR is not set
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
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# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
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# CONFIG_RT_DEBUG_IPC_CONFIG is not set
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# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
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# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
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# CONFIG_RT_DEBUG_MEM_CONFIG is not set
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# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
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# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
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# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
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#
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# Inter-Thread communication
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@ -83,7 +94,7 @@ CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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CONFIG_FINSH_ECHO_DISABLE_DEFAULT=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_CMD_SIZE=80
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@ -417,7 +428,10 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_FASTLZ is not set
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# CONFIG_PKG_USING_MINILZO is not set
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# CONFIG_PKG_USING_QUICKLZ is not set
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# CONFIG_PKG_USING_LZMA is not set
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# CONFIG_PKG_USING_MULTIBUTTON is not set
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# CONFIG_PKG_USING_MULTIBUTTON_V102 is not set
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# CONFIG_PKG_USING_MULTIBUTTON_LATEST_VERSION is not set
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# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
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# CONFIG_PKG_USING_CANFESTIVAL is not set
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# CONFIG_PKG_USING_ZLIB is not set
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@ -458,7 +472,20 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
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#
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# General Purpose UARTs
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# Hardware Drivers Config
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#
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#
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# Onboard Peripheral Drivers
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#
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CONFIG_BSP_USING_USB_TO_USART=y
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#
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# On-chip Peripheral Drivers
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#
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CONFIG_BSP_USING_UART0=y
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#
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# Board extended module Drivers
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#
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CONFIG_BOARD_BLUETRUM_EVB=y
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@ -2,9 +2,12 @@
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*.bin
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*.dcf
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*.map
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*.lst
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*.pyc
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*.elf
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*.old
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*.o
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build
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dist
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packages
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@ -102,6 +102,8 @@ msh >
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## 注意事项
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波特率默认为 1.5M，需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片
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编译报错的时候，如果出现重复定义的报错，可能需要在 `cconfig.h` 中手动添加以下配置
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```
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@ -1,4 +1,16 @@
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menu "General Purpose UARTs"
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menu "Hardware Drivers Config"
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menu "Onboard Peripheral Drivers"
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config BSP_USING_USB_TO_USART
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bool "Enable USB TO USART (uart0)"
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select BSP_USING_UART
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select BSP_USING_UART0
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default y
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endmenu
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menu "On-chip Peripheral Drivers"
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menuconfig BSP_USING_UART0
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bool "Enable UART0"
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@ -6,3 +18,8 @@ menuconfig BSP_USING_UART0
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default y
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endmenu
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menu "Board extended module Drivers"
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endmenu
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endmenu
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@ -17,7 +17,7 @@ void timer0_cfg(uint32_t ticks);
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void rt_soft_isr(int vector, void *param);
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void cpu_irq_comm(void);
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void set_cpu_irq_comm(void (*irq_hook)(void));
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extern uint32_t __aram_start, __eram_end;
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extern uint32_t __heap_start, __heap_end;
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void hal_printf(const char *fmt, ...)
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{
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@ -108,7 +108,7 @@ void rt_hw_board_init(void)
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rt_hw_systick_init();
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#ifdef RT_USING_HEAP
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rt_system_heap_init(&__aram_start, &__eram_end);
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rt_system_heap_init(&__heap_start, &__heap_end);
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#endif
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#ifdef RT_USING_PIN
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@ -1,21 +1,26 @@
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/* Define the flash max size */
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__max_flash_size = 768k;
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__comm_ram_size = 104k;
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__heap_ram_size = 14k;
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__base = 0x10000000;
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__comm_vma = 0x17000;
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__max_comm_size = 76k;
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__comm_vma = 0x12800;
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__heap_vma = __comm_vma + __comm_ram_size;
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__ram1_vma = 0x50000;
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MEMORY
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{
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init : org = __base, len = 512
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flash(rx) : org = __base + 512, len = __max_flash_size
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comm(rx) : org = __comm_vma, len = __max_comm_size
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data : org = 0x11000, len = 16k
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stack : org = 0x15000, len = 8k
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aram : org = 0x50000, len = 16k
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dram : org = 0x54000, len = 12k
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eram : org = 0x57000, len = 0xa00
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comm(rx) : org = __comm_vma, len = __comm_ram_size
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data : org = 0x11000, len = 5k
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stack : org = 0x12400, len = 1k
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heap : org = __heap_vma, len = __heap_ram_size
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ram1(rx) : org = __ram1_vma, len = 0x7a00
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}
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SECTIONS
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@ -24,17 +29,17 @@ SECTIONS
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*(.reset)
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} > init
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.comm : {
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KEEP(*(.vector))
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*(.com_text*)
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*(.text*)
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*(.rodata*)
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*(.com_rodata*)
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*(.rela*)
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*(.data*)
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*(.sdata*)
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LONG(0)
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} > comm AT > flash
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.ram1 __ram1_vma : {
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/*board\\ports\\*.o(.text*)*/
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*hal_drivers\\*.o(.text*)
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*hal_libraries\\ab32vg1_hal\\*.o(.text*)
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*components\\drivers\\*.o(.text* .rodata*)
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*components\\libc\\*.o(.text*)
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*ab32vg1_hal_msp.o(.text*)
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*components.o(.text* .rodata*)
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*ipc.o(.text* .rodata*)
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. = ALIGN(32);
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} > ram1 AT > flash
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.rti : {
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. = ALIGN(4);
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@ -52,6 +57,19 @@ SECTIONS
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(32);
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} > ram1 AT > flash
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.comm : {
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KEEP(*(.vector))
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*(.text*)
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*(.rodata*)
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*(.srodata*)
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*(.rela*)
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*(.data*)
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*(.sdata*)
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. = ALIGN(512);
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} > comm AT > flash
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.flash : {
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@ -71,26 +89,21 @@ SECTIONS
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.stack (NOLOAD) : {
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__irq_stack_start = .;
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. = 0x2000;
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. = 0x400;
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__irq_stack = .;
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} > stack
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__irq_stack_size = __irq_stack - __irq_stack_start;
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.code_aecram (NOLOAD): {
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__aram_start = .;
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} > aram
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.code_decram (NOLOAD): {
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} > dram
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.code_encram (NOLOAD): {
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__eram_start = .;
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. = 0xa00;
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__eram_end = .;
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} > eram
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.heap : {
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__heap_start = .;
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. = __heap_ram_size;
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__heap_end = .;
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} > heap
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}
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/* Calc the lma */
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__bank_size = SIZEOF(.flash);
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__comm_lma = LOADADDR(.comm);
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__comm_size = SIZEOF(.comm) + SIZEOF(.rti);
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__comm_size = SIZEOF(.comm);
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__ram1_lma = LOADADDR(.ram1);
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__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);
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@ -19,6 +19,7 @@
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#define RT_USING_TIMER_SOFT
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#define RT_TIMER_THREAD_PRIO 4
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#define RT_TIMER_THREAD_STACK_SIZE 512
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#define RT_DEBUG
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/* Inter-Thread communication */
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@ -62,7 +63,6 @@
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#define FINSH_HISTORY_LINES 5
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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#define FINSH_ECHO_DISABLE_DEFAULT
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#define FINSH_THREAD_PRIORITY 20
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#define FINSH_THREAD_STACK_SIZE 4096
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#define FINSH_CMD_SIZE 80
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@ -154,9 +154,18 @@
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/* games: games run on RT-Thread console */
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/* General Purpose UARTs */
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/* Hardware Drivers Config */
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/* Onboard Peripheral Drivers */
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#define BSP_USING_USB_TO_USART
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/* On-chip Peripheral Drivers */
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#define BSP_USING_UART0
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/* Board extended module Drivers */
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#define BOARD_BLUETRUM_EVB
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#endif
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@ -40,9 +40,19 @@ static const hal_sfr_t port_sfr[] =
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GPIOF_BASE,
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};
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static uint8_t _pin_port(uint32_t pin)
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{
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uint8_t port = 0;
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for (port = 0; port < 3; port++) {
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if (pin < (port_table[port].total_pin + port_table[port].delta_pin)) {
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break;
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}
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}
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return port;
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}
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#define PIN_NUM(port, no) ((uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin))
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#define _PIN_PORT(pin) (uint8_t)(((pin) >> 3) & 0xFu)
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#define PIN_PORT(pin) ((port_table[_PIN_PORT(pin)].delta_pin == 8) ? _PIN_PORT(pin) : _PIN_PORT(pin) + 1)
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#define PIN_PORT(pin) _pin_port(pin)
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#define PORT_SFR(port) (port_sfr[(port)])
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#define PIN_NO(pin) (uint8_t)((pin) & 0xFu)
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@ -95,7 +105,7 @@ static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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uint8_t port = PIN_PORT(pin);
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uint8_t gpio_pin = pin - port_table[port].total_pin;
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hal_gpio_write(PORT_SFR(port), gpio_pin, value);
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hal_gpio_write(PORT_SFR(port), gpio_pin, (uint8_t)value);
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}
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static int ab32_pin_read(rt_device_t dev, rt_base_t pin)
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@ -187,7 +187,7 @@ int rt_hw_usart_init(void)
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uart_obj[i].config = &uart_config[i];
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uart_obj[i].serial.ops = &ab32_uart_ops;
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uart_obj[i].serial.config = config;
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uart_obj[0].serial.config.baud_rate = 1500000;
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uart_obj[i].serial.config.baud_rate = 1500000;
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/* register UART device */
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result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
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@ -80,8 +80,6 @@ enum
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#define GPIO_PIN_6 (BIT(6))
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#define GPIO_PIN_7 (BIT(7))
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#define __HAL_GPIO_SET_DIR(__PORT__, __PIN__, __DIR__) (__DIR__) ? (GPIOx_REG((__PORT__), (GPIOxDIR)) |= BIT(__PIN__)) : (GPIOx_REG((__PORT__), (GPIOxDIR)) &= ~BIT(__PIN__))
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/* Include GPIO HAL Extended module */
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#include "ab32vg1_hal_gpio_ex.h"
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@ -34,5 +34,5 @@ void hal_udelay(uint16_t nus)
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}
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}
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WEAK void hal_printf(const char *format, ...)
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WEAK void hal_printf(const char *fmt, ...)
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{}
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@ -23,12 +23,6 @@
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#define WEAK __attribute__((weak))
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#define PACKED __attribute__((packed))
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// #define WDT_CLR() WDTCON = 0xa
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// #define WDT_EN() WDTCON = 0x110
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// #define WDT_DIS() WDTCON = 0xaa0
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// #define WDT_RST() WDTCON = 0xa000110; while (1)
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// #define WDT_RST_DELAY() WDTCON = 0xa100110; while (1)
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#define BYTE0(n) ((unsigned char)(n))
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#define BYTE1(n) ((unsigned char)((n)>>8))
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#define BYTE2(n) ((unsigned char)((n)>>16))
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@ -9,44 +9,18 @@
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.global _start
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.section .reset, "ax"
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_start:
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//load comm
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la a0, __comm_vma
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la a1, __comm_lma
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la a2, __comm_size
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call 0x84044
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/* memcpy start */
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//先按32 BYTE一个循环来copy
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mv t0, a0 //备份dst
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srli t1, a2, 5 //长度除32的商
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slli t1, t1, 5
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add t1, a0, t1 //t1存放对齐的结束地址
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_memcpy_loop1: //8 WORDS every cycle
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lw a2, 0(a1)
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lw a3, 4(a1)
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lw a4, 8(a1)
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lw a5, 12(a1)
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sw a2, 0(a0)
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sw a3, 4(a0)
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sw a4, 8(a0)
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sw a5, 12(a0)
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lw a2, 16(a1)
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lw a3, 20(a1)
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lw a4, 24(a1)
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lw a5, 28(a1)
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sw a2, 16(a0)
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sw a3, 20(a0)
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sw a4, 24(a0)
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sw a5, 28(a0)
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addi a0, a0, 32
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addi a1, a1, 32
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blt a0, t1, _memcpy_loop1
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mv a0, t0 //返回dst
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/* memcpy end */
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//load ram1
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la a0, __ram1_vma
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la a1, __ram1_lma
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la a2, __ram1_size
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call 0x84044
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la a0, __irq_stack_start //Stack清成0x23
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li a1, 0x23
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@ -83,7 +57,6 @@ _start:
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mret
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.global cpu_irq_comm
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.section .com_text.irq
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cpu_irq_comm:
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la a5, __irq_stack
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mv sp, a5
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@ -20,7 +20,6 @@ typedef struct _sys_t {
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uint32_t uart0baud; //UART0BAUD
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} sys_t;
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AT(.text.sys_clk.table)
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const uint8_t sysclk_sel_tbl[] = {
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OSCDIV_2M, //SYS_2M
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PLL0DIV_12M, //SYS_12M
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@ -34,7 +33,6 @@ const uint8_t sysclk_sel_tbl[] = {
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PLL0DIV_120M, //SYS_120M
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};
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AT(.text.sys_clk.table)
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const uint8_t sysclk_index[] = {
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2,
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12,
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@ -51,7 +49,6 @@ const uint8_t sysclk_index[] = {
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sys_t sys = {0};
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void my_printf(const char *format, ...);
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AT(.com_text.delay)
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static void delay_us(uint16_t nus)
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{
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int i;
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@ -60,13 +57,11 @@ static void delay_us(uint16_t nus)
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}
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}
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AT(.text.sys_clk)
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uint8_t get_clksel_val(uint8_t val)
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{
|
||||
return sysclk_sel_tbl[val];
|
||||
}
|
||||
|
||||
AT(.text.sys_clk)
|
||||
uint8_t get_cur_sysclk(void)
|
||||
{
|
||||
return sys.sys_clk;
|
||||
|
|
@ -90,13 +85,11 @@ uint32_t get_sysclk_nhz(void)
|
|||
// }
|
||||
//}
|
||||
|
||||
AT(.text.sys_clk)
|
||||
uint8_t get_sd_rate(void)
|
||||
{
|
||||
return 0; //unit: M
|
||||
}
|
||||
|
||||
AT(.text.sys_clk)
|
||||
uint8_t set_sd_baud(uint8_t sd_rate)
|
||||
{
|
||||
uint8_t sd0baud=0;
|
||||
|
|
@ -148,7 +141,6 @@ void update_sd0baud(void)
|
|||
}
|
||||
}
|
||||
|
||||
AT(.text.sys_clk)
|
||||
uint8_t sysclk_update_baud(uint8_t baud)
|
||||
{
|
||||
uint8_t sd_rate=get_sd_rate();
|
||||
|
|
@ -181,7 +173,6 @@ void set_sys_uart0baud(uint32_t baud)
|
|||
}
|
||||
|
||||
//切系统时钟前，先设置模块时钟分频较大值，保证模块不会超频的情况
|
||||
AT(.com_text.sys)
|
||||
void set_peripherals_clkdiv_safety(void)
|
||||
{
|
||||
uint32_t clkcon3 = CLKCON3;
|
||||
|
|
|
|||
Loading…
Reference in New Issue