[bluetrum] edit .lds

Expand the COMM section
This commit is contained in:
greedyhao 2020-12-15 23:43:04 +08:00
parent ec060312b7
commit 54c880e979
14 changed files with 134 additions and 97 deletions

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@ -23,7 +23,18 @@ CONFIG_IDLE_THREAD_STACK_SIZE=1024
CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_DEBUG is not set CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
# #
# Inter-Thread communication # Inter-Thread communication
@ -83,7 +94,7 @@ CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y CONFIG_FINSH_USING_DESCRIPTION=y
CONFIG_FINSH_ECHO_DISABLE_DEFAULT=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80 CONFIG_FINSH_CMD_SIZE=80
@ -417,7 +428,10 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_MULTIBUTTON_V102 is not set
# CONFIG_PKG_USING_MULTIBUTTON_LATEST_VERSION is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_ZLIB is not set
@ -458,7 +472,20 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# #
# General Purpose UARTs # Hardware Drivers Config
#
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
#
# On-chip Peripheral Drivers
# #
CONFIG_BSP_USING_UART0=y CONFIG_BSP_USING_UART0=y
#
# Board extended module Drivers
#
CONFIG_BOARD_BLUETRUM_EVB=y CONFIG_BOARD_BLUETRUM_EVB=y

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@ -2,9 +2,12 @@
*.bin *.bin
*.dcf *.dcf
*.map *.map
*.lst
*.pyc *.pyc
*.elf *.elf
*.old *.old
*.o
build build
dist dist
packages

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@ -102,6 +102,8 @@ msh >
## 注意事项 ## 注意事项
波特率默认为 1.5M,需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片
编译报错的时候,如果出现重复定义的报错,可能需要在 `cconfig.h` 中手动添加以下配置 编译报错的时候,如果出现重复定义的报错,可能需要在 `cconfig.h` 中手动添加以下配置
``` ```

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@ -1,4 +1,16 @@
menu "General Purpose UARTs" menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart0)"
select BSP_USING_UART
select BSP_USING_UART0
default y
endmenu
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART0 menuconfig BSP_USING_UART0
bool "Enable UART0" bool "Enable UART0"
@ -6,3 +18,8 @@ menuconfig BSP_USING_UART0
default y default y
endmenu endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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@ -17,7 +17,7 @@ void timer0_cfg(uint32_t ticks);
void rt_soft_isr(int vector, void *param); void rt_soft_isr(int vector, void *param);
void cpu_irq_comm(void); void cpu_irq_comm(void);
void set_cpu_irq_comm(void (*irq_hook)(void)); void set_cpu_irq_comm(void (*irq_hook)(void));
extern uint32_t __aram_start, __eram_end; extern uint32_t __heap_start, __heap_end;
void hal_printf(const char *fmt, ...) void hal_printf(const char *fmt, ...)
{ {
@ -108,7 +108,7 @@ void rt_hw_board_init(void)
rt_hw_systick_init(); rt_hw_systick_init();
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
rt_system_heap_init(&__aram_start, &__eram_end); rt_system_heap_init(&__heap_start, &__heap_end);
#endif #endif
#ifdef RT_USING_PIN #ifdef RT_USING_PIN

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@ -1,21 +1,26 @@
/* Define the flash max size */ /* Define the flash max size */
__max_flash_size = 768k; __max_flash_size = 768k;
__comm_ram_size = 104k;
__heap_ram_size = 14k;
__base = 0x10000000; __base = 0x10000000;
__comm_vma = 0x17000; __comm_vma = 0x12800;
__max_comm_size = 76k; __heap_vma = __comm_vma + __comm_ram_size;
__ram1_vma = 0x50000;
MEMORY MEMORY
{ {
init : org = __base, len = 512 init : org = __base, len = 512
flash(rx) : org = __base + 512, len = __max_flash_size flash(rx) : org = __base + 512, len = __max_flash_size
comm(rx) : org = __comm_vma, len = __max_comm_size comm(rx) : org = __comm_vma, len = __comm_ram_size
data : org = 0x11000, len = 16k
stack : org = 0x15000, len = 8k data : org = 0x11000, len = 5k
aram : org = 0x50000, len = 16k stack : org = 0x12400, len = 1k
dram : org = 0x54000, len = 12k heap : org = __heap_vma, len = __heap_ram_size
eram : org = 0x57000, len = 0xa00 ram1(rx) : org = __ram1_vma, len = 0x7a00
} }
SECTIONS SECTIONS
@ -24,17 +29,17 @@ SECTIONS
*(.reset) *(.reset)
} > init } > init
.comm : { .ram1 __ram1_vma : {
KEEP(*(.vector)) /*board\\ports\\*.o(.text*)*/
*(.com_text*) *hal_drivers\\*.o(.text*)
*(.text*) *hal_libraries\\ab32vg1_hal\\*.o(.text*)
*(.rodata*) *components\\drivers\\*.o(.text* .rodata*)
*(.com_rodata*) *components\\libc\\*.o(.text*)
*(.rela*) *ab32vg1_hal_msp.o(.text*)
*(.data*) *components.o(.text* .rodata*)
*(.sdata*) *ipc.o(.text* .rodata*)
LONG(0) . = ALIGN(32);
} > comm AT > flash } > ram1 AT > flash
.rti : { .rti : {
. = ALIGN(4); . = ALIGN(4);
@ -52,6 +57,19 @@ SECTIONS
__vsymtab_start = .; __vsymtab_start = .;
KEEP(*(VSymTab)) KEEP(*(VSymTab))
__vsymtab_end = .; __vsymtab_end = .;
. = ALIGN(32);
} > ram1 AT > flash
.comm : {
KEEP(*(.vector))
*(.text*)
*(.rodata*)
*(.srodata*)
*(.rela*)
*(.data*)
*(.sdata*)
. = ALIGN(512);
} > comm AT > flash } > comm AT > flash
.flash : { .flash : {
@ -71,26 +89,21 @@ SECTIONS
.stack (NOLOAD) : { .stack (NOLOAD) : {
__irq_stack_start = .; __irq_stack_start = .;
. = 0x2000; . = 0x400;
__irq_stack = .; __irq_stack = .;
} > stack } > stack
__irq_stack_size = __irq_stack - __irq_stack_start; __irq_stack_size = __irq_stack - __irq_stack_start;
.code_aecram (NOLOAD): { .heap : {
__aram_start = .; __heap_start = .;
} > aram . = __heap_ram_size;
__heap_end = .;
.code_decram (NOLOAD): { } > heap
} > dram
.code_encram (NOLOAD): {
__eram_start = .;
. = 0xa00;
__eram_end = .;
} > eram
} }
/* Calc the lma */ /* Calc the lma */
__bank_size = SIZEOF(.flash); __bank_size = SIZEOF(.flash);
__comm_lma = LOADADDR(.comm); __comm_lma = LOADADDR(.comm);
__comm_size = SIZEOF(.comm) + SIZEOF(.rti); __comm_size = SIZEOF(.comm);
__ram1_lma = LOADADDR(.ram1);
__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);

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@ -19,6 +19,7 @@
#define RT_USING_TIMER_SOFT #define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_DEBUG
/* Inter-Thread communication */ /* Inter-Thread communication */
@ -62,7 +63,6 @@
#define FINSH_HISTORY_LINES 5 #define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB #define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION #define FINSH_USING_DESCRIPTION
#define FINSH_ECHO_DISABLE_DEFAULT
#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80 #define FINSH_CMD_SIZE 80
@ -154,9 +154,18 @@
/* games: games run on RT-Thread console */ /* games: games run on RT-Thread console */
/* General Purpose UARTs */ /* Hardware Drivers Config */
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_UART0 #define BSP_USING_UART0
/* Board extended module Drivers */
#define BOARD_BLUETRUM_EVB #define BOARD_BLUETRUM_EVB
#endif #endif

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@ -40,9 +40,19 @@ static const hal_sfr_t port_sfr[] =
GPIOF_BASE, GPIOF_BASE,
}; };
static uint8_t _pin_port(uint32_t pin)
{
uint8_t port = 0;
for (port = 0; port < 3; port++) {
if (pin < (port_table[port].total_pin + port_table[port].delta_pin)) {
break;
}
}
return port;
}
#define PIN_NUM(port, no) ((uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin)) #define PIN_NUM(port, no) ((uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin))
#define _PIN_PORT(pin) (uint8_t)(((pin) >> 3) & 0xFu) #define PIN_PORT(pin) _pin_port(pin)
#define PIN_PORT(pin) ((port_table[_PIN_PORT(pin)].delta_pin == 8) ? _PIN_PORT(pin) : _PIN_PORT(pin) + 1)
#define PORT_SFR(port) (port_sfr[(port)]) #define PORT_SFR(port) (port_sfr[(port)])
#define PIN_NO(pin) (uint8_t)((pin) & 0xFu) #define PIN_NO(pin) (uint8_t)((pin) & 0xFu)
@ -95,7 +105,7 @@ static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{ {
uint8_t port = PIN_PORT(pin); uint8_t port = PIN_PORT(pin);
uint8_t gpio_pin = pin - port_table[port].total_pin; uint8_t gpio_pin = pin - port_table[port].total_pin;
hal_gpio_write(PORT_SFR(port), gpio_pin, value); hal_gpio_write(PORT_SFR(port), gpio_pin, (uint8_t)value);
} }
static int ab32_pin_read(rt_device_t dev, rt_base_t pin) static int ab32_pin_read(rt_device_t dev, rt_base_t pin)

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@ -187,7 +187,7 @@ int rt_hw_usart_init(void)
uart_obj[i].config = &uart_config[i]; uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &ab32_uart_ops; uart_obj[i].serial.ops = &ab32_uart_ops;
uart_obj[i].serial.config = config; uart_obj[i].serial.config = config;
uart_obj[0].serial.config.baud_rate = 1500000; uart_obj[i].serial.config.baud_rate = 1500000;
/* register UART device */ /* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,

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@ -80,8 +80,6 @@ enum
#define GPIO_PIN_6 (BIT(6)) #define GPIO_PIN_6 (BIT(6))
#define GPIO_PIN_7 (BIT(7)) #define GPIO_PIN_7 (BIT(7))
#define __HAL_GPIO_SET_DIR(__PORT__, __PIN__, __DIR__) (__DIR__) ? (GPIOx_REG((__PORT__), (GPIOxDIR)) |= BIT(__PIN__)) : (GPIOx_REG((__PORT__), (GPIOxDIR)) &= ~BIT(__PIN__))
/* Include GPIO HAL Extended module */ /* Include GPIO HAL Extended module */
#include "ab32vg1_hal_gpio_ex.h" #include "ab32vg1_hal_gpio_ex.h"

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@ -34,5 +34,5 @@ void hal_udelay(uint16_t nus)
} }
} }
WEAK void hal_printf(const char *format, ...) WEAK void hal_printf(const char *fmt, ...)
{} {}

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@ -23,12 +23,6 @@
#define WEAK __attribute__((weak)) #define WEAK __attribute__((weak))
#define PACKED __attribute__((packed)) #define PACKED __attribute__((packed))
// #define WDT_CLR() WDTCON = 0xa
// #define WDT_EN() WDTCON = 0x110
// #define WDT_DIS() WDTCON = 0xaa0
// #define WDT_RST() WDTCON = 0xa000110; while (1)
// #define WDT_RST_DELAY() WDTCON = 0xa100110; while (1)
#define BYTE0(n) ((unsigned char)(n)) #define BYTE0(n) ((unsigned char)(n))
#define BYTE1(n) ((unsigned char)((n)>>8)) #define BYTE1(n) ((unsigned char)((n)>>8))
#define BYTE2(n) ((unsigned char)((n)>>16)) #define BYTE2(n) ((unsigned char)((n)>>16))

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@ -9,44 +9,18 @@
.global _start .global _start
.section .reset, "ax" .section .reset, "ax"
_start: _start:
//load comm //load comm
la a0, __comm_vma la a0, __comm_vma
la a1, __comm_lma la a1, __comm_lma
la a2, __comm_size la a2, __comm_size
call 0x84044
/* memcpy start */ //load ram1
//32 BYTEcopy la a0, __ram1_vma
mv t0, a0 //dst la a1, __ram1_lma
srli t1, a2, 5 //32 la a2, __ram1_size
call 0x84044
slli t1, t1, 5
add t1, a0, t1 //t1
_memcpy_loop1: //8 WORDS every cycle
lw a2, 0(a1)
lw a3, 4(a1)
lw a4, 8(a1)
lw a5, 12(a1)
sw a2, 0(a0)
sw a3, 4(a0)
sw a4, 8(a0)
sw a5, 12(a0)
lw a2, 16(a1)
lw a3, 20(a1)
lw a4, 24(a1)
lw a5, 28(a1)
sw a2, 16(a0)
sw a3, 20(a0)
sw a4, 24(a0)
sw a5, 28(a0)
addi a0, a0, 32
addi a1, a1, 32
blt a0, t1, _memcpy_loop1
mv a0, t0 //dst
/* memcpy end */
la a0, __irq_stack_start //Stack0x23 la a0, __irq_stack_start //Stack0x23
li a1, 0x23 li a1, 0x23
@ -83,7 +57,6 @@ _start:
mret mret
.global cpu_irq_comm .global cpu_irq_comm
.section .com_text.irq
cpu_irq_comm: cpu_irq_comm:
la a5, __irq_stack la a5, __irq_stack
mv sp, a5 mv sp, a5

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@ -20,7 +20,6 @@ typedef struct _sys_t {
uint32_t uart0baud; //UART0BAUD uint32_t uart0baud; //UART0BAUD
} sys_t; } sys_t;
AT(.text.sys_clk.table)
const uint8_t sysclk_sel_tbl[] = { const uint8_t sysclk_sel_tbl[] = {
OSCDIV_2M, //SYS_2M OSCDIV_2M, //SYS_2M
PLL0DIV_12M, //SYS_12M PLL0DIV_12M, //SYS_12M
@ -34,7 +33,6 @@ const uint8_t sysclk_sel_tbl[] = {
PLL0DIV_120M, //SYS_120M PLL0DIV_120M, //SYS_120M
}; };
AT(.text.sys_clk.table)
const uint8_t sysclk_index[] = { const uint8_t sysclk_index[] = {
2, 2,
12, 12,
@ -51,7 +49,6 @@ const uint8_t sysclk_index[] = {
sys_t sys = {0}; sys_t sys = {0};
void my_printf(const char *format, ...); void my_printf(const char *format, ...);
AT(.com_text.delay)
static void delay_us(uint16_t nus) static void delay_us(uint16_t nus)
{ {
int i; int i;
@ -60,13 +57,11 @@ static void delay_us(uint16_t nus)
} }
} }
AT(.text.sys_clk)
uint8_t get_clksel_val(uint8_t val) uint8_t get_clksel_val(uint8_t val)
{ {
return sysclk_sel_tbl[val]; return sysclk_sel_tbl[val];
} }
AT(.text.sys_clk)
uint8_t get_cur_sysclk(void) uint8_t get_cur_sysclk(void)
{ {
return sys.sys_clk; return sys.sys_clk;
@ -90,13 +85,11 @@ uint32_t get_sysclk_nhz(void)
// } // }
//} //}
AT(.text.sys_clk)
uint8_t get_sd_rate(void) uint8_t get_sd_rate(void)
{ {
return 0; //unit: M return 0; //unit: M
} }
AT(.text.sys_clk)
uint8_t set_sd_baud(uint8_t sd_rate) uint8_t set_sd_baud(uint8_t sd_rate)
{ {
uint8_t sd0baud=0; uint8_t sd0baud=0;
@ -148,7 +141,6 @@ void update_sd0baud(void)
} }
} }
AT(.text.sys_clk)
uint8_t sysclk_update_baud(uint8_t baud) uint8_t sysclk_update_baud(uint8_t baud)
{ {
uint8_t sd_rate=get_sd_rate(); uint8_t sd_rate=get_sd_rate();
@ -181,7 +173,6 @@ void set_sys_uart0baud(uint32_t baud)
} }
//切系统时钟前,先设置模块时钟分频较大值,保证模块不会超频的情况 //切系统时钟前,先设置模块时钟分频较大值,保证模块不会超频的情况
AT(.com_text.sys)
void set_peripherals_clkdiv_safety(void) void set_peripherals_clkdiv_safety(void)
{ {
uint32_t clkcon3 = CLKCON3; uint32_t clkcon3 = CLKCON3;