libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

[fixup] check NULL pointer before access (#8573) 

Signed-off-by: Shell <smokewood@qq.com>
This commit is contained in:
Shell 2024-03-02 16:05:19 +08:00 committed by GitHub
parent 00c6800e4e
commit 53754ff50a
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
7 changed files with 54 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
bsp/qemu-virt64-aarch64/applications/main.c
View File

@ -9,10 +9,11 @@
*/ */
#include <stdio.h> #include <stdio.h>
#include <rtthread.h>
int main(void) int main(void)
{ {
printf("hello rt-thread\n"); rt_kprintf("hello rt-thread\n");
return 0; return 0;
} }

8
bsp/qemu-virt64-aarch64/drivers/secondary_cpu.c
View File

@ -14,6 +14,10 @@
#include "mmu.h" #include "mmu.h"
#include "gtimer.h" #include "gtimer.h"
#ifdef BSP_USING_GICV3
#include <gicv3.h>
#endif
#ifdef RT_USING_SMP #ifdef RT_USING_SMP
extern unsigned long MMUTable[]; extern unsigned long MMUTable[];
@ -29,6 +33,10 @@ void rt_hw_secondary_cpu_bsp_start(void)
arm_gic_cpu_init(0, 0); arm_gic_cpu_init(0, 0);
#ifdef BSP_USING_GICV3
arm_gic_redist_init(0, 0);
#endif /* BSP_USING_GICV3 */
// local timer init // local timer init
rt_hw_gtimer_init(); rt_hw_gtimer_init();

2
components/mm/mm_aspace.c
View File

@ -1278,7 +1278,7 @@ int rt_aspace_load_page(rt_aspace_t aspace, void *addr, rt_size_t npage)
if (!varea) if (!varea)
{ {
LOG_W("%s: varea not exist", __func__); LOG_W("%s: varea not exist(addr=%p)", __func__, addr);
err = -RT_ENOENT; err = -RT_ENOENT;
} }
else if ((char *)addr >= end || (rt_size_t)addr & ARCH_PAGE_MASK || else if ((char *)addr >= end || (rt_size_t)addr & ARCH_PAGE_MASK ||

2
libcpu/aarch64/common/backtrace.c
View File

@ -85,7 +85,7 @@ rt_err_t rt_hw_backtrace_frame_unwind(rt_thread_t thread, struct rt_hw_backtrace
if (fp && !((long)fp & 0x7)) if (fp && !((long)fp & 0x7))
{ {
#ifdef RT_USING_SMART #ifdef RT_USING_SMART
if (thread->lwp) if (thread && thread->lwp)
{ {
rt_lwp_t lwp = thread->lwp; rt_lwp_t lwp = thread->lwp;
void *this_lwp = lwp_self(); void *this_lwp = lwp_self();

55
libcpu/aarch64/common/gicv3.c
View File

@ -81,24 +81,24 @@ static unsigned int _gic_max_irq;
#define ICC_ASGI1R_EL1 "S3_0_C12_C11_6" #define ICC_ASGI1R_EL1 "S3_0_C12_C11_6"
/* Macro to access the Distributor Control Register (GICD_CTLR) */ /* Macro to access the Distributor Control Register (GICD_CTLR) */
#define GICD_CTLR_RWP (1 << 31) #define GICD_CTLR_RWP (1U << 31)
#define GICD_CTLR_E1NWF (1 << 7) #define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_DS (1 << 6) #define GICD_CTLR_DS (1U << 6)
#define GICD_CTLR_ARE_NS (1 << 5) #define GICD_CTLR_ARE_NS (1U << 5)
#define GICD_CTLR_ARE_S (1 << 4) #define GICD_CTLR_ARE_S (1U << 4)
#define GICD_CTLR_ENGRP1S (1 << 2) #define GICD_CTLR_ENGRP1S (1U << 2)
#define GICD_CTLR_ENGRP1NS (1 << 1) #define GICD_CTLR_ENGRP1NS (1U << 1)
#define GICD_CTLR_ENGRP0 (1 << 0) #define GICD_CTLR_ENGRP0 (1U << 0)
/* Macro to access the Redistributor Control Register (GICR_CTLR) */ /* Macro to access the Redistributor Control Register (GICR_CTLR) */
#define GICR_CTLR_UWP (1 << 31) #define GICR_CTLR_UWP (1U << 31)
#define GICR_CTLR_DPG1S (1 << 26) #define GICR_CTLR_DPG1S (1U << 26)
#define GICR_CTLR_DPG1NS (1 << 25) #define GICR_CTLR_DPG1NS (1U << 25)
#define GICR_CTLR_DPG0 (1 << 24) #define GICR_CTLR_DPG0 (1U << 24)
#define GICR_CTLR_RWP (1 << 3) #define GICR_CTLR_RWP (1U << 3)
#define GICR_CTLR_IR (1 << 2) #define GICR_CTLR_IR (1U << 2)
#define GICR_CTLR_CES (1 << 1) #define GICR_CTLR_CES (1U << 1)
#define GICR_CTLR_EnableLPI (1 << 0) #define GICR_CTLR_EnableLPI (1U << 0)
/* Macro to access the Generic Interrupt Controller Interface (GICC) */ /* Macro to access the Generic Interrupt Controller Interface (GICC) */
#define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U) #define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U)
@ -162,7 +162,7 @@ static unsigned int _gic_max_irq;
int arm_gic_get_active_irq(rt_uint64_t index) int arm_gic_get_active_irq(rt_uint64_t index)
{ {
int irq; rt_base_t irq;
RT_ASSERT(index < ARM_GIC_MAX_NR); RT_ASSERT(index < ARM_GIC_MAX_NR);
@ -178,7 +178,7 @@ void arm_gic_ack(rt_uint64_t index, int irq)
RT_ASSERT(irq >= 0); RT_ASSERT(irq >= 0);
__DSB(); __DSB();
SET_GICV3_REG(ICC_EOIR1_EL1, irq); SET_GICV3_REG(ICC_EOIR1_EL1, (rt_base_t)irq);
} }
void arm_gic_mask(rt_uint64_t index, int irq) void arm_gic_mask(rt_uint64_t index, int irq)
@ -397,7 +397,7 @@ void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority)
rt_int32_t cpu_id = rt_hw_cpu_id(); rt_int32_t cpu_id = rt_hw_cpu_id();
mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq);
mask &= ~(0xff << ((irq % 4) * 8)); mask &= ~(0xffUL << ((irq % 4) * 8));
mask |= ((priority & 0xff) << ((irq % 4) * 8)); mask |= ((priority & 0xff) << ((irq % 4) * 8));
GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask;
} }
@ -468,7 +468,7 @@ rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index)
void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point) void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point)
{ {
index = index; RT_UNUSED(index);
binary_point &= 0x7; binary_point &= 0x7;
SET_GICV3_REG(ICC_BPR1_EL1, binary_point); SET_GICV3_REG(ICC_BPR1_EL1, binary_point);
@ -478,7 +478,7 @@ rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index)
{ {
rt_uint64_t binary_point; rt_uint64_t binary_point;
index = index; RT_UNUSED(index);
GET_GICV3_REG(ICC_BPR1_EL1, binary_point); GET_GICV3_REG(ICC_BPR1_EL1, binary_point);
return binary_point; return binary_point;
} }
@ -616,7 +616,7 @@ rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
rt_uint64_t irq; rt_uint64_t irq;
RT_ASSERT(index < ARM_GIC_MAX_NR); RT_ASSERT(index < ARM_GIC_MAX_NR);
index = index; RT_UNUSED(index);
GET_GICV3_REG(ICC_HPPIR1_EL1, irq); GET_GICV3_REG(ICC_HPPIR1_EL1, irq);
return irq; return irq;
@ -625,13 +625,18 @@ rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index) rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index)
{ {
rt_uint64_t ret = 0; rt_uint64_t ret = 0;
rt_base_t level;
int cpuid;
RT_ASSERT(index < ARM_GIC_MAX_NR); RT_ASSERT(index < ARM_GIC_MAX_NR);
if (_gic_table[index].cpu_hw_base != RT_NULL) level = rt_hw_local_irq_disable();
cpuid = rt_hw_cpu_id();
if (_gic_table[index].cpu_hw_base[cpuid] != RT_NULL)
{ {
ret = GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); ret = GIC_CPU_IIDR(_gic_table[index].cpu_hw_base[cpuid]);
} }
rt_hw_local_irq_enable(level);
return ret; return ret;
} }
@ -857,7 +862,7 @@ int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base)
value = arm_gic_get_system_register_enable_mask(index); value = arm_gic_get_system_register_enable_mask(index);
value |= (1 << 0); value |= (1 << 0);
arm_gic_set_system_register_enable_mask(index, value); arm_gic_set_system_register_enable_mask(index, value);
SET_GICV3_REG(ICC_CTLR_EL1, 0); SET_GICV3_REG(ICC_CTLR_EL1, 0l);
arm_gic_set_interface_prior_mask(index, 0xff); arm_gic_set_interface_prior_mask(index, 0xff);

4
libcpu/aarch64/common/setup.c
View File

@ -390,8 +390,10 @@ void rt_hw_common_setup(void)
for (int i = 0; i < mem_region_nr; ++i, ++mem_region) for (int i = 0; i < mem_region_nr; ++i, ++mem_region)
{ {
if (mem_region != page_region) if (mem_region != page_region && mem_region->name)
{ {
mem_region->start -= PV_OFFSET;
mem_region->end -= PV_OFFSET;
rt_page_install(*mem_region); rt_page_install(*mem_region);
} }
} }

7
src/scheduler_mp.c
View File

@ -1255,8 +1255,15 @@ rt_uint16_t rt_critical_level(void)
current_thread = rt_cpu_self()->current_thread; current_thread = rt_cpu_self()->current_thread;
if (current_thread)
{
/* the necessary memory barrier is done on irq_(dis|en)able */ /* the necessary memory barrier is done on irq_(dis|en)able */
critical_lvl = RT_SCHED_CTX(current_thread).critical_lock_nest; critical_lvl = RT_SCHED_CTX(current_thread).critical_lock_nest;
}
else
{
critical_lvl = 0;
}
rt_hw_local_irq_enable(level); rt_hw_local_irq_enable(level);
return critical_lvl; return critical_lvl;