support gcc for ch32f10x.
This commit is contained in:
charlown
parent
02a3ac4036
commit
5169360e21
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@ -0,0 +1,313 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : startup_ch32f10x.s
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* Author : WCH
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* Version : V1.0.0
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* Date : 2020/11/01
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* Description : CH32F10x vector table for GCC toolchain.
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*******************************************************************************/
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.syntax unified
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.cpu cortex-m3
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/*******************************************************************************
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Reset handler
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*******************************************************************************/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/*******************************************************************************
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This simply enters an infinite loop.
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*******************************************************************************/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/*******************************************************************************
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Vector Table Mapped to Address 0 at Reset.
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/*******************************************************************************
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External Interrupts
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*******************************************************************************/
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word TAMPER_IRQHandler
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.word RTC_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word DMA1_Channel5_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_2_IRQHandler
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.word USB_HP_CAN1_TX_IRQHandler
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.word USB_LP_CAN1_RX0_IRQHandler
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.word CAN1_RX1_IRQHandler
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.word CAN1_SCE_IRQHandler
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.word EXTI9_5_IRQHandler
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.word TIM1_BRK_IRQHandler
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.word TIM1_UP_IRQHandler
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.word TIM1_TRG_COM_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word TIM4_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word I2C2_EV_IRQHandler
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.word I2C2_ER_IRQHandler
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word USART1_IRQHandler
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.word USART2_IRQHandler
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.word USART3_IRQHandler
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.word EXTI15_10_IRQHandler
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.word RTCAlarm_IRQHandler
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.word USBWakeUp_IRQHandler
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.word USBHD_IRQHandler
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/*******************************************************************************
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Dummy Exception Handlers (infinite loops which can be modified)
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler,Default_Handler
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.weak TAMPER_IRQHandler
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.thumb_set TAMPER_IRQHandler,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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.weak DMA1_Channel2_IRQHandler
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.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
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.weak DMA1_Channel3_IRQHandler
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.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
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.weak DMA1_Channel4_IRQHandler
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.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
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.weak DMA1_Channel5_IRQHandler
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.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
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.weak DMA1_Channel6_IRQHandler
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.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
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.weak DMA1_Channel7_IRQHandler
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.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
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.weak ADC1_2_IRQHandler
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.thumb_set ADC1_2_IRQHandler,Default_Handler
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.weak USB_HP_CAN1_TX_IRQHandler
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.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
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.weak USB_LP_CAN1_RX0_IRQHandler
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.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
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.weak CAN1_RX1_IRQHandler
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.thumb_set CAN1_RX1_IRQHandler,Default_Handler
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.weak CAN1_SCE_IRQHandler
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.thumb_set CAN1_SCE_IRQHandler,Default_Handler
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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.weak TIM1_BRK_IRQHandler
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.thumb_set TIM1_BRK_IRQHandler,Default_Handler
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.weak TIM1_UP_IRQHandler
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.thumb_set TIM1_UP_IRQHandler,Default_Handler
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.weak TIM1_TRG_COM_IRQHandler
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.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler,Default_Handler
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.weak TIM4_IRQHandler
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.thumb_set TIM4_IRQHandler,Default_Handler
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.weak I2C1_EV_IRQHandler
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.thumb_set I2C1_EV_IRQHandler,Default_Handler
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.weak I2C1_ER_IRQHandler
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.thumb_set I2C1_ER_IRQHandler,Default_Handler
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.weak I2C2_EV_IRQHandler
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.thumb_set I2C2_EV_IRQHandler,Default_Handler
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.weak I2C2_ER_IRQHandler
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.thumb_set I2C2_ER_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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.weak USART2_IRQHandler
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.thumb_set USART2_IRQHandler,Default_Handler
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.weak USART3_IRQHandler
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.thumb_set USART3_IRQHandler,Default_Handler
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.weak EXTI15_10_IRQHandler
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.thumb_set EXTI15_10_IRQHandler,Default_Handler
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.weak RTCAlarm_IRQHandler
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.thumb_set RTCAlarm_IRQHandler,Default_Handler
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.weak USBWakeUp_IRQHandler
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.thumb_set USBWakeUp_IRQHandler,Default_Handler
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.weak USBHD_IRQHandler
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.thumb_set USBHD_IRQHandler,Default_Handler
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@ -17,6 +17,8 @@ startup_path_prefix = SDK_LIB
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if rtconfig.CROSS_TOOL == 'keil':
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src += [startup_path_prefix + '/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Source/ARM/startup_ch32f10x.s']
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [startup_path_prefix + '/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Source/GCC/startup_ch32f10x.S']
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path = [cwd]
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@ -0,0 +1,152 @@
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/* Program Entry, set to mark it as "used" and avoid gc */
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x08000000, LENGTH = 64k /* 64KB flash */
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RAM (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 20K sram */
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}
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ENTRY(Reset_Handler)
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_system_stack_size = 0x200;
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SECTIONS
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{
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.text :
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{
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. = ALIGN(4);
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_stext = .;
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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*(.gnu.linkonce.t*)
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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/* section information for initial. */
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(4);
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PROVIDE(__ctors_start__ = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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PROVIDE(__ctors_end__ = .);
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. = ALIGN(4);
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_etext = .;
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} > ROM = 0
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = .;
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} > ROM
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__exidx_end = .;
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/* .data section which is used for initialized data */
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.data : AT (_sidata)
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d*)
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(__dtors_end__ = .);
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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.stack :
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{
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. = ALIGN(4);
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_sstack = .;
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. = . + _system_stack_size;
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. = ALIGN(4);
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_estack = .;
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} >RAM
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__bss_start = .;
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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*(.bss.init)
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} > RAM
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__bss_end = .;
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_end = .;
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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* Symbols in the DWARF debugging sections are relative to the beginning
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* of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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