Merge pull request #766 from AubrCool/fix-stm32f10x.wdt
[BSP] stm32f10x add watchdog driver
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commit
5148b9ff27
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@ -39,6 +39,10 @@ if GetDepend('RT_USING_RTGUI'):
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elif rtconfig.RT_USING_LCD_TYPE == 'SSD1289':
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src += ['ssd1289.c']
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# add wdt driver.
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if GetDepend('RT_USING_WDT'):
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src += ['stm32f1_wdg.c']
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CPPPATH = [cwd]
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@ -0,0 +1,118 @@
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/*
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* File : stm32f1_wdg.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-01-18 aubrcool@qq.com 1st version
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*/
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#include "stm32f10x.h"
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#include <rtdevice.h>
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#ifdef RT_USING_WDT
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static rt_err_t stm32f1_wdg_init(rt_watchdog_t *wdt)
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{
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return RT_EOK;
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}
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static rt_err_t stm32f1_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
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{
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rt_uint32_t timeout_ms = 0;
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rt_uint32_t timeout_pow = 1;
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switch(cmd)
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{
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case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
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timeout_ms = (rt_uint32_t) arg;
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IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
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if(timeout_ms >= 13107)
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{
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if(timeout_ms >= 26214)
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{
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timeout_ms = 26214;
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}
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IWDG_SetPrescaler(IWDG_Prescaler_256);
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timeout_pow = 256;
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}
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else if(timeout_ms >= 6553)
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{
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IWDG_SetPrescaler(IWDG_Prescaler_128);
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timeout_pow = 128;
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}
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else if(timeout_ms >= 3276)
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{
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IWDG_SetPrescaler(IWDG_Prescaler_64);
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timeout_pow = 64;
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}
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else if(timeout_ms >= 1638)
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{
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IWDG_SetPrescaler(IWDG_Prescaler_32);
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timeout_pow = 32;
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}
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else if(timeout_ms >= 819)
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{
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IWDG_SetPrescaler(IWDG_Prescaler_16);
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timeout_pow = 16;
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}
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else if(timeout_ms >= 409)
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{
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IWDG_SetPrescaler(IWDG_Prescaler_8);
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timeout_pow = 8;
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}
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else
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{
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IWDG_SetPrescaler(IWDG_Prescaler_4);
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timeout_pow = 4;
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}
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timeout_ms = timeout_ms * 40 / timeout_pow;
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if(timeout_ms > 0xFFF)
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{
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timeout_ms = 0xFFF;
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}
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IWDG_SetReload(timeout_ms);
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IWDG_ReloadCounter();
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break;
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case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
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timeout_pow = IWDG->PR;
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if(timeout_pow > 6)
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{
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timeout_pow = 6;
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}
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timeout_pow = 1 << (2 + timeout_pow);
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timeout_ms = IWDG->RLR;
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timeout_ms &= 0xFFF;
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*((rt_uint32_t *) arg) = timeout_ms * timeout_pow / 40;
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break;
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case RT_DEVICE_CTRL_WDT_KEEPALIVE:
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IWDG_ReloadCounter();
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break;
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case RT_DEVICE_CTRL_WDT_START:
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IWDG_Enable();
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break;
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default:
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return RT_EIO;
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}
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return RT_EOK;
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}
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static const struct rt_watchdog_ops stm32f1_wdg_pos =
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{
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stm32f1_wdg_init,
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stm32f1_wdg_control,
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};
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static rt_watchdog_t stm32f1_wdg;
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int rt_hw_wdg_init(void)
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{
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stm32f1_wdg.ops = &stm32f1_wdg_pos;
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rt_hw_watchdog_register(&stm32f1_wdg, "wdg", 0, RT_NULL);
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(rt_hw_wdg_init);
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#endif /*RT_USING_WDT*/
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@ -38,7 +38,7 @@ struct rt_watchdog_ops;
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struct rt_watchdog_device
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{
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struct rt_device parent;
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struct rt_watchdog_ops *ops;
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const struct rt_watchdog_ops *ops;
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};
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typedef struct rt_watchdog_device rt_watchdog_t;
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