bsp beaglebone: add IAR support (#6443)

* bsp beaglebone: add IAR template files and fix it's build error

ATTENTION:
project.* was generated by scons, so I add it to gitignore.
rtconfig.py *FLAGS located in "PLATFORM == 'iccarm'" are unverified and maybe wrong.
(我只是从STM32里面抄来,然后根据自己的理解改了一下,并没有验证这些参数的正确性,
我也不知道怎么用命令行调用这些参数来编译)

* bsp beaglebone: add beaglebone_ram.icf ROM address from uboot_cmd.txt

am335x_DDR.icf use 0x82000000, different to uboot_cmd.txt & gcc beaglebone_ram.lds,
the difference will easy cause later developer got below error:

=> go 0x80200000
## Starting application at 0x80200000 ...
undefined instruction
pc : [<8200956c>]	   lr : [<8ff62497>]
reloc pc : [<728a956c>]	   lr : [<80802497>]
sp : 8df37358  ip : 00000000	 fp : 00000002
r10: 8df4d448  r9 : 8df3feb8	 r8 : 8ffd30f8
r7 : 8ff78089  r6 : 00000002	 r5 : 80200000  r4 : 8df4d44c
r3 : 80200000  r2 : 8df4d44c	 r1 : 8df4d44c  r0 : 00000001
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32
Code: 5dbffcdd bb9bdf7f abf85423 eff1f77f (7ed7daaf)
Resetting CPU ...

resetting ...

* libcpu am335x: context_iar.S rt_hw_context_switch: add thumb mode support

IAR new project defualt Processor mode is Thumb, this will cause user
easy occur the following error:
...
msh />Execption:
r00:0x8800aaa8 r01:0x802080c5 r02:0x00000000 r03:0x88009b4c
r04:0x00001000 r05:0x00000000 r06:0x00001403 r07:0x00100000
r08:0x00000000 r09:0x00000000 r10:0x0000000a
fp :0x0000000a ip :0x65687374
sp :0x00006c6c lr :0x0000008a pc :0x88008be0
cpsr:0x880001bc
software interrupt
shutdown...
(0) assertion failed at function:rt_hw_cpu_shutdown, line number:160

* bsp beaglebone: change IAR template.ewp code use Arm mode

Arm mode bin size will bigger than Thumb mode

* libcpu am335x: IAR: use rt_hw_cpu_dcache_enable instead of rt_cpu_dcache_enable

Reviewer mysterywolf say:
麻烦把rt_cpu_icache_enable 和 rt_cpu_dcache_enable, 统一改成 rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable
rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable 是其他bsp也是这么命名的 这是个命名统一的函数
This commit is contained in:
YangZhongQing 2022-09-22 14:13:34 +08:00 committed by GitHub
parent 560166477e
commit 50cb4be8ce
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 2301 additions and 4 deletions

3
bsp/beaglebone/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
/DDR Debug
*.ewd
project.*

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@ -16,6 +16,9 @@
#if defined(__CC_ARM) #if defined(__CC_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit; extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) #define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
#elif defined(__ICCARM__)
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#elif defined(__GNUC__) #elif defined(__GNUC__)
extern int __bss_end; extern int __bss_end;
#define HEAP_BEGIN ((void*)&__bss_end) #define HEAP_BEGIN ((void*)&__bss_end)

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@ -0,0 +1,45 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x80200000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x80200000;
define symbol __ICFEDIT_region_ROM_end__ = 0x87FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x88000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x8FFFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x100;
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x100;
define symbol __ICFEDIT_size_undstack__ = 0x100;
define symbol __ICFEDIT_size_abtstack__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
initialize by copy { readwrite };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem :__ICFEDIT_intvec_start__ {readonly section .intvec};
place in ROM_region { readonly, block RTT_INIT_FUNC };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };

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@ -11,6 +11,9 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc': if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc' PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin' EXEC_PATH = r'C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 9.1'
if os.getenv('RTT_EXEC_PATH'): if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH') EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@ -48,3 +51,55 @@ if PLATFORM == 'gcc':
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
SIZE + ' $TARGET \n' SIZE + ' $TARGET \n'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
# ATTENTION from author vipox@qq.com: below *FLAGS are unverified and maybe wrong!
# I just copied it from STM32 and changed it according to my own understanding.
# However, even if it is wrong, it does not affect our generation of IAR project.
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-A8'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv3'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-A8'
AFLAGS += ' --fpu VFPv3'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "beaglebone_ram.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'

2144
bsp/beaglebone/template.ewp Normal file

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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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@ -40,6 +40,8 @@ rt_hw_context_switch:
STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC) STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC)
STMFD SP!, {R0-R12, LR} ; push lr & register file STMFD SP!, {R0-R12, LR} ; push lr & register file
MRS R4, CPSR MRS R4, CPSR
TST LR, #0x01
ORRNE R4, R4, #0x20 ; it's thumb code
STMFD SP!, {R4} ; push cpsr STMFD SP!, {R4} ; push cpsr
STR SP, [R0] ; store sp in preempted tasks TCB STR SP, [R0] ; store sp in preempted tasks TCB
LDR SP, [R1] ; get new task stack pointer LDR SP, [R1] ; get new task stack pointer
@ -56,6 +58,8 @@ rt_hw_context_switch_to:
LDR SP, [R0] ; get new task stack pointer LDR SP, [R0] ; get new task stack pointer
LDMFD SP!, {R4} ; pop new task spsr LDMFD SP!, {R4} ; pop new task spsr
MSR SPSR_cxsf, R4 MSR SPSR_cxsf, R4
BIC R4, R4, #0x20 ; must be ARM mode
MSR CPSR_CXSF, R4
LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc
/* /*

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@ -6,6 +6,8 @@
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2011-09-15 Bernard first version * 2011-09-15 Bernard first version
* 2022-09-20 YangZhongQing
* add IAR assembler
*/ */
#include <rthw.h> #include <rthw.h>
@ -86,10 +88,42 @@ rt_inline void cache_disable(rt_uint32_t bit)
:"r" (bit) \ :"r" (bit) \
:"memory"); :"memory");
} }
#elif defined(__ICCARM__)
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t tmp;
__asm volatile( \
"mrc p15,0,%0,c1,c0,0\n\t" \
"orr %0,%0,%1\n\t" \
"mcr p15,0,%0,c1,c0,0" \
:"+r"(tmp) \
:"r"(bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t tmp;
__asm volatile( \
"mrc p15,0,%0,c1,c0,0\n\t" \
"bic %0,%0,%1\n\t" \
"mcr p15,0,%0,c1,c0,0" \
:"+r"(tmp) \
:"r"(bit) \
:"memory");
}
#endif #endif
#if defined(__CC_ARM)|(__GNUC__)
/** /**
* enable I-Cache * enable I-Cache
* *
@ -143,7 +177,6 @@ rt_base_t rt_hw_cpu_dcache_status()
{ {
return (cp15_rd() & DCACHE_MASK); return (cp15_rd() & DCACHE_MASK);
} }
#endif
/** /**
* shutdown CPU * shutdown CPU

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@ -145,7 +145,7 @@ static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr) void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
{ {
volatile rt_uint32_t *pTT; volatile rt_uint32_t *pTT;
volatile int i,nSec; int i,nSec;
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20); pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
nSec=(vaddrEnd>>20)-(vaddrStart>>20); nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0;i<=nSec;i++) for(i=0;i<=nSec;i++)