diff --git a/bsp/lm3s/board.h b/bsp/lm3s/board.h index 3c796846d4..9a2f330aa0 100644 --- a/bsp/lm3s/board.h +++ b/bsp/lm3s/board.h @@ -15,6 +15,11 @@ #ifndef __BOARD_H__ #define __BOARD_H__ +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#define LM3S_SRAM_SIZE 64 +#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) + void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); void rt_hw_board_init(void); diff --git a/bsp/lm3s/startup.c b/bsp/lm3s/startup.c index cf2d45ac03..412b74c738 100644 --- a/bsp/lm3s/startup.c +++ b/bsp/lm3s/startup.c @@ -19,9 +19,9 @@ /** * @addtogroup LM3S - */ + */ -extern void rt_hw_serial_init(void); +extern void rt_hw_serial_init(void); /*@{*/ #ifdef RT_USING_FINSH @@ -82,12 +82,12 @@ void rtthread_startup(void) #ifdef RT_USING_HEAP #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20010000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)0x20010000); + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); #else /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)0x20010000); + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); #endif #endif diff --git a/libcpu/arm/lm3s/start_gcc.s b/libcpu/arm/lm3s/start_gcc.s index 81bca5b719..1d1b8e558d 100644 --- a/libcpu/arm/lm3s/start_gcc.s +++ b/libcpu/arm/lm3s/start_gcc.s @@ -1,32 +1,3 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 - * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure external SRAM mounted on STM3210E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ .section .bss.init .equ Stack_Size, 0x00000200 .space Stack_Size @@ -52,8 +23,6 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss -// .equ Initial_spTop, 0x20000200 -.equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely @@ -131,17 +100,17 @@ Infinite_Loop: g_pfnVectors: .word Initial_spTop .word Reset_Handler - .word Default_Handler //NMI_Handler + .word Default_Handler //NMI_Handler .word rt_hw_hard_fault - .word Default_Handler //MemManage_Handler - .word Default_Handler //BusFault_Handler - .word Default_Handler //UsageFault_Handler + .word Default_Handler //MemManage_Handler + .word Default_Handler //BusFault_Handler + .word Default_Handler //UsageFault_Handler .word 0 .word 0 .word 0 .word 0 - .word Default_Handler //SVC_Handler - .word Default_Handler //DebugMon_Handler + .word Default_Handler //SVC_Handler + .word Default_Handler //DebugMon_Handler .word 0 .word rt_hw_pend_sv .word rt_hw_timer_handler