update libcpu/arm/cortex-m3: restore MSP.
This commit is contained in:
aozima
parent
f9e673354a
commit
4d421cad73
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@ -10,161 +10,170 @@
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* Change Logs:
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* Date Author Notes
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* 2009-10-11 Bernard First version
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* 2010-12-29 onelife Modify for EFM32
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* 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
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* 2011-07-12 onelife Add interrupt context check function
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* 2010-12-29 onelife Modify for EFM32
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* 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
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* 2011-07-12 onelife Add interrupt context check function
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* 2013-06-18 aozima add restore MSP feature.
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*/
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.cpu cortex-m3
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.cpu cortex-m3
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.equ ICSR, 0xE000ED04 /* interrupt control state register */
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.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
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.equ SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
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.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
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.equ ICSR, 0xE000ED04 /* interrupt control state register */
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.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
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.equ SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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MRS R0, PRIMASK
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CPSID I
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BX LR
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MRS R0, PRIMASK
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CPSID I
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BX LR
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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MSR PRIMASK, R0
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BX LR
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MSR PRIMASK, R0
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BX LR
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* R0 --> from
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* R1 --> to
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*/
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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/* set rt_thread_switch_interrupt_flag to 1 */
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LDR R2, =rt_thread_switch_interrupt_flag
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOV R3, #1
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STR R3, [R2]
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/* set rt_thread_switch_interrupt_flag to 1 */
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LDR R2, =rt_thread_switch_interrupt_flag
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOV R3, #1
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STR R3, [R2]
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LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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STR R0, [R2]
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LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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STR R0, [R2]
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_reswitch:
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LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR R1, [R2]
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LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR R1, [R2]
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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STR R1, [R0]
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BX LR
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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STR R1, [R0]
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BX LR
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/* R0 --> swith from thread stack
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* R1 --> swith to thread stack
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* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
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*/
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.global PendSV_Handler
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.type PendSV_Handler, %function
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.global PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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/* disable interrupt to protect context switch */
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MRS R2, PRIMASK
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CPSID I
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/* disable interrupt to protect context switch */
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MRS R2, PRIMASK
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CPSID I
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/* get rt_thread_switch_interrupt_flag */
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LDR R0, =rt_thread_switch_interrupt_flag
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LDR R1, [R0]
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CBZ R1, pendsv_exit /* pendsv aLReady handled */
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/* get rt_thread_switch_interrupt_flag */
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LDR R0, =rt_thread_switch_interrupt_flag
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LDR R1, [R0]
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CBZ R1, pendsv_exit /* pendsv aLReady handled */
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOV R1, #0
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STR R1, [R0]
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOV R1, #0
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STR R1, [R0]
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LDR R0, =rt_interrupt_from_thread
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LDR R1, [R0]
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CBZ R1, swtich_to_thread /* skip register save at the first time */
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LDR R0, =rt_interrupt_from_thread
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LDR R1, [R0]
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CBZ R1, swtich_to_thread /* skip register save at the first time */
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MRS R1, PSP /* get from thread stack pointer */
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STMFD R1!, {R4 - R11} /* push R4 - R11 register */
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LDR R0, [R0]
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STR R1, [R0] /* update from thread stack pointer */
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MRS R1, PSP /* get from thread stack pointer */
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STMFD R1!, {R4 - R11} /* push R4 - R11 register */
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LDR R0, [R0]
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STR R1, [R0] /* update from thread stack pointer */
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swtich_to_thread:
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LDR R1, =rt_interrupt_to_thread
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LDR R1, [R1]
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LDR R1, [R1] /* load thread stack pointer */
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LDR R1, =rt_interrupt_to_thread
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LDR R1, [R1]
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LDR R1, [R1] /* load thread stack pointer */
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LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
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MSR PSP, R1 /* update stack pointer */
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LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
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MSR PSP, R1 /* update stack pointer */
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pendsv_exit:
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/* restore interrupt */
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MSR PRIMASK, R2
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/* restore interrupt */
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MSR PRIMASK, R2
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ORR LR, LR, #0x04
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BX LR
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ORR LR, LR, #0x04
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BX LR
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* R0 --> to
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*/
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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rt_hw_context_switch_to:
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LDR R1, =rt_interrupt_to_thread
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STR R0, [R1]
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LDR R1, =rt_interrupt_to_thread
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STR R0, [R1]
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/* set from thread to 0 */
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LDR R1, =rt_interrupt_from_thread
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MOV R0, #0
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STR R0, [R1]
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/* set from thread to 0 */
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LDR R1, =rt_interrupt_from_thread
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MOV R0, #0
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STR R0, [R1]
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/* set interrupt flag to 1 */
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LDR R1, =rt_thread_switch_interrupt_flag
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MOV R0, #1
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STR R0, [R1]
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/* set interrupt flag to 1 */
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LDR R1, =rt_thread_switch_interrupt_flag
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MOV R0, #1
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STR R0, [R1]
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/* set the PendSV exception priority */
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LDR R0, =SHPR3
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LDR R1, =PENDSV_PRI_LOWEST
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LDR.W R2, [R0,#0] /* read */
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ORR R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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/* set the PendSV exception priority */
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LDR R0, =SHPR3
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LDR R1, =PENDSV_PRI_LOWEST
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LDR.W R2, [R0,#0] /* read */
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ORR R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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STR R1, [R0]
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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STR R1, [R0]
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CPSIE I /* enable interrupts at processor level */
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/* restore MSP */
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LDR r0, =SCB_VTOR
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LDR r0, [r0]
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LDR r0, [r0]
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NOP
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MSR msp, r0
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/* never reach here! */
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CPSIE I /* enable interrupts at processor level */
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/* never reach here! */
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/* compatible with old version */
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.global rt_hw_interrupt_thread_switch
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.type rt_hw_interrupt_thread_switch, %function
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.global rt_hw_interrupt_thread_switch
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.type rt_hw_interrupt_thread_switch, %function
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rt_hw_interrupt_thread_switch:
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BX LR
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NOP
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BX LR
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NOP
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.global HardFault_Handler
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.type HardFault_Handler, %function
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.global HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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/* get current context */
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MRS R0, PSP /* get fault thread stack pointer */
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@ -179,8 +188,8 @@ HardFault_Handler:
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* rt_uint32_t rt_hw_interrupt_check(void);
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* R0 --> state
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*/
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.global rt_hw_interrupt_check
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.type rt_hw_interrupt_check, %function
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.global rt_hw_interrupt_check
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.type rt_hw_interrupt_check, %function
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rt_hw_interrupt_check:
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MRS R0, IPSR
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BX LR
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MRS R0, IPSR
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BX LR
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@ -11,6 +11,7 @@
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2009-09-27 Bernard add protect when contex switch occurs
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; * 2013-06-18 aozima add restore MSP feature.
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; */
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;/**
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@ -18,6 +19,7 @@
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; */
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;/*@{*/
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SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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@ -151,6 +153,13 @@ rt_hw_context_switch_to:
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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; restore MSP
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LDR r0, =SCB_VTOR
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LDR r0, [r0]
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LDR r0, [r0]
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NOP
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MSR msp, r0
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CPSIE I ; enable interrupts at processor level
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; never reach here!
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@ -10,6 +10,7 @@
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2013-06-18 aozima add restore MSP feature.
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; */
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;/**
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@ -17,6 +18,7 @@
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; */
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;/*@{*/
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SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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@ -158,6 +160,13 @@ rt_hw_context_switch_to PROC
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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; restore MSP
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LDR r0, =SCB_VTOR
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LDR r0, [r0]
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LDR r0, [r0]
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NOP
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MSR msp, r0
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; enable interrupts at processor level
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CPSIE I
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