libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

[GD32_ARM] Fix bugs in drv_adc when enable multiple channel.

This commit is contained in:
Jiangrunnan 2024-01-31 21:32:15 +08:00 committed by Meco Man
parent 49c8ff2531
commit 4cbc1a41f6
1 changed files with 41 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
bsp/gd32/arm/libraries/gd32_drivers/drv_adc.c
View File

@ -122,23 +122,20 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
{
gd32_adc_gpio_init(adc->adc_clk, adc->adc_pins[channel]);
adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1);
adc_data_alignment_config(adc_periph, ADC_DATAALIGN_RIGHT);
#if defined SOC_SERIES_GD32F4xx
adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_EXTI_11);
adc_channel_length_config(adc_periph, ADC_ROUTINE_CHANNEL, 1);
adc_external_trigger_source_config(adc_periph, ADC_ROUTINE_CHANNEL, ADC_EXTTRIG_ROUTINE_EXTI_11);
adc_external_trigger_config(adc_periph, ADC_ROUTINE_CHANNEL, ENABLE);
#else
adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1);
adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
#endif
adc_external_trigger_config(adc_periph, ADC_REGULAR_CHANNEL, ENABLE);
#if defined SOC_SERIES_GD32F4xx
adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_480);
#else
adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5);
#endif
adc_enable(adc_periph);
rt_hw_us_delay(1);
/* ADC calibration and reset calibration */
adc_calibration_enable(adc_periph);
@ -147,7 +144,7 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
{
adc_disable(adc_periph);
}
return 0;
return RT_EOK;
}
/**
@ -159,6 +156,7 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
uint32_t adc_periph;
uint32_t timeout = 0;
struct gd32_adc *adc = (struct gd32_adc *)(device->parent.user_data);
if (!value)
@ -168,15 +166,38 @@ static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t chann
}
adc_periph = (uint32_t)(adc->adc_periph);
adc_flag_clear(adc_periph, ADC_FLAG_EOC | ADC_FLAG_STRC);
#if defined SOC_SERIES_GD32F4xx
adc_routine_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_480);
adc_software_trigger_enable(adc_periph, ADC_ROUTINE_CHANNEL);
#else
adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5);
adc_software_trigger_enable(adc_periph, ADC_REGULAR_CHANNEL);
#endif
while(!adc_flag_get(adc_periph, ADC_FLAG_EOC)){};
// clear flag
adc_flag_clear(adc_periph, ADC_FLAG_EOC);
while (!adc_flag_get(adc_periph, ADC_FLAG_EOC))
{
if(timeout >= 100)
{
adc_flag_clear(adc_periph, ADC_FLAG_EOC | ADC_FLAG_STRC);
LOG_E("Convert Timeout");
return -RT_ETIMEOUT;
}
else
{
timeout++;
rt_hw_us_delay(1);
}
}
#if defined SOC_SERIES_GD32F4xx
*value = adc_routine_data_read(adc_periph);
#else
*value = adc_regular_data_read(adc_periph);
#endif
return 0;
adc_flag_clear(adc_periph, ADC_FLAG_EOC | ADC_FLAG_STRC);
return RT_EOK;
}
static struct rt_adc_ops gd32_adc_ops = {