[bsp][bluetrum] add adc and rtc support
This commit is contained in:
greedyhao
parent
e210bc7cb6
commit
4b9e58cb1b
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@ -108,14 +108,6 @@ CONFIG_FINSH_ARG_MAX=10
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# Device virtual file system
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#
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# CONFIG_RT_USING_DFS is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
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#
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# Device Drivers
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@ -383,6 +375,7 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
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# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
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# CONFIG_PKG_USING_QFPLIB_M3 is not set
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# CONFIG_PKG_USING_LPM is not set
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#
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# peripheral libraries and drivers
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@ -516,6 +509,8 @@ CONFIG_BSP_USING_UART0=y
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# CONFIG_BSP_USING_PWM is not set
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# CONFIG_BSP_USING_WDT is not set
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# CONFIG_BSP_USING_TIM is not set
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# CONFIG_BSP_USING_ONCHIP_RTC is not set
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# CONFIG_BSP_USING_ADC is not set
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#
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# Board extended module Drivers
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@ -162,6 +162,22 @@ menu "On-chip Peripheral Drivers"
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default n
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endif
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config BSP_USING_ONCHIP_RTC
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bool "Enable RTC"
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select RT_USING_RTC
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select RT_USING_LIBC
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default n
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menuconfig BSP_USING_ADC
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bool "Enable ADC"
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default n
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select RT_USING_ADC
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if BSP_USING_ADC
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config BSP_USING_ADC0
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bool "Enable ADC0"
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default n
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endif
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endmenu
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menu "Board extended module Drivers"
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@ -40,16 +40,6 @@ SECTIONS
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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PROVIDE(__ctors_start__ = .);
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KEEP (*(SORT(.init_array.*)))
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@ -59,8 +49,6 @@ SECTIONS
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. = ALIGN(4);
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*components*drivers**.o (.text*)
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*components.o (.text*)
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*idle.o (.text*)
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*object.o (.text*)
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} > ram1 AT > flash
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.comm __comm_vma : {
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@ -69,7 +57,9 @@ SECTIONS
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EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o
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*romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o
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*letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o
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*trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)
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*trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o
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*fixdfsi.o *addsf3.o *divsf3.o *eqsf2.o *gesf2.o *float*.o
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*lesf2.o *mulsf3.o *subsf3.o *fixsfsi.o *fixunssfsi.o) *(.text)
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*finsh*shell.o (.text*)
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*(.text.unlikely)
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*(.text.startup)
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@ -108,6 +98,17 @@ SECTIONS
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} > heap
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.flash : {
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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*(.text*)
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*(.rodata*)
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*(.srodata*)
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@ -28,6 +28,12 @@ if GetDepend('RT_USING_HWTIMER'):
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if GetDepend('RT_USING_PWM'):
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src += ['drv_pwm.c']
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if GetDepend('RT_USING_RTC'):
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src += ['drv_rtc.c']
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if GetDepend('RT_USING_ADC'):
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src += ['drv_adc.c']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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objs = [group]
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-02-01 greedyhao first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC0
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#ifndef ADC0_CONFIG
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#define ADC0_CONFIG \
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{ \
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.adc_dat_handle = (hal_sfr_t)&SADCDAT0, \
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.name = "adc0", \
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}
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#endif /* ADC0_CONFIG */
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#endif /* BSP_USING_ADC0 */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,163 @@
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/*
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-02-01 greedyhao first version
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*/
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#include "drv_gpio.h"
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#ifdef BSP_USING_ADC0
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#include "adc_config.h"
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// #define DRV_DEBUG
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#define LOG_TAG "drv.adc"
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#include <drv_log.h>
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struct ab32_adc
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{
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struct rt_adc_device ab32_adc_device;
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hal_sfr_t adc_dat_handle;
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char *name;
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};
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enum
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{
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#ifdef BSP_USING_ADC0
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ADC0_INDEX,
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#endif
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ADC_INDEX_END
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};
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static struct ab32_adc ab32_adc_obj[] =
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{
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#ifdef BSP_USING_ADC0
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ADC0_CONFIG,
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#endif
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};
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static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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{
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RT_ASSERT(device != RT_NULL);
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hal_adc_enable(enabled);
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return RT_EOK;
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}
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static rt_uint32_t ab32_adc_get_channel(rt_uint32_t channel)
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{
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rt_uint32_t ab32_channel = 0;
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switch (channel)
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{
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case 0:
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ab32_channel = ADC_CHANNEL_0;
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break;
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case 1:
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ab32_channel = ADC_CHANNEL_1;
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break;
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case 2:
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ab32_channel = ADC_CHANNEL_2;
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break;
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case 3:
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ab32_channel = ADC_CHANNEL_3;
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break;
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case 4:
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ab32_channel = ADC_CHANNEL_4;
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break;
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case 5:
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ab32_channel = ADC_CHANNEL_5;
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break;
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case 6:
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ab32_channel = ADC_CHANNEL_6;
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break;
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case 7:
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ab32_channel = ADC_CHANNEL_7;
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break;
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case 8:
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ab32_channel = ADC_CHANNEL_8;
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break;
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case 9:
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ab32_channel = ADC_CHANNEL_9;
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break;
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case 10:
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ab32_channel = ADC_CHANNEL_10;
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break;
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case 11:
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ab32_channel = ADC_CHANNEL_11;
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break;
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case 12:
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ab32_channel = ADC_CHANNEL_12;
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break;
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case 13:
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ab32_channel = ADC_CHANNEL_13;
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break;
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case 14:
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ab32_channel = ADC_CHANNEL_14;
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break;
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case 15:
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ab32_channel = ADC_CHANNEL_15;
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break;
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}
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return ab32_channel;
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}
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static rt_err_t ab32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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hal_sfr_t ab32_adc_handler;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(value != RT_NULL);
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ab32_adc_handler = device->parent.user_data;
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hal_adc_start(ab32_adc_get_channel(channel));
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hal_adc_poll_for_conversion(1000);
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*value = ab32_adc_handler[channel];
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return RT_EOK;
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}
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static const struct rt_adc_ops _adc_ops =
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{
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.enabled = ab32_adc_enabled,
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.convert = ab32_get_adc_value,
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};
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static int ab32_adc_init(void)
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{
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int result = RT_EOK;
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int i = 0;
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if (ADC_INDEX_END == 0) {
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return result;
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}
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CLKCON0 |= BIT(28); // enable adc clock
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for (i = 0; i < sizeof(ab32_adc_obj) / sizeof(ab32_adc_obj[0]); i++) {
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if (rt_hw_adc_register(&ab32_adc_obj[i].ab32_adc_device, ab32_adc_obj[i].name, &_adc_ops, (const void *)ab32_adc_obj[i].adc_dat_handle) == RT_EOK)
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{
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LOG_D("%s init success", ab32_adc_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", ab32_adc_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(ab32_adc_init);
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#endif
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@ -0,0 +1,218 @@
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/*
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-28 greedyhao first version
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*/
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#include "board.h"
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#include <time.h>
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#ifdef BSP_USING_ONCHIP_RTC
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//#define DRV_DEBUG
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#define LOG_TAG "drv.rtc"
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#include <drv_log.h>
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static struct rt_device rtc;
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/************** HAL Start *******************/
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#define IRTC_ENTER_CRITICAL() uint32_t cpu_ie = PICCON & BIT(0); PICCONCLR = BIT(0);
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#define IRTC_EXIT_CRITICAL() PICCON |= cpu_ie
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uint8_t get_weekday(struct tm *const _tm)
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{
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uint8_t weekday;
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time_t secs = mktime(_tm);
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weekday = (secs / 86400 + 4) % 7;
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return weekday;
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}
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void irtc_write(uint32_t cmd)
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{
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RTCDAT = cmd;
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while (RTCCON & RTC_CON_TRANS_DONE);
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}
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uint8_t irtc_read(void)
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{
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RTCDAT = 0x00;
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while (RTCCON & RTC_CON_TRANS_DONE);
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return (uint8_t)RTCDAT;
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}
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void irtc_time_write(uint32_t cmd, uint32_t dat)
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{
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IRTC_ENTER_CRITICAL();
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RTCCON |= RTC_CON_CHIP_SELECT;
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irtc_write(cmd | RTC_WR);
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irtc_write((uint8_t)(dat >> 24));
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irtc_write((uint8_t)(dat >> 16));
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irtc_write((uint8_t)(dat >> 8));
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irtc_write((uint8_t)(dat >> 0));
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RTCCON &= ~RTC_CON_CHIP_SELECT;
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IRTC_EXIT_CRITICAL();
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}
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uint32_t irtc_time_read(uint32_t cmd)
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{
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uint32_t rd_val;
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IRTC_ENTER_CRITICAL();
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RTCCON |= RTC_CON_CHIP_SELECT;
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irtc_write(cmd | RTC_RD);
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*((uint8_t *)&rd_val + 3) = irtc_read();
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*((uint8_t *)&rd_val + 2) = irtc_read();
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*((uint8_t *)&rd_val + 1) = irtc_read();
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*((uint8_t *)&rd_val + 0) = irtc_read();
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RTCCON &= ~RTC_CON_CHIP_SELECT;
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IRTC_EXIT_CRITICAL();
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return rd_val;
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}
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void irtc_sfr_write(uint32_t cmd, uint8_t dat)
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{
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IRTC_ENTER_CRITICAL();
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RTCCON |= RTC_CON_CHIP_SELECT;
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irtc_write(cmd | RTC_WR);
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irtc_write(dat);
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RTCCON &= ~RTC_CON_CHIP_SELECT;
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IRTC_EXIT_CRITICAL();
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}
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uint8_t irtc_sfr_read(uint32_t cmd)
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{
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uint8_t rd_val;
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IRTC_ENTER_CRITICAL();
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RTCCON |= RTC_CON_CHIP_SELECT;
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irtc_write(cmd | RTC_RD);
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rd_val = irtc_read();
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RTCCON &= ~RTC_CON_CHIP_SELECT;
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IRTC_EXIT_CRITICAL();
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}
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void hal_rtc_init(void)
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{
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time_t sec = 0;
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struct tm tm_new = {0};
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uint8_t temp = irtc_sfr_read(RTCCON0_CMD);
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temp &= ~RTC_CON0_XOSC32K_ENABLE;
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temp |= RTC_CON0_EXTERNAL_32K;
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irtc_sfr_write(RTCCON0_CMD, temp);
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temp = irtc_sfr_read(RTCCON2_CMD);
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irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
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temp = irtc_sfr_read(RTCCON0_CMD);
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if (temp & BIT(7)) {
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temp &= ~BIT(7);
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irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
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}
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tm_new.tm_mday = 29;
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tm_new.tm_mon = 1 - 1;
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tm_new.tm_year = 2021 - 1900;
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sec = mktime(&tm_new);
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irtc_time_write(RTCCNT_CMD, sec);
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}
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/************** HAL End *******************/
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static time_t get_rtc_timestamp(void)
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{
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time_t sec = 0;
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sec = irtc_time_read(RTCCNT_CMD);
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LOG_D("get rtc time.");
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return sec;
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}
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static rt_err_t set_rtc_time_stamp(time_t time_stamp)
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{
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irtc_time_write(RTCCNT_CMD, time_stamp);
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return RT_EOK;
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}
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static void rt_rtc_init(void)
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{
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hal_rtc_init();
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}
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static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
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{
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rt_err_t result = RT_EOK;
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RT_ASSERT(dev != RT_NULL);
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switch (cmd)
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{
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case RT_DEVICE_CTRL_RTC_GET_TIME:
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*(rt_uint32_t *)args = get_rtc_timestamp();
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LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
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break;
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case RT_DEVICE_CTRL_RTC_SET_TIME:
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if (set_rtc_time_stamp(*(rt_uint32_t *)args))
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{
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result = -RT_ERROR;
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}
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LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
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break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops rtc_ops =
|
||||
{
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
rt_rtc_control
|
||||
};
|
||||
#endif
|
||||
|
||||
static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
rt_rtc_init();
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
device->ops = &rtc_ops;
|
||||
#else
|
||||
device->init = RT_NULL;
|
||||
device->open = RT_NULL;
|
||||
device->close = RT_NULL;
|
||||
device->read = RT_NULL;
|
||||
device->write = RT_NULL;
|
||||
device->control = rt_rtc_control;
|
||||
#endif
|
||||
device->type = RT_Device_Class_RTC;
|
||||
device->rx_indicate = RT_NULL;
|
||||
device->tx_complete = RT_NULL;
|
||||
device->user_data = RT_NULL;
|
||||
|
||||
/* register a character device */
|
||||
return rt_device_register(device, name, flag);
|
||||
}
|
||||
|
||||
int rt_hw_rtc_init(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
LOG_E("rtc register err code: %d", result);
|
||||
return result;
|
||||
}
|
||||
LOG_D("rtc init success");
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
|
||||
|
||||
#endif /* BSP_USING_ONCHIP_RTC */
|
||||
|
|
@ -11,7 +11,6 @@ Import('rtconfig')
|
|||
PKGNAME = "ab32vg1_hal"
|
||||
VERSION = "v1.0.0"
|
||||
DEPENDS = [""]
|
||||
#DEPENDS = ["PKG_USING_RW007"]
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Compile the configuration
|
||||
|
|
@ -35,6 +34,7 @@ DEPENDS = [""]
|
|||
#
|
||||
# LINKFLAGS: Link options
|
||||
#---------------------------------------------------------------------------------
|
||||
CWD = GetCurrentDir()
|
||||
SOURCES = Glob("./source/*.c")
|
||||
|
||||
LOCAL_CPPPATH = []
|
||||
|
|
@ -48,8 +48,8 @@ ASFLAGS = ""
|
|||
CPPDEFINES = []
|
||||
LOCAL_CPPDEFINES = []
|
||||
|
||||
LIBS = []
|
||||
LIBPATH = []
|
||||
LIBS = ['hal']
|
||||
LIBPATH = [CWD]
|
||||
|
||||
LINKFLAGS = ""
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2021, BLUETRUM Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef AB32VG1_HAL_ADC_H__
|
||||
#define AB32VG1_HAL_ADC_H__
|
||||
|
||||
#include "ab32vg1_hal_def.h"
|
||||
|
||||
/**
|
||||
* @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_0 (1u << 0)
|
||||
#define ADC_CHANNEL_1 (1u << 1)
|
||||
#define ADC_CHANNEL_2 (1u << 2)
|
||||
#define ADC_CHANNEL_3 (1u << 3)
|
||||
#define ADC_CHANNEL_4 (1u << 4)
|
||||
#define ADC_CHANNEL_5 (1u << 5)
|
||||
#define ADC_CHANNEL_6 (1u << 6)
|
||||
#define ADC_CHANNEL_7 (1u << 7)
|
||||
#define ADC_CHANNEL_8 (1u << 8)
|
||||
#define ADC_CHANNEL_9 (1u << 9)
|
||||
#define ADC_CHANNEL_10 (1u << 10)
|
||||
#define ADC_CHANNEL_11 (1u << 11)
|
||||
#define ADC_CHANNEL_12 (1u << 12)
|
||||
#define ADC_CHANNEL_13 (1u << 13)
|
||||
#define ADC_CHANNEL_14 (1u << 14)
|
||||
#define ADC_CHANNEL_15 (1u << 15)
|
||||
/**
|
||||
* @}
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ADC
|
||||
*
|
||||
* @param enable
|
||||
*/
|
||||
void hal_adc_enable(uint8_t enable);
|
||||
|
||||
/**
|
||||
* @brief Starts conversion of the channels
|
||||
*
|
||||
* @param channel @ref ADC_channels
|
||||
*/
|
||||
void hal_adc_start(uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Poll for conversion complete
|
||||
*
|
||||
* @param timeout Timeout value in millisecond
|
||||
* @return hal_error_t
|
||||
*/
|
||||
hal_error_t hal_adc_poll_for_conversion(uint32_t timeout);
|
||||
|
||||
#endif
|
||||
|
|
@ -15,6 +15,8 @@
|
|||
// #define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLE
|
||||
#define HAL_ADC_MODULE_ENABLE
|
||||
|
||||
/* Includes */
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
|
@ -45,6 +47,14 @@
|
|||
#include "ab32vg1_hal_tim.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLE
|
||||
#include "ab32vg1_hal_rtc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLE
|
||||
#include "ab32vg1_hal_adc.h"
|
||||
#endif
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2020, BLUETRUM Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef AB32VG1_HAL_RTC_H__
|
||||
#define AB32VG1_HAL_RTC_H__
|
||||
|
||||
#define RTC_BASE ((hal_sfr_t)&RTCCON)
|
||||
|
||||
enum
|
||||
{
|
||||
RTCxCON,
|
||||
RTCxDAT,
|
||||
RTCxCPND = 3,
|
||||
};
|
||||
|
||||
// RTCCON
|
||||
#define RTC_CON_VUSB_OLINE (0x1u << 20) /*!< VUSB online state */
|
||||
#define RTC_CON_WK_PIN_STATE (0x1u << 19) /*!< RTC wakeup pin state */
|
||||
#define RTC_CON_1S_PEND (0x1u << 18) /*!< RTC 1s pending */
|
||||
#define RTC_CON_ALM_PEND (0x1u << 17) /*!< RTC alarm pending */
|
||||
#define RTC_CON_TRANS_DONE (0x1u << 16) /*!< RTC trans done */
|
||||
#define RTC_CON_ALM_WK_ENABLE (0x1u << 8) /*!< RTC alarm wakeup enable */
|
||||
#define RTC_CON_1S_WK_ENABLE (0x1u << 7) /*!< RTC 1s wakeup enable */
|
||||
#define RTC_CON_VUSB_RST_ENABLE (0x1u << 6) /*!< VUSB insert reset system enable */
|
||||
#define RTC_CON_WK_RST_ENABLE (0x1u << 5) /*!< RTC wakeup power down mode reset \
|
||||
system enable */
|
||||
#define RTC_CON_ALM_INTERRUPT (0x1u << 4) /*!< RTC alarm interrupt enable */
|
||||
#define RTC_CON_1S_INTERRUPT (0x1u << 3) /*!< RTC 1s interrupt enable */
|
||||
#define RTC_CON_BAUD_SELECT (0x3u << 1) /*!< Increase clock selection */
|
||||
#define RTC_CON_CHIP_SELECT (0x1u << 0) /*!< RTC chip select */
|
||||
|
||||
// RTCCON0
|
||||
#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */
|
||||
#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */
|
||||
#define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */
|
||||
#define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */
|
||||
#define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */
|
||||
#define RTC_CON0_LVD_ENABLE (0x01u << 2) /*!< LVD enbale */
|
||||
#define RTC_CON0_XOSC32K_ENABLE (0x01u << 1) /*!< XOSC32K enable */
|
||||
#define RTC_CON0_RCOSC_ENABLE (0x01u << 0) /*!< RCOSC enable */
|
||||
|
||||
// RTCCON2
|
||||
#define RTC_CON2_32K_SELECT (0x01u << 7) /*!< 32K osc select */
|
||||
|
||||
#endif
|
||||
|
|
@ -14,23 +14,23 @@
|
|||
/*!< Interrupt Number Definition */
|
||||
typedef enum
|
||||
{
|
||||
IRQ_SW_VECTOR = 2,
|
||||
IRQ_TMR0_VECTOR = 3,
|
||||
IRQ_TMR1_VECTOR = 4,
|
||||
IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */
|
||||
IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */
|
||||
IRQ_USB_VECTOR = 7,
|
||||
IRQ_SD_VECTOR = 8,
|
||||
IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */
|
||||
IRQ_SDADC_VECTOR = 10,
|
||||
IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */
|
||||
IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */
|
||||
IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */
|
||||
IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */
|
||||
IRQ_HSUART_VECTOR = 15,
|
||||
IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */
|
||||
IRQ_I2S_VECTOR = 17,
|
||||
IRQ_TOTAL_NUM = 23,
|
||||
IRQ_SW_VECTOR = 2,
|
||||
IRQ_TMR0_VECTOR = 3,
|
||||
IRQ_TMR1_VECTOR = 4,
|
||||
IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */
|
||||
IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */
|
||||
IRQ_USB_VECTOR = 7,
|
||||
IRQ_SD_VECTOR = 8,
|
||||
IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */
|
||||
IRQ_SDADC_VECTOR = 10,
|
||||
IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */
|
||||
IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */
|
||||
IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */
|
||||
IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */
|
||||
IRQ_HSUART_VECTOR = 15,
|
||||
IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */
|
||||
IRQ_I2S_VECTOR = 17,
|
||||
IRQ_TOTAL_NUM = 23,
|
||||
} irq_type;
|
||||
#endif // __ASSEMBLER__
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue