Add SDIO stack support, current only support SDSC and SDHC card
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1771 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
luohui2320@gmail.com
parent
3ac0b7b966
commit
49ddb7e0f5
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@ -8,8 +8,8 @@ src_drv = ['console.c']
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if GetDepend('RT_USING_LED'):
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src_drv += ['led.c']
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#if GetDepend('RT_USING_DFS'):
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#src_drv += ['sdcard.c']
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if GetDepend('RT_USING_MMCSD'):
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src_drv += ['at91_mci.c']
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if GetDepend('RT_USING_LWIP'):
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src_drv += ['macb.c']
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@ -36,6 +36,11 @@
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#include <devfs.h>
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#endif
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#ifdef RT_USING_MMCSD
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#include <mmcsd_core.h>
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#include "at91_mci.h"
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#endif
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#ifdef RT_USING_LWIP
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#include <netif/ethernetif.h>
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#include <arch/sys_arch_init.h>
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@ -101,6 +106,19 @@ void rt_init_thread_entry(void* parameter)
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}
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#endif
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#ifdef RT_USING_MMCSD
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rt_mmcsd_core_init();
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rt_mmcsd_blk_init();
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at91_mci_init();
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rt_thread_delay(RT_TICK_PER_SECOND*2);
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/* mount sd card fat partition 1 as root directory */
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if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
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{
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rt_kprintf("File System initialized!\n");
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}
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else
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rt_kprintf("File System initialzation failed!\n");
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#endif
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}
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#endif
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@ -109,6 +127,8 @@ void rt_init_thread_entry(void* parameter)
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/* register ethernetif device */
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eth_system_device_init();
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rt_hw_macb_init();
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/* re-init device driver */
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//rt_device_init_all();
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/* init lwip system */
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lwip_sys_init();
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rt_kprintf("TCP/IP initialized!\n");
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@ -0,0 +1,891 @@
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/*
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* File : at91_mci.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-07-25 weety first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <mmcsd_core.h>
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#include <at91sam926x.h>
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#include "at91_mci.h"
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#define USE_SLOT_B
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//#define RT_MCI_DBG
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#ifdef RT_MCI_DBG
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#define mci_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
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#else
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#define mci_dbg(fmt, ...)
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#endif
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#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
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| AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
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| AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
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#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg))
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#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg))
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#define REQ_ST_INIT (1U << 0)
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#define REQ_ST_CMD (1U << 1)
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#define REQ_ST_STOP (1U << 2)
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struct at91_mci {
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct rt_timer timer;
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//struct rt_semaphore sem_ack;
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rt_uint32_t *buf;
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rt_uint32_t current_status;
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};
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static struct at91_mci *at_mci;
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/*
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* Reset the controller and restore most of the state
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*/
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static void at91_reset_host()
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{
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rt_uint32_t mr;
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rt_uint32_t sdcr;
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rt_uint32_t dtor;
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rt_uint32_t imr;
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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imr = at91_mci_read(AT91_MCI_IMR);
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at91_mci_write(AT91_MCI_IDR, 0xffffffff);
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/* save current state */
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mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;
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sdcr = at91_mci_read(AT91_MCI_SDCR);
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dtor = at91_mci_read(AT91_MCI_DTOR);
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/* reset the controller */
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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/* restore state */
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
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at91_mci_write(AT91_MCI_MR, mr);
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at91_mci_write(AT91_MCI_SDCR, sdcr);
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at91_mci_write(AT91_MCI_DTOR, dtor);
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at91_mci_write(AT91_MCI_IER, imr);
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/* make sure sdio interrupts will fire */
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at91_mci_read(AT91_MCI_SR);
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rt_hw_interrupt_enable(level);
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}
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/*
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* Enable the controller
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*/
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static void at91_mci_enable()
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{
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rt_uint32_t mr;
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
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at91_mci_write(AT91_MCI_IDR, 0xffffffff);
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at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
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mr = AT91_MCI_PDCMODE | 0x34a;
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mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
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at91_mci_write(AT91_MCI_MR, mr);
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/* use Slot A or B (only one at same time) */
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at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */
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}
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/*
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* Disable the controller
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*/
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static void at91_mci_disable()
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{
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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}
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static void at91_timeout_timer(void *data)
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{
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struct at91_mci *mci;
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mci = (struct at91_mci *)data;
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if (mci->req)
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{
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rt_kprintf("Timeout waiting end of packet\n");
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if (mci->current_status == REQ_ST_CMD)
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{
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if (mci->req->cmd && mci->req->data)
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{
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mci->req->data->err = -RT_ETIMEOUT;
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}
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else
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{
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if (mci->req->cmd)
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mci->req->cmd->err = -RT_ETIMEOUT;
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}
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}
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else if (mci->current_status == REQ_ST_STOP)
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{
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mci->req->stop->err = -RT_ETIMEOUT;
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}
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at91_reset_host();
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mmcsd_req_complete(mci->host);
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}
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}
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/*
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* Prepare a dma read
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*/
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static void at91_mci_init_dma_read(struct at91_mci *mci)
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{
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rt_uint8_t i;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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rt_uint32_t length;
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mci_dbg("pre dma read\n");
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cmd = mci->cmd;
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if (!cmd)
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{
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mci_dbg("no command\n");
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return;
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}
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data = cmd->data;
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if (!data)
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{
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mci_dbg("no data\n");
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return;
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}
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for (i = 0; i < 1; i++)
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{
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/* Check to see if this needs filling */
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if (i == 0)
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{
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if (at91_mci_read(AT91_PDC_RCR) != 0)
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{
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mci_dbg("Transfer active in current\n");
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continue;
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}
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}
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else {
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if (at91_mci_read(AT91_PDC_RNCR) != 0)
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{
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mci_dbg("Transfer active in next\n");
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continue;
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}
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}
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length = data->blksize * data->blks;
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mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
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if (i == 0)
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{
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at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf));
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at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
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}
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else
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{
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at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf));
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at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
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}
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}
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mci_dbg("pre dma read done\n");
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}
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/*
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* Send a command
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*/
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static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
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{
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rt_uint32_t cmdr, mr;
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rt_uint32_t block_length;
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struct rt_mmcsd_data *data = cmd->data;
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struct rt_mmcsd_host *host = mci->host;
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rt_uint32_t blocks;
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rt_uint32_t ier = 0;
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rt_uint32_t length;
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mci->cmd = cmd;
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/* Needed for leaving busy state before CMD1 */
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if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1))
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{
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mci_dbg("Clearing timeout\n");
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at91_mci_write(AT91_MCI_ARGR, 0);
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at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
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while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
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{
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/* spin */
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mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
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}
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}
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cmdr = cmd->cmd_code;
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if (resp_type(cmd) == RESP_NONE)
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cmdr |= AT91_MCI_RSPTYP_NONE;
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else
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{
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/* if a response is expected then allow maximum response latancy */
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cmdr |= AT91_MCI_MAXLAT;
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/* set 136 bit response for R2, 48 bit response otherwise */
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if (resp_type(cmd) == RESP_R2)
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cmdr |= AT91_MCI_RSPTYP_136;
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else
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cmdr |= AT91_MCI_RSPTYP_48;
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}
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if (data)
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{
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block_length = data->blksize;
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blocks = data->blks;
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/* always set data start - also set direction flag for read */
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if (data->flags & DATA_DIR_READ)
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cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
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else if (data->flags & DATA_DIR_WRITE)
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cmdr |= AT91_MCI_TRCMD_START;
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if (data->flags & DATA_STREAM)
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cmdr |= AT91_MCI_TRTYP_STREAM;
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if (data->blks > 1)
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cmdr |= AT91_MCI_TRTYP_MULTIPLE;
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}
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else
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{
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block_length = 0;
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blocks = 0;
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}
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/*if (cmd->cmd_code == GO_IDLE_STATE)
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{
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cmdr |= AT91_MCI_SPCMD_INIT;
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}*/
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if (cmd->cmd_code == STOP_TRANSMISSION)
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cmdr |= AT91_MCI_TRCMD_STOP;
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if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
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cmdr |= AT91_MCI_OPDCMD;
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/*
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* Set the arguments and send the command
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*/
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mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
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cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
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if (!data)
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{
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
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at91_mci_write(AT91_PDC_RPR, 0);
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at91_mci_write(AT91_PDC_RCR, 0);
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at91_mci_write(AT91_PDC_RNPR, 0);
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at91_mci_write(AT91_PDC_RNCR, 0);
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at91_mci_write(AT91_PDC_TPR, 0);
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at91_mci_write(AT91_PDC_TCR, 0);
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at91_mci_write(AT91_PDC_TNPR, 0);
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at91_mci_write(AT91_PDC_TNCR, 0);
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ier = AT91_MCI_CMDRDY;
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}
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else
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{
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/* zero block length and PDC mode */
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mr = at91_mci_read(AT91_MCI_MR) & 0x5fff;
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mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0;
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mr |= (block_length << 16);
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mr |= AT91_MCI_PDCMODE;
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at91_mci_write(AT91_MCI_MR, mr);
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at91_mci_write(AT91_MCI_BLKR,
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AT91_MCI_BLKR_BCNT(blocks) |
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AT91_MCI_BLKR_BLKLEN(block_length));
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/*
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* Disable the PDC controller
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*/
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
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if (cmdr & AT91_MCI_TRCMD_START)
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{
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if (cmdr & AT91_MCI_TRDIR)
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{
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/*
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* Handle a read
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*/
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at91_mci_init_dma_read(mci);
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ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
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}
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else
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{
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/*
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* Handle a write
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*/
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length = block_length * blocks;
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/*
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* at91mci MCI1 rev2xx Data Write Operation and
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* number of bytes erratum
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*/
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if (length < 12)
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{
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length = 12;
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mci->buf = rt_malloc(length);
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if (!mci->buf)
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{
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rt_kprintf("rt alloc tx buffer failed\n");
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cmd->err = -RT_ENOMEM;
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mmcsd_req_complete(mci->host);
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return;
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}
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rt_memset(mci->buf, 0, 12);
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rt_memcpy(mci->buf, data->buf, block_length * blocks);
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at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
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at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
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length : length / 4);
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}
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else
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{
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at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
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at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
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length : length / 4);
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}
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mci_dbg("Transmitting %d bytes\n", length);
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ier = AT91_MCI_CMDRDY;
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}
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}
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}
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/*
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* Send the command and then enable the PDC - not the other way round as
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* the data sheet says
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*/
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at91_mci_write(AT91_MCI_ARGR, cmd->arg);
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at91_mci_write(AT91_MCI_CMDR, cmdr);
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if (cmdr & AT91_MCI_TRCMD_START)
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{
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if (cmdr & AT91_MCI_TRDIR)
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
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}
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/* Enable selected interrupts */
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at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier);
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}
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/*
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* Process the next step in the request
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*/
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static void at91_mci_process_next(struct at91_mci *mci)
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{
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if (mci->current_status == REQ_ST_INIT)
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{
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mci->current_status = REQ_ST_CMD;
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at91_mci_send_command(mci, mci->req->cmd);
|
||||
}
|
||||
else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
|
||||
{
|
||||
mci->current_status = REQ_ST_STOP;
|
||||
at91_mci_send_command(mci, mci->req->stop);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_timer_stop(&mci->timer);
|
||||
/* the mci controller hangs after some transfers,
|
||||
* and the workaround is to reset it after each transfer.
|
||||
*/
|
||||
at91_reset_host();
|
||||
mmcsd_req_complete(mci->host);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle an MMC request
|
||||
*/
|
||||
static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
||||
{
|
||||
rt_uint32_t timeout = RT_TICK_PER_SECOND;
|
||||
struct at91_mci *mci = host->private_data;
|
||||
mci->req = req;
|
||||
mci->current_status = REQ_ST_INIT;
|
||||
|
||||
rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
|
||||
rt_timer_start(&mci->timer);
|
||||
|
||||
at91_mci_process_next(mci);
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle transmitted data
|
||||
*/
|
||||
static void at91_mci_handle_transmitted(struct at91_mci *mci)
|
||||
{
|
||||
struct rt_mmcsd_cmd *cmd;
|
||||
struct rt_mmcsd_data *data;
|
||||
|
||||
mci_dbg("Handling the transmit\n");
|
||||
|
||||
/* Disable the transfer */
|
||||
at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
|
||||
|
||||
/* Now wait for cmd ready */
|
||||
at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
|
||||
|
||||
cmd = mci->cmd;
|
||||
if (!cmd) return;
|
||||
|
||||
data = cmd->data;
|
||||
if (!data) return;
|
||||
|
||||
if (data->blks > 1)
|
||||
{
|
||||
mci_dbg("multiple write : wait for BLKE...\n");
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE);
|
||||
} else
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Handle after a dma read
|
||||
*/
|
||||
static void at91_mci_post_dma_read(struct at91_mci *mci)
|
||||
{
|
||||
struct rt_mmcsd_cmd *cmd;
|
||||
struct rt_mmcsd_data *data;
|
||||
|
||||
mci_dbg("post dma read\n");
|
||||
|
||||
cmd = mci->cmd;
|
||||
if (!cmd)
|
||||
{
|
||||
mci_dbg("no command\n");
|
||||
return;
|
||||
}
|
||||
|
||||
data = cmd->data;
|
||||
if (!data)
|
||||
{
|
||||
mci_dbg("no data\n");
|
||||
return;
|
||||
}
|
||||
|
||||
at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX);
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
|
||||
|
||||
mci_dbg("post dma read done\n");
|
||||
}
|
||||
|
||||
/*Handle after command sent ready*/
|
||||
static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
|
||||
{
|
||||
if (!mci->cmd)
|
||||
return 1;
|
||||
else if (!mci->cmd->data)
|
||||
{
|
||||
if (mci->current_status == REQ_ST_STOP)
|
||||
{
|
||||
/*After multi block write, we must wait for NOTBUSY*/
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
|
||||
}
|
||||
else return 1;
|
||||
}
|
||||
else if (mci->cmd->data->flags & DATA_DIR_WRITE)
|
||||
{
|
||||
/*After sendding multi-block-write command, start DMA transfer*/
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
|
||||
at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
|
||||
}
|
||||
|
||||
/* command not completed, have to wait */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle a command that has been completed
|
||||
*/
|
||||
static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
|
||||
{
|
||||
struct rt_mmcsd_cmd *cmd = mci->cmd;
|
||||
struct rt_mmcsd_data *data = cmd->data;
|
||||
|
||||
at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
||||
|
||||
cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
|
||||
cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
|
||||
cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
|
||||
cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
|
||||
|
||||
if (mci->buf)
|
||||
{
|
||||
//rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
|
||||
rt_free(mci->buf);
|
||||
mci->buf = RT_NULL;
|
||||
}
|
||||
|
||||
mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
|
||||
status, at91_mci_read(AT91_MCI_SR),
|
||||
cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
||||
|
||||
if (status & AT91_MCI_ERRORS)
|
||||
{
|
||||
if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
|
||||
{
|
||||
cmd->err = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE))
|
||||
{
|
||||
if (data)
|
||||
{
|
||||
if (status & AT91_MCI_DTOE)
|
||||
data->err = -RT_ETIMEOUT;
|
||||
else if (status & AT91_MCI_DCRCE)
|
||||
data->err = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (status & AT91_MCI_RTOE)
|
||||
cmd->err = -RT_ETIMEOUT;
|
||||
else if (status & AT91_MCI_RCRCE)
|
||||
cmd->err = -RT_ERROR;
|
||||
else
|
||||
cmd->err = -RT_ERROR;
|
||||
}
|
||||
|
||||
rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
|
||||
cmd->err, data ? data->err : 0,
|
||||
cmd->cmd_code);
|
||||
}
|
||||
}
|
||||
else
|
||||
cmd->err = 0;
|
||||
|
||||
at91_mci_process_next(mci);
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle an interrupt
|
||||
*/
|
||||
static void at91_mci_irq(int irq)
|
||||
{
|
||||
rt_int32_t completed = 0;
|
||||
rt_uint32_t int_status, int_mask;
|
||||
|
||||
int_status = at91_mci_read(AT91_MCI_SR);
|
||||
int_mask = at91_mci_read(AT91_MCI_IMR);
|
||||
|
||||
mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
|
||||
int_status & int_mask);
|
||||
|
||||
int_status = int_status & int_mask;
|
||||
|
||||
if (int_status & AT91_MCI_ERRORS)
|
||||
{
|
||||
completed = 1;
|
||||
|
||||
if (int_status & AT91_MCI_UNRE)
|
||||
mci_dbg("MMC: Underrun error\n");
|
||||
if (int_status & AT91_MCI_OVRE)
|
||||
mci_dbg("MMC: Overrun error\n");
|
||||
if (int_status & AT91_MCI_DTOE)
|
||||
mci_dbg("MMC: Data timeout\n");
|
||||
if (int_status & AT91_MCI_DCRCE)
|
||||
mci_dbg("MMC: CRC error in data\n");
|
||||
if (int_status & AT91_MCI_RTOE)
|
||||
mci_dbg("MMC: Response timeout\n");
|
||||
if (int_status & AT91_MCI_RENDE)
|
||||
mci_dbg("MMC: Response end bit error\n");
|
||||
if (int_status & AT91_MCI_RCRCE)
|
||||
mci_dbg("MMC: Response CRC error\n");
|
||||
if (int_status & AT91_MCI_RDIRE)
|
||||
mci_dbg("MMC: Response direction error\n");
|
||||
if (int_status & AT91_MCI_RINDE)
|
||||
mci_dbg("MMC: Response index error\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Only continue processing if no errors */
|
||||
|
||||
if (int_status & AT91_MCI_TXBUFE)
|
||||
{
|
||||
mci_dbg("TX buffer empty\n");
|
||||
at91_mci_handle_transmitted(at_mci);
|
||||
}
|
||||
|
||||
if (int_status & AT91_MCI_ENDRX)
|
||||
{
|
||||
mci_dbg("ENDRX\n");
|
||||
at91_mci_post_dma_read(at_mci);
|
||||
}
|
||||
|
||||
if (int_status & AT91_MCI_RXBUFF)
|
||||
{
|
||||
mci_dbg("RX buffer full\n");
|
||||
at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
|
||||
at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
|
||||
completed = 1;
|
||||
}
|
||||
|
||||
if (int_status & AT91_MCI_ENDTX)
|
||||
mci_dbg("Transmit has ended\n");
|
||||
|
||||
if (int_status & AT91_MCI_NOTBUSY)
|
||||
{
|
||||
mci_dbg("Card is ready\n");
|
||||
//at91_mci_update_bytes_xfered(host);
|
||||
completed = 1;
|
||||
}
|
||||
|
||||
if (int_status & AT91_MCI_DTIP)
|
||||
mci_dbg("Data transfer in progress\n");
|
||||
|
||||
if (int_status & AT91_MCI_BLKE)
|
||||
{
|
||||
mci_dbg("Block transfer has ended\n");
|
||||
if (at_mci->req->data && at_mci->req->data->blks > 1)
|
||||
{
|
||||
/* multi block write : complete multi write
|
||||
* command and send stop */
|
||||
completed = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
|
||||
}
|
||||
}
|
||||
|
||||
/*if (int_status & AT91_MCI_SDIOIRQA)
|
||||
rt_mmcsd_signal_sdio_irq(host->mmc);
|
||||
|
||||
if (int_status & AT91_MCI_SDIOIRQB)
|
||||
rt_mmcsd_signal_sdio_irq(host->mmc);*/
|
||||
|
||||
if (int_status & AT91_MCI_TXRDY)
|
||||
mci_dbg("Ready to transmit\n");
|
||||
|
||||
if (int_status & AT91_MCI_RXRDY)
|
||||
mci_dbg("Ready to receive\n");
|
||||
|
||||
if (int_status & AT91_MCI_CMDRDY)
|
||||
{
|
||||
mci_dbg("Command ready\n");
|
||||
completed = at91_mci_handle_cmdrdy(at_mci);
|
||||
}
|
||||
}
|
||||
|
||||
if (completed)
|
||||
{
|
||||
mci_dbg("Completed command\n");
|
||||
at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
||||
at91_mci_completed_command(at_mci, int_status);
|
||||
}
|
||||
else
|
||||
at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the IOCFG
|
||||
*/
|
||||
static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
||||
{
|
||||
rt_uint32_t clkdiv;
|
||||
//struct at91_mci *mci = host->private_data;
|
||||
rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
|
||||
|
||||
if (io_cfg->clock == 0)
|
||||
{
|
||||
/* Disable the MCI controller */
|
||||
at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
|
||||
clkdiv = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the MCI controller */
|
||||
at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
|
||||
|
||||
if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
|
||||
clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
|
||||
else
|
||||
clkdiv = (at91_master_clock / io_cfg->clock) / 2;
|
||||
|
||||
mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
|
||||
at91_master_clock / (2 * (clkdiv + 1)));
|
||||
}
|
||||
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
|
||||
{
|
||||
mci_dbg("MMC: Setting controller bus width to 4\n");
|
||||
at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
|
||||
}
|
||||
else
|
||||
{
|
||||
mci_dbg("MMC: Setting controller bus width to 1\n");
|
||||
at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
|
||||
}
|
||||
|
||||
/* Set the clock divider */
|
||||
at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
|
||||
|
||||
/* maybe switch power to the card */
|
||||
switch (io_cfg->power_mode)
|
||||
{
|
||||
case MMCSD_POWER_OFF:
|
||||
break;
|
||||
case MMCSD_POWER_UP:
|
||||
break;
|
||||
case MMCSD_POWER_ON:
|
||||
/*at91_mci_write(AT91_MCI_ARGR, 0);
|
||||
at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD);
|
||||
mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR));
|
||||
while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
|
||||
{
|
||||
|
||||
}
|
||||
mci_dbg("at91 mci power on\n");*/
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
static const struct rt_mmcsd_host_ops ops = {
|
||||
at91_mci_request,
|
||||
at91_mci_set_iocfg,
|
||||
RT_NULL,
|
||||
};
|
||||
|
||||
void at91_mci_detect(int irq)
|
||||
{
|
||||
rt_kprintf("mmcsd gpio detected\n");
|
||||
}
|
||||
|
||||
static void mci_gpio_init()
|
||||
{
|
||||
#ifdef USE_SLOT_B
|
||||
at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
|
||||
at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8));
|
||||
at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
|
||||
at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8));
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8));
|
||||
|
||||
at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7));
|
||||
at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7));
|
||||
at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7));
|
||||
at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7));
|
||||
#else
|
||||
at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11));
|
||||
at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
|
||||
#endif
|
||||
}
|
||||
|
||||
rt_int32_t at91_mci_init(void)
|
||||
{
|
||||
struct rt_mmcsd_host *host;
|
||||
//struct at91_mci *mci;
|
||||
|
||||
host = mmcsd_alloc_host();
|
||||
if (!host)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
at_mci = rt_malloc(sizeof(struct at91_mci));
|
||||
if (!at_mci)
|
||||
{
|
||||
rt_kprintf("alloc mci failed\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
rt_memset(at_mci, 0, sizeof(struct at91_mci));
|
||||
|
||||
host->ops = &ops;
|
||||
host->freq_min = 375000;
|
||||
host->freq_max = 25000000;
|
||||
host->valid_ocr = VDD_32_33 | VDD_33_34;
|
||||
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE;
|
||||
|
||||
at_mci->host = host;
|
||||
|
||||
mci_gpio_init();
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock
|
||||
|
||||
at91_mci_disable();
|
||||
at91_mci_enable();
|
||||
|
||||
/* instal interrupt */
|
||||
rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, RT_NULL);
|
||||
rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
|
||||
rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), at91_mci_detect, RT_NULL);
|
||||
rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7));
|
||||
|
||||
rt_timer_init(&at_mci->timer, "mci_timer",
|
||||
at91_timeout_timer,
|
||||
at_mci,
|
||||
RT_TICK_PER_SECOND,
|
||||
RT_TIMER_FLAG_PERIODIC);
|
||||
|
||||
//rt_timer_start(&mci->timer);
|
||||
|
||||
//rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
host->private_data = at_mci;
|
||||
|
||||
mmcsd_change(host);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
mmcsd_free_host(host);
|
||||
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
#include "finsh.h"
|
||||
FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
|
||||
|
||||
void mci_dump(void)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
|
||||
rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR));
|
||||
rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR));
|
||||
rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR));
|
||||
|
||||
for (i = 0; i <= 0x4c; i += 4) {
|
||||
rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
|
||||
}
|
||||
}
|
||||
|
||||
FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* File : at91_mci.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-06-09 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __AT91_MCI_H__
|
||||
#define __AT91_MCI_H__
|
||||
|
||||
#define AT91_MCI_CR 0x00 /* Control Register */
|
||||
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
|
||||
#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
|
||||
#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
|
||||
#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
|
||||
#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
|
||||
|
||||
#define AT91_MCI_MR 0x04 /* Mode Register */
|
||||
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
|
||||
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
|
||||
#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
|
||||
#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
|
||||
#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
|
||||
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
|
||||
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
|
||||
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
|
||||
|
||||
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
|
||||
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
|
||||
#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
|
||||
#define AT91_MCI_DTOMUL_1 (0 << 4)
|
||||
#define AT91_MCI_DTOMUL_16 (1 << 4)
|
||||
#define AT91_MCI_DTOMUL_128 (2 << 4)
|
||||
#define AT91_MCI_DTOMUL_256 (3 << 4)
|
||||
#define AT91_MCI_DTOMUL_1K (4 << 4)
|
||||
#define AT91_MCI_DTOMUL_4K (5 << 4)
|
||||
#define AT91_MCI_DTOMUL_64K (6 << 4)
|
||||
#define AT91_MCI_DTOMUL_1M (7 << 4)
|
||||
|
||||
#define AT91_MCI_SDCR 0x0c /* SD Card Register */
|
||||
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
|
||||
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
|
||||
|
||||
#define AT91_MCI_ARGR 0x10 /* Argument Register */
|
||||
|
||||
#define AT91_MCI_CMDR 0x14 /* Command Register */
|
||||
#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
|
||||
#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
|
||||
#define AT91_MCI_RSPTYP_NONE (0 << 6)
|
||||
#define AT91_MCI_RSPTYP_48 (1 << 6)
|
||||
#define AT91_MCI_RSPTYP_136 (2 << 6)
|
||||
#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
|
||||
#define AT91_MCI_SPCMD_NONE (0 << 8)
|
||||
#define AT91_MCI_SPCMD_INIT (1 << 8)
|
||||
#define AT91_MCI_SPCMD_SYNC (2 << 8)
|
||||
#define AT91_MCI_SPCMD_ICMD (4 << 8)
|
||||
#define AT91_MCI_SPCMD_IRESP (5 << 8)
|
||||
#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
|
||||
#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
|
||||
#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
|
||||
#define AT91_MCI_TRCMD_NONE (0 << 16)
|
||||
#define AT91_MCI_TRCMD_START (1 << 16)
|
||||
#define AT91_MCI_TRCMD_STOP (2 << 16)
|
||||
#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
|
||||
#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
|
||||
#define AT91_MCI_TRTYP_BLOCK (0 << 19)
|
||||
#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
|
||||
#define AT91_MCI_TRTYP_STREAM (2 << 19)
|
||||
|
||||
#define AT91_MCI_BLKR 0x18 /* Block Register */
|
||||
#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
|
||||
#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
|
||||
|
||||
#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
|
||||
#define AT91_MCR_RDR 0x30 /* Receive Data Register */
|
||||
#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
|
||||
|
||||
#define AT91_MCI_SR 0x40 /* Status Register */
|
||||
#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */
|
||||
#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */
|
||||
#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */
|
||||
#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */
|
||||
#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
|
||||
#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
|
||||
#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */
|
||||
#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
|
||||
#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
|
||||
#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
|
||||
#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
|
||||
#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
|
||||
#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */
|
||||
#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */
|
||||
#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */
|
||||
#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */
|
||||
#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
|
||||
#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */
|
||||
#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */
|
||||
#define AT91_MCI_OVRE (1U << 30) /* Overrun */
|
||||
#define AT91_MCI_UNRE (1U << 31) /* Underrun */
|
||||
|
||||
#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
|
||||
#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
|
||||
#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
|
||||
|
||||
extern rt_int32_t at91_mci_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -118,6 +118,8 @@
|
|||
|
||||
//#define RT_USING_LED
|
||||
|
||||
#define RT_USING_MMCSD
|
||||
|
||||
#define RT_USING_DBGU
|
||||
/* #define RT_USING_UART0 */
|
||||
/* #define RT_USING_UART1 */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
src = Split("""
|
||||
block_dev.c
|
||||
mmcsd_core.c
|
||||
sd.c
|
||||
""")
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
path = [RTT_ROOT + '/components/mmcsd']
|
||||
|
||||
|
||||
group = DefineGroup('MMCSD', src, depend = ['RT_USING_MMCSD'], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,447 @@
|
|||
/*
|
||||
* File : block_dev.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <dfs_fs.h>
|
||||
#include "list.h"
|
||||
|
||||
#include "mmcsd_core.h"
|
||||
#include "mmcsd_cmd.h"
|
||||
|
||||
static rt_list_t blk_devices;
|
||||
|
||||
struct mmcsd_blk_device {
|
||||
struct rt_mmcsd_card *card;
|
||||
rt_list_t list;
|
||||
struct rt_device dev;
|
||||
struct dfs_partition part;
|
||||
struct rt_device_blk_geometry geometry;
|
||||
};
|
||||
|
||||
#ifndef RT_MMCSD_MAX_PARTITION
|
||||
#define RT_MMCSD_MAX_PARTITION 16
|
||||
#endif
|
||||
|
||||
static rt_int32_t mmcsd_num_wr_blocks(struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_int32_t err;
|
||||
rt_uint32_t blocks;
|
||||
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
struct rt_mmcsd_data data;
|
||||
rt_uint32_t timeout_us;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = APP_CMD;
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC;
|
||||
|
||||
err = mmcsd_send_cmd(card->host, &cmd, 0);
|
||||
if (err)
|
||||
return -RT_ERROR;
|
||||
if (!controller_is_spi(card->host) && !(cmd.resp[0] & R1_APP_CMD))
|
||||
return -RT_ERROR;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_APP_SEND_NUM_WR_BLKS;
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
data.timeout_ns = card->tacc_ns * 100;
|
||||
data.timeout_clks = card->tacc_clks * 100;
|
||||
|
||||
timeout_us = data.timeout_ns / 1000;
|
||||
timeout_us += data.timeout_clks * 1000 /
|
||||
(card->host->io_cfg.clock / 1000);
|
||||
|
||||
if (timeout_us > 100000)
|
||||
{
|
||||
data.timeout_ns = 100000000;
|
||||
data.timeout_clks = 0;
|
||||
}
|
||||
|
||||
data.blksize = 4;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = &blocks;
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
mmcsd_send_request(card->host, &req);
|
||||
|
||||
if (cmd.err || data.err)
|
||||
return -RT_ERROR;
|
||||
|
||||
return blocks;
|
||||
}
|
||||
|
||||
static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, rt_uint32_t sector, void *buf, rt_size_t blks, rt_uint8_t dir)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd, stop;
|
||||
struct rt_mmcsd_data data;
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_host *host = card->host;
|
||||
rt_uint32_t r_cmd, w_cmd;
|
||||
|
||||
mmcsd_host_lock(host);
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
rt_memset(&stop, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
cmd.arg = sector;
|
||||
if (!(card->card_type & CARD_TYPE_SDHC))
|
||||
{
|
||||
cmd.arg <<= 9;
|
||||
}
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
data.blksize = SECTOR_SIZE;
|
||||
data.blks = blks;
|
||||
|
||||
if (blks > 1)
|
||||
{
|
||||
if (!controller_is_spi(card->host) || !dir)
|
||||
{
|
||||
req.stop = &stop;
|
||||
stop.cmd_code = STOP_TRANSMISSION;
|
||||
stop.arg = 0;
|
||||
stop.flags = RESP_SPI_R1B | RESP_R1B | CMD_AC;
|
||||
}
|
||||
r_cmd = READ_MULTIPLE_BLOCK;
|
||||
w_cmd = WRITE_MULTIPLE_BLOCK;
|
||||
}
|
||||
else
|
||||
{
|
||||
req.stop = NULL;
|
||||
r_cmd = READ_SINGLE_BLOCK;
|
||||
w_cmd = WRITE_BLOCK;
|
||||
}
|
||||
|
||||
if (!dir)
|
||||
{
|
||||
cmd.cmd_code = r_cmd;
|
||||
data.flags |= DATA_DIR_READ;
|
||||
}
|
||||
else
|
||||
{
|
||||
cmd.cmd_code = w_cmd;
|
||||
data.flags |= DATA_DIR_WRITE;
|
||||
}
|
||||
|
||||
mmcsd_set_data_timeout(&data, card);
|
||||
|
||||
data.buf = buf;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
if (!controller_is_spi(card->host) && dir != 0)
|
||||
{
|
||||
do
|
||||
{
|
||||
rt_int32_t err;
|
||||
|
||||
cmd.cmd_code = SEND_STATUS;
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = RESP_R1 | CMD_AC;
|
||||
err = mmcsd_send_cmd(card->host, &cmd, 5);
|
||||
if (err)
|
||||
{
|
||||
rt_kprintf("error %d requesting status\n", err);
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* Some cards mishandle the status bits,
|
||||
* so make sure to check both the busy
|
||||
* indication and the card state.
|
||||
*/
|
||||
} while (!(cmd.resp[0] & R1_READY_FOR_DATA) ||
|
||||
(R1_CURRENT_STATE(cmd.resp[0]) == 7));
|
||||
|
||||
}
|
||||
|
||||
mmcsd_host_unlock(host);
|
||||
|
||||
if (cmd.err || data.err || stop.err)
|
||||
{
|
||||
rt_kprintf("mmcsd request blocks error\n");
|
||||
rt_kprintf("%d,%d,%d, 0x%08x,0x%08x\n", cmd.err, data.err, stop.err, data.flags, sector);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_mmcsd_init(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_mmcsd_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_mmcsd_close(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_mmcsd_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data;
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_BLK_GETGEOME:
|
||||
rt_memcpy(args, &blk_dev->geometry, sizeof(struct rt_device_blk_geometry));
|
||||
break;
|
||||
default: break;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_mmcsd_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_err_t err;
|
||||
struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data;
|
||||
struct dfs_partition *part = &blk_dev->part;
|
||||
|
||||
if ( dev == RT_NULL )
|
||||
{
|
||||
rt_set_errno(-DFS_STATUS_EINVAL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_sem_take(part->lock, RT_WAITING_FOREVER);
|
||||
err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos, buffer, size, 0);
|
||||
rt_sem_release(part->lock);
|
||||
|
||||
/* the length of reading must align to SECTOR SIZE */
|
||||
if (err)
|
||||
{
|
||||
rt_set_errno(-DFS_STATUS_EIO);
|
||||
return 0;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
static rt_size_t rt_mmcsd_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_err_t err;
|
||||
struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data;
|
||||
struct dfs_partition *part = &blk_dev->part;
|
||||
|
||||
if ( dev == RT_NULL )
|
||||
{
|
||||
rt_set_errno(-DFS_STATUS_EINVAL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_sem_take(part->lock, RT_WAITING_FOREVER);
|
||||
err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos, (void *)buffer, size, 1);
|
||||
rt_sem_release(part->lock);
|
||||
|
||||
/* the length of reading must align to SECTOR SIZE */
|
||||
if (err)
|
||||
{
|
||||
rt_set_errno(-DFS_STATUS_EIO);
|
||||
return 0;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
int err;
|
||||
|
||||
/* Block-addressed cards ignore MMC_SET_BLOCKLEN. */
|
||||
if (card->card_type & CARD_TYPE_SDHC)
|
||||
return 0;
|
||||
|
||||
mmcsd_host_lock(card->host);
|
||||
cmd.cmd_code = SET_BLOCKLEN;
|
||||
cmd.arg = 512;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC;
|
||||
err = mmcsd_send_cmd(card->host, &cmd, 5);
|
||||
mmcsd_host_unlock(card->host);
|
||||
|
||||
if (err)
|
||||
{
|
||||
rt_kprintf("MMCSD: unable to set block size to %d: %d\n",
|
||||
cmd.arg, err);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_int32_t err = 0;
|
||||
rt_uint8_t i, status;
|
||||
rt_uint8_t *sector;
|
||||
char dname[4];
|
||||
char sname[8];
|
||||
struct mmcsd_blk_device *blk_dev = RT_NULL;
|
||||
|
||||
err = mmcsd_set_blksize(card);
|
||||
if(err)
|
||||
{
|
||||
return err;
|
||||
}
|
||||
|
||||
/* get the first sector to read partition table */
|
||||
sector = (rt_uint8_t*) rt_malloc (SECTOR_SIZE);
|
||||
if (sector == RT_NULL)
|
||||
{
|
||||
rt_kprintf("allocate partition sector buffer failed\n");
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
status = rt_mmcsd_req_blk(card, 0, sector, 1, 0);
|
||||
if (status == RT_EOK)
|
||||
{
|
||||
for(i=0; i < RT_MMCSD_MAX_PARTITION; i++)
|
||||
{
|
||||
blk_dev = rt_malloc(sizeof(struct mmcsd_blk_device));
|
||||
if (!blk_dev)
|
||||
{
|
||||
rt_kprintf("mmcsd:malloc mem failde\n");
|
||||
break;
|
||||
}
|
||||
rt_memset((void *)blk_dev, 0, sizeof(struct mmcsd_blk_device));
|
||||
/* get the first partition */
|
||||
status = dfs_filesystem_get_partition(&blk_dev->part, sector, i);
|
||||
if (status == RT_EOK)
|
||||
{
|
||||
rt_snprintf(dname, 4, "sd%d", i);
|
||||
rt_snprintf(sname, 8, "sem_sd%d", i);
|
||||
blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO);
|
||||
|
||||
/* register mmcsd device */
|
||||
blk_dev->dev.type = RT_Device_Class_Block;
|
||||
blk_dev->dev.init = rt_mmcsd_init;
|
||||
blk_dev->dev.open = rt_mmcsd_open;
|
||||
blk_dev->dev.close = rt_mmcsd_close;
|
||||
blk_dev->dev.read = rt_mmcsd_read;
|
||||
blk_dev->dev.write = rt_mmcsd_write;
|
||||
blk_dev->dev.control = rt_mmcsd_control;
|
||||
blk_dev->dev.user_data = blk_dev;
|
||||
|
||||
blk_dev->card = card;
|
||||
|
||||
blk_dev->geometry.bytes_per_sector = 1<<9;
|
||||
blk_dev->geometry.block_size = card->card_blksize;
|
||||
blk_dev->geometry.sector_count = blk_dev->part.size;
|
||||
|
||||
rt_device_register(&blk_dev->dev, dname,
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
|
||||
list_insert_after(&blk_devices, &blk_dev->list);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(i == 0)
|
||||
{
|
||||
/* there is no partition table */
|
||||
blk_dev->part.offset = 0;
|
||||
blk_dev->part.size = 0;
|
||||
blk_dev->part.lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO);
|
||||
|
||||
/* register mmcsd device */
|
||||
blk_dev->dev.type = RT_Device_Class_Block;
|
||||
blk_dev->dev.init = rt_mmcsd_init;
|
||||
blk_dev->dev.open = rt_mmcsd_open;
|
||||
blk_dev->dev.close = rt_mmcsd_close;
|
||||
blk_dev->dev.read = rt_mmcsd_read;
|
||||
blk_dev->dev.write = rt_mmcsd_write;
|
||||
blk_dev->dev.control = rt_mmcsd_control;
|
||||
blk_dev->dev.user_data = blk_dev;
|
||||
|
||||
blk_dev->card = card;
|
||||
|
||||
blk_dev->geometry.bytes_per_sector = 1<<9;
|
||||
blk_dev->geometry.block_size = card->card_blksize;
|
||||
if (card->card_type | CARD_TYPE_SDHC)
|
||||
{
|
||||
blk_dev->geometry.sector_count = (card->csd.c_size + 1) * 1024;
|
||||
}
|
||||
else
|
||||
{
|
||||
blk_dev->geometry.sector_count =
|
||||
card->card_capacity * 1024 / 512;
|
||||
}
|
||||
|
||||
rt_device_register(&blk_dev->dev, "sd0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
|
||||
list_insert_after(&blk_devices, &blk_dev->list);
|
||||
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_free(blk_dev);
|
||||
blk_dev = RT_NULL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("read mmcsd first sector failed\n");
|
||||
err = -RT_ERROR;
|
||||
}
|
||||
|
||||
/* release sector buffer */
|
||||
rt_free(sector);
|
||||
|
||||
return err;
|
||||
|
||||
|
||||
}
|
||||
|
||||
void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_list_t *l;
|
||||
struct mmcsd_blk_device *blk_dev;
|
||||
|
||||
for (l = (&blk_devices)->next; l != &blk_devices; l = l->next)
|
||||
{
|
||||
blk_dev = (struct mmcsd_blk_device *)list_entry(l, struct mmcsd_blk_device, list);
|
||||
if (blk_dev->card == card)
|
||||
{
|
||||
rt_device_unregister(&blk_dev->dev);
|
||||
list_remove(&blk_dev->list);
|
||||
rt_free(blk_dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void rt_mmcsd_blk_init(void)
|
||||
{
|
||||
list_init(&blk_devices);
|
||||
}
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* File : list.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-15 weety copy from kservice APIs
|
||||
*/
|
||||
|
||||
#ifndef __RT_LIST_H__
|
||||
#define __RT_LIST_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @addtogroup list
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* @brief initialize a list
|
||||
*
|
||||
* @param l list to be initialized
|
||||
*/
|
||||
rt_inline void list_init(rt_list_t *l)
|
||||
{
|
||||
l->next = l->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node after a list
|
||||
*
|
||||
* @param l list to insert it
|
||||
* @param n new node to be inserted
|
||||
*/
|
||||
rt_inline void list_insert_after(rt_list_t *l, rt_list_t *n)
|
||||
{
|
||||
l->next->prev = n;
|
||||
n->next = l->next;
|
||||
|
||||
l->next = n;
|
||||
n->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node before a list
|
||||
*
|
||||
* @param n new node to be inserted
|
||||
* @param l list to insert it
|
||||
*/
|
||||
rt_inline void list_insert_before(rt_list_t *l, rt_list_t *n)
|
||||
{
|
||||
l->prev->next = n;
|
||||
n->prev = l->prev;
|
||||
|
||||
l->prev = n;
|
||||
n->next = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief remove node from list.
|
||||
* @param n the node to remove from the list.
|
||||
*/
|
||||
rt_inline void list_remove(rt_list_t *n)
|
||||
{
|
||||
n->next->prev = n->prev;
|
||||
n->prev->next = n->next;
|
||||
|
||||
n->next = n->prev = n;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief tests whether a list is empty
|
||||
* @param l the list to test.
|
||||
*/
|
||||
rt_inline int list_isempty(const rt_list_t *l)
|
||||
{
|
||||
return l->next == l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the struct for this entry
|
||||
* @param node the entry point
|
||||
* @param type the type of structure
|
||||
* @param member the name of list in structure
|
||||
*/
|
||||
#define list_entry(node, type, member) \
|
||||
((type *)((char *)(node) - (unsigned long)(&((type *)0)->member)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* File : mmcsd_card.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __MMCSD_CARD_H__
|
||||
#define __MMCSD_CARD_H__
|
||||
|
||||
#include "mmcsd_host.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SD_SCR_BUS_WIDTH_1 (1 << 0)
|
||||
#define SD_SCR_BUS_WIDTH_4 (1 << 2)
|
||||
|
||||
struct rt_mmcsd_cid {
|
||||
rt_uint8_t mid; /* ManufacturerID */
|
||||
rt_uint8_t prv; /* Product Revision */
|
||||
rt_uint16_t oid; /* OEM/Application ID */
|
||||
rt_uint32_t psn; /* Product Serial Number */
|
||||
rt_uint8_t pnm[5]; /* Product Name */
|
||||
rt_uint8_t reserved1;/* reserved */
|
||||
rt_uint16_t mdt; /* Manufacturing Date */
|
||||
rt_uint8_t crc; /* CID CRC */
|
||||
rt_uint8_t reserved2;/* not used, always 1 */
|
||||
};
|
||||
|
||||
struct rt_mmcsd_csd {
|
||||
rt_uint8_t csd_structure; /* CSD register version */
|
||||
rt_uint8_t taac;
|
||||
rt_uint8_t nsac;
|
||||
rt_uint8_t tran_speed; /* max data transfer rate */
|
||||
rt_uint16_t card_cmd_class; /* card command classes */
|
||||
rt_uint8_t rd_blk_len; /* max read data block length */
|
||||
rt_uint8_t rd_blk_part;
|
||||
rt_uint8_t wr_blk_misalign;
|
||||
rt_uint8_t rd_blk_misalign;
|
||||
rt_uint8_t dsr_imp; /* DSR implemented */
|
||||
rt_uint8_t c_size_mult; /* CSD 1.0 , device size multiplier */
|
||||
rt_uint32_t c_size; /* device size */
|
||||
rt_uint8_t r2w_factor;
|
||||
rt_uint8_t wr_blk_len; /* max wtire data block length */
|
||||
rt_uint8_t wr_blk_partial;
|
||||
rt_uint8_t csd_crc;
|
||||
|
||||
};
|
||||
|
||||
struct rt_sd_scr {
|
||||
rt_uint8_t sd_version;
|
||||
rt_uint8_t sd_bus_widths;
|
||||
};
|
||||
|
||||
struct rt_mmcsd_card {
|
||||
struct rt_mmcsd_host *host;
|
||||
rt_uint32_t rca; /* card addr */
|
||||
rt_uint32_t resp_cid[4]; /* card CID register */
|
||||
rt_uint32_t resp_csd[4]; /* card CSD register */
|
||||
rt_uint32_t resp_scr[2]; /* card SCR register */
|
||||
|
||||
rt_uint16_t tacc_clks; /* data access time by ns */
|
||||
rt_uint32_t tacc_ns; /* data access time by clk cycles */
|
||||
rt_uint32_t max_data_rate; /* max data transfer rate */
|
||||
rt_uint32_t card_capacity; /* card capacity, unit:KB */
|
||||
rt_uint32_t card_blksize; /* card block size */
|
||||
rt_uint32_t card_type;
|
||||
#define CARD_TYPE_MMC (1 << 0) /* MMC card */
|
||||
#define CARD_TYPE_SD (1 << 1) /* SD card */
|
||||
#define CARD_TYPE_SDIO (1 << 2) /* SDIO card */
|
||||
#define CARD_TYPE_SDHC (1 << 3) /* SDHC card */
|
||||
struct rt_sd_scr scr;
|
||||
struct rt_mmcsd_csd csd;
|
||||
rt_uint32_t hs_max_data_rate; /* max data transfer rate in high speed mode */
|
||||
rt_uint32_t flags;
|
||||
#define CARD_MODE_HIGHSPEED (1 << 0)
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* File : mmcsd_cmd.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __CMD_H__
|
||||
#define __CMD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* class 1 */
|
||||
#define GO_IDLE_STATE 0 /* bc */
|
||||
#define SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
|
||||
#define ALL_SEND_CID 2 /* bcr R2 */
|
||||
#define SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
|
||||
#define SET_DSR 4 /* bc [31:16] RCA */
|
||||
#define SWITCH 6 /* ac [31:0] See below R1b */
|
||||
#define SELECT_CARD 7 /* ac [31:16] RCA R1 */
|
||||
#define SEND_EXT_CSD 8 /* adtc R1 */
|
||||
#define SEND_CSD 9 /* ac [31:16] RCA R2 */
|
||||
#define SEND_CID 10 /* ac [31:16] RCA R2 */
|
||||
#define READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
|
||||
#define STOP_TRANSMISSION 12 /* ac R1b */
|
||||
#define SEND_STATUS 13 /* ac [31:16] RCA R1 */
|
||||
#define GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
|
||||
#define SPI_READ_OCR 58 /* spi spi_R3 */
|
||||
#define SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
|
||||
|
||||
/* class 2 */
|
||||
#define SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
|
||||
#define READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
|
||||
#define READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 3 */
|
||||
#define WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 4 */
|
||||
#define SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
|
||||
#define WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
|
||||
#define WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
|
||||
#define PROGRAM_CID 26 /* adtc R1 */
|
||||
#define PROGRAM_CSD 27 /* adtc R1 */
|
||||
|
||||
/* class 6 */
|
||||
#define SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
|
||||
#define CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
|
||||
#define SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
|
||||
#define ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
|
||||
#define ERASE 38 /* ac R1b */
|
||||
|
||||
/* class 9 */
|
||||
#define FAST_IO 39 /* ac <Complex> R4 */
|
||||
#define GO_IRQ_STATE 40 /* bcr R5 */
|
||||
|
||||
/* class 7 */
|
||||
#define LOCK_UNLOCK 42 /* adtc R1b */
|
||||
|
||||
/* class 8 */
|
||||
#define APP_CMD 55 /* ac [31:16] RCA R1 */
|
||||
#define GEN_CMD 56 /* adtc [0] RD/WR R1 */
|
||||
|
||||
|
||||
/* SD commands type argument response */
|
||||
/* class 0 */
|
||||
/* This is basically the same command as for MMC with some quirks. */
|
||||
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
|
||||
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
|
||||
|
||||
/* class 10 */
|
||||
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
|
||||
|
||||
/* Application commands */
|
||||
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
|
||||
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
|
||||
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||
#define SD_APP_SEND_SCR 51 /* adtc R1 */
|
||||
|
||||
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
|
||||
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
|
||||
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,631 @@
|
|||
/*
|
||||
* File : mmcsd_core.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "mmcsd_core.h"
|
||||
#include "mmcsd_card.h"
|
||||
#include "mmcsd_cmd.h"
|
||||
#include "sd.h"
|
||||
|
||||
#ifndef RT_MMCSD_STACK_SIZE
|
||||
#define RT_MMCSD_STACK_SIZE 1024
|
||||
#endif
|
||||
#ifndef RT_MMCSD_THREAD_PREORITY
|
||||
#define RT_MMCSD_THREAD_PREORITY 0x40
|
||||
#endif
|
||||
|
||||
//static struct rt_semaphore mmcsd_sem;
|
||||
static struct rt_thread mmcsd_detect_thread;
|
||||
static rt_uint8_t mmcsd_stack[RT_MMCSD_STACK_SIZE];
|
||||
static struct rt_mailbox mmcsd_detect_mb;
|
||||
static rt_uint32_t mmcsd_detect_mb_pool[4];
|
||||
|
||||
void mmcsd_host_lock(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_sem_take(&host->bus_lock, RT_WAITING_FOREVER);
|
||||
}
|
||||
|
||||
void mmcsd_host_unlock(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_sem_release(&host->bus_lock);
|
||||
}
|
||||
|
||||
void mmcsd_req_complete(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_sem_release(&host->sem_ack);
|
||||
}
|
||||
|
||||
void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
||||
{
|
||||
req->cmd->data = req->data;
|
||||
host->ops->request(host, req);
|
||||
rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries)
|
||||
{
|
||||
struct rt_mmcsd_req req;
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
rt_memset(cmd->resp, 0, sizeof(cmd->resp));
|
||||
|
||||
req.cmd = cmd;
|
||||
cmd->data = RT_NULL;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
return cmd->err;
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_int32_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
if (!controller_is_spi(host)) {
|
||||
mmcsd_set_chip_select(host, MMCSD_CS_HIGH);
|
||||
mmcsd_delay_ms(1);
|
||||
}
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = GO_IDLE_STATE;
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_NONE | CMD_BC;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 0);
|
||||
|
||||
mmcsd_delay_ms(1);
|
||||
|
||||
if (!controller_is_spi(host))
|
||||
{
|
||||
mmcsd_set_chip_select(host, MMCSD_CS_IGNORE);
|
||||
mmcsd_delay_ms(1);
|
||||
}
|
||||
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
rt_int32_t err;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SPI_READ_OCR;
|
||||
cmd.arg = high_capacity ? (1 << 30) : 0;
|
||||
cmd.flags = RESP_SPI_R3;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 0);
|
||||
|
||||
*ocr = cmd.resp[1];
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
|
||||
{
|
||||
rt_int32_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = ALL_SEND_CID;
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_R2 | CMD_BCR;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
|
||||
{
|
||||
rt_int32_t err, i;
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
struct rt_mmcsd_data data;
|
||||
rt_uint32_t *buf = RT_NULL;
|
||||
|
||||
if (!controller_is_spi(host))
|
||||
{
|
||||
if (!host->card)
|
||||
return -RT_ERROR;
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SEND_CID;
|
||||
cmd.arg = host->card->rca << 16;
|
||||
cmd.flags = RESP_R2 | CMD_AC;
|
||||
err = mmcsd_send_cmd(host, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
buf = rt_malloc(16);
|
||||
if (!buf)
|
||||
{
|
||||
rt_kprintf("malloc mem failed\n");
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
cmd.cmd_code = SEND_CID;
|
||||
cmd.arg = 0;
|
||||
|
||||
/* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
|
||||
* rely on callers to never use this with "native" calls for reading
|
||||
* CSD or CID. Native versions of those commands use the R2 type,
|
||||
* not R1 plus a data block.
|
||||
*/
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
data.blksize = 16;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = buf;
|
||||
/*
|
||||
* The spec states that CSR and CID accesses have a timeout
|
||||
* of 64 clock cycles.
|
||||
*/
|
||||
data.timeout_ns = 0;
|
||||
data.timeout_clks = 64;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
if (cmd.err || data.err)
|
||||
{
|
||||
rt_free(buf);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
for (i = 0;i < 4;i++)
|
||||
cid[i] = buf[i];
|
||||
rt_free(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd)
|
||||
{
|
||||
rt_int32_t err, i;
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
struct rt_mmcsd_data data;
|
||||
rt_uint32_t *buf = RT_NULL;
|
||||
|
||||
if (!controller_is_spi(card->host))
|
||||
{
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SEND_CSD;
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = RESP_R2 | CMD_AC;
|
||||
err = mmcsd_send_cmd(card->host, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rt_memcpy(csd, cmd.resp, sizeof(rt_uint32_t) * 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
buf = rt_malloc(16);
|
||||
if (!buf)
|
||||
{
|
||||
rt_kprintf("malloc mem failed\n");
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
cmd.cmd_code = SEND_CSD;
|
||||
cmd.arg = 0;
|
||||
|
||||
/* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
|
||||
* rely on callers to never use this with "native" calls for reading
|
||||
* CSD or CID. Native versions of those commands use the R2 type,
|
||||
* not R1 plus a data block.
|
||||
*/
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
data.blksize = 16;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = buf;
|
||||
|
||||
/*
|
||||
* The spec states that CSR and CID accesses have a timeout
|
||||
* of 64 clock cycles.
|
||||
*/
|
||||
data.timeout_ns = 0;
|
||||
data.timeout_clks = 64;
|
||||
|
||||
mmcsd_send_request(card->host, &req);
|
||||
|
||||
if (cmd.err || data.err)
|
||||
{
|
||||
rt_free(buf);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
for (i = 0;i < 4;i++)
|
||||
csd[i] = buf[i];
|
||||
rt_free(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_int32_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SELECT_CARD;
|
||||
|
||||
if (card)
|
||||
{
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = RESP_R1 | CMD_AC;
|
||||
}
|
||||
else
|
||||
{
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_NONE | CMD_AC;
|
||||
}
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card)
|
||||
{
|
||||
return _mmcsd_select_card(card->host, card);
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *card)
|
||||
{
|
||||
return _mmcsd_select_card(card->host, RT_NULL);
|
||||
}
|
||||
|
||||
rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
rt_int32_t err;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SPI_CRC_ON_OFF;
|
||||
cmd.flags = RESP_SPI_R1;
|
||||
cmd.arg = use_crc;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 0);
|
||||
if (!err)
|
||||
host->spi_use_crc = use_crc;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
rt_inline void mmcsd_set_iocfg(struct rt_mmcsd_host *host)
|
||||
{
|
||||
struct rt_mmcsd_io_cfg *io_cfg = &host->io_cfg;
|
||||
|
||||
mmcsd_dbg("clock %uHz busmode %u powermode %u cs %u Vdd %u "
|
||||
"width %u \n",
|
||||
io_cfg->clock, io_cfg->bus_mode,
|
||||
io_cfg->power_mode, io_cfg->chip_select, io_cfg->vdd,
|
||||
io_cfg->bus_width);
|
||||
|
||||
host->ops->set_iocfg(host, io_cfg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Control chip select pin on a host.
|
||||
*/
|
||||
void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode)
|
||||
{
|
||||
host->io_cfg.chip_select = mode;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the host clock to the highest possible frequency that
|
||||
* is below "hz".
|
||||
*/
|
||||
void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk)
|
||||
{
|
||||
if (clk < host->freq_min)
|
||||
{
|
||||
rt_kprintf("clock too low\n");
|
||||
}
|
||||
|
||||
host->io_cfg.clock = clk;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
|
||||
/*
|
||||
* Change the bus mode (open drain/push-pull) of a host.
|
||||
*/
|
||||
void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode)
|
||||
{
|
||||
host->io_cfg.bus_mode = mode;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
|
||||
/*
|
||||
* Change data bus width of a host.
|
||||
*/
|
||||
void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width)
|
||||
{
|
||||
host->io_cfg.bus_width = width;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
|
||||
void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_uint32_t mult;
|
||||
|
||||
if (card->card_type & CARD_TYPE_SDIO)
|
||||
{
|
||||
data->timeout_ns = 1000000000; /* SDIO card 1s */
|
||||
data->timeout_clks = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* SD cards use a 100 multiplier rather than 10
|
||||
*/
|
||||
mult = (card->card_type & CARD_TYPE_SD) ? 100 : 10;
|
||||
|
||||
/*
|
||||
* Scale up the multiplier (and therefore the timeout) by
|
||||
* the r2w factor for writes.
|
||||
*/
|
||||
if (data->flags & DATA_DIR_WRITE)
|
||||
mult <<= card->csd.r2w_factor;
|
||||
|
||||
data->timeout_ns = card->tacc_ns * mult;
|
||||
data->timeout_clks = card->tacc_clks * mult;
|
||||
|
||||
/*
|
||||
* SD cards also have an upper limit on the timeout.
|
||||
*/
|
||||
if (card->card_type & CARD_TYPE_SD)
|
||||
{
|
||||
rt_uint32_t timeout_us, limit_us;
|
||||
|
||||
timeout_us = data->timeout_ns / 1000;
|
||||
timeout_us += data->timeout_clks * 1000 /
|
||||
(card->host->io_cfg.clock / 1000);
|
||||
|
||||
if (data->flags & DATA_DIR_WRITE)
|
||||
/*
|
||||
* The limit is really 250 ms, but that is
|
||||
* insufficient for some crappy cards.
|
||||
*/
|
||||
limit_us = 300000;
|
||||
else
|
||||
limit_us = 100000;
|
||||
|
||||
/*
|
||||
* SDHC cards always use these fixed values.
|
||||
*/
|
||||
if (timeout_us > limit_us || card->card_type & CARD_TYPE_SDHC)
|
||||
{
|
||||
data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */
|
||||
data->timeout_clks = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (controller_is_spi(card->host))
|
||||
{
|
||||
if (data->flags & DATA_DIR_WRITE)
|
||||
{
|
||||
if (data->timeout_ns < 1000000000)
|
||||
data->timeout_ns = 1000000000; /* 1s */
|
||||
}
|
||||
else
|
||||
{
|
||||
if (data->timeout_ns < 100000000)
|
||||
data->timeout_ns = 100000000; /* 100ms */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Mask off any voltages we don't support and select
|
||||
* the lowest voltage
|
||||
*/
|
||||
rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr)
|
||||
{
|
||||
int bit;
|
||||
|
||||
ocr &= host->valid_ocr;
|
||||
|
||||
bit = ffs(ocr);
|
||||
if (bit)
|
||||
{
|
||||
bit -= 1;
|
||||
|
||||
ocr &= 3 << bit;
|
||||
|
||||
host->io_cfg.vdd = bit;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("host doesn't support card's voltages\n");
|
||||
ocr = 0;
|
||||
}
|
||||
|
||||
return ocr;
|
||||
}
|
||||
|
||||
|
||||
static void mmcsd_power_up(struct rt_mmcsd_host *host)
|
||||
{
|
||||
int bit = fls(host->valid_ocr) - 1;
|
||||
|
||||
host->io_cfg.vdd = bit;
|
||||
if (controller_is_spi(host))
|
||||
{
|
||||
host->io_cfg.chip_select = MMCSD_CS_HIGH;
|
||||
host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
host->io_cfg.chip_select = MMCSD_CS_IGNORE;
|
||||
host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
|
||||
}
|
||||
host->io_cfg.power_mode = MMCSD_POWER_UP;
|
||||
host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
|
||||
mmcsd_set_iocfg(host);
|
||||
|
||||
/*
|
||||
* This delay should be sufficient to allow the power supply
|
||||
* to reach the minimum voltage.
|
||||
*/
|
||||
mmcsd_delay_ms(10);
|
||||
|
||||
host->io_cfg.clock = host->freq_min;
|
||||
host->io_cfg.power_mode = MMCSD_POWER_ON;
|
||||
mmcsd_set_iocfg(host);
|
||||
|
||||
/*
|
||||
* This delay must be at least 74 clock sizes, or 1 ms, or the
|
||||
* time required to reach a stable voltage.
|
||||
*/
|
||||
mmcsd_delay_ms(10);
|
||||
}
|
||||
|
||||
static void mmcsd_power_off(struct rt_mmcsd_host *host)
|
||||
{
|
||||
host->io_cfg.clock = 0;
|
||||
host->io_cfg.vdd = 0;
|
||||
if (!controller_is_spi(host))
|
||||
{
|
||||
host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
|
||||
host->io_cfg.chip_select = MMCSD_CS_IGNORE;
|
||||
}
|
||||
host->io_cfg.power_mode = MMCSD_POWER_OFF;
|
||||
host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
|
||||
mmcsd_set_iocfg(host);
|
||||
}
|
||||
|
||||
void mmcsd_change(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_mb_send(&mmcsd_detect_mb, (rt_uint32_t)host);
|
||||
}
|
||||
|
||||
void mmcsd_detect(void *param)
|
||||
{
|
||||
struct rt_mmcsd_host *host;
|
||||
rt_uint32_t ocr;
|
||||
rt_int32_t err;
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (rt_mb_recv(&mmcsd_detect_mb, (rt_uint32_t*)&host, RT_WAITING_FOREVER) == RT_EOK)
|
||||
{
|
||||
mmcsd_host_lock(host);
|
||||
mmcsd_power_up(host);
|
||||
mmcsd_go_idle(host);
|
||||
|
||||
mmcsd_send_if_cond(host, host->valid_ocr);
|
||||
|
||||
/*
|
||||
* detect SD card
|
||||
*/
|
||||
err = mmcsd_send_app_op_cond(host, 0, &ocr);
|
||||
if (!err)
|
||||
{
|
||||
if (init_sd(host, ocr))
|
||||
mmcsd_power_off(host);
|
||||
mmcsd_host_unlock(host);
|
||||
continue;
|
||||
}
|
||||
mmcsd_host_unlock(host);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct rt_mmcsd_host *mmcsd_alloc_host(void)
|
||||
{
|
||||
struct rt_mmcsd_host *host;
|
||||
|
||||
host = rt_malloc(sizeof(struct rt_mmcsd_host));
|
||||
if (!host)
|
||||
{
|
||||
rt_kprintf("alloc host failed\n");
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
rt_memset(host, 0, sizeof(struct rt_mmcsd_host));
|
||||
|
||||
rt_sem_init(&host->bus_lock, "sd_bus_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&host->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
return host;
|
||||
}
|
||||
|
||||
void mmcsd_free_host(struct rt_mmcsd_host *host)
|
||||
{
|
||||
rt_sem_detach(&host->bus_lock);
|
||||
rt_sem_detach(&host->sem_ack);
|
||||
rt_free(host);
|
||||
}
|
||||
|
||||
void rt_mmcsd_core_init(void)
|
||||
{
|
||||
rt_err_t ret;
|
||||
|
||||
/* init detect sd cart thread */
|
||||
/* init mailbox and create detect sd card thread */
|
||||
ret = rt_mb_init(&mmcsd_detect_mb, "mmcsdmb",
|
||||
&mmcsd_detect_mb_pool[0], sizeof(mmcsd_detect_mb_pool),
|
||||
RT_IPC_FLAG_FIFO);
|
||||
RT_ASSERT(ret == RT_EOK);
|
||||
|
||||
ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL,
|
||||
&mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20);
|
||||
if (ret == RT_EOK)
|
||||
{
|
||||
rt_thread_startup(&mmcsd_detect_thread);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
* File : mmcsd_core.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __CORE_H__
|
||||
#define __CORE_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "mmcsd_host.h"
|
||||
#include "mmcsd_card.h"
|
||||
#include "mmcsd_cmd.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef RT_MMCSD_DBG
|
||||
#define mmcsd_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define mmcsd_dbg(fmt, ...)
|
||||
#endif
|
||||
|
||||
struct rt_mmcsd_data {
|
||||
rt_uint32_t blksize;
|
||||
rt_uint32_t blks;
|
||||
rt_uint32_t *buf;
|
||||
rt_int32_t err;
|
||||
rt_uint32_t flags;
|
||||
#define DATA_DIR_WRITE (1 << 0)
|
||||
#define DATA_DIR_READ (1 << 1)
|
||||
#define DATA_STREAM (1 << 2)
|
||||
rt_uint32_t timeout_ns;
|
||||
rt_uint32_t timeout_clks;
|
||||
};
|
||||
|
||||
struct rt_mmcsd_cmd {
|
||||
rt_uint32_t cmd_code;
|
||||
rt_uint32_t arg;
|
||||
rt_uint32_t resp[4];
|
||||
rt_uint32_t flags;
|
||||
/*rsponse types
|
||||
*bits:0~3
|
||||
*/
|
||||
#define RESP_MASK (0xF)
|
||||
#define RESP_NONE (0)
|
||||
#define RESP_R1 (1 << 0)
|
||||
#define RESP_R1B (2 << 0)
|
||||
#define RESP_R2 (3 << 0)
|
||||
#define RESP_R3 (4 << 0)
|
||||
#define RESP_R4 (5 << 0)
|
||||
#define RESP_R6 (6 << 0)
|
||||
#define RESP_R7 (7 << 0)
|
||||
/*command types
|
||||
*bits:4~5
|
||||
*/
|
||||
#define CMD_MASK (3 << 4) /* command type */
|
||||
#define CMD_AC (0 << 4)
|
||||
#define CMD_ADTC (1 << 4)
|
||||
#define CMD_BC (2 << 4)
|
||||
#define CMD_BCR (3 << 4)
|
||||
|
||||
#define resp_type(cmd) ((cmd)->flags & RESP_MASK)
|
||||
|
||||
/*spi rsponse types
|
||||
*bits:6~8
|
||||
*/
|
||||
#define RESP_SPI_MASK (0x7 << 6)
|
||||
#define RESP_SPI_R1 (1 << 6)
|
||||
#define RESP_SPI_R1B (2 << 6)
|
||||
#define RESP_SPI_R2 (3 << 6)
|
||||
#define RESP_SPI_R3 (4 << 6)
|
||||
#define RESP_SPI_R4 (5 << 6)
|
||||
#define RESP_SPI_R5 (6 << 6)
|
||||
#define RESP_SPI_R7 (7 << 6)
|
||||
|
||||
#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK)
|
||||
/*
|
||||
* These are the command types.
|
||||
*/
|
||||
#define cmd_type(cmd) ((cmd)->flags & CMD_MASK)
|
||||
|
||||
rt_int32_t err;
|
||||
|
||||
struct rt_mmcsd_data *data;
|
||||
};
|
||||
|
||||
struct rt_mmcsd_req {
|
||||
struct rt_mmcsd_data *data;
|
||||
struct rt_mmcsd_cmd *cmd;
|
||||
struct rt_mmcsd_cmd *stop;
|
||||
};
|
||||
|
||||
/*the following is response bit*/
|
||||
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||
#define R1_ERROR (1 << 19) /* erx, c */
|
||||
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||
#define R1_APP_CMD (1 << 5) /* sr, c */
|
||||
|
||||
|
||||
#define R1_SPI_IDLE (1 << 0)
|
||||
#define R1_SPI_ERASE_RESET (1 << 1)
|
||||
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
|
||||
#define R1_SPI_COM_CRC (1 << 3)
|
||||
#define R1_SPI_ERASE_SEQ (1 << 4)
|
||||
#define R1_SPI_ADDRESS (1 << 5)
|
||||
#define R1_SPI_PARAMETER (1 << 6)
|
||||
/* R1 bit 7 is always zero */
|
||||
#define R2_SPI_CARD_LOCKED (1 << 8)
|
||||
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
|
||||
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
|
||||
#define R2_SPI_ERROR (1 << 10)
|
||||
#define R2_SPI_CC_ERROR (1 << 11)
|
||||
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
|
||||
#define R2_SPI_WP_VIOLATION (1 << 13)
|
||||
#define R2_SPI_ERASE_PARAM (1 << 14)
|
||||
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
|
||||
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
|
||||
|
||||
#define CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||
|
||||
/**
|
||||
* fls - find last (most-significant) bit set
|
||||
* @x: the word to search
|
||||
*
|
||||
* This is defined the same way as ffs.
|
||||
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
|
||||
*/
|
||||
|
||||
rt_inline rt_uint32_t fls(rt_uint32_t val)
|
||||
{
|
||||
rt_uint32_t bit = 32;
|
||||
|
||||
if (!val)
|
||||
return 0;
|
||||
if (!(val & 0xffff0000u))
|
||||
{
|
||||
val <<= 16;
|
||||
bit -= 16;
|
||||
}
|
||||
if (!(val & 0xff000000u))
|
||||
{
|
||||
val <<= 8;
|
||||
bit -= 8;
|
||||
}
|
||||
if (!(val & 0xf0000000u))
|
||||
{
|
||||
val <<= 4;
|
||||
bit -= 4;
|
||||
}
|
||||
if (!(val & 0xc0000000u))
|
||||
{
|
||||
val <<= 2;
|
||||
bit -= 2;
|
||||
}
|
||||
if (!(val & 0x80000000u))
|
||||
{
|
||||
val <<= 1;
|
||||
bit -= 1;
|
||||
}
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
#if !defined(__GNUC__)
|
||||
rt_inline rt_uint32_t ffs(rt_uint32_t x)
|
||||
{
|
||||
int r = 1;
|
||||
|
||||
if (!x)
|
||||
return 0;
|
||||
if (!(x & 0xffff)) {
|
||||
x >>= 16;
|
||||
r += 16;
|
||||
}
|
||||
if (!(x & 0xff)) {
|
||||
x >>= 8;
|
||||
r += 8;
|
||||
}
|
||||
if (!(x & 0xf)) {
|
||||
x >>= 4;
|
||||
r += 4;
|
||||
}
|
||||
if (!(x & 3)) {
|
||||
x >>= 2;
|
||||
r += 2;
|
||||
}
|
||||
if (!(x & 1)) {
|
||||
x >>= 1;
|
||||
r += 1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
#endif
|
||||
|
||||
void mmcsd_host_lock(struct rt_mmcsd_host *host);
|
||||
void mmcsd_host_unlock(struct rt_mmcsd_host *host);
|
||||
void mmcsd_req_complete(struct rt_mmcsd_host *host);
|
||||
void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
|
||||
rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries);
|
||||
rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host);
|
||||
rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr);
|
||||
rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
|
||||
rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
|
||||
rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd);
|
||||
rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card);
|
||||
rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *host);
|
||||
rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc);
|
||||
void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode);
|
||||
void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk);
|
||||
void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode);
|
||||
void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width);
|
||||
void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card);
|
||||
rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
void mmcsd_change(struct rt_mmcsd_host *host);
|
||||
void mmcsd_detect(void *param);
|
||||
struct rt_mmcsd_host *mmcsd_alloc_host(void);
|
||||
void mmcsd_free_host(struct rt_mmcsd_host *host);
|
||||
void rt_mmcsd_core_init(void);
|
||||
|
||||
void rt_mmcsd_blk_init(void);
|
||||
rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card);
|
||||
void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* File : mmcsd_host.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __HOST_H__
|
||||
#define __HOST_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct rt_mmcsd_io_cfg {
|
||||
rt_uint32_t clock; /* clock rate */
|
||||
rt_uint16_t vdd;
|
||||
|
||||
/* vdd stores the bit number of the selected voltage range from below. */
|
||||
|
||||
rt_uint8_t bus_mode; /* command output mode */
|
||||
|
||||
#define MMCSD_BUSMODE_OPENDRAIN 1
|
||||
#define MMCSD_BUSMODE_PUSHPULL 2
|
||||
|
||||
rt_uint8_t chip_select; /* SPI chip select */
|
||||
|
||||
#define MMCSD_CS_IGNORE 0
|
||||
#define MMCSD_CS_HIGH 1
|
||||
#define MMCSD_CS_LOW 2
|
||||
|
||||
rt_uint8_t power_mode; /* power supply mode */
|
||||
|
||||
#define MMCSD_POWER_OFF 0
|
||||
#define MMCSD_POWER_UP 1
|
||||
#define MMCSD_POWER_ON 2
|
||||
|
||||
rt_uint8_t bus_width; /* data bus width */
|
||||
|
||||
#define MMCSD_BUS_WIDTH_1 0
|
||||
#define MMCSD_BUS_WIDTH_4 2
|
||||
#define MMCSD_BUS_WIDTH_8 3
|
||||
|
||||
};
|
||||
|
||||
struct rt_mmcsd_host;
|
||||
struct rt_mmcsd_req;
|
||||
|
||||
struct rt_mmcsd_host_ops {
|
||||
void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
|
||||
void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg);
|
||||
rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host);
|
||||
};
|
||||
|
||||
struct rt_mmcsd_host {
|
||||
struct rt_mmcsd_card *card;
|
||||
const struct rt_mmcsd_host_ops *ops;
|
||||
rt_uint32_t freq_min;
|
||||
rt_uint32_t freq_max;
|
||||
struct rt_mmcsd_io_cfg io_cfg;
|
||||
rt_uint32_t valid_ocr; /* current valid OCR */
|
||||
#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */
|
||||
#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */
|
||||
#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */
|
||||
#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */
|
||||
#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */
|
||||
#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */
|
||||
#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */
|
||||
#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */
|
||||
#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */
|
||||
#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */
|
||||
#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */
|
||||
#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */
|
||||
#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */
|
||||
#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
|
||||
#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */
|
||||
#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */
|
||||
#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */
|
||||
rt_uint32_t flags; /* define device capabilities */
|
||||
#define MMCSD_BUSWIDTH_4 (1 << 0)
|
||||
#define MMCSD_BUSWIDTH_8 (1 << 1)
|
||||
#define MMCSD_MUTBLKWRITE (1 << 2)
|
||||
#define MMCSD_HOST_IS_SPI (1 << 3)
|
||||
#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI)
|
||||
rt_uint32_t spi_use_crc;
|
||||
struct rt_semaphore bus_lock;
|
||||
struct rt_semaphore sem_ack;
|
||||
|
||||
void *private_data;
|
||||
};
|
||||
|
||||
rt_inline void mmcsd_delay_ms(rt_uint32_t ms)
|
||||
{
|
||||
if (ms < 1000 / RT_TICK_PER_SECOND)
|
||||
{
|
||||
rt_thread_delay(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_thread_delay(ms/(1000 / RT_TICK_PER_SECOND));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,730 @@
|
|||
/*
|
||||
* File : sd.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#include "mmcsd_core.h"
|
||||
#include "mmcsd_cmd.h"
|
||||
|
||||
static const rt_uint32_t tran_unit[] = {
|
||||
10000, 100000, 1000000, 10000000,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static const rt_uint8_t tran_value[] = {
|
||||
0, 10, 12, 13, 15, 20, 25, 30,
|
||||
35, 40, 45, 50, 55, 60, 70, 80,
|
||||
};
|
||||
|
||||
static const rt_uint32_t tacc_uint[] = {
|
||||
1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
|
||||
};
|
||||
|
||||
static const rt_uint8_t tacc_value[] = {
|
||||
0, 10, 12, 13, 15, 20, 25, 30,
|
||||
35, 40, 45, 50, 55, 60, 70, 80,
|
||||
};
|
||||
|
||||
rt_inline rt_uint32_t GET_BITS(rt_uint32_t *resp, rt_uint32_t start, rt_uint32_t size)
|
||||
{
|
||||
const rt_int32_t __size = size;
|
||||
const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1;
|
||||
const rt_int32_t __off = 3 - ((start) / 32);
|
||||
const rt_int32_t __shft = (start) & 31;
|
||||
rt_uint32_t __res;
|
||||
|
||||
__res = resp[__off] >> __shft;
|
||||
if (__size + __shft > 32)
|
||||
__res |= resp[__off-1] << ((32 - __shft) % 32);
|
||||
return __res & __mask;
|
||||
}
|
||||
|
||||
static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card)
|
||||
{
|
||||
struct rt_mmcsd_csd *csd = &card->csd;
|
||||
rt_uint32_t *resp = card->resp_csd;
|
||||
|
||||
csd->csd_structure = GET_BITS(resp, 126, 2);
|
||||
|
||||
switch (csd->csd_structure) {
|
||||
case 0:
|
||||
csd->taac = GET_BITS(resp, 112, 8);
|
||||
csd->nsac = GET_BITS(resp, 104, 8);
|
||||
csd->tran_speed = GET_BITS(resp, 96, 8);
|
||||
csd->card_cmd_class = GET_BITS(resp, 84, 12);
|
||||
csd->rd_blk_len = GET_BITS(resp, 80, 4);
|
||||
csd->rd_blk_part = GET_BITS(resp, 79, 1);
|
||||
csd->wr_blk_misalign = GET_BITS(resp, 78, 1);
|
||||
csd->rd_blk_misalign = GET_BITS(resp, 77, 1);
|
||||
csd->dsr_imp = GET_BITS(resp, 76, 1);
|
||||
csd->c_size = GET_BITS(resp, 62, 12);
|
||||
csd->c_size_mult = GET_BITS(resp, 47, 3);
|
||||
csd->r2w_factor = GET_BITS(resp, 26, 3);
|
||||
csd->wr_blk_len = GET_BITS(resp, 22, 4);
|
||||
csd->wr_blk_partial = GET_BITS(resp, 21, 1);
|
||||
csd->csd_crc = GET_BITS(resp, 1, 7);
|
||||
|
||||
card->card_blksize = 1 << csd->rd_blk_len;
|
||||
card->card_capacity = (csd->c_size + 1) << (csd->c_size_mult + 2);
|
||||
card->card_capacity *= card->card_blksize;
|
||||
card->card_capacity >>= 10; /* unit:KB */
|
||||
card->tacc_clks = csd->nsac * 100;
|
||||
card->tacc_ns = (tacc_uint[csd->taac&0x07] * tacc_value[(csd->taac&0x78)>>3] + 9) / 10;
|
||||
card->max_data_rate = tran_unit[csd->tran_speed&0x07] * tran_value[(csd->tran_speed&0x78)>>3];
|
||||
|
||||
#if 0
|
||||
val = GET_BITS(resp, 115, 4);
|
||||
unit = GET_BITS(resp, 112, 3);
|
||||
csd->tacc_ns = (tacc_uint[unit] * tacc_value[val] + 9) / 10;
|
||||
csd->tacc_clks = GET_BITS(resp, 104, 8) * 100;
|
||||
|
||||
val = GET_BITS(resp, 99, 4);
|
||||
unit = GET_BITS(resp, 96, 3);
|
||||
csd->max_data_rate = tran_unit[unit] * tran_value[val];
|
||||
csd->ccc = GET_BITS(resp, 84, 12);
|
||||
|
||||
unit = GET_BITS(resp, 47, 3);
|
||||
val = GET_BITS(resp, 62, 12);
|
||||
csd->device_size = (1 + val) << (unit + 2);
|
||||
|
||||
csd->read_bl_len = GET_BITS(resp, 80, 4);
|
||||
csd->write_bl_len = GET_BITS(resp, 22, 4);
|
||||
csd->r2w_factor = GET_BITS(resp, 26, 3);
|
||||
#endif
|
||||
break;
|
||||
case 1:
|
||||
card->card_type |= CARD_TYPE_SDHC;
|
||||
|
||||
/*This field is fixed to 0Eh, which indicates 1 ms.
|
||||
The host should not use TAAC, NSAC, and R2W_FACTOR
|
||||
to calculate timeout and should uses fixed timeout
|
||||
values for read and write operations*/
|
||||
csd->taac = GET_BITS(resp, 112, 8);
|
||||
csd->nsac = GET_BITS(resp, 104, 8);
|
||||
csd->tran_speed = GET_BITS(resp, 96, 8);
|
||||
csd->card_cmd_class = GET_BITS(resp, 84, 12);
|
||||
csd->rd_blk_len = GET_BITS(resp, 80, 4);
|
||||
csd->rd_blk_part = GET_BITS(resp, 79, 1);
|
||||
csd->wr_blk_misalign = GET_BITS(resp, 78, 1);
|
||||
csd->rd_blk_misalign = GET_BITS(resp, 77, 1);
|
||||
csd->dsr_imp = GET_BITS(resp, 76, 1);
|
||||
csd->c_size = GET_BITS(resp, 48, 22);
|
||||
|
||||
csd->r2w_factor = GET_BITS(resp, 26, 3);
|
||||
csd->wr_blk_len = GET_BITS(resp, 22, 4);
|
||||
csd->wr_blk_partial = GET_BITS(resp, 21, 1);
|
||||
csd->csd_crc = GET_BITS(resp, 1, 7);
|
||||
|
||||
card->card_blksize = 512;
|
||||
card->card_capacity = (csd->c_size + 1) * 512; /* unit:KB */
|
||||
card->tacc_clks = 0;
|
||||
card->tacc_ns = 0;
|
||||
card->max_data_rate = tran_unit[csd->tran_speed&0x07] * tran_value[(csd->tran_speed&0x78)>>3];
|
||||
|
||||
#if 0
|
||||
csd->tacc_ns = 0;
|
||||
csd->tacc_clks = 0;
|
||||
|
||||
val = GET_BITS(resp, 99, 4);
|
||||
unit = GET_BITS(resp, 96, 3);
|
||||
csd->max_data_rate = tran_unit[unit] * tran_value[val];
|
||||
csd->ccc = GET_BITS(resp, 84, 12);
|
||||
|
||||
val = GET_BITS(resp, 48, 22);
|
||||
csd->device_size = (1 + val) << 10;
|
||||
|
||||
csd->read_bl_len = 9;
|
||||
csd->write_bl_len = 9;
|
||||
/* host should not use this factor and should use 250ms for write timeout */
|
||||
csd->r2w_factor = 2;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("unrecognised CSD structure version %d\n", csd->csd_structure);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
rt_kprintf("SD card capacity %d KB\n", card->card_capacity);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_int32_t mmcsd_parse_scr(struct rt_mmcsd_card *card)
|
||||
{
|
||||
struct rt_sd_scr *scr = &card->scr;
|
||||
rt_uint32_t resp[4];
|
||||
|
||||
resp[3] = card->resp_scr[1];
|
||||
resp[2] = card->resp_scr[0];
|
||||
scr->sd_version = GET_BITS(resp, 56, 4);
|
||||
scr->sd_bus_widths = GET_BITS(resp, 48, 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_int32_t err;
|
||||
struct rt_mmcsd_host *host = card->host;
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
struct rt_mmcsd_data data;
|
||||
rt_uint8_t *buf;
|
||||
|
||||
buf = rt_malloc(64);
|
||||
if (!buf)
|
||||
{
|
||||
rt_kprintf("alloc memory failed\n");
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
if (!(card->card_type & CARD_TYPE_SD))
|
||||
goto err;
|
||||
if (card->scr.sd_version < SCR_SPEC_VER_1)
|
||||
goto err;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_SWITCH;
|
||||
cmd.arg = 0x00FFFFF1;
|
||||
cmd.flags = RESP_R1 | CMD_ADTC;
|
||||
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
mmcsd_set_data_timeout(&data, card);
|
||||
|
||||
data.blksize = 64;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = (rt_uint32_t *)buf;
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
if (cmd.err || data.err)
|
||||
{
|
||||
goto err1;
|
||||
}
|
||||
|
||||
if (buf[13] & 0x02)
|
||||
card->hs_max_data_rate = 50000000;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_SWITCH;
|
||||
cmd.arg = 0x80FFFFF1;
|
||||
cmd.flags = RESP_R1 | CMD_ADTC;
|
||||
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
mmcsd_set_data_timeout(&data, card);
|
||||
|
||||
data.blksize = 64;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = (rt_uint32_t *)buf;
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
if (cmd.err || data.err)
|
||||
{
|
||||
goto err1;
|
||||
}
|
||||
|
||||
if ((buf[16] & 0xF) != 1)
|
||||
{
|
||||
rt_kprintf("switching card to high speed failed\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
card->flags |= CARD_MODE_HIGHSPEED;
|
||||
|
||||
err:
|
||||
rt_free(buf);
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
if (cmd.err)
|
||||
{
|
||||
err = cmd.err;
|
||||
}
|
||||
|
||||
if (data.err)
|
||||
{
|
||||
err = data.err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static rt_err_t mmcsd_app_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card)
|
||||
{
|
||||
rt_err_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
cmd.cmd_code = APP_CMD;
|
||||
|
||||
if (card)
|
||||
{
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = RESP_R1 | CMD_AC;
|
||||
}
|
||||
else
|
||||
{
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_R1 | CMD_BCR;
|
||||
}
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 0);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Check that card supported application commands */
|
||||
if (!controller_is_spi(host) && !(cmd.resp[0] & R1_APP_CMD))
|
||||
return -RT_ERROR;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
rt_err_t mmcsd_send_app_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card,
|
||||
struct rt_mmcsd_cmd *cmd, int retry)
|
||||
{
|
||||
struct rt_mmcsd_req req;
|
||||
|
||||
rt_uint32_t i;
|
||||
rt_err_t err;
|
||||
|
||||
err = -RT_ERROR;
|
||||
|
||||
/*
|
||||
* We have to resend MMC_APP_CMD for each attempt so
|
||||
* we cannot use the retries field in mmc_command.
|
||||
*/
|
||||
for (i = 0;i <= retry;i++)
|
||||
{
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
|
||||
err = mmcsd_app_cmd(host, card);
|
||||
if (err)
|
||||
{
|
||||
/* no point in retrying; no APP commands allowed */
|
||||
if (controller_is_spi(host))
|
||||
{
|
||||
if (cmd->resp[0] & R1_SPI_ILLEGAL_COMMAND)
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
|
||||
rt_memset(cmd->resp, 0, sizeof(cmd->resp));
|
||||
|
||||
req.cmd = cmd;
|
||||
//cmd->data = NULL;
|
||||
|
||||
mmcsd_send_request(host, &req);
|
||||
|
||||
err = cmd->err;
|
||||
if (!cmd->err)
|
||||
break;
|
||||
|
||||
/* no point in retrying illegal APP commands */
|
||||
if (controller_is_spi(host))
|
||||
{
|
||||
if (cmd->resp[0] & R1_SPI_ILLEGAL_COMMAND)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
rt_err_t mmcsd_app_set_bus_width(struct rt_mmcsd_card *card, rt_int32_t width)
|
||||
{
|
||||
rt_err_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_APP_SET_BUS_WIDTH;
|
||||
cmd.flags = RESP_R1 | CMD_AC;
|
||||
|
||||
switch (width)
|
||||
{
|
||||
case MMCSD_BUS_WIDTH_1:
|
||||
cmd.arg = MMCSD_BUS_WIDTH_1;
|
||||
break;
|
||||
case MMCSD_BUS_WIDTH_4:
|
||||
cmd.arg = MMCSD_BUS_WIDTH_4;
|
||||
break;
|
||||
default:
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
err = mmcsd_send_app_cmd(card->host, card, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t mmcsd_send_app_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
rt_uint32_t i;
|
||||
rt_err_t err = RT_EOK;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_APP_OP_COND;
|
||||
if (controller_is_spi(host))
|
||||
cmd.arg = ocr & (1 << 30); /* SPI only defines one bit */
|
||||
else
|
||||
cmd.arg = ocr;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R3 | CMD_BCR;
|
||||
|
||||
for (i = 100; i; i--)
|
||||
{
|
||||
err = mmcsd_send_app_cmd(host, RT_NULL, &cmd, 3);
|
||||
if (err)
|
||||
break;
|
||||
|
||||
/* if we're just probing, do a single pass */
|
||||
if (ocr == 0)
|
||||
break;
|
||||
|
||||
/* otherwise wait until reset completes */
|
||||
if (controller_is_spi(host))
|
||||
{
|
||||
if (!(cmd.resp[0] & R1_SPI_IDLE))
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (cmd.resp[0] & CARD_BUSY)
|
||||
break;
|
||||
}
|
||||
|
||||
err = -RT_ETIMEOUT;
|
||||
|
||||
mmcsd_delay_ms(10); //delay 10ms
|
||||
}
|
||||
|
||||
if (rocr && !controller_is_spi(host))
|
||||
*rocr = cmd.resp[0];
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* To support SD 2.0 cards, we must always invoke SD_SEND_IF_COND
|
||||
* before SD_APP_OP_COND. This command will harmlessly fail for
|
||||
* SD 1.0 cards.
|
||||
*/
|
||||
rt_err_t mmcsd_send_if_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
rt_err_t err;
|
||||
rt_uint8_t pattern;
|
||||
|
||||
cmd.cmd_code = SD_SEND_IF_COND;
|
||||
cmd.arg = ((ocr & 0xFF8000) != 0) << 8 | 0xAA;
|
||||
cmd.flags = RESP_SPI_R7 | RESP_R7 | CMD_BCR;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 0);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (controller_is_spi(host))
|
||||
pattern = cmd.resp[1] & 0xFF;
|
||||
else
|
||||
pattern = cmd.resp[0] & 0xFF;
|
||||
|
||||
if (pattern != 0xAA)
|
||||
return -RT_ERROR;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t mmcsd_get_card_addr(struct rt_mmcsd_host *host, rt_uint32_t *rca)
|
||||
{
|
||||
rt_err_t err;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd.cmd_code = SD_SEND_RELATIVE_ADDR;
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_R6 | CMD_BCR;
|
||||
|
||||
err = mmcsd_send_cmd(host, &cmd, 3);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
*rca = cmd.resp[0] >> 16;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
#define be32_to_cpu(x) ((rt_uint32_t)( \
|
||||
(((rt_uint32_t)(x) & (rt_uint32_t)0x000000ffUL) << 24) | \
|
||||
(((rt_uint32_t)(x) & (rt_uint32_t)0x0000ff00UL) << 8) | \
|
||||
(((rt_uint32_t)(x) & (rt_uint32_t)0x00ff0000UL) >> 8) | \
|
||||
(((rt_uint32_t)(x) & (rt_uint32_t)0xff000000UL) >> 24)))
|
||||
|
||||
rt_int32_t mmcsd_get_scr(struct rt_mmcsd_card *card, rt_uint32_t *scr)
|
||||
{
|
||||
rt_int32_t err;
|
||||
struct rt_mmcsd_req req;
|
||||
struct rt_mmcsd_cmd cmd;
|
||||
struct rt_mmcsd_data data;
|
||||
|
||||
err = mmcsd_app_cmd(card->host, card);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
|
||||
rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
|
||||
|
||||
req.cmd = &cmd;
|
||||
req.data = &data;
|
||||
|
||||
cmd.cmd_code = SD_APP_SEND_SCR;
|
||||
cmd.arg = 0;
|
||||
cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
data.blksize = 8;
|
||||
data.blks = 1;
|
||||
data.flags = DATA_DIR_READ;
|
||||
data.buf = scr;
|
||||
|
||||
mmcsd_set_data_timeout(&data, card);
|
||||
|
||||
mmcsd_send_request(card->host, &req);
|
||||
|
||||
if (cmd.err)
|
||||
return cmd.err;
|
||||
if (data.err)
|
||||
return data.err;
|
||||
|
||||
scr[0] = be32_to_cpu(scr[0]);
|
||||
scr[1] = be32_to_cpu(scr[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr)
|
||||
{
|
||||
struct rt_mmcsd_card *card;
|
||||
rt_int32_t err;
|
||||
rt_uint32_t resp[4];
|
||||
rt_uint32_t max_data_rate;
|
||||
|
||||
mmcsd_go_idle(host);
|
||||
|
||||
/*
|
||||
* If SD_SEND_IF_COND indicates an SD 2.0
|
||||
* compliant card and we should set bit 30
|
||||
* of the ocr to indicate that we can handle
|
||||
* block-addressed SDHC cards.
|
||||
*/
|
||||
err = mmcsd_send_if_cond(host, ocr);
|
||||
if (!err)
|
||||
ocr |= 1 << 30;
|
||||
|
||||
err = mmcsd_send_app_op_cond(host, ocr, RT_NULL);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
if (controller_is_spi(host))
|
||||
err = mmcsd_get_cid(host, resp);
|
||||
else
|
||||
err = mmcsd_all_get_cid(host, resp);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
card = rt_malloc(sizeof(struct rt_mmcsd_card));
|
||||
if (!card)
|
||||
{
|
||||
rt_kprintf("malloc card failed\n");
|
||||
err = -RT_ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
rt_memset(card, 0, sizeof(struct rt_mmcsd_card));
|
||||
|
||||
card->card_type = CARD_TYPE_SD;
|
||||
card->host = host;
|
||||
rt_memcpy(card->resp_cid, resp, sizeof(card->resp_cid));
|
||||
|
||||
/*
|
||||
* For native busses: get card RCA and quit open drain mode.
|
||||
*/
|
||||
if (!controller_is_spi(host))
|
||||
{
|
||||
err = mmcsd_get_card_addr(host, &card->rca);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
mmcsd_set_bus_mode(host, MMCSD_BUSMODE_PUSHPULL);
|
||||
}
|
||||
|
||||
err = mmcsd_get_csd(card, card->resp_csd);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
err = mmcsd_parse_csd(card);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
if (!controller_is_spi(host))
|
||||
{
|
||||
err = mmcsd_select_card(card);
|
||||
if (err)
|
||||
goto err1;
|
||||
}
|
||||
|
||||
err = mmcsd_get_scr(card, card->resp_scr);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
mmcsd_parse_scr(card);
|
||||
|
||||
if (controller_is_spi(host))
|
||||
{
|
||||
err = mmcsd_spi_use_crc(host, 1);
|
||||
if (err)
|
||||
goto err1;
|
||||
}
|
||||
|
||||
/*
|
||||
* change SD card to high-speed, only SD2.0 spec
|
||||
*/
|
||||
err = mmcsd_switch(card);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
/* set bus speed */
|
||||
max_data_rate = (unsigned int)-1;
|
||||
|
||||
if (card->flags & CARD_MODE_HIGHSPEED)
|
||||
{
|
||||
if (max_data_rate > card->hs_max_data_rate)
|
||||
max_data_rate = card->hs_max_data_rate;
|
||||
}
|
||||
else if (max_data_rate > card->max_data_rate)
|
||||
{
|
||||
max_data_rate = card->max_data_rate;
|
||||
}
|
||||
|
||||
mmcsd_set_clock(host, max_data_rate);
|
||||
|
||||
/*switch bus width*/
|
||||
if ((host->flags & MMCSD_BUSWIDTH_4) &&
|
||||
(card->scr.sd_bus_widths & SD_SCR_BUS_WIDTH_4))
|
||||
{
|
||||
err = mmcsd_app_set_bus_width(card, MMCSD_BUS_WIDTH_4);
|
||||
if (err)
|
||||
goto err1;
|
||||
|
||||
mmcsd_set_bus_width(host, MMCSD_BUS_WIDTH_4);
|
||||
}
|
||||
|
||||
host->card = card;
|
||||
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
rt_free(card);
|
||||
err:
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Starting point for SD card init.
|
||||
*/
|
||||
rt_int32_t init_sd(struct rt_mmcsd_host *host, rt_uint32_t ocr)
|
||||
{
|
||||
rt_int32_t err;
|
||||
rt_uint32_t current_ocr;
|
||||
/*
|
||||
* We need to get OCR a different way for SPI.
|
||||
*/
|
||||
if (controller_is_spi(host)) {
|
||||
mmcsd_go_idle(host);
|
||||
|
||||
err = mmcsd_spi_read_ocr(host, 0, &ocr);
|
||||
if (err)
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (ocr & VDD_165_195) {
|
||||
rt_kprintf(" SD card claims to support the "
|
||||
"incompletely defined 'low voltage range'. This "
|
||||
"will be ignored.\n");
|
||||
ocr &= ~VDD_165_195;
|
||||
}
|
||||
|
||||
current_ocr = mmcsd_select_voltage(host, ocr);
|
||||
|
||||
/*
|
||||
* Can we support the voltage(s) of the card(s)?
|
||||
*/
|
||||
if (!current_ocr) {
|
||||
err = -RT_ERROR;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Detect and init the card.
|
||||
*/
|
||||
err = mmcsd_sd_init_card(host, current_ocr);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
mmcsd_host_unlock(host);
|
||||
|
||||
err = rt_mmcsd_blk_probe(host->card);
|
||||
if (err)
|
||||
goto remove_card;
|
||||
mmcsd_host_lock(host);
|
||||
|
||||
return 0;
|
||||
|
||||
remove_card:
|
||||
mmcsd_host_lock(host);
|
||||
rt_mmcsd_blk_remove(host->card);
|
||||
rt_free(host->card);
|
||||
host->card = RT_NULL;
|
||||
err:
|
||||
|
||||
rt_kprintf("init SD card failed\n");
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#ifndef __SD_H__
|
||||
#define __SD_H__
|
||||
/*
|
||||
* File : sd.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "mmcsd_host.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
rt_err_t mmcsd_send_if_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
rt_err_t mmcsd_send_app_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr);
|
||||
rt_int32_t init_sd(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue