diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 37924d74c6..5fcb19ceec 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -248,6 +248,18 @@ config ARCH_RISCV_FPU config ARCH_RISCV_VECTOR bool + if ARCH_RISCV_VECTOR + choice + prompt "RISCV Vector Vlen" + default ARCH_VECTOR_VLEN_128 + + config ARCH_VECTOR_VLEN_128 + bool "128" + config ARCH_VECTOR_VLEN_256 + bool "256" + endchoice + endif + config ARCH_RISCV_FPU_S select ARCH_RISCV_FPU bool diff --git a/libcpu/risc-v/common64/stackframe.h b/libcpu/risc-v/common64/stackframe.h index dd87b35aa1..f6311a76fe 100644 --- a/libcpu/risc-v/common64/stackframe.h +++ b/libcpu/risc-v/common64/stackframe.h @@ -16,7 +16,6 @@ #include #include "encoding.h" -#include "ext_context.h" /* bytes of register width */ #ifdef ARCH_CPU_64BIT @@ -30,6 +29,8 @@ #error "Not supported XLEN" #endif +#include "ext_context.h" + /* 33 general register + 1 padding */ #define CTX_GENERAL_REG_NR 34 diff --git a/libcpu/risc-v/t-head/c908/SConscript b/libcpu/risc-v/t-head/c908/SConscript index 5f750ad65f..1f56051d1d 100644 --- a/libcpu/risc-v/t-head/c908/SConscript +++ b/libcpu/risc-v/t-head/c908/SConscript @@ -5,8 +5,8 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -if not GetDepend('ARCH_USING_ASID'): - SrcRemove(src, ['asid.c']) +if GetDepend('ARCH_RISCV_VECTOR'): + CPPPATH += [cwd + '/../../vector/rvv-1.0'] group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) diff --git a/libcpu/risc-v/vector/rvv-1.0/rvv_context.h b/libcpu/risc-v/vector/rvv-1.0/rvv_context.h new file mode 100644 index 0000000000..4466b3aeff --- /dev/null +++ b/libcpu/risc-v/vector/rvv-1.0/rvv_context.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-10 RT-Thread the first version, + * compatible to riscv-v-spec-1.0 + */ +#ifndef __RVV_CONTEXT_1_0_H__ +#define __RVV_CONTEXT_1_0_H__ + +#if defined(ARCH_VECTOR_VLEN_128) + #define CTX_VECTOR_REGS 64 +#elif defined(ARCH_VECTOR_VLEN_256) + #define CTX_VECTOR_REGS 128 +#else +#error "No supported VLEN" +#endif /* VLEN */ + +#define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4) + +#ifdef __ASSEMBLY__ + +/** + * ================================== + * VECTOR EXTENSION + * ================================== + */ + +#define VEC_FRAME_VSTART (0 * REGBYTES) +#define VEC_FRAME_VTYPE (1 * REGBYTES) +#define VEC_FRAME_VL (2 * REGBYTES) +#define VEC_FRAME_VCSR (3 * REGBYTES) +#define VEC_FRAME_V0 (4 * REGBYTES) + +.macro GET_VEC_FRAME_LEN, xreg + csrr \xreg, vlenb + slli \xreg, \xreg, 5 + addi \xreg, \xreg, 4 * REGBYTES +.endm + +/** + * @brief save vector extension hardware state + * + * @param dst register storing bottom of storage block + * + */ +.macro SAVE_VECTOR, dst + mv t1, \dst + + csrr t0, vstart + STORE t0, VEC_FRAME_VSTART(t1) + csrr t0, vtype + STORE t0, VEC_FRAME_VTYPE(t1) + csrr t0, vl + STORE t0, VEC_FRAME_VL(t1) + csrr t0, vcsr + STORE t0, VEC_FRAME_VCSR(t1) + + addi t1, t1, VEC_FRAME_V0 + + // config vector setting, + // t2 is updated to length of a vector group in bytes + VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) + + vse8.v v0, (t1) + add t1, t1, t2 + vse8.v v8, (t1) + add t1, t1, t2 + vse8.v v16, (t1) + add t1, t1, t2 + vse8.v v24, (t1) +.endm + +/** + * @brief restore vector extension hardware states + * + * @param dst register storing bottom of storage block + * + */ +.macro RESTORE_VECTOR, dst + // restore vector registers first since it will modify vector states + mv t0, \dst + addi t1, t0, VEC_FRAME_V0 + + VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) + + vle8.v v0, (t1) + add t1, t1, t2 + vle8.v v8, (t1) + add t1, t1, t2 + vle8.v v16, (t1) + add t1, t1, t2 + vle8.v v24, (t1) + + mv t1, t0 + + LOAD t0, VEC_FRAME_VSTART(t1) + csrw vstart, t0 + LOAD t0, VEC_FRAME_VCSR(t1) + csrw vcsr, t0 + + LOAD t0, VEC_FRAME_VTYPE(t1) + LOAD t3, VEC_FRAME_VL(t1) + VEC_CONFIG_SET_VL_VTYPE(t3, t0) +.endm + +#endif + +#endif /* __RVV_CONTEXT_H__ */ diff --git a/libcpu/risc-v/vector/rvv-1.0/vector_encoding.h b/libcpu/risc-v/vector/rvv-1.0/vector_encoding.h new file mode 100644 index 0000000000..022beb0603 --- /dev/null +++ b/libcpu/risc-v/vector/rvv-1.0/vector_encoding.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-10 RT-Thread the first version, + * compatible to riscv-v-spec-1.0 + */ + +#ifndef __VECTOR_ENCODING_1_0_H__ +#define __VECTOR_ENCODING_1_0_H__ + +/* mstatus/sstatus */ +#define MSTATUS_VS 0x00000600 +#define SSTATUS_VS 0x00000600 /* Vector Status */ +#define SSTATUS_VS_INITIAL 0x00000200 +#define SSTATUS_VS_CLEAN 0x00000400 +#define SSTATUS_VS_DIRTY 0x00000600 + +#ifdef __ASSEMBLY__ + +/** + * assembler names used for vset{i}vli vtypei immediate + */ + +#define VEC_IMM_SEW_8 e8 +#define VEC_IMM_SEW_16 e16 +#define VEC_IMM_SEW_32 e32 +#define VEC_IMM_SEW_64 e64 +/* group setting, encoding by multiplier */ +#define VEC_IMM_LMUL_F8 mf8 +#define VEC_IMM_LMUL_F4 mf4 +#define VEC_IMM_LMUL_F2 mf2 +#define VEC_IMM_LMUL_1 m1 +#define VEC_IMM_LMUL_2 m2 +#define VEC_IMM_LMUL_4 m4 +#define VEC_IMM_LMUL_8 m8 +/* TAIL & MASK agnostic bits */ +#define VEC_IMM_TAIL_AGNOSTIC ta +#define VEC_IMM_MASK_AGNOSTIC ma +#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC +#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC +#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC + +/** + * configuration setting instruction + */ +#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype +#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype + +#endif + +#endif /* __VECTOR_ENCODING_H__ */