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refactor: improve adc driver 

1. Calibration is required when ADC is enabled, and calibration is not required when enabling
ADC.
2. format code style
This commit is contained in:
192.168.1.134 2021-10-27 09:57:55 +08:00
parent 291bbac24f
commit 48ffde55a2
12 changed files with 274 additions and 273 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

145
bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
View File

@ -44,63 +44,63 @@ static rt_uint32_t n32_adc_get_channel(rt_uint32_t channel)
switch (channel) switch (channel)
{ {
case 0: case 0:
n32_channel = ADC_CH_0; n32_channel = ADC_CH_0;
break; break;
case 1: case 1:
n32_channel = ADC_CH_1; n32_channel = ADC_CH_1;
break; break;
case 2: case 2:
n32_channel = ADC_CH_2; n32_channel = ADC_CH_2;
break; break;
case 3: case 3:
n32_channel = ADC_CH_3; n32_channel = ADC_CH_3;
break; break;
case 4: case 4:
n32_channel = ADC_CH_4; n32_channel = ADC_CH_4;
break; break;
case 5: case 5:
n32_channel = ADC_CH_5; n32_channel = ADC_CH_5;
break; break;
case 6: case 6:
n32_channel = ADC_CH_6; n32_channel = ADC_CH_6;
break; break;
case 7: case 7:
n32_channel = ADC_CH_7; n32_channel = ADC_CH_7;
break; break;
case 8: case 8:
n32_channel = ADC_CH_8; n32_channel = ADC_CH_8;
break; break;
case 9: case 9:
n32_channel = ADC_CH_9; n32_channel = ADC_CH_9;
break; break;
case 10: case 10:
n32_channel = ADC_CH_10; n32_channel = ADC_CH_10;
break; break;
case 11: case 11:
n32_channel = ADC_CH_11; n32_channel = ADC_CH_11;
break; break;
case 12: case 12:
n32_channel = ADC_CH_12; n32_channel = ADC_CH_12;
break; break;
case 13: case 13:
n32_channel = ADC_CH_13; n32_channel = ADC_CH_13;
break; break;
case 14: case 14:
n32_channel = ADC_CH_14; n32_channel = ADC_CH_14;
break; break;
case 15: case 15:
n32_channel = ADC_CH_15; n32_channel = ADC_CH_15;
break; break;
case 16: case 16:
n32_channel = ADC_CH_16; n32_channel = ADC_CH_16;
break; break;
case 17: case 17:
n32_channel = ADC_CH_17; n32_channel = ADC_CH_17;
break; break;
case 18: case 18:
n32_channel = ADC_CH_18; n32_channel = ADC_CH_18;
break; break;
} }
return n32_channel; return n32_channel;
@ -124,27 +124,23 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
ADC_InitStructure.ChsNumber = 1; ADC_InitStructure.ChsNumber = 1;
ADC_Init(n32_adc_handler, &ADC_InitStructure); ADC_Init(n32_adc_handler, &ADC_InitStructure);
/* ADCx regular channels configuration */
ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5);
if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2)) if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2))
&& ((n32_adc_get_channel(channel) == ADC_CH_16) || (n32_adc_get_channel(channel) == ADC_CH_18))) && ((n32_adc_get_channel(channel) == ADC_CH_16)
|| (n32_adc_get_channel(channel) == ADC_CH_18)))
{ {
ADC_EnableTempSensorVrefint(ENABLE); ADC_EnableTempSensorVrefint(ENABLE);
} }
/* Enable ADCx */
ADC_Enable(n32_adc_handler, ENABLE);
/* Start ADCx calibration */
ADC_StartCalibration(n32_adc_handler);
/* Check the end of ADCx calibration */
while(ADC_GetCalibrationStatus(n32_adc_handler));
if (enabled) if (enabled)
{ {
/* Enable ADC1 */ /* Enable ADC1 */
ADC_Enable(n32_adc_handler, ENABLE); ADC_Enable(n32_adc_handler, ENABLE);
/*Check ADC Ready*/
while (ADC_GetFlagStatusNew(n32_adc_handler, ADC_FLAG_RDY) == RESET);
/* Start ADCx calibration */
ADC_StartCalibration(n32_adc_handler);
/* Check the end of ADCx calibration */
while (ADC_GetCalibrationStatus(n32_adc_handler));
} }
else else
{ {
@ -164,11 +160,16 @@ static rt_err_t n32_get_adc_value(struct rt_adc_device *device, rt_uint32_t chan
n32_adc_handler = device->parent.user_data; n32_adc_handler = device->parent.user_data;
/* ADCx regular channels configuration */
ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5);
/* Start ADCx Software Conversion */ /* Start ADCx Software Conversion */
ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE); ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE);
/* Wait for the ADC to convert */ /* Wait for the ADC to convert */
while(ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET); while (ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET);
ADC_ClearFlag(n32_adc_handler, ADC_FLAG_ENDC);
/* get ADC value */ /* get ADC value */
*value = ADC_GetDat(n32_adc_handler); *value = ADC_GetDat(n32_adc_handler);
@ -191,8 +192,8 @@ static int rt_hw_adc_init(void)
{ {
/* register ADC device */ /* register ADC device */
if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device, if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device,
n32_adc_obj[i].name, &at_adc_ops, n32_adc_obj[i].name, &at_adc_ops,
n32_adc_obj[i].ADC_Handler) == RT_EOK) n32_adc_obj[i].ADC_Handler) == RT_EOK)
{ {
LOG_D("%s register success", n32_adc_obj[i].name); LOG_D("%s register success", n32_adc_obj[i].name);
} }

10
bsp/n32g452xx/Libraries/rt_drivers/drv_common.c
View File

@ -12,11 +12,11 @@
#include "board.h" #include "board.h"
#ifdef RT_USING_SERIAL #ifdef RT_USING_SERIAL
#ifdef RT_USING_SERIAL_V2 #ifdef RT_USING_SERIAL_V2
#include "drv_usart_v2.h" #include "drv_usart_v2.h"
#else #else
#include "drv_usart.h" #include "drv_usart.h"
#endif #endif
#endif #endif
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH

2
bsp/n32g452xx/Libraries/rt_drivers/drv_common.h
View File

@ -14,7 +14,7 @@
#include <rtthread.h> #include <rtthread.h>
#include <rthw.h> #include <rthw.h>
#ifdef RT_USING_DEVICE #ifdef RT_USING_DEVICE
#include <rtdevice.h> #include <rtdevice.h>
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

10
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c
View File

@ -15,7 +15,7 @@
#include "drv_flash.h" #include "drv_flash.h"
#if defined(PKG_USING_FAL) #if defined(PKG_USING_FAL)
#include "fal.h" #include "fal.h"
#endif #endif
//#define DRV_DEBUG //#define DRV_DEBUG
@ -147,11 +147,11 @@ int n32_flash_erase(rt_uint32_t addr, size_t size)
return -RT_EINVAL; return -RT_EINVAL;
} }
while(addr < end_addr) while (addr < end_addr)
{ {
page_addr = get_page(addr); page_addr = get_page(addr);
if(FLASH_EraseOnePage(page_addr) != FLASH_COMPL) if (FLASH_EraseOnePage(page_addr) != FLASH_COMPL)
{ {
result = -RT_ERROR; result = -RT_ERROR;
goto __exit; goto __exit;
@ -160,10 +160,10 @@ int n32_flash_erase(rt_uint32_t addr, size_t size)
addr += FLASH_PAGE_SIZE; addr += FLASH_PAGE_SIZE;
} }
FLASH_Lock(); FLASH_Lock();
__exit: __exit:
if(result != RT_EOK) if (result != RT_EOK)
{ {
return result; return result;
} }

86
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
View File

@ -573,9 +573,9 @@ void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{ {
int i; int i;
for(i = 0; i < 32; i++) for (i = 0; i < 32; i++)
{ {
if((0x01 << i) == bit) if ((0x01 << i) == bit)
{ {
return i; return i;
} }
@ -585,7 +585,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{ {
rt_int32_t mapindex = bit2bitno(pinbit); rt_int32_t mapindex = bit2bitno(pinbit);
if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{ {
return RT_NULL; return RT_NULL;
} }
@ -604,22 +604,22 @@ rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
return -RT_ENOSYS; return -RT_ENOSYS;
} }
irqindex = bit2bitno(index->pin); irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{ {
return -RT_ENOSYS; return -RT_ENOSYS;
} }
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == pin && if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr && pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode && pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args pin_irq_hdr_tab[irqindex].args == args
) )
{ {
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
return RT_EOK; return RT_EOK;
} }
if(pin_irq_hdr_tab[irqindex].pin != -1) if (pin_irq_hdr_tab[irqindex].pin != -1)
{ {
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
return -RT_EBUSY; return -RT_EBUSY;
@ -644,13 +644,13 @@ rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
return -RT_ENOSYS; return -RT_ENOSYS;
} }
irqindex = bit2bitno(index->pin); irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{ {
return -RT_ENOSYS; return -RT_ENOSYS;
} }
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1) if (pin_irq_hdr_tab[irqindex].pin == -1)
{ {
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
return RT_EOK; return RT_EOK;
@ -679,15 +679,15 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
{ {
return -RT_ENOSYS; return -RT_ENOSYS;
} }
if(enabled == PIN_IRQ_ENABLE) if (enabled == PIN_IRQ_ENABLE)
{ {
irqindex = bit2bitno(index->pin); irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{ {
return -RT_ENOSYS; return -RT_ENOSYS;
} }
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1) if (pin_irq_hdr_tab[irqindex].pin == -1)
{ {
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
return -RT_ENOSYS; return -RT_ENOSYS;
@ -701,35 +701,35 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure); GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno; NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
GPIO_ConfigEXTILine(index->port_source, index->pin_source); GPIO_ConfigEXTILine(index->port_source, index->pin_source);
EXTI_InitStructure.EXTI_Line = irqmap->irqbit; EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
switch(pin_irq_hdr_tab[irqindex].mode) switch (pin_irq_hdr_tab[irqindex].mode)
{ {
case PIN_IRQ_MODE_RISING: case PIN_IRQ_MODE_RISING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break; break;
case PIN_IRQ_MODE_FALLING: case PIN_IRQ_MODE_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break; break;
case PIN_IRQ_MODE_RISING_FALLING: case PIN_IRQ_MODE_RISING_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break; break;
} }
EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_InitStructure); EXTI_InitPeripheral(&EXTI_InitStructure);
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
else if(enabled == PIN_IRQ_DISABLE) else if (enabled == PIN_IRQ_DISABLE)
{ {
irqmap = get_pin_irq_map(index->pin); irqmap = get_pin_irq_map(index->pin);
if(irqmap == RT_NULL) if (irqmap == RT_NULL)
{ {
return -RT_ENOSYS; return -RT_ENOSYS;
} }
@ -768,7 +768,7 @@ INIT_BOARD_EXPORT(n32_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno) rt_inline void pin_irq_hdr(int irqno)
{ {
EXTI_ClrITPendBit(pin_irq_map[irqno].irqbit); EXTI_ClrITPendBit(pin_irq_map[irqno].irqbit);
if(pin_irq_hdr_tab[irqno].hdr) if (pin_irq_hdr_tab[irqno].hdr)
{ {
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
} }
@ -817,23 +817,23 @@ void EXTI9_5_IRQHandler(void)
{ {
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_LINE5) != RESET) if (EXTI_GetITStatus(EXTI_LINE5) != RESET)
{ {
pin_irq_hdr(5); pin_irq_hdr(5);
} }
if(EXTI_GetITStatus(EXTI_LINE6) != RESET) if (EXTI_GetITStatus(EXTI_LINE6) != RESET)
{ {
pin_irq_hdr(6); pin_irq_hdr(6);
} }
if(EXTI_GetITStatus(EXTI_LINE7) != RESET) if (EXTI_GetITStatus(EXTI_LINE7) != RESET)
{ {
pin_irq_hdr(7); pin_irq_hdr(7);
} }
if(EXTI_GetITStatus(EXTI_LINE8) != RESET) if (EXTI_GetITStatus(EXTI_LINE8) != RESET)
{ {
pin_irq_hdr(8); pin_irq_hdr(8);
} }
if(EXTI_GetITStatus(EXTI_LINE9) != RESET) if (EXTI_GetITStatus(EXTI_LINE9) != RESET)
{ {
pin_irq_hdr(9); pin_irq_hdr(9);
} }
@ -844,27 +844,27 @@ void EXTI15_10_IRQHandler(void)
{ {
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_LINE10) != RESET) if (EXTI_GetITStatus(EXTI_LINE10) != RESET)
{ {
pin_irq_hdr(10); pin_irq_hdr(10);
} }
if(EXTI_GetITStatus(EXTI_LINE11) != RESET) if (EXTI_GetITStatus(EXTI_LINE11) != RESET)
{ {
pin_irq_hdr(11); pin_irq_hdr(11);
} }
if(EXTI_GetITStatus(EXTI_LINE12) != RESET) if (EXTI_GetITStatus(EXTI_LINE12) != RESET)
{ {
pin_irq_hdr(12); pin_irq_hdr(12);
} }
if(EXTI_GetITStatus(EXTI_LINE13) != RESET) if (EXTI_GetITStatus(EXTI_LINE13) != RESET)
{ {
pin_irq_hdr(13); pin_irq_hdr(13);
} }
if(EXTI_GetITStatus(EXTI_LINE14) != RESET) if (EXTI_GetITStatus(EXTI_LINE14) != RESET)
{ {
pin_irq_hdr(14); pin_irq_hdr(14);
} }
if(EXTI_GetITStatus(EXTI_LINE15) != RESET) if (EXTI_GetITStatus(EXTI_LINE15) != RESET)
{ {
pin_irq_hdr(15); pin_irq_hdr(15);
} }

52
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c
View File

@ -82,7 +82,7 @@ enum
struct n32_hwtimer struct n32_hwtimer
{ {
rt_hwtimer_t time_device; rt_hwtimer_t time_device;
TIM_Module* tim_handle; TIM_Module *tim_handle;
IRQn_Type tim_irqn; IRQn_Type tim_irqn;
char *name; char *name;
}; };
@ -198,7 +198,7 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
TIM_ConfigInt(tim, TIM_INT_UPDATE ,ENABLE); TIM_ConfigInt(tim, TIM_INT_UPDATE, ENABLE);
TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE); TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE);
LOG_D("%s init success", tim_device->name); LOG_D("%s init success", tim_device->name);
@ -270,29 +270,29 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
tim = (TIM_Module *)timer->parent.user_data; tim = (TIM_Module *)timer->parent.user_data;
switch(cmd) switch (cmd)
{ {
case HWTIMER_CTRL_FREQ_SET: case HWTIMER_CTRL_FREQ_SET:
{ {
rt_uint32_t freq; rt_uint32_t freq;
rt_uint16_t val; rt_uint16_t val;
/* set timer frequence */ /* set timer frequence */
freq = *((rt_uint32_t *)arg); freq = *((rt_uint32_t *)arg);
/* time init */ /* time init */
RCC_GetClocksFreqValue(&RCC_ClockStruct); RCC_GetClocksFreqValue(&RCC_ClockStruct);
val = RCC_ClockStruct.SysclkFreq / freq; val = RCC_ClockStruct.SysclkFreq / freq;
TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE); TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE);
} }
break; break;
default: default:
{ {
result = -RT_ENOSYS; result = -RT_ENOSYS;
} }
break; break;
} }
return result; return result;
@ -314,7 +314,7 @@ void TIM2_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device);
@ -332,7 +332,7 @@ void TIM3_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device);
@ -350,7 +350,7 @@ void TIM4_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device);
@ -368,7 +368,7 @@ void TIM5_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device);
@ -386,7 +386,7 @@ void TIM6_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device);
@ -404,7 +404,7 @@ void TIM7_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
if(TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET) if (TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET)
{ {
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device); rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device);

8
bsp/n32g452xx/Libraries/rt_drivers/drv_log.h
View File

@ -13,15 +13,15 @@
*/ */
#ifndef LOG_TAG #ifndef LOG_TAG
#define DBG_TAG "drv" #define DBG_TAG "drv"
#else #else
#define DBG_TAG LOG_TAG #define DBG_TAG LOG_TAG
#endif /* LOG_TAG */ #endif /* LOG_TAG */
#ifdef DRV_DEBUG #ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG #define DBG_LVL DBG_LOG
#else #else
#define DBG_LVL DBG_INFO #define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */ #endif /* DRV_DEBUG */
#include <rtdbg.h> #include <rtdbg.h>

76
bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
View File

@ -12,10 +12,10 @@
#include "drv_pwm.h" #include "drv_pwm.h"
#ifdef RT_USING_PWM #ifdef RT_USING_PWM
#if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \ #if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
!defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4)
#error "Please define at least one BSP_USING_TIMx_CHx" #error "Please define at least one BSP_USING_TIMx_CHx"
#endif #endif
#endif /* RT_USING_PWM */ #endif /* RT_USING_PWM */
#define DRV_DEBUG #define DRV_DEBUG
@ -28,7 +28,7 @@ struct rt_device_pwm pwm_device;
struct n32_pwm struct n32_pwm
{ {
struct rt_device_pwm pwm_device; struct rt_device_pwm pwm_device;
TIM_Module* tim_handle; TIM_Module *tim_handle;
rt_uint8_t channel; rt_uint8_t channel;
char *name; char *name;
}; };
@ -58,45 +58,45 @@ static struct rt_pwm_ops drv_ops =
drv_pwm_control drv_pwm_control
}; };
static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable) static rt_err_t drv_pwm_enable(TIM_Module *TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{ {
/* Get the value of channel */ /* Get the value of channel */
rt_uint32_t channel = configuration->channel; rt_uint32_t channel = configuration->channel;
if (!enable) if (!enable)
{ {
if(channel == 1) if (channel == 1)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
} }
else if(channel == 2) else if (channel == 2)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
} }
else if(channel == 3) else if (channel == 3)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
} }
else if(channel == 4) else if (channel == 4)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
} }
} }
else else
{ {
if(channel == 1) if (channel == 1)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
} }
else if(channel == 2) else if (channel == 2)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
} }
else if(channel == 3) else if (channel == 3)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
} }
else if(channel == 4) else if (channel == 4)
{ {
TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE); TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
} }
@ -107,7 +107,7 @@ static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *co
return RT_EOK; return RT_EOK;
} }
static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
{ {
RCC_ClocksType RCC_Clockstruct; RCC_ClocksType RCC_Clockstruct;
rt_uint32_t ar, div, cc1, cc2, cc3, cc4; rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
@ -128,19 +128,19 @@ static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *confi
/* Convert nanosecond to frequency and duty cycle. */ /* Convert nanosecond to frequency and duty cycle. */
tim_clock /= 1000000UL; tim_clock /= 1000000UL;
configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock; configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 1) if (channel == 1)
configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock; configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 2) if (channel == 2)
configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock; configuration->pulse = (cc2 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 3) if (channel == 3)
configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock; configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 4) if (channel == 4)
configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock; configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
return RT_EOK; return RT_EOK;
} }
static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
{ {
/* Init timer pin and enable clock */ /* Init timer pin and enable clock */
n32_msp_tim_init(TIMx); n32_msp_tim_init(TIMx);
@ -155,7 +155,7 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi
} }
else else
{ {
if (1 == (RCC_Clock.HclkFreq/RCC_Clock.Pclk1Freq)) if (1 == (RCC_Clock.HclkFreq / RCC_Clock.Pclk1Freq))
input_clock = RCC_Clock.Pclk1Freq; input_clock = RCC_Clock.Pclk1Freq;
else else
input_clock = RCC_Clock.Pclk1Freq * 2; input_clock = RCC_Clock.Pclk1Freq * 2;
@ -186,22 +186,22 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi
TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH; TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
rt_uint32_t channel = configuration->channel; rt_uint32_t channel = configuration->channel;
if(channel == 1) if (channel == 1)
{ {
TIM_InitOc1(TIMx, &TIM_OCInitStructure); TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
} }
else if(channel == 2) else if (channel == 2)
{ {
TIM_InitOc2(TIMx, &TIM_OCInitStructure); TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
} }
else if(channel == 3) else if (channel == 3)
{ {
TIM_InitOc3(TIMx, &TIM_OCInitStructure); TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
} }
else if(channel == 4) else if (channel == 4)
{ {
TIM_InitOc4(TIMx, &TIM_OCInitStructure); TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
@ -220,16 +220,16 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
switch (cmd) switch (cmd)
{ {
case PWM_CMD_ENABLE: case PWM_CMD_ENABLE:
return drv_pwm_enable(TIMx, configuration, RT_TRUE); return drv_pwm_enable(TIMx, configuration, RT_TRUE);
case PWM_CMD_DISABLE: case PWM_CMD_DISABLE:
return drv_pwm_enable(TIMx, configuration, RT_FALSE); return drv_pwm_enable(TIMx, configuration, RT_FALSE);
case PWM_CMD_SET: case PWM_CMD_SET:
return drv_pwm_set(TIMx, configuration); return drv_pwm_set(TIMx, configuration);
case PWM_CMD_GET: case PWM_CMD_GET:
return drv_pwm_get(TIMx, configuration); return drv_pwm_get(TIMx, configuration);
default: default:
return RT_EINVAL; return RT_EINVAL;
} }
} }
@ -238,9 +238,9 @@ static int rt_hw_pwm_init(void)
int i = 0; int i = 0;
int result = RT_EOK; int result = RT_EOK;
for(i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++) for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
{ {
if(rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK) if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
{ {
LOG_D("%s register success", n32_pwm_obj[i].name); LOG_D("%s register success", n32_pwm_obj[i].name);
} }

22
bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
View File

@ -17,8 +17,8 @@
#include <drv_log.h> #include <drv_log.h>
#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) #if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
#error "Please define at least one BSP_USING_I2Cx" #error "Please define at least one BSP_USING_I2Cx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif #endif
static const struct n32_soft_i2c_config soft_i2c_config[] = static const struct n32_soft_i2c_config soft_i2c_config[] =
@ -46,7 +46,7 @@ static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0
*/ */
static void n32_i2c_gpio_init(struct n32_i2c *i2c) static void n32_i2c_gpio_init(struct n32_i2c *i2c)
{ {
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data; struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)i2c->ops.data;
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
@ -63,7 +63,7 @@ static void n32_i2c_gpio_init(struct n32_i2c *i2c)
*/ */
static void n32_set_sda(void *data, rt_int32_t state) static void n32_set_sda(void *data, rt_int32_t state)
{ {
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
if (state) if (state)
{ {
rt_pin_write(cfg->sda, PIN_HIGH); rt_pin_write(cfg->sda, PIN_HIGH);
@ -82,7 +82,7 @@ static void n32_set_sda(void *data, rt_int32_t state)
*/ */
static void n32_set_scl(void *data, rt_int32_t state) static void n32_set_scl(void *data, rt_int32_t state)
{ {
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
if (state) if (state)
{ {
rt_pin_write(cfg->scl, PIN_HIGH); rt_pin_write(cfg->scl, PIN_HIGH);
@ -100,7 +100,7 @@ static void n32_set_scl(void *data, rt_int32_t state)
*/ */
static rt_int32_t n32_get_sda(void *data) static rt_int32_t n32_get_sda(void *data)
{ {
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
return rt_pin_read(cfg->sda); return rt_pin_read(cfg->sda);
} }
@ -111,7 +111,7 @@ static rt_int32_t n32_get_sda(void *data)
*/ */
static rt_int32_t n32_get_scl(void *data) static rt_int32_t n32_get_scl(void *data)
{ {
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
return rt_pin_read(cfg->scl); return rt_pin_read(cfg->scl);
} }
/** /**
@ -199,7 +199,7 @@ int rt_hw_i2c_init(void)
for (int i = 0; i < obj_num; i++) for (int i = 0; i < obj_num; i++)
{ {
i2c_obj[i].ops = n32_bit_ops_default; i2c_obj[i].ops = n32_bit_ops_default;
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops;
n32_i2c_gpio_init(&i2c_obj[i]); n32_i2c_gpio_init(&i2c_obj[i]);
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
@ -207,9 +207,9 @@ int rt_hw_i2c_init(void)
n32_i2c_bus_unlock(&soft_i2c_config[i]); n32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name, soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl, soft_i2c_config[i].scl,
soft_i2c_config[i].sda); soft_i2c_config[i].sda);
} }
return RT_EOK; return RT_EOK;

62
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
View File

@ -51,7 +51,7 @@ static void DMA_Configuration(struct rt_serial_device *serial);
static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{ {
struct n32_uart* uart; struct n32_uart *uart;
USART_InitType USART_InitStructure; USART_InitType USART_InitStructure;
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
@ -102,14 +102,14 @@ static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct seria
/* Enable USART */ /* Enable USART */
USART_Enable(uart->uart_device, ENABLE); USART_Enable(uart->uart_device, ENABLE);
USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE|USART_FLAG_TXC); USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE | USART_FLAG_TXC);
return RT_EOK; return RT_EOK;
} }
static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{ {
struct n32_uart* uart; struct n32_uart *uart;
rt_uint32_t ctrl_arg = (rt_uint32_t)(arg); rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
@ -117,34 +117,34 @@ static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void
switch (cmd) switch (cmd)
{ {
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_DISABLE_IRQ(uart->irq);
/* disable interrupt */ /* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT: USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE);
/* disable rx irq */ break;
UART_DISABLE_IRQ(uart->irq); /* enable interrupt */
/* disable interrupt */ case RT_DEVICE_CTRL_SET_INT:
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE); /* enable rx irq */
break; UART_ENABLE_IRQ(uart->irq);
/* enable interrupt */ /* enable interrupt */
case RT_DEVICE_CTRL_SET_INT: USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE);
/* enable rx irq */ break;
UART_ENABLE_IRQ(uart->irq); /* USART config */
/* enable interrupt */ case RT_DEVICE_CTRL_CONFIG :
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE); if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
break; {
/* USART config */ DMA_Configuration(serial);
case RT_DEVICE_CTRL_CONFIG : }
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) break;
{
DMA_Configuration(serial);
}
break;
} }
return RT_EOK; return RT_EOK;
} }
static int n32_uart_putc(struct rt_serial_device *serial, char c) static int n32_uart_putc(struct rt_serial_device *serial, char c)
{ {
struct n32_uart* uart; struct n32_uart *uart;
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
uart = (struct n32_uart *)serial->parent.user_data; uart = (struct n32_uart *)serial->parent.user_data;
@ -171,7 +171,7 @@ static int n32_uart_putc(struct rt_serial_device *serial, char c)
static int n32_uart_getc(struct rt_serial_device *serial) static int n32_uart_getc(struct rt_serial_device *serial)
{ {
int ch; int ch;
struct n32_uart* uart; struct n32_uart *uart;
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
uart = (struct n32_uart *)serial->parent.user_data; uart = (struct n32_uart *)serial->parent.user_data;
@ -250,23 +250,23 @@ static void uart_isr(struct rt_serial_device *serial)
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
if(USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET) if (USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET)
{ {
if(USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET) if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET)
{ {
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
} }
/* clear interrupt */ /* clear interrupt */
USART_ClrIntPendingBit(uart->uart_device, USART_INT_RXDNE); USART_ClrIntPendingBit(uart->uart_device, USART_INT_RXDNE);
} }
if(USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET) if (USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET)
{ {
dma_uart_rx_idle_isr(serial); dma_uart_rx_idle_isr(serial);
} }
if (USART_GetIntStatus(uart->uart_device, USART_INT_TXC) != RESET) if (USART_GetIntStatus(uart->uart_device, USART_INT_TXC) != RESET)
{ {
/* clear interrupt */ /* clear interrupt */
if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
{ {
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
} }
@ -443,7 +443,7 @@ void DMA2_Channel3_IRQHandler(void)
} }
#endif /* BSP_USING_UART4 */ #endif /* BSP_USING_UART4 */
static void NVIC_Configuration(struct n32_uart* uart) static void NVIC_Configuration(struct n32_uart *uart)
{ {
NVIC_InitType NVIC_InitStructure; NVIC_InitType NVIC_InitStructure;
@ -473,7 +473,7 @@ static void DMA_Configuration(struct rt_serial_device *serial)
/* rx dma config */ /* rx dma config */
DMA_DeInit(uart->dma.rx_ch); DMA_DeInit(uart->dma.rx_ch);
DMA_InitStructure.PeriphAddr = (uint32_t)&(uart->uart_device->DAT); DMA_InitStructure.PeriphAddr = (uint32_t) & (uart->uart_device->DAT);
DMA_InitStructure.MemAddr = (uint32_t)(rx_fifo->buffer); DMA_InitStructure.MemAddr = (uint32_t)(rx_fifo->buffer);
DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC;
DMA_InitStructure.BufSize = serial->config.bufsz; DMA_InitStructure.BufSize = serial->config.bufsz;
@ -500,7 +500,7 @@ static void DMA_Configuration(struct rt_serial_device *serial)
int rt_hw_usart_init(void) int rt_hw_usart_init(void)
{ {
struct n32_uart* uart; struct n32_uart *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#if defined(BSP_USING_UART1) #if defined(BSP_USING_UART1)

2
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
View File

@ -15,7 +15,7 @@
#include <board.h> #include <board.h>
#ifdef BSP_USING_SRAM #ifdef BSP_USING_SRAM
#include "drv_sram.h" #include "drv_sram.h"
#endif #endif
/** /**
* @brief This function is executed in case of error occurrence. * @brief This function is executed in case of error occurrence.

72
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
View File

@ -23,7 +23,7 @@ void n32_msp_usart_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_UART1 #ifdef BSP_USING_UART1
if(USART1 == USARTx) if (USART1 == USARTx)
{ {
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -37,7 +37,7 @@ void n32_msp_usart_init(void *Instance)
} }
#endif #endif
#ifdef BSP_USING_UART2 #ifdef BSP_USING_UART2
if(USART2 == USARTx) if (USART2 == USARTx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -51,7 +51,7 @@ void n32_msp_usart_init(void *Instance)
} }
#endif #endif
#ifdef BSP_USING_UART3 #ifdef BSP_USING_UART3
if(USART3 == USARTx) if (USART3 == USARTx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -65,7 +65,7 @@ void n32_msp_usart_init(void *Instance)
} }
#endif #endif
#ifdef BSP_USING_UART4 #ifdef BSP_USING_UART4
if(UART4 == USARTx) if (UART4 == USARTx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -91,7 +91,7 @@ void n32_msp_spi_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_SPI1 #ifdef BSP_USING_SPI1
if(SPI1 == SPIx) if (SPI1 == SPIx)
{ {
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -108,7 +108,7 @@ void n32_msp_spi_init(void *Instance)
} }
#endif #endif
#ifdef BSP_USING_SPI2 #ifdef BSP_USING_SPI2
if(SPI2 == SPIx) if (SPI2 == SPIx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -137,7 +137,7 @@ void n32_msp_sdio_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStructure); GPIO_InitStruct(&GPIO_InitCtlStructure);
GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
if(SDIO == SDIOx) if (SDIO == SDIOx)
{ {
/* if used dma ... */ /* if used dma ... */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE); RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE);
@ -162,7 +162,7 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStructure); GPIO_InitStruct(&GPIO_InitCtlStructure);
TIM_Module *TIMx = (TIM_Module *)Instance; TIM_Module *TIMx = (TIM_Module *)Instance;
if(TIMx == TIM1) if (TIMx == TIM1)
{ {
/* TIM1 clock enable */ /* TIM1 clock enable */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
@ -177,7 +177,7 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
} }
if(TIMx == TIM2) if (TIMx == TIM2)
{ {
/* TIM2 clock enable */ /* TIM2 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE);
@ -192,12 +192,12 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
} }
if(TIMx == TIM3) if (TIMx == TIM3)
{ {
/* TIM3 clock enable */ /* TIM3 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
/* GPIOA clock enable */ /* GPIOA clock enable */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA|RCC_APB2_PERIPH_GPIOB, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7; GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
@ -218,15 +218,15 @@ void n32_msp_adc_init(void *Instance)
ADC_Module *ADCx = (ADC_Module *)Instance; ADC_Module *ADCx = (ADC_Module *)Instance;
#ifdef BSP_USING_ADC1 #ifdef BSP_USING_ADC1
if(ADCx == ADC1) if (ADCx == ADC1)
{ {
/* ADC1 & GPIO clock enable */ /* ADC1 & GPIO clock enable */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE); RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
/* Configure ADC Channel as analog input */ /* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; GPIO_InitCtlStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz; GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN; GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct); GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
@ -234,11 +234,11 @@ void n32_msp_adc_init(void *Instance)
#endif #endif
#ifdef BSP_USING_ADC2 #ifdef BSP_USING_ADC2
if(ADCx == ADC2) if (ADCx == ADC2)
{ {
/* ADC2 & GPIO clock enable */ /* ADC2 & GPIO clock enable */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE); RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
/* Configure ADC Channel as analog input */ /* Configure ADC Channel as analog input */
@ -257,7 +257,7 @@ void n32_msp_hwtim_init(void *Instance)
TIM_Module *TIMx = (TIM_Module *)Instance; TIM_Module *TIMx = (TIM_Module *)Instance;
#ifdef BSP_USING_HWTIM3 #ifdef BSP_USING_HWTIM3
if(TIMx == TIM3) if (TIMx == TIM3)
{ {
/* TIM3 clock enable */ /* TIM3 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
@ -265,7 +265,7 @@ void n32_msp_hwtim_init(void *Instance)
#endif #endif
#ifdef BSP_USING_HWTIM4 #ifdef BSP_USING_HWTIM4
if(TIMx == TIM4) if (TIMx == TIM4)
{ {
/* TIM4 clock enable */ /* TIM4 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE);
@ -273,7 +273,7 @@ void n32_msp_hwtim_init(void *Instance)
#endif #endif
#ifdef BSP_USING_HWTIM5 #ifdef BSP_USING_HWTIM5
if(TIMx == TIM5) if (TIMx == TIM5)
{ {
/* TIM5 clock enable */ /* TIM5 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE);
@ -281,19 +281,19 @@ void n32_msp_hwtim_init(void *Instance)
#endif #endif
#ifdef BSP_USING_HWTIM6 #ifdef BSP_USING_HWTIM6
if(TIMx == TIM6) if (TIMx == TIM6)
{ {
/* TIM6 clock enable */ /* TIM6 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE);
} }
#endif #endif
#ifdef BSP_USING_HWTIM7 #ifdef BSP_USING_HWTIM7
if(TIMx == TIM7) if (TIMx == TIM7)
{ {
/* TIM7 clock enable */ /* TIM7 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE);
} }
#endif #endif
} }
#endif #endif
@ -307,7 +307,7 @@ void n32_msp_can_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_CAN1 #ifdef BSP_USING_CAN1
if(CAN1 == CANx) if (CAN1 == CANx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -321,7 +321,7 @@ void n32_msp_can_init(void *Instance)
} }
#endif #endif
#ifdef BSP_USING_CAN2 #ifdef BSP_USING_CAN2
if(CAN2 == CANx) if (CAN2 == CANx)
{ {
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
@ -347,7 +347,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name)
if (uartx == NULL) if (uartx == NULL)
{ {
uartx = rt_device_find(name); uartx = rt_device_find(name);
rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX|RT_DEVICE_FLAG_DMA_RX); rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX);
RT_ASSERT(err == RT_EOK); RT_ASSERT(err == RT_EOK);
} }
rt_device_write(uartx, 0, name, strlen(name)); rt_device_write(uartx, 0, name, strlen(name));
@ -356,7 +356,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name)
int ret = rt_device_read(uartx, 0, recv_buf, sizeof(recv_buf)); int ret = rt_device_read(uartx, 0, recv_buf, sizeof(recv_buf));
if (ret != 0) if (ret != 0)
{ {
for (int i=0; i<ret; ++i) for (int i = 0; i < ret; ++i)
rt_kprintf("[%02x]", recv_buf[i]); rt_kprintf("[%02x]", recv_buf[i]);
} }
rt_device_write(uartx, 0, "\r\n", 2); rt_device_write(uartx, 0, "\r\n", 2);
@ -377,9 +377,9 @@ MSH_CMD_EXPORT(uart_test, uart_test)
#ifdef BSP_USING_ADC #ifdef BSP_USING_ADC
#ifdef BSP_USING_ADC1 #ifdef BSP_USING_ADC1
#define ADC_DEV_NAME "adc1" #define ADC_DEV_NAME "adc1"
#else #else
#define ADC_DEV_NAME "adc2" #define ADC_DEV_NAME "adc2"
#endif #endif
#define REFER_VOLTAGE 3300 #define REFER_VOLTAGE 3300
#define CONVERT_BITS (1 << 12) #define CONVERT_BITS (1 << 12)
@ -396,7 +396,7 @@ static int adc_vol_sample(int argc, char *argv[])
return RT_ERROR; return RT_ERROR;
} }
for (int i=6; i<=9; ++i) for (int i = 6; i <= 9; ++i)
{ {
ret = rt_adc_enable(adc_dev, i); ret = rt_adc_enable(adc_dev, i);
value = rt_adc_read(adc_dev, i); value = rt_adc_read(adc_dev, i);