[hc32] Add some bsp drivers. (#8480)

2025-01-19 11:53:31 +08:00 · 2024-01-09 21:56:37 +08:00 · 2024-01-09 21:56:37 +08:00 · 48244f25f8
commit 48244f25f8
parent 58a159a0d6
688 changed files with 367246 additions and 19020 deletions
--- a/bsp/hc32/README.md
+++ b/bsp/hc32/README.md
@ -17,7 +17,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
 | **BSP 使用教程** | **简介**                                          |
 |:-------------------- |:------------------------------------------------- |
 | [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
-| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
+| [外设驱动介绍](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
 | **BSP 制作与提交** | **简介**                                     |
 | [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 |

--- a/bsp/hc32/docs/HC32系列BSP制作教程.md
+++ b/bsp/hc32/docs/HC32系列BSP制作教程.md
@ -1,2 +1,251 @@
 # HC32 系列 BSP 制作教程

+为了让广大开发者更好、更方便地使用 BSP 进行开发，XHSC 开发团队重新整理了现有的 HC32 系列的 BSP，推出了新的 BSP 框架。新的 BSP 框架在易用性、移植便利性、驱动完整性、代码规范性等方面都有较大提升，在新的 BSP 框架下进行开发，可以大大提高应用的开发效率。
+
+在新的 BSP 文件夹中将固件库、外设驱动等可以被多个 BSP 引用的代码文件统一存放在 Library 文件夹中，通过在特定 BSP 中引用这些文件的方式，来包含 BSP 中所需的库文件或者驱动文件。这种方式不仅大大提高了代码复用率，降低了 BSP 的维护成本，而且可以更方便地给开发者提供更丰富的驱动文件，让开发者可以更容易地找到自己需要的资源。
+
+新 BSP 框架的主要特性如下：
+
+- 提供多系列 BSP 模板，大大降低新 BSP 的添加难度；
+- 每个 BSP 都配有齐全的驱动文件，开发者可以方便地使用所有驱动；
+
+## 1. BSP 框架介绍
+
+BSP 框架结构如下图所示：
+
+![BSP 框架图](./figures/frame.jpg)
+
+每一个 HC32 系列的 BSP 由两部分组成，分别是通用库和特定开发板 BSP，下面的表格以 F4 系列 BSP 为例介绍这两个部分：
+
+| 项目           | 文件夹                   | 说明                                                   |
+| -------------- | ------------------------ | :----------------------------------------------------- |
+| 通用库         | hc32/libraries           | 用于存放 DDL 库以及基于 DDL 库的多系列通用外设驱动文件 |
+| 特定开发板 BSP | hc32/ev_hc32f4a0_lqfp176 | 在 BSP 模板的基础上修改而成                            |
+
+## 2. 知识准备
+
+制作一个 BSP 的过程就是构建一个新系统的过程，因此想要制作出好用的 BSP，要对 RT-Thread 系统的构建过程有一定了解，需要的知识准备如下所示：
+
+- 掌握  HC32 系列 BSP 的使用方法
+  了解 BSP 的使用方法，可以阅读 [BSP 说明文档](../README.md) 中使用教程表格内的文档。了解外设驱动的添加方法可以参考《外设驱动添加指南》。
+- 了解 Scons 工程构建方法
+  RT-Thread 使用 Scons 作为系统的构建工具，因此了解 Scons 的常用命令对制作新 BSP 是基本要求。
+- 了解设备驱动框架
+  在 RT-Thread 系统中，应用程序通过设备驱动框架来操作硬件，因此了解设备驱动框架，对添加 BSP 驱动是很重要的。
+- 了解 Kconfig 语法
+  RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 Kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
+
+## 3. BSP 制作方法
+
+本节以制作 XHSC 官方评估板 `ev_hc32f4a0_lqfp176` 的 BSP 为例，讲解如何为一个新的开发板添加 BSP。
+
+BSP 的制作过程分为如下五个步骤：
+
+1. 复制 BSP 通用模板
+2. BOARD 配置
+3. 修改 BSP 中的 Kconfig 文件
+4. 修改构建工程相关文件
+5. 重新生成工程
+
+在接下来的章节中将会详细介绍这五个步骤，帮助开发者快速创建所需要的 BSP。
+
+### 3.1 复制 BSP 通用模板
+
+制作新 BSP 的第一步是复制一份同系列的 BSP 作为基础，通过对 BSP 的修改来获得新 BSP。
+
+本次示例所用的 F4A0 的 BSP 文件结构如下：
+
+![F4A0 系列 BSP 文件夹内容](figures/bsp_template.jpg)
+
+本次制作的 BSP 为 HC32F4A0 系列，因此复制 `ev_hc32f4a0_lqfp176` 文件夹，并将该文件夹的名称改为所要制作的 BSP 的名字，此处不变。
+
+在BSP 的制作过程中，需修改 board 文件夹内的配置文件，下表总结了 board 文件夹中需要修改的内容：
+
+| 项目                      | 需要修改的内容说明                        |
+| ------------------------- | ----------------------------------------- |
+| linker_scripts （文件夹） | BSP 特定的链接脚本                        |
+| board.c/h                 | 系统时钟、GPIO 初始化函数、芯片存储器大小 |
+| board_config.c/h          | 外设管脚配置及初始化                      |
+| Kconfig                   | 芯片型号、系列、外设资源                  |
+| SConscript                | 芯片启动文件、目标芯片型号                |
+
+### 3.2 修改 board 配置
+
+#### 3.2.1 配置外设管脚
+
+在 **board_config.c** 文件中实现了外设管脚相关配置，下图展示了串口 USART 的管脚配置，示例函数 `rt_hw_board_uart_init` 中配置了 USART1 和 USART6 的管脚。其他外设的管脚配置参照该函数。
+
+![管脚配置](figures/pin_config.jpg)
+
+在 **board_config.h** 中实现了管脚的宏定义，可根据实际使用的管脚进行修改。
+
+![管脚宏定义](figures/pin_define.jpg)
+
+#### 3.2.2 配置系统时钟
+
+在 **board.c** 文件中存放了函数 `SystemClock_Config()` ，该函数负责初始化系统时钟。如下图所示，示例中时钟为240Mhz，可根据实际使用进行修改。
+
+![时钟配置](figures/clock_config.jpg)
+
+#### 3.2.3 配置 FLASH 和 RAM
+
+在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，这个文件中需要修改的是 `HC32_FLASH_SIZE` 和 `HC32_SRAM_SIZE` 这两个宏控制的参数。如下图所示：
+
+![内存配置](figures/flash.jpg)
+
+#### 3.2.4 配置堆内存
+
+通常情况下，系统 RAM 中的一部分内存空间会被用作堆内存。下面代码的作用是，在不同编译器下规定堆内存的起始地址 **HEAP_BEGIN** 和结束地址 **HEAP_END**。这里 **HEAP_BEGIN** 和 **HEAP_END** 的值需要和后面 [3.4.1 修改链接脚本](#341-修改链接脚本) 章节所修改的配置相一致。
+
+在某些系列的芯片中，芯片 RAM 可能分布在不连续的多块内.存区域上。此时堆内存的位置可以和系统内存在同一片连续的内存区域，也可以存放在一片独立的内存区域中。
+
+![堆内存配置](figures/heap.jpg)
+
+#### 3.2.5 配置中断
+
+在 **irq_config.h** 文件中，统一分配了外设使用的中断号。HC32F4A0 系列的中断可灵活配置，用户可根据实际使用情况，灵活调整外设中断号。如下图所示：
+
+![中断配置](figures/irq_config.jpg)
+
+### 3.3 修改 Kconfig 选项
+
+在本小节中修改 `board/Kconfig` 文件的内容有如下两点：
+
+- 芯片型号和系列
+- BSP 上的外设支持选项
+
+芯片型号和系列的修改如下表所示：
+
+| 宏定义            | 意义     | 格式              |
+| ----------------- | -------- | ----------------- |
+| SOC_HC32F4A0SI    | 芯片型号 | SOC_HC32xxx       |
+| SOC_SERIES_HC32F4 | 芯片系列 | SOC_SERIES_HC32xx |
+
+关于 BSP 上的外设支持选项，一个初次提交的 BSP 仅仅需要支持 GPIO 驱动和串口驱动即可，因此在配置选项中只需保留这两个驱动配置项，如下图所示：
+
+![修改 Kconfig](./figures/Kconfig.jpg)
+
+### 3.4 修改工程构建相关文件
+
+接下来需要修改用于构建工程相关的文件。
+
+#### 3.4.1 修改链接脚本
+
+**linker_scripts** 链接文件如下图所示：
+
+![需要修改的链接脚本](./figures/linker_scripts.jpg)
+
+下面以 MDK 使用的链接脚本 link.sct 为例，展示如何修改链接脚本：
+
+![MDK连接脚本](figures/link_sct.jpg)
+
+本次制作 BSP 使用的芯片为 HC32F4A0，FLASH 为 2M，因此修改 LR_IROM1 和 ER_IROM1 的参数为 0x00200000。RAM 的大小为512k， 因此修改 RW_IRAM1 的参数为 0x00080000， 起始地址为0x1FFE0000。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据实际需求修改。
+
+其他两个链接脚本的文件分别为 iar 使用的 link.icf 和 gcc 编译器使用的 link.ld，修改的方式也是类似的，如下图所示：
+
+- link.icf 修改内容
+
+  ![link_icf](figures/link_icf.jpg)
+- link.ld 修改内容
+
+  ![link_lds](figures/link_ld.jpg)
+
+#### 3.4.2 修改构建脚本
+
+**SConscript** 脚本决定 MDK/IAR 工程的生成以及编译过程中要添加文件。
+
+在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：
+
+![修改启动文件和芯片型号](./figures/SConscript.jpg)
+
+注意：若复制的是同系列的BSP来进行修改，这个文件可不做修改。
+
+#### 3.4.2 修改工程模板
+
+**template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK5/IAR 的工程模板文件，如下图所示：
+
+![MDK/IAR 工程模板](./figures/template.jpg)
+
+下面以 MDK5 模板的修改为例，介绍如何修改模板配置：
+
+![选择芯片型号](./figures/template_mdk1.jpg)
+
+修改程序下载方式：
+
+![配置下载方式](./figures/template_mdk2.jpg)
+
+### 3.5 重新生成工程
+
+重新生成工程需要使用 Env 工具。
+
+#### 3.5.1 重新生成 rtconfig.h 文件
+
+在 Env 界面输入命令 menuconfig 对工程进行配置，并生成新的 rtconfig.h 文件。如下图所示：
+
+![输入menuconfig进入配置界面](./figures/menuconfig_1.jpg)
+
+![选择要打开的外设](./figures/menuconfig_2.jpg)
+
+#### 3.5.2 重新生成 MDK/IAR 工程
+
+下面以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。
+
+使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示：
+
+![重新生成 BSP 工程](./figures/menuconfig_3.jpg)
+
+重新生成工程成功：
+
+![重新生成 BSP 工程](./figures/menuconfig_4.jpg)
+
+到这一步为止，新的 BSP 就可以使用了。
+
+接下来我们可以分别使用命令 `scons --target=mdk4` ， `scons --target=iar` ，`scons --target=eclipse`，来更新 MDK4 , IAR 和 GCC 的工程，使得该 BSP 变成一个完整的，可以提交到 GitHub 的 BSP （MDK4工程的制作为可选）。
+
+## 4. 规范
+
+本章节介绍 RT-Thread HC32 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。
+
+### 4.1 BSP 制作规范
+
+HC32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 IDE 配置。在已有的 HC32 系列 BSP 的模板中，已经根据下列规范对模板进行配置。在制作新 BSP 的过程中，拷贝模板进行修改时，需要注意的是不要修改这些默认的配置。BSP 制作完成后，需要对新制作的 BSP 进行功能测试，功能正常后再进行代码提交。
+
+下面将详细介绍 BSP 的制作规范。
+
+#### 4.1.1 工程配置
+
+- 遵从RT-Thread 编码规范，代码注释风格统一
+- main 函数功能保持一致
+  - 如果有 LED 的话，main 函数里 **只放一个** LED 1HZ 闪烁的程序
+- 在 `rt_hw_board_init` 中需要完成堆的初始化：调用 `rt_system_heap_init`
+- 默认只初始化 GPIO 驱动和 FinSH 对应的串口驱动，不使用 DMA
+- 当使能板载外设驱动时，应做到不需要修改代码就能编译下载使用
+- 提交前应检查 GCC/MDK/IAR 三种编译器直接编译或者重新生成后编译是否成功
+- 使用 `dist` 命令对 BSP 进行发布，检查使用 `dist` 命令生成的工程是否可以正常使用
+
+#### 4.1.2 ENV 配置
+
+- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
+- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
+- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE）
+- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
+- 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
+- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
+
+#### 4.1.3 IDE 配置
+
+- 使能下载代码后自动运行
+- 使能 C99 支持
+- 使能 One ELF Section per Function（MDK）
+- MDK/IAR 生成的临时文件分别放到build下的 MDK/IAR 文件夹下
+- MDK/GCC/IAR 生成 bin 文件名字统一成 rtthread.bin
+
+### 4.2 BSP 提交规范
+
+- 提交前请认真修改 BSP 的 README.md 文件，README.md 文件的外设支持表单只填写 BSP 支持的外设，可参考其他 BSP 填写。查看文档[《HC32系列驱动介绍》](./HC32系列驱动介绍.md)了解驱动分类。
+- 提交 BSP 分为 2 个阶段提交：
+  - 第一阶段：基础 BSP 包括串口驱动和 GPIO 驱动，能运行 FinSH 控制台。完成 MDK4、MDK5 、IAR 和 GCC 编译器支持，如果芯片不支持某款编译器（比如MDK4）可以不用做。 BSP 的 README.md 文件需要填写第二阶段要完成的驱动。
+  - 第二阶段：完成板载外设驱动支持，所有板载外设使用 menuconfig 配置后就能直接使用。若开发板没有板载外设，则此阶段可以不用完成。不同的驱动要分开提交，方便 review 和合并。
+- 只提交 BSP 必要的文件，删除无关的中间文件，能够提交的文件请对照其他 BSP。
+- 提交前要对 BSP 进行编译测试，确保在不同编译器下编译正常。
+- 提交前要对 BSP 进行功能测试，确保 BSP 的在提交前符合工程配置章节中的要求。
--- a/bsp/hc32/docs/HC32系列BSP外设驱动使用教程.md
+++ b/bsp/hc32/docs/HC32系列BSP外设驱动使用教程.md
@ -1 +1,11 @@
 # HC32系列BSP外设驱动使用教程
+
+## 简介
+
+本文档是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+主要包括以下内容：
+
+1. 如何使用开发板上更多的板载资源
+2. 如何使用更多的片上资源
+3. 如何添加更多片上资源选项
--- a/bsp/hc32/docs/HC32系列BSP外设驱动添加指南.md
+++ b/bsp/hc32/docs/HC32系列BSP外设驱动添加指南.md
@ -0,0 +1,2 @@
+# HC32系列驱动介绍
+
--- a/bsp/hc32/docs/HC32系列驱动介绍.md
+++ b/bsp/hc32/docs/HC32系列驱动介绍.md
@ -1,2 +1,64 @@
 # HC32系列驱动介绍

+在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套  I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示：
+
+![rt_device](figures/rt_device.png)
+
+使用 I/O 设备管理框架开发应用程序，有如下优点：
+
+- 使用同一套标准的 API 开发应用程序，使应用程序具有更好的移植性
+- 底层驱动的升级和修改不会影响到上层代码
+- 驱动和应用程序相互独立，方便多个开发者协同开发
+
+## 1. 驱动分类介绍
+
+本小节介绍 BSP 提供的不同类别驱动的概念，对一个 BSP 而言，有如下三类驱动：
+
+- **片上外设驱动**：指 MCU 芯片上的外设，例如硬件定时器、ADC等
+- **板载外设驱动**：指 MCU 之外，开发板上外设，例如 TF 卡、以太网等
+- **扩展模块驱动**：指可以通过扩展接口或者杜邦线连接的开发板的模块
+
+这三种外设的示意图如下所示：
+
+![Peripheral](figures/peripheral.png)
+
+## 2. 外设驱动的使用方法
+
+当前 RT-Thread 提供的驱动库已经支持 HC32 多个系列的 BSP。点击下表中的驱动名称，即可跳转到对应驱动框架的介绍文档。开发者可以通过阅读相关资料，了解如何在应用开发中通过设备驱动框架来使用这些外设驱动。
+
+### 2.1 片上外设
+
+| 序号 | 驱动                                                         | 简介                           |
+| ---- | ------------------------------------------------------------ | ------------------------------ |
+| 1    | [GPIO](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pin/pin) | 操作 GPIO 管脚                 |
+| 2    | [UART](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/uart/uart_v1/uart) | 通过串口收发数据               |
+| 3    | [UART V2](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/uart/uart_v2/uart) | 通过串口收发数据               |
+| 4    | [SOFT I2C](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/i2c/i2c) | 通过软件 I2C 收发数据          |
+| 5    | [I2C](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/i2c/i2c) | 通过硬件 I2C 收发数据          |
+| 6    | [SPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi) | 通过 SPI 收发数据              |
+| 7    | [QSPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi?id=配置-qspi-设备) | 通过 SPI（1、2、4线） 收发数据 |
+| 8    | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量             |
+| 9    | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量             |
+| 10   | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据              |
+| 11   | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时             |
+| 12   | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形      |
+| 13   | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间                 |
+| 14   | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动                     |
+| 15   | [CRYPTO](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/crypto/crypto) | 对数据进行加解密操作           |
+| 16   | [PULSE ENCODER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pulse_encoder/pulse_encoder) | 脉冲编码器驱动                 |
+
+### 2.2 板载外设
+
+| 序号 | 驱动    | 简介                                    |
+| ---- | ------- | --------------------------------------- |
+| 1    | SD      | 适用于 SDIO 接口的 SD(TF) 卡              |
+| 2    | ETH     | 以太网                                  |
+| 3    | USB     | USB                                    |
+| 4    | NAND    | NAND                                   |
+| 4    | SDRAM   | SDRAM                                  |
+
+### 2.3 扩展模块
+
+### 2.4 驱动示例代码
+
+在 RT-Thread 的 `examples\test` 目录下，有 RT-Thread 提供的基于不同外设驱动的示例代码。在 env 工具中开启 BSP 中要测试的驱动，并将 `examples\test` 中对应的驱动框架测试文件加入工程，即可快速测试 BSP 中提供的驱动。
--- a/bsp/hc32/docs/figures/Kconfig.jpg
+++ b/bsp/hc32/docs/figures/Kconfig.jpg
--- a/bsp/hc32/docs/figures/SConscript.jpg
+++ b/bsp/hc32/docs/figures/SConscript.jpg
--- a/bsp/hc32/docs/figures/bsp_template.jpg
+++ b/bsp/hc32/docs/figures/bsp_template.jpg
--- a/bsp/hc32/docs/figures/clock_config.jpg
+++ b/bsp/hc32/docs/figures/clock_config.jpg
--- a/bsp/hc32/docs/figures/dma_config.jpg
+++ b/bsp/hc32/docs/figures/dma_config.jpg
--- a/bsp/hc32/docs/figures/flash.jpg
+++ b/bsp/hc32/docs/figures/flash.jpg
--- a/bsp/hc32/docs/figures/frame.jpg
+++ b/bsp/hc32/docs/figures/frame.jpg
--- a/bsp/hc32/docs/figures/heap.jpg
+++ b/bsp/hc32/docs/figures/heap.jpg
--- a/bsp/hc32/docs/figures/irq_config.jpg
+++ b/bsp/hc32/docs/figures/irq_config.jpg
--- a/bsp/hc32/docs/figures/link_icf.jpg
+++ b/bsp/hc32/docs/figures/link_icf.jpg
--- a/bsp/hc32/docs/figures/link_ld.jpg
+++ b/bsp/hc32/docs/figures/link_ld.jpg
--- a/bsp/hc32/docs/figures/link_sct.jpg
+++ b/bsp/hc32/docs/figures/link_sct.jpg
--- a/bsp/hc32/docs/figures/linker_scripts.jpg
+++ b/bsp/hc32/docs/figures/linker_scripts.jpg
--- a/bsp/hc32/docs/figures/menuconfig_1.jpg
+++ b/bsp/hc32/docs/figures/menuconfig_1.jpg
--- a/bsp/hc32/docs/figures/menuconfig_2.jpg
+++ b/bsp/hc32/docs/figures/menuconfig_2.jpg
--- a/bsp/hc32/docs/figures/menuconfig_3.jpg
+++ b/bsp/hc32/docs/figures/menuconfig_3.jpg
--- a/bsp/hc32/docs/figures/menuconfig_4.jpg
+++ b/bsp/hc32/docs/figures/menuconfig_4.jpg
--- a/bsp/hc32/docs/figures/peripheral.png
+++ b/bsp/hc32/docs/figures/peripheral.png
--- a/bsp/hc32/docs/figures/pin_config.jpg
+++ b/bsp/hc32/docs/figures/pin_config.jpg
--- a/bsp/hc32/docs/figures/pin_define.jpg
+++ b/bsp/hc32/docs/figures/pin_define.jpg
--- a/bsp/hc32/docs/figures/rt_device.png
+++ b/bsp/hc32/docs/figures/rt_device.png
--- a/bsp/hc32/docs/figures/template.jpg
+++ b/bsp/hc32/docs/figures/template.jpg
--- a/bsp/hc32/docs/figures/template_mdk1.jpg
+++ b/bsp/hc32/docs/figures/template_mdk1.jpg
--- a/bsp/hc32/docs/figures/template_mdk2.jpg
+++ b/bsp/hc32/docs/figures/template_mdk2.jpg
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.config
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.config
@ -9,8 +9,10 @@
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@ -20,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
@ -35,7 +38,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
-# CONFIG_RT_DEBUGING_INIT is not set
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set

 #
 # Inter-Thread communication
@ -63,19 +66,15 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
-CONFIG_RT_VER_NUM=0x50002
+CONFIG_RT_VER_NUM=0x50100
 # CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # CONFIG_RT_USING_CACHE is not set
 CONFIG_RT_USING_HW_ATOMIC=y
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@ -119,6 +118,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 #
 # Device Drivers
 #
+# CONFIG_RT_USING_DM is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
@ -127,7 +127,7 @@ CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
-# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
@ -144,7 +144,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@ -215,6 +214,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set

+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
 #
 # Utilities
 #
@ -267,6 +272,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
 # CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@ -288,7 +308,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@ -309,6 +328,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NMEALIB is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@ -328,6 +349,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZFTP is not set
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set

 #
 # security packages
@ -374,7 +397,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # LVGL: powerful and easy-to-use embedded GUI library
 #
 # CONFIG_PKG_USING_LVGL is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set

@ -451,6 +473,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 # CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set

 #
 # system packages
@ -487,6 +510,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
@ -510,6 +535,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QBOOT is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
 # CONFIG_PKG_USING_EVENT_RECORDER is not set
@ -523,6 +549,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
 # CONFIG_PKG_USING_FLASH_BLOB is not set
 # CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set

 #
 # peripheral libraries and drivers
@ -587,6 +618,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
 # CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_MAX17048 is not set
@ -687,6 +719,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FINGERPRINT is not set
 # CONFIG_PKG_USING_BT_ECB02C is not set
 # CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set

 #
@ -701,6 +738,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set

 #
 # Signal Processing and Control Algorithm Packages
@ -710,6 +748,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set

 #
 # miscellaneous packages
@ -741,12 +780,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_COWSAY is not set
 # CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@ -784,6 +825,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set

@ -791,13 +833,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@ -842,7 +884,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@ -881,7 +923,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@ -904,7 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@ -912,7 +953,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@ -925,12 +966,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set

 #
 # Display
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
@ -939,6 +982,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Timing
 #
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
@ -964,18 +1008,17 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set

 #
 # Other
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set

 #
 # Signal IO
@ -1000,9 +1043,15 @@ CONFIG_SOC_SERIES_HC32F4=y
 #
 CONFIG_SOC_HC32F460PE=y

+#
+# On-chip Drivers
+#
+CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y
+
 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_SPI_FLASH is not set

 #
 # On-chip Peripheral Drivers
@ -1015,12 +1064,21 @@ CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART4=y
 # CONFIG_BSP_UART4_RX_USING_DMA is not set
 # CONFIG_BSP_UART4_TX_USING_DMA is not set
-# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_WDT_TMR is not set
 # CONFIG_BSP_USING_RTC is not set
-# CONFIG_BSP_USING_I2C2 is not set
-# CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_PWM_TMRA is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_PM is not set
+# CONFIG_BSP_USING_HWCRYPTO is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_QSPI is not set
+# CONFIG_BSP_USING_PULSE_ENCODER is not set
+# CONFIG_BSP_USING_HWTIMER is not set

 #
 # Board extended module Drivers
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.cproject
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.cproject
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.project
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.project
@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/libraries</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md
@ -39,12 +39,13 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下：
 | :------------ | :-----------: | :-----------------------------------: |
 | USB 转串口    |      支持     |          使用 UART4                  |
 | LED           |     支持     |           LED                   |
-| **片上外设**  | **支持情况** |               **备注**                |
+
+| **片上外设**   | **支持情况** |               **备注**                |
 | :------------ | :-----------: | :-----------------------------------: |
-| ADC           |     支持     | ADC1: CH10, CH11, CH12,<br>ADC2: CH7 |
-| CAN           |     支持     |              CAN1                      |
-| GPIO          |     支持     | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
-| I2C           |     支持     | 软件 |
+| ADC           |     支持     | 				ADC1~2					  |
+| CAN           |     支持     |              CAN1                    |
+| GPIO          |     支持     | PA0, PA1... PH2 ---> PIN: 0, 1...82  |
+| I2C           |     支持     | 软件 								  |
 | UART          |     支持     |              UART1~4                 |


@ -107,4 +108,4 @@ msh >

 维护人:

-  [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
+-  [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct
@ -56,5 +56,7 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

+objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/main.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/main.c
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -13,7 +12,6 @@
 #include <rtdevice.h>
 #include <board.h>

-
 /* defined the LED_GREEN pin: PD4 */
 #define LED_GREEN_PIN GET_PIN(D, 4)

--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c
@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-10-27     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
@ -7,7 +7,23 @@ config SOC_HC32F460PE
    select RT_USING_USER_MAIN
    default y

+menu "On-chip Drivers"
+    config BSP_USING_ON_CHIP_FLASH_CACHE
+        bool "Enable on-chip Flash Cache"
+        default y
+endmenu
+
 menu "Onboard Peripheral Drivers"
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (w25q64 spi3)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI3
+        select BSP_USING_ON_CHIP_FLASH
+        select RT_USING_SFUD
+        select RT_USING_DFS
+        select RT_USING_FAL
+        select RT_USING_MTD_NOR
+        default n

 endmenu

@ -22,79 +38,279 @@ menu "On-chip Peripheral Drivers"
        default y
        select RT_USING_SERIAL
        if BSP_USING_UART
-            config BSP_USING_UART1
+            menuconfig BSP_USING_UART1
                bool "Enable UART1"
                default y
+                if BSP_USING_UART1
+                    config BSP_UART1_RX_USING_DMA
+                        bool "Enable UART1 RX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART1_RX_USING_DMA
-                bool "Enable UART1 RX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART1_TX_USING_DMA
+                        bool "Enable UART1 TX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART1_TX_USING_DMA
-                bool "Enable UART1 TX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART1_RX_BUFSIZE
+                        int "Set UART1 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256

-            config BSP_USING_UART2
+                    config BSP_UART1_TX_BUFSIZE
+                        int "Set UART1 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+
+            menuconfig BSP_USING_UART2
                bool "Enable UART2"
                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART2_RX_USING_DMA
-                bool "Enable UART2 RX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART2_TX_USING_DMA
-                bool "Enable UART2 TX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256

-            config BSP_USING_UART3
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART3
                bool "Enable UART3"
                default n
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_USING_DMA
+                        bool "Enable UART3 RX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART3_RX_USING_DMA
-                bool "Enable UART3 RX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART3_TX_USING_DMA
+                        bool "Enable UART3 TX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART3_TX_USING_DMA
-                bool "Enable UART3 TX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256

-            config BSP_USING_UART4
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART4
                bool "Enable UART4"
                default n
+                if BSP_USING_UART4
+                    config BSP_UART4_RX_USING_DMA
+                        bool "Enable UART4 RX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART4_RX_USING_DMA
-                bool "Enable UART4 RX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART4_TX_USING_DMA
+                        bool "Enable UART4 TX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n

-            config BSP_UART4_TX_USING_DMA
-                bool "Enable UART4 TX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
-                default n
+                    config BSP_UART4_RX_BUFSIZE
+                        int "Set UART4 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART4_TX_BUFSIZE
+                        int "Set UART4 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
        endif

-    menuconfig BSP_USING_CAN
-        bool "Enable CAN"
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C BUS"
        default n
-        select RT_USING_CAN
-        if BSP_USING_CAN
-            config BSP_USING_CAN1
-                bool "using can1"
+        select RT_USING_I2C
+
+        if BSP_USING_I2C
+            menuconfig BSP_USING_I2C1_SW
+                bool "Enable I2C1 BUS (software simulation)"
                default n
+                select RT_USING_I2C_BITOPS
+                select RT_USING_PIN
+                if BSP_USING_I2C1_SW
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 scl pin number"
+                        range 1 100
+                        default 7
+                    config BSP_I2C1_SDA_PIN
+                        int "I2C1 sda pin number"
+                        range 1 100
+                        default 36
+                endif
+        endif
+
+        if BSP_USING_I2C
+            config BSP_I2C_USING_DMA
+                bool
+                default n
+            config BSP_USING_I2C_HW
+                bool
+                default n
+
+            menuconfig BSP_USING_I2C1
+                bool "Enable I2C1 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C1_TX_USING_DMA
+                        bool "Enable I2C1 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                    config BSP_I2C1_RX_USING_DMA
+                        bool "Enable I2C1 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                endif
+
+            menuconfig BSP_USING_I2C2
+                bool "Enable I2C2 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C2_TX_USING_DMA
+                        bool "Enable I2C2 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                    config BSP_I2C2_RX_USING_DMA
+                        bool "Enable I2C2 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                endif
+
+            menuconfig BSP_USING_I2C3
+                bool "Enable I2C3 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C3
+                    config BSP_I2C3_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C3_TX_USING_DMA
+                        bool "Enable I2C3 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C3_USING_DMA
+                    config BSP_I2C3_RX_USING_DMA
+                        bool "Enable I2C3 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C3_USING_DMA
+                endif
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_SPI_USING_DMA
+                bool
+                default n
+
+            menuconfig BSP_USING_SPI1
+                bool "Enable SPI1 BUS"
+                default n
+                if BSP_USING_SPI1
+                    config BSP_SPI1_TX_USING_DMA
+                        bool "Enable SPI1 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI1_RX_USING_DMA
+                        bool "Enable SPI1 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI1_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n
+                if BSP_USING_SPI2
+                    config BSP_SPI2_TX_USING_DMA
+                        bool "Enable SPI2 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI2_RX_USING_DMA
+                        bool "Enable SPI2 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI2_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_SPI3_TX_USING_DMA
+                        bool "Enable SPI3 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI3_RX_USING_DMA
+                        bool "Enable SPI3 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI3_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI4
+                bool "Enable SPI4 BUS"
+                default n
+                if BSP_USING_SPI4
+                    config BSP_SPI4_TX_USING_DMA
+                        bool "Enable SPI4 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI4_RX_USING_DMA
+                        bool "Enable SPI4 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI4_TX_USING_DMA
+                        default n
+                endif
        endif

    menuconfig BSP_USING_ADC
@ -110,6 +326,32 @@ menu "On-chip Peripheral Drivers"
                default n
        endif

+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        select RT_CAN_USING_HDR
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using can1"
+                default n
+        endif
+
+    menuconfig BSP_USING_WDT_TMR
+        bool "Enable Watchdog Timer"
+        default n
+        select RT_USING_WDT
+        if BSP_USING_WDT_TMR
+            config BSP_USING_WDT
+                bool "Using WDT"
+                default n
+                if BSP_USING_WDT
+                    config BSP_WDT_CONTINUE_COUNT
+                        bool "Low Power Mode Keeps Counting"
+                        default n
+                endif
+        endif
+
    menuconfig BSP_USING_RTC
        bool "Enable RTC"
        select RT_USING_RTC
@ -117,7 +359,7 @@ menu "On-chip Peripheral Drivers"
        if BSP_USING_RTC
            choice
                prompt "Select clock source"
-                default BSP_RTC_USING_LRC
+                default BSP_RTC_USING_XTAL32

                config BSP_RTC_USING_XTAL32
                    bool "RTC USING XTAL32"
@ -127,45 +369,267 @@ menu "On-chip Peripheral Drivers"
            endchoice
        endif

-    menuconfig BSP_USING_I2C2
-        bool "Enable I2C2 BUS (software simulation)"
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
        default n
-        select RT_USING_I2C
-        select RT_USING_I2C_BITOPS
-        select RT_USING_PIN
-        if BSP_USING_I2C2
-            config BSP_I2C2_SCL_PIN
-                int "i2c2 scl pin number"
-                range 1 100
-                default 48
-            config BSP_I2C2_SDA_PIN
-                int "I2C2 sda pin number"
-                range 1 100
-                default 49
+        select RT_USING_SDIO
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1"
+                default n
+            config BSP_USING_SDIO2
+                bool "Enable SDIO2"
+                default n
        endif

-    config BSP_USING_WDT
-        bool "Enable Watchdog Timer"
-        select RT_USING_WDT
+    menuconfig BSP_USING_PM
+        bool "Enable PM"
        default n
+        select RT_USING_PM
+        if BSP_USING_PM
+            choice
+                prompt "Select WKTM Clock Src"
+                default BSP_USING_WKTM_LRC

-    menuconfig BSP_USING_PWM_TMRA
-        bool "Enable timerA output PWM"
-        depends on (!BSP_USING_UART3)
+                config BSP_USING_WKTM_XTAL32
+                    bool "Using Xtal32"
+                config BSP_USING_WKTM_LRC
+                    bool "Using LRC"
+                if BSP_RTC_USING_XTAL32
+                    config BSP_USING_WKTM_64HZ
+                        bool "Using 64HZ(Note:must use XTAL32 and run RTC)"
+                endif
+            endchoice
+        endif
+
+    menuconfig BSP_USING_HWCRYPTO
+        bool "Using Hardware Crypto drivers"
+        default n
+        select RT_USING_HWCRYPTO
+        if BSP_USING_HWCRYPTO
+            config BSP_USING_UQID
+            bool "Enable UQID (unique id)"
+            default n
+
+            config BSP_USING_RNG
+            bool "Using Hardware RNG"
+            default n
+            select RT_HWCRYPTO_USING_RNG
+
+            config BSP_USING_CRC
+            bool "Using Hardware CRC"
+            default n
+            select RT_HWCRYPTO_USING_CRC
+
+            config BSP_USING_AES
+            bool "Using Hardware AES"
+            default n
+            select RT_HWCRYPTO_USING_AES
+            if BSP_USING_AES
+                choice
+                    prompt "Select AES Mode"
+                    default BSP_USING_AES_ECB
+
+                    config BSP_USING_AES_ECB
+                        bool "ECB mode"
+                        select RT_HWCRYPTO_USING_AES_ECB
+                endchoice
+            endif
+
+            config BSP_USING_HASH
+            bool "Using Hardware Hash"
+            default n
+            select RT_HWCRYPTO_USING_SHA2
+            if BSP_USING_HASH
+                choice
+                    prompt "Select Hash Mode"
+                    default BSP_USING_SHA2_256
+
+                    config BSP_USING_SHA2_256
+                        bool "SHA2_256 Mode"
+                        select RT_HWCRYPTO_USING_SHA2_256
+                endchoice
+            endif
+
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable output PWM"
        default n
        select RT_USING_PWM
-        if BSP_USING_PWM_TMRA
-        menuconfig BSP_USING_PWM_TMRA_4
-            bool "Enable timerA-4 output PWM"
-            default n
-            if BSP_USING_PWM_TMRA_4
-                config BSP_USING_PWM_TMRA_4_CH7
-                    bool "Enable timerA-4 channel7"
-                    default n
-                config BSP_USING_PWM_TMRA_4_CH8
-                    bool "Enable timerA-4 channel8"
-                    default n
+        if BSP_USING_PWM
+            menuconfig BSP_USING_PWM_TMRA
+                bool "Enable timerA output PWM"
+                default n
+                if BSP_USING_PWM_TMRA
+                    menuconfig BSP_USING_PWM_TMRA_4
+                        bool "Enable timerA-4 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_4
+                            config BSP_USING_PWM_TMRA_4_CH1
+                                bool "Enable timerA-4 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_4_CH2
+                                bool "Enable timerA-4 channel2"
+                                default n
+                        endif
+                    menuconfig BSP_USING_PWM_TMRA_5
+                        bool "Enable timerA-5 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_5
+                            config BSP_USING_PWM_TMRA_5_CH1
+                                bool "Enable timerA-5 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_5_CH2
+                                bool "Enable timerA-5 channel2"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR4
+                bool "Enable timer4 output PWM"
+                default n
+                if BSP_USING_PWM_TMR4
+                    menuconfig BSP_USING_PWM_TMR4_1
+                        bool "Enable timer4-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR4_1
+                            config BSP_USING_PWM_TMR4_1_OUH
+                                bool "Enable TMR4_1_OUH channel1"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OUL
+                                bool "Enable TMR4_1_OUL channel2"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVH
+                                bool "Enable TMR4_1_OVH channel3"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVL
+                                bool "Enable TMR4_1_OVL channel4"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWH
+                                bool "Enable TMR4_1_OWH channel5"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWL
+                                bool "Enable TMR4_1_OWL channel6"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR6
+                bool "Enable timer6 output PWM"
+                default n
+                if BSP_USING_PWM_TMR6
+                    menuconfig BSP_USING_PWM_TMR6_1
+                        bool "Enable timer6-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR6_1
+                            config BSP_USING_PWM_TMR6_1_A
+                                bool "Enable TMR6_1_A channel1"
+                                default n
+                            config BSP_USING_PWM_TMR6_1_B
+                                bool "Enable TMR6_1_B channel2"
+                                default n
+                        endif
+                endif
+        endif
+
+    menuconfig BSP_USING_USB
+        bool "Enable USB"
+        default n
+        select RT_USING_USB_DEVICE if BSP_USING_USBD
+        select RT_USING_USB_HOST if BSP_USING_USBH
+        if BSP_USING_USB
+            config BSP_USING_USBFS
+                bool
+                default y
+
+            choice
+                prompt "Select USB Mode"
+                default BSP_USING_USBD
+
+                config BSP_USING_USBD
+                    bool "USB Device Mode"
+
+                config BSP_USING_USBH
+                    bool "USB Host Mode"
+            endchoice
+
+            if BSP_USING_USBD
+                config BSP_USING_USBD_VBUS_SENSING
+                    bool "Enable VBUS Sensing"
+                    default y
            endif
+
+            if BSP_USING_USBH
+                menuconfig RT_USBH_MSTORAGE
+                    bool "Enable Udisk Drivers"
+                    default n
+                    if RT_USBH_MSTORAGE
+                        config UDISK_MOUNTPOINT
+                        string "Udisk mount dir"
+                        default "/"
+                    endif
+            endif
+        endif
+
+    menuconfig BSP_USING_QSPI
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SPI
+        default n
+        if BSP_USING_QSPI
+            config BSP_QSPI_USING_DMA
+                bool "Enable QSPI DMA support"
+                default n
+            config BSP_QSPI_USING_SOFT_CS
+                bool "Enable QSPI Soft CS Pin"
+                default n
+        endif
+
+    menuconfig BSP_USING_PULSE_ENCODER
+        bool "Enable Pulse Encoder"
+        default n
+        select RT_USING_PULSE_ENCODER
+        if BSP_USING_PULSE_ENCODER
+            menuconfig BSP_USING_TMRA_PULSE_ENCODER
+                bool "Use TIMERA As The Pulse Encoder"
+                default n
+                if BSP_USING_TMRA_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMRA_1
+                        bool "Use TIMERA_1 As The Pulse Encoder"
+                        default n
+                endif
+            menuconfig BSP_USING_TMR6_PULSE_ENCODER
+                bool "Use TIMER6 As The Pulse Encoder"
+                default n
+                if BSP_USING_TMR6_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMR6_1
+                        bool "Use TIMER6_1 As The Pulse Encoder"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable Hw Timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_TMRA_1
+                bool "Use Timer_a1 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_2
+                bool "Use Timer_a2 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_3
+                bool "Use Timer_a3 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_4
+                bool "Use Timer_a4 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_5
+                bool "Use Timer_a5 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_6
+                bool "Use Timer_a6 As The Hw Timer"
+                default n
        endif

 endmenu
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript
@ -12,9 +12,13 @@ board.c
 board_config.c
 ''')

+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/drv_spi_flash.c')
+
 path =  [cwd]
 path += [cwd + '/ports']
 path += [cwd + '/config']
+path += [cwd + '/config/usb_config']

 startup_path_prefix = SDK_LIB

@ -25,7 +29,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']:
 elif rtconfig.PLATFORM in ['iccarm']:
    src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s']

-CPPDEFINES = ['HC32F460']
+CPPDEFINES = ['HC32F460', '__DEBUG']
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

 Return('group')
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -10,37 +9,42 @@
 */

 #include "board.h"
-
-#ifdef RT_USING_PIN
-#include <drv_gpio.h>
-#endif
-
-#ifdef RT_USING_SERIAL
-#ifdef RT_USING_SERIAL_V2
-#include <drv_usart_v2.h>
-#else
-#include <drv_usart.h>
-#endif /* RT_USING_SERIAL */
-#endif /* RT_USING_SERIAL_V2 */
+#include "board_config.h"

 /* unlock/lock peripheral */
 #define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
 #define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)

+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
 /**
-  * @brief  This function is executed in case of error occurrence.
-  * @param  None
-  * @retval None
-  */
-void Error_Handler(void)
+ * @brief Switch clock stable time
+ * @note Approx. 30us
+ */
+#define CLK_SYSCLK_SW_STB               (HCLK_VALUE / 50000UL)
+/**
+ * @brief Clk delay function
+ * @param [in] u32Delay         count
+ * @retval when switch clock source, should be delay some time to wait stable.
+ */
+static void CLK_Delay(uint32_t u32Delay)
 {
-    /* USER CODE BEGIN Error_Handler */
-    /* User can add his own implementation to report the HAL error return state */
-    while (1)
+    __IO uint32_t u32Timeout = 0UL;
+
+    while (u32Timeout < u32Delay)
    {
+        u32Timeout++;
    }
-    /* USER CODE END Error_Handler */
+}
+#endif
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_CACHE)
+    EFM_CacheCmd(ENABLE);
+#endif
 }

 /** System Clock Configuration
@ -49,36 +53,40 @@ void SystemClock_Config(void)
 {
    stc_clock_xtal_init_t     stcXtalInit;
    stc_clock_pll_init_t      stcMpllInit;
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    stc_clock_pllx_init_t stcUpllInit;
+#endif
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif

-    (void)CLK_XtalStructInit(&stcXtalInit);
-    (void)CLK_PLLStructInit(&stcMpllInit);
-
-    /* Set bus clk div. */
+    /* PCLK0, HCLK  Max 200MHz */
+    /* PCLK1, PCLK4 Max 100MHz */
+    /* PCLK2, PCLK3 Max 50MHz  */
+    /* EX BUS Max 100MHz */
    CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \
                                      CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2));

+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+    (void)CLK_XtalStructInit(&stcXtalInit);
    /* Config Xtal and enable Xtal */
-    stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
-    stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8Mode  = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv   = CLK_XTAL_DRV_ULOW;
    stcXtalInit.u8State = CLK_XTAL_ON;
    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
    (void)CLK_XtalInit(&stcXtalInit);

+    (void)CLK_PLLStructInit(&stcMpllInit);
    /* MPLL config (XTAL / pllmDiv * plln / PllpDiv = 200M). */
+    stcMpllInit.u8PLLState = CLK_PLL_ON;
    stcMpllInit.PLLCFGR = 0UL;
    stcMpllInit.PLLCFGR_f.PLLM = 1UL - 1UL;
    stcMpllInit.PLLCFGR_f.PLLN = 50UL - 1UL;
    stcMpllInit.PLLCFGR_f.PLLP = 2UL - 1UL;
    stcMpllInit.PLLCFGR_f.PLLQ = 2UL - 1UL;
    stcMpllInit.PLLCFGR_f.PLLR = 2UL - 1UL;
-    stcMpllInit.u8PLLState = CLK_PLL_ON;
    stcMpllInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
    (void)CLK_PLLInit(&stcMpllInit);
-    /* Wait MPLL ready. */
-    while (SET != CLK_GetStableStatus(CLK_STB_FLAG_PLL))
-    {
-        ;
-    }

    /* sram init include read/write wait cycle setting */
    SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
@ -92,104 +100,52 @@ void SystemClock_Config(void)
    (void)PWC_HighSpeedToHighPerformance();
    /* Switch system clock source to MPLL. */
    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    /* PLLX for USB */
+    (void)CLK_PLLxStructInit(&stcUpllInit);
+    /* VCO = (8/2)*120 = 480MHz*/
+    stcUpllInit.u8PLLState = CLK_PLL_ON;
+    stcUpllInit.PLLCFGR = 0UL;
+    stcUpllInit.PLLCFGR_f.PLLM = 2UL - 1UL;
+    stcUpllInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcUpllInit.PLLCFGR_f.PLLP = 10UL - 1UL;
+    stcUpllInit.PLLCFGR_f.PLLQ = 6UL - 1UL;
+    stcUpllInit.PLLCFGR_f.PLLR = 6UL - 1UL;
+    (void)CLK_PLLxInit(&stcUpllInit);
+#endif
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
 }

 /** Peripheral Clock Configuration
 */
-static void PeripheralClock_Config(void)
+void PeripheralClock_Config(void)
 {
-#if defined(HC32F460)
 #if defined(RT_USING_ADC)
    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
 #endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
+    /* Wait stable here, since the current DDL API does not include this */
+    CLK_Delay(CLK_SYSCLK_SW_STB);
 #endif
 }

-/*******************************************************************************
- * Function Name  : SysTick_Configuration
- * Description    : Configures the SysTick for OS tick.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void  SysTick_Configuration(void)
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
 {
-    stc_clock_freq_t stcClkFreq;
-    rt_uint32_t cnts;
-
-    CLK_GetClockFreq(&stcClkFreq);
-
-    cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
-
-    SysTick_Config(cnts);
-}
-
-/**
- * This is the timer interrupt service routine.
- *
- */
-void SysTick_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/**
- * This function will initial HC32 board.
- */
-void rt_hw_board_init()
-{
-    /* Peripheral registers write unprotected */
    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
-
-    SystemClock_Config();
-    PeripheralClock_Config();
-    /* Configure the SysTick */
-    SysTick_Configuration();
-
-    /* Heap initialization */
-#if defined(RT_USING_HEAP)
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
-#endif
-
-    /* Pin driver initialization is open by default */
-#ifdef RT_USING_PIN
-    rt_hw_pin_init();
-#endif
-
-    /* USART driver initialization is open by default */
-#ifdef RT_USING_SERIAL
-    rt_hw_usart_init();
-#endif
-
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-
-    /* Board underlying hardware initialization */
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
-
-void rt_hw_us_delay(rt_uint32_t us)
-{
-    uint32_t start, now, delta, reload, us_tick;
-    start = SysTick->VAL;
-    reload = SysTick->LOAD;
-    us_tick = SystemCoreClock / 1000000UL;
-
-    do
-    {
-        now = SysTick->VAL;
-        delta = start > now ?  start - now : reload + start - now;
-    }
-    while (delta < us_tick * us);
 }

 /*@}*/
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -20,12 +19,18 @@
 extern "C" {
 #endif

+
+#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_SIZE                 (512 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
 #define HC32_SRAM_SIZE                  (188)
 #define HC32_SRAM_END                   (0x1FFF8000 + HC32_SRAM_SIZE * 1024)

 #ifdef __ARMCC_VERSION
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define HEAP_BEGIN                      (&Image$$RW_IRAM1$$ZI$$Limit)
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
 #elif __ICCARM__
 #pragma section="HEAP"
 #define HEAP_BEGIN                      (__segment_end("HEAP"))
@ -36,6 +41,11 @@ extern int __bss_end;

 #define HEAP_END                        HC32_SRAM_END

+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
@ -1,14 +1,11 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2022-04-28     CDT          first version
- * 2022-06-16     lianghongquan     use macro definition config adc pin.
- * 2022-06-28     lianghongquan     add function rt_hw_board_pwm_tmra_init().
 */

 #include <rtdevice.h>
@ -25,32 +22,18 @@ rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)

    switch ((rt_uint32_t)USARTx)
    {
-#if defined(BSP_USING_UART1)
-    case (rt_uint32_t)CM_USART1:
-        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33);
-        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32);
-        break;
-#endif
 #if defined(BSP_USING_UART2)
    case (rt_uint32_t)CM_USART2:
        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, GPIO_FUNC_37);
-        GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, GPIO_FUNC_36);
-        break;
-#endif
-#if defined(BSP_USING_UART3)
-    case (rt_uint32_t)CM_USART3:
-        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART3_RX_PORT, USART3_RX_PIN, GPIO_FUNC_33);
-        GPIO_SetFunc(USART3_TX_PORT, USART3_TX_PIN, GPIO_FUNC_32);
+        GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
+        GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
        break;
 #endif
 #if defined(BSP_USING_UART4)
    case (rt_uint32_t)CM_USART4:
        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART4_RX_PORT, USART4_RX_PIN, GPIO_FUNC_37);
-        GPIO_SetFunc(USART4_TX_PORT, USART4_TX_PIN, GPIO_FUNC_36);
+        GPIO_SetFunc(USART4_RX_PORT, USART4_RX_PIN, USART4_RX_FUNC);
+        GPIO_SetFunc(USART4_TX_PORT, USART4_TX_PIN, USART4_TX_FUNC);
        break;
 #endif
    default:
@ -62,33 +45,26 @@ rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
 }
 #endif

-#if defined(BSP_USING_CAN)
-void CanPhyEnable(void)
-{
-#if defined(BSP_USING_CAN1)
-#ifdef CAN1_STB_FUNC_ENABLE
-    GPIO_ResetPins(CAN_STB_PORT, CAN_STB_PIN);
-    GPIO_OutputCmd(CAN_STB_PORT, CAN_STB_PIN, ENABLE);
-#endif
-#endif
-}
-rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+#if defined(RT_USING_I2C)
+rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
 {
    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);

-    switch ((rt_uint32_t)CANx)
+    switch ((rt_uint32_t)I2Cx)
    {
-#if defined(BSP_USING_CAN1)
-case (rt_uint32_t)CM_CAN:
-    GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
-    GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
-    break;
+#if defined(BSP_USING_I2C3)
+    case (rt_uint32_t)CM_I2C3:
+        /* Configure I2C3 SDA/SCL pin. */
+        GPIO_SetFunc(I2C3_SDA_PORT, I2C3_SDA_PIN, I2C3_SDA_FUNC);
+        GPIO_SetFunc(I2C3_SCL_PORT, I2C3_SCL_PIN, I2C3_SCL_FUNC);
+        break;
 #endif
-default:
-    result = -RT_ERROR;
-    break;
+    default:
+        result = -RT_ERROR;
+        break;
    }
-
    return result;
 }
 #endif
@ -105,14 +81,114 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
    {
 #if defined(BSP_USING_ADC1)
    case (rt_uint32_t)CM_ADC1:
-        (void)GPIO_Init(ADC1_CH10_PORT, ADC1_CH10_PIN, &stcGpioInit);
-        (void)GPIO_Init(ADC1_CH12_PORT, ADC1_CH12_PIN, &stcGpioInit);
-        (void)GPIO_Init(ADC1_CH13_PORT, ADC1_CH13_PIN, &stcGpioInit);
+        (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
        break;
 #endif
 #if defined(BSP_USING_ADC2)
    case (rt_uint32_t)CM_ADC2:
-        (void)GPIO_Init(ADC2_CH7_PORT, ADC2_CH7_PIN, &stcGpioInit);
+        (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_CAN)
+void CanPhyEnable(void)
+{
+    GPIO_ResetPins(CAN1_STB_PORT, CAN1_STB_PIN);
+    GPIO_OutputCmd(CAN1_STB_PORT, CAN1_STB_PIN, ENABLE);
+}
+rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)CANx)
+    {
+#if defined(BSP_USING_CAN1)
+    case (rt_uint32_t)CM_CAN1:
+        GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+
+#if defined (RT_USING_SPI)
+rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
+{
+    rt_err_t result = RT_EOK;
+#if defined(BSP_USING_SPI3)
+    stc_gpio_init_t stcGpioInit;
+#endif
+
+    switch ((rt_uint32_t)CM_SPIx)
+    {
+#if defined(BSP_USING_SPI3)
+    case (rt_uint32_t)CM_SPI3:
+        GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinState = PIN_STAT_SET;
+        stcGpioInit.u16PinDir   = PIN_DIR_OUT;
+        GPIO_Init(SPI3_WP_PORT, SPI3_WP_PIN, &stcGpioInit);
+        GPIO_Init(SPI3_HOLD_PORT, SPI3_HOLD_PIN, &stcGpioInit);
+
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        (void)GPIO_Init(SPI3_SCK_PORT,  SPI3_SCK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SPI3_MOSI_PORT, SPI3_MOSI_PIN, &stcGpioInit);
+        (void)GPIO_Init(SPI3_MISO_PORT, SPI3_MISO_PIN, &stcGpioInit);
+        GPIO_SetFunc(SPI3_SCK_PORT,  SPI3_SCK_PIN,  SPI3_SCK_FUNC);
+        GPIO_SetFunc(SPI3_MOSI_PORT, SPI3_MOSI_PIN, SPI3_MOSI_FUNC);
+        GPIO_SetFunc(SPI3_MISO_PORT, SPI3_MISO_PIN, SPI3_MISO_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined (RT_USING_SDIO)
+rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    switch ((rt_uint32_t)SDIOCx)
+    {
+#if defined(BSP_USING_SDIO1)
+    case (rt_uint32_t)CM_SDIOC1:
+        /************************* Set pin drive capacity *************************/
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        (void)GPIO_Init(SDIOC1_CK_PORT,  SDIOC1_CK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D0_PORT,  SDIOC1_D0_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D1_PORT,  SDIOC1_D1_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D2_PORT,  SDIOC1_D2_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D3_PORT,  SDIOC1_D3_PIN,  &stcGpioInit);
+
+        GPIO_SetFunc(SDIOC1_CK_PORT,  SDIOC1_CK_PIN,  SDIOC1_CK_FUNC);
+        GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC);
+        GPIO_SetFunc(SDIOC1_D0_PORT,  SDIOC1_D0_PIN,  SDIOC1_D0_FUNC);
+        GPIO_SetFunc(SDIOC1_D1_PORT,  SDIOC1_D1_PIN,  SDIOC1_D1_FUNC);
+        GPIO_SetFunc(SDIOC1_D2_PORT,  SDIOC1_D2_PIN,  SDIOC1_D2_FUNC);
+        GPIO_SetFunc(SDIOC1_D3_PORT,  SDIOC1_D3_PIN,  SDIOC1_D3_FUNC);
        break;
 #endif
    default:
@ -125,177 +201,42 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
 #endif

 #if defined(RT_USING_PWM)
+#if defined(BSP_USING_PWM_TMRA)
 rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
 {
    rt_err_t result = RT_EOK;
    switch ((rt_uint32_t)TMRAx)
    {
-#if defined(BSP_USING_PWM_TMRA_1)
-    case (rt_uint32_t)CM_TMRA_1:
-    #ifdef BSP_USING_PWM_TMRA_1_CH1
-        GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH2
-        GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH3
-        GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH4
-        GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH5
-        GPIO_SetFunc(PWM_TMRA_1_CH5_PORT, PWM_TMRA_1_CH5_PIN, PWM_TMRA_1_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH6
-        GPIO_SetFunc(PWM_TMRA_1_CH6_PORT, PWM_TMRA_1_CH6_PIN, PWM_TMRA_1_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH7
-        GPIO_SetFunc(PWM_TMRA_1_CH7_PORT, PWM_TMRA_1_CH7_PIN, PWM_TMRA_1_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_1_CH8
-        GPIO_SetFunc(PWM_TMRA_1_CH8_PORT, PWM_TMRA_1_CH8_PIN, PWM_TMRA_1_CH8_PIN_FUNC);
-    #endif
-        break;
-#endif
-#if defined(BSP_USING_PWM_TMRA_2)
-    case (rt_uint32_t)CM_TMRA_2:
-    #ifdef BSP_USING_PWM_TMRA_2_CH1
-        GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH2
-        GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH3
-        GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH4
-        GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH5
-        GPIO_SetFunc(PWM_TMRA_2_CH5_PORT, PWM_TMRA_2_CH5_PIN, PWM_TMRA_2_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH6
-        GPIO_SetFunc(PWM_TMRA_2_CH6_PORT, PWM_TMRA_2_CH6_PIN, PWM_TMRA_2_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH7
-        GPIO_SetFunc(PWM_TMRA_2_CH7_PORT, PWM_TMRA_2_CH7_PIN, PWM_TMRA_2_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_2_CH8
-        GPIO_SetFunc(PWM_TMRA_2_CH8_PORT, PWM_TMRA_2_CH8_PIN, PWM_TMRA_2_CH8_PIN_FUNC);
-    #endif
-        break;
-#endif
-#if defined(BSP_USING_PWM_TMRA_3)
-    case (rt_uint32_t)CM_TMRA_3:
-    #ifdef BSP_USING_PWM_TMRA_3_CH1
-        GPIO_SetFunc(PWM_TMRA_3_CH1_PORT, PWM_TMRA_3_CH1_PIN, PWM_TMRA_3_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH2
-        GPIO_SetFunc(PWM_TMRA_3_CH2_PORT, PWM_TMRA_3_CH2_PIN, PWM_TMRA_3_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH3
-        GPIO_SetFunc(PWM_TMRA_3_CH3_PORT, PWM_TMRA_3_CH3_PIN, PWM_TMRA_3_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH4
-        GPIO_SetFunc(PWM_TMRA_3_CH4_PORT, PWM_TMRA_3_CH4_PIN, PWM_TMRA_3_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH5
-        GPIO_SetFunc(PWM_TMRA_3_CH5_PORT, PWM_TMRA_3_CH5_PIN, PWM_TMRA_3_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH6
-        GPIO_SetFunc(PWM_TMRA_3_CH6_PORT, PWM_TMRA_3_CH6_PIN, PWM_TMRA_3_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH7
-        GPIO_SetFunc(PWM_TMRA_3_CH7_PORT, PWM_TMRA_3_CH7_PIN, PWM_TMRA_3_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_3_CH8
-        GPIO_SetFunc(PWM_TMRA_3_CH8_PORT, PWM_TMRA_3_CH8_PIN, PWM_TMRA_3_CH8_PIN_FUNC);
-    #endif
-        break;
-#endif
 #if defined(BSP_USING_PWM_TMRA_4)
    case (rt_uint32_t)CM_TMRA_4:
-    #ifdef BSP_USING_PWM_TMRA_4_CH1
+#ifdef BSP_USING_PWM_TMRA_4_CH1
        GPIO_SetFunc(PWM_TMRA_4_CH1_PORT, PWM_TMRA_4_CH1_PIN, PWM_TMRA_4_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH2
+#endif
+#ifdef BSP_USING_PWM_TMRA_4_CH2
        GPIO_SetFunc(PWM_TMRA_4_CH2_PORT, PWM_TMRA_4_CH2_PIN, PWM_TMRA_4_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH3
+#endif
+#ifdef BSP_USING_PWM_TMRA_4_CH3
        GPIO_SetFunc(PWM_TMRA_4_CH3_PORT, PWM_TMRA_4_CH3_PIN, PWM_TMRA_4_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH4
+#endif
+#ifdef BSP_USING_PWM_TMRA_4_CH4
        GPIO_SetFunc(PWM_TMRA_4_CH4_PORT, PWM_TMRA_4_CH4_PIN, PWM_TMRA_4_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH5
-        GPIO_SetFunc(PWM_TMRA_4_CH5_PORT, PWM_TMRA_4_CH5_PIN, PWM_TMRA_4_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH6
-        GPIO_SetFunc(PWM_TMRA_4_CH6_PORT, PWM_TMRA_4_CH6_PIN, PWM_TMRA_4_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH7
-        GPIO_SetFunc(PWM_TMRA_4_CH7_PORT, PWM_TMRA_4_CH7_PIN, PWM_TMRA_4_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_4_CH8
-        GPIO_SetFunc(PWM_TMRA_4_CH8_PORT, PWM_TMRA_4_CH8_PIN, PWM_TMRA_4_CH8_PIN_FUNC);
-    #endif
+#endif
        break;
 #endif
 #if defined(BSP_USING_PWM_TMRA_5)
    case (rt_uint32_t)CM_TMRA_5:
-    #ifdef BSP_USING_PWM_TMRA_5_CH1
+#ifdef BSP_USING_PWM_TMRA_5_CH1
        GPIO_SetFunc(PWM_TMRA_5_CH1_PORT, PWM_TMRA_5_CH1_PIN, PWM_TMRA_5_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH2
-        GPIO_SetFunc(PWM_TMRA_5_CH2_PORT, PWM_TMRA_5_CH2_PIN, PWM_TMRA_5_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH3
-        GPIO_SetFunc(PWM_TMRA_5_CH3_PORT, PWM_TMRA_5_CH3_PIN, PWM_TMRA_5_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH4
-        GPIO_SetFunc(PWM_TMRA_5_CH4_PORT, PWM_TMRA_5_CH4_PIN, PWM_TMRA_5_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH5
-        GPIO_SetFunc(PWM_TMRA_5_CH5_PORT, PWM_TMRA_5_CH5_PIN, PWM_TMRA_5_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH6
-        GPIO_SetFunc(PWM_TMRA_5_CH6_PORT, PWM_TMRA_5_CH6_PIN, PWM_TMRA_5_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH7
-        GPIO_SetFunc(PWM_TMRA_5_CH7_PORT, PWM_TMRA_5_CH7_PIN, PWM_TMRA_5_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_5_CH8
-        GPIO_SetFunc(PWM_TMRA_5_CH8_PORT, PWM_TMRA_5_CH8_PIN, PWM_TMRA_5_CH8_PIN_FUNC);
-    #endif
-        break;
 #endif
-#if defined(BSP_USING_PWM_TMRA_6)
-    case (rt_uint32_t)CM_TMRA_6:
-    #ifdef BSP_USING_PWM_TMRA_6_CH1
-        GPIO_SetFunc(PWM_TMRA_6_CH1_PORT, PWM_TMRA_6_CH1_PIN, PWM_TMRA_6_CH1_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH2
-        GPIO_SetFunc(PWM_TMRA_6_CH2_PORT, PWM_TMRA_6_CH2_PIN, PWM_TMRA_6_CH2_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH3
-        GPIO_SetFunc(PWM_TMRA_6_CH3_PORT, PWM_TMRA_6_CH3_PIN, PWM_TMRA_6_CH3_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH4
-        GPIO_SetFunc(PWM_TMRA_6_CH4_PORT, PWM_TMRA_6_CH4_PIN, PWM_TMRA_6_CH4_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH5
-        GPIO_SetFunc(PWM_TMRA_6_CH5_PORT, PWM_TMRA_6_CH5_PIN, PWM_TMRA_6_CH5_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH6
-        GPIO_SetFunc(PWM_TMRA_6_CH6_PORT, PWM_TMRA_6_CH6_PIN, PWM_TMRA_6_CH6_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH7
-        GPIO_SetFunc(PWM_TMRA_6_CH7_PORT, PWM_TMRA_6_CH7_PIN, PWM_TMRA_6_CH7_PIN_FUNC);
-    #endif
-    #ifdef BSP_USING_PWM_TMRA_6_CH8
-        GPIO_SetFunc(PWM_TMRA_6_CH8_PORT, PWM_TMRA_6_CH8_PIN, PWM_TMRA_6_CH8_PIN_FUNC);
-    #endif
+#ifdef BSP_USING_PWM_TMRA_5_CH2
+        GPIO_SetFunc(PWM_TMRA_5_CH2_PORT, PWM_TMRA_5_CH2_PIN, PWM_TMRA_5_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_5_CH3
+        GPIO_SetFunc(PWM_TMRA_5_CH3_PORT, PWM_TMRA_5_CH3_PIN, PWM_TMRA_5_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_5_CH4
+        GPIO_SetFunc(PWM_TMRA_5_CH4_PORT, PWM_TMRA_5_CH4_PIN, PWM_TMRA_5_CH4_PIN_FUNC);
+#endif
        break;
 #endif
    default:
@ -306,3 +247,154 @@ rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
    return result;
 }
 #endif
+
+#if defined(BSP_USING_PWM_TMR4)
+rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR4x)
+    {
+#if defined(BSP_USING_PWM_TMR4_1)
+    case (rt_uint32_t)CM_TMR4_1:
+#ifdef BSP_USING_PWM_TMR4_1_OUH
+        GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OUL
+        GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVH
+        GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVL
+        GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWH
+        GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWL
+        GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR6)
+rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR6x)
+    {
+#if defined(BSP_USING_PWM_TMR6_1)
+    case (rt_uint32_t)CM_TMR6_1:
+#ifdef BSP_USING_PWM_TMR6_1_A
+        GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR6_1_B
+        GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+#endif
+
+#ifdef RT_USING_PM
+void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
+{
+    switch (run_mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        SystemClock_Config();
+        break;
+
+    case PM_RUN_MODE_LOW_SPEED:
+        CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
+
+    default:
+        break;
+    }
+}
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+rt_err_t rt_hw_usb_board_init(void)
+{
+    stc_gpio_init_t stcGpioCfg;
+    (void)GPIO_StructInit(&stcGpioCfg);
+#if defined(BSP_USING_USBFS)
+    stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG;
+    (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg);
+#if defined(BSP_USING_USBD)
+    GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */
+#endif
+#if defined(BSP_USING_USBH)
+    GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */
+#endif
+#endif
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_QSPI)
+rt_err_t rt_hw_qspi_board_init(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+#ifndef BSP_QSPI_USING_SOFT_CS
+    (void)GPIO_Init(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  QSPI_FLASH_CS_FUNC);
+#endif
+    (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMRA_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
+#endif
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMR6_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
+#endif
+
+    return RT_EOK;
+}
+#endif
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
@ -1,14 +1,11 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2022-04-28     CDT          first version
- * 2022-06-16     lianghongquan     use macro definition config adc pin.
- * 2022-06-28     lianghongquan     add PWM_TMRA pin define.
 */


@ -20,81 +17,296 @@
 #include "drv_config.h"


+/************************* XTAL port **********************/
+#define XTAL_PORT                       (GPIO_PORT_H)
+#define XTAL_IN_PIN                     (GPIO_PIN_01)
+#define XTAL_OUT_PIN                    (GPIO_PIN_00)
+
 /************************ USART port **********************/
-#if defined(BSP_USING_UART1)
-    #define USART1_RX_PORT                  (GPIO_PORT_C)
-    #define USART1_RX_PIN                   (GPIO_PIN_04)
-
-    #define USART1_TX_PORT                  (GPIO_PORT_A)
-    #define USART1_TX_PIN                   (GPIO_PIN_07)
-#endif
-
 #if defined(BSP_USING_UART2)
    #define USART2_RX_PORT                  (GPIO_PORT_A)
    #define USART2_RX_PIN                   (GPIO_PIN_03)
+    #define USART2_RX_FUNC                  (GPIO_FUNC_37)

    #define USART2_TX_PORT                  (GPIO_PORT_A)
    #define USART2_TX_PIN                   (GPIO_PIN_02)
-#endif
-
-#if defined(BSP_USING_UART3)
-    #define USART3_RX_PORT                  (GPIO_PORT_C)
-    #define USART3_RX_PIN                   (GPIO_PIN_13)
-
-    #define USART3_TX_PORT                  (GPIO_PORT_H)
-    #define USART3_TX_PIN                   (GPIO_PIN_02)
+    #define USART2_TX_FUNC                  (GPIO_FUNC_36)
 #endif

 #if defined(BSP_USING_UART4)
    #define USART4_RX_PORT                  (GPIO_PORT_B)
    #define USART4_RX_PIN                   (GPIO_PIN_09)
+    #define USART4_RX_FUNC                  (GPIO_FUNC_37)

    #define USART4_TX_PORT                  (GPIO_PORT_E)
    #define USART4_TX_PIN                   (GPIO_PIN_06)
+    #define USART4_TX_FUNC                  (GPIO_FUNC_36)
 #endif

-/***********  CAN configure *********/
-#if defined(BSP_USING_CAN1)
-    #define CAN1_TX_PORT                     (GPIO_PORT_B)
-    #define CAN1_TX_PIN                      (GPIO_PIN_07)
-    #define CAN1_TX_PIN_FUNC                 (GPIO_FUNC_50)
+/************************ I2C port **********************/
+#if defined(BSP_USING_I2C3)
+    #define I2C3_SDA_PORT                   (GPIO_PORT_B)
+    #define I2C3_SDA_PIN                    (GPIO_PIN_05)
+    #define I2C3_SDA_FUNC                   (GPIO_FUNC_48)

-    #define CAN1_RX_PORT                     (GPIO_PORT_B)
-    #define CAN1_RX_PIN                      (GPIO_PIN_06)
-    #define CAN1_RX_PIN_FUNC                 (GPIO_FUNC_51)
-
-    #define CAN1_STB_FUNC_ENABLE
-    #define CAN_STB_PORT                     (GPIO_PORT_D)
-    #define CAN_STB_PIN                      (GPIO_PIN_15)
+    #define I2C3_SCL_PORT                   (GPIO_PORT_E)
+    #define I2C3_SCL_PIN                    (GPIO_PIN_15)
+    #define I2C3_SCL_FUNC                   (GPIO_FUNC_49)
 #endif

 /***********  ADC configure *********/
 #if defined(BSP_USING_ADC1)
-    #define ADC1_CH10_PORT                     (GPIO_PORT_C)
-    #define ADC1_CH10_PIN                      (GPIO_PIN_00)
-
-    #define ADC1_CH12_PORT                     (GPIO_PORT_C)
-    #define ADC1_CH12_PIN                      (GPIO_PIN_02)
-
-    #define ADC1_CH13_PORT                     (GPIO_PORT_C)
-    #define ADC1_CH13_PIN                      (GPIO_PIN_03)
+    #define ADC1_CH_PORT                    (GPIO_PORT_C)
+    #define ADC1_CH_PIN                     (GPIO_PIN_00)
 #endif

 #if defined(BSP_USING_ADC2)
-    //ADC2 has 7 channels CH0-CH7. ADC12_IN4-ADC12_IN11 means ADC2 CH0-CH7
-    #define ADC2_CH7_PORT                     (GPIO_PORT_C)
-    #define ADC2_CH7_PIN                      (GPIO_PIN_01)
+    #define ADC2_CH_PORT                    (GPIO_PORT_C)
+    #define ADC2_CH_PIN                     (GPIO_PIN_01)
 #endif

-/***********  PWM_TMRA configure *********/
-#if defined(BSP_USING_PWM_TMRA_4)
-    #define PWM_TMRA_4_CH7_PORT             (GPIO_PORT_H)
-    #define PWM_TMRA_4_CH7_PIN              (GPIO_PIN_02)
-    #define PWM_TMRA_4_CH7_PIN_FUNC         (GPIO_FUNC_4)
+/***********  CAN configure *********/
+#if defined(BSP_USING_CAN1)
+    #define CAN1_TX_PORT                    (GPIO_PORT_B)
+    #define CAN1_TX_PIN                     (GPIO_PIN_07)
+    #define CAN1_TX_PIN_FUNC                (GPIO_FUNC_50)

-    #define PWM_TMRA_4_CH8_PORT             (GPIO_PORT_C)
-    #define PWM_TMRA_4_CH8_PIN              (GPIO_PIN_13)
-    #define PWM_TMRA_4_CH8_PIN_FUNC         (GPIO_FUNC_4)
+    #define CAN1_RX_PORT                    (GPIO_PORT_B)
+    #define CAN1_RX_PIN                     (GPIO_PIN_06)
+    #define CAN1_RX_PIN_FUNC                (GPIO_FUNC_51)
+
+    #define CAN1_STB_PORT                   (GPIO_PORT_D)
+    #define CAN1_STB_PIN                    (GPIO_PIN_15)
 #endif

+/************************* SPI port ***********************/
+#if defined(BSP_USING_SPI3)
+    #define SPI3_CS_PORT                (GPIO_PORT_C)
+    #define SPI3_CS_PIN                 (GPIO_PIN_07)
+
+    #define SPI3_SCK_PORT               (GPIO_PORT_C)
+    #define SPI3_SCK_PIN                (GPIO_PIN_06)
+    #define SPI3_SCK_FUNC               (GPIO_FUNC_43)
+
+    #define SPI3_MOSI_PORT              (GPIO_PORT_D)
+    #define SPI3_MOSI_PIN               (GPIO_PIN_08)
+    #define SPI3_MOSI_FUNC              (GPIO_FUNC_40)
+
+    #define SPI3_MISO_PORT              (GPIO_PORT_D)
+    #define SPI3_MISO_PIN               (GPIO_PIN_09)
+    #define SPI3_MISO_FUNC              (GPIO_FUNC_41)
+
+    #define SPI3_WP_PORT                (GPIO_PORT_D)
+    #define SPI3_WP_PIN                 (GPIO_PIN_10)
+
+    #define SPI3_HOLD_PORT              (GPIO_PORT_D)
+    #define SPI3_HOLD_PIN               (GPIO_PIN_11)
 #endif
+
+/************************ SDIOC port **********************/
+#if defined(BSP_USING_SDIO1)
+    #define SDIOC1_CK_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_CK_PIN                   (GPIO_PIN_12)
+    #define SDIOC1_CK_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_CMD_PORT                 (GPIO_PORT_D)
+    #define SDIOC1_CMD_PIN                  (GPIO_PIN_02)
+    #define SDIOC1_CMD_FUNC                 (GPIO_FUNC_9)
+
+    #define SDIOC1_D0_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_D0_PIN                   (GPIO_PIN_08)
+    #define SDIOC1_D0_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D1_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_D1_PIN                   (GPIO_PIN_09)
+    #define SDIOC1_D1_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D2_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_D2_PIN                   (GPIO_PIN_10)
+    #define SDIOC1_D2_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D3_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_D3_PIN                   (GPIO_PIN_11)
+    #define SDIOC1_D3_FUNC                  (GPIO_FUNC_9)
+#endif
+
+/************************ RTC/PM *****************************/
+#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
+    #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+        #define XTAL32_PORT                     (GPIO_PORT_C)
+        #define XTAL32_IN_PIN                   (GPIO_PIN_15)
+        #define XTAL32_OUT_PIN                  (GPIO_PIN_14)
+    #endif
+#endif
+
+#if defined(RT_USING_PWM)
+    /***********  PWM_TMRA configure *********/
+    #if defined(BSP_USING_PWM_TMRA_4)
+        #if defined(BSP_USING_PWM_TMRA_4_CH1)
+            #define PWM_TMRA_4_CH1_PORT             (GPIO_PORT_D)
+            #define PWM_TMRA_4_CH1_PIN              (GPIO_PIN_12)
+            #define PWM_TMRA_4_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_4_CH2)
+            #define PWM_TMRA_4_CH2_PORT             (GPIO_PORT_D)
+            #define PWM_TMRA_4_CH2_PIN              (GPIO_PIN_13)
+            #define PWM_TMRA_4_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_4_CH3)
+            #define PWM_TMRA_4_CH3_PORT             (GPIO_PORT_D)
+            #define PWM_TMRA_4_CH3_PIN              (GPIO_PIN_14)
+            #define PWM_TMRA_4_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_4_CH4)
+            #define PWM_TMRA_4_CH4_PORT             (GPIO_PORT_D)
+            #define PWM_TMRA_4_CH4_PIN              (GPIO_PIN_15)
+            #define PWM_TMRA_4_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    #if defined(BSP_USING_PWM_TMRA_5)
+        #if defined(BSP_USING_PWM_TMRA_5_CH1)
+            #define PWM_TMRA_5_CH1_PORT             (GPIO_PORT_C)
+            #define PWM_TMRA_5_CH1_PIN              (GPIO_PIN_10)
+            #define PWM_TMRA_5_CH1_PIN_FUNC         (GPIO_FUNC_5)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_5_CH2)
+            #define PWM_TMRA_5_CH2_PORT             (GPIO_PORT_C)
+            #define PWM_TMRA_5_CH2_PIN              (GPIO_PIN_11)
+            #define PWM_TMRA_5_CH2_PIN_FUNC         (GPIO_FUNC_5)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_5_CH3)
+            #define PWM_TMRA_5_CH3_PORT             (GPIO_PORT_C)
+            #define PWM_TMRA_5_CH3_PIN              (GPIO_PIN_12)
+            #define PWM_TMRA_5_CH3_PIN_FUNC         (GPIO_FUNC_5)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_5_CH4)
+            #define PWM_TMRA_5_CH4_PORT             (GPIO_PORT_D)
+            #define PWM_TMRA_5_CH4_PIN              (GPIO_PIN_00)
+            #define PWM_TMRA_5_CH4_PIN_FUNC         (GPIO_FUNC_5)
+        #endif
+    #endif
+
+    /***********  PWM_TMR4 configure *********/
+    #if defined(BSP_USING_PWM_TMR4_1)
+        #if defined(BSP_USING_PWM_TMR4_1_OUH)
+            #define PWM_TMR4_1_OUH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OUH_PIN              (GPIO_PIN_09)
+            #define PWM_TMR4_1_OUH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OUL)
+            #define PWM_TMR4_1_OUL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OUL_PIN              (GPIO_PIN_08)
+            #define PWM_TMR4_1_OUL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVH)
+            #define PWM_TMR4_1_OVH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OVH_PIN              (GPIO_PIN_11)
+            #define PWM_TMR4_1_OVH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVL)
+            #define PWM_TMR4_1_OVL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OVL_PIN              (GPIO_PIN_10)
+            #define PWM_TMR4_1_OVL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWH)
+            #define PWM_TMR4_1_OWH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OWH_PIN              (GPIO_PIN_13)
+            #define PWM_TMR4_1_OWH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWL)
+            #define PWM_TMR4_1_OWL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OWL_PIN              (GPIO_PIN_12)
+            #define PWM_TMR4_1_OWL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+    #endif
+
+    /***********  PWM_TMR6 configure *********/
+    #if defined(BSP_USING_PWM_TMR6_1)
+        #if defined(BSP_USING_PWM_TMR6_1_A)
+            #define PWM_TMR6_1_A_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_A_PIN                (GPIO_PIN_08)
+            #define PWM_TMR6_1_A_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+        #if defined(BSP_USING_PWM_TMR6_1_B)
+            #define PWM_TMR6_1_B_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_B_PIN                (GPIO_PIN_07)
+            #define PWM_TMR6_1_B_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+    #endif
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    #if defined(BSP_USING_USBFS)
+        /* USBFS Core*/
+        #define USBF_DP_PORT                    (GPIO_PORT_A)
+        #define USBF_DP_PIN                     (GPIO_PIN_12)
+        #define USBF_DP_FUNC                    (GPIO_FUNC_10)
+        #define USBF_DM_PORT                    (GPIO_PORT_A)
+        #define USBF_DM_PIN                     (GPIO_PIN_11)
+        #define USBF_DM_FUNC                    (GPIO_FUNC_10)
+        #define USBF_VBUS_PORT                  (GPIO_PORT_A)
+        #define USBF_VBUS_PIN                   (GPIO_PIN_09)
+        #define USBF_VBUS_FUNC                  (GPIO_FUNC_10)
+        #define USBF_DRVVBUS_PORT               (GPIO_PORT_B)
+        #define USBF_DRVVBUS_PIN                (GPIO_PIN_08)
+        #define USBF_DRVVBUS_FUNC               (GPIO_FUNC_10)
+    #endif
+#endif
+
+#if defined(BSP_USING_QSPI)
+    #ifndef BSP_QSPI_USING_SOFT_CS
+        /* QSSN */
+        #define QSPI_FLASH_CS_PORT              (GPIO_PORT_C)
+        #define QSPI_FLASH_CS_PIN               (GPIO_PIN_07)
+        #define QSPI_FLASH_CS_FUNC              (GPIO_FUNC_7)
+    #endif
+    /* QSCK */
+    #define QSPI_FLASH_SCK_PORT             (GPIO_PORT_C)
+    #define QSPI_FLASH_SCK_PIN              (GPIO_PIN_06)
+    #define QSPI_FLASH_SCK_FUNC             (GPIO_FUNC_7)
+    /* QSIO0 */
+    #define QSPI_FLASH_IO0_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO0_PIN              (GPIO_PIN_08)
+    #define QSPI_FLASH_IO0_FUNC             (GPIO_FUNC_7)
+    /* QSIO1 */
+    #define QSPI_FLASH_IO1_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO1_PIN              (GPIO_PIN_09)
+    #define QSPI_FLASH_IO1_FUNC             (GPIO_FUNC_7)
+    /* QSIO2 */
+    #define QSPI_FLASH_IO2_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO2_PIN              (GPIO_PIN_10)
+    #define QSPI_FLASH_IO2_FUNC             (GPIO_FUNC_7)
+    /* QSIO3 */
+    #define QSPI_FLASH_IO3_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO3_PIN              (GPIO_PIN_11)
+    #define QSPI_FLASH_IO3_FUNC             (GPIO_FUNC_7)
+#endif
+
+/*********** TMRA_PULSE_ENCODER configure *********/
+#if defined(RT_USING_PULSE_ENCODER)
+    #if defined(BSP_USING_TMRA_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+            #define PULSE_ENCODER_TMRA_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC  (GPIO_FUNC_4)
+            #define PULSE_ENCODER_TMRA_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_B_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC  (GPIO_FUNC_4)
+        #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+    #endif /* BSP_USING_TMRA_PULSE_ENCODER */
+
+    #if defined(BSP_USING_TMR6_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+            #define PULSE_ENCODER_TMR6_1_A_PORT      (GPIO_PORT_E)
+            #define PULSE_ENCODER_TMR6_1_A_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC  (GPIO_FUNC_3)
+            #define PULSE_ENCODER_TMR6_1_B_PORT      (GPIO_PORT_E)
+            #define PULSE_ENCODER_TMR6_1_B_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC  (GPIO_FUNC_3)
+        #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+    #endif /* BSP_USING_TMR6_PULSE_ENCODER */
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif
+
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h
@ -1,13 +1,11 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
- * Copyright (c) 2022, xiaoxiaolisunny
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
- * Date           Author                   Notes
- * 2022-06-07     xiaoxiaolisunny          first version
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
 */

 #ifndef __ADC_CONFIG_H__
@ -25,6 +23,7 @@ extern "C" {
 #define ADC1_INIT_PARAMS                                                        \
    {                                                                           \
       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
       .resolution                      = ADC_RESOLUTION_12BIT,                 \
       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
       .eoc_poll_time_max               = 100,                                  \
@ -47,6 +46,7 @@ extern "C" {
 #define ADC2_INIT_PARAMS                                                        \
    {                                                                           \
       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
       .resolution                      = ADC_RESOLUTION_12BIT,                 \
       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
       .eoc_poll_time_max               = 100,                                  \
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h
@ -1,13 +1,11 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
- * Copyright (c) 2022, xiaoxiaolisunny
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
- * Date           Author                   Notes
- * 2022-06-07     xiaoxiaolisunny          first version
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
 */

 #ifndef __CAN_CONFIG_H__
@ -21,10 +19,16 @@ extern "C" {
 #endif

 #ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME                       ("can1")
 #ifndef CAN1_INIT_PARAMS
 #define CAN1_INIT_PARAMS                                    \
    {                                                       \
-       .name = "can1",                                      \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
    }
 #endif /* CAN1_INIT_PARAMS */
 #endif /* BSP_USING_CAN1 */
@ -34,80 +38,80 @@ extern "C" {

  Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
  TQ = u32Prescaler / CANClock.
-  Bit time = (u32TimeSeg1 + u32TimeSeg2) x TQ.
+  Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.

-  The following bit time configures are based on CAN Clock 8M
+  The following bit time configures are based on CAN Clock 40M
 */
 #define CAN_BIT_TIME_CONFIG_1M_BAUD                         \
    {                                                       \
-        .u32Prescaler = 1,                                  \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_800K_BAUD                       \
    {                                                       \
-        .u32Prescaler = 1,                                  \
-        .u32TimeSeg1 = 6,                                  \
-        .u32TimeSeg2 = 4,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 20,                                  \
+        .u32TimeSeg2 = 5,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_500K_BAUD                       \
    {                                                       \
-        .u32Prescaler = 2,                                  \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 4,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_250K_BAUD                       \
    {                                                       \
-        .u32Prescaler = 4,                                  \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 8,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_125K_BAUD                       \
    {                                                       \
-        .u32Prescaler = 8,                                 \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 16,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_100K_BAUD                       \
    {                                                       \
-        .u32Prescaler = 10,                                 \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 20,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_50K_BAUD                        \
    {                                                       \
-        .u32Prescaler = 20,                                 \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 40,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_20K_BAUD                        \
    {                                                       \
-        .u32Prescaler = 50,                                \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 100,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #define CAN_BIT_TIME_CONFIG_10K_BAUD                        \
    {                                                       \
-        .u32Prescaler = 100,                                \
-        .u32TimeSeg1 = 5,                                  \
-        .u32TimeSeg2 = 3,                                   \
-        .u32SJW = 3                                         \
+        .u32Prescaler = 200,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
    }

 #ifdef __cplusplus
@ -115,5 +119,3 @@ extern "C" {
 #endif

 #endif /* __CAN_CONFIG_H__ */
-
-
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -25,19 +24,37 @@ extern "C" {
 #define SPI1_RX_DMA_CHANNEL             DMA_CH0
 #define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
 #define SPI1_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
 #define SPI1_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
 #define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
-#endif
-
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
-#define SPI3_RX_DMA_INSTANCE            CM_DMA1
-#define SPI3_RX_DMA_CHANNEL             DMA_CH0
-#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
-#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_0
-#define SPI3_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
-#define SPI3_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
-#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE)
+#define SDIO1_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_RX_DMA_CHANNEL            DMA_CH0
+#define SDIO1_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_RX_DMA_TRIG_SELECT        AOS_DMA1_0
+#define SDIO1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define SDIO1_RX_DMA_IRQn               BSP_DMA1_CH0_IRQ_NUM
+#define SDIO1_RX_DMA_INT_PRIO           BSP_DMA1_CH0_IRQ_PRIO
+#define SDIO1_RX_DMA_INT_SRC            INT_SRC_DMA1_TC0
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE            CM_DMA1
+#define I2C1_TX_DMA_CHANNEL             DMA_CH0
+#define I2C1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           CM_DMA1
+#define UART1_RX_DMA_CHANNEL            DMA_CH0
+#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA1_0
+#define UART1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define UART1_RX_DMA_IRQn               BSP_DMA1_CH0_IRQ_NUM
+#define UART1_RX_DMA_INT_PRIO           BSP_DMA1_CH0_IRQ_PRIO
+#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA1_TC0
 #endif

 /* DMA1 ch1 */
@ -46,19 +63,37 @@ extern "C" {
 #define SPI1_TX_DMA_CHANNEL             DMA_CH1
 #define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
 #define SPI1_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
 #define SPI1_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
 #define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
-#endif
-
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
-#define SPI3_TX_DMA_INSTANCE            CM_DMA1
-#define SPI3_TX_DMA_CHANNEL             DMA_CH1
-#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
-#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_1
-#define SPI3_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
-#define SPI3_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
-#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE)
+#define SDIO1_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_TX_DMA_CHANNEL            DMA_CH1
+#define SDIO1_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_TX_DMA_TRIG_SELECT        AOS_DMA1_1
+#define SDIO1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define SDIO1_TX_DMA_IRQn               BSP_DMA1_CH1_IRQ_NUM
+#define SDIO1_TX_DMA_INT_PRIO           BSP_DMA1_CH1_IRQ_PRIO
+#define SDIO1_TX_DMA_INT_SRC            INT_SRC_DMA1_TC1
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE            CM_DMA1
+#define I2C1_RX_DMA_CHANNEL             DMA_CH1
+#define I2C1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE           CM_DMA1
+#define UART2_RX_DMA_CHANNEL            DMA_CH1
+#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA1_1
+#define UART2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define UART2_RX_DMA_IRQn               BSP_DMA1_CH1_IRQ_NUM
+#define UART2_RX_DMA_INT_PRIO           BSP_DMA1_CH1_IRQ_PRIO
+#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA1_TC1
 #endif

 /* DMA1 ch2 */
@ -67,19 +102,37 @@ extern "C" {
 #define SPI2_RX_DMA_CHANNEL             DMA_CH2
 #define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
 #define SPI2_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
 #define SPI2_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
 #define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
-#endif
-
-#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_RX_DMA_INSTANCE            CM_DMA1
-#define SPI4_RX_DMA_CHANNEL             DMA_CH2
-#define SPI4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
-#define SPI4_RX_DMA_TRIG_SELECT         AOS_DMA1_2
-#define SPI4_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
-#define SPI4_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
-#define SPI4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE)
+#define SDIO2_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_RX_DMA_CHANNEL            DMA_CH2
+#define SDIO2_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_RX_DMA_TRIG_SELECT        AOS_DMA1_2
+#define SDIO2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define SDIO2_RX_DMA_IRQn               BSP_DMA1_CH2_IRQ_NUM
+#define SDIO2_RX_DMA_INT_PRIO           BSP_DMA1_CH2_IRQ_PRIO
+#define SDIO2_RX_DMA_INT_SRC            INT_SRC_DMA1_TC2
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE            CM_DMA1
+#define I2C2_TX_DMA_CHANNEL             DMA_CH2
+#define I2C2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_RX_DMA_INSTANCE           CM_DMA1
+#define UART3_RX_DMA_CHANNEL            DMA_CH2
+#define UART3_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART3_RX_DMA_TRIG_SELECT        AOS_DMA1_2
+#define UART3_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define UART3_RX_DMA_IRQn               BSP_DMA1_CH2_IRQ_NUM
+#define UART3_RX_DMA_INT_PRIO           BSP_DMA1_CH2_IRQ_PRIO
+#define UART3_RX_DMA_INT_SRC            INT_SRC_DMA1_TC2
 #endif

 /* DMA1 ch3 */
@ -88,100 +141,145 @@ extern "C" {
 #define SPI2_TX_DMA_CHANNEL             DMA_CH3
 #define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
 #define SPI2_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
 #define SPI2_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
 #define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
-#endif
-
-#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_TX_DMA_INSTANCE            CM_DMA1
-#define SPI4_TX_DMA_CHANNEL             DMA_CH3
-#define SPI4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
-#define SPI4_TX_DMA_TRIG_SELECT         AOS_DMA1_3
-#define SPI4_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
-#define SPI4_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
-#define SPI4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE)
+#define SDIO2_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_TX_DMA_CHANNEL            DMA_CH3
+#define SDIO2_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_TX_DMA_TRIG_SELECT        AOS_DMA1_3
+#define SDIO2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define SDIO2_TX_DMA_IRQn               BSP_DMA1_CH3_IRQ_NUM
+#define SDIO2_TX_DMA_INT_PRIO           BSP_DMA1_CH3_IRQ_PRIO
+#define SDIO2_TX_DMA_INT_SRC            INT_SRC_DMA1_TC3
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE            CM_DMA1
+#define I2C2_RX_DMA_CHANNEL             DMA_CH3
+#define I2C2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_RX_DMA_INSTANCE           CM_DMA1
+#define UART4_RX_DMA_CHANNEL            DMA_CH3
+#define UART4_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART4_RX_DMA_TRIG_SELECT        AOS_DMA1_3
+#define UART4_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define UART4_RX_DMA_IRQn               BSP_DMA1_CH3_IRQ_NUM
+#define UART4_RX_DMA_INT_PRIO           BSP_DMA1_CH3_IRQ_PRIO
+#define UART4_RX_DMA_INT_SRC            INT_SRC_DMA1_TC3
 #endif

 /* DMA2 ch0 */
-#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_RX_DMA_INSTANCE           CM_DMA2
-#define UART1_RX_DMA_CHANNEL            DMA_CH0
-#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
-#define UART1_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
-#define UART1_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
-#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
-#endif
-
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
-#define UART3_RX_DMA_INSTANCE           CM_DMA2
-#define UART3_RX_DMA_CHANNEL            DMA_CH0
-#define UART3_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART3_RX_DMA_TRIG_SELECT        AOS_DMA2_0
-#define UART3_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
-#define UART3_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
-#define UART3_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            CM_DMA2
+#define SPI3_RX_DMA_CHANNEL             DMA_CH0
+#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA2_0
+#define SPI3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI3_RX_DMA_IRQn                BSP_DMA2_CH0_IRQ_NUM
+#define SPI3_RX_DMA_INT_PRIO            BSP_DMA2_CH0_IRQ_PRIO
+#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA2_TC0
+#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
+#define I2C3_TX_DMA_INSTANCE            CM_DMA2
+#define I2C3_TX_DMA_CHANNEL             DMA_CH0
+#define I2C3_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C3_TX_DMA_TRIG_SELECT         AOS_DMA2_0
+#define I2C3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C3_TX_DMA_IRQn                BSP_DMA2_CH0_IRQ_NUM
+#define I2C3_TX_DMA_INT_PRIO            BSP_DMA2_CH0_IRQ_PRIO
+#define I2C3_TX_DMA_INT_SRC             INT_SRC_DMA2_TC0
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           CM_DMA2
+#define UART1_TX_DMA_CHANNEL            DMA_CH0
+#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define UART1_TX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
+#define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
+#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC0
 #endif

 /* DMA2 ch1 */
-#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
-#define UART1_TX_DMA_INSTANCE           CM_DMA2
-#define UART1_TX_DMA_CHANNEL            DMA_CH1
-#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
-#define UART1_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
-#define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
-#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
-#endif
-
-#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
-#define UART3_TX_DMA_INSTANCE           CM_DMA2
-#define UART3_TX_DMA_CHANNEL            DMA_CH1
-#define UART3_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART3_TX_DMA_TRIG_SELECT        AOS_DMA2_1
-#define UART3_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
-#define UART3_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
-#define UART3_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            CM_DMA2
+#define SPI3_TX_DMA_CHANNEL             DMA_CH1
+#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA2_1
+#define SPI3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI3_TX_DMA_IRQn                BSP_DMA2_CH1_IRQ_NUM
+#define SPI3_TX_DMA_INT_PRIO            BSP_DMA2_CH1_IRQ_PRIO
+#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA2_TC1
+#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
+#define I2C3_RX_DMA_INSTANCE            CM_DMA2
+#define I2C3_RX_DMA_CHANNEL             DMA_CH1
+#define I2C3_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C3_RX_DMA_TRIG_SELECT         AOS_DMA2_1
+#define I2C3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C3_RX_DMA_IRQn                BSP_DMA2_CH1_IRQ_NUM
+#define I2C3_RX_DMA_INT_PRIO            BSP_DMA2_CH1_IRQ_PRIO
+#define I2C3_RX_DMA_INT_SRC             INT_SRC_DMA2_TC1
+#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           CM_DMA2
+#define UART2_TX_DMA_CHANNEL            DMA_CH1
+#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define UART2_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
+#define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
+#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
 #endif

 /* DMA2 ch2 */
-#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
-#define UART2_RX_DMA_INSTANCE           CM_DMA2
-#define UART2_RX_DMA_CHANNEL            DMA_CH2
-#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
-#define UART2_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
-#define UART2_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
-#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
-#endif
-
-#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
-#define UART4_RX_DMA_INSTANCE           CM_DMA2
-#define UART4_RX_DMA_CHANNEL            DMA_CH2
-#define UART4_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART4_RX_DMA_TRIG_SELECT        AOS_DMA2_2
-#define UART4_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
-#define UART4_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
-#define UART4_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_RX_DMA_INSTANCE            CM_DMA2
+#define SPI4_RX_DMA_CHANNEL             DMA_CH2
+#define SPI4_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define SPI4_RX_DMA_TRIG_SELECT         AOS_DMA2_2
+#define SPI4_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define SPI4_RX_DMA_IRQn                BSP_DMA2_CH2_IRQ_NUM
+#define SPI4_RX_DMA_INT_PRIO            BSP_DMA2_CH2_IRQ_PRIO
+#define SPI4_RX_DMA_INT_SRC             INT_SRC_DMA2_TC2
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_TX_DMA_INSTANCE           CM_DMA2
+#define UART3_TX_DMA_CHANNEL            DMA_CH2
+#define UART3_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART3_TX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART3_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define UART3_TX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
+#define UART3_TX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
+#define UART3_TX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_INSTANCE               CM_DMA2
+#define QSPI_DMA_CHANNEL                DMA_CH2
+#define QSPI_DMA_CLOCK                  (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define QSPI_DMA_TRIG_SELECT            AOS_DMA2_2
+#define QSPI_DMA_TRANS_FLAG             DMA_FLAG_TC_CH2
+#define QSPI_DMA_IRQn                   BSP_DMA2_CH2_IRQ_NUM
+#define QSPI_DMA_INT_PRIO               BSP_DMA2_CH2_IRQ_PRIO
+#define QSPI_DMA_INT_SRC                INT_SRC_DMA2_TC2
 #endif

 /* DMA2 ch3 */
-#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
-#define UART2_TX_DMA_INSTANCE           CM_DMA2
-#define UART2_TX_DMA_CHANNEL            DMA_CH3
-#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
-#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
-#define UART2_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
-#define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
-#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
-#endif
-
-#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_TX_DMA_INSTANCE            CM_DMA2
+#define SPI4_TX_DMA_CHANNEL             DMA_CH3
+#define SPI4_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define SPI4_TX_DMA_TRIG_SELECT         AOS_DMA2_3
+#define SPI4_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define SPI4_TX_DMA_IRQn                BSP_DMA2_CH3_IRQ_NUM
+#define SPI4_TX_DMA_INT_PRIO            BSP_DMA2_CH3_IRQ_PRIO
+#define SPI4_TX_DMA_INT_SRC             INT_SRC_DMA2_TC3
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
 #define UART4_TX_DMA_INSTANCE           CM_DMA2
 #define UART4_TX_DMA_CHANNEL            DMA_CH3
 #define UART4_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART4_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART4_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
 #define UART4_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
 #define UART4_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
 #define UART4_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h
@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c1",                                     \
+        .Instance = CM_I2C1,                                    \
+        .clock    = FCG1_PERIPH_I2C1,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_TX_DMA_INSTANCE,                 \
+        .channel        = I2C1_TX_DMA_CHANNEL,                  \
+        .clock          = I2C1_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_TEI,                     \
+        .flag           = I2C1_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_RX_DMA_INSTANCE,                 \
+        .channel        = I2C1_RX_DMA_CHANNEL,                  \
+        .clock          = I2C1_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_RXI,                     \
+        .flag           = I2C1_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c2",                                     \
+        .Instance = CM_I2C2,                                    \
+        .clock    = FCG1_PERIPH_I2C2,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_TX_DMA_INSTANCE,                 \
+        .channel        = I2C2_TX_DMA_CHANNEL,                  \
+        .clock          = I2C2_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_TEI,                     \
+        .flag           = I2C2_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_RX_DMA_INSTANCE,                 \
+        .channel        = I2C2_RX_DMA_CHANNEL,                  \
+        .clock          = I2C2_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_RXI,                     \
+        .flag           = I2C2_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c3",                                     \
+        .Instance = CM_I2C3,                                    \
+        .clock    = FCG1_PERIPH_I2C3,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_TX_DMA_INSTANCE,                 \
+        .channel        = I2C3_TX_DMA_CHANNEL,                  \
+        .clock          = I2C3_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_TEI,                     \
+        .flag           = I2C3_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_RX_DMA_INSTANCE,                 \
+        .channel        = I2C3_RX_DMA_CHANNEL,                  \
+        .clock          = I2C3_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_RXI,                     \
+        .flag           = I2C3_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -71,33 +70,36 @@ extern "C" {
 #define BSP_DMA2_CH1_IRQ_NUM            INT043_IRQn
 #define BSP_DMA2_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
 /* DMA2 ch2 */
-#define BSP_DMA2_CH2_IRQ_NUM            INT008_IRQn
+#define BSP_DMA2_CH2_IRQ_NUM            INT020_IRQn
 #define BSP_DMA2_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
 /* DMA2 ch3 */
-#define BSP_DMA2_CH3_IRQ_NUM            INT009_IRQn
+#define BSP_DMA2_CH3_IRQ_NUM            INT021_IRQn
 #define BSP_DMA2_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

-
 #if defined(BSP_USING_UART1)
-#define BSP_UART1_RXERR_IRQ_NUM         INT010_IRQn
+#define BSP_UART1_RXERR_IRQ_NUM         INT012_IRQn
 #define BSP_UART1_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
-#define BSP_UART1_RX_IRQ_NUM            INT083_IRQn
+#define BSP_UART1_RX_IRQ_NUM            INT082_IRQn
 #define BSP_UART1_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
-#define BSP_UART1_TX_IRQ_NUM            INT082_IRQn
+#define BSP_UART1_TX_IRQ_NUM            INT081_IRQn
 #define BSP_UART1_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 #if defined(BSP_UART1_RX_USING_DMA)
-#define BSP_UART1_RXTO_IRQ_NUM          INT006_IRQn
+#define BSP_UART1_RXTO_IRQ_NUM          INT013_IRQn
 #define BSP_UART1_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
 #endif
-#if defined(BSP_UART1_TX_USING_DMA)
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
+#define BSP_UART1_TX_CPLT_IRQ_NUM       INT080_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
 #define BSP_UART1_TX_CPLT_IRQ_NUM       INT080_IRQn
 #define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
 #endif
 #endif /* BSP_USING_UART1 */

 #if defined(BSP_USING_UART2)
-#define BSP_UART2_RXERR_IRQ_NUM         INT011_IRQn
+#define BSP_UART2_RXERR_IRQ_NUM         INT014_IRQn
 #define BSP_UART2_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
 #define BSP_UART2_RX_IRQ_NUM            INT085_IRQn
 #define BSP_UART2_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
@ -105,35 +107,43 @@ extern "C" {
 #define BSP_UART2_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 #if defined(BSP_UART2_RX_USING_DMA)
-#define BSP_UART2_RXTO_IRQ_NUM          INT007_IRQn
+#define BSP_UART2_RXTO_IRQ_NUM          INT015_IRQn
 #define BSP_UART2_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
 #endif
-#if defined(BSP_UART2_TX_USING_DMA)
-#define BSP_UART2_TX_CPLT_IRQ_NUM       INT081_IRQn
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       INT083_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       INT083_IRQn
 #define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
 #endif
 #endif /* BSP_USING_UART2 */

 #if defined(BSP_USING_UART3)
-#define BSP_UART3_RXERR_IRQ_NUM         INT012_IRQn
+#define BSP_UART3_RXERR_IRQ_NUM         INT016_IRQn
 #define BSP_UART3_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
-#define BSP_UART3_RX_IRQ_NUM            INT089_IRQn
+#define BSP_UART3_RX_IRQ_NUM            INT088_IRQn
 #define BSP_UART3_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
-#define BSP_UART3_TX_IRQ_NUM            INT088_IRQn
+#define BSP_UART3_TX_IRQ_NUM            INT087_IRQn
 #define BSP_UART3_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 #if defined(BSP_UART3_RX_USING_DMA)
-#define BSP_UART3_RXTO_IRQ_NUM          INT014_IRQn
+#define BSP_UART3_RXTO_IRQ_NUM          INT017_IRQn
 #define BSP_UART3_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
 #endif
-#if defined(BSP_UART3_TX_USING_DMA)
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
+#define BSP_UART3_TX_CPLT_IRQ_NUM       INT086_IRQn
+#define BSP_UART3_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
 #define BSP_UART3_TX_CPLT_IRQ_NUM       INT086_IRQn
 #define BSP_UART3_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
 #endif
 #endif /* BSP_USING_UART3 */

 #if defined(BSP_USING_UART4)
-#define BSP_UART4_RXERR_IRQ_NUM         INT013_IRQn
+#define BSP_UART4_RXERR_IRQ_NUM         INT018_IRQn
 #define BSP_UART4_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
 #define BSP_UART4_RX_IRQ_NUM            INT091_IRQn
 #define BSP_UART4_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
@ -141,19 +151,99 @@ extern "C" {
 #define BSP_UART4_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 #if defined(BSP_UART4_RX_USING_DMA)
-#define BSP_UART4_RXTO_IRQ_NUM          INT015_IRQn
+#define BSP_UART4_RXTO_IRQ_NUM          INT019_IRQn
 #define BSP_UART4_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
 #endif
-#if defined(BSP_UART4_TX_USING_DMA)
-#define BSP_UART4_TX_CPLT_IRQ_NUM       INT087_IRQn
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
+#define BSP_UART4_TX_CPLT_IRQ_NUM       INT089_IRQn
+#define BSP_UART4_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART4_TX_CPLT_IRQ_NUM       INT089_IRQn
 #define BSP_UART4_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
 #endif
 #endif /* BSP_USING_UART4 */

+#if defined(BSP_USING_SPI1)
+#define BSP_SPI1_ERR_IRQ_NUM            INT008_IRQn
+#define BSP_SPI1_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI2)
+#define BSP_SPI2_ERR_IRQ_NUM            INT009_IRQn
+#define BSP_SPI2_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI3)
+#define BSP_SPI3_ERR_IRQ_NUM            INT010_IRQn
+#define BSP_SPI3_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI4)
+#define BSP_SPI4_ERR_IRQ_NUM            INT011_IRQn
+#define BSP_SPI4_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
 #if defined(BSP_USING_CAN1)
-#define BSP_CAN1_IRQ_NUM                INT004_IRQn
+#define BSP_CAN1_IRQ_NUM                INT126_IRQn
 #define BSP_CAN1_IRQ_PRIO               DDL_IRQ_PRIO_DEFAULT
-#endif/* BSP_USING_CAN1 */
+#endif /* BSP_USING_CAN1 */
+
+#if defined(BSP_USING_SDIO1)
+#define BSP_SDIO1_IRQ_NUM               INT122_IRQn
+#define BSP_SDIO1_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_SDIO1 */
+
+#if defined(BSP_USING_SDIO2)
+#define BSP_SDIO2_IRQ_NUM               INT124_IRQn
+#define BSP_SDIO2_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_SDIO2 */
+
+#if defined(RT_USING_ALARM)
+#define BSP_RTC_ALARM_IRQ_NUM           INT044_IRQn
+#define BSP_RTC_ALARM_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#endif/* RT_USING_ALARM */
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+#define BSP_USB_GLB_IRQ_NUM             INT003_IRQn
+#define BSP_USB_GLB_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_USBD */
+
+#if defined (BSP_USING_QSPI)
+#define BSP_QSPI_ERR_IRQ_NUM            INT004_IRQn
+#define BSP_QSPI_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_QSPI */
+
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM   INT080_IRQn
+#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM   INT081_IRQn
+#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
+
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM   INT050_IRQn
+#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM   INT051_IRQn
+#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
+
+#if defined(BSP_USING_TMR0_1A)
+#define BSP_USING_TMR0_1A_IRQ_NUM       INT046_IRQn
+#define BSP_USING_TMR0_1A_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMR0_1A */
+#if defined(BSP_USING_TMR0_1B)
+#define BSP_USING_TMR0_1B_IRQ_NUM       INT047_IRQn
+#define BSP_USING_TMR0_1B_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMR0_1B */
+#if defined(BSP_USING_TMR0_2A)
+#define BSP_USING_TMR0_2A_IRQ_NUM       INT048_IRQn
+#define BSP_USING_TMR0_2A_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMR0_2A */
+#if defined(BSP_USING_TMR0_2B)
+#define BSP_USING_TMR0_2B_IRQ_NUM       INT049_IRQn
+#define BSP_USING_TMR0_2B_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMR0_2B */

 #ifdef __cplusplus
 }
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h
@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK                                          \
+(   (1UL << PM_SLEEP_MODE_IDLE)  |                                             \
+    (1UL << PM_SLEEP_MODE_DEEP))
+#endif
+
+/**
+ * @brief  run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG                                                        \
+    {                                                                          \
+       .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg                                \
+    }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief  sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG                                                      \
+{                                                                              \
+    .pwc_sleep_type = PWC_SLEEP_WFE_INT,                                       \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief  sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG                                                      \
+{                                                                              \
+    {                                                                          \
+        .u16Clock = PWC_STOP_CLK_KEEP,                                         \
+        .u8StopDrv = PWC_STOP_DRV_HIGH,                                        \
+        .u16ExBusHold = PWC_STOP_EXBUS_HIZ,                                    \
+        .u16FlashWait = PWC_STOP_FLASH_WAIT_ON,                                \
+    },                                                                         \
+    .pwc_stop_type = PWC_STOP_WFE_INT,                                         \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief  sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG                                                   \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD1,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief  sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG                                                  \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD3,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h
@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2023-06-09     CDT               first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_PULSE_ENCODER)
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
+#ifndef PULSE_ENCODER_TMRA_1_CONFIG
+#define PULSE_ENCODER_TMRA_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue      = 1000UL,                                           \
+       .name                = "pulse_a1"                                        \
+    }
+#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
+#ifndef PULSE_ENCODER_TMRA_2_CONFIG
+#define PULSE_ENCODER_TMRA_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a2"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
+#ifndef PULSE_ENCODER_TMRA_3_CONFIG
+#define PULSE_ENCODER_TMRA_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a3"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
+#ifndef PULSE_ENCODER_TMRA_4_CONFIG
+#define PULSE_ENCODER_TMRA_4_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_4,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_4,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_4_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_4_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a4"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
+#ifndef PULSE_ENCODER_TMRA_5_CONFIG
+#define PULSE_ENCODER_TMRA_5_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_5,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_5,                                   \
+       .hw_count =                                                              \
+        {                                                                       \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_5_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_5_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a5"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
+#ifndef PULSE_ENCODER_TMRA_6_CONFIG
+#define PULSE_ENCODER_TMRA_6_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_6,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_6,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_6_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_6_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a6"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
+#ifndef PULSE_ENCODER_TMR6_1_CONFIG
+#define PULSE_ENCODER_TMR6_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_61"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
+#ifndef PULSE_ENCODER_TMR6_2_CONFIG
+#define PULSE_ENCODER_TMR6_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_62"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
+#ifndef PULSE_ENCODER_TMR6_3_CONFIG
+#define PULSE_ENCODER_TMR6_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_63"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */
+
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h
@ -0,0 +1,433 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2023-02-22     CDT               first version
+ */
+
+#ifndef __PWM_TMR_CONFIG_H__
+#define __PWM_TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM_TMRA
+
+#ifdef BSP_USING_PWM_TMRA_1
+#ifndef PWM_TMRA_1_CONFIG
+#define PWM_TMRA_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a1",             \
+        .instance                       = CM_TMRA_1,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_1_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_1 */
+
+#ifdef BSP_USING_PWM_TMRA_2
+#ifndef PWM_TMRA_2_CONFIG
+#define PWM_TMRA_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a2",             \
+        .instance                       = CM_TMRA_2,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_2_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_2 */
+
+#ifdef BSP_USING_PWM_TMRA_3
+#ifndef PWM_TMRA_3_CONFIG
+#define PWM_TMRA_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a3",             \
+        .instance                       = CM_TMRA_3,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_3_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_3 */
+
+#ifdef BSP_USING_PWM_TMRA_4
+#ifndef PWM_TMRA_4_CONFIG
+#define PWM_TMRA_4_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a4",             \
+        .instance                       = CM_TMRA_4,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_4_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_4 */
+
+#ifdef BSP_USING_PWM_TMRA_5
+#ifndef PWM_TMRA_5_CONFIG
+#define PWM_TMRA_5_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a5",             \
+        .instance                       = CM_TMRA_5,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_5_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_5 */
+
+#ifdef BSP_USING_PWM_TMRA_6
+#ifndef PWM_TMRA_6_CONFIG
+#define PWM_TMRA_6_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a6",             \
+        .instance                       = CM_TMRA_6,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_6_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_6 */
+
+#endif /* BSP_USING_PWM_TMRA */
+
+#ifdef BSP_USING_PWM_TMR4
+
+#ifdef BSP_USING_PWM_TMR4_1
+#ifndef PWM_TMR4_1_CONFIG
+#define PWM_TMR4_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t41",            \
+        .instance                       = CM_TMR4_1,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_1 */
+
+#ifdef BSP_USING_PWM_TMR4_2
+#ifndef PWM_TMR4_2_CONFIG
+#define PWM_TMR4_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t42",            \
+        .instance                       = CM_TMR4_2,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_2 */
+
+#ifdef BSP_USING_PWM_TMR4_3
+#ifndef PWM_TMR4_3_CONFIG
+#define PWM_TMR4_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t43",            \
+        .instance                       = CM_TMR4_3,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_3 */
+
+#endif /* BSP_USING_PWM_TMR4 */
+
+#ifdef BSP_USING_PWM_TMR6
+
+#ifdef BSP_USING_PWM_TMR6_1
+#ifndef PWM_TMR6_1_CONFIG
+#define PWM_TMR6_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_1,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_UP,          \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_HIGH,    \
+                .u32StopPolarity            = TMR6_PWM_HIGH,    \
+                .u32CompareMatchPolarity    = TMR6_PWM_LOW,     \
+                .u32PeriodMatchPolarity     = TMR6_PWM_HIGH,    \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_HIGH,    \
+                .u32StopPolarity            = TMR6_PWM_HIGH,    \
+                .u32CompareMatchPolarity    = TMR6_PWM_LOW,     \
+                .u32PeriodMatchPolarity     = TMR6_PWM_HIGH,    \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_1 */
+#ifdef BSP_USING_PWM_TMR6_2
+#ifndef PWM_TMR6_2_CONFIG
+#define PWM_TMR6_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_2,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CompareMatchPolarity    = TMR6_PWM_HIGH,    \
+                .u32PeriodMatchPolarity     = TMR6_PWM_LOW,     \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CompareMatchPolarity    = TMR6_PWM_HIGH,    \
+                .u32PeriodMatchPolarity     = TMR6_PWM_LOW,     \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_2 */
+#ifdef BSP_USING_PWM_TMR6_3
+#ifndef PWM_TMR6_3_CONFIG
+#define PWM_TMR6_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_3,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CompareMatchPolarity    = TMR6_PWM_HIGH,    \
+                .u32PeriodMatchPolarity     = TMR6_PWM_LOW,     \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CompareMatchPolarity    = TMR6_PWM_HIGH,    \
+                .u32PeriodMatchPolarity     = TMR6_PWM_LOW,     \
+                .u32StartStopHold   = TMR6_PWM_START_STOP_HOLD, \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_3 */
+
+#endif /* BSP_USING_PWM_TMR6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_TMRA_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h
@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-06-15     CDT          first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_QSPI,                                \
+        .clock    = FCG1_PERIPH_QSPI,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_QSPI_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_QSPI_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_QSPI_INTR,                \
+        },                                                  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS                                        \
+    {                                                           \
+        .u32PrefetchMode   = QSPI_PREFETCH_MD_INVD,             \
+        .u32SetupTime      = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5,   \
+        .u32ReleaseTime    = QSPI_QSSN_RELEASE_DELAY_QSCK32,    \
+        .u32IntervalTime   = QSPI_QSSN_INTERVAL_QSCK1,          \
+    }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL               QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                     \
+    {                                                       \
+        .Instance       = QSPI_DMA_INSTANCE,                \
+        .channel        = QSPI_DMA_CHANNEL,                 \
+        .clock          = QSPI_DMA_CLOCK,                   \
+        .trigger_select = QSPI_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_AOS_STRG,                 \
+        .flag           = QSPI_DMA_TRANS_FLAG,              \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = QSPI_DMA_IRQn,                    \
+            .irq_prio   = QSPI_DMA_INT_PRIO,                \
+            .int_src    = QSPI_DMA_INT_SRC,                 \
+        }                                                   \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h
@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_SDIO1)
+#ifndef SDIO1_BUS_CONFIG
+#define SDIO1_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio1",                                  \
+        .instance   = CM_SDIOC1,                                \
+        .clock      = FCG1_PERIPH_SDIOC1,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO1_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO1_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC1_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_RX_DMA_INSTANCE,            \
+            .channel        = SDIO1_RX_DMA_CHANNEL,             \
+            .clock          = SDIO1_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_TX_DMA_INSTANCE,            \
+            .channel        = SDIO1_TX_DMA_CHANNEL,             \
+            .clock          = SDIO1_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO1_BUS_CONFIG */
+#endif /* BSP_USING_SDIO1 */
+
+#if defined(BSP_USING_SDIO2)
+#ifndef SDIO2_BUS_CONFIG
+#define SDIO2_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio2",                                  \
+        .instance   = CM_SDIOC2,                                \
+        .clock      = FCG1_PERIPH_SDIOC2,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO2_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO2_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC2_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_RX_DMA_INSTANCE,            \
+            .channel        = SDIO2_RX_DMA_CHANNEL,             \
+            .clock          = SDIO2_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_TX_DMA_INSTANCE,            \
+            .channel        = SDIO2_TX_DMA_CHANNEL,             \
+            .clock          = SDIO2_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO2_BUS_CONFIG */
+#endif /* BSP_USING_SDIO2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h
@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI1,                                \
+        .bus_name = "spi1",                                 \
+        .clock    = FCG1_PERIPH_SPI1,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI1_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI1_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI1_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_TX_DMA_INSTANCE,             \
+        .channel        = SPI1_TX_DMA_CHANNEL,              \
+        .clock          = SPI1_TX_DMA_CLOCK,                \
+        .trigger_select = SPI1_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPTI,                \
+        .flag           = SPI1_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_RX_DMA_INSTANCE,             \
+        .channel        = SPI1_RX_DMA_CHANNEL,              \
+        .clock          = SPI1_RX_DMA_CLOCK,                \
+        .trigger_select = SPI1_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPRI,                \
+        .flag           = SPI1_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI2,                                \
+        .bus_name = "spi2",                                 \
+        .clock    = FCG1_PERIPH_SPI2,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI2_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI2_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI2_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_TX_DMA_INSTANCE,             \
+        .channel        = SPI2_TX_DMA_CHANNEL,              \
+        .clock          = SPI2_TX_DMA_CLOCK,                \
+        .trigger_select = SPI2_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPTI,                \
+        .flag           = SPI2_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_RX_DMA_INSTANCE,             \
+        .channel        = SPI2_RX_DMA_CHANNEL,              \
+        .clock          = SPI2_RX_DMA_CLOCK,                \
+        .trigger_select = SPI2_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPRI,                \
+        .flag           = SPI2_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI3,                                \
+        .bus_name = "spi3",                                 \
+        .clock    = FCG1_PERIPH_SPI3,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI3_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI3_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI3_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_TX_DMA_INSTANCE,             \
+        .channel        = SPI3_TX_DMA_CHANNEL,              \
+        .clock          = SPI3_TX_DMA_CLOCK,                \
+        .trigger_select = SPI3_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPTI,                \
+        .flag           = SPI3_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_RX_DMA_INSTANCE,             \
+        .channel        = SPI3_RX_DMA_CHANNEL,              \
+        .clock          = SPI3_RX_DMA_CLOCK,                \
+        .trigger_select = SPI3_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPRI,                \
+        .flag           = SPI3_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI4,                                \
+        .bus_name = "spi4",                                 \
+        .clock    = FCG1_PERIPH_SPI4,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI4_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI4_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI4_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_TX_DMA_INSTANCE,             \
+        .channel        = SPI4_TX_DMA_CHANNEL,              \
+        .clock          = SPI4_TX_DMA_CLOCK,                \
+        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
+        .flag           = SPI4_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_RX_DMA_INSTANCE,             \
+        .channel        = SPI4_RX_DMA_CHANNEL,              \
+        .clock          = SPI4_RX_DMA_CLOCK,                \
+        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
+        .flag           = SPI4_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h
@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2023-06-21     CDT               first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_TMRA_1
+#ifndef TMRA_1_CONFIG
+#define TMRA_1_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_1,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_1,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_1_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_1_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_1"                          \
+    }
+#endif /* TMRA_1_CONFIG */
+#endif /* BSP_USING_TMRA_1 */
+
+#ifdef BSP_USING_TMRA_2
+#ifndef TMRA_2_CONFIG
+#define TMRA_2_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_2,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_2,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_2_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_2_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_2"                          \
+    }
+#endif /* TMRA_2_CONFIG */
+#endif /* BSP_USING_TMRA_2 */
+
+#ifdef BSP_USING_TMRA_3
+#ifndef TMRA_3_CONFIG
+#define TMRA_3_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_3,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_3,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_3_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_3_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_3"                          \
+    }
+#endif /* TMRA_3_CONFIG */
+#endif /* BSP_USING_TMRA_3 */
+
+#ifdef BSP_USING_TMRA_4
+#ifndef TMRA_4_CONFIG
+#define TMRA_4_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_4,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_4,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_4_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_4_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_4"                          \
+    }
+#endif /* TMRA_4_CONFIG */
+#endif /* BSP_USING_TMRA_4 */
+
+#ifdef BSP_USING_TMRA_5
+#ifndef TMRA_5_CONFIG
+#define TMRA_5_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_5,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_5,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_5_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_5_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_5"                          \
+    }
+#endif /* TMRA_5_CONFIG */
+#endif /* BSP_USING_TMRA_5 */
+
+#ifdef BSP_USING_TMRA_6
+#ifndef TMRA_6_CONFIG
+#define TMRA_6_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_6,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_6,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_6_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_6_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_6"                          \
+    }
+#endif /* TMRA_6_CONFIG */
+#endif /* BSP_USING_TMRA_6 */
+
+#endif /* __TMR_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -57,6 +56,7 @@ extern "C" {
        .clock          = UART1_RX_DMA_CLOCK,                   \
        .trigger_select = UART1_RX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART1_RI,                    \
+        .flag           = UART1_RX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART1_RX_DMA_IRQn,                    \
@ -83,7 +83,7 @@ extern "C" {
 #endif /* UART1_RXTO_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */

-#if defined(BSP_UART1_TX_USING_DMA)
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
 #ifndef UART1_TX_CPLT_CONFIG
 #define UART1_TX_CPLT_CONFIG                                    \
    {                                                           \
@ -94,8 +94,22 @@ extern "C" {
            .int_src    = INT_SRC_USART1_TCI,                   \
        },                                                      \
    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART1_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART1_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART1_TCI,                   \
+        },                                                      \
+    }
+#endif
 #endif /* UART1_TX_CPLT_CONFIG */

+#if defined(BSP_UART1_TX_USING_DMA)
 #ifndef UART1_DMA_TX_CONFIG
 #define UART1_DMA_TX_CONFIG                                     \
    {                                                           \
@ -104,6 +118,7 @@ extern "C" {
        .clock          = UART1_TX_DMA_CLOCK,                   \
        .trigger_select = UART1_TX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART1_TI,                    \
+        .flag           = UART1_TX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART1_TX_DMA_IRQn,                    \
@ -152,6 +167,7 @@ extern "C" {
        .clock          = UART2_RX_DMA_CLOCK,                   \
        .trigger_select = UART2_RX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART2_RI,                    \
+        .flag           = UART2_RX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART2_RX_DMA_IRQn,                    \
@ -178,7 +194,7 @@ extern "C" {
 #endif /* UART2_RXTO_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */

-#if defined(BSP_UART2_TX_USING_DMA)
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_TX_CPLT_CONFIG
 #define UART2_TX_CPLT_CONFIG                                    \
    {                                                           \
@ -189,8 +205,22 @@ extern "C" {
            .int_src    = INT_SRC_USART2_TCI,                   \
        },                                                      \
    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART2_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART2_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART2_TCI,                   \
+        },                                                      \
+    }
+#endif
 #endif /* UART2_TX_CPLT_CONFIG */

+#if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                     \
    {                                                           \
@ -199,6 +229,7 @@ extern "C" {
        .clock          = UART2_TX_DMA_CLOCK,                   \
        .trigger_select = UART2_TX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART2_TI,                    \
+        .flag           = UART2_TX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num     = UART2_TX_DMA_IRQn,                   \
@ -247,6 +278,7 @@ extern "C" {
        .clock          = UART3_RX_DMA_CLOCK,                   \
        .trigger_select = UART3_RX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART3_RI,                    \
+        .flag           = UART3_RX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART3_RX_DMA_IRQn,                    \
@ -273,7 +305,7 @@ extern "C" {
 #endif /* UART3_RXTO_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */

-#if defined(BSP_UART3_TX_USING_DMA)
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_TX_CPLT_CONFIG
 #define UART3_TX_CPLT_CONFIG                                    \
    {                                                           \
@ -284,8 +316,22 @@ extern "C" {
            .int_src    = INT_SRC_USART3_TCI,                   \
        },                                                      \
    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART3_TX_CPLT_CONFIG
+#define UART3_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART3_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART3_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART3_TCI,                   \
+        },                                                      \
+    }
+#endif
 #endif /* UART3_TX_CPLT_CONFIG */

+#if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                     \
    {                                                           \
@ -294,6 +340,7 @@ extern "C" {
        .clock          = UART3_TX_DMA_CLOCK,                   \
        .trigger_select = UART3_TX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART3_TI,                    \
+        .flag           = UART3_TX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART3_TX_DMA_IRQn,                    \
@ -342,6 +389,7 @@ extern "C" {
        .clock          = UART4_RX_DMA_CLOCK,                   \
        .trigger_select = UART4_RX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART4_RI,                    \
+        .flag           = UART4_RX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART4_RX_DMA_IRQn,                    \
@ -368,7 +416,7 @@ extern "C" {
 #endif /* UART4_RXTO_CONFIG */
 #endif /* BSP_UART4_RX_USING_DMA */

-#if defined(BSP_UART4_TX_USING_DMA)
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
 #ifndef UART4_TX_CPLT_CONFIG
 #define UART4_TX_CPLT_CONFIG                                    \
    {                                                           \
@ -379,8 +427,22 @@ extern "C" {
            .int_src    = INT_SRC_USART4_TCI,                   \
        },                                                      \
    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART4_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART4_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART4_TCI,                   \
+        },                                                      \
+    }
+#endif
 #endif /* UART4_TX_CPLT_CONFIG */

+#if defined(BSP_UART4_TX_USING_DMA)
 #ifndef UART4_DMA_TX_CONFIG
 #define UART4_DMA_TX_CONFIG                                     \
    {                                                           \
@ -389,6 +451,7 @@ extern "C" {
        .clock          = UART4_TX_DMA_CLOCK,                   \
        .trigger_select = UART4_TX_DMA_TRIG_SELECT,             \
        .trigger_event  = EVT_SRC_USART4_TI,                    \
+        .flag           = UART1_TX_DMA_TRANS_FLAG,              \
        .irq_config     =                                       \
        {                                                       \
            .irq_num    = UART4_TX_DMA_IRQn,                    \
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h
@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_APP_CONF_H__
+#define __USB_APP_CONF_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "rtconfig.h"
+
+/* USB MODE CONFIGURATION */
+
+
+#if defined(BSP_USING_USBFS)
+#define USB_FS_MODE
+#else
+#define USB_FS_MODE
+#endif
+
+#if defined(BSP_USING_USBD)
+#define USE_DEVICE_MODE
+#elif defined(BSP_USING_USBH)
+#define USE_HOST_MODE
+#else
+#define USE_DEVICE_MODE
+#endif
+
+#ifndef USB_FS_MODE
+#error  "USB_FS_MODE should be defined"
+#endif
+
+#ifndef USE_DEVICE_MODE
+#ifndef USE_HOST_MODE
+#error  "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD)
+/* USB DEVICE FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                         (128U)
+#define TX0_FIFO_FS_SIZE                        (32U)
+#define TX1_FIFO_FS_SIZE                        (32U)
+#define TX2_FIFO_FS_SIZE                        (32U)
+#define TX3_FIFO_FS_SIZE                        (32U)
+#define TX4_FIFO_FS_SIZE                        (32U)
+#define TX5_FIFO_FS_SIZE                        (32U)
+
+#if ((RX_FIFO_FS_SIZE + \
+      TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
+      TX5_FIFO_FS_SIZE) > 320U)
+#error  "The USB max FIFO size is 320 x 4 Bytes!"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD_VBUS_SENSING)
+#define VBUS_SENSING_ENABLED
+#endif
+#endif
+
+#if defined(BSP_USING_USBH)
+/* USB HOST FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                          (128U)
+#define TXH_NP_FS_FIFOSIZ                        (64U)
+#define TXH_P_FS_FIFOSIZ                         (128U)
+
+#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 320U)
+#error  "The USB max FIFO size is 320 x 4 Bytes!"
+#endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_APP_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h
@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_BSP_H__
+#define __USB_BSP_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "hc32_ll_utility.h"
+
+extern void usb_udelay(const uint32_t usec);
+extern void usb_mdelay(const uint32_t msec);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_BSP_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -19,20 +18,18 @@
 extern "C" {
 #endif

-/* Suppress warning messages */
-#if defined(__CC_ARM)
-// Suppress warning message: extended constant initialiser used
-#pragma diag_suppress 1296
-#elif defined(__ICCARM__)
-#elif defined(__GNUC__)
-#endif
-
 #include "dma_config.h"
 #include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
 #include "gpio_config.h"
 #include "can_config.h"
-#include "adc_config.h"
-#include "pwm_tmra_config.h"
+#include "sdio_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"

 #ifdef __cplusplus
 }
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h
@ -5,10 +5,10 @@
 @verbatim
   Change Logs:
   Date             Author          Notes
-   2022-04-28       CDT             First version
+   2022-03-31       CDT             First version
 @endverbatim
 *******************************************************************************
- * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
 *
 * This software component is licensed by XHSC under BSD 3-Clause license
 * (the "License"); You may not use this file except in compliance with the
@ -23,6 +23,7 @@
 /*******************************************************************************
 * Include files
 ******************************************************************************/
+#include <rtconfig.h>

 /* C binding of definitions if building with C++ compiler */
 #ifdef __cplusplus
@ -58,64 +59,44 @@ extern "C"
 #define LL_CLK_ENABLE                               (DDL_ON)
 #define LL_CMP_ENABLE                               (DDL_ON)
 #define LL_CRC_ENABLE                               (DDL_ON)
-#define LL_CTC_ENABLE                               (DDL_ON)
-#define LL_DAC_ENABLE                               (DDL_ON)
+#define LL_DBGC_ENABLE                              (DDL_OFF)
 #define LL_DCU_ENABLE                               (DDL_ON)
 #define LL_DMA_ENABLE                               (DDL_ON)
-#define LL_DMC_ENABLE                               (DDL_ON)
-#define LL_DVP_ENABLE                               (DDL_ON)
 #define LL_EFM_ENABLE                               (DDL_ON)
 #define LL_EMB_ENABLE                               (DDL_ON)
-#define LL_ETH_ENABLE                               (DDL_ON)
 #define LL_EVENT_PORT_ENABLE                        (DDL_OFF)
 #define LL_FCG_ENABLE                               (DDL_ON)
 #define LL_FCM_ENABLE                               (DDL_ON)
-#define LL_FMAC_ENABLE                              (DDL_ON)
 #define LL_GPIO_ENABLE                              (DDL_ON)
 #define LL_HASH_ENABLE                              (DDL_ON)
-#define LL_HRPWM_ENABLE                             (DDL_ON)
 #define LL_I2C_ENABLE                               (DDL_ON)
 #define LL_I2S_ENABLE                               (DDL_ON)
 #define LL_INTERRUPTS_ENABLE                        (DDL_ON)
 #define LL_INTERRUPTS_SHARE_ENABLE                  (DDL_ON)
 #define LL_KEYSCAN_ENABLE                           (DDL_ON)
-#define LL_MAU_ENABLE                               (DDL_ON)
-#define LL_MDIO_ENABLE                              (DDL_OFF)
 #define LL_MPU_ENABLE                               (DDL_ON)
-#define LL_NFC_ENABLE                               (DDL_ON)
 #define LL_OTS_ENABLE                               (DDL_ON)
-#define LL_PLA_ENABLE                               (DDL_OFF)
 #define LL_PWC_ENABLE                               (DDL_ON)
 #define LL_QSPI_ENABLE                              (DDL_ON)
 #define LL_RMU_ENABLE                               (DDL_ON)
 #define LL_RTC_ENABLE                               (DDL_ON)
 #define LL_SDIOC_ENABLE                             (DDL_ON)
-#define LL_SMC_ENABLE                               (DDL_ON)
 #define LL_SPI_ENABLE                               (DDL_ON)
 #define LL_SRAM_ENABLE                              (DDL_ON)
 #define LL_SWDT_ENABLE                              (DDL_ON)
 #define LL_TMR0_ENABLE                              (DDL_ON)
-#define LL_TMR2_ENABLE                              (DDL_ON)
 #define LL_TMR4_ENABLE                              (DDL_ON)
 #define LL_TMR6_ENABLE                              (DDL_ON)
 #define LL_TMRA_ENABLE                              (DDL_ON)
 #define LL_TRNG_ENABLE                              (DDL_ON)
 #define LL_USART_ENABLE                             (DDL_ON)
-#define LL_USB_ENABLE                               (DDL_OFF)
-#define LL_VREF_ENABLE                              (DDL_OFF)
+#define LL_USB_ENABLE                               (DDL_ON)
 #define LL_WDT_ENABLE                               (DDL_ON)

 /**
 * @brief The following is a list of currently supported BSP boards.
 */
-#define BSP_EV_HC32F4A0_LQFP176                     (1U)
-#define BSP_EV_HC32F4A0_LQFP176_MEM                 (2U)
-#define BSP_EV_HC32F460_LQFP100_V1                  (3U)
 #define BSP_EV_HC32F460_LQFP100_V2                  (4U)
-#define BSP_EV_HC32F451_LQFP100                     (5U)
-#define BSP_EV_HC32F452_LQFP100                     (6U)
-#define BSP_EV_HC32F472_LQFP100                     (7U)
-#define BSP_SK_HC32F4A0_LQFP100                     (8U)

 /**
 * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
@ -131,23 +112,9 @@ extern "C"
 * Select the components you need to use to DDL_ON.
 */
 #define BSP_24CXX_ENABLE                            (DDL_OFF)
-#define BSP_CY62167EV30LL_ENABLE                    (DDL_OFF)
-#define BSP_IS42S16400J7TLI_ENABLE                  (DDL_OFF)
-#define BSP_IS62WV51216_ENABLE                      (DDL_OFF)
-#define BSP_MT29F2G08AB_ENABLE                      (DDL_OFF)
-#define BSP_NT35510_ENABLE                          (DDL_OFF)
-#define BSP_OV5640_ENABLE                           (DDL_OFF)
-#define BSP_S29GL064N90TFI03_ENABLE                 (DDL_OFF)
-#define BSP_TCA9539_ENABLE                          (DDL_OFF)
 #define BSP_W25QXX_ENABLE                           (DDL_OFF)
 #define BSP_WM8731_ENABLE                           (DDL_OFF)

-/**
- * @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0).
- * @note  Set value to non-zero if re-define main function.
- */
-#define RE_DEFINE_MAIN                              (0)
-
 /*******************************************************************************
 * Global variable definitions ('extern')
 ******************************************************************************/
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf
@ -1,21 +1,68 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
+/***************************************************************************//**
+ * \file HC32F460.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+/*###ICF### Section handled by ICF editor, don't touch! *****/
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+  error "Link location not defined or not supported!";
+}
+if((!isdefinedsymbol(_HC32F460_512K_)) && (!isdefinedsymbol(_HC32F460_256K_))) {
+  error "Mcu type or size not defined or not supported!";
+}
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFF8000;
+define symbol ram1_end_address  = 0x20026FFF;
+
+if(isdefinedsymbol(_LINK_RAM_)) {
+  define symbol ram_start_reserve = 0x8000;
+  define symbol rom1_base_address = ram1_base_address;
+  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
+  define symbol rom2_base_address = 0x0;
+  define symbol rom2_end_address  = 0x0;
+} else {
+  define symbol ram_start_reserve = 0x0;
+  define symbol rom1_base_address = 0x0;
+  define symbol rom2_base_address = 0x03000C00;
+  define symbol rom2_end_address = 0x03000FBF;
+  if (isdefinedsymbol(_HC32F460_512K_)) {
+    define symbol rom1_end_address  = 0x0007FFFF;
+  } else if (isdefinedsymbol(_HC32F460_256K_)) {
+    define symbol rom1_end_address  = 0x0003FFFF;
+  }
+}
+
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x0007FFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x03000FFB;
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
 define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
 define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
 define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
 define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
 define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
 define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x20026FFF;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
 define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
 define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
 define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
@ -25,16 +72,18 @@ define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
 define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
 define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;

-
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0xC00;
 define symbol __ICFEDIT_size_proc_stack__ = 0x0;
 define symbol __ICFEDIT_size_heap__   = 0x400;
 /**** End of ICF editor section. ###ICF###*/

+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
 define memory mem with size = 4G;
-define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
-                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__];
+define region OTP_region       =   mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
 define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];

@ -47,5 +96,6 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };

 place in ROM_region   { readonly };
+place in OTP_region   { readonly section .otp_data };
 place in RAM_region   { readwrite,
                        block CSTACK, block HEAP };
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld
@ -1,5 +1,5 @@
 /******************************************************************************
- * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
 *
 * This software component is licensed by XHSC under BSD 3-Clause license
 * (the "License"); You may not use this file except in compliance with the
@ -11,8 +11,8 @@
 /*  File        HC32F460xE.ld                                                */
 /*  Abstract    Linker script for HC32F460 Device with                       */
 /*              512KByte FLASH, 192KByte RAM                                 */
-/*  Version     V1.0                                                          */
-/*  Date        2022-04-28                                                   */
+/*  Version     V1.0                                                         */
+/*  Date        2022-03-31                                                   */
 /*****************************************************************************/

 /* Custom defines, according to section 7.7 of the user manual.
@ -163,42 +163,6 @@ SECTIONS
        __data_end__ = .;
    } >RAM

-    __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
-    .ret_ram_data : AT (__etext_ret_ram)
-    {
-        . = ALIGN(4);
-        __data_start_ret_ram__ = .;
-        *(.ret_ram_data)
-        *(.ret_ram_data*)
-        . = ALIGN(4);
-        __data_end_ret_ram__ = .;
-    } >RET_RAM
-
-    __bss_start = .;
-    .bss :
-    {
-        . = ALIGN(4);
-        _sbss = .;
-        __bss_start__ = _sbss;
-        *(.bss)
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = .;
-        __bss_end__ = _ebss;
-    } >RAM
-    __bss_end = .;
-
-    .ret_ram_bss :
-    {
-        . = ALIGN(4);
-        __bss_start_ret_ram__ = .;
-        *(.ret_ram_bss)
-        *(.ret_ram_bss*)
-        . = ALIGN(4);
-        __bss_end_ret_ram__ = .;
-    } >RET_RAM
-
    .heap_stack (COPY) :
    {
        . = ALIGN(8);
@ -215,6 +179,45 @@ SECTIONS
        __StackTop = .;
    } >RAM

+    __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
+    .ramb_data : AT (__etext_ret_ram)
+    {
+        . = ALIGN(4);
+        __data_start_ret_ram__ = .;
+        *(.ramb_data)
+        *(.ramb_data*)
+        . = ALIGN(4);
+        __data_end_ret_ram__ = .;
+    } >RET_RAM
+
+    __bss_start = .;
+    .bss __StackTop (NOLOAD):
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+        . = ALIGN(4);
+        *(.noinit*)
+        . = ALIGN(4);
+    } >RAM
+    __bss_end = .;
+
+    .ramb_bss :
+    {
+        . = ALIGN(4);
+        __bss_start_ret_ram__ = .;
+        *(.ramb_bss)
+        *(.ramb_bss*)
+        . = ALIGN(4);
+        __bss_end_ret_ram__ = .;
+    } >RET_RAM
+
    /DISCARD/ :
    {
        libc.a (*)
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.sct
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.sct
@ -8,7 +8,14 @@ LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
        .ANY (+RO)
        .ANY (+XO)
    }
-    RW_IRAM1 0x1FFF8000 0x0002F000  {  ; RW data
+    RW_IRAM1 0x1FFF8000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFF8008 0x0002EFF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
        .ANY (+RW +ZI)
    }
 }
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/SConscript
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/SConscript
@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/drv_spi_flash.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/drv_spi_flash.c
@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <board.h>
+#include <drv_spi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+#include <dfs_fs.h>
+#include <fal.h>
+
+#ifdef BSP_USING_SPI_FLASH
+
+#include "spi_flash.h"
+#ifdef RT_USING_SFUD
+    #include "spi_flash_sfud.h"
+#endif
+
+#define SPI_BUS_NAME                    "spi3"
+#define SPI_FLASH_DEVICE_NAME           "spi30"
+#define SPI_FLASH_CHIP                  "w25q64"
+#define SPI_FLASH_SS_PORT               GPIO_PORT_C
+#define SPI_FLASH_SS_PIN                GPIO_PIN_07
+/* Partition Name */
+#define FS_PARTITION_NAME              "filesystem"
+
+#ifdef RT_USING_SFUD
+static void rt_hw_spi_flash_reset(char *spi_dev_name)
+{
+    struct rt_spi_device *spi_dev_w25;
+    rt_uint8_t w25_en_reset = 0x66;
+    rt_uint8_t w25_reset_dev = 0x99;
+
+    spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
+    if (!spi_dev_w25)
+    {
+        rt_kprintf("Can't find %s device!\n", spi_dev_name);
+    }
+    else
+    {
+        rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
+        rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
+        DDL_DelayMS(1U);
+        rt_kprintf("Reset ext flash!\n");
+    }
+}
+
+static int rt_hw_spi_flash_with_sfud_init(void)
+{
+    rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
+
+    if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+    {
+        rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
+        if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+static int rt_hw_fs_init(void)
+{
+    struct rt_device *mtd_dev = RT_NULL;
+
+    /* 初始化 fal */
+    fal_init();
+    /* 生成 mtd 设备 */
+    mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
+    if (!mtd_dev)
+    {
+        LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
+        return -RT_ERROR;
+    }
+    else
+    {
+        /* 挂载 littlefs */
+        if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+        {
+            LOG_I("Filesystem initialized!");
+            return RT_EOK;
+        }
+        else
+        {
+            /* 格式化文件系统 */
+            if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
+            {
+                /* 挂载 littlefs */
+                if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+                {
+                    LOG_I("Filesystem initialized!");
+                    return RT_EOK;
+                }
+                else
+                {
+                    LOG_E("Failed to initialize filesystem!");
+                    return -RT_ERROR;
+                }
+            }
+            else
+            {
+                LOG_E("Failed to Format fs!");
+                return -RT_ERROR;
+            }
+        }
+    }
+}
+INIT_APP_EXPORT(rt_hw_fs_init);
+
+#endif /* RT_USING_SFUD */
+
+#endif /* BSP_USING_SPI_FLASH */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/SConscript
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/SConscript
@ -0,0 +1,20 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+src     += Glob('*.c')
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/fal_cfg.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/fal_cfg.h
@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &hc32_onchip_flash,                                              \
+    &ext_nor_flash0,                                                 \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                 \
+{                                                                                      \
+    {FAL_PART_MAGIC_WROD,          "app",   "onchip_flash",   0,  512 * 1024, 0},      \
+    {FAL_PART_MAGIC_WROD,   "filesystem",         "w25q64",   0,  8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/fal_flash_sfud_port.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal/fal_flash_sfud_port.c
@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <fal.h>
+
+#include <sfud.h>
+#ifdef RT_USING_SFUD
+    #include <spi_flash_sfud.h>
+#endif
+
+#ifndef FAL_USING_NOR_FLASH_DEV_NAME
+    #define FAL_USING_NOR_FLASH_DEV_NAME            "w25q64"
+#endif
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static sfud_flash_t sfud_dev = NULL;
+struct fal_flash_dev ext_nor_flash0 =
+{
+    .name       = FAL_USING_NOR_FLASH_DEV_NAME,
+    .addr       = 0,
+    .len        = 8 * 1024 * 1024,
+    .blk_size   = 4096,
+    .ops        = {init, read, write, erase},
+    .write_gran = 1
+};
+
+static int init(void)
+{
+    /* RT-Thread RTOS platform */
+    sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
+    if (NULL == sfud_dev)
+    {
+        return -1;
+    }
+    /* update the flash chip information */
+    ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
+    ext_nor_flash0.len      = sfud_dev->chip.capacity;
+
+    return 0;
+}
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
+
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/figures/board.jpg
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/figures/board.jpg
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/jlink/ev_hc32f460_lqfp100_v2
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/jlink/ev_hc32f460_lqfp100_v2
@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;peripherals/&gt;&#13;&#10;"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
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+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
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+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
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+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
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+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
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+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F460"/>
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+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/project"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd
@ -11,7 +11,7 @@
            <name>C-SPY</name>
            <archiveVersion>2</archiveVersion>
            <data>
-                <version>31</version>
+                <version>32</version>
                <wantNonLocal>1</wantNonLocal>
                <debug>0</debug>
                <option>
@ -44,7 +44,7 @@
                </option>
                <option>
                    <name>MemFile</name>
-                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd</state>
+                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd</state>
                </option>
                <option>
                    <name>RunToEnable</name>
@ -80,7 +80,7 @@
                </option>
                <option>
                    <name>OCProductVersion</name>
-                    <state>8.40.1.21529</state>
+                    <state>7.70.1.11471</state>
                </option>
                <option>
                    <name>OCDynDriverList</name>
@ -88,7 +88,7 @@
                </option>
                <option>
                    <name>OCLastSavedByProductVersion</name>
-                    <state>8.40.1.21529</state>
+                    <state>8.50.9.33458</state>
                </option>
                <option>
                    <name>UseFlashLoader</name>
@ -112,7 +112,7 @@
                </option>
                <option>
                    <name>FlashLoadersV3</name>
-                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/config/flashloader/HC32F460xE.board</state>
+                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/config/flashloader/FlashHC32F460xE.board</state>
                </option>
                <option>
                    <name>OCImagesSuppressCheck1</name>
@ -218,6 +218,10 @@
                    <name>OCMulticoreSessionFile</name>
                    <state></state>
                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
            </data>
        </settings>
        <settings>
@ -1003,7 +1007,7 @@
            <name>STLINK_ID</name>
            <archiveVersion>2</archiveVersion>
            <data>
-                <version>6</version>
+                <version>7</version>
                <wantNonLocal>1</wantNonLocal>
                <debug>0</debug>
                <option>
@ -1118,8 +1122,8 @@
                </option>
                <option>
                    <name>CCSTLinkProbeList</name>
-                    <version>0</version>
-                    <state>1</state>
+                    <version>1</version>
+                    <state>0</state>
                </option>
            </data>
        </settings>
@ -1375,7 +1379,7 @@
                <option>
                    <name>CCXds100ProbeList</name>
                    <version>0</version>
-                    <state>3</state>
+                    <state>2</state>
                </option>
                <option>
                    <name>CCXds100SWOPortRadio</name>
@ -1441,11 +1445,11 @@
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file>
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file>
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
@ -1492,7 +1496,7 @@
            <name>C-SPY</name>
            <archiveVersion>2</archiveVersion>
            <data>
-                <version>31</version>
+                <version>32</version>
                <wantNonLocal>1</wantNonLocal>
                <debug>0</debug>
                <option>
@ -1521,11 +1525,11 @@
                </option>
                <option>
                    <name>MemOverride</name>
-                    <state>1</state>
+                    <state>0</state>
                </option>
                <option>
                    <name>MemFile</name>
-                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd</state>
+                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd</state>
                </option>
                <option>
                    <name>RunToEnable</name>
@ -1561,15 +1565,15 @@
                </option>
                <option>
                    <name>OCProductVersion</name>
-                    <state>8.40.1.21529</state>
+                    <state>7.70.1.11471</state>
                </option>
                <option>
                    <name>OCDynDriverList</name>
-                    <state>CMSISDAP_ID</state>
+                    <state>ARMSIM_ID</state>
                </option>
                <option>
                    <name>OCLastSavedByProductVersion</name>
-                    <state>8.40.1.21529</state>
+                    <state></state>
                </option>
                <option>
                    <name>UseFlashLoader</name>
@ -1593,7 +1597,7 @@
                </option>
                <option>
                    <name>FlashLoadersV3</name>
-                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/config/flashloader/HC32F460xE.board</state>
+                    <state>$PROJ_DIR$/../libraries/hc32f460_ddl/config/flashloader/FlashHC32F460xE.board</state>
                </option>
                <option>
                    <name>OCImagesSuppressCheck1</name>
@ -1621,7 +1625,7 @@
                </option>
                <option>
                    <name>OverrideDefFlashBoard</name>
-                    <state>1</state>
+                    <state>0</state>
                </option>
                <option>
                    <name>OCImagesOffset1</name>
@ -1661,7 +1665,7 @@
                </option>
                <option>
                    <name>OCMulticoreNrOfCores</name>
-                    <state>1</state>
+                    <state></state>
                </option>
                <option>
                    <name>OCMulticoreWorkspace</name>
@ -1699,6 +1703,10 @@
                    <name>OCMulticoreSessionFile</name>
                    <state></state>
                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
            </data>
        </settings>
        <settings>
@ -2484,7 +2492,7 @@
            <name>STLINK_ID</name>
            <archiveVersion>2</archiveVersion>
            <data>
-                <version>6</version>
+                <version>7</version>
                <wantNonLocal>1</wantNonLocal>
                <debug>0</debug>
                <option>
@ -2599,8 +2607,8 @@
                </option>
                <option>
                    <name>CCSTLinkProbeList</name>
-                    <version>0</version>
-                    <state>1</state>
+                    <version>1</version>
+                    <state>0</state>
                </option>
            </data>
        </settings>
@ -2856,7 +2864,7 @@
                <option>
                    <name>CCXds100ProbeList</name>
                    <version>0</version>
-                    <state>3</state>
+                    <state>2</state>
                </option>
                <option>
                    <name>CCXds100SWOPortRadio</name>
@ -2922,11 +2930,11 @@
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file>
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
-                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file>
                <loadFlag>0</loadFlag>
            </plugin>
            <plugin>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp
@ -179,12 +179,13 @@
        <debug>0</debug>
        <option>
          <name>CCDefines</name>
-          <state>__DEBUG</state>
+          <state />
          <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
          <state>RT_USING_DLIBC</state>
          <state>RT_USING_LIBC</state>
          <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
          <state>HC32F460</state>
+          <state>__DEBUG</state>
          <state>__RTTHREAD__</state>
          <state>USE_DDL_DRIVER</state>
        </option>
@ -316,27 +317,28 @@
        <option>
          <name>CCIncludePath2</name>
          <state />
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
          <state>$PROJ_DIR$\..\..\..\components\finsh</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
-          <state>$PROJ_DIR$\board\ports</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
          <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
-          <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\applications</state>
          <state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
-          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
-          <state>$PROJ_DIR$\board\config</state>
-          <state>$PROJ_DIR$\..\..\..\include</state>
-          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
+          <state>$PROJ_DIR$\.</state>
          <state>$PROJ_DIR$\board</state>
+          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
+          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+          <state>$PROJ_DIR$\board\ports</state>
+          <state>$PROJ_DIR$\applications</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
+          <state>$PROJ_DIR$\..\..\..\include</state>
+          <state>$PROJ_DIR$\board\config\usb_config</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
+          <state>$PROJ_DIR$\board\config</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
        </option>
        <option>
          <name>CCStdIncCheck</name>
@ -723,7 +725,8 @@
        </option>
        <option>
          <name>IlinkConfigDefines</name>
-          <state />
+          <state>_LINK_FLASH_= 0</state>
+          <state>_HC32F460_512K_= 1</state>
        </option>
        <option>
          <name>IlinkMapFile</name>
@ -1172,6 +1175,7 @@
          <state>RT_USING_LIBC</state>
          <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
          <state>HC32F460</state>
+          <state>__DEBUG</state>
          <state>__RTTHREAD__</state>
          <state>USE_DDL_DRIVER</state>
        </option>
@ -1303,27 +1307,28 @@
        <option>
          <name>CCIncludePath2</name>
          <state />
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
          <state>$PROJ_DIR$\..\..\..\components\finsh</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
-          <state>$PROJ_DIR$\board\ports</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
          <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
-          <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\applications</state>
          <state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
-          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
-          <state>$PROJ_DIR$\board\config</state>
-          <state>$PROJ_DIR$\..\..\..\include</state>
-          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
+          <state>$PROJ_DIR$\.</state>
          <state>$PROJ_DIR$\board</state>
+          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
+          <state>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+          <state>$PROJ_DIR$\board\ports</state>
+          <state>$PROJ_DIR$\applications</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
+          <state>$PROJ_DIR$\..\..\..\include</state>
+          <state>$PROJ_DIR$\board\config\usb_config</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
+          <state>$PROJ_DIR$\board\config</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
        </option>
        <option>
          <name>CCStdIncCheck</name>
@ -1706,7 +1711,8 @@
        </option>
        <option>
          <name>IlinkConfigDefines</name>
-          <state />
+          <state>_LINK_FLASH_= 0</state>
+          <state>_HC32F460_512K_= 1</state>
        </option>
        <option>
          <name>IlinkMapFile</name>
@ -1979,6 +1985,9 @@
    <file>
      <name>$PROJ_DIR$\applications\main.c</name>
    </file>
+    <file>
+      <name>$PROJ_DIR$\applications\xtal32_fcm.c</name>
+    </file>
  </group>
  <group>
    <name>Compiler</name>
@ -2090,6 +2099,9 @@
    <file>
      <name>$PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f460.s</name>
    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_common.c</name>
+    </file>
    <file>
      <name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c</name>
    </file>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx
@ -10,7 +10,7 @@
    <aExt>*.s*; *.src; *.a*</aExt>
    <oExt>*.obj; *.o</oExt>
    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
    <pExt>*.plm</pExt>
    <CppX>*.cpp</CppX>
    <nMigrate>0</nMigrate>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
@ -30,7 +30,7 @@
          <SLE66CMisc />
          <SLE66AMisc />
          <SLE66LinkerMisc />
-          <SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR</SFDFile>
+          <SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR</SFDFile>
          <bCustSvd>1</bCustSvd>
          <UseEnv>0</UseEnv>
          <BinPath />
@ -46,10 +46,10 @@
            <InvalidFlash>1</InvalidFlash>
          </TargetStatus>
          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
-          <OutputName>rtthread</OutputName>
+          <OutputName>rt-thread</OutputName>
          <CreateExecutable>1</CreateExecutable>
          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
+          <CreateHexFile>1</CreateHexFile>
          <DebugInformation>1</DebugInformation>
          <BrowseInformation>0</BrowseInformation>
          <ListingPath>.\build\keil\List\</ListingPath>
@ -182,8 +182,9 @@
            <uocXRam>0</uocXRam>
            <RvdsVP>1</RvdsVP>
            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
            <hadIRAM2>1</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
+            <hadIROM2>1</hadIROM2>
            <StupSel>8</StupSel>
            <useUlib>0</useUlib>
            <EndSel>1</EndSel>
@ -277,7 +278,7 @@
              <OCR_RVCT5>
                <Type>1</Type>
                <StartAddress>0x03000C00</StartAddress>
-                <Size>0x3FC</Size>
+                <Size>0x3C0</Size>
              </OCR_RVCT5>
              <OCR_RVCT6>
                <Type>0</Type>
@ -333,9 +334,9 @@
            <v6Rtti>0</v6Rtti>
            <VariousControls>
              <MiscControls />
-              <Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, USE_DDL_DRIVER, __RTTHREAD__</Define>
+              <Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, USE_DDL_DRIVER, __RTTHREAD__, __DEBUG</Define>
              <Undefine />
-              <IncludePath>..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;.;..\libraries\hc32f460_ddl\drivers\cmsis\Include;board;..\..\..\components\libc\compilers\common\extension;applications;..\..\..\libcpu\arm\cortex-m4;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board\ports;..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc;..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\..\..\components\drivers\include;..\libraries\hc32_drivers;..\..\..\components\libc\posix\ipc;board\config;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\finsh</IncludePath>
+              <IncludePath>..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\libraries\hc32_drivers;..\libraries\hc32f460_ddl\drivers\cmsis\Include;board\config;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;board\config\usb_config;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;board\ports;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc;.;board;..\..\..\libcpu\arm\cortex-m4;applications</IncludePath>
            </VariousControls>
          </Cads>
          <Aads>
@ -348,7 +349,7 @@
            <NoWarn>0</NoWarn>
            <uSurpInc>0</uSurpInc>
            <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
+            <ClangAsOpt>4</ClangAsOpt>
            <VariousControls>
              <MiscControls />
              <Define />
@ -385,6 +386,13 @@
              <FilePath>applications\main.c</FilePath>
            </File>
          </Files>
+          <Files>
+            <File>
+              <FileName>xtal32_fcm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\xtal32_fcm.c</FilePath>
+            </File>
+          </Files>
        </Group>
        <Group>
          <GroupName>Compiler</GroupName>
@ -579,6 +587,13 @@
              <FilePath>..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f460.s</FilePath>
            </File>
          </Files>
+          <Files>
+            <File>
+              <FileName>drv_common.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32_drivers\drv_common.c</FilePath>
+            </File>
+          </Files>
          <Files>
            <File>
              <FileName>drv_gpio.c</FileName>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h
@ -7,6 +7,7 @@
 /* RT-Thread Kernel */

 #define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
@ -38,14 +39,12 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
-
-/* Kernel Device Object */
-
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart4"
-#define RT_VER_NUM 0x50002
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
 #define RT_USING_HW_ATOMIC
 #define RT_USING_CPU_FFS
 #define ARCH_ARM
@ -85,6 +84,7 @@
 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN

@ -114,6 +114,9 @@
 /* Network */


+/* Memory protection */
+
+
 /* Utilities */


@ -133,6 +136,15 @@
 /* Wiced WiFi */


+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
 /* IoT Cloud */


@ -240,8 +252,13 @@

 #define SOC_HC32F460PE

+/* On-chip Drivers */
+
+#define BSP_USING_ON_CHIP_FLASH_CACHE
+
 /* Onboard Peripheral Drivers */

+
 /* On-chip Peripheral Drivers */

 #define BSP_USING_GPIO
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py
@ -17,7 +17,10 @@ if os.getenv('RTT_ROOT'):
 # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
 if  CROSS_TOOL == 'gcc':
    PLATFORM    = 'gcc'
-    EXEC_PATH   = r'C:/Users/XXYYZZ'
+    if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    else:
+        EXEC_PATH   = r'C:/Users/XXYYZZ'
 elif CROSS_TOOL == 'keil':
    PLATFORM    = 'armcc'
    EXEC_PATH   = r'C:/Keil_v5'
@ -25,9 +28,6 @@ elif CROSS_TOOL == 'iar':
    PLATFORM    = 'iccarm'
    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'

-if os.getenv('RTT_EXEC_PATH'):
-    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
 BUILD = 'debug'

 if PLATFORM == 'gcc':
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/settings/project.dni
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/settings/project.dni
@ -0,0 +1,42 @@
+[PlDriver]
+MemConfigValue=$PROJ_DIR$/../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd
+[PlCacheRanges]
+CustomRanges0=0 0 524288 1 2048
+CustomRangesText0=Flash
+CustomRanges1=0 50334720 1020 1 2048
+CustomRangesText1=OTP
+CustomRanges2=0 536838144 192512 0 2048
+CustomRangesText2=SRAM
+CustomRanges3=0 537853952 4096 0 2048
+CustomRangesText3=RET_SRAM
+CustomRanges4=0 1073741824 536870912 2 0
+CustomRangesText4=Peripheral
+CustomRanges5=0 2550136832 67108864 1 2048
+CustomRangesText5=QSPI
+CustomRanges6=0 2617245696 67108864 2 67108864
+CustomRangesText6=QSPI_REG
+CustomRanges7=0 3758096384 536870912 2 0
+CustomRangesText7=Private peripheral
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[Disassemble mode]
+mode=0
+[Breakpoints2]
+Count=0
+[Aliases]
+Count=0
+SuppressDialog=0
+[Jet]
+DisableInterrupts=0
+LeaveRunning=0
+MultiCoreRunAll=0
+[ArmDriver]
+EnableCache=0
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp
@ -181,7 +181,7 @@
        <debug>0</debug>
        <option>
          <name>CCDefines</name>
-          <state>__DEBUG</state>
+          <state></state>
        </option>
        <option>
          <name>CCPreprocFile</name>
@ -697,7 +697,8 @@
        </option>
        <option>
          <name>IlinkConfigDefines</name>
-          <state></state>
+          <state>_LINK_FLASH_= 0</state>
+          <state>_HC32F460_512K_= 1</state>
        </option>
        <option>
          <name>IlinkMapFile</name>
@ -1652,7 +1653,8 @@
        </option>
        <option>
          <name>IlinkConfigDefines</name>
-          <state></state>
+          <state>_LINK_FLASH_= 0</state>
+          <state>_HC32F460_512K_= 1</state>
        </option>
        <option>
          <name>IlinkMapFile</name>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvoptx
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvoptx
@ -10,7 +10,7 @@
    <aExt>*.s*; *.src; *.a*</aExt>
    <oExt>*.obj; *.o</oExt>
    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
    <pExt>*.plm</pExt>
    <CppX>*.cpp</CppX>
    <nMigrate>0</nMigrate>
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx
@ -33,7 +33,7 @@
          <SLE66CMisc></SLE66CMisc>
          <SLE66AMisc></SLE66AMisc>
          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR</SFDFile>
+          <SFDFile>../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR</SFDFile>
          <bCustSvd>1</bCustSvd>
          <UseEnv>0</UseEnv>
          <BinPath></BinPath>
@ -49,10 +49,10 @@
            <InvalidFlash>1</InvalidFlash>
          </TargetStatus>
          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
-          <OutputName>rtthread</OutputName>
+          <OutputName>rt-thread</OutputName>
          <CreateExecutable>1</CreateExecutable>
          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
+          <CreateHexFile>1</CreateHexFile>
          <DebugInformation>1</DebugInformation>
          <BrowseInformation>0</BrowseInformation>
          <ListingPath>.\build\keil\List\</ListingPath>
@ -185,8 +185,9 @@
            <uocXRam>0</uocXRam>
            <RvdsVP>1</RvdsVP>
            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
            <hadIRAM2>1</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
+            <hadIROM2>1</hadIROM2>
            <StupSel>8</StupSel>
            <useUlib>0</useUlib>
            <EndSel>1</EndSel>
@ -280,7 +281,7 @@
              <OCR_RVCT5>
                <Type>1</Type>
                <StartAddress>0x03000C00</StartAddress>
-                <Size>0x3FC</Size>
+                <Size>0x3C0</Size>
              </OCR_RVCT5>
              <OCR_RVCT6>
                <Type>0</Type>
@ -351,7 +352,7 @@
            <NoWarn>0</NoWarn>
            <uSurpInc>0</uSurpInc>
            <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
+            <ClangAsOpt>4</ClangAsOpt>
            <VariousControls>
              <MiscControls></MiscControls>
              <Define></Define>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/.config
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.config
@ -9,8 +9,10 @@
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@ -20,22 +22,26 @@ CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512

 #
 # kservice optimization
 #
-# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
 # CONFIG_RT_KPRINTF_USING_LONGLONG is not set
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
-# CONFIG_RT_DEBUGING_INIT is not set
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set

 #
 # Inter-Thread communication
@ -63,19 +69,15 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x50002
+CONFIG_RT_VER_NUM=0x50100
 # CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # CONFIG_RT_USING_CACHE is not set
 CONFIG_RT_USING_HW_ATOMIC=y
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@ -119,6 +121,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 #
 # Device Drivers
 #
+# CONFIG_RT_USING_DM is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
@ -127,7 +130,7 @@ CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
-# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
@ -144,7 +147,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@ -215,6 +217,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set

+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
 #
 # Utilities
 #
@ -267,6 +275,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
 # CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@ -288,7 +311,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@ -309,6 +331,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NMEALIB is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@ -328,6 +352,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZFTP is not set
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set

 #
 # security packages
@ -374,7 +400,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # LVGL: powerful and easy-to-use embedded GUI library
 #
 # CONFIG_PKG_USING_LVGL is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set

@ -451,6 +476,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 # CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set

 #
 # system packages
@ -487,6 +513,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
@ -510,6 +538,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QBOOT is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
 # CONFIG_PKG_USING_EVENT_RECORDER is not set
@ -523,6 +552,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
 # CONFIG_PKG_USING_FLASH_BLOB is not set
 # CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set

 #
 # peripheral libraries and drivers
@ -587,6 +621,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
 # CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_MAX17048 is not set
@ -687,6 +722,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FINGERPRINT is not set
 # CONFIG_PKG_USING_BT_ECB02C is not set
 # CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set

 #
@ -701,6 +741,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set

 #
 # Signal Processing and Control Algorithm Packages
@ -710,6 +751,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set

 #
 # miscellaneous packages
@ -741,12 +783,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_COWSAY is not set
 # CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@ -784,6 +828,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set

@ -791,13 +836,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@ -842,7 +887,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@ -881,7 +926,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@ -904,7 +948,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@ -912,7 +956,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@ -925,12 +969,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set

 #
 # Display
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
@ -939,6 +985,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # Timing
 #
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
@ -964,18 +1011,17 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set

 #
 # Other
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set

 #
 # Signal IO
@ -1000,11 +1046,21 @@ CONFIG_SOC_SERIES_HC32F4=y
 #
 CONFIG_SOC_HC32F4A0SI=y

+#
+# On-chip Drivers
+#
+CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y
+
 #
 # Onboard Peripheral Drivers
 #
 # CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_TCA9539 is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_MT29F2G08AB is not set

 #
 # On-chip Peripheral Drivers
@ -1023,10 +1079,23 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART8 is not set
 # CONFIG_BSP_USING_UART9 is not set
 # CONFIG_BSP_USING_UART10 is not set
-# CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
 # CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_WDT_TMR is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_EXMC is not set
+# CONFIG_BSP_USING_PM is not set
+# CONFIG_BSP_USING_HWCRYPTO is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_QSPI is not set
+# CONFIG_BSP_USING_PULSE_ENCODER is not set
+# CONFIG_BSP_USING_HWTIMER is not set

 #
 # Board extended module Drivers
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/.cproject
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.cproject
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/.project
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.project
@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/libraries</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md
@ -40,17 +40,31 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下：
 | **板载外设**  | **支持情况** |               **备注**                |
 | :------------ | :-----------: | :-----------------------------------: |
 | USB 转串口    |      支持     |          使用 UART1                  |
-| LED           |     支持     |           LED                        |
 | ETH           |     支持     |              					     |
-| ADC           |     支持     |                                       |
-| CAN           |     支持     |                                       |
+| LED           |     支持     |           LED                        |
+| Nand | 支持 | MT29F2G08AB |
+| SDRAM | 支持 | IS42S16400J |
+
 | **片上外设**  | **支持情况** |               **备注**                |
 | :------------ | :-----------: | :-----------------------------------: |
+| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
+| DAC | 支持 |  |
+| ADC           |     支持     |                             |
+| CAN           |     支持     |                                       |
 | GPIO          |     支持     | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
-| UART          |     支持     |              UART1~10                 |
+| PM | 支持 |  |
+| Lptimer | 支持 |  |
+| Hwtimer | 支持 |  |
+| Pulse_encoder | 支持 |  |
+| PWM | 支持 |  |
+| RTC | 支持 | 闹钟精度为1分钟 |
+| WDT | 支持 |  |
+| I2C           |     支持     |              软件、硬件 I2C                 |
+| QSPI | 支持 |  |
 | SPI           |     支持     |              SPI1~6                   |
-| I2C           |     支持     |              软件 I2C                 |
-
+| SDIO | 支持 |  |
+| UART V1 & V2         |     支持     |              UART1~10                 |
+| USB | 支持 | USBFS/HS Core， device/host模式 |

 ## 使用说明

@ -107,8 +121,19 @@ msh >

 ## 注意事项

+| 板载外设 |  模式  | 注意事项                                                     |
+| :------: | :----: | :----------------------------------------------------------- |
+|   USB    | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） |
+|   USB    | device | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
+|   USB    |  host  | 由于main()函数中的LED闪烁示例，使用的是USBFS主机口的供电控制管脚，因而当配置为使用USBFS Core的主机模式时，需要将main()函数中的LED示例代码手动屏蔽。 |
+|   USB    |  host  | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 |
+|   USB    |  host  | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
+|   USB    |  host  | 目前仅实现并测试了对U盘的支持。                              |
+|   USB    |  host  | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
+|   USB    |  ALL   | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 |
+
 ## 联系人信息

 维护人:

-  [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
+-  [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct
@ -56,5 +56,7 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

+objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -13,7 +12,6 @@
 #include <rtdevice.h>
 #include <board.h>

-
 /* defined the LED_GREEN pin: PC9 */
 #define LED_GREEN_PIN GET_PIN(C, 9)

--- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c
@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-10-27     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
@ -15,9 +15,13 @@ board_config.c
 if GetDepend(['BSP_USING_TCA9539']):
    src += Glob('ports/tca9539.c')

+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/drv_spi_flash.c')
+
 path =  [cwd]
 path += [cwd + '/ports']
 path += [cwd + '/config']
+path += [cwd + '/config/usb_config']

 startup_path_prefix = SDK_LIB

@ -28,7 +32,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']:
 elif rtconfig.PLATFORM in ['iccarm']:
    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']

-CPPDEFINES = ['HC32F4A0']
+CPPDEFINES = ['HC32F4A0', '__DEBUG']
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

 Return('group')
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -10,37 +9,50 @@
 */

 #include "board.h"
-
-#ifdef RT_USING_PIN
-#include <drv_gpio.h>
-#endif
-
-#ifdef RT_USING_SERIAL
-#ifdef RT_USING_SERIAL_V2
-#include <drv_usart_v2.h>
-#else
-#include <drv_usart.h>
-#endif /* RT_USING_SERIAL */
-#endif /* RT_USING_SERIAL_V2 */
+#include "board_config.h"

 /* unlock/lock peripheral */
 #define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
 #define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)

+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
 /**
-  * @brief  This function is executed in case of error occurrence.
-  * @param  None
-  * @retval None
-  */
-void Error_Handler(void)
+ * @brief Switch clock stable time
+ * @note Approx. 30us
+ */
+#define CLK_SYSCLK_SW_STB               (HCLK_VALUE / 50000UL)
+/**
+ * @brief Clk delay function
+ * @param [in] u32Delay         count
+ * @retval when switch clock source, should be delay some time to wait stable.
+ */
+static void CLK_Delay(uint32_t u32Delay)
 {
-    /* USER CODE BEGIN Error_Handler */
-    /* User can add his own implementation to report the HAL error return state */
-    while (1)
+    __IO uint32_t u32Timeout = 0UL;
+
+    while (u32Timeout < u32Delay)
    {
+        u32Timeout++;
    }
-    /* USER CODE END Error_Handler */
+}
+#endif
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+    EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+    EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+    EFM_PrefetchCmd(ENABLE);
+#endif
+    /* Reset the VBAT area */
+    PWC_VBAT_Reset();
 }

 /** System Clock Configuration
@ -49,6 +61,12 @@ void SystemClock_Config(void)
 {
    stc_clock_xtal_init_t stcXtalInit;
    stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    stc_clock_pllx_init_t stcPLLAInit;
+#endif
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif

    /* PCLK0, HCLK  Max 240MHz */
    /* PCLK1, PCLK4 Max 120MHz */
@ -59,6 +77,7 @@ void SystemClock_Config(void)
                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
                     CLK_HCLK_DIV1));

+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
    (void)CLK_XtalStructInit(&stcXtalInit);
    /* Config Xtal and enable Xtal */
    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
@ -81,122 +100,66 @@ void SystemClock_Config(void)

    /* Highspeed SRAM set to 0 Read/Write wait cycle */
    SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
-
    /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
    SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
-
    /* 0-wait @ 40MHz */
    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
-
    /* 4 cycles for 200 ~ 250MHz */
    GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
-
    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    /* PLLX for USB */
+    (void)CLK_PLLxStructInit(&stcPLLAInit);
+    /* VCO = (8/2)*120 = 480MHz*/
+    stcPLLAInit.u8PLLState = CLK_PLL_ON;
+    stcPLLAInit.PLLCFGR = 0UL;
+    stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    (void)CLK_PLLxInit(&stcPLLAInit);
+#endif
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
 }

 /** Peripheral Clock Configuration
 */
-static void PeripheralClock_Config(void)
+void PeripheralClock_Config(void)
 {
-#if defined(HC32F4A0)
 #if defined(BSP_USING_CAN1)
    CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
 #endif
-#if   defined(BSP_USING_CAN2)
+#if defined(BSP_USING_CAN2)
    CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
 #endif

 #if defined(RT_USING_ADC)
    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
 #endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
+    /* Wait stable here, since the current DDL API does not include this */
+    CLK_Delay(CLK_SYSCLK_SW_STB);
 #endif
 }

-/*******************************************************************************
- * Function Name  : SysTick_Configuration
- * Description    : Configures the SysTick for OS tick.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void  SysTick_Configuration(void)
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
 {
-    stc_clock_freq_t stcClkFreq;
-    rt_uint32_t cnts;
-
-    CLK_GetClockFreq(&stcClkFreq);
-
-    cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
-
-    SysTick_Config(cnts);
-}
-
-/**
- * This is the timer interrupt service routine.
- *
- */
-void SysTick_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/**
- * This function will initial HC32 board.
- */
-void rt_hw_board_init()
-{
-    /* Peripheral registers write unprotected */
    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
-
-    SystemClock_Config();
-    PeripheralClock_Config();
-    /* Configure the SysTick */
-    SysTick_Configuration();
-
-    /* Heap initialization */
-#if defined(RT_USING_HEAP)
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
-#endif
-
-    /* Pin driver initialization is open by default */
-#ifdef RT_USING_PIN
-    rt_hw_pin_init();
-#endif
-
-    /* USART driver initialization is open by default */
-#ifdef RT_USING_SERIAL
-    rt_hw_usart_init();
-#endif
-
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-
-    /* Board underlying hardware initialization */
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
-
-void rt_hw_us_delay(rt_uint32_t us)
-{
-    uint32_t start, now, delta, reload, us_tick;
-    start = SysTick->VAL;
-    reload = SysTick->LOAD;
-    us_tick = SystemCoreClock / 1000000UL;
-
-    do
-    {
-        now = SysTick->VAL;
-        delta = start > now ?  start - now : reload + start - now;
-    }
-    while (delta < us_tick * us);
 }

 /*@}*/
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -20,12 +19,18 @@
 extern "C" {
 #endif

+
+#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_SIZE                 (2 * 1024 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
 #define HC32_SRAM_SIZE                  (512)
 #define HC32_SRAM_END                   (0x1FFE0000 + HC32_SRAM_SIZE * 1024)

 #ifdef __ARMCC_VERSION
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define HEAP_BEGIN                      (&Image$$RW_IRAM1$$ZI$$Limit)
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
 #elif __ICCARM__
 #pragma section="HEAP"
 #define HEAP_BEGIN                      (__segment_end("HEAP"))
@ -36,6 +41,11 @@ extern int __bss_end;

 #define HEAP_END                        HC32_SRAM_END

+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -27,15 +26,15 @@ rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
 #if defined(BSP_USING_UART1)
    case (rt_uint32_t)CM_USART1:
        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33);
-        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32);
+        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
+        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
        break;
 #endif
 #if defined(BSP_USING_UART6)
    case (rt_uint32_t)CM_USART6:
        /* Configure USART RX/TX pin. */
-        GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, GPIO_FUNC_37);
-        GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, GPIO_FUNC_36);
+        GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC);
+        GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC);
        break;
 #endif
    default:
@ -47,6 +46,30 @@ rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
 }
 #endif

+#if defined(RT_USING_I2C)
+rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);
+
+    switch ((rt_uint32_t)I2Cx)
+    {
+#if defined(BSP_USING_I2C1)
+    case (rt_uint32_t)CM_I2C1:
+        /* Configure I2C1 SDA/SCL pin. */
+        GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
+        GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
 #if defined(RT_USING_ADC)
 rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
 {
@ -81,6 +104,37 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
 }
 #endif

+#if defined(RT_USING_DAC)
+rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)DACx)
+    {
+#if defined(BSP_USING_DAC1)
+    case (rt_uint32_t)CM_DAC1:
+        (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
+        (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_DAC2)
+    case (rt_uint32_t)CM_DAC2:
+        (void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit);
+        (void)GPIO_Init(DAC2_CH2_PORT, DAC2_CH2_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
 #if defined(RT_USING_CAN)
 void CanPhyEnable(void)
 {
@ -119,14 +173,29 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
 rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
 {
    rt_err_t result = RT_EOK;
+#if defined(BSP_USING_SPI1)
+    stc_gpio_init_t stcGpioInit;
+#endif

    switch ((rt_uint32_t)CM_SPIx)
    {
 #if defined(BSP_USING_SPI1)
    case (rt_uint32_t)CM_SPI1:
-        GPIO_SetFunc(GPIO_PORT_C, GPIO_PIN_06, GPIO_FUNC_40);   /* SCK  */
-        GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_13, GPIO_FUNC_41);   /* MOSI */
-        GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_12, GPIO_FUNC_42);   /* MISO */
+        GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinState = PIN_STAT_SET;
+        stcGpioInit.u16PinDir   = PIN_DIR_OUT;
+        GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
+        GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
+
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
+        (void)GPIO_Init(SPI1_SCK_PORT,  SPI1_SCK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
+        (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
+        GPIO_SetFunc(SPI1_SCK_PORT,  SPI1_SCK_PIN,  SPI1_SCK_FUNC);
+        GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
+        GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
        break;
 #endif
    default:
@ -154,60 +223,479 @@ rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx)

 rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx)
 {
-#if defined(ETH_USING_INTERFACE_RMII)
-    /*
-        ETH_SMI_MDIO ----------------> PA2
-        ETH_SMI_MDC -----------------> PC1
-        ETH_RMII_TX_EN --------------> PG11
-        ETH_RMII_TXD0 ---------------> PG13
-        ETH_RMII_TXD1 ---------------> PG14
-        ETH_RMII_REF_CLK ------------> PA1
-        ETH_RMII_CRS_DV -------------> PA7
-        ETH_RMII_RXD0 ---------------> PC4
-        ETH_RMII_RXD1 ---------------> PC5
-        ETH_RMII_RX_ER --------------> PI10
-    */
-    /* Configure PA1, PA2 and PA7 */
-    GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
-    /* Configure PC1, PC4 and PC5 */
-    GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
-    /* Configure PG11, PG13 and PG14 */
-    GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
-    /* Configure PI10 */
-    GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
+#if defined(ETH_INTERFACE_USING_RMII)
+    GPIO_SetFunc(ETH_SMI_MDIO_PORT,     ETH_SMI_MDIO_PIN,     ETH_SMI_MDIO_FUNC);
+    GPIO_SetFunc(ETH_SMI_MDC_PORT,      ETH_SMI_MDC_PIN,      ETH_SMI_MDC_FUNC);
+    GPIO_SetFunc(ETH_RMII_TX_EN_PORT,   ETH_RMII_TX_EN_PIN,   ETH_RMII_TX_EN_FUNC);
+    GPIO_SetFunc(ETH_RMII_TXD0_PORT,    ETH_RMII_TXD0_PIN,    ETH_RMII_TXD0_FUNC);
+    GPIO_SetFunc(ETH_RMII_TXD1_PORT,    ETH_RMII_TXD1_PIN,    ETH_RMII_TXD1_FUNC);
+    GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC);
+    GPIO_SetFunc(ETH_RMII_CRS_DV_PORT,  ETH_RMII_CRS_DV_PIN,  ETH_RMII_CRS_DV_FUNC);
+    GPIO_SetFunc(ETH_RMII_RXD0_PORT,    ETH_RMII_RXD0_PIN,    ETH_RMII_RXD0_FUNC);
+    GPIO_SetFunc(ETH_RMII_RXD1_PORT,    ETH_RMII_RXD1_PIN,    ETH_RMII_RXD1_FUNC);
 #else
-    /*
-        ETH_SMI_MDIO ----------------> PA2
-        ETH_SMI_MDC -----------------> PC1
-        ETH_MII_TX_CLK --------------> PB6
-        ETH_MII_TX_EN ---------------> PG11
-        ETH_MII_TXD0 ----------------> PG13
-        ETH_MII_TXD1 ----------------> PG14
-        ETH_MII_TXD2 ----------------> PB9
-        ETH_MII_TXD3 ----------------> PB8
-        ETH_MII_RX_CLK --------------> PA1
-        ETH_MII_RX_DV ---------------> PA7
-        ETH_MII_RXD0 ----------------> PC4
-        ETH_MII_RXD1 ----------------> PC5
-        ETH_MII_RXD2 ----------------> PB0
-        ETH_MII_RXD3 ----------------> PB1
-        ETH_MII_RX_ER ---------------> PI10
-        ETH_MII_CRS -----------------> PH2
-        ETH_MII_COL -----------------> PH3
-    */
-    /* Configure PA1, PA2 and PA7 */
-    GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
-    /* Configure PB0, PB1, PB6, PB8 and PB9 */
-    GPIO_SetFunc(GPIO_PORT_B, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_06 | GPIO_PIN_08 | GPIO_PIN_09), GPIO_FUNC_11);
-    /* Configure PC1, PC4 and PC5 */
-    GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
-    /* Configure PG11, PG13 and PG14 */
-    GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
-    /* Configure PH2, PH3 */
-    GPIO_SetFunc(GPIO_PORT_H, (GPIO_PIN_02 | GPIO_PIN_03), GPIO_FUNC_11);
-    /* Configure PI10 */
-    GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
+    GPIO_SetFunc(ETH_SMI_MDIO_PORT,   ETH_SMI_MDIO_PIN,   ETH_SMI_MDIO_FUNC);
+    GPIO_SetFunc(ETH_SMI_MDC_PORT,    ETH_SMI_MDC_PIN,    ETH_SMI_MDC_FUNC);
+    GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC);
+    GPIO_SetFunc(ETH_MII_TX_EN_PORT,  ETH_MII_TX_EN_PIN,  ETH_MII_TX_EN_FUNC);
+    GPIO_SetFunc(ETH_MII_TXD0_PORT,   ETH_MII_TXD0_PIN,   ETH_MII_TXD0_FUNC);
+    GPIO_SetFunc(ETH_MII_TXD1_PORT,   ETH_MII_TXD1_PIN,   ETH_MII_TXD1_FUNC);
+    GPIO_SetFunc(ETH_MII_TXD2_PORT,   ETH_MII_TXD2_PIN,   ETH_MII_TXD2_FUNC);
+    GPIO_SetFunc(ETH_MII_TXD3_PORT,   ETH_MII_TXD3_PIN,   ETH_MII_TXD3_FUNC);
+    GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC);
+    GPIO_SetFunc(ETH_MII_RX_DV_PORT,  ETH_MII_RX_DV_PIN,  ETH_MII_RX_DV_FUNC);
+    GPIO_SetFunc(ETH_MII_RXD0_PORT,   ETH_MII_RXD0_PIN,   ETH_MII_RXD0_FUNC);
+    GPIO_SetFunc(ETH_MII_RXD1_PORT,   ETH_MII_RXD1_PIN,   ETH_MII_RXD1_FUNC);
+    GPIO_SetFunc(ETH_MII_RXD2_PORT,   ETH_MII_RXD2_PIN,   ETH_MII_RXD2_FUNC);
+    GPIO_SetFunc(ETH_MII_RXD3_PORT,   ETH_MII_RXD3_PIN,   ETH_MII_RXD3_FUNC);
+    GPIO_SetFunc(ETH_MII_RX_ER_PORT,  ETH_MII_RX_ER_PIN,  ETH_MII_RX_ER_FUNC);
+    GPIO_SetFunc(ETH_MII_CRS_PORT,    ETH_MII_CRS_PIN,    ETH_MII_CRS_FUNC);
+    GPIO_SetFunc(ETH_MII_COL_PORT,    ETH_MII_COL_PIN,    ETH_MII_COL_FUNC);
 #endif
    return RT_EOK;
 }
 #endif
+
+#if defined (RT_USING_SDIO)
+rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    switch ((rt_uint32_t)SDIOCx)
+    {
+#if defined(BSP_USING_SDIO1)
+    case (rt_uint32_t)CM_SDIOC1:
+        /************************* Set pin drive capacity *************************/
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        (void)GPIO_Init(SDIOC1_CK_PORT,  SDIOC1_CK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D0_PORT,  SDIOC1_D0_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D1_PORT,  SDIOC1_D1_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D2_PORT,  SDIOC1_D2_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SDIOC1_D3_PORT,  SDIOC1_D3_PIN,  &stcGpioInit);
+
+        GPIO_SetFunc(SDIOC1_CK_PORT,  SDIOC1_CK_PIN,  SDIOC1_CK_FUNC);
+        GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC);
+        GPIO_SetFunc(SDIOC1_D0_PORT,  SDIOC1_D0_PIN,  SDIOC1_D0_FUNC);
+        GPIO_SetFunc(SDIOC1_D1_PORT,  SDIOC1_D1_PIN,  SDIOC1_D1_FUNC);
+        GPIO_SetFunc(SDIOC1_D2_PORT,  SDIOC1_D2_PIN,  SDIOC1_D2_FUNC);
+        GPIO_SetFunc(SDIOC1_D3_PORT,  SDIOC1_D3_PIN,  SDIOC1_D3_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_PWM)
+#if defined(BSP_USING_PWM_TMRA)
+rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMRAx)
+    {
+#if defined(BSP_USING_PWM_TMRA_1)
+    case (rt_uint32_t)CM_TMRA_1:
+#ifdef BSP_USING_PWM_TMRA_1_CH1
+        GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH2
+        GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH3
+        GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH4
+        GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
+#endif
+        break;
+#endif
+
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR4)
+rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR4x)
+    {
+#if defined(BSP_USING_PWM_TMR4_1)
+    case (rt_uint32_t)CM_TMR4_1:
+#ifdef BSP_USING_PWM_TMR4_1_OUH
+        GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OUL
+        GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVH
+        GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVL
+        GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWH
+        GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWL
+        GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
+#endif
+        break;
+#endif
+
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR6)
+rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR6x)
+    {
+#if defined(BSP_USING_PWM_TMR6_1)
+    case (rt_uint32_t)CM_TMR6_1:
+#ifdef BSP_USING_PWM_TMR6_1_A
+        GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR6_1_B
+        GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
+#endif
+        break;
+#endif
+
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+#endif
+
+#if defined (BSP_USING_SDRAM)
+rt_err_t rt_hw_board_sdram_init(void)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    /************************* Set pin drive capacity *************************/
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+    /* DMC_CKE */
+    (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit);
+    /* DMC_CLK */
+    (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit);
+    /* DMC_LDQM && DMC_UDQM */
+    (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit);
+    /* DMC_BA[0:1] */
+    (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit);
+    /* DMC_CAS && DMC_RAS */
+    (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit);
+    /* DMC_WE */
+    (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit);
+    /* DMC_DATA[0:15] */
+    (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit);
+    /* DMC_ADD[0:11]*/
+    (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit);
+    (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit);
+
+    /************************** Set EXMC pin function *************************/
+    /* DMC_CKE */
+    GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC);
+    /* DMC_CLK */
+    GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC);
+    /* DMC_LDQM && DMC_UDQM */
+    GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC);
+    GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC);
+    /* DMC_BA[0:1] */
+    GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC);
+    GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC);
+    /* DMC_CS */
+    GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC);
+    /* DMC_CAS && DMC_RAS */
+    GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC);
+    GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC);
+    /* DMC_WE */
+    GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC);
+    /* DMC_DATA[0:15] */
+    GPIO_SetFunc(SDRAM_DATA0_PORT,  SDRAM_DATA0_PIN,  SDRAM_DATA0_FUNC);
+    GPIO_SetFunc(SDRAM_DATA1_PORT,  SDRAM_DATA1_PIN,  SDRAM_DATA1_FUNC);
+    GPIO_SetFunc(SDRAM_DATA2_PORT,  SDRAM_DATA2_PIN,  SDRAM_DATA2_FUNC);
+    GPIO_SetFunc(SDRAM_DATA3_PORT,  SDRAM_DATA3_PIN,  SDRAM_DATA3_FUNC);
+    GPIO_SetFunc(SDRAM_DATA4_PORT,  SDRAM_DATA4_PIN,  SDRAM_DATA4_FUNC);
+    GPIO_SetFunc(SDRAM_DATA5_PORT,  SDRAM_DATA5_PIN,  SDRAM_DATA5_FUNC);
+    GPIO_SetFunc(SDRAM_DATA6_PORT,  SDRAM_DATA6_PIN,  SDRAM_DATA6_FUNC);
+    GPIO_SetFunc(SDRAM_DATA7_PORT,  SDRAM_DATA7_PIN,  SDRAM_DATA7_FUNC);
+    GPIO_SetFunc(SDRAM_DATA8_PORT,  SDRAM_DATA8_PIN,  SDRAM_DATA8_FUNC);
+    GPIO_SetFunc(SDRAM_DATA9_PORT,  SDRAM_DATA9_PIN,  SDRAM_DATA9_FUNC);
+    GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC);
+    GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC);
+    GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC);
+    GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC);
+    GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC);
+    GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC);
+    /* DMC_ADD[0:11]*/
+    GPIO_SetFunc(SDRAM_ADD0_PORT,  SDRAM_ADD0_PIN,  SDRAM_ADD0_FUNC);
+    GPIO_SetFunc(SDRAM_ADD1_PORT,  SDRAM_ADD1_PIN,  SDRAM_ADD1_FUNC);
+    GPIO_SetFunc(SDRAM_ADD2_PORT,  SDRAM_ADD2_PIN,  SDRAM_ADD2_FUNC);
+    GPIO_SetFunc(SDRAM_ADD3_PORT,  SDRAM_ADD3_PIN,  SDRAM_ADD3_FUNC);
+    GPIO_SetFunc(SDRAM_ADD4_PORT,  SDRAM_ADD4_PIN,  SDRAM_ADD4_FUNC);
+    GPIO_SetFunc(SDRAM_ADD5_PORT,  SDRAM_ADD5_PIN,  SDRAM_ADD5_FUNC);
+    GPIO_SetFunc(SDRAM_ADD6_PORT,  SDRAM_ADD6_PIN,  SDRAM_ADD6_FUNC);
+    GPIO_SetFunc(SDRAM_ADD7_PORT,  SDRAM_ADD7_PIN,  SDRAM_ADD7_FUNC);
+    GPIO_SetFunc(SDRAM_ADD8_PORT,  SDRAM_ADD8_PIN,  SDRAM_ADD8_FUNC);
+    GPIO_SetFunc(SDRAM_ADD9_PORT,  SDRAM_ADD9_PIN,  SDRAM_ADD9_FUNC);
+    GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC);
+    GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC);
+
+    return result;
+}
+#endif
+
+#ifdef RT_USING_PM
+void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
+{
+    switch (run_mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+        break;
+
+    case PM_RUN_MODE_LOW_SPEED:
+        /* Ensure that system clock less than 8M */
+        CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
+
+    default:
+        break;
+    }
+}
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+rt_err_t rt_hw_usb_board_init(void)
+{
+    stc_gpio_init_t stcGpioCfg;
+    (void)GPIO_StructInit(&stcGpioCfg);
+#if defined(BSP_USING_USBFS)
+    stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG;
+    (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg);
+#if defined(BSP_USING_USBD)
+    GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */
+#endif
+#if defined(BSP_USING_USBH)
+    GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */
+#endif
+#elif defined(BSP_USING_USBHS)
+#if defined(BSP_USING_USBHS_PHY_EMBED)
+    /* USBHS work in embedded PHY */
+    stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG;
+    (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg);
+#if defined(BSP_USING_USBD)
+    GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC);
+#endif
+#if defined(BSP_USING_USBH)
+    GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE);
+    GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */
+#endif
+#else
+    /* Reset 3300 */
+    TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET);
+    TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT);
+
+    (void)GPIO_StructInit(&stcGpioCfg);
+    /* High drive capability */
+    stcGpioCfg.u16PinDrv = PIN_HIGH_DRV;
+    (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg);
+    (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg);
+
+    GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC);
+    GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC);
+    GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC);
+    GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D0_PORT,  USBH_ULPI_D0_PIN,  USBH_ULPI_D0_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D1_PORT,  USBH_ULPI_D1_PIN,  USBH_ULPI_D1_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D2_PORT,  USBH_ULPI_D2_PIN,  USBH_ULPI_D2_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D3_PORT,  USBH_ULPI_D3_PIN,  USBH_ULPI_D3_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D4_PORT,  USBH_ULPI_D4_PIN,  USBH_ULPI_D4_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D5_PORT,  USBH_ULPI_D5_PIN,  USBH_ULPI_D5_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D6_PORT,  USBH_ULPI_D6_PIN,  USBH_ULPI_D6_FUNC);
+    GPIO_SetFunc(USBH_ULPI_D7_PORT,  USBH_ULPI_D7_PIN,  USBH_ULPI_D7_FUNC);
+
+    TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET);
+#endif
+
+#endif
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_QSPI)
+rt_err_t rt_hw_qspi_board_init(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+#ifndef BSP_QSPI_USING_SOFT_CS
+    (void)GPIO_Init(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  QSPI_FLASH_CS_FUNC);
+#endif
+    (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMRA_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
+#endif
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMR6_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
+#endif
+
+    return RT_EOK;
+}
+#endif
+
+#if defined (BSP_USING_NAND)
+rt_err_t rt_hw_board_nand_init(void)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    /************************* Set pin drive capacity *************************/
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+
+    /* NFC_CE */
+    (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit);
+    /* NFC_RE */
+    (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit);
+    /* NFC_WE */
+    (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit);
+    /* NFC_CLE */
+    (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit);
+    /* NFC_ALE */
+    (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit);
+    /* NFC_WP */
+    (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit);
+    GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN);
+
+    /* NFC_DATA[0:7] */
+    (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit);
+    (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit);
+    /* NFC_RB */
+    (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit);
+
+    /************************** Set EXMC pin function *************************/
+    /* NFC_CE */
+    GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC);
+    /* NFC_RE */
+    GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC);
+    /* NFC_WE */
+    GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC);
+    /* NFC_CLE */
+    GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC);
+    /* NFC_ALE */
+    GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC);
+    /* NFC_WP */
+    GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC);
+    /* NFC_RB */
+    GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC);
+    /* NFC_DATA[0:7] */
+    GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC);
+    GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC);
+    GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC);
+    GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC);
+    GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC);
+    GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC);
+    GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC);
+    GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC);
+
+    return result;
+}
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -18,58 +17,662 @@
 #include "drv_config.h"


+/************************* XTAL port **********************/
+#define XTAL_PORT                       (GPIO_PORT_H)
+#define XTAL_IN_PIN                     (GPIO_PIN_01)
+#define XTAL_OUT_PIN                    (GPIO_PIN_00)
+
 /************************ USART port **********************/
 #if defined(BSP_USING_UART1)
    #define USART1_RX_PORT                  (GPIO_PORT_H)
    #define USART1_RX_PIN                   (GPIO_PIN_13)
+    #define USART1_RX_FUNC                  (GPIO_FUNC_33)

    #define USART1_TX_PORT                  (GPIO_PORT_H)
    #define USART1_TX_PIN                   (GPIO_PIN_15)
+    #define USART1_TX_FUNC                  (GPIO_FUNC_32)
 #endif

 #if defined(BSP_USING_UART6)
    #define USART6_RX_PORT                  (GPIO_PORT_H)
    #define USART6_RX_PIN                   (GPIO_PIN_06)
+    #define USART6_RX_FUNC                  (GPIO_FUNC_37)

    #define USART6_TX_PORT                  (GPIO_PORT_E)
    #define USART6_TX_PIN                   (GPIO_PIN_06)
+    #define USART6_TX_FUNC                  (GPIO_FUNC_36)
+#endif
+
+/************************ I2C port **********************/
+#if defined(BSP_USING_I2C1)
+    #define I2C1_SDA_PORT                   (GPIO_PORT_F)
+    #define I2C1_SDA_PIN                    (GPIO_PIN_10)
+    #define I2C1_SDA_FUNC                   (GPIO_FUNC_48)
+
+    #define I2C1_SCL_PORT                   (GPIO_PORT_D)
+    #define I2C1_SCL_PIN                    (GPIO_PIN_03)
+    #define I2C1_SCL_FUNC                   (GPIO_FUNC_49)
 #endif

 /***********  ADC configure *********/
 #if defined(BSP_USING_ADC1)
-    #define ADC1_CH_PORT                     (GPIO_PORT_C)
-    #define ADC1_CH_PIN                      (GPIO_PIN_00)
+    #define ADC1_CH_PORT                    (GPIO_PORT_C)
+    #define ADC1_CH_PIN                     (GPIO_PIN_00)
 #endif

 #if defined(BSP_USING_ADC2)
-    #define ADC2_CH_PORT                     (GPIO_PORT_C)
-    #define ADC2_CH_PIN                      (GPIO_PIN_01)
+    #define ADC2_CH_PORT                    (GPIO_PORT_C)
+    #define ADC2_CH_PIN                     (GPIO_PIN_01)
 #endif

 #if defined(BSP_USING_ADC3)
-    #define ADC3_CH_PORT                     (GPIO_PORT_C)
-    #define ADC3_CH_PIN                      (GPIO_PIN_02)
+    #define ADC3_CH_PORT                    (GPIO_PORT_C)
+    #define ADC3_CH_PIN                     (GPIO_PIN_02)
+#endif
+
+/***********  DAC configure *********/
+#if defined(BSP_USING_DAC1)
+    #define DAC1_CH1_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH1_PIN                    (GPIO_PIN_04)
+    #define DAC1_CH2_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH2_PIN                    (GPIO_PIN_05)
+#endif
+
+#if defined(BSP_USING_DAC2)
+    #define DAC2_CH1_PORT                   (GPIO_PORT_C)
+    #define DAC2_CH1_PIN                    (GPIO_PIN_04)
+    #define DAC2_CH2_PORT                   (GPIO_PORT_C)
+    #define DAC2_CH2_PIN                    (GPIO_PIN_05)
 #endif

 /***********  CAN configure *********/
 #if defined(BSP_USING_CAN1)
-    #define CAN1_TX_PORT                     (GPIO_PORT_D)
-    #define CAN1_TX_PIN                      (GPIO_PIN_05)
-    #define CAN1_TX_PIN_FUNC                 (GPIO_FUNC_60)
+    #define CAN1_TX_PORT                    (GPIO_PORT_D)
+    #define CAN1_TX_PIN                     (GPIO_PIN_05)
+    #define CAN1_TX_PIN_FUNC                (GPIO_FUNC_60)

-    #define CAN1_RX_PORT                     (GPIO_PORT_D)
-    #define CAN1_RX_PIN                      (GPIO_PIN_04)
-    #define CAN1_RX_PIN_FUNC                 (GPIO_FUNC_61)
+    #define CAN1_RX_PORT                    (GPIO_PORT_D)
+    #define CAN1_RX_PIN                     (GPIO_PIN_04)
+    #define CAN1_RX_PIN_FUNC                (GPIO_FUNC_61)
 #endif

 #if defined(BSP_USING_CAN2)
-    #define CAN2_TX_PORT                     (GPIO_PORT_D)
-    #define CAN2_TX_PIN                      (GPIO_PIN_07)
-    #define CAN2_TX_PIN_FUNC                 (GPIO_FUNC_62)
+    #define CAN2_TX_PORT                    (GPIO_PORT_D)
+    #define CAN2_TX_PIN                     (GPIO_PIN_07)
+    #define CAN2_TX_PIN_FUNC                (GPIO_FUNC_62)

-    #define CAN2_RX_PORT                     (GPIO_PORT_D)
-    #define CAN2_RX_PIN                      (GPIO_PIN_06)
-    #define CAN2_RX_PIN_FUNC                 (GPIO_FUNC_63)
+    #define CAN2_RX_PORT                    (GPIO_PORT_D)
+    #define CAN2_RX_PIN                     (GPIO_PIN_06)
+    #define CAN2_RX_PIN_FUNC                (GPIO_FUNC_63)
 #endif

+/************************* SPI port ***********************/
+#if defined(BSP_USING_SPI1)
+    #define SPI1_CS_PORT                (GPIO_PORT_C)
+    #define SPI1_CS_PIN                 (GPIO_PIN_07)
+
+    #define SPI1_SCK_PORT               (GPIO_PORT_C)
+    #define SPI1_SCK_PIN                (GPIO_PIN_06)
+    #define SPI1_SCK_FUNC               (GPIO_FUNC_40)
+
+    #define SPI1_MOSI_PORT              (GPIO_PORT_B)
+    #define SPI1_MOSI_PIN               (GPIO_PIN_13)
+    #define SPI1_MOSI_FUNC              (GPIO_FUNC_41)
+
+    #define SPI1_MISO_PORT              (GPIO_PORT_B)
+    #define SPI1_MISO_PIN               (GPIO_PIN_12)
+    #define SPI1_MISO_FUNC              (GPIO_FUNC_42)
+
+    #define SPI1_WP_PORT                (GPIO_PORT_B)
+    #define SPI1_WP_PIN                 (GPIO_PIN_10)
+
+    #define SPI1_HOLD_PORT              (GPIO_PORT_B)
+    #define SPI1_HOLD_PIN               (GPIO_PIN_02)
 #endif
+
+/************************* ETH port ***********************/
+
+#if defined(BSP_USING_ETH)
+    #if defined(ETH_INTERFACE_USING_RMII)
+        #define ETH_SMI_MDIO_PORT       (GPIO_PORT_A)
+        #define ETH_SMI_MDIO_PIN        (GPIO_PIN_02)
+        #define ETH_SMI_MDIO_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_SMI_MDC_PORT        (GPIO_PORT_C)
+        #define ETH_SMI_MDC_PIN         (GPIO_PIN_01)
+        #define ETH_SMI_MDC_FUNC        (GPIO_FUNC_11)
+
+        #define ETH_RMII_TX_EN_PORT     (GPIO_PORT_G)
+        #define ETH_RMII_TX_EN_PIN      (GPIO_PIN_11)
+        #define ETH_RMII_TX_EN_FUNC     (GPIO_FUNC_11)
+
+        #define ETH_RMII_TXD0_PORT      (GPIO_PORT_G)
+        #define ETH_RMII_TXD0_PIN       (GPIO_PIN_13)
+        #define ETH_RMII_TXD0_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_RMII_TXD1_PORT      (GPIO_PORT_G)
+        #define ETH_RMII_TXD1_PIN       (GPIO_PIN_14)
+        #define ETH_RMII_TXD1_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_RMII_REF_CLK_PORT   (GPIO_PORT_A)
+        #define ETH_RMII_REF_CLK_PIN    (GPIO_PIN_01)
+        #define ETH_RMII_REF_CLK_FUNC   (GPIO_FUNC_11)
+
+        #define ETH_RMII_CRS_DV_PORT    (GPIO_PORT_A)
+        #define ETH_RMII_CRS_DV_PIN     (GPIO_PIN_07)
+        #define ETH_RMII_CRS_DV_FUNC    (GPIO_FUNC_11)
+
+        #define ETH_RMII_RXD0_PORT      (GPIO_PORT_C)
+        #define ETH_RMII_RXD0_PIN       (GPIO_PIN_04)
+        #define ETH_RMII_RXD0_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_RMII_RXD1_PORT      (GPIO_PORT_C)
+        #define ETH_RMII_RXD1_PIN       (GPIO_PIN_05)
+        #define ETH_RMII_RXD1_FUNC      (GPIO_FUNC_11)
+    #else
+        #define ETH_SMI_MDIO_PORT       (GPIO_PORT_A)
+        #define ETH_SMI_MDIO_PIN        (GPIO_PIN_02)
+        #define ETH_SMI_MDIO_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_SMI_MDC_PORT        (GPIO_PORT_C)
+        #define ETH_SMI_MDC_PIN         (GPIO_PIN_01)
+        #define ETH_SMI_MDC_FUNC        (GPIO_FUNC_11)
+
+        #define ETH_MII_TX_CLK_PORT     (GPIO_PORT_B)
+        #define ETH_MII_TX_CLK_PIN      (GPIO_PIN_06)
+        #define ETH_MII_TX_CLK_FUNC     (GPIO_FUNC_11)
+
+        #define ETH_MII_TX_EN_PORT      (GPIO_PORT_G)
+        #define ETH_MII_TX_EN_PIN       (GPIO_PIN_11)
+        #define ETH_MII_TX_EN_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_MII_TXD0_PORT       (GPIO_PORT_G)
+        #define ETH_MII_TXD0_PIN        (GPIO_PIN_13)
+        #define ETH_MII_TXD0_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_TXD1_PORT       (GPIO_PORT_G)
+        #define ETH_MII_TXD1_PIN        (GPIO_PIN_14)
+        #define ETH_MII_TXD1_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_TXD2_PORT       (GPIO_PORT_B)
+        #define ETH_MII_TXD2_PIN        (GPIO_PIN_09)
+        #define ETH_MII_TXD2_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_TXD3_PORT       (GPIO_PORT_B)
+        #define ETH_MII_TXD3_PIN        (GPIO_PIN_08)
+        #define ETH_MII_TXD3_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_RX_CLK_PORT     (GPIO_PORT_A)
+        #define ETH_MII_RX_CLK_PIN      (GPIO_PIN_01)
+        #define ETH_MII_RX_CLK_FUNC     (GPIO_FUNC_11)
+
+        #define ETH_MII_RX_DV_PORT      (GPIO_PORT_A)
+        #define ETH_MII_RX_DV_PIN       (GPIO_PIN_07)
+        #define ETH_MII_RX_DV_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_MII_RXD0_PORT       (GPIO_PORT_C)
+        #define ETH_MII_RXD0_PIN        (GPIO_PIN_04)
+        #define ETH_MII_RXD0_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_RXD1_PORT       (GPIO_PORT_C)
+        #define ETH_MII_RXD1_PIN        (GPIO_PIN_05)
+        #define ETH_MII_RXD1_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_RXD2_PORT       (GPIO_PORT_B)
+        #define ETH_MII_RXD2_PIN        (GPIO_PIN_00)
+        #define ETH_MII_RXD2_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_RXD3_PORT       (GPIO_PORT_B)
+        #define ETH_MII_RXD3_PIN        (GPIO_PIN_01)
+        #define ETH_MII_RXD3_FUNC       (GPIO_FUNC_11)
+
+        #define ETH_MII_RX_ER_PORT      (GPIO_PORT_I)
+        #define ETH_MII_RX_ER_PIN       (GPIO_PIN_10)
+        #define ETH_MII_RX_ER_FUNC      (GPIO_FUNC_11)
+
+        #define ETH_MII_CRS_PORT        (GPIO_PORT_H)
+        #define ETH_MII_CRS_PIN         (GPIO_PIN_02)
+        #define ETH_MII_CRS_FUNC        (GPIO_FUNC_11)
+
+        #define ETH_MII_COL_PORT        (GPIO_PORT_H)
+        #define ETH_MII_COL_PIN         (GPIO_PIN_03)
+        #define ETH_MII_COL_FUNC        (GPIO_FUNC_11)
+    #endif
+#endif
+
+/************************ NAND port **********************/
+#if defined(BSP_USING_NAND)
+    #define NAND_CE_PORT                    (GPIO_PORT_C)   /* PC02 - EXMC_CE0 */
+    #define NAND_CE_PIN                     (GPIO_PIN_02)
+    #define NAND_CE_FUNC                    (GPIO_FUNC_12)
+
+    #define NAND_RE_PORT                    (GPIO_PORT_F)   /* PF11 - EXMC_OE */
+    #define NAND_RE_PIN                     (GPIO_PIN_11)
+    #define NAND_RE_FUNC                    (GPIO_FUNC_12)
+
+    #define NAND_WE_PORT                    (GPIO_PORT_C)   /* PC00 - EXMC_WE */
+    #define NAND_WE_PIN                     (GPIO_PIN_00)
+    #define NAND_WE_FUNC                    (GPIO_FUNC_12)
+
+    #define NAND_CLE_PORT                   (GPIO_PORT_I)   /* PI12 - EXMC_CLE */
+    #define NAND_CLE_PIN                    (GPIO_PIN_12)
+    #define NAND_CLE_FUNC                   (GPIO_FUNC_12)
+
+    #define NAND_ALE_PORT                   (GPIO_PORT_C)   /* PC03 - EXMC_ALE */
+    #define NAND_ALE_PIN                    (GPIO_PIN_03)
+    #define NAND_ALE_FUNC                   (GPIO_FUNC_12)
+
+    #define NAND_WP_PORT                    (GPIO_PORT_G)   /* PG15 - EXMC_BAA */
+    #define NAND_WP_PIN                     (GPIO_PIN_15)
+    #define NAND_WP_FUNC                    (GPIO_FUNC_12)
+
+    #define NAND_RB_PORT                    (GPIO_PORT_G)   /* PG06 - EXMC_RB0 */
+    #define NAND_RB_PIN                     (GPIO_PIN_06)
+    #define NAND_RB_FUNC                    (GPIO_FUNC_12)
+
+    #define NAND_DATA0_PORT                 (GPIO_PORT_D)   /* PD14 - EXMC_DATA0 */
+    #define NAND_DATA0_PIN                  (GPIO_PIN_14)
+    #define NAND_DATA0_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA1_PORT                 (GPIO_PORT_D)   /* PD15 - EXMC_DATA1 */
+    #define NAND_DATA1_PIN                  (GPIO_PIN_15)
+    #define NAND_DATA1_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA2_PORT                 (GPIO_PORT_D)   /* PD0 - EXMC_DATA2 */
+    #define NAND_DATA2_PIN                  (GPIO_PIN_00)
+    #define NAND_DATA2_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA3_PORT                 (GPIO_PORT_D)   /* PD1 - EXMC_DATA3 */
+    #define NAND_DATA3_PIN                  (GPIO_PIN_01)
+    #define NAND_DATA3_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA4_PORT                 (GPIO_PORT_E)   /* PE7 - EXMC_DATA4 */
+    #define NAND_DATA4_PIN                  (GPIO_PIN_07)
+    #define NAND_DATA4_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA5_PORT                 (GPIO_PORT_E)   /* PE8 - EXMC_DATA5 */
+    #define NAND_DATA5_PIN                  (GPIO_PIN_08)
+    #define NAND_DATA5_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA6_PORT                 (GPIO_PORT_E)   /* PE9 - EXMC_DATA6 */
+    #define NAND_DATA6_PIN                  (GPIO_PIN_09)
+    #define NAND_DATA6_FUNC                 (GPIO_FUNC_12)
+    #define NAND_DATA7_PORT                 (GPIO_PORT_E)   /* PE10 - EXMC_DATA7 */
+    #define NAND_DATA7_PIN                  (GPIO_PIN_10)
+    #define NAND_DATA7_FUNC                 (GPIO_FUNC_12)
+#endif
+
+/************************ SDIOC port **********************/
+#if defined(BSP_USING_SDIO1)
+    #define SDIOC1_CK_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_CK_PIN                   (GPIO_PIN_12)
+    #define SDIOC1_CK_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_CMD_PORT                 (GPIO_PORT_D)
+    #define SDIOC1_CMD_PIN                  (GPIO_PIN_02)
+    #define SDIOC1_CMD_FUNC                 (GPIO_FUNC_9)
+
+    #define SDIOC1_D0_PORT                  (GPIO_PORT_B)
+    #define SDIOC1_D0_PIN                   (GPIO_PIN_07)
+    #define SDIOC1_D0_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D1_PORT                  (GPIO_PORT_A)
+    #define SDIOC1_D1_PIN                   (GPIO_PIN_08)
+    #define SDIOC1_D1_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D2_PORT                  (GPIO_PORT_C)
+    #define SDIOC1_D2_PIN                   (GPIO_PIN_10)
+    #define SDIOC1_D2_FUNC                  (GPIO_FUNC_9)
+
+    #define SDIOC1_D3_PORT                  (GPIO_PORT_B)
+    #define SDIOC1_D3_PIN                   (GPIO_PIN_05)
+    #define SDIOC1_D3_FUNC                  (GPIO_FUNC_9)
+#endif
+
+/************************ SDRAM port **********************/
+#if defined(BSP_USING_SDRAM)
+    #define SDRAM_CKE_PORT                  (GPIO_PORT_C)   /* PC03 - EXMC_ALE */
+    #define SDRAM_CKE_PIN                   (GPIO_PIN_03)
+    #define SDRAM_CKE_FUNC                  (GPIO_FUNC_12)
+
+    #define SDRAM_CLK_PORT                  (GPIO_PORT_G)   /* PD03 - EXMC_CLK */
+    #define SDRAM_CLK_PIN                   (GPIO_PIN_08)
+    #define SDRAM_CLK_FUNC                  (GPIO_FUNC_12)
+
+    #define SDRAM_DQM0_PORT                 (GPIO_PORT_E)   /* PE00 - EXMC_CE4 */
+    #define SDRAM_DQM0_PIN                  (GPIO_PIN_00)
+    #define SDRAM_DQM0_FUNC                 (GPIO_FUNC_12)
+    #define SDRAM_DQM1_PORT                 (GPIO_PORT_E)   /* PE01 - EXMC_CE5 */
+    #define SDRAM_DQM1_PIN                  (GPIO_PIN_01)
+    #define SDRAM_DQM1_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_BA0_PORT                  (GPIO_PORT_D)   /* PD11 - EXMC_ADD16 */
+    #define SDRAM_BA0_PIN                   (GPIO_PIN_11)
+    #define SDRAM_BA0_FUNC                  (GPIO_FUNC_12)
+    #define SDRAM_BA1_PORT                  (GPIO_PORT_D)   /* PD12 - EXMC_ADD17 */
+    #define SDRAM_BA1_PIN                   (GPIO_PIN_12)
+    #define SDRAM_BA1_FUNC                  (GPIO_FUNC_12)
+
+    #define SDRAM_CS_PORT                   (GPIO_PORT_G)   /* PG09 - EXMC_CE1 */
+    #define SDRAM_CS_PIN                    (GPIO_PIN_09)
+    #define SDRAM_CS_FUNC                   (GPIO_FUNC_12)
+
+    #define SDRAM_RAS_PORT                  (GPIO_PORT_F)   /* PF11 - EXMC_OE */
+    #define SDRAM_RAS_PIN                   (GPIO_PIN_11)
+    #define SDRAM_RAS_FUNC                  (GPIO_FUNC_12)
+
+    #define SDRAM_CAS_PORT                  (GPIO_PORT_G)   /* PG15 - EXMC_BAA */
+    #define SDRAM_CAS_PIN                   (GPIO_PIN_15)
+    #define SDRAM_CAS_FUNC                  (GPIO_FUNC_12)
+
+    #define SDRAM_WE_PORT                   (GPIO_PORT_C)   /* PC00 - EXMC_WE */
+    #define SDRAM_WE_PIN                    (GPIO_PIN_00)
+    #define SDRAM_WE_FUNC                   (GPIO_FUNC_12)
+
+    #define SDRAM_ADD0_PORT                 (GPIO_PORT_F)   /* PF00 - EXMC_ADD0 */
+    #define SDRAM_ADD0_PIN                  (GPIO_PIN_00)
+    #define SDRAM_ADD0_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD1_PORT                 (GPIO_PORT_F)   /* PF01 - EXMC_ADD1 */
+    #define SDRAM_ADD1_PIN                  (GPIO_PIN_01)
+    #define SDRAM_ADD1_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD2_PORT                 (GPIO_PORT_F)   /* PF02 - EXMC_ADD2 */
+    #define SDRAM_ADD2_PIN                  (GPIO_PIN_02)
+    #define SDRAM_ADD2_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD3_PORT                 (GPIO_PORT_F)   /* PF03 - EXMC_ADD3 */
+    #define SDRAM_ADD3_PIN                  (GPIO_PIN_03)
+    #define SDRAM_ADD3_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD4_PORT                 (GPIO_PORT_F)   /* PF04 - EXMC_ADD4 */
+    #define SDRAM_ADD4_PIN                  (GPIO_PIN_04)
+    #define SDRAM_ADD4_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD5_PORT                 (GPIO_PORT_F)   /* PF05 - EXMC_ADD5 */
+    #define SDRAM_ADD5_PIN                  (GPIO_PIN_05)
+    #define SDRAM_ADD5_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD6_PORT                 (GPIO_PORT_F)   /* PF12 - EXMC_ADD6 */
+    #define SDRAM_ADD6_PIN                  (GPIO_PIN_12)
+    #define SDRAM_ADD6_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD7_PORT                 (GPIO_PORT_F)   /* PF13 - EXMC_ADD7 */
+    #define SDRAM_ADD7_PIN                  (GPIO_PIN_13)
+    #define SDRAM_ADD7_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD8_PORT                 (GPIO_PORT_F)   /* PF14 - EXMC_ADD8 */
+    #define SDRAM_ADD8_PIN                  (GPIO_PIN_14)
+    #define SDRAM_ADD8_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD9_PORT                 (GPIO_PORT_F)   /* PF15 - EXMC_ADD9 */
+    #define SDRAM_ADD9_PIN                  (GPIO_PIN_15)
+    #define SDRAM_ADD9_FUNC                 (GPIO_FUNC_12)
+
+    #define SDRAM_ADD10_PORT                (GPIO_PORT_G)   /* PG00 - EXMC_ADD10 */
+    #define SDRAM_ADD10_PIN                 (GPIO_PIN_00)
+    #define SDRAM_ADD10_FUNC                (GPIO_FUNC_12)
+
+    #define SDRAM_ADD11_PORT                (GPIO_PORT_G)   /* PG01 - EXMC_ADD11 */
+    #define SDRAM_ADD11_PIN                 (GPIO_PIN_01)
+    #define SDRAM_ADD11_FUNC                (GPIO_FUNC_12)
+
+    #define SDRAM_DATA0_PORT                (GPIO_PORT_D)   /* PD14 - EXMC_DATA0 */
+    #define SDRAM_DATA0_PIN                 (GPIO_PIN_14)
+    #define SDRAM_DATA0_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA1_PORT                (GPIO_PORT_D)   /* PD15 - EXMC_DATA1 */
+    #define SDRAM_DATA1_PIN                 (GPIO_PIN_15)
+    #define SDRAM_DATA1_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA2_PORT                (GPIO_PORT_D)   /* PD00 - EXMC_DATA2 */
+    #define SDRAM_DATA2_PIN                 (GPIO_PIN_00)
+    #define SDRAM_DATA2_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA3_PORT                (GPIO_PORT_D)   /* PD01 - EXMC_DATA3 */
+    #define SDRAM_DATA3_PIN                 (GPIO_PIN_01)
+    #define SDRAM_DATA3_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA4_PORT                (GPIO_PORT_E)   /* PE07 - EXMC_DATA4 */
+    #define SDRAM_DATA4_PIN                 (GPIO_PIN_07)
+    #define SDRAM_DATA4_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA5_PORT                (GPIO_PORT_E)   /* PE08 - EXMC_DATA5 */
+    #define SDRAM_DATA5_PIN                 (GPIO_PIN_08)
+    #define SDRAM_DATA5_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA6_PORT                (GPIO_PORT_E)   /* PE09 - EXMC_DATA6 */
+    #define SDRAM_DATA6_PIN                 (GPIO_PIN_09)
+    #define SDRAM_DATA6_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA7_PORT                (GPIO_PORT_E)   /* PE10 - EXMC_DATA7 */
+    #define SDRAM_DATA7_PIN                 (GPIO_PIN_10)
+    #define SDRAM_DATA7_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA8_PORT                (GPIO_PORT_E)   /* PE11 - EXMC_DATA8 */
+    #define SDRAM_DATA8_PIN                 (GPIO_PIN_11)
+    #define SDRAM_DATA8_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA9_PORT                (GPIO_PORT_E)   /* PE12 - EXMC_DATA9 */
+    #define SDRAM_DATA9_PIN                 (GPIO_PIN_12)
+    #define SDRAM_DATA9_FUNC                (GPIO_FUNC_12)
+    #define SDRAM_DATA10_PORT               (GPIO_PORT_E)   /* PE13 - EXMC_DATA10 */
+    #define SDRAM_DATA10_PIN                (GPIO_PIN_13)
+    #define SDRAM_DATA10_FUNC               (GPIO_FUNC_12)
+    #define SDRAM_DATA11_PORT               (GPIO_PORT_E)   /* PE14 - EXMC_DATA11 */
+    #define SDRAM_DATA11_PIN                (GPIO_PIN_14)
+    #define SDRAM_DATA11_FUNC               (GPIO_FUNC_12)
+    #define SDRAM_DATA12_PORT               (GPIO_PORT_E)   /* PE15 - EXMC_DATA12 */
+    #define SDRAM_DATA12_PIN                (GPIO_PIN_15)
+    #define SDRAM_DATA12_FUNC               (GPIO_FUNC_12)
+    #define SDRAM_DATA13_PORT               (GPIO_PORT_D)   /* PD08 - EXMC_DATA13 */
+    #define SDRAM_DATA13_PIN                (GPIO_PIN_08)
+    #define SDRAM_DATA13_FUNC               (GPIO_FUNC_12)
+    #define SDRAM_DATA14_PORT               (GPIO_PORT_D)   /* PD09 - EXMC_DATA14 */
+    #define SDRAM_DATA14_PIN                (GPIO_PIN_09)
+    #define SDRAM_DATA14_FUNC               (GPIO_FUNC_12)
+    #define SDRAM_DATA15_PORT               (GPIO_PORT_D)   /* PD10 - EXMC_DATA15 */
+    #define SDRAM_DATA15_PIN                (GPIO_PIN_10)
+    #define SDRAM_DATA15_FUNC               (GPIO_FUNC_12)
+#endif
+
+/************************ RTC/PM *****************************/
+#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
+    #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+        #define XTAL32_PORT                     (GPIO_PORT_C)
+        #define XTAL32_IN_PIN                   (GPIO_PIN_15)
+        #define XTAL32_OUT_PIN                  (GPIO_PIN_14)
+    #endif
+#endif
+
+#if defined(RT_USING_PWM)
+    /***********  PWM_TMRA configure *********/
+    #if defined(BSP_USING_PWM_TMRA_1)
+        #if defined(BSP_USING_PWM_TMRA_1_CH1)
+            #define PWM_TMRA_1_CH1_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH1_PIN              (GPIO_PIN_08)
+            #define PWM_TMRA_1_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH2)
+            #define PWM_TMRA_1_CH2_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH2_PIN              (GPIO_PIN_09)
+            #define PWM_TMRA_1_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH3)
+            #define PWM_TMRA_1_CH3_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH3_PIN              (GPIO_PIN_10)
+            #define PWM_TMRA_1_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH4)
+            #define PWM_TMRA_1_CH4_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH4_PIN              (GPIO_PIN_11)
+            #define PWM_TMRA_1_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    /***********  PWM_TMR4 configure *********/
+    #if defined(BSP_USING_PWM_TMR4_1)
+        #if defined(BSP_USING_PWM_TMR4_1_OUH)
+            #define PWM_TMR4_1_OUH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OUH_PIN              (GPIO_PIN_09)
+            #define PWM_TMR4_1_OUH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OUL)
+            #define PWM_TMR4_1_OUL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OUL_PIN              (GPIO_PIN_08)
+            #define PWM_TMR4_1_OUL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVH)
+            #define PWM_TMR4_1_OVH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OVH_PIN              (GPIO_PIN_11)
+            #define PWM_TMR4_1_OVH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVL)
+            #define PWM_TMR4_1_OVL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OVL_PIN              (GPIO_PIN_10)
+            #define PWM_TMR4_1_OVL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWH)
+            #define PWM_TMR4_1_OWH_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OWH_PIN              (GPIO_PIN_13)
+            #define PWM_TMR4_1_OWH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWL)
+            #define PWM_TMR4_1_OWL_PORT             (GPIO_PORT_E)
+            #define PWM_TMR4_1_OWL_PIN              (GPIO_PIN_12)
+            #define PWM_TMR4_1_OWL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+    #endif
+
+    /***********  PWM_TMR6 configure *********/
+    #if defined(BSP_USING_PWM_TMR6_1)
+        #if defined(BSP_USING_PWM_TMR6_1_A)
+            #define PWM_TMR6_1_A_PORT               (GPIO_PORT_F)
+            #define PWM_TMR6_1_A_PIN                (GPIO_PIN_13)
+            #define PWM_TMR6_1_A_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+        #if defined(BSP_USING_PWM_TMR6_1_B)
+            #define PWM_TMR6_1_B_PORT               (GPIO_PORT_F)
+            #define PWM_TMR6_1_B_PIN                (GPIO_PIN_14)
+            #define PWM_TMR6_1_B_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+    #endif
+
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    #if defined(BSP_USING_USBFS)
+        /* USBFS Core*/
+        #define USBF_DP_PORT                    (GPIO_PORT_A)
+        #define USBF_DP_PIN                     (GPIO_PIN_12)
+        #define USBF_DP_FUNC                    (GPIO_FUNC_10)
+        #define USBF_DM_PORT                    (GPIO_PORT_A)
+        #define USBF_DM_PIN                     (GPIO_PIN_11)
+        #define USBF_DM_FUNC                    (GPIO_FUNC_10)
+        #define USBF_VBUS_PORT                  (GPIO_PORT_A)
+        #define USBF_VBUS_PIN                   (GPIO_PIN_09)
+        #define USBF_VBUS_FUNC                  (GPIO_FUNC_10)
+        #define USBF_DRVVBUS_PORT               (GPIO_PORT_C)
+        #define USBF_DRVVBUS_PIN                (GPIO_PIN_09)
+        #define USBF_DRVVBUS_FUNC               (GPIO_FUNC_10)
+    #elif defined(BSP_USING_USBHS)
+        /* USBHS Core*/
+        #if defined(BSP_USING_USBHS_PHY_EMBED)
+            #define USBH_DP_PORT                    (GPIO_PORT_B)
+            #define USBH_DP_PIN                     (GPIO_PIN_15)
+            #define USBH_DP_FUNC                    (GPIO_FUNC_10)
+            #define USBH_DM_PORT                    (GPIO_PORT_B)
+            #define USBH_DM_PIN                     (GPIO_PIN_14)
+            #define USBH_DM_FUNC                    (GPIO_FUNC_10)
+            #define USBH_VBUS_PORT                  (GPIO_PORT_B)
+            #define USBH_VBUS_PIN                   (GPIO_PIN_13)
+            #define USBH_VBUS_FUNC                  (GPIO_FUNC_12)
+            #define USBH_DRVVBUS_PORT               (GPIO_PORT_B)
+            #define USBH_DRVVBUS_PIN                (GPIO_PIN_11)
+            #define USBH_DRVVBUS_FUNC               (GPIO_FUNC_10)
+        #else
+            /* USBHS Core, external PHY */
+            #define USBH_ULPI_CLK_PORT              (GPIO_PORT_E)
+            #define USBH_ULPI_CLK_PIN               (GPIO_PIN_12)
+            #define USBH_ULPI_CLK_FUNC              (GPIO_FUNC_10)
+            #define USBH_ULPI_DIR_PORT              (GPIO_PORT_C)
+            #define USBH_ULPI_DIR_PIN               (GPIO_PIN_02)
+            #define USBH_ULPI_DIR_FUNC              (GPIO_FUNC_10)
+            #define USBH_ULPI_NXT_PORT              (GPIO_PORT_C)
+            #define USBH_ULPI_NXT_PIN               (GPIO_PIN_03)
+            #define USBH_ULPI_NXT_FUNC              (GPIO_FUNC_10)
+            #define USBH_ULPI_STP_PORT              (GPIO_PORT_C)
+            #define USBH_ULPI_STP_PIN               (GPIO_PIN_00)
+            #define USBH_ULPI_STP_FUNC              (GPIO_FUNC_10)
+            #define USBH_ULPI_D0_PORT               (GPIO_PORT_E)
+            #define USBH_ULPI_D0_PIN                (GPIO_PIN_13)
+            #define USBH_ULPI_D0_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D1_PORT               (GPIO_PORT_E)
+            #define USBH_ULPI_D1_PIN                (GPIO_PIN_14)
+            #define USBH_ULPI_D1_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D2_PORT               (GPIO_PORT_E)
+            #define USBH_ULPI_D2_PIN                (GPIO_PIN_15)
+            #define USBH_ULPI_D2_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D3_PORT               (GPIO_PORT_B)
+            #define USBH_ULPI_D3_PIN                (GPIO_PIN_10)
+            #define USBH_ULPI_D3_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D4_PORT               (GPIO_PORT_B)
+            #define USBH_ULPI_D4_PIN                (GPIO_PIN_11)
+            #define USBH_ULPI_D4_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D5_PORT               (GPIO_PORT_B)
+            #define USBH_ULPI_D5_PIN                (GPIO_PIN_12)
+            #define USBH_ULPI_D5_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D6_PORT               (GPIO_PORT_B)
+            #define USBH_ULPI_D6_PIN                (GPIO_PIN_13)
+            #define USBH_ULPI_D6_FUNC               (GPIO_FUNC_10)
+            #define USBH_ULPI_D7_PORT               (GPIO_PORT_E)
+            #define USBH_ULPI_D7_PIN                (GPIO_PIN_11)
+            #define USBH_ULPI_D7_FUNC               (GPIO_FUNC_10)
+            /* 3300 reset */
+            #define USB_3300_RESET_PORT             (EIO_PORT1)
+            #define USB_3300_RESET_PIN              (EIO_USB3300_RST)
+        #endif
+    #endif
+#endif
+
+#if defined(BSP_USING_QSPI)
+    #ifndef BSP_QSPI_USING_SOFT_CS
+        /* QSSN */
+        #define QSPI_FLASH_CS_PORT              (GPIO_PORT_C)
+        #define QSPI_FLASH_CS_PIN               (GPIO_PIN_07)
+        #define QSPI_FLASH_CS_FUNC              (GPIO_FUNC_18)
+    #endif
+    /* QSCK */
+    #define QSPI_FLASH_SCK_PORT             (GPIO_PORT_C)
+    #define QSPI_FLASH_SCK_PIN              (GPIO_PIN_06)
+    #define QSPI_FLASH_SCK_FUNC             (GPIO_FUNC_18)
+    /* QSIO0 */
+    #define QSPI_FLASH_IO0_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO0_PIN              (GPIO_PIN_13)
+    #define QSPI_FLASH_IO0_FUNC             (GPIO_FUNC_18)
+    /* QSIO1 */
+    #define QSPI_FLASH_IO1_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO1_PIN              (GPIO_PIN_12)
+    #define QSPI_FLASH_IO1_FUNC             (GPIO_FUNC_18)
+    /* QSIO2 */
+    #define QSPI_FLASH_IO2_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO2_PIN              (GPIO_PIN_10)
+    #define QSPI_FLASH_IO2_FUNC             (GPIO_FUNC_18)
+    /* QSIO3 */
+    #define QSPI_FLASH_IO3_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO3_PIN              (GPIO_PIN_02)
+    #define QSPI_FLASH_IO3_FUNC             (GPIO_FUNC_18)
+#endif
+
+/*********** TMRA_PULSE_ENCODER configure *********/
+#if defined(RT_USING_PULSE_ENCODER)
+    #if defined(BSP_USING_TMRA_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+            #define PULSE_ENCODER_TMRA_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC  (GPIO_FUNC_4)
+            #define PULSE_ENCODER_TMRA_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_B_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC  (GPIO_FUNC_4)
+        #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+    #endif /* BSP_USING_TMRA_PULSE_ENCODER */
+
+    #if defined(BSP_USING_TMR6_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+            #define PULSE_ENCODER_TMR6_1_A_PORT      (GPIO_PORT_B)
+            #define PULSE_ENCODER_TMR6_1_A_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC  (GPIO_FUNC_3)
+            #define PULSE_ENCODER_TMR6_1_B_PORT      (GPIO_PORT_B)
+            #define PULSE_ENCODER_TMR6_1_B_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC  (GPIO_FUNC_3)
+        #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+    #endif /* BSP_USING_TMR6_PULSE_ENCODER */
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -24,6 +23,7 @@ extern "C" {
 #define ADC1_INIT_PARAMS                                                        \
    {                                                                           \
       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
       .resolution                      = ADC_RESOLUTION_12BIT,                 \
       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
       .eoc_poll_time_max               = 100,                                  \
@ -46,6 +46,7 @@ extern "C" {
 #define ADC2_INIT_PARAMS                                                        \
    {                                                                           \
       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
       .resolution                      = ADC_RESOLUTION_12BIT,                 \
       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
       .eoc_poll_time_max               = 100,                                  \
@ -68,6 +69,7 @@ extern "C" {
 #define ADC3_INIT_PARAMS                                                        \
    {                                                                           \
       .name                            = "adc3",                               \
+       .vref                            = 3300,                                 \
       .resolution                      = ADC_RESOLUTION_12BIT,                 \
       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
       .eoc_poll_time_max               = 100,                                  \
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -20,19 +19,31 @@ extern "C" {
 #endif

 #ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME                       ("can1")
 #ifndef CAN1_INIT_PARAMS
 #define CAN1_INIT_PARAMS                                    \
    {                                                       \
-       .name = "can1",                                      \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
    }
 #endif /* CAN1_INIT_PARAMS */
 #endif /* BSP_USING_CAN1 */

 #ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN2_NAME                       ("can2")
 #ifndef CAN2_INIT_PARAMS
 #define CAN2_INIT_PARAMS                                    \
    {                                                       \
-       .name = "can2",                                      \
+       .name = CAN2_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
    }
 #endif /* CAN2_INIT_PARAMS */
 #endif /* BSP_USING_CAN2 */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h
@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac1",                                 \
+    }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac2",                                 \
+    }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -25,9 +24,28 @@ extern "C" {
 #define SPI1_RX_DMA_CHANNEL             DMA_CH0
 #define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
 #define SPI1_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
 #define SPI1_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
 #define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE)
+#define SDIO1_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_RX_DMA_CHANNEL            DMA_CH0
+#define SDIO1_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_RX_DMA_TRIG_SELECT        AOS_DMA1_0
+#define SDIO1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define SDIO1_RX_DMA_IRQn               BSP_DMA1_CH0_IRQ_NUM
+#define SDIO1_RX_DMA_INT_PRIO           BSP_DMA1_CH0_IRQ_PRIO
+#define SDIO1_RX_DMA_INT_SRC            INT_SRC_DMA1_TC0
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE            CM_DMA1
+#define I2C1_TX_DMA_CHANNEL             DMA_CH0
+#define I2C1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC0
 #endif

 /* DMA1 ch1 */
@ -36,9 +54,28 @@ extern "C" {
 #define SPI1_TX_DMA_CHANNEL             DMA_CH1
 #define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
 #define SPI1_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
 #define SPI1_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
 #define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE)
+#define SDIO1_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_TX_DMA_CHANNEL            DMA_CH1
+#define SDIO1_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_TX_DMA_TRIG_SELECT        AOS_DMA1_1
+#define SDIO1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define SDIO1_TX_DMA_IRQn               BSP_DMA1_CH1_IRQ_NUM
+#define SDIO1_TX_DMA_INT_PRIO           BSP_DMA1_CH1_IRQ_PRIO
+#define SDIO1_TX_DMA_INT_SRC            INT_SRC_DMA1_TC1
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE            CM_DMA1
+#define I2C1_RX_DMA_CHANNEL             DMA_CH1
+#define I2C1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC1
 #endif

 /* DMA1 ch2 */
@ -47,9 +84,28 @@ extern "C" {
 #define SPI2_RX_DMA_CHANNEL             DMA_CH2
 #define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
 #define SPI2_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
 #define SPI2_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
 #define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE)
+#define SDIO2_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_RX_DMA_CHANNEL            DMA_CH2
+#define SDIO2_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_RX_DMA_TRIG_SELECT        AOS_DMA1_2
+#define SDIO2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define SDIO2_RX_DMA_IRQn               BSP_DMA1_CH2_IRQ_NUM
+#define SDIO2_RX_DMA_INT_PRIO           BSP_DMA1_CH2_IRQ_PRIO
+#define SDIO2_RX_DMA_INT_SRC            INT_SRC_DMA1_TC2
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE            CM_DMA1
+#define I2C2_TX_DMA_CHANNEL             DMA_CH2
+#define I2C2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC2
 #endif

 /* DMA1 ch3 */
@ -58,9 +114,37 @@ extern "C" {
 #define SPI2_TX_DMA_CHANNEL             DMA_CH3
 #define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
 #define SPI2_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
 #define SPI2_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
 #define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE)
+#define SDIO2_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_TX_DMA_CHANNEL            DMA_CH3
+#define SDIO2_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_TX_DMA_TRIG_SELECT        AOS_DMA1_3
+#define SDIO2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define SDIO2_TX_DMA_IRQn               BSP_DMA1_CH3_IRQ_NUM
+#define SDIO2_TX_DMA_INT_PRIO           BSP_DMA1_CH3_IRQ_PRIO
+#define SDIO2_TX_DMA_INT_SRC            INT_SRC_DMA1_TC3
+#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_INSTANCE               CM_DMA1
+#define QSPI_DMA_CHANNEL                DMA_CH3
+#define QSPI_DMA_CLOCK                  (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define QSPI_DMA_TRIG_SELECT            AOS_DMA1_3
+#define QSPI_DMA_TRANS_FLAG             DMA_FLAG_TC_CH3
+#define QSPI_DMA_IRQn                   BSP_DMA1_CH3_IRQ_NUM
+#define QSPI_DMA_INT_PRIO               BSP_DMA1_CH3_IRQ_PRIO
+#define QSPI_DMA_INT_SRC                INT_SRC_DMA1_TC3
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE            CM_DMA1
+#define I2C2_RX_DMA_CHANNEL             DMA_CH3
+#define I2C2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC3
 #endif

 /* DMA1 ch4 */
@ -69,9 +153,19 @@ extern "C" {
 #define SPI3_RX_DMA_CHANNEL             DMA_CH4
 #define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_4
+#define SPI3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH4
 #define SPI3_RX_DMA_IRQn                BSP_DMA1_CH4_IRQ_NUM
 #define SPI3_RX_DMA_INT_PRIO            BSP_DMA1_CH4_IRQ_PRIO
 #define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC4
+#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
+#define I2C3_TX_DMA_INSTANCE            CM_DMA1
+#define I2C3_TX_DMA_CHANNEL             DMA_CH4
+#define I2C3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C3_TX_DMA_TRIG_SELECT         AOS_DMA1_4
+#define I2C3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH4
+#define I2C3_TX_DMA_IRQn                BSP_DMA1_CH4_IRQ_NUM
+#define I2C3_TX_DMA_INT_PRIO            BSP_DMA1_CH4_IRQ_PRIO
+#define I2C3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC4
 #endif

 /* DMA1 ch5 */
@ -80,9 +174,19 @@ extern "C" {
 #define SPI3_TX_DMA_CHANNEL             DMA_CH5
 #define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_5
+#define SPI3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH5
 #define SPI3_TX_DMA_IRQn                BSP_DMA1_CH5_IRQ_NUM
 #define SPI3_TX_DMA_INT_PRIO            BSP_DMA1_CH5_IRQ_PRIO
 #define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC5
+#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
+#define I2C3_RX_DMA_INSTANCE            CM_DMA1
+#define I2C3_RX_DMA_CHANNEL             DMA_CH5
+#define I2C3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C3_RX_DMA_TRIG_SELECT         AOS_DMA1_5
+#define I2C3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH5
+#define I2C3_RX_DMA_IRQn                BSP_DMA1_CH5_IRQ_NUM
+#define I2C3_RX_DMA_INT_PRIO            BSP_DMA1_CH5_IRQ_PRIO
+#define I2C3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC5
 #endif

 /* DMA1 ch6 */
@ -91,9 +195,19 @@ extern "C" {
 #define SPI4_RX_DMA_CHANNEL             DMA_CH6
 #define SPI4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI4_RX_DMA_TRIG_SELECT         AOS_DMA1_6
+#define SPI4_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH6
 #define SPI4_RX_DMA_IRQn                BSP_DMA1_CH6_IRQ_NUM
 #define SPI4_RX_DMA_INT_PRIO            BSP_DMA1_CH6_IRQ_PRIO
 #define SPI4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC6
+#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE)
+#define I2C4_TX_DMA_INSTANCE            CM_DMA1
+#define I2C4_TX_DMA_CHANNEL             DMA_CH6
+#define I2C4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C4_TX_DMA_TRIG_SELECT         AOS_DMA1_6
+#define I2C4_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH6
+#define I2C4_TX_DMA_IRQn                BSP_DMA1_CH6_IRQ_NUM
+#define I2C4_TX_DMA_INT_PRIO            BSP_DMA1_CH6_IRQ_PRIO
+#define I2C4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC6
 #endif

 /* DMA1 ch7 */
@ -102,9 +216,19 @@ extern "C" {
 #define SPI4_TX_DMA_CHANNEL             DMA_CH7
 #define SPI4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
 #define SPI4_TX_DMA_TRIG_SELECT         AOS_DMA1_7
+#define SPI4_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH7
 #define SPI4_TX_DMA_IRQn                BSP_DMA1_CH7_IRQ_NUM
 #define SPI4_TX_DMA_INT_PRIO            BSP_DMA1_CH7_IRQ_PRIO
 #define SPI4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC7
+#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE)
+#define I2C4_RX_DMA_INSTANCE            CM_DMA1
+#define I2C4_RX_DMA_CHANNEL             DMA_CH7
+#define I2C4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C4_RX_DMA_TRIG_SELECT         AOS_DMA1_7
+#define I2C4_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH7
+#define I2C4_RX_DMA_IRQn                BSP_DMA1_CH7_IRQ_NUM
+#define I2C4_RX_DMA_INT_PRIO            BSP_DMA1_CH7_IRQ_PRIO
+#define I2C4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC7
 #endif

 /* DMA2 ch0 */
@ -113,9 +237,19 @@ extern "C" {
 #define UART1_RX_DMA_CHANNEL            DMA_CH0
 #define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
 #define UART1_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
 #define UART1_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
 #define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE)
+#define I2C5_TX_DMA_INSTANCE            CM_DMA2
+#define I2C5_TX_DMA_CHANNEL             DMA_CH0
+#define I2C5_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C5_TX_DMA_TRIG_SELECT         AOS_DMA2_0
+#define I2C5_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C5_TX_DMA_IRQn                BSP_DMA2_CH0_IRQ_NUM
+#define I2C5_TX_DMA_INT_PRIO            BSP_DMA2_CH0_IRQ_PRIO
+#define I2C5_TX_DMA_INT_SRC             INT_SRC_DMA2_TC0
 #endif

 /* DMA2 ch1 */
@ -124,9 +258,19 @@ extern "C" {
 #define UART1_TX_DMA_CHANNEL            DMA_CH1
 #define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
 #define UART1_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
 #define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
 #define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE)
+#define I2C5_RX_DMA_INSTANCE            CM_DMA2
+#define I2C5_RX_DMA_CHANNEL             DMA_CH1
+#define I2C5_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C5_RX_DMA_TRIG_SELECT         AOS_DMA2_1
+#define I2C5_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C5_RX_DMA_IRQn                BSP_DMA2_CH1_IRQ_NUM
+#define I2C5_RX_DMA_INT_PRIO            BSP_DMA2_CH1_IRQ_PRIO
+#define I2C5_RX_DMA_INT_SRC             INT_SRC_DMA2_TC1
 #endif

 /* DMA2 ch2 */
@ -135,9 +279,19 @@ extern "C" {
 #define UART2_RX_DMA_CHANNEL            DMA_CH2
 #define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
 #define UART2_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
 #define UART2_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
 #define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE)
+#define I2C6_TX_DMA_INSTANCE            CM_DMA2
+#define I2C6_TX_DMA_CHANNEL             DMA_CH2
+#define I2C6_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C6_TX_DMA_TRIG_SELECT         AOS_DMA2_2
+#define I2C6_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C6_TX_DMA_IRQn                BSP_DMA2_CH2_IRQ_NUM
+#define I2C6_TX_DMA_INT_PRIO            BSP_DMA2_CH2_IRQ_PRIO
+#define I2C6_TX_DMA_INT_SRC             INT_SRC_DMA2_TC2
 #endif

 /* DMA2 ch3 */
@ -146,9 +300,19 @@ extern "C" {
 #define UART2_TX_DMA_CHANNEL            DMA_CH3
 #define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
 #define UART2_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
 #define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
 #define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
+#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE)
+#define I2C6_RX_DMA_INSTANCE            CM_DMA2
+#define I2C6_RX_DMA_CHANNEL             DMA_CH3
+#define I2C6_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C6_RX_DMA_TRIG_SELECT         AOS_DMA2_3
+#define I2C6_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C6_RX_DMA_IRQn                BSP_DMA2_CH3_IRQ_NUM
+#define I2C6_RX_DMA_INT_PRIO            BSP_DMA2_CH3_IRQ_PRIO
+#define I2C6_RX_DMA_INT_SRC             INT_SRC_DMA2_TC3
 #endif

 /* DMA2 ch4 */
@ -157,6 +321,7 @@ extern "C" {
 #define UART6_RX_DMA_CHANNEL            DMA_CH4
 #define UART6_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART6_RX_DMA_TRIG_SELECT        AOS_DMA2_4
+#define UART6_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
 #define UART6_RX_DMA_IRQn               BSP_DMA2_CH4_IRQ_NUM
 #define UART6_RX_DMA_INT_PRIO           BSP_DMA2_CH4_IRQ_PRIO
 #define UART6_RX_DMA_INT_SRC            INT_SRC_DMA2_TC4
@ -168,6 +333,7 @@ extern "C" {
 #define UART6_TX_DMA_CHANNEL            DMA_CH5
 #define UART6_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART6_TX_DMA_TRIG_SELECT        AOS_DMA2_5
+#define UART6_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
 #define UART6_TX_DMA_IRQn               BSP_DMA2_CH5_IRQ_NUM
 #define UART6_TX_DMA_INT_PRIO           BSP_DMA2_CH5_IRQ_PRIO
 #define UART6_TX_DMA_INT_SRC            INT_SRC_DMA2_TC5
@ -179,6 +345,7 @@ extern "C" {
 #define UART7_RX_DMA_CHANNEL            DMA_CH6
 #define UART7_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART7_RX_DMA_TRIG_SELECT        AOS_DMA2_6
+#define UART7_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH6
 #define UART7_RX_DMA_IRQn               BSP_DMA2_CH6_IRQ_NUM
 #define UART7_RX_DMA_INT_PRIO           BSP_DMA2_CH6_IRQ_PRIO
 #define UART7_RX_DMA_INT_SRC            INT_SRC_DMA2_TC6
@ -190,6 +357,7 @@ extern "C" {
 #define UART7_TX_DMA_CHANNEL            DMA_CH7
 #define UART7_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
 #define UART7_TX_DMA_TRIG_SELECT        AOS_DMA2_7
+#define UART7_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH7
 #define UART7_TX_DMA_IRQn               BSP_DMA2_CH7_IRQ_NUM
 #define UART7_TX_DMA_INT_PRIO           BSP_DMA2_CH7_IRQ_PRIO
 #define UART7_TX_DMA_INT_SRC            INT_SRC_DMA2_TC7
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h
@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h
@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c1",                                     \
+        .Instance = CM_I2C1,                                    \
+        .clock    = FCG1_PERIPH_I2C1,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_TX_DMA_INSTANCE,                 \
+        .channel        = I2C1_TX_DMA_CHANNEL,                  \
+        .clock          = I2C1_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_TEI,                     \
+        .flag           = I2C1_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_RX_DMA_INSTANCE,                 \
+        .channel        = I2C1_RX_DMA_CHANNEL,                  \
+        .clock          = I2C1_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_RXI,                     \
+        .flag           = I2C1_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c2",                                     \
+        .Instance = CM_I2C2,                                    \
+        .clock    = FCG1_PERIPH_I2C2,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_TX_DMA_INSTANCE,                 \
+        .channel        = I2C2_TX_DMA_CHANNEL,                  \
+        .clock          = I2C2_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_TEI,                     \
+        .flag           = I2C2_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_RX_DMA_INSTANCE,                 \
+        .channel        = I2C2_RX_DMA_CHANNEL,                  \
+        .clock          = I2C2_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_RXI,                     \
+        .flag           = I2C2_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c3",                                     \
+        .Instance = CM_I2C3,                                    \
+        .clock    = FCG1_PERIPH_I2C3,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_TX_DMA_INSTANCE,                 \
+        .channel        = I2C3_TX_DMA_CHANNEL,                  \
+        .clock          = I2C3_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_TEI,                     \
+        .flag           = I2C3_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_RX_DMA_INSTANCE,                 \
+        .channel        = I2C3_RX_DMA_CHANNEL,                  \
+        .clock          = I2C3_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_RXI,                     \
+        .flag           = I2C3_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C4)
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c4",                                     \
+        .Instance = CM_I2C4,                                    \
+        .clock    = FCG1_PERIPH_I2C4,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C4_CONFIG */
+
+#if defined(BSP_I2C4_USING_DMA)
+#ifndef I2C4_TX_DMA_CONFIG
+#define I2C4_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_TX_DMA_INSTANCE,                 \
+        .channel        = I2C4_TX_DMA_CHANNEL,                  \
+        .clock          = I2C4_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_TEI,                     \
+        .flag           = I2C4_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_TX_DMA_CONFIG */
+
+#ifndef I2C4_RX_DMA_CONFIG
+#define I2C4_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_RX_DMA_INSTANCE,                 \
+        .channel        = I2C4_RX_DMA_CHANNEL,                  \
+        .clock          = I2C4_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_RXI,                     \
+        .flag           = I2C4_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_RX_DMA_CONFIG */
+#endif /* BSP_I2C4_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C5)
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c5",                                     \
+        .Instance = CM_I2C5,                                    \
+        .clock    = FCG1_PERIPH_I2C5,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C5_CONFIG */
+
+#if defined(BSP_I2C5_USING_DMA)
+#ifndef I2C5_TX_DMA_CONFIG
+#define I2C5_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_TX_DMA_INSTANCE,                 \
+        .channel        = I2C5_TX_DMA_CHANNEL,                  \
+        .clock          = I2C5_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_TEI,                     \
+        .flag           = I2C5_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_TX_DMA_CONFIG */
+
+#ifndef I2C5_RX_DMA_CONFIG
+#define I2C5_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_RX_DMA_INSTANCE,                 \
+        .channel        = I2C5_RX_DMA_CHANNEL,                  \
+        .clock          = I2C5_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_RXI,                     \
+        .flag           = I2C5_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_RX_DMA_CONFIG */
+#endif /* BSP_I2C5_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C6)
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c6",                                     \
+        .Instance = CM_I2C6,                                    \
+        .clock    = FCG1_PERIPH_I2C6,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C6_CONFIG */
+
+#if defined(BSP_I2C6_USING_DMA)
+#ifndef I2C6_TX_DMA_CONFIG
+#define I2C6_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_TX_DMA_INSTANCE,                 \
+        .channel        = I2C6_TX_DMA_CHANNEL,                  \
+        .clock          = I2C6_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_TEI,                     \
+        .flag           = I2C6_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_TX_DMA_CONFIG */
+
+#ifndef I2C6_RX_DMA_CONFIG
+#define I2C6_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_RX_DMA_INSTANCE,                 \
+        .channel        = I2C6_RX_DMA_CHANNEL,                  \
+        .clock          = I2C6_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_RXI,                     \
+        .flag           = I2C6_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_RX_DMA_CONFIG */
+#endif /* BSP_I2C6_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
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