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删除依赖TI的KeyStone_common.c文件

This commit is contained in:
Huang bo 2021-12-15 10:43:06 +08:00
parent c37fcb6049
commit 466f9ad4e3
9 changed files with 345 additions and 5460 deletions
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4
bsp/ti-tms320c6678/applications/board.c
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@ -11,7 +11,7 @@
#include "board.h"
#include "interrupt.h"
#include "drv_timer.h"
#include "KeyStone_common.h"
#include "common.h"
#include <rtthread.h>
@ -21,7 +21,7 @@
void rt_hw_board_init(void)
{
// initial CPU core
KeyStone_common_CPU_init();
keystone_cpu_init();
// initial interrupt controller
rt_hw_interrupt_init();

4355
bsp/ti-tms320c6678/common/KeyStone_common.c
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1090
bsp/ti-tms320c6678/common/KeyStone_common.h
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201
bsp/ti-tms320c6678/common/common.c Normal file
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@ -0,0 +1,201 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#include "common.h"
CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
CSL_TmrPlusRegs * gpTimerRegs[9] = {
(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_3_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_4_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_5_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_6_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_7_REGS,
(CSL_TmrPlusRegs *)(CSL_TIMER_7_REGS+(CSL_TIMER_7_REGS-CSL_TIMER_6_REGS))
};
void cpu_interrupt_init(void)
{
//clear interrupt and excpetion events
ICR = IFR;
ECR = EFR;
IER= 3; //disable all interrupts
/* disable event combine */
gpCGEM_regs->EVTMASK[0] = 0xffffffff;
gpCGEM_regs->EVTMASK[1] = 0xffffffff;
gpCGEM_regs->EVTMASK[2] = 0xffffffff;
gpCGEM_regs->EVTMASK[3] = 0xffffffff;
/*Clear all CPU events*/
gpCGEM_regs->EVTCLR[0]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[1]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[2]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[3]= 0xFFFFFFFF;
/*Interrupt Service Table Pointer to begining of LL2 memory*/
ISTP= 0x800000;
}
void keystone_cpu_init(void)
{
/* clear all interrupt flag/status, setup ISTP to begining of LL2 */
cpu_interrupt_init();
}
/*===============================Timer=================================*/
void reset_timer(int timer_num)
{
if(gpTimerRegs[timer_num]->TGCR)
{
gpTimerRegs[timer_num]->TGCR= 0;
gpTimerRegs[timer_num]->TCR= 0;
}
}
void timer64_init(Timer64_Config * tmrCfg)
{
reset_timer(tmrCfg->timer_num);
gpTimerRegs[tmrCfg->timer_num]->CNTLO= 0;
gpTimerRegs[tmrCfg->timer_num]->CNTHI= 0;
/*please note, in clock mode, two timer periods generate a clock,
one timer period output high voltage level, the other timer period
output low voltage level, so, the timer period should be half to the
desired output clock period*/
if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
tmrCfg->period= tmrCfg->period/2;
/*the value written into period register is the expected value minus one*/
gpTimerRegs[tmrCfg->timer_num]->PRDLO= _loll(tmrCfg->period-1);
gpTimerRegs[tmrCfg->timer_num]->PRDHI= _hill(tmrCfg->period-1);
if(tmrCfg->reload_period>1)
{
gpTimerRegs[tmrCfg->timer_num]->RELLO= _loll(tmrCfg->reload_period-1);
gpTimerRegs[tmrCfg->timer_num]->RELHI= _hill(tmrCfg->reload_period-1);
}
if(TIMER_WATCH_DOG==tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TGCR=
/*Select watch-dog mode*/
(CSL_TMR_TIMMODE_WDT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
|(CSL_TMR_TGCR_TIMLORS_MASK)
|(CSL_TMR_TGCR_TIMHIRS_MASK);
}
else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TGCR= TMR_TGCR_PLUSEN_MASK
/*for plus featuers, dual 32-bit unchained timer mode should be used*/
|(CSL_TMR_TIMMODE_DUAL_UNCHAINED<<CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
|(CSL_TMR_TGCR_TIMLORS_MASK);
//in plus mode, interrupt/event must be enabled manually
gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
}
else
{
gpTimerRegs[tmrCfg->timer_num]->TGCR=
/*Select 64-bit general timer mode*/
(CSL_TMR_TIMMODE_GPT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
|(CSL_TMR_TGCR_TIMLORS_MASK)
|(CSL_TMR_TGCR_TIMHIRS_MASK);
}
/*make timer stop with emulation*/
gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
if(TIMER_WATCH_DOG==tmrCfg->timerMode)
{
/*enable watchdog timer*/
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
|(CSL_TMR_WDTCR_WDKEY_CMD1<<CSL_TMR_WDTCR_WDKEY_SHIFT);
gpTimerRegs[tmrCfg->timer_num]->TCR=
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
/*The timer is enabled continuously*/
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
/*select pulse mode*/
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
/*active watchdog timer*/
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
|(CSL_TMR_WDTCR_WDKEY_CMD2<<CSL_TMR_WDTCR_WDKEY_SHIFT);
}
else if(TIMER_ONE_SHOT_PULSE==tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR=
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
/*The timer is enabled one-shot*/
|(CSL_TMR_ENAMODE_ENABLE<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
/*select pulse mode*/
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
}
else if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR=
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
/*The timer is enabled continuously*/
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
/*select clock mode*/
|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT )
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
}
else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR=
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
/*The timer is enabled continuously with period reload*/
|(CSL_TMR_ENAMODE_CONT_RELOAD<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
/*select clock mode*/
|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT )
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
}
else /*TIMER_PERIODIC_PULSE*/
{
gpTimerRegs[tmrCfg->timer_num]->TCR=
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
/*The timer is enabled continuously*/
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
/*select clock mode*/
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
}
}

110
bsp/ti-tms320c6678/common/common.h Normal file
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@ -0,0 +1,110 @@
/*
* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 Dystopia the first version
*/
#ifndef __COMMON_H__
#define __COMMON_H__
#include <c6x.h>
#include <cslr_cgem.h>
#include <cslr_device.h>
#include <cslr_bootcfg.h>
#include <cslr_tmr.h>
#include <csl_tmr.h>
/* DSP core clock speed in Hz */
#define DSP_CORE_SPEED_HZ 1000000000
extern CSL_CgemRegs * gpCGEM_regs;
extern CSL_BootcfgRegs * gpBootCfgRegs;
/*----------------------Timer plus registers definition----------------*/
typedef struct {
volatile unsigned int PID12;
volatile unsigned int EMUMGT_CLKSPD;
volatile unsigned int GPINT_EN;
volatile unsigned int GPDIR_DAT;
volatile unsigned int CNTLO;
volatile unsigned int CNTHI;
volatile unsigned int PRDLO;
volatile unsigned int PRDHI;
volatile unsigned int TCR;
volatile unsigned int TGCR;
volatile unsigned int WDTCR;
volatile unsigned int TLGC;
volatile unsigned int TLMR;
volatile unsigned int RELLO;
volatile unsigned int RELHI;
volatile unsigned int CAPLO;
volatile unsigned int CAPHI;
volatile unsigned int INTCTL_STAT;
volatile unsigned char RSVD0[24];
volatile unsigned int TIMERLO_COMPARE_REG[8];
volatile unsigned char RSVD1[32];
} CSL_TmrPlusRegs;
#define TMR_TCR_READRSTMODE_HI_SHIFT (26)
#define TMR_TCR_CAPEVTMODE_LO_SHIFT (12)
#define TMR_TCR_CAPMODE_LO_SHIFT (11)
#define TMR_TCR_READRSTMODE_LO_SHIFT (10)
#define TMR_TCR_READRSTMODE_HI_MASK (1<<26)
#define TMR_TCR_CAPEVTMODE_LO_MASK (3<<12)
#define TMR_TCR_CAPMODE_LO_MASK (1<<11)
#define TMR_TCR_READRSTMODE_LO_MASK (1<<10)
#define TMR_TGCR_PLUSEN_SHIFT 4
#define TMR_TGCR_PLUSEN_MASK (1<<4)
#define TMR_INTCTLSTAT_EN_ALL_CLR_ALL 0x000F000F
#define CSL_TMR_WDTCR_WDKEY_CMD1 (0x0000A5C6u)
#define CSL_TMR_WDTCR_WDKEY_CMD2 (0x0000DA7Eu)
#define CSL_TMR_ENAMODE_CONT_RELOAD 3
extern CSL_TmrPlusRegs * gpTimer0Regs;
extern CSL_TmrPlusRegs * gpTimer1Regs;
extern CSL_TmrPlusRegs * gpTimer2Regs;
extern CSL_TmrPlusRegs * gpTimer3Regs;
extern CSL_TmrPlusRegs * gpTimer4Regs;
extern CSL_TmrPlusRegs * gpTimer5Regs;
extern CSL_TmrPlusRegs * gpTimer6Regs;
extern CSL_TmrPlusRegs * gpTimer7Regs;
extern CSL_TmrPlusRegs * gpTimer8Regs;
extern CSL_TmrPlusRegs * gpTimerRegs[];
typedef enum
{
TIMER_ONE_SHOT_PULSE = 0, /*generate one shot pulse with timer*/
TIMER_PERIODIC_PULSE, /*generate periodic pulse with timer*/
TIMER_PERIODIC_CLOCK, /*generate periodic clock with timer*/
/*generate periodic square wave with period reload feature, the difference
between wave and clock is the duty cycle of clock is always 50%*/
TIMER_PERIODIC_WAVE,
TIMER_WATCH_DOG /*configure timer as watch dog*/
}TTimerMode;
typedef struct {
int timer_num; /*select one timer*/
TTimerMode timerMode; /*select function of the timer*/
unsigned long long period; /*in the unit of DSP core clock/6*/
unsigned long long reload_period; /*the reload value of period*/
int pulseWidth; /*pulse width between 0~3*/
}Timer64_Config;
/* Reset a 64-bit timer */
extern void reset_timer(int timer_num);
/* Initailize a 64-bit timer */
extern void timer64_init(Timer64_Config * tmrCfg);
extern void keystone_cpu_init(void);
#endif /* __COMMON_H__ */

9
bsp/ti-tms320c6678/driver/drv_timer.c
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@ -9,7 +9,8 @@
*/
#include "drv_timer.h"
#include "KeyStone_common.h"
#include "interrupt.h"
#include "common.h"
#include <rthw.h>
#include <rtthread.h>
@ -37,7 +38,7 @@ void rt_hw_system_timer_init(void)
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
// enable CPU INT14
CPU_interrupt_enable(1 << 14);
rt_hw_interrupt_umask(1 << 14);
return ;
}
@ -57,9 +58,9 @@ void rt_hw_system_timer_start(void)
// configure the timer to generate clocks and interrupts
tmrCfg.timer_num = DNUM;
tmrCfg.timerMode = TIMER_PERIODIC_CLOCK;
tmrCfg.period = (unsigned long long) RT_TICK_PER_SECOND * gDSP_Core_Speed_Hz / 6000;
tmrCfg.period = (unsigned long long) RT_TICK_PER_SECOND * DSP_CORE_SPEED_HZ / 6000;
tmrCfg.reload_period = 0;
// initial timer
Timer64_Init(&tmrCfg);
timer64_init(&tmrCfg);
}

3
bsp/ti-tms320c6678/driver/drv_timer.h
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@ -11,6 +11,9 @@
#ifndef __SYS_TIMER_H__
#define __SYS_TIMER_H__
#include <c6x.h>
#include <tistdtypes.h>
void rt_hw_system_timer_init(void);
void rt_hw_system_timer_start(void);

28
libcpu/ti-dsp/c6x/c66xx.h
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@ -11,15 +11,25 @@
#ifndef __C66XX_H__
#define __C66XX_H__
extern cregister volatile unsigned int IERR; /* Internal Exception Report Register */
extern cregister volatile unsigned int ECR; /* Exception Clear Register */
extern cregister volatile unsigned int EFR; /* Exception Flag Register */
extern cregister volatile unsigned int TSR; /* Task State Register */
extern cregister volatile unsigned int ITSR; /* Interrupt Task State Register */
extern cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */
extern cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */
extern cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */
extern cregister volatile unsigned int DNUM; /* Core number */
extern __cregister volatile unsigned int IERR; /* Internal Exception Report Register */
extern __cregister volatile unsigned int ECR; /* Exception Clear Register */
extern __cregister volatile unsigned int EFR; /* Exception Flag Register */
extern __cregister volatile unsigned int TSR; /* Task State Register */
extern __cregister volatile unsigned int ITSR; /* Interrupt Task State Register */
extern __cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */
extern __cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */
extern __cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */
extern __cregister volatile unsigned int DNUM; /* Core number */
extern __cregister volatile unsigned int AMR;
extern __cregister volatile unsigned int CSR;
extern __cregister volatile unsigned int IFR;
extern __cregister volatile unsigned int ISR;
extern __cregister volatile unsigned int ICR;
extern __cregister volatile unsigned int IER;
extern __cregister volatile unsigned int ISTP;
extern __cregister volatile unsigned int IRP;
extern __cregister volatile unsigned int NRP;
#ifdef _BIG_ENDIAN
#define RT_REG_PAIR(odd, even) unsigned long odd; unsigned long even

5
libcpu/ti-dsp/c6x/interrupt.c
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@ -60,6 +60,11 @@ void rt_hw_interrupt_umask(int vector)
{
return;
}
ICR = vector;
IER |= vector;
//enable GIE
TSR = TSR | 1;
}
/**