[bsp][stm32][stm32f429-atk-apollo][audio]add f429 audio driver
This commit is contained in:
Ernest
parent
ab37857609
commit
45fe517da5
File diff suppressed because one or more lines are too long
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@ -57,7 +57,7 @@
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/* #define HAL_LTDC_MODULE_ENABLED */
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/* #define HAL_RNG_MODULE_ENABLED */
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#define HAL_RTC_MODULE_ENABLED
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/* #define HAL_SAI_MODULE_ENABLED */
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#define HAL_SAI_MODULE_ENABLED
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#define HAL_SD_MODULE_ENABLED
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/* #define HAL_MMC_MODULE_ENABLED */
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#define HAL_SPI_MODULE_ENABLED
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@ -14,114 +14,120 @@ KeepUserPlacement=false
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Mcu.Family=STM32F4
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Mcu.IP0=ADC1
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Mcu.IP1=CAN1
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Mcu.IP10=SPI2
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Mcu.IP11=SPI5
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Mcu.IP12=SYS
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Mcu.IP13=TIM2
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Mcu.IP14=TIM11
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Mcu.IP15=TIM13
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Mcu.IP16=TIM14
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Mcu.IP17=USART1
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Mcu.IP18=USART2
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Mcu.IP19=USART3
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Mcu.IP10=SPI1
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Mcu.IP11=SPI2
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Mcu.IP12=SPI5
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Mcu.IP13=SYS
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Mcu.IP14=TIM2
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Mcu.IP15=TIM11
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Mcu.IP16=TIM13
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Mcu.IP17=TIM14
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Mcu.IP18=USART1
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Mcu.IP19=USART2
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Mcu.IP2=ETH
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Mcu.IP20=USART3
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Mcu.IP3=FMC
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Mcu.IP4=IWDG
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Mcu.IP5=NVIC
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Mcu.IP6=RCC
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Mcu.IP7=RTC
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Mcu.IP8=SDIO
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Mcu.IP9=SPI1
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Mcu.IPNb=20
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Mcu.IP8=SAI1
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Mcu.IP9=SDIO
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Mcu.IPNb=21
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Mcu.Name=STM32F429I(E-G)Tx
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Mcu.Package=LQFP176
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Mcu.Pin0=PC14/OSC32_IN
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Mcu.Pin1=PC15/OSC32_OUT
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Mcu.Pin10=PF9
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Mcu.Pin11=PH0/OSC_IN
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Mcu.Pin12=PH1/OSC_OUT
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Mcu.Pin13=PC0
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Mcu.Pin14=PC1
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Mcu.Pin15=PC2
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Mcu.Pin16=PC3
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Mcu.Pin17=PA1
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Mcu.Pin18=PA2
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Mcu.Pin19=PA3
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Mcu.Pin2=PF0
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Mcu.Pin20=PA5
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Mcu.Pin21=PA6
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Mcu.Pin22=PA7
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Mcu.Pin23=PC4
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Mcu.Pin24=PC5
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Mcu.Pin25=PF11
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Mcu.Pin26=PF12
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Mcu.Pin27=PF13
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Mcu.Pin28=PF14
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Mcu.Pin29=PF15
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Mcu.Pin3=PF1
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Mcu.Pin30=PG0
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Mcu.Pin31=PG1
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Mcu.Pin32=PE7
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Mcu.Pin33=PE8
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Mcu.Pin34=PE9
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Mcu.Pin35=PE10
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Mcu.Pin36=PE11
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Mcu.Pin37=PE12
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Mcu.Pin38=PE13
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Mcu.Pin39=PE14
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Mcu.Pin4=PF2
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Mcu.Pin40=PE15
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Mcu.Pin41=PB10
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Mcu.Pin42=PB11
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Mcu.Pin43=PB13
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Mcu.Pin44=PB14
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Mcu.Pin45=PB15
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Mcu.Pin46=PD8
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Mcu.Pin47=PD9
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Mcu.Pin48=PD10
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Mcu.Pin49=PD14
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Mcu.Pin5=PF3
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Mcu.Pin50=PD15
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Mcu.Pin51=PG2
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Mcu.Pin52=PG4
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Mcu.Pin53=PG5
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Mcu.Pin54=PG8
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Mcu.Pin55=PC8
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Mcu.Pin56=PC9
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Mcu.Pin57=PA9
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Mcu.Pin58=PA10
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Mcu.Pin59=PA11
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Mcu.Pin6=PF4
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Mcu.Pin60=PA12
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Mcu.Pin61=PA13
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Mcu.Pin62=PA14
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Mcu.Pin63=PC10
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Mcu.Pin64=PC11
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Mcu.Pin65=PC12
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Mcu.Pin66=PD0
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Mcu.Pin67=PD1
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Mcu.Pin68=PD2
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Mcu.Pin69=PD5
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Mcu.Pin7=PF5
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Mcu.Pin70=PD6
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Mcu.Pin71=PG11
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Mcu.Pin72=PG13
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Mcu.Pin73=PG14
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Mcu.Pin74=PG15
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Mcu.Pin75=PB3
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Mcu.Pin76=PB5
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Mcu.Pin77=PE0
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Mcu.Pin78=PE1
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Mcu.Pin79=VP_IWDG_VS_IWDG
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Mcu.Pin8=PF7
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Mcu.Pin80=VP_RTC_VS_RTC_Activate
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Mcu.Pin81=VP_SYS_VS_Systick
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Mcu.Pin82=VP_TIM2_VS_ClockSourceINT
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Mcu.Pin83=VP_TIM11_VS_ClockSourceINT
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Mcu.Pin84=VP_TIM13_VS_ClockSourceINT
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Mcu.Pin85=VP_TIM14_VS_ClockSourceINT
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Mcu.Pin9=PF8
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Mcu.PinsNb=86
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Mcu.Pin0=PE2
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Mcu.Pin1=PE3
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Mcu.Pin10=PF3
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Mcu.Pin11=PF4
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Mcu.Pin12=PF5
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Mcu.Pin13=PF7
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Mcu.Pin14=PF8
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Mcu.Pin15=PF9
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Mcu.Pin16=PH0/OSC_IN
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Mcu.Pin17=PH1/OSC_OUT
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Mcu.Pin18=PC0
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Mcu.Pin19=PC1
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Mcu.Pin2=PE4
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Mcu.Pin20=PC2
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Mcu.Pin21=PC3
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Mcu.Pin22=PA1
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Mcu.Pin23=PA2
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Mcu.Pin24=PA3
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Mcu.Pin25=PA5
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Mcu.Pin26=PA6
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Mcu.Pin27=PA7
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Mcu.Pin28=PC4
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Mcu.Pin29=PC5
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Mcu.Pin3=PE5
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Mcu.Pin30=PF11
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Mcu.Pin31=PF12
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Mcu.Pin32=PF13
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Mcu.Pin33=PF14
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Mcu.Pin34=PF15
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Mcu.Pin35=PG0
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Mcu.Pin36=PG1
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Mcu.Pin37=PE7
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Mcu.Pin38=PE8
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Mcu.Pin39=PE9
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Mcu.Pin4=PE6
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Mcu.Pin40=PE10
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Mcu.Pin41=PE11
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Mcu.Pin42=PE12
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Mcu.Pin43=PE13
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Mcu.Pin44=PE14
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Mcu.Pin45=PE15
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Mcu.Pin46=PB10
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Mcu.Pin47=PB11
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Mcu.Pin48=PB13
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Mcu.Pin49=PB14
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Mcu.Pin5=PC14/OSC32_IN
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Mcu.Pin50=PB15
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Mcu.Pin51=PD8
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Mcu.Pin52=PD9
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Mcu.Pin53=PD10
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Mcu.Pin54=PD14
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Mcu.Pin55=PD15
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Mcu.Pin56=PG2
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Mcu.Pin57=PG4
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Mcu.Pin58=PG5
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Mcu.Pin59=PG8
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Mcu.Pin6=PC15/OSC32_OUT
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Mcu.Pin60=PC8
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Mcu.Pin61=PC9
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Mcu.Pin62=PA9
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Mcu.Pin63=PA10
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Mcu.Pin64=PA11
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Mcu.Pin65=PA12
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Mcu.Pin66=PA13
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Mcu.Pin67=PA14
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Mcu.Pin68=PC10
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Mcu.Pin69=PC11
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Mcu.Pin7=PF0
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Mcu.Pin70=PC12
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Mcu.Pin71=PD0
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Mcu.Pin72=PD1
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Mcu.Pin73=PD2
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Mcu.Pin74=PD5
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Mcu.Pin75=PD6
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Mcu.Pin76=PG11
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Mcu.Pin77=PG13
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Mcu.Pin78=PG14
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Mcu.Pin79=PG15
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Mcu.Pin8=PF1
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Mcu.Pin80=PB3
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Mcu.Pin81=PB5
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Mcu.Pin82=PE0
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Mcu.Pin83=PE1
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Mcu.Pin84=VP_IWDG_VS_IWDG
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Mcu.Pin85=VP_RTC_VS_RTC_Activate
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Mcu.Pin86=VP_SYS_VS_Systick
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Mcu.Pin87=VP_TIM2_VS_ClockSourceINT
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Mcu.Pin88=VP_TIM11_VS_ClockSourceINT
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Mcu.Pin89=VP_TIM13_VS_ClockSourceINT
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Mcu.Pin9=PF2
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Mcu.Pin90=VP_TIM14_VS_ClockSourceINT
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Mcu.PinsNb=91
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Mcu.ThirdPartyNb=0
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Mcu.UserConstants=
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Mcu.UserName=STM32F429IGTx
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@ -230,6 +236,16 @@ PE12.Signal=FMC_D9_DA9
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PE13.Signal=FMC_D10_DA10
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PE14.Signal=FMC_D11_DA11
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PE15.Signal=FMC_D12_DA12
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PE2.Mode=SAI_A_MasterWithClock
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PE2.Signal=SAI1_MCLK_A
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PE3.Mode=SAI_B_SyncSlave
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PE3.Signal=SAI1_SD_B
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PE4.Mode=SAI_A_MasterWithClock
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PE4.Signal=SAI1_FS_A
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PE5.Mode=SAI_A_MasterWithClock
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PE5.Signal=SAI1_SCK_A
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PE6.Mode=SAI_A_MasterWithClock
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PE6.Signal=SAI1_SD_A
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PE7.Signal=FMC_D4_DA4
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PE8.Signal=FMC_D5_DA5
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PE9.Signal=FMC_D6_DA6
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@ -313,8 +329,8 @@ RCC.HCLKFreq_Value=180000000
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RCC.HSE_VALUE=25000000
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RCC.HSI_VALUE=16000000
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RCC.I2SClocksFreq_Value=160000000
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RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
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RCC.LCDTFTFreq_Value=20416666.666666668
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RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSAIN,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
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RCC.LCDTFTFreq_Value=25000000
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RCC.LSI_VALUE=32000
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RCC.MCO2PinFreq_Value=180000000
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RCC.PLLCLKFreq_Value=180000000
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@ -322,23 +338,35 @@ RCC.PLLM=15
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RCC.PLLN=216
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RCC.PLLQ=8
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RCC.PLLQCLKFreq_Value=45000000
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RCC.PLLSAIN=60
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RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
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RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
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RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
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RCC.RTCFreq_Value=32768
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RCC.RTCHSEDivFreq_Value=12500000
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RCC.SAI_AClocksFreq_Value=20416666.666666668
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RCC.SAI_BClocksFreq_Value=20416666.666666668
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RCC.SAI_AClocksFreq_Value=25000000
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RCC.SAI_BClocksFreq_Value=25000000
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RCC.SYSCLKFreq_VALUE=180000000
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RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
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RCC.VCOI2SOutputFreq_Value=320000000
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RCC.VCOInputFreq_Value=1666666.6666666667
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RCC.VCOOutputFreq_Value=360000000
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RCC.VCOSAIOutputFreq_Value=81666666.66666667
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RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668
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RCC.VCOSAIOutputFreq_ValueR=40833333.333333336
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RCC.VCOSAIOutputFreq_Value=100000000
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RCC.VCOSAIOutputFreq_ValueQ=25000000
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RCC.VCOSAIOutputFreq_ValueR=50000000
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RCC.VcooutputI2S=160000000
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RCC.VcooutputI2SQ=160000000
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SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-49.13 %
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SAI1.FrameLength-SAI_B_SyncSlave=8
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SAI1.IPParameters=Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,Synchro-SAI_B_SyncSlave,FrameLength-SAI_B_SyncSlave,Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock
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SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A
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SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B
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SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE
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SAI1.RealAudioFreq-SAI_A_MasterWithClock=97.656 KHz
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SAI1.Synchro-SAI_A_MasterWithClock=SAI_ASYNCHRONOUS
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SAI1.Synchro-SAI_B_SyncSlave=SAI_SYNCHRONOUS
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SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER
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SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE
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SH.ADCx_IN5.0=ADC1_IN5,IN5
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SH.ADCx_IN5.ConfNb=1
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SH.FMC_A0.0=FMC_A0,13b-sda1
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@ -72,6 +72,9 @@ IWDG_HandleTypeDef hiwdg;
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RTC_HandleTypeDef hrtc;
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SAI_HandleTypeDef hsai_BlockA1;
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SAI_HandleTypeDef hsai_BlockB1;
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SD_HandleTypeDef hsd;
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SPI_HandleTypeDef hspi1;
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@ -112,6 +115,7 @@ static void MX_SPI1_Init(void);
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static void MX_SPI2_Init(void);
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static void MX_SPI5_Init(void);
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static void MX_CAN1_Init(void);
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static void MX_SAI1_Init(void);
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static void MX_USART2_UART_Init(void);
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static void MX_USART3_UART_Init(void);
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/* USER CODE BEGIN PFP */
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@ -168,6 +172,7 @@ int main(void)
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MX_SPI2_Init();
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MX_SPI5_Init();
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MX_CAN1_Init();
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MX_SAI1_Init();
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MX_USART2_UART_Init();
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MX_USART3_UART_Init();
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/* USER CODE BEGIN 2 */
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@ -197,6 +202,12 @@ void SystemClock_Config(void)
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/** Macro to configure SAI1BlockB clock source selection
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*/
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__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(SAI_CLKSOURCE_PLLSAI);
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/** Macro to configure SAI1BlockA clock source selection
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*/
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__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(SAI_CLKSOURCE_PLLSAI);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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@ -237,7 +248,10 @@ void SystemClock_Config(void)
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{
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Error_Handler();
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}
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLSAI|RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.PLLSAI.PLLSAIN = 60;
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PeriphClkInitStruct.PLLSAI.PLLSAIQ = 4;
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PeriphClkInitStruct.PLLSAIDivQ = 1;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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@ -439,6 +453,72 @@ static void MX_RTC_Init(void)
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}
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/**
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* @brief SAI1 Initialization Function
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* @param None
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* @retval None
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*/
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static void MX_SAI1_Init(void)
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{
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/* USER CODE BEGIN SAI1_Init 0 */
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/* USER CODE END SAI1_Init 0 */
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/* USER CODE BEGIN SAI1_Init 1 */
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/* USER CODE END SAI1_Init 1 */
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hsai_BlockA1.Instance = SAI1_Block_A;
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hsai_BlockA1.Init.Protocol = SAI_FREE_PROTOCOL;
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hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_TX;
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hsai_BlockA1.Init.DataSize = SAI_DATASIZE_24;
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hsai_BlockA1.Init.FirstBit = SAI_FIRSTBIT_MSB;
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hsai_BlockA1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
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hsai_BlockA1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
|
||||
hsai_BlockA1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
|
||||
hsai_BlockA1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
|
||||
hsai_BlockA1.Init.ClockSource = SAI_CLKSOURCE_PLLSAI;
|
||||
hsai_BlockA1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K;
|
||||
hsai_BlockA1.FrameInit.FrameLength = 8;
|
||||
hsai_BlockA1.FrameInit.ActiveFrameLength = 1;
|
||||
hsai_BlockA1.FrameInit.FSDefinition = SAI_FS_STARTFRAME;
|
||||
hsai_BlockA1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
|
||||
hsai_BlockA1.FrameInit.FSOffset = SAI_FS_FIRSTBIT;
|
||||
hsai_BlockA1.SlotInit.FirstBitOffset = 0;
|
||||
hsai_BlockA1.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
|
||||
hsai_BlockA1.SlotInit.SlotNumber = 1;
|
||||
hsai_BlockA1.SlotInit.SlotActive = 0x00000000;
|
||||
if (HAL_SAI_Init(&hsai_BlockA1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
hsai_BlockB1.Instance = SAI1_Block_B;
|
||||
hsai_BlockB1.Init.Protocol = SAI_FREE_PROTOCOL;
|
||||
hsai_BlockB1.Init.AudioMode = SAI_MODESLAVE_RX;
|
||||
hsai_BlockB1.Init.DataSize = SAI_DATASIZE_24;
|
||||
hsai_BlockB1.Init.FirstBit = SAI_FIRSTBIT_MSB;
|
||||
hsai_BlockB1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
|
||||
hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
|
||||
hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
|
||||
hsai_BlockB1.FrameInit.FrameLength = 8;
|
||||
hsai_BlockB1.FrameInit.ActiveFrameLength = 1;
|
||||
hsai_BlockB1.FrameInit.FSDefinition = SAI_FS_STARTFRAME;
|
||||
hsai_BlockB1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
|
||||
hsai_BlockB1.FrameInit.FSOffset = SAI_FS_FIRSTBIT;
|
||||
hsai_BlockB1.SlotInit.FirstBitOffset = 0;
|
||||
hsai_BlockB1.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
|
||||
hsai_BlockB1.SlotInit.SlotNumber = 1;
|
||||
hsai_BlockB1.SlotInit.SlotActive = 0x00000000;
|
||||
if (HAL_SAI_Init(&hsai_BlockB1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN SAI1_Init 2 */
|
||||
|
||||
/* USER CODE END SAI1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDIO Initialization Function
|
||||
* @param None
|
||||
|
|
@ -896,12 +976,12 @@ static void MX_GPIO_Init(void)
|
|||
{
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
|
||||
|
|
|
|||
|
|
@ -1105,6 +1105,97 @@ void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
|
|||
/* USER CODE END SDRAM_MspDeInit 1 */
|
||||
}
|
||||
|
||||
static uint32_t SAI1_client =0;
|
||||
|
||||
void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
/* SAI1 */
|
||||
if(hsai->Instance==SAI1_Block_A)
|
||||
{
|
||||
/* Peripheral clock enable */
|
||||
if (SAI1_client == 0)
|
||||
{
|
||||
__HAL_RCC_SAI1_CLK_ENABLE();
|
||||
}
|
||||
SAI1_client ++;
|
||||
|
||||
/**SAI1_A_Block_A GPIO Configuration
|
||||
PE2 ------> SAI1_MCLK_A
|
||||
PE4 ------> SAI1_FS_A
|
||||
PE5 ------> SAI1_SCK_A
|
||||
PE6 ------> SAI1_SD_A
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
}
|
||||
if(hsai->Instance==SAI1_Block_B)
|
||||
{
|
||||
/* Peripheral clock enable */
|
||||
if (SAI1_client == 0)
|
||||
{
|
||||
__HAL_RCC_SAI1_CLK_ENABLE();
|
||||
}
|
||||
SAI1_client ++;
|
||||
|
||||
/**SAI1_B_Block_B GPIO Configuration
|
||||
PE3 ------> SAI1_SD_B
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
|
||||
{
|
||||
|
||||
/* SAI1 */
|
||||
if(hsai->Instance==SAI1_Block_A)
|
||||
{
|
||||
SAI1_client --;
|
||||
if (SAI1_client == 0)
|
||||
{
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SAI1_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**SAI1_A_Block_A GPIO Configuration
|
||||
PE2 ------> SAI1_MCLK_A
|
||||
PE4 ------> SAI1_FS_A
|
||||
PE5 ------> SAI1_SCK_A
|
||||
PE6 ------> SAI1_SD_A
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6);
|
||||
|
||||
}
|
||||
if(hsai->Instance==SAI1_Block_B)
|
||||
{
|
||||
SAI1_client --;
|
||||
if (SAI1_client == 0)
|
||||
{
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SAI1_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**SAI1_B_Block_B GPIO Configuration
|
||||
PE3 ------> SAI1_SD_B
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
|
|
|||
|
|
@ -60,7 +60,24 @@ menu "Onboard Peripheral Drivers"
|
|||
select RT_USING_DFS
|
||||
select RT_USING_DFS_ELMFAT
|
||||
default n
|
||||
|
||||
config BSP_USING_AUDIO
|
||||
bool "Enable AUDIO (WM8978)"
|
||||
select BSP_USING_I2C1
|
||||
select RT_USING_AUDIO
|
||||
default n
|
||||
|
||||
if BSP_USING_AUDIO
|
||||
config BSP_USING_AUDIO_PLAY
|
||||
bool "Enable Audio Play"
|
||||
default y
|
||||
|
||||
config BSP_USING_AUDIO_RECORD
|
||||
bool "Enable Audio Record"
|
||||
select BSP_USING_AUDIO_PLAY
|
||||
default n
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
|
|
|||
|
|
@ -20,11 +20,21 @@ if GetDepend(['BSP_USING_SPI_FLASH']):
|
|||
|
||||
if GetDepend(['BSP_USING_SDCARD']):
|
||||
src += Glob('ports/sdcard_port.c')
|
||||
|
||||
|
||||
if GetDepend(['BSP_USING_AUDIO']):
|
||||
src += Glob('ports/audio/drv_wm8978.c')
|
||||
src += Glob('ports/audio/drv_sound.c')
|
||||
|
||||
if GetDepend(['BSP_USING_AUDIO_RECORD']):
|
||||
src += Glob('ports/audio/drv_mic.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/CubeMX_Config/Inc']
|
||||
path += [cwd + '/ports']
|
||||
|
||||
if GetDepend(['BSP_USING_AUDIO']):
|
||||
path += [cwd + '/ports/audio']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
|
|
|
|||
|
|
@ -0,0 +1,385 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-28 Ernest the first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_mic.h"
|
||||
#include "drv_wm8978.h"
|
||||
#include "drv_sound.h"
|
||||
|
||||
#define DBG_TAG "drv.mic"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#define CODEC_I2C_NAME ("i2c1")
|
||||
#define RX_DMA_FIFO_SIZE (2048)
|
||||
|
||||
extern struct drv_sai _sai_a;
|
||||
static struct drv_sai _sai_b = {0};
|
||||
|
||||
struct stm32_mic
|
||||
{
|
||||
struct rt_i2c_bus_device *i2c_bus;
|
||||
struct rt_audio_device audio;
|
||||
struct rt_audio_configure config;
|
||||
rt_uint8_t *rx_fifo;
|
||||
rt_bool_t startup;
|
||||
};
|
||||
static struct stm32_mic _stm32_audio_record = {0};
|
||||
|
||||
static rt_err_t SAIB_samplerate_set(rt_uint32_t freq)
|
||||
{
|
||||
__HAL_SAI_DISABLE(&_sai_b.hsai);
|
||||
_sai_b.hsai.Init.AudioFrequency = freq;
|
||||
HAL_SAI_Init(&_sai_b.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_b.hsai);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void SAIB_channels_set(rt_uint16_t channels)
|
||||
{
|
||||
if (channels == 2)
|
||||
{
|
||||
_sai_b.hsai.Init.MonoStereoMode = SAI_STEREOMODE;
|
||||
}
|
||||
else
|
||||
{
|
||||
_sai_b.hsai.Init.MonoStereoMode = SAI_MONOMODE;
|
||||
}
|
||||
__HAL_SAI_DISABLE(&_sai_b.hsai);
|
||||
HAL_SAI_Init(&_sai_b.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_b.hsai);
|
||||
}
|
||||
|
||||
void SAIB_samplebits_set(rt_uint16_t samplebits)
|
||||
{
|
||||
switch (samplebits)
|
||||
{
|
||||
case 16:
|
||||
_sai_b.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
break;
|
||||
case 24:
|
||||
_sai_b.hsai.Init.DataSize = SAI_DATASIZE_24;
|
||||
break;
|
||||
case 32:
|
||||
_sai_b.hsai.Init.DataSize = SAI_DATASIZE_32;
|
||||
break;
|
||||
default:
|
||||
_sai_b.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
break;
|
||||
}
|
||||
__HAL_SAI_DISABLE(&_sai_b.hsai);
|
||||
HAL_SAI_Init(&_sai_b.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_b.hsai);
|
||||
}
|
||||
|
||||
void SAIB_config_set(struct rt_audio_configure config)
|
||||
{
|
||||
SAIB_channels_set(config.channels);
|
||||
SAIB_samplerate_set(config.samplerate);
|
||||
SAIB_samplebits_set(config.samplebits);
|
||||
}
|
||||
|
||||
static void SAIB_config_init()
|
||||
{
|
||||
_sai_b.hsai.Instance = SAI1_Block_B;
|
||||
_sai_b.hsai.Init.AudioMode = SAI_MODESLAVE_RX;
|
||||
_sai_b.hsai.Init.Synchro = SAI_SYNCHRONOUS;
|
||||
_sai_b.hsai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE;
|
||||
_sai_b.hsai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
|
||||
_sai_b.hsai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;
|
||||
_sai_b.hsai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S;
|
||||
_sai_b.hsai.Init.MonoStereoMode = SAI_STEREOMODE;
|
||||
_sai_b.hsai.Init.Protocol = SAI_FREE_PROTOCOL;
|
||||
_sai_b.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
_sai_b.hsai.Init.FirstBit = SAI_FIRSTBIT_MSB;
|
||||
_sai_b.hsai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
|
||||
|
||||
/* frame */
|
||||
_sai_b.hsai.FrameInit.FrameLength = 64;
|
||||
_sai_b.hsai.FrameInit.ActiveFrameLength = 32;
|
||||
_sai_b.hsai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
|
||||
_sai_b.hsai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
|
||||
_sai_b.hsai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
|
||||
|
||||
/* slot */
|
||||
_sai_b.hsai.SlotInit.FirstBitOffset = 0;
|
||||
_sai_b.hsai.SlotInit.SlotSize = SAI_SLOTSIZE_32B;
|
||||
_sai_b.hsai.SlotInit.SlotNumber = 2;
|
||||
_sai_b.hsai.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1;
|
||||
|
||||
HAL_SAI_Init(&_sai_b.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_b.hsai);
|
||||
}
|
||||
|
||||
static void SAIB_tx_dma(void)
|
||||
{
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
__HAL_LINKDMA(&_sai_b.hsai, hdmarx, _sai_b.hdma);
|
||||
_sai_b.hdma.Instance = DMA2_Stream5;
|
||||
_sai_b.hdma.Init.Channel = DMA_CHANNEL_0;
|
||||
_sai_b.hdma.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
_sai_b.hdma.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
_sai_b.hdma.Init.MemInc = DMA_MINC_ENABLE;
|
||||
_sai_b.hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||||
_sai_b.hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
||||
_sai_b.hdma.Init.Mode = DMA_CIRCULAR;
|
||||
_sai_b.hdma.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
_sai_b.hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
_sai_b.hdma.Init.MemBurst = DMA_MBURST_SINGLE;
|
||||
_sai_b.hdma.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
HAL_DMA_DeInit(&_sai_b.hdma);
|
||||
HAL_DMA_Init(&_sai_b.hdma);
|
||||
|
||||
__HAL_DMA_DISABLE(&_sai_b.hdma);
|
||||
|
||||
__HAL_DMA_CLEAR_FLAG(&_sai_b.hdma, DMA_FLAG_TCIF1_5);
|
||||
__HAL_DMA_ENABLE_IT(&_sai_b.hdma, DMA_IT_TC);
|
||||
|
||||
HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 1);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
|
||||
}
|
||||
|
||||
static rt_err_t sai_record_init()
|
||||
{
|
||||
SAIA_config_init();
|
||||
SAIB_config_init();
|
||||
|
||||
/* set record samplerate */
|
||||
SAIA_config_set(_stm32_audio_record.config);
|
||||
SAIB_config_set(_stm32_audio_record.config);
|
||||
SAIA_tx_dma();
|
||||
SAIB_tx_dma();
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void DMA2_Stream5_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_DMA_IRQHandler(_sai_b.hsai.hdmarx);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
|
||||
{
|
||||
rt_audio_rx_done(&(_stm32_audio_record.audio), &_stm32_audio_record.rx_fifo[0], RX_DMA_FIFO_SIZE / 2);
|
||||
}
|
||||
|
||||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
|
||||
{
|
||||
|
||||
rt_audio_rx_done(&(_stm32_audio_record.audio), &_stm32_audio_record.rx_fifo[RX_DMA_FIFO_SIZE / 2], RX_DMA_FIFO_SIZE / 2);
|
||||
}
|
||||
|
||||
static rt_err_t stm32_mic_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type);
|
||||
|
||||
switch (caps->main_type)
|
||||
{
|
||||
/* Provide capabilities of INTPUT unit */
|
||||
case AUDIO_TYPE_INPUT:
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_DSP_PARAM:
|
||||
caps->udata.config.channels = _stm32_audio_record.config.channels;
|
||||
caps->udata.config.samplebits = _stm32_audio_record.config.samplebits;
|
||||
caps->udata.config.samplerate = _stm32_audio_record.config.samplerate;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_SAMPLERATE:
|
||||
caps->udata.config.samplerate = _stm32_audio_record.config.samplerate;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_CHANNELS:
|
||||
caps->udata.config.channels = _stm32_audio_record.config.channels;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_SAMPLEBITS:
|
||||
caps->udata.config.samplebits = _stm32_audio_record.config.samplebits;
|
||||
break;
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void start_record_mode(void)
|
||||
{
|
||||
rt_uint8_t temp[4] = {0};
|
||||
|
||||
HAL_SAI_DMAStop(&_sai_b.hsai);
|
||||
HAL_SAI_Transmit(&_sai_a.hsai, temp, 4, 0);
|
||||
HAL_SAI_Receive_DMA(&_sai_b.hsai, _stm32_audio_record.rx_fifo, RX_DMA_FIFO_SIZE / 2);
|
||||
}
|
||||
|
||||
static rt_err_t stm32_mic_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type);
|
||||
|
||||
switch (caps->main_type)
|
||||
{
|
||||
case AUDIO_TYPE_INPUT:
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
|
||||
case AUDIO_DSP_PARAM:
|
||||
{
|
||||
_stm32_audio_record.config.samplerate = caps->udata.config.samplerate;
|
||||
_stm32_audio_record.config.channels = caps->udata.config.channels;
|
||||
_stm32_audio_record.config.samplebits = caps->udata.config.samplebits;
|
||||
|
||||
HAL_SAI_DMAStop(&_sai_b.hsai);
|
||||
SAIA_config_set(caps->udata.config);
|
||||
SAIB_config_set(caps->udata.config);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_DSP_SAMPLERATE:
|
||||
{
|
||||
_stm32_audio_record.config.samplerate = caps->udata.config.samplerate;
|
||||
SAIA_samplerate_set(caps->udata.config.samplerate);
|
||||
break;
|
||||
}
|
||||
case AUDIO_DSP_CHANNELS:
|
||||
{
|
||||
_stm32_audio_record.config.channels = caps->udata.config.channels;
|
||||
SAIA_channels_set(caps->udata.config.channels);
|
||||
SAIB_channels_set(caps->udata.config.channels);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_DSP_SAMPLEBITS:
|
||||
{
|
||||
_stm32_audio_record.config.samplebits = caps->udata.config.samplebits;
|
||||
SAIA_samplebits_set(caps->udata.config.samplebits);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
/* After set config, MCLK will stop */
|
||||
start_record_mode();
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_mic_init(struct rt_audio_device *audio)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
/* initialize wm8978 */
|
||||
_stm32_audio_record.i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME);
|
||||
if (_stm32_audio_record.i2c_bus != RT_NULL)
|
||||
{
|
||||
LOG_D("Find device i2c1 success");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Find device i2c1 error");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
result = wm8978_init(_stm32_audio_record.i2c_bus);
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
LOG_E("initialize wm8978 failed");
|
||||
return result;
|
||||
}
|
||||
|
||||
sai_record_init();
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_mic_start(struct rt_audio_device *audio, int stream)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
if (stream == AUDIO_STREAM_RECORD)
|
||||
{
|
||||
/* set mic start */
|
||||
wm8978_record_start(_stm32_audio_record.i2c_bus);
|
||||
/* start transfer data */
|
||||
start_record_mode();
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_mic_stop(struct rt_audio_device *audio, int stream)
|
||||
{
|
||||
if (stream == AUDIO_STREAM_RECORD)
|
||||
{
|
||||
HAL_SAI_DMAStop(&_sai_b.hsai);
|
||||
HAL_SAI_DMAStop(&_sai_a.hsai);
|
||||
wm8978_mic_enabled(_stm32_audio_record.i2c_bus, 0);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static struct rt_audio_ops _mic_audio_ops =
|
||||
{
|
||||
.getcaps = stm32_mic_getcaps,
|
||||
.configure = stm32_mic_configure,
|
||||
.init = stm32_mic_init,
|
||||
.start = stm32_mic_start,
|
||||
.stop = stm32_mic_stop,
|
||||
.transmit = RT_NULL,
|
||||
.buffer_info = RT_NULL,
|
||||
};
|
||||
|
||||
int rt_hw_mic_init(void)
|
||||
{
|
||||
struct rt_audio_device *audio = &_stm32_audio_record.audio;
|
||||
/* mic default */
|
||||
_stm32_audio_record.rx_fifo = rt_calloc(1, RX_DMA_FIFO_SIZE);
|
||||
if (_stm32_audio_record.rx_fifo == RT_NULL)
|
||||
{
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
_stm32_audio_record.config.channels = 1;
|
||||
_stm32_audio_record.config.samplerate = 16000;
|
||||
_stm32_audio_record.config.samplebits = 16;
|
||||
|
||||
/* register mic device */
|
||||
audio->ops = &_mic_audio_ops;
|
||||
rt_audio_register(audio, "mic0", RT_DEVICE_FLAG_RDONLY, &_stm32_audio_record);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_hw_mic_init);
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-28 Ernest the first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_MIC_H_
|
||||
#define __DRV_MIC_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,470 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-28 Ernest the first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_wm8978.h"
|
||||
#include "drv_sound.h"
|
||||
|
||||
#define DBG_TAG "drv.sound"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#define CODEC_I2C_NAME ("i2c1")
|
||||
|
||||
#define TX_DMA_FIFO_SIZE (2048)
|
||||
|
||||
struct drv_sai _sai_a = {0};
|
||||
|
||||
struct stm32_audio
|
||||
{
|
||||
struct rt_i2c_bus_device *i2c_bus;
|
||||
struct rt_audio_device audio;
|
||||
struct rt_audio_configure replay_config;
|
||||
int replay_volume;
|
||||
rt_uint8_t *tx_fifo;
|
||||
rt_bool_t startup;
|
||||
};
|
||||
struct stm32_audio _stm32_audio_play = {0};
|
||||
|
||||
/* sample_rate, PLLI2SN(50.7), PLLI2SQ, PLLI2SDivQ, MCKDIV */
|
||||
const rt_uint32_t SAI_PSC_TBL[][5] =
|
||||
{
|
||||
{AUDIO_FREQUENCY_048K, 206, 7, 0, 12},
|
||||
{AUDIO_FREQUENCY_044K, 257, 2, 18, 2},
|
||||
{AUDIO_FREQUENCY_032K, 206, 7, 0, 6},
|
||||
{AUDIO_FREQUENCY_022K, 257, 2, 18, 1},
|
||||
{AUDIO_FREQUENCY_016K, 206, 7, 0, 3},
|
||||
{AUDIO_FREQUENCY_011K, 257, 2, 18, 0},
|
||||
{AUDIO_FREQUENCY_008K, 206, 7, 0, 2},
|
||||
};
|
||||
|
||||
void SAIA_samplerate_set(rt_uint32_t freq)
|
||||
{
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
int i;
|
||||
|
||||
/* check frequence */
|
||||
for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++)
|
||||
{
|
||||
if ((freq) == SAI_PSC_TBL[i][0])break;
|
||||
}
|
||||
if (i == (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])))
|
||||
{
|
||||
LOG_E("Can not support this frequence: %d.", freq);
|
||||
return;
|
||||
}
|
||||
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S;
|
||||
PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1];
|
||||
PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2];
|
||||
PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1;
|
||||
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
|
||||
__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S);
|
||||
|
||||
__HAL_SAI_DISABLE(&_sai_a.hsai);
|
||||
_sai_a.hsai.Init.AudioFrequency = freq;
|
||||
HAL_SAI_Init(&_sai_a.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_a.hsai);
|
||||
}
|
||||
|
||||
void SAIA_channels_set(rt_uint16_t channels)
|
||||
{
|
||||
if (channels == 2)
|
||||
{
|
||||
_sai_a.hsai.Init.MonoStereoMode = SAI_STEREOMODE;
|
||||
}
|
||||
else
|
||||
{
|
||||
_sai_a.hsai.Init.MonoStereoMode = SAI_MONOMODE;
|
||||
}
|
||||
__HAL_SAI_DISABLE(&_sai_a.hsai);
|
||||
HAL_SAI_Init(&_sai_a.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_a.hsai);
|
||||
}
|
||||
|
||||
void SAIA_samplebits_set(rt_uint16_t samplebits)
|
||||
{
|
||||
switch (samplebits)
|
||||
{
|
||||
case 16:
|
||||
_sai_a.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
break;
|
||||
case 24:
|
||||
_sai_a.hsai.Init.DataSize = SAI_DATASIZE_24;
|
||||
break;
|
||||
case 32:
|
||||
_sai_a.hsai.Init.DataSize = SAI_DATASIZE_32;
|
||||
break;
|
||||
default:
|
||||
_sai_a.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
break;
|
||||
}
|
||||
__HAL_SAI_DISABLE(&_sai_a.hsai);
|
||||
HAL_SAI_Init(&_sai_a.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_a.hsai);
|
||||
}
|
||||
|
||||
void SAIA_config_set(struct rt_audio_configure config)
|
||||
{
|
||||
SAIA_channels_set(config.channels);
|
||||
SAIA_samplerate_set(config.samplerate);
|
||||
SAIA_samplebits_set(config.samplebits);
|
||||
}
|
||||
|
||||
/* initial sai A */
|
||||
rt_err_t SAIA_config_init(void)
|
||||
{
|
||||
_sai_a.hsai.Instance = SAI1_Block_A;
|
||||
_sai_a.hsai.Init.AudioMode = SAI_MODEMASTER_TX;
|
||||
_sai_a.hsai.Init.Synchro = SAI_ASYNCHRONOUS;
|
||||
_sai_a.hsai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE;
|
||||
_sai_a.hsai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
|
||||
_sai_a.hsai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;
|
||||
_sai_a.hsai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S;
|
||||
|
||||
_sai_a.hsai.Init.Protocol = SAI_FREE_PROTOCOL;
|
||||
_sai_a.hsai.Init.DataSize = SAI_DATASIZE_16;
|
||||
_sai_a.hsai.Init.FirstBit = SAI_FIRSTBIT_MSB;
|
||||
_sai_a.hsai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
|
||||
|
||||
//frame
|
||||
_sai_a.hsai.FrameInit.FrameLength = 64;
|
||||
_sai_a.hsai.FrameInit.ActiveFrameLength = 32;
|
||||
_sai_a.hsai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
|
||||
_sai_a.hsai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
|
||||
_sai_a.hsai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
|
||||
|
||||
//slot
|
||||
_sai_a.hsai.SlotInit.FirstBitOffset = 0;
|
||||
_sai_a.hsai.SlotInit.SlotSize = SAI_SLOTSIZE_32B;
|
||||
_sai_a.hsai.SlotInit.SlotNumber = 2;
|
||||
_sai_a.hsai.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1;
|
||||
|
||||
HAL_SAI_Init(&_sai_a.hsai);
|
||||
__HAL_SAI_ENABLE(&_sai_a.hsai);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t SAIA_tx_dma(void)
|
||||
{
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
__HAL_LINKDMA(&_sai_a.hsai, hdmatx, _sai_a.hdma);
|
||||
|
||||
_sai_a.hdma.Instance = DMA2_Stream3;
|
||||
_sai_a.hdma.Init.Channel = DMA_CHANNEL_0;
|
||||
_sai_a.hdma.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
_sai_a.hdma.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
_sai_a.hdma.Init.MemInc = DMA_MINC_ENABLE;
|
||||
|
||||
_sai_a.hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||||
_sai_a.hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
||||
|
||||
_sai_a.hdma.Init.Mode = DMA_CIRCULAR;
|
||||
_sai_a.hdma.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
_sai_a.hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
_sai_a.hdma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
_sai_a.hdma.Init.MemBurst = DMA_MBURST_SINGLE;
|
||||
_sai_a.hdma.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
|
||||
HAL_DMA_DeInit(&_sai_a.hdma);
|
||||
HAL_DMA_Init(&_sai_a.hdma);
|
||||
|
||||
__HAL_DMA_DISABLE(&_sai_a.hdma);
|
||||
|
||||
__HAL_DMA_ENABLE_IT(&_sai_a.hdma, DMA_IT_TC);
|
||||
__HAL_DMA_CLEAR_FLAG(&_sai_a.hdma, DMA_FLAG_TCIF3_7);
|
||||
/* set nvic */
|
||||
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void DMA2_Stream3_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_DMA_IRQHandler(_sai_a.hsai.hdmatx);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
|
||||
{
|
||||
rt_audio_tx_complete(&_stm32_audio_play.audio);
|
||||
}
|
||||
|
||||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
|
||||
{
|
||||
rt_audio_tx_complete(&_stm32_audio_play.audio);
|
||||
}
|
||||
|
||||
rt_err_t sai_a_init()
|
||||
{
|
||||
/* set sai_a DMA */
|
||||
SAIA_tx_dma();
|
||||
SAIA_config_init();
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_player_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data;
|
||||
|
||||
LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type);
|
||||
|
||||
switch (caps->main_type)
|
||||
{
|
||||
case AUDIO_TYPE_QUERY: /* query the types of hw_codec device */
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_TYPE_QUERY:
|
||||
caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
|
||||
break;
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_DSP_PARAM:
|
||||
caps->udata.config.channels = st_audio->replay_config.channels;
|
||||
caps->udata.config.samplebits = st_audio->replay_config.samplebits;
|
||||
caps->udata.config.samplerate = st_audio->replay_config.samplerate;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_SAMPLERATE:
|
||||
caps->udata.config.samplerate = st_audio->replay_config.samplerate;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_CHANNELS:
|
||||
caps->udata.config.channels = st_audio->replay_config.channels;
|
||||
break;
|
||||
|
||||
case AUDIO_DSP_SAMPLEBITS:
|
||||
caps->udata.config.samplebits = st_audio->replay_config.samplebits;
|
||||
break;
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_TYPE_MIXER: /* report the Mixer Units */
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_MIXER_QUERY:
|
||||
caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_LINE;
|
||||
break;
|
||||
|
||||
case AUDIO_MIXER_VOLUME:
|
||||
caps->udata.value = st_audio->replay_volume;
|
||||
break;
|
||||
|
||||
case AUDIO_MIXER_LINE:
|
||||
break;
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_player_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data;
|
||||
|
||||
LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type);
|
||||
|
||||
switch (caps->main_type)
|
||||
{
|
||||
case AUDIO_TYPE_MIXER:
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_MIXER_MUTE:
|
||||
{
|
||||
/* set mute mode */
|
||||
wm8978_mute_enabled(_stm32_audio_play.i2c_bus, RT_FALSE);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_MIXER_VOLUME:
|
||||
{
|
||||
int volume = caps->udata.value;
|
||||
|
||||
st_audio->replay_volume = volume;
|
||||
/* set mixer volume */
|
||||
wm8978_set_volume(_stm32_audio_play.i2c_bus, volume);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_TYPE_OUTPUT:
|
||||
{
|
||||
switch (caps->sub_type)
|
||||
{
|
||||
case AUDIO_DSP_PARAM:
|
||||
{
|
||||
struct rt_audio_configure config = caps->udata.config;
|
||||
|
||||
st_audio->replay_config.samplerate = config.samplerate;
|
||||
st_audio->replay_config.samplebits = config.samplebits;
|
||||
st_audio->replay_config.channels = config.channels;
|
||||
|
||||
SAIA_config_set(config);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_DSP_SAMPLERATE:
|
||||
{
|
||||
st_audio->replay_config.samplerate = caps->udata.config.samplerate;
|
||||
SAIA_samplerate_set(caps->udata.config.samplerate);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_DSP_CHANNELS:
|
||||
{
|
||||
st_audio->replay_config.channels = caps->udata.config.channels;
|
||||
SAIA_channels_set(caps->udata.config.channels);
|
||||
break;
|
||||
}
|
||||
|
||||
case AUDIO_DSP_SAMPLEBITS:
|
||||
{
|
||||
st_audio->replay_config.samplebits = caps->udata.config.samplebits;
|
||||
SAIA_samplebits_set(caps->udata.config.samplebits);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_player_init(struct rt_audio_device *audio)
|
||||
{
|
||||
/* initialize wm8978 */
|
||||
_stm32_audio_play.i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME);
|
||||
|
||||
sai_a_init();
|
||||
wm8978_init(_stm32_audio_play.i2c_bus);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_player_start(struct rt_audio_device *audio, int stream)
|
||||
{
|
||||
if (stream == AUDIO_STREAM_REPLAY)
|
||||
{
|
||||
HAL_SAI_Transmit_DMA(&_sai_a.hsai, _stm32_audio_play.tx_fifo, TX_DMA_FIFO_SIZE / 2);
|
||||
wm8978_player_start(_stm32_audio_play.i2c_bus);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_player_stop(struct rt_audio_device *audio, int stream)
|
||||
{
|
||||
if (stream == AUDIO_STREAM_REPLAY)
|
||||
{
|
||||
HAL_SAI_DMAStop(&_sai_a.hsai);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void stm32_player_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
|
||||
{
|
||||
/**
|
||||
* TX_FIFO
|
||||
* +----------------+----------------+
|
||||
* | block1 | block2 |
|
||||
* +----------------+----------------+
|
||||
* \ block_size /
|
||||
*/
|
||||
info->buffer = _stm32_audio_play.tx_fifo;
|
||||
info->total_size = TX_DMA_FIFO_SIZE;
|
||||
info->block_size = TX_DMA_FIFO_SIZE / 2;
|
||||
info->block_count = 2;
|
||||
}
|
||||
static struct rt_audio_ops _p_audio_ops =
|
||||
{
|
||||
.getcaps = stm32_player_getcaps,
|
||||
.configure = stm32_player_configure,
|
||||
.init = stm32_player_init,
|
||||
.start = stm32_player_start,
|
||||
.stop = stm32_player_stop,
|
||||
.transmit = RT_NULL,
|
||||
.buffer_info = stm32_player_buffer_info,
|
||||
};
|
||||
|
||||
int rt_hw_sound_init(void)
|
||||
{
|
||||
rt_uint8_t *tx_fifo;
|
||||
|
||||
/* player */
|
||||
tx_fifo = rt_malloc(TX_DMA_FIFO_SIZE);
|
||||
if (tx_fifo == RT_NULL)
|
||||
{
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
rt_memset(tx_fifo, 0, TX_DMA_FIFO_SIZE);
|
||||
_stm32_audio_play.tx_fifo = tx_fifo;
|
||||
|
||||
/* register sound device */
|
||||
_stm32_audio_play.audio.ops = &_p_audio_ops;
|
||||
rt_audio_register(&_stm32_audio_play.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &_stm32_audio_play);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_hw_sound_init);
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-07-28 Ernest the first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_SOUND_H_
|
||||
#define __DRV_SOUND_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000)
|
||||
#define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100)
|
||||
#define AUDIO_FREQUENCY_032K ((rt_uint32_t) 32000)
|
||||
#define AUDIO_FREQUENCY_022K ((rt_uint32_t) 22050)
|
||||
#define AUDIO_FREQUENCY_016K ((rt_uint32_t) 16000)
|
||||
#define AUDIO_FREQUENCY_011K ((rt_uint32_t) 11025)
|
||||
#define AUDIO_FREQUENCY_008K ((rt_uint32_t) 8000)
|
||||
|
||||
struct drv_sai
|
||||
{
|
||||
SAI_HandleTypeDef hsai;
|
||||
DMA_HandleTypeDef hdma;
|
||||
};
|
||||
|
||||
void SAIA_samplerate_set(rt_uint32_t samplerate);
|
||||
void SAIA_channels_set(rt_uint16_t channels);
|
||||
void SAIA_samplebits_set(rt_uint16_t samplebits);
|
||||
void SAIA_config_set(struct rt_audio_configure config);
|
||||
|
||||
rt_err_t SAIA_tx_dma(void);
|
||||
rt_err_t SAIA_config_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-14 ZeroFree first implementation
|
||||
* 2019-07-28 Ernest perfect player, add record and other APIs
|
||||
*/
|
||||
|
||||
#ifndef __DRV_WM8978_H__
|
||||
#define __DRV_WM8978_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
enum data_fomat_select
|
||||
{
|
||||
RIGHT_FOMAT_SELECT,
|
||||
LEFT_FOMAT_SELECT,
|
||||
I2S_FOMAT_SELECT,
|
||||
PCM_FOMAT_SELECT,
|
||||
};
|
||||
|
||||
rt_err_t wm8978_init(struct rt_i2c_bus_device *dev);
|
||||
void wm8978_player_start(struct rt_i2c_bus_device *dev);
|
||||
void wm8978_record_start(struct rt_i2c_bus_device *dev);
|
||||
|
||||
int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol);
|
||||
|
||||
void wm8978_reset(struct rt_i2c_bus_device *dev);
|
||||
/* enable ADC/DAC */
|
||||
void wm8978_ADC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool);
|
||||
void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool);
|
||||
|
||||
void wm8978_mic_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool);
|
||||
void wm8978_linein_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool);
|
||||
void wm8978_aux_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool);
|
||||
void wm8978_linein_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value);
|
||||
void wm8978_aux_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value);
|
||||
void wm8978_mic_gain(struct rt_i2c_bus_device *dev, rt_uint8_t gain);
|
||||
void wm8978_output_set(struct rt_i2c_bus_device *dev, rt_bool_t dac, rt_bool_t bypass);
|
||||
void wm8978_hpvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume);
|
||||
void wm8978_spkvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume);
|
||||
|
||||
/* set interface mode */
|
||||
void wm8978_interface_cfg(struct rt_i2c_bus_device *dev, enum data_fomat_select fmt, rt_uint32_t bitBand);
|
||||
|
||||
void wm8978_mute_enabled(struct rt_i2c_bus_device *dev, rt_bool_t enable);
|
||||
rt_err_t wm8978_set_EQ1(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain);
|
||||
rt_err_t wm8978_set_EQ2(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain);
|
||||
rt_err_t wm8978_set_EQ3(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain);
|
||||
rt_err_t wm8978_set_EQ4(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain);
|
||||
rt_err_t wm8978_set_EQ5(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain);
|
||||
void wm8978_3D_Set(struct rt_i2c_bus_device *dev, rt_uint8_t depth);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue