diff --git a/bsp/renesas/ebf_qi_min_6m5/.settings/standalone.prefs b/bsp/renesas/ebf_qi_min_6m5/.settings/standalone.prefs
index acab027996..b6f207cd9b 100644
--- a/bsp/renesas/ebf_qi_min_6m5/.settings/standalone.prefs
+++ b/bsp/renesas/ebf_qi_min_6m5/.settings/standalone.prefs
@@ -1,19 +1,21 @@
-#Sun Nov 13 22:01:41 CST 2022
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#3.5.0/libraries=
+#Sun Jun 04 12:44:50 CST 2023
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2425160085,ra/fsp/inc/api/bsp_api.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|1728953905,ra/fsp/inc/fsp_features.h|3297195641,ra/fsp/inc/fsp_version.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|546480625,ra/fsp/inc/fsp_common_api.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.4.0/all=1446732504,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.4.0/all=1835725510,ra/fsp/src/bsp/mcu/all/bsp_io.c|2359800297,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1399471156,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1915400095,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|668319255,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1060094479,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2399628405,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|27008654,ra/fsp/src/bsp/mcu/all/bsp_io.h|2365965045,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|271204625,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1664932476,ra/fsp/inc/fsp_version.h|1884526901,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3610800851,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3793821860,ra/fsp/inc/instances/r_ioport.h|270868601,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2678185049,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2970131887,ra/fsp/src/bsp/mcu/all/bsp_security.c|552454302,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1610748464,ra/fsp/inc/fsp_features.h|543620856,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2942601344,ra/fsp/inc/fsp_common_api.h|3376402702,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1707338993,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2618298326,ra/fsp/inc/api/r_ioport_api.h|3085135894,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1246740431,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1668386995,ra/fsp/src/bsp/mcu/all/bsp_security.h|1509328298,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2932063803,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3032783805,ra/fsp/src/bsp/mcu/all/bsp_common.h|1128795121,ra/fsp/inc/api/bsp_api.h|1220888647,ra/fsp/src/bsp/mcu/all/bsp_common.c|871460117,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4290340792,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3375746094,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=DeviceAndToolSelection
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.4.0/all=3548214691,ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h|1616333260,ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h|4125051366,ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.582032887=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#3.5.0/all=3982164632,ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h|1585467956,ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h|4282536086,ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.4.0/all=3793821860,ra/fsp/inc/instances/r_ioport.h|2618298326,ra/fsp/inc/api/r_ioport_api.h|2879227488,ra/fsp/src/r_ioport/r_ioport.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.4.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#4.4.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.4.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.4.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.4.0/all=620459583,ra/fsp/src/r_sci_uart/r_sci_uart.c|1201226050,ra/fsp/inc/instances/r_sci_uart.h|1461745579,ra/fsp/inc/api/r_uart_api.h|1910009580,ra/fsp/inc/api/r_transfer_api.h
diff --git a/bsp/renesas/ebf_qi_min_6m5/README.md b/bsp/renesas/ebf_qi_min_6m5/README.md
index 130435400c..65348aa15d 100644
--- a/bsp/renesas/ebf_qi_min_6m5/README.md
+++ b/bsp/renesas/ebf_qi_min_6m5/README.md
@@ -29,14 +29,15 @@
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
-| :----------------- | :----------------- | :------------- |
+|:-------- |:-------- |:--------------- |
| UART | 支持 | UART4 为默认日志输出端口 |
| GPIO | 支持 | |
+| I2C | 支持 | |
+| SPI | 支持 | |
| 持续更新中... | | |
| **外接外设** | **支持情况** | **备注** |
| 持续更新中... | | |
-
## 使用说明
使用说明分为如下两个章节：
@@ -44,6 +45,7 @@
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
@@ -129,7 +131,7 @@ void hal_entry(void)
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
-1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 3.5.0 版本
+1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 4.4.0 版本
2. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
**ENV 配置**
@@ -139,12 +141,12 @@ void hal_entry(void)
此 BSP 默认只开启了 UART4 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
+
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
-
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
diff --git a/bsp/renesas/ebf_qi_min_6m5/board/Kconfig b/bsp/renesas/ebf_qi_min_6m5/board/Kconfig
index 5dce5057b7..2890268e74 100644
--- a/bsp/renesas/ebf_qi_min_6m5/board/Kconfig
+++ b/bsp/renesas/ebf_qi_min_6m5/board/Kconfig
@@ -50,6 +50,111 @@ menu "Hardware Drivers Config"
endif
endif
+ menuconfig BSP_USING_I2C
+ bool "Enable I2C BUS"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C
+ menuconfig BSP_USING_SCI_I2C
+ bool "Enable SCI I2C BUS"
+ default n
+ if BSP_USING_SCI_I2C
+ config BSP_USING_SCI_I2C0
+ bool "Enable SCI I2C0 BUS"
+ default n
+ config BSP_USING_SCI_I2C1
+ bool "Enable SCI I2C1 BUS"
+ default n
+ config BSP_USING_SCI_I2C2
+ bool "Enable SCI I2C2 BUS"
+ default n
+ config BSP_USING_SCI_I2C3
+ bool "Enable SCI I2C3 BUS"
+ default n
+ config BSP_USING_SCI_I2C4
+ bool "Enable SCI I2C4 BUS"
+ default n
+ config BSP_USING_SCI_I2C5
+ bool "Enable SCI I2C5 BUS"
+ default n
+ config BSP_USING_SCI_I2C6
+ bool "Enable SCI I2C6 BUS"
+ default n
+ config BSP_USING_SCI_I2C7
+ bool "Enable SCI I2C7 BUS"
+ default n
+ config BSP_USING_SCI_I2C8
+ bool "Enable SCI I2C8 BUS"
+ default n
+ config BSP_USING_SCI_I2C9
+ bool "Enable SCI I2C9 BUS"
+ default n
+ endif
+ config BSP_USING_HW_I2C
+ bool "Enable Hardware I2C BUS"
+ default n
+ if BSP_USING_HW_I2C
+ config BSP_USING_HW_I2C1
+ bool "Enable Hardware I2C1 BUS"
+ default n
+ endif
+ if !BSP_USING_HW_I2C
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ hex "i2c1 scl pin number"
+ range 0x0000 0x0B0F
+ default 0x050C
+ config BSP_I2C1_SDA_PIN
+ hex "I2C1 sda pin number"
+ range 0x0000 0x0B0F
+ default 0x050B
+ endif
+ endif
+ endif
+
+ menuconfig BSP_USING_SCI_SPI
+ bool "Enable SCI SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SCI_SPI
+ config BSP_USING_SCI_SPI0
+ bool "Enable SCI SPI0 BUS"
+ default n
+ config BSP_USING_SCI_SPI1
+ bool "Enable SCI SPI1 BUS"
+ default n
+ config BSP_USING_SCI_SPI2
+ bool "Enable SCI SPI2 BUS"
+ default n
+ config BSP_USING_SCI_SPI3
+ bool "Enable SCI SPI3 BUS"
+ default n
+ config BSP_USING_SCI_SPI5
+ bool "Enable SCI SPI5 BUS"
+ default n
+ config BSP_USING_SCI_SPI6
+ bool "Enable SCI SPI6 BUS"
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI0
+ bool "Enable SPI0 BUS"
+ default n
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+ endif
+
endmenu
menu "Board extended module Drivers"
diff --git a/bsp/renesas/ebf_qi_min_6m5/board/SConscript b/bsp/renesas/ebf_qi_min_6m5/board/SConscript
index ca95be14e2..f5c04afb84 100644
--- a/bsp/renesas/ebf_qi_min_6m5/board/SConscript
+++ b/bsp/renesas/ebf_qi_min_6m5/board/SConscript
@@ -9,4 +9,9 @@ for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+objs = objs + DefineGroup('Drivers', [], depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
Return('objs')
diff --git a/bsp/renesas/ebf_qi_min_6m5/buildinfo.gpdsc b/bsp/renesas/ebf_qi_min_6m5/buildinfo.gpdsc
index c199227672..d18df28cb0 100644
--- a/bsp/renesas/ebf_qi_min_6m5/buildinfo.gpdsc
+++ b/bsp/renesas/ebf_qi_min_6m5/buildinfo.gpdsc
@@ -43,10 +43,13 @@
+
+
+
@@ -59,7 +62,7 @@
-
+
diff --git a/bsp/renesas/ebf_qi_min_6m5/configuration.xml b/bsp/renesas/ebf_qi_min_6m5/configuration.xml
index d98fbcf153..c15a1fb97e 100644
--- a/bsp/renesas/ebf_qi_min_6m5/configuration.xml
+++ b/bsp/renesas/ebf_qi_min_6m5/configuration.xml
@@ -3,12 +3,13 @@
+
-
+
@@ -20,6 +21,7 @@
+
@@ -37,6 +39,7 @@
+
@@ -70,13 +73,18 @@
+
+
+
+
+
@@ -113,8 +121,10 @@
+
+
@@ -125,8 +135,10 @@
+
+
@@ -137,41 +149,43 @@
+
+
-
- Board Support Package Common Files
- Renesas.RA.3.5.0.pack
-
-
- I/O Port
- Renesas.RA.3.5.0.pack
-
-
- Arm CMSIS Version 5 - Core (M)
- Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack
-
-
- Board support package for R7FA6M5BH3CFC
- Renesas.RA_mcu_ra6m5.3.5.0.pack
-
-
- Board support package for RA6M5
- Renesas.RA_mcu_ra6m5.3.5.0.pack
-
-
- Board support package for RA6M5 - FSP Data
- Renesas.RA_mcu_ra6m5.3.5.0.pack
-
-
+
Custom Board Support Files
- Renesas.RA_board_custom.3.5.0.pack
+ Renesas.RA_board_custom.4.4.0.pack
-
+
+ Board support package for R7FA6M5BH3CFC
+ Renesas.RA_mcu_ra6m5.4.4.0.pack
+
+
+ Board support package for RA6M5
+ Renesas.RA_mcu_ra6m5.4.4.0.pack
+
+
+ Board support package for RA6M5 - FSP Data
+ Renesas.RA_mcu_ra6m5.4.4.0.pack
+
+
+ Arm CMSIS Version 5 - Core (M)
+ Arm.CMSIS5.5.9.0+renesas.0.fsp.4.4.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.4.4.0.pack
+
+
+ I/O Port
+ Renesas.RA.4.4.0.pack
+
+
SCI UART
- Renesas.RA.3.5.0.pack
+ Renesas.RA.4.4.0.pack
@@ -183,10 +197,6 @@
-
-
-
-
@@ -205,6 +215,10 @@
+
+
+
+
@@ -223,6 +237,7 @@
+
diff --git a/bsp/renesas/ebf_qi_min_6m5/script/memory_regions.scat b/bsp/renesas/ebf_qi_min_6m5/memory_regions.scat
similarity index 95%
rename from bsp/renesas/ebf_qi_min_6m5/script/memory_regions.scat
rename to bsp/renesas/ebf_qi_min_6m5/memory_regions.scat
index fc4d8e0bb0..7af88a1df2 100644
--- a/bsp/renesas/ebf_qi_min_6m5/script/memory_regions.scat
+++ b/bsp/renesas/ebf_qi_min_6m5/memory_regions.scat
@@ -12,7 +12,7 @@
#define OPTION_SETTING_S_LENGTH 0x100
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
- #define SDRAM_START 0x90000000
+ #define SDRAM_START 0x80010000
#define SDRAM_LENGTH 0x0
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x4000000
diff --git a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx
index 371ab3ff1b..7a9bcfa946 100644
--- a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx
+++ b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx
@@ -335,7 +335,7 @@
-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal
RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
- ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;.
+ ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;.
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
index 2f048e4552..8b4765f186 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
- * @version V5.0.4
- * @date 23. July 2019
+ * @version V5.0.5
+ * @date 02. February 2022
******************************************************************************/
/*
- * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,7 +33,7 @@
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
index 33df455436..94128a1a70 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
- * @version V1.4.1
- * @date 04. June 2021
+ * @version V1.4.2
+ * @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -526,7 +526,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -535,7 +535,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
@@ -1490,15 +1493,14 @@ typedef struct
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
- uint32_t RESERVED12[4];
+ uint32_t RESERVED12[3];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
- __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
- __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
- __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
- uint32_t RESERVED14[3];
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
@@ -3158,6 +3160,15 @@ typedef struct
/*@} */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
index 2bd9e76064..c119fbf242 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version V5.2.2
- * @date 04. June 2021
+ * @version V5.2.3
+ * @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2182,6 +2185,15 @@ typedef struct
/*@} */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
index f9cf6ab183..18a2e6fb03 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version V5.2.2
- * @date 04. June 2021
+ * @version V5.2.3
+ * @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
/*@} */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
index 552c29464d..3843d9542c 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
- * @version V1.1.2
- * @date 04. June 2021
+ * @version V1.1.3
+ * @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
/*@} */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
index ecee4e0afb..faa30ce36a 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm55.h
* @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
- * @version V1.2.1
- * @date 04. June 2021
+ * @version V1.2.4
+ * @date 21. April 2022
******************************************************************************/
/*
- * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -58,7 +58,7 @@
* CMSIS definitions
******************************************************************************/
/**
- \ingroup Cortex_CM55
+ \ingroup Cortex_M55
@{
*/
@@ -303,9 +303,11 @@
Core Register contain:
- Core Register
- Core NVIC Register
+ - Core EWIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
+ - Core PMU Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
@@ -526,7 +528,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -535,7 +537,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
@@ -987,13 +992,13 @@ typedef struct
/**
\ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
+ \defgroup CMSIS_ICB Implementation Control Block register (ICB)
+ \brief Type definitions for the Implementation Control Block Register
@{
*/
/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
+ \brief Structure type to access the Implementation Control Block (ICB).
*/
typedef struct
{
@@ -1001,13 +1006,56 @@ typedef struct
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
+} ICB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */
+#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */
+
+#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */
+#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */
+#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */
+
+#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */
+#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */
+
+#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */
+#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */
+
+#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */
+#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */
+
+#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */
+#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */
+
+#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */
+#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */
+
+#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */
+#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */
+
+#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-/*@} end of group CMSIS_SCnotSCB */
+/*@} end of group CMSIS_ICB */
/**
@@ -1349,6 +1397,133 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Memory System Control Registers (MEMSYSCTL)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory System Control Registers (MEMSYSCTL).
+ */
+typedef struct
+{
+ __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */
+ __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */
+ uint32_t RESERVED1[2U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */
+ __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */
+ uint32_t RESERVED2[313U];
+ __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */
+ __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */
+ uint32_t RESERVED3[2U];
+ __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */
+ uint32_t RESERVED4[44U];
+ __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */
+ __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */
+ uint32_t RESERVED5[2U];
+ __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */
+} MemSysCtl_Type;
+
+/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */
+#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */
+#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */
+
+#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */
+#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
+
+#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */
+#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */
+#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */
+#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */
+
+#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
+#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
+
+#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */
+#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */
+
+#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */
+#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */
+
+/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */
+#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */
+#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */
+
+#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */
+#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */
+
+#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */
+#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */
+
+#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */
+#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */
+
+/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */
+#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */
+#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */
+
+#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */
+#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */
+
+/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */
+#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */
+#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */
+
+#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */
+#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */
+
+/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */
+#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */
+#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */
+
+#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */
+#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */
+
+/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
+
+/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
+
+
+/*@}*/ /* end of group MemSysCtl_Type */
+
+
/**
\ingroup CMSIS_core_register
\defgroup PwrModCtl_Type Power Mode Control Registers
@@ -1361,26 +1536,315 @@ typedef struct
*/
typedef struct
{
- __IOM uint32_t CPDLPSTATE;
- __IOM uint32_t DPDLPSTATE;
+ __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */
+ __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */
} PwrModCtl_Type;
-
/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
-#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE CLPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE CLPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
-#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE ELPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE ELPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */
-#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE RLPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE RLPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
-#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE DLPSTATE Position */
-#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk 3UL /*!< PWRMODCTL DPDLPSTATE DLPSTATE Mask */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
-/*@}*/ /* end of group CMSIS_PWRMODCTL */
+/*@}*/ /* end of group PwrModCtl_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup EWIC_Type External Wakeup Interrupt Controller Registers
+ \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
+ @{
+ */
+
+/**
+ \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
+ */
+typedef struct
+{
+ __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */
+ uint32_t RESERVED0[31U];
+ __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */
+ __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */
+} EWIC_Type;
+
+/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */
+#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */
+#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */
+
+#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */
+#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */
+
+#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */
+#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */
+#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */
+#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */
+
+#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */
+#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */
+
+#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */
+#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */
+#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */
+#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */
+
+/*@}*/ /* end of group EWIC_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Error Banking Registers (ERRBNK)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Error Banking Registers (ERRBNK).
+ */
+typedef struct
+{
+ __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */
+ __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */
+ __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */
+ uint32_t RESERVED1[2U];
+ __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */
+} ErrBnk_Type;
+
+/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */
+#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */
+#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */
+
+#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */
+#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */
+
+#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */
+#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */
+
+#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */
+#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */
+
+#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */
+#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */
+
+/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */
+#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */
+#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */
+
+#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */
+#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */
+
+#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */
+#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */
+
+#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */
+#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */
+
+#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */
+#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */
+#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */
+#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */
+
+#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */
+#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */
+
+#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */
+#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */
+
+#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */
+#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */
+
+#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */
+#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */
+
+#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */
+#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */
+#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */
+#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */
+
+#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */
+#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */
+
+#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */
+#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */
+
+#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */
+#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */
+
+#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */
+#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */
+
+#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */
+#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */
+#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */
+#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */
+
+#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */
+#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */
+
+#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */
+#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */
+
+#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */
+#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */
+
+#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */
+#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */
+
+#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */
+#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */
+
+#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */
+#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */
+#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */
+#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */
+
+#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */
+#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */
+
+#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */
+#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */
+
+#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */
+#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */
+
+#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */
+#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */
+
+#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */
+#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */
+
+#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */
+#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */
+
+/*@}*/ /* end of group ErrBnk_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
+ */
+typedef struct
+{
+ __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */
+ __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */
+} PrcCfgInf_Type;
+
+/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */
+
+/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */
+
+/*@}*/ /* end of group PrcCfgInf_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup STL_Type Software Test Library Observation Registers
+ \brief Type definitions for the Software Test Library Observation Registerss (STL)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Software Test Library Observation Registerss (STL).
+ */
+typedef struct
+{
+ __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */
+ __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */
+ uint32_t RESERVED0[2U];
+ __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */
+ __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */
+ __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */
+ __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */
+
+} STL_Type;
+
+/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */
+#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */
+#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */
+
+#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */
+#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */
+
+#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */
+#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */
+
+#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */
+#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */
+
+/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */
+#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */
+#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */
+
+#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */
+#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */
+
+#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */
+#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */
+
+#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */
+#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */
+
+/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */
+#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */
+#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */
+
+#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */
+#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */
+
+#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */
+#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */
+
+/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */
+#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */
+#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */
+
+#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */
+#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */
+
+/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */
+#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */
+#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */
+
+#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */
+#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */
+
+/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */
+#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */
+#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */
+
+#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */
+#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */
+
+/*@}*/ /* end of group STL_Type */
/**
@@ -1524,15 +1988,14 @@ typedef struct
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
- uint32_t RESERVED12[4];
+ uint32_t RESERVED12[3];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
- __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
- __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
- __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
- uint32_t RESERVED14[3];
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
@@ -3127,7 +3590,12 @@ typedef struct
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */
+ #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */
#define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */
+ #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */
+ #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */
+ #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
@@ -3136,14 +3604,19 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */
+ #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */
#define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */
+ #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */
+ #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */
+ #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
@@ -3175,7 +3648,7 @@ typedef struct
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
@@ -3195,6 +3668,69 @@ typedef struct
/*@} */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
+
+/* 'SCnSCB' is deprecated and replaced by 'ICB' */
+typedef ICB_Type SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos)
+#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk)
+
+#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos)
+#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk)
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos)
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk)
+
+#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos)
+#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk)
+
+#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos)
+#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk)
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos)
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk)
+
+#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos)
+#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk)
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos)
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk)
+
+#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos)
+#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk)
+
+#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos)
+#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk)
+
+#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos)
+#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk)
+
+#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos)
+#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk)
+
+#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos)
+#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk)
+
+#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos)
+#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk)
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos)
+#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk)
+
+#define SCnSCB (ICB)
+#define SCnSCB_NS (ICB_NS)
+
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
@@ -3888,6 +4424,9 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */
+#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */
+#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */
#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h
new file mode 100644
index 0000000000..6046311189
--- /dev/null
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h
@@ -0,0 +1,4672 @@
+/**************************************************************************//**
+ * @file core_cm85.h
+ * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File
+ * @version V1.0.4
+ * @date 21. April 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM85_H_GENERIC
+#define __CORE_CM85_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M85
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM85 definitions */
+
+#define __CORTEX_M (85U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM85_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM85_H_DEPENDANT
+#define __CORE_CM85_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM85_REV
+ #define __CM85_REV 0x0001U
+ #warning "__CM85_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
+ #define __PMU_PRESENT 0U
+ #warning "__PMU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __PMU_PRESENT != 0U
+ #ifndef __PMU_NUM_EVENTCNT
+ #define __PMU_NUM_EVENTCNT 8U
+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+ #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+ #endif
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M85 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core EWIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core PMU Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:1; /*!< bit: 20 Reserved */
+ uint32_t B:1; /*!< bit: 21 BTI active (read 0) */
+ uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_B_Pos 21U /*!< xPSR: B Position */
+#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */
+ uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */
+ uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */
+ uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */
+ uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */
+#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */
+
+#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */
+#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */
+
+#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */
+#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */
+
+#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */
+#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */
+
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED7[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ICB Implementation Control Block register (ICB)
+ \brief Type definitions for the Implementation Control Block Register
+ @{
+ */
+
+/**
+ \brief Structure type to access the Implementation Control Block (ICB).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} ICB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */
+#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */
+
+#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */
+#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */
+#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */
+
+#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */
+#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */
+
+#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+/* Interrupt Controller Type Register Definitions */
+#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_ICB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Memory System Control Registers (MEMSYSCTL)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory System Control Registers (MEMSYSCTL).
+ */
+typedef struct
+{
+ __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */
+ __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */
+ uint32_t RESERVED1[2U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */
+ __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */
+ uint32_t RESERVED2[313U];
+ __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */
+ __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */
+ uint32_t RESERVED3[2U];
+ __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */
+ uint32_t RESERVED4[44U];
+ __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */
+ __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */
+ uint32_t RESERVED5[2U];
+ __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */
+} MemSysCtl_Type;
+
+/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */
+#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */
+#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */
+
+#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */
+#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
+
+#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */
+#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */
+#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
+#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
+
+#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */
+#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */
+
+#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */
+#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */
+
+/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */
+#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */
+#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */
+
+#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */
+#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */
+
+/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */
+#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */
+#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */
+
+#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */
+#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */
+
+/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */
+#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */
+#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */
+
+#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */
+#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */
+
+/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */
+#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */
+#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */
+
+#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */
+#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */
+
+/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
+
+/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
+
+
+/*@}*/ /* end of group MemSysCtl_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup PwrModCtl_Type Power Mode Control Registers
+ \brief Type definitions for the Power Mode Control Registers (PWRMODCTL)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Power Mode Control Registers (PWRMODCTL).
+ */
+typedef struct
+{
+ __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */
+ __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */
+} PwrModCtl_Type;
+
+/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
+
+/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
+
+/*@}*/ /* end of group PwrModCtl_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup EWIC_Type External Wakeup Interrupt Controller Registers
+ \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
+ @{
+ */
+
+/**
+ \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
+ */
+typedef struct
+{
+ __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */
+ uint32_t RESERVED0[31U];
+ __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */
+ __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */
+} EWIC_Type;
+
+/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */
+#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */
+#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */
+
+#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */
+#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */
+
+#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */
+#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */
+#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */
+#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */
+
+#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */
+#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */
+
+#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */
+#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */
+#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */
+#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */
+
+/*@}*/ /* end of group EWIC_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Error Banking Registers (ERRBNK)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Error Banking Registers (ERRBNK).
+ */
+typedef struct
+{
+ __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */
+ __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */
+ __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */
+ uint32_t RESERVED1[2U];
+ __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */
+} ErrBnk_Type;
+
+/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */
+#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */
+#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */
+
+#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */
+#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */
+
+#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */
+#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */
+
+#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */
+#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */
+
+#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */
+#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */
+
+/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */
+#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */
+#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */
+
+#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */
+#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */
+
+#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */
+#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */
+
+#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */
+#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */
+
+#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */
+#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */
+#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */
+#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */
+
+#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */
+#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */
+
+#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */
+#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */
+
+#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */
+#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */
+
+#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */
+#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */
+
+#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */
+#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */
+#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */
+#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */
+
+#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */
+#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */
+
+#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */
+#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */
+
+#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */
+#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */
+
+#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */
+#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */
+
+#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */
+#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */
+#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */
+#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */
+
+#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */
+#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */
+
+#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */
+#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */
+
+#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */
+#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */
+
+#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */
+#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */
+
+#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */
+#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */
+
+#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */
+#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */
+#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */
+#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */
+
+#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */
+#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */
+
+#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */
+#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */
+
+#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */
+#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */
+
+#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */
+#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */
+
+#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */
+#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */
+
+#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */
+#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */
+
+/*@}*/ /* end of group ErrBnk_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
+ \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
+ */
+typedef struct
+{
+ __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */
+ __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */
+} PrcCfgInf_Type;
+
+/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */
+
+/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */
+
+/*@}*/ /* end of group PrcCfgInf_Type */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[3];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/** \brief PMU Authentication Status Register Definitions */
+
+#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
+
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */
+ #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */
+ #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */
+ #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */
+ #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */
+ #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */
+ #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */
+ #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */
+ #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
+ \brief Register alias definitions for backwards compatibility.
+ @{
+ */
+
+/*@} */
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+/**
+ \brief Cortex-M85 PMU events
+ \note Architectural PMU events can be found in pmu_armv8.h
+*/
+
+#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */
+#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */
+#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */
+#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */
+#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */
+#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */
+#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */
+#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */
+#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */
+#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */
+#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */
+#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */
+#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
+#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
+#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
+#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */
+#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */
+#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */
+#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
+#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+/* ################### PAC Key functions ########################### */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+#include "pac_armv81.h"
+#endif
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM85_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h
new file mode 100644
index 0000000000..d86c8d3857
--- /dev/null
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h
@@ -0,0 +1,3592 @@
+/**************************************************************************//**
+ * @file core_starmc1.h
+ * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File
+ * @version V1.0.2
+ * @date 07. April 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited.
+ * Copyright (c) 2018-2022 Arm China.
+ * All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_STAR_H_GENERIC
+#define __CORE_STAR_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup STAR-MC1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* Macro Define for STAR-MC1 */
+#define __STAR_MC (1U) /*!< STAR-MC Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_STAR_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_STAR_H_DEPENDANT
+#define __CORE_STAR_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __STAR_REV
+ #define __STAR_REV 0x0000U
+ #warning "__STAR_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group STAR-MC1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for STAR-MC1 processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED_ADD1[21U];
+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
+ uint32_t RESERVED3[69U];
+ __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+typedef struct
+{
+ __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */
+}EMSS_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */
+#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */
+
+#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */
+#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */
+
+
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache line Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */
+#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */
+
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean line by Set-way Register Definitions */
+#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */
+#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */
+
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */
+#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */
+
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* ArmChina: Implementation Defined */
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */
+#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */
+
+#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */
+#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */
+
+#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */
+#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */
+
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses including
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/**
+ \brief Software Reset
+ \details Initiates a system reset request to reset the CPU.
+ */
+__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses including
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
+ SCB_AIRCR_SYSRESETREQ_Msk );
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+#endif
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_STAR_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h
new file mode 100644
index 0000000000..854b60a204
--- /dev/null
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h
@@ -0,0 +1,206 @@
+/******************************************************************************
+ * @file pac_armv81.h
+ * @brief CMSIS PAC key functions for Armv8.1-M PAC extension
+ * @version V1.0.0
+ * @date 23. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef PAC_ARMV81_H
+#define PAC_ARMV81_H
+
+
+/* ################### PAC Key functions ########################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
+ \brief Functions that access the PAC keys.
+ @{
+ */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+
+/**
+ \brief read the PAC key used for privileged mode
+ \details Reads the PAC key stored in the PAC_KEY_P registers.
+ \param [out] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
+ __ASM volatile (
+ "mrs r1, pac_key_p_0\n"
+ "str r1,[%0,#0]\n"
+ "mrs r1, pac_key_p_1\n"
+ "str r1,[%0,#4]\n"
+ "mrs r1, pac_key_p_2\n"
+ "str r1,[%0,#8]\n"
+ "mrs r1, pac_key_p_3\n"
+ "str r1,[%0,#12]\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief write the PAC key used for privileged mode
+ \details writes the given PAC key to the PAC_KEY_P registers.
+ \param [in] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
+ __ASM volatile (
+ "ldr r1,[%0,#0]\n"
+ "msr pac_key_p_0, r1\n"
+ "ldr r1,[%0,#4]\n"
+ "msr pac_key_p_1, r1\n"
+ "ldr r1,[%0,#8]\n"
+ "msr pac_key_p_2, r1\n"
+ "ldr r1,[%0,#12]\n"
+ "msr pac_key_p_3, r1\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief read the PAC key used for unprivileged mode
+ \details Reads the PAC key stored in the PAC_KEY_U registers.
+ \param [out] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
+ __ASM volatile (
+ "mrs r1, pac_key_u_0\n"
+ "str r1,[%0,#0]\n"
+ "mrs r1, pac_key_u_1\n"
+ "str r1,[%0,#4]\n"
+ "mrs r1, pac_key_u_2\n"
+ "str r1,[%0,#8]\n"
+ "mrs r1, pac_key_u_3\n"
+ "str r1,[%0,#12]\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief write the PAC key used for unprivileged mode
+ \details writes the given PAC key to the PAC_KEY_U registers.
+ \param [in] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
+ __ASM volatile (
+ "ldr r1,[%0,#0]\n"
+ "msr pac_key_u_0, r1\n"
+ "ldr r1,[%0,#4]\n"
+ "msr pac_key_u_1, r1\n"
+ "ldr r1,[%0,#8]\n"
+ "msr pac_key_u_2, r1\n"
+ "ldr r1,[%0,#12]\n"
+ "msr pac_key_u_3, r1\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+
+/**
+ \brief read the PAC key used for privileged mode (non-secure)
+ \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
+ \param [out] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
+ __ASM volatile (
+ "mrs r1, pac_key_p_0_ns\n"
+ "str r1,[%0,#0]\n"
+ "mrs r1, pac_key_p_1_ns\n"
+ "str r1,[%0,#4]\n"
+ "mrs r1, pac_key_p_2_ns\n"
+ "str r1,[%0,#8]\n"
+ "mrs r1, pac_key_p_3_ns\n"
+ "str r1,[%0,#12]\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief write the PAC key used for privileged mode (non-secure)
+ \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
+ \param [in] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
+ __ASM volatile (
+ "ldr r1,[%0,#0]\n"
+ "msr pac_key_p_0_ns, r1\n"
+ "ldr r1,[%0,#4]\n"
+ "msr pac_key_p_1_ns, r1\n"
+ "ldr r1,[%0,#8]\n"
+ "msr pac_key_p_2_ns, r1\n"
+ "ldr r1,[%0,#12]\n"
+ "msr pac_key_p_3_ns, r1\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief read the PAC key used for unprivileged mode (non-secure)
+ \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
+ \param [out] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
+ __ASM volatile (
+ "mrs r1, pac_key_u_0_ns\n"
+ "str r1,[%0,#0]\n"
+ "mrs r1, pac_key_u_1_ns\n"
+ "str r1,[%0,#4]\n"
+ "mrs r1, pac_key_u_2_ns\n"
+ "str r1,[%0,#8]\n"
+ "mrs r1, pac_key_u_3_ns\n"
+ "str r1,[%0,#12]\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+/**
+ \brief write the PAC key used for unprivileged mode (non-secure)
+ \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
+ \param [in] pPacKey 128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
+ __ASM volatile (
+ "ldr r1,[%0,#0]\n"
+ "msr pac_key_u_0_ns, r1\n"
+ "ldr r1,[%0,#4]\n"
+ "msr pac_key_u_1_ns, r1\n"
+ "ldr r1,[%0,#8]\n"
+ "msr pac_key_u_2_ns, r1\n"
+ "ldr r1,[%0,#12]\n"
+ "msr pac_key_u_3_ns, r1\n"
+ : : "r" (pPacKey) : "memory", "r1"
+ );
+}
+
+#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
+
+#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
+
+/*@} end of CMSIS_Core_PacKeyFunctions */
+
+
+#endif /* PAC_ARMV81_H */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/bsp_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/bsp_api.h
index c3fd642f1e..9148440c8a 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/bsp_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/bsp_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_ioport_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_ioport_api.h
index 5983dcba0f..3ebc3aaa83 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_ioport_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_ioport_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -16,8 +16,7 @@
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
+ **********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
@@ -70,6 +69,12 @@ typedef enum e_ioport_peripheral
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as an AGT peripheral pin */
+ IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as an AGT peripheral pin */
+ IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@@ -119,6 +124,9 @@ typedef enum e_ioport_peripheral
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a CEU peripheral pin */
+ IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@@ -175,24 +183,14 @@ typedef enum e_ioport_peripheral
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as a MIPI peripheral pin */
+ IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as a ULPT peripheral pin */
+ IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
} ioport_peripheral_t;
-/* DEPRECATED Superset of Ethernet channels. */
-typedef enum e_ioport_eth_ch
-{
- IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
- IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
- IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
-} ioport_ethernet_channel_t;
-
-/* DEPRECATED Superset of Ethernet PHY modes. */
-typedef enum e_ioport_eth_mode
-{
- IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
- IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII
- IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
-} ioport_ethernet_mode_t;
-
/** Options to configure pin functions */
typedef enum e_ioport_cfg_options
{
@@ -294,15 +292,6 @@ typedef struct st_ioport_api
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
- /* DEPRECATED Configure the PHY mode of the Ethernet channels.
- * @par Implemented as
- * - @ref R_IOPORT_EthernetModeCfg()
- * @param[in] channel Channel configuration will be set for.
- * @param[in] mode PHY mode to set the channel to.
- */
- fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
- ioport_ethernet_mode_t mode);
-
/** Read level of a pin.
* @par Implemented as
* - @ref R_IOPORT_PinRead()
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_transfer_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_transfer_api.h
index 83e8f0a862..383b828d42 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_transfer_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_transfer_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -213,7 +213,8 @@ typedef struct st_transfer_info
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
- };
+ } transfer_settings_word_b;
+
uint32_t transfer_settings_word;
};
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_uart_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_uart_api.h
index 14e7ee445c..779af1e801 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_uart_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_uart_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_common_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_common_api.h
index 478b41a5f3..42a0133f9c 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_common_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_common_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -57,8 +57,11 @@
#endif
/** FSP Header and Footer definitions */
-#define FSP_HEADER FSP_CPP_HEADER
-#define FSP_FOOTER FSP_CPP_FOOTER
+#define FSP_HEADER FSP_CPP_HEADER
+#define FSP_FOOTER FSP_CPP_FOOTER
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
@@ -153,6 +156,9 @@ typedef enum e_fsp_err
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
+ /* Start of IIRFA Specific */
+ FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity.
+
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
@@ -187,6 +193,10 @@ typedef enum e_fsp_err
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
+ /* Start of IIRFA specific */
+ FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected
+ FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected
+
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
@@ -287,6 +297,17 @@ typedef enum e_fsp_err
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
+ FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
+ FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
+ FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
+ FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
+ FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
+ FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
+ FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
+ FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
+ FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
+ FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
+
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
@@ -361,4 +382,7 @@ typedef enum e_fsp_err
* Function prototypes
**********************************************************************************************************************/
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_features.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_features.h
index 09bd6b7f3e..13aaec26e4 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_features.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_features.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -44,6 +44,9 @@
* @{
**********************************************************************************************************************/
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
@@ -118,6 +121,7 @@ typedef enum e_fsp_ip
FSP_IP_TFU = 74, ///< Trigonometric Function Unit
FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
FSP_IP_CANFD = 76, ///< CAN-FD
+ FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
@@ -285,10 +289,16 @@ typedef enum e_fsp_signal
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
+ FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A
+ FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B
+ FSP_SIGNAL_ULPT_INT, ///< ULPT INT
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_version.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_version.h
index e8b2bfc502..9b158265a0 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_version.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_version.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -19,41 +19,45 @@
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
-#define FSP_VERSION_H
+ #define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
-#include "bsp_api.h"
+ #include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
-#define FSP_VERSION_MAJOR (3U)
+ #define FSP_VERSION_MAJOR (4U)
/** FSP pack minor version. */
-#define FSP_VERSION_MINOR (5U)
+ #define FSP_VERSION_MINOR (4U)
/** FSP pack patch version. */
-#define FSP_VERSION_PATCH (0U)
+ #define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
-#define FSP_VERSION_BUILD (0U)
+ #define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
-#define FSP_VERSION_STRING ("3.5.0")
+ #define FSP_VERSION_STRING ("4.4.0")
/** Unique FSP version ID. */
-#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.5.0")
+ #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.4.0")
/**********************************************************************************************************************
* Typedef definitions
@@ -65,16 +69,22 @@ typedef union st_fsp_pack_version
/** Version id */
uint32_t version_id;
- /** Code version parameters, little endian order. */
- struct
+ /**
+ * Code version parameters, little endian order.
+ */
+ struct version_id_b_s
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
- };
+ } version_id_b;
} fsp_pack_version_t;
/** @} */
+ #ifdef __cplusplus
+}
+ #endif
+
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_ioport.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_ioport.h
index 9e1861cde8..b46cbf72b5 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_ioport.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_ioport.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -345,9 +345,6 @@ fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
-fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
- ioport_ethernet_channel_t channel,
- ioport_ethernet_mode_t mode);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_sci_uart.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_sci_uart.h
index 520240450a..1cbbeb7d78 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_sci_uart.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_sci_uart.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -107,11 +107,11 @@ typedef enum e_sci_uart_rx_fifo_trigger
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
-typedef enum e_sci_uart_start_bit_detect
+typedef enum e_sci_uart_start_bit_t
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
-} sci_uart_start_bit_detect_t;
+} sci_uart_start_bit_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
@@ -120,6 +120,20 @@ typedef enum e_sci_uart_noise_cancellation
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
} sci_uart_noise_cancellation_t;
+/** RS-485 Enable/Disable. */
+typedef enum e_sci_uart_rs485_enable
+{
+ SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
+ SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
+} sci_uart_rs485_enable_t;
+
+/** The polarity of the RS-485 DE signal. */
+typedef enum e_sci_uart_rs485_de_polarity
+{
+ SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
+ SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
+} sci_uart_rs485_de_polarity_t;
+
/** Register settings to acheive a desired baud rate and modulation duty. */
typedef struct st_baud_setting_t
{
@@ -136,23 +150,32 @@ typedef struct st_baud_setting_t
uint8_t : 1;
uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint8_t : 1;
- };
+ } semr_baudrate_bits_b;
};
uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint8_t brr; ///< Bit Rate Register setting
uint8_t mddr; ///< Modulation Duty Register setting
} baud_setting_t;
+/** Configuration settings for controlling the DE signal for RS-485. */
+typedef struct st_sci_uart_rs485_setting
+{
+ sci_uart_rs485_enable_t enable; ///< Enable the DE signal.
+ sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
+ bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin.
+} sci_uart_rs485_setting_t;
+
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
- sci_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
+ sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin
+ sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
new file mode 100644
index 0000000000..19ea67b3cf
--- /dev/null
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
@@ -0,0 +1,28147 @@
+/*
+ * This software is supplied by Renesas Electronics Corporation and is only intended for
+ * use with Renesas products. No other uses are authorized. This software is owned by
+ * Renesas Electronics Corporation and is protected under all applicable laws, including
+ * copyright laws.
+ *
+ * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT
+ * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED
+ * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * Renesas reserves the right, without notice, to make changes to this software and to
+ * discontinue the availability of this software. By using this software, you agree to
+ * the additional terms and conditions found by accessing the following link:
+ * http://www.renesas.com/disclaimer
+ *
+ *
+ * @file ./out/R7FA6M5BH.h
+ * @brief CMSIS HeaderFile
+ * @version 1.10.08
+ */
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup R7FA6M5BH
+ * @{
+ */
+
+#ifndef R7FA6M5BH_H
+ #define R7FA6M5BH_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
+ #define __CM33_REV 0x0004U /*!< CM33 Core Revision */
+ #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+ #define __MPU_PRESENT 1 /*!< MPU present */
+ #define __FPU_PRESENT 1 /*!< FPU present */
+ #define __FPU_DP 0 /*!< Double Precision FPU */
+ #define __DSP_PRESENT 1 /*!< DSP extension present */
+ #define __SAUREGION_PRESENT 0 /*!< SAU region present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+ #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
+ #include "system.h" /*!< R7FA6M5BH System */
+
+ #ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+ #endif
+ #ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+ #endif
+ #ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+ #endif
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+ #if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+ #elif defined(__ICCARM__)
+ #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+ #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+ #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_BUS_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
+
+ struct
+ {
+ __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
+ uint16_t : 2;
+ __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
+ uint16_t : 4;
+ __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
+ __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
+ uint16_t : 5;
+ __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
+ } MOD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+ * is valid only when the PWENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+ * is valid only when the PRENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
+ uint32_t : 3;
+ __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
+ uint32_t : 3;
+ } WCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
+ uint32_t : 2;
+ __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
+ uint32_t : 1;
+ } WCR2_b;
+ };
+ __IM uint32_t RESERVED1;
+} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
+
+ struct
+ {
+ __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
+ uint16_t : 3;
+ __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
+ uint16_t : 2;
+ __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
+ uint16_t : 3;
+ __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
+ uint16_t : 3;
+ } CR_b;
+ };
+ __IM uint16_t RESERVED1[3];
+
+ union
+ {
+ __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
+
+ struct
+ {
+ __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
+ uint16_t : 4;
+ __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
+ uint16_t : 4;
+ } REC_b;
+ };
+ __IM uint16_t RESERVED2[2];
+} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */
+
+ struct
+ {
+ __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */
+ uint8_t : 3;
+ __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */
+ uint8_t : 2;
+ } SDCCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */
+
+ struct
+ {
+ __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */
+ uint8_t : 7;
+ } SDCMOD_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */
+
+ struct
+ {
+ __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */
+ uint8_t : 7;
+ } SDAMOD_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint32_t RESERVED1[3];
+
+ union
+ {
+ __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */
+
+ struct
+ {
+ __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */
+ uint8_t : 7;
+ } SDSELF_b;
+ };
+ __IM uint8_t RESERVED2;
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */
+
+ struct
+ {
+ __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */
+ __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
+ * Setting. ( REFW+1 Cycles ) */
+ } SDRFCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */
+
+ struct
+ {
+ __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */
+ uint8_t : 7;
+ } SDRFEN_b;
+ };
+ __IM uint8_t RESERVED4;
+ __IM uint32_t RESERVED5[2];
+
+ union
+ {
+ __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */
+
+ struct
+ {
+ __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */
+ uint8_t : 7;
+ } SDICR_b;
+ };
+ __IM uint8_t RESERVED6;
+ __IM uint16_t RESERVED7;
+
+ union
+ {
+ __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */
+
+ struct
+ {
+ __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */
+ __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */
+ __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
+ * ) */
+ uint16_t : 5;
+ } SDIR_b;
+ };
+ __IM uint16_t RESERVED8;
+ __IM uint32_t RESERVED9[6];
+
+ union
+ {
+ __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */
+
+ struct
+ {
+ __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */
+ uint8_t : 6;
+ } SDADR_b;
+ };
+ __IM uint8_t RESERVED10;
+ __IM uint16_t RESERVED11;
+
+ union
+ {
+ __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */
+
+ struct
+ {
+ __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */
+ uint32_t : 5;
+ __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */
+ __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */
+ __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */
+ uint32_t : 2;
+ __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */
+ uint32_t : 13;
+ } SDTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */
+
+ struct
+ {
+ __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
+ * set command is issued. */
+ uint16_t : 1;
+ } SDMOD_b;
+ };
+ __IM uint16_t RESERVED12;
+ __IM uint32_t RESERVED13;
+
+ union
+ {
+ __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */
+
+ struct
+ {
+ __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */
+ uint8_t : 2;
+ __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */
+ __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */
+ uint8_t : 3;
+ } SDSR_b;
+ };
+ __IM uint8_t RESERVED14;
+ __IM uint16_t RESERVED15;
+} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */
+
+/**
+ * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
+
+ struct
+ {
+ __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+ * an error address. */
+ } ADD_b;
+ };
+
+ union
+ {
+ __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */
+
+ struct
+ {
+ __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */
+ uint8_t : 6;
+ __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */
+ } STAT_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[2];
+} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */
+
+ struct
+ {
+ uint16_t : 15;
+ __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */
+ } CNT_b;
+ };
+ __IM uint16_t RESERVED;
+} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */
+ uint16_t : 10;
+ } CNT_b;
+ };
+ __IM uint16_t RESERVED;
+} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */
+ __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */
+ __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */
+ __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */
+ } NCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */
+
+ struct
+ {
+ __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */
+ __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */
+ __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */
+ uint32_t : 4;
+ __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */
+ __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */
+ __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */
+ __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */
+ __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */
+ __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */
+ __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */
+ __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */
+ __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */
+ __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */
+ __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */
+ __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+ * enable */
+ uint32_t : 1;
+ __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */
+ __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */
+ __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */
+ __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */
+ __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */
+ __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */
+ __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */
+ __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */
+ __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */
+ } CTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */
+
+ struct
+ {
+ __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */
+ __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */
+ __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */
+ __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */
+ __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */
+ __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */
+ __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */
+ __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */
+ __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */
+ uint32_t : 7;
+ __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */
+ __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */
+ } STS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */
+
+ struct
+ {
+ __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */
+ __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */
+ __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */
+ __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */
+ __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */
+ __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */
+ __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */
+ __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */
+ __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */
+ __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */
+ __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */
+ __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */
+ __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */
+ __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */
+ __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */
+ uint32_t : 1;
+ __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */
+ uint32_t : 1;
+ } ERFL_b;
+ };
+} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */
+ __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */
+ uint32_t : 3;
+ __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */
+ uint32_t : 4;
+ __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */
+ uint32_t : 4;
+ } DCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */
+ uint32_t : 5;
+ __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */
+ __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */
+ __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */
+ uint32_t : 5;
+ __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */
+ __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */
+ __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */
+ __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */
+ uint32_t : 1;
+ __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */
+ __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */
+ __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */
+ __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */
+ } FDCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */
+
+ struct
+ {
+ __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */
+ __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */
+ uint32_t : 30;
+ } FDCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */
+ __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */
+ __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */
+ uint32_t : 5;
+ __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */
+ __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */
+ __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */
+
+ struct
+ {
+ __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */
+ uint32_t : 3;
+ __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */
+ uint32_t : 4;
+ } FDCRC_b;
+ };
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */
+
+ struct
+ {
+ __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */
+ uint32_t : 7;
+ __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */
+ uint32_t : 23;
+ } BLCT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */
+
+ struct
+ {
+ uint32_t : 3;
+ __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */
+ } BLSTS_b;
+ };
+} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */
+ __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */
+ __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */
+ __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */
+ __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */
+ __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */
+ __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */
+ } M_b;
+ };
+
+ union
+ {
+ __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */
+ __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination
+ * 0 */
+ __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination
+ * 1 */
+ __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination
+ * 2 */
+ __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */
+ __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+ * Pointer */
+ uint32_t : 2;
+ __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */
+ __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */
+ } P0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */
+ uint32_t : 18;
+ } P1_b;
+ };
+} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */
+
+ struct
+ {
+ __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */
+ __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */
+ uint32_t : 5;
+ __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */
+ __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */
+ } ACC0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */
+
+ struct
+ {
+ __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */
+ __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */
+ uint32_t : 14;
+ } ACC1_b;
+ };
+} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */
+
+ struct
+ {
+ __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */
+ uint32_t : 1;
+ __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */
+ __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */
+
+ struct
+ {
+ __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */
+ uint32_t : 12;
+ __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */
+ uint32_t : 6;
+ __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */
+
+ struct
+ {
+ __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */
+ } DF_b[64];
+ };
+ __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */
+
+ struct
+ {
+ __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */
+ uint32_t : 1;
+ __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */
+ __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */
+
+ struct
+ {
+ __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */
+ uint32_t : 12;
+ __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */
+ uint32_t : 6;
+ __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */
+
+ struct
+ {
+ __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */
+ } DF_b[64];
+ };
+ __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
+
+ struct
+ {
+ __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
+ uint32_t : 1;
+ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
+ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
+
+ struct
+ {
+ __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
+ uint32_t : 12;
+ __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
+
+ struct
+ {
+ __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
+ uint32_t : 6;
+ __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
+
+ struct
+ {
+ __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
+ } DF_b[64];
+ };
+ __IM uint32_t RESERVED[13];
+} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */
+
+ struct
+ {
+ __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */
+ uint32_t : 1;
+ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */
+ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */
+
+ struct
+ {
+ __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */
+ uint32_t : 12;
+ __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */
+
+ struct
+ {
+ __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */
+ uint32_t : 6;
+ __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */
+ } FDCTR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */
+
+ struct
+ {
+ __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */
+ } DF_b[64];
+ };
+ __IM uint32_t RESERVED[13];
+} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */
+
+ struct
+ {
+ __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */
+ uint8_t : 5;
+ __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */
+ __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */
+ } BY_b;
+ };
+ __IM uint8_t RESERVED;
+} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */
+
+/**
+ * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */
+ uint16_t : 7;
+ } HA_b;
+ };
+ __IM uint16_t RESERVED;
+} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */
+
+ struct
+ {
+ __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
+ * Address = { SVA9,SVA8,SVA[7:0] } */
+ } L_b;
+ };
+
+ union
+ {
+ __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */
+
+ struct
+ {
+ __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */
+ __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */
+ __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */
+ uint8_t : 5;
+ } U_b;
+ };
+} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */
+
+/**
+ * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */
+
+ struct
+ {
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */
+ __IOM uint16_t RP : 1; /*!< [1..1] Read protection */
+ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */
+ uint16_t : 13;
+ } C_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */
+
+ struct
+ {
+ __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE:
+ * The low-order 2 bits are fixed to 0. */
+ } S_b;
+ };
+
+ union
+ {
+ __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */
+
+ struct
+ {
+ __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region
+ * end, for use in region determination.NOTE: The low-order
+ * 2 bits are fixed to 1. */
+ } E_b;
+ };
+ __IM uint32_t RESERVED1;
+} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */
+
+ struct
+ {
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */
+ __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */
+ uint16_t : 6;
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+ * stored. */
+ } CTL_b;
+ };
+ __IM uint16_t RESERVED;
+ __IM uint32_t RESERVED1[63];
+ __IM uint16_t RESERVED2;
+
+ union
+ {
+ __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */
+
+ struct
+ {
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+ * stored. */
+ } PT_b;
+ };
+ __IM uint32_t RESERVED3[63];
+ __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */
+} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */
+
+ struct
+ {
+ uint16_t : 2;
+ __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */
+ __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */
+ __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */
+ __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */
+ __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */
+ __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */
+ uint16_t : 4;
+ __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */
+ __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
+ * is read as 1. The write value should be 1.) */
+ __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */
+ __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */
+ } R_b;
+ };
+ __IM uint16_t RESERVED;
+} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+ * stored. */
+ } OAD_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */
+
+ struct
+ {
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */
+ uint16_t : 7;
+ __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */
+ uint16_t : 7;
+ } CTL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */
+
+ struct
+ {
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+ * stored. */
+ } PT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */
+
+ struct
+ {
+ __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
+ * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
+ * The low-order 2 bits are fixed to 0. */
+ } SA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */
+
+ struct
+ {
+ __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
+ * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
+ * The low-order 2 bits are fixed to 1. */
+ } EA_b;
+ };
+} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
+ */
+typedef struct
+{
+ union
+ {
+ union
+ {
+ __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */
+
+ struct
+ {
+ __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */
+ __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */
+ __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */
+ uint32_t : 1;
+ __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */
+ __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */
+ __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
+ uint32_t : 3;
+ __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
+ __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */
+ __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */
+ __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */
+ __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */
+ uint32_t : 7;
+ __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
+ * function. For individual pin functions, see the MPC table */
+ uint32_t : 3;
+ } PmnPFS_b;
+ };
+
+ struct
+ {
+ union
+ {
+ struct
+ {
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */
+
+ struct
+ {
+ __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */
+ __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */
+ __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */
+ uint16_t : 1;
+ __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */
+ __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */
+ __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
+ uint16_t : 3;
+ __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
+ __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */
+ __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */
+ __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */
+ } PmnPFS_HA_b;
+ };
+ };
+
+ struct
+ {
+ __IM uint16_t RESERVED1;
+ __IM uint8_t RESERVED2;
+
+ union
+ {
+ __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */
+
+ struct
+ {
+ __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */
+ __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */
+ __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */
+ uint8_t : 1;
+ __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */
+ __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */
+ __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
+ uint8_t : 1;
+ } PmnPFS_BY_b;
+ };
+ };
+ };
+ };
+ };
+} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_PFS_PORT [PORT] (Port [0..14])
+ */
+typedef struct
+{
+ __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */
+} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
+ */
+typedef struct
+{
+ __IM uint8_t RESERVED[389];
+
+ union
+ {
+ __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */
+
+ struct
+ {
+ __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */
+ uint8_t : 7;
+ } VL1SEL_b;
+ };
+} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */
+
+/**
+ * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
+ */
+typedef struct
+{
+ __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */
+} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */
+
+/**
+ * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */
+
+ struct
+ {
+ __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */
+ __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */
+ uint8_t : 1;
+ __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */
+ uint8_t : 1;
+ __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */
+ } RTCCR_b;
+ };
+ __IM uint8_t RESERVED;
+} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */
+
+/**
+ * @brief R_RTC_CP [CP] (Capture registers)
+ */
+typedef struct
+{
+ __IM uint8_t RESERVED[2];
+
+ union
+ {
+ union
+ {
+ __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */
+
+ struct
+ {
+ __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of
+ * seconds */
+ __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
+ * seconds */
+ uint8_t : 1;
+ } RSEC_b;
+ };
+
+ union
+ {
+ __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */
+
+ struct
+ {
+ __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
+ * value when a time capture event is detected. */
+ } BCNT0_b;
+ };
+ };
+ __IM uint8_t RESERVED1;
+
+ union
+ {
+ union
+ {
+ __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */
+
+ struct
+ {
+ __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+ * minutes */
+ __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
+ * minutes */
+ uint8_t : 1;
+ } RMIN_b;
+ };
+
+ union
+ {
+ __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */
+
+ struct
+ {
+ __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
+ * value when a time capture event is detected. */
+ } BCNT1_b;
+ };
+ };
+ __IM uint8_t RESERVED2;
+
+ union
+ {
+ union
+ {
+ __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */
+
+ struct
+ {
+ __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+ * minutes */
+ __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
+ * minutes */
+ __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */
+ uint8_t : 1;
+ } RHR_b;
+ };
+
+ union
+ {
+ __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */
+
+ struct
+ {
+ __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
+ * value when a time capture event is detected. */
+ } BCNT2_b;
+ };
+ };
+ __IM uint8_t RESERVED3[3];
+
+ union
+ {
+ union
+ {
+ __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */
+
+ struct
+ {
+ __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */
+ __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */
+ uint8_t : 2;
+ } RDAY_b;
+ };
+
+ union
+ {
+ __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */
+
+ struct
+ {
+ __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
+ * value when a time capture event is detected. */
+ } BCNT3_b;
+ };
+ };
+ __IM uint8_t RESERVED4;
+
+ union
+ {
+ __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */
+
+ struct
+ {
+ __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */
+ __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of
+ * months */
+ uint8_t : 3;
+ } RMON_b;
+ };
+ __IM uint8_t RESERVED5[3];
+} R_RTC_CP_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
+
+ struct
+ {
+ __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
+ uint16_t : 2;
+ __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
+ uint16_t : 4;
+ __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
+ __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
+ uint16_t : 5;
+ __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
+ } MOD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+ * is valid only when the PWENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+ * is valid only when the PRENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
+ uint32_t : 3;
+ __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
+ uint32_t : 3;
+ } WCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
+ uint32_t : 2;
+ __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
+ uint32_t : 1;
+ } WCR2_b;
+ };
+ __IM uint32_t RESERVED1;
+} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
+
+ struct
+ {
+ __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
+ uint16_t : 3;
+ __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
+ uint16_t : 2;
+ __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
+ uint16_t : 3;
+ __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
+ uint16_t : 3;
+ } CR_b;
+ };
+ __IM uint16_t RESERVED1[3];
+
+ union
+ {
+ __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
+
+ struct
+ {
+ __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
+ uint16_t : 4;
+ __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
+ uint16_t : 4;
+ } REC_b;
+ };
+ __IM uint16_t RESERVED2[2];
+} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
+
+ struct
+ {
+ __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+ * an error address. */
+ } ADD_b;
+ };
+
+ union
+ {
+ __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */
+
+ struct
+ {
+ __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */
+ uint8_t : 7;
+ } ERRRW_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[2];
+} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */
+
+ struct
+ {
+ __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs,
+ * It stores an error address. */
+ } TZFADD_b;
+ };
+
+ union
+ {
+ __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */
+
+ struct
+ {
+ __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the
+ * time of the error */
+ uint8_t : 7;
+ } TZFERRRW_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[2];
+} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */
+ __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */
+ uint16_t : 6;
+ } E_b;
+ };
+
+ union
+ {
+ __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */
+
+ struct
+ {
+ __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */
+ } N_b;
+ };
+} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows
+ * clearing the transaction counter to 0. */
+ __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction
+ * counter function. */
+ uint16_t : 6;
+ } E_b;
+ };
+
+ union
+ {
+ __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */
+
+ struct
+ {
+ __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number
+ * of total packets (number of transactions) to be received
+ * by the relevant PIPE.When read from: When TRENB = 0: Indicate
+ * the specified number of transactions.When TRENB = 1: Indicate
+ * the number of currently counted transactions. */
+ } N_b;
+ };
+} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */
+
+ struct
+ {
+ __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */
+ __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */
+ __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */
+ uint8_t : 1;
+ __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */
+ __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */
+ __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */
+ __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */
+ } AGTCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */
+
+ struct
+ {
+ __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */
+ __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */
+ __IOM uint8_t TCK : 3; /*!< [6..4] Count source */
+ uint8_t : 1;
+ } AGTMR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */
+
+ struct
+ {
+ __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+ * ratio */
+ uint8_t : 4;
+ __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */
+ } AGTMR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */
+
+ struct
+ {
+ __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */
+ uint8_t : 2;
+ __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
+ uint8_t : 3;
+ } AGTIOSEL_ALT_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */
+
+ struct
+ {
+ __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+ * mode. */
+ uint8_t : 1;
+ __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */
+ uint8_t : 1;
+ __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */
+ __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */
+ } AGTIOC_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */
+
+ struct
+ {
+ uint8_t : 2;
+ __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */
+ uint8_t : 5;
+ } AGTISR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */
+
+ struct
+ {
+ __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
+ __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */
+ __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */
+ uint8_t : 1;
+ __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
+ __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */
+ __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */
+ uint8_t : 1;
+ } AGTCMSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */
+
+ struct
+ {
+ __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */
+ uint8_t : 2;
+ __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
+ uint8_t : 3;
+ } AGTIOSEL_b;
+ };
+} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */
+
+ struct
+ {
+ __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCRn register, the 16-bit
+ * counter is forcibly stopped and set to FFFFH. */
+ } AGT_b;
+ };
+
+ union
+ {
+ __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */
+
+ struct
+ {
+ __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCRn register, set to
+ * FFFFH */
+ } AGTCMA_b;
+ };
+
+ union
+ {
+ __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */
+
+ struct
+ {
+ __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCR register, set to
+ * FFFFH */
+ } AGTCMB_b;
+ };
+ __IM uint16_t RESERVED;
+ __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */
+} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */
+
+ struct
+ {
+ __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCRn register, the 16-bit
+ * counter is forcibly stopped and set to FFFFH. */
+ } AGT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */
+
+ struct
+ {
+ __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCRn register, set to
+ * FFFFH */
+ } AGTCMA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */
+
+ struct
+ {
+ __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCR register, set to
+ * FFFFH */
+ } AGTCMB_b;
+ };
+ __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */
+} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================ R_ADC0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A/D Converter (R_ADC0)
+ */
+
+typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */
+{
+ union
+ {
+ __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */
+
+ struct
+ {
+ __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
+ * input channel for double triggered operation. The setting
+ * is only effective while double trigger mode is selected. */
+ uint16_t : 1;
+ __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */
+ __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */
+ __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */
+ __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */
+ __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */
+ uint16_t : 1;
+ __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */
+ __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */
+ __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */
+ } ADCSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */
+
+ struct
+ {
+ __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
+ * '1' while scanning. */
+ uint8_t : 6;
+ __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */
+ } ADREF_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */
+
+ struct
+ {
+ __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */
+ uint8_t : 7;
+ } ADEXREF_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */
+
+ struct
+ {
+ __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */
+ __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */
+ __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */
+ __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */
+ __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */
+ __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */
+ __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */
+ __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */
+ __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */
+ __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */
+ __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */
+ __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */
+ __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */
+ __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */
+ __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */
+ __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */
+ } ADANSA_b[2];
+ };
+
+ union
+ {
+ __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
+ * Select Register */
+
+ struct
+ {
+ __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */
+ __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */
+ } ADADS_b[2];
+ };
+
+ union
+ {
+ __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
+ * at the only setting of ADC[2:0] bits = 001b or 011b. When
+ * average mode is selected by setting the ADADC.AVEE bit
+ * to 1, do not set the addition count to three times (ADADC.ADC[2:0]
+ * = 010b) */
+ uint8_t : 4;
+ __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
+ * by setting the ADADC.AVEE bit to 0, set the addition count
+ * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
+ * can only be used with 12-bit accuracy selected. NOTE: AVEE
+ * bit is valid at the only setting of ADC[2:0] bits = 001b
+ * or 011b. When average mode is selected by setting the ADADC.AVEE
+ * bit to 1, do not set the addition count to three times
+ * (ADADC.ADC[2:0] = 010b) */
+ } ADADC_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */
+
+ struct
+ {
+ uint16_t : 1;
+ __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */
+ uint16_t : 1;
+ __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */
+ __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */
+ uint16_t : 2;
+ __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */
+ __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */
+ __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */
+ uint16_t : 2;
+ __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */
+ __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */
+ } ADCER_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */
+
+ struct
+ {
+ __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
+ * the A/D conversion start trigger for group B in group scan
+ * mode. */
+ uint16_t : 2;
+ __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
+ * start trigger in single scan mode and continuous mode.
+ * In group scan mode, the A/D conversion start trigger for
+ * group A is selected. */
+ uint16_t : 2;
+ } ADSTRGR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */
+
+ struct
+ {
+ __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
+ * Mode Select */
+ __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
+ * Mode Select */
+ uint16_t : 6;
+ __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */
+ __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */
+ __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
+ * Group B in group scan mode. */
+ __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
+ * Group B in group scan mode. */
+ uint16_t : 2;
+ __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */
+ __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */
+ } ADEXICR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */
+
+ struct
+ {
+ __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */
+ __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */
+ __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */
+ __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */
+ __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */
+ __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */
+ __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */
+ __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */
+ __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */
+ __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */
+ __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */
+ __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */
+ __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */
+ __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */
+ __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */
+ __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */
+ } ADANSB_b[2];
+ };
+
+ union
+ {
+ __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */
+
+ struct
+ {
+ __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+ * result of A/D conversion in response to the second trigger
+ * in double trigger mode. */
+ } ADDBLDR_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */
+
+ struct
+ {
+ __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+ * A/D conversion result of temperature sensor output. */
+ } ADTSDR_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */
+
+ struct
+ {
+ __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+ * A/D result of internal reference voltage. */
+ } ADOCDR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */
+
+ struct
+ {
+ __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for
+ * data determine ADCER.ADRFMT and ADCER.ADPRC. */
+ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */
+ } ADRD_RIGHT_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */
+
+ struct
+ {
+ __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
+ __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
+ * data determine ADCER.ADRFMT and ADCER.ADPRC. */
+ } ADRD_LEFT_b;
+ };
+ };
+
+ union
+ {
+ __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */
+
+ struct
+ {
+ __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for
+ * storing the result of A/D conversion. */
+ } ADDR_b[29];
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2;
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */
+
+ struct
+ {
+ __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */
+ } ADAMPOFF_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */
+
+ struct
+ {
+ __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */
+ __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */
+ uint8_t : 6;
+ } ADTSTPR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */
+
+ struct
+ {
+ __IOM uint16_t WRION : 5; /*!< [4..0] WRION */
+ uint16_t : 3;
+ __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */
+ uint16_t : 2;
+ __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */
+ } ADDDACER_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */
+
+ struct
+ {
+ __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
+ * Setting Set the sampling time (4 to 255 states) */
+ __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */
+ __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */
+ __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */
+ uint16_t : 5;
+ } ADSHCR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */
+
+ struct
+ {
+ __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
+ * only for channel. */
+ uint16_t : 1;
+ __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */
+ uint16_t : 2;
+ __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
+ * for adjustment to hardening of process. */
+ uint16_t : 1;
+ __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
+ * power save bit for A/D hard macro to hardening of process. */
+ __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
+ * bit for A/D hard macro to hardening of process. */
+ __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
+ * bit for A/D hard macro to hardening of process. */
+ } ADEXTSTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */
+
+ struct
+ {
+ __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */
+ __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
+ * amplifier test.Refreshing the pressure switch that opens
+ * for the DAC output voltage charge period when the amplifier
+ * of the S&H circuit is tested only for the channel is set. */
+ uint16_t : 1;
+ __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control
+ * bit. */
+ __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control
+ * bit */
+ uint16_t : 1;
+ __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
+ * module Details are described to the bit explanation. */
+ __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
+ * bit explanation. */
+ } ADTSTRA_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */
+
+ struct
+ {
+ __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
+ * corresponds to ADVAL 14:0 input of A/D analog module. */
+ uint16_t : 1;
+ } ADTSTRB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */
+
+ struct
+ {
+ __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
+ * analog module. */
+ uint16_t : 4;
+ __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */
+ uint16_t : 3;
+ } ADTSTRC_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */
+
+ struct
+ {
+ __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
+ * corresponds to ADVAL 16 input of A/D analog module. */
+ uint16_t : 15;
+ } ADTSTRD_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */
+
+ struct
+ {
+ __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */
+ __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */
+ __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */
+ __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */
+ __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */
+ __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */
+ uint16_t : 10;
+ } ADSWTSTR0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */
+
+ struct
+ {
+ __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */
+ __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */
+ __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */
+ __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */
+ __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */
+ __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */
+ uint16_t : 10;
+ } ADSWTSTR1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */
+
+ struct
+ {
+ __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit
+ * (ANEX0 switch) */
+ __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit
+ * (ANEX1 switch). */
+ uint16_t : 2;
+ __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */
+ __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */
+ __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */
+ uint16_t : 1;
+ __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */
+ __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */
+ __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */
+ __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */
+ __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */
+ uint16_t : 3;
+ } ADSWTSTR2_b;
+ };
+ __IM uint16_t RESERVED4;
+
+ union
+ {
+ __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */
+
+ struct
+ {
+ __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */
+ __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */
+ uint8_t : 3;
+ } ADDISCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */
+
+ struct
+ {
+ __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
+ * the pressure switch in A/D analog module is set. */
+ uint8_t : 1;
+ __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */
+ uint8_t : 1;
+ } ADSWCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */
+
+ struct
+ {
+ __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
+ * Select */
+ uint8_t : 7;
+ } ADSHMSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */
+
+ struct
+ {
+ __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */
+ uint8_t : 6;
+ } ADICR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */
+
+ struct
+ {
+ uint8_t : 1;
+ __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */
+ uint8_t : 6;
+ } ADACSR_b;
+ };
+ __IM uint8_t RESERVED5;
+
+ union
+ {
+ __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */
+
+ struct
+ {
+ __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS
+ * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
+ * set to 01b (group scan mode). If the bits are set to any
+ * other values, proper operation is not guaranteed. */
+ __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
+ * when PGS = 0.) */
+ uint16_t : 6;
+ __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */
+ uint16_t : 6;
+ __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
+ * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
+ * has been set to 1, single scan is performed continuously
+ * for group B regardless of the setting of the GBRSCN bit. */
+ } ADGSPCR_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
+ * Scan) */
+
+ struct
+ {
+ __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */
+ __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */
+ } ADGSCS_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */
+
+ struct
+ {
+ __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+ * the result of A/D conversion in response to the respective
+ * triggers during extended operation in double trigger mode. */
+ } ADDBLDRA_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */
+
+ struct
+ {
+ __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+ * the result of A/D conversion in response to the respective
+ * triggers during extended operation in double trigger mode. */
+ } ADDBLDRB_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */
+ } ADSER_b;
+ };
+ __IM uint8_t RESERVED6;
+
+ union
+ {
+ __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
+ * Control Register */
+
+ struct
+ {
+ __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */
+ uint8_t : 2;
+ __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */
+ uint8_t : 2;
+ __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
+ } ADHVREFCNT_b;
+ };
+ __IM uint8_t RESERVED7;
+
+ union
+ {
+ __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
+ * Register */
+
+ struct
+ {
+ __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination
+ * result.This bit is valid when both window A operation and
+ * window B operation are enabled. */
+ uint8_t : 3;
+ __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */
+ __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */
+ uint8_t : 2;
+ } ADWINMON_b;
+ };
+ __IM uint8_t RESERVED8;
+ __IM uint16_t RESERVED9;
+
+ union
+ {
+ __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */
+
+ struct
+ {
+ __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
+ * are valid when both window A and window B are enabled (CMPAE
+ * = 1 and CMPBE = 1). */
+ uint16_t : 7;
+ __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */
+ uint16_t : 1;
+ __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */
+ uint16_t : 1;
+ __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */
+ __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */
+ __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */
+ } ADCMPCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
+ * Select Register */
+
+ struct
+ {
+ __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */
+ __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */
+ uint8_t : 6;
+ } ADCMPANSER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
+ * Comparison Condition Setting Register */
+
+ struct
+ {
+ __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
+ * Condition Select */
+ __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
+ * Select */
+ uint8_t : 6;
+ } ADCMPLER_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */
+ __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */
+ __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */
+ __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */
+ __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */
+ __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */
+ __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */
+ __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */
+ __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */
+ __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */
+ __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */
+ __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */
+ __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */
+ __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */
+ __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */
+ __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */
+ } ADCMPANSR_b[2];
+ };
+
+ union
+ {
+ __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */
+ __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */
+ __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */
+ __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */
+ __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */
+ __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */
+ __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */
+ __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */
+ __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */
+ __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */
+ __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */
+ __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */
+ __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */
+ __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */
+ __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */
+ __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */
+ } ADCMPLR_b[2];
+ };
+
+ union
+ {
+ __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
+ * compare window A function is used. ADCMPDR0 sets the lower-side
+ * level of window A. */
+ } ADCMPDR0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
+ * compare window A function is used. ADCMPDR1 sets the upper-side
+ * level of window A.. */
+ } ADCMPDR1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */
+ __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */
+ } ADCMPSR_b[2];
+ };
+
+ union
+ {
+ __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
+ * Channel Status Register */
+
+ struct
+ {
+ __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
+ * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+ * this bit indicates the temperature sensor output comparison
+ * result. When window A operation is disabled (ADCMPCR.CMPAE
+ * = 0b), comparison conditions for CMPSTTSA are not met any
+ * time. */
+ __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
+ * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+ * this bit indicates the temperature sensor output comparison
+ * result. When window A operation is disabled (ADCMPCR.CMPAE
+ * = 0b), comparison conditions for CMPSTTSA are not met any
+ * time. */
+ uint8_t : 6;
+ } ADCMPSER_b;
+ };
+ __IM uint8_t RESERVED10;
+
+ union
+ {
+ __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that
+ * compares it on the condition of compare window B is selected. */
+ uint8_t : 1;
+ __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */
+ } ADCMPBNSR_b;
+ };
+ __IM uint8_t RESERVED11;
+
+ union
+ {
+ __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
+ * used to set the lower level of the window B. */
+ } ADWINLLB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
+ * used to set the higher level of the window B. */
+ } ADWINULB_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */
+
+ struct
+ {
+ __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows
+ * the comparative result of CH (AN000-AN027, temperature
+ * sensor, and internal reference voltage) made the object
+ * of window B relation condition. */
+ uint8_t : 7;
+ } ADCMPBSR_b;
+ };
+ __IM uint8_t RESERVED12;
+ __IM uint16_t RESERVED13;
+
+ union
+ {
+ __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF0_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF1_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF2_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF3_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF4_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF5_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF6_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF7_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF8_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF9_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF10_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF11_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF12_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF13_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF14_b;
+ };
+
+ union
+ {
+ __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */
+
+ struct
+ {
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+ * registers that sequentially store all A/D converted values.
+ * The automatic clear function is not applied to these registers. */
+ } ADBUF15_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */
+
+ struct
+ {
+ __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */
+ uint8_t : 7;
+ } ADBUFEN_b;
+ };
+ __IM uint8_t RESERVED14;
+
+ union
+ {
+ __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */
+
+ struct
+ {
+ __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of
+ * data buffer to which the next A/D converted data is transferred. */
+ __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */
+ uint8_t : 3;
+ } ADBUFPTR_b;
+ };
+ __IM uint8_t RESERVED15;
+ __IM uint32_t RESERVED16[2];
+ __IM uint8_t RESERVED17;
+
+ union
+ {
+ __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */
+
+ struct
+ {
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */
+ } ADSSTRL_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */
+
+ struct
+ {
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */
+ } ADSSTRT_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */
+
+ struct
+ {
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */
+ } ADSSTRO_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */
+
+ struct
+ {
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */
+ } ADSSTR_b[16];
+ };
+
+ union
+ {
+ __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */
+
+ struct
+ {
+ __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */
+ __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */
+ __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */
+ __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */
+ uint16_t : 12;
+ } ADANIM_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */
+
+ struct
+ {
+ uint8_t : 6;
+ __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */
+ __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */
+ } ADCALEXE_b;
+ };
+ __IM uint8_t RESERVED18;
+
+ union
+ {
+ __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */
+ __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */
+ __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */
+ __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */
+ uint8_t : 2;
+ __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
+ } VREFAMPCNT_b;
+ };
+ __IM uint8_t RESERVED19;
+ __IM uint16_t RESERVED20;
+
+ union
+ {
+ __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */
+
+ struct
+ {
+ __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */
+ } ADRD_b;
+ };
+
+ union
+ {
+ __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */
+
+ struct
+ {
+ __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
+ uint8_t : 6;
+ } ADRST_b;
+ };
+ __IM uint8_t RESERVED21;
+ __IM uint32_t RESERVED22[41];
+
+ union
+ {
+ __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */
+
+ struct
+ {
+ __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */
+ __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */
+ __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */
+ __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */
+ __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */
+ __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */
+ __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */
+ __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */
+ __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */
+ __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */
+ __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */
+ __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */
+ __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */
+ __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */
+ __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */
+ __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */
+ } ADPGACR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
+ * Register 0 */
+
+ struct
+ {
+ __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
+ * b) when the shingle end is input and each PGA P000 is set.
+ * When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
+ * sets the gain magnification when the differential motion
+ * is input by the combination with ADPGSDCR0.P000DG 1:0. */
+ __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
+ * b) when the shingle end is input and each PGA P001 is set.
+ * When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
+ * sets the gain magnification when the differential motion
+ * is input by the combination with ADPGSDCR0.P001DG 1:0. */
+ __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
+ * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
+ * each PGA P002 is set. When the differential motion is input,
+ * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
+ * the differential motion is input by the combination with
+ * ADPGSDCR0.P002DG 1:0. */
+ __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
+ * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
+ * each PGA P003 is set. When the differential motion is input,
+ * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
+ * the differential motion is input by the combination with
+ * ADPGSDCR0.P003DG 1:0. */
+ } ADPGAGS0_b;
+ };
+ __IM uint32_t RESERVED23[3];
+
+ union
+ {
+ __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
+ * Input Control Register */
+
+ struct
+ {
+ __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
+ * bits are used, set {P000DEN, P000GEN} to 11b. */
+ uint16_t : 1;
+ __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */
+ __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
+ * bits are used, set {P001DEN, P001GEN} to 11b. */
+ uint16_t : 1;
+ __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */
+ __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
+ * bits are used, set {P002DEN, P002GEN} to 11b. */
+ uint16_t : 1;
+ __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */
+ __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
+ * bits are used, set {P003DEN, P003GEN} to 11b. */
+ uint16_t : 1;
+ __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */
+ } ADPGADCR0_b;
+ };
+ __IM uint16_t RESERVED24;
+
+ union
+ {
+ __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
+ * Input Bias Select Register 0 */
+
+ struct
+ {
+ __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
+ * SelectNOTE: This bit selects the input bias voltage value
+ * when differential inputs are used. */
+ uint8_t : 7;
+ } ADPGADBS0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
+ * Input Bias Select Register 1 */
+
+ struct
+ {
+ __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
+ * This bit selects the input bias voltage value when differential
+ * inputs are used. */
+ uint8_t : 7;
+ } ADPGADBS1_b;
+ };
+ __IM uint16_t RESERVED25;
+ __IM uint32_t RESERVED26[10];
+
+ union
+ {
+ __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */
+
+ struct
+ {
+ __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */
+ uint32_t : 13;
+ __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */
+ uint32_t : 12;
+ } ADREFMON_b;
+ };
+} R_ADC0_Type; /*!< Size = 484 (0x1e4) */
+
+/* =========================================================================================================================== */
+/* ================ R_PSCU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Peripheral Security Control Unit (R_PSCU)
+ */
+
+typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */
+{
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */
+
+ struct
+ {
+ uint32_t : 1;
+ __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */
+ __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */
+ __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */
+ uint32_t : 2;
+ __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */
+ __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */
+ __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */
+ __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */
+ uint32_t : 1;
+ __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */
+ __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */
+ uint32_t : 2;
+ __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
+ * bit security attribution */
+ __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */
+ uint32_t : 1;
+ __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */
+ __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */
+ uint32_t : 2;
+ __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */
+ __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */
+ __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */
+ __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */
+ __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */
+ __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */
+ __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */
+ __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */
+ __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */
+ __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */
+ } PSARB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */
+
+ struct
+ {
+ __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */
+ __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */
+ uint32_t : 1;
+ __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */
+ uint32_t : 4;
+ __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */
+ uint32_t : 3;
+ __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */
+ __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */
+ uint32_t : 6;
+ __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */
+ uint32_t : 6;
+ __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */
+ uint32_t : 3;
+ __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */
+ } PSARC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */
+
+ struct
+ {
+ __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */
+ __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */
+ __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */
+ __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */
+ uint32_t : 7;
+ __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */
+ __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */
+ __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */
+ __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */
+ __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */
+ __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */
+ uint32_t : 2;
+ __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */
+ __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */
+ uint32_t : 1;
+ __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */
+ uint32_t : 2;
+ __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */
+ __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */
+ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */
+ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */
+ uint32_t : 3;
+ } PSARD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */
+
+ struct
+ {
+ __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */
+ __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */
+ __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */
+ uint32_t : 11;
+ __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */
+ __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */
+ uint32_t : 6;
+ __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */
+ __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */
+ __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */
+ __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */
+ __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */
+ __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */
+ __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */
+ __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */
+ __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */
+ __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */
+ } PSARE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */
+ __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */
+ __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */
+ __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */
+ uint32_t : 28;
+ } MSSAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+ * A */
+
+ struct
+ {
+ uint32_t : 15;
+ __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */
+ uint32_t : 8;
+ } CFSAMONA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+ * B */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */
+ uint32_t : 8;
+ } CFSAMONB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */
+ uint32_t : 16;
+ } DFSAMON_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */
+
+ struct
+ {
+ uint32_t : 13;
+ __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */
+ uint32_t : 11;
+ } SSAMONA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */
+ uint32_t : 11;
+ } SSAMONB_b;
+ };
+
+ union
+ {
+ __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */
+
+ struct
+ {
+ __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */
+ uint32_t : 28;
+ } DLMMON_b;
+ };
+} R_PSCU_Type; /*!< Size = 48 (0x30) */
+
+/* =========================================================================================================================== */
+/* ================ R_BUS ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS)
+ */
+
+typedef struct /*!< (@ 0x40003000) R_BUS Structure */
+{
+ __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
+ __IM uint32_t RESERVED[480];
+ __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
+
+ union
+ {
+ __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
+
+ struct
+ {
+ __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
+ } CSRECEN_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[223];
+ __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */
+ __IM uint32_t RESERVED3[235];
+ __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */
+ __IM uint32_t RESERVED4[58];
+ __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */
+ __IM uint32_t RESERVED5[432];
+ __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */
+} R_BUS_Type; /*!< Size = 6320 (0x18b0) */
+
+/* =========================================================================================================================== */
+/* ================ R_CAC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
+ */
+
+typedef struct /*!< (@ 0x40083600) R_CAC Structure */
+{
+ union
+ {
+ __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */
+
+ struct
+ {
+ __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */
+ uint8_t : 7;
+ } CACR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */
+ __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */
+ __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */
+ __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */
+ } CACR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */
+
+ struct
+ {
+ __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */
+ __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */
+ __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
+ * Select */
+ __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */
+ } CACR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */
+
+ struct
+ {
+ __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */
+ __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */
+ __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */
+ uint8_t : 1;
+ __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */
+ __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */
+ __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */
+ uint8_t : 1;
+ } CAICR_b;
+ };
+
+ union
+ {
+ __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */
+
+ struct
+ {
+ __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */
+ __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */
+ __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */
+ uint8_t : 5;
+ } CASTR_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */
+
+ struct
+ {
+ __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
+ * the upper-limit value of the frequency. */
+ } CAULVR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */
+
+ struct
+ {
+ __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
+ * the lower-limit value of the frequency. */
+ } CALLVR_b;
+ };
+
+ union
+ {
+ __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */
+
+ struct
+ {
+ __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
+ * the counter value at the time a valid reference signal
+ * edge is input */
+ } CACNTBR_b;
+ };
+} R_CAC_Type; /*!< Size = 12 (0xc) */
+
+/* =========================================================================================================================== */
+/* ================ R_CANFD ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD)
+ */
+
+typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */
+{
+ __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */
+ __IM uint32_t RESERVED[25];
+
+ union
+ {
+ __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */
+ __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */
+ __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */
+ __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */
+ __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */
+ __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */
+ uint32_t : 2;
+ __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */
+ __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */
+ __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */
+ __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */
+ } CFDGCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */
+
+ struct
+ {
+ __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */
+ __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */
+ uint32_t : 5;
+ __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */
+ __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */
+ __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */
+ __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */
+ uint32_t : 2;
+ __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */
+ __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */
+ __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */
+ __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */
+ uint32_t : 14;
+ } CFDGCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */
+
+ struct
+ {
+ __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */
+ __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */
+ __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */
+ __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */
+ uint32_t : 28;
+ } CFDGSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */
+
+ struct
+ {
+ __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */
+ __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */
+ __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */
+ __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */
+ __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */
+ __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */
+ __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */
+ uint32_t : 1;
+ __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */
+ __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */
+ uint32_t : 6;
+ __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */
+ __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */
+ uint32_t : 14;
+ } CFDGERFL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */
+
+ struct
+ {
+ __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */
+ uint32_t : 16;
+ } CFDGTSC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */
+
+ struct
+ {
+ __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */
+ uint32_t : 4;
+ __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */
+ uint32_t : 23;
+ } CFDGAFLECTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */
+ uint32_t : 7;
+ __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */
+ uint32_t : 7;
+ } CFDGAFLCFG0_b;
+ };
+ __IM uint32_t RESERVED1[3];
+
+ union
+ {
+ __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */
+
+ struct
+ {
+ __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */
+ __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */
+ uint32_t : 21;
+ } CFDRMNB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */
+
+ struct
+ {
+ __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */
+ } CFDRMND0_b;
+ };
+ __IM uint32_t RESERVED2[3];
+
+ union
+ {
+ __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */
+
+ struct
+ {
+ __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */
+ __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */
+ uint32_t : 2;
+ __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */
+ uint32_t : 1;
+ __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */
+ uint32_t : 1;
+ __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */
+ __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */
+ __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */
+ uint32_t : 15;
+ } CFDRFCC_b[8];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */
+
+ struct
+ {
+ __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */
+ __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */
+ __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */
+ __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */
+ uint32_t : 4;
+ __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */
+ __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */
+ uint32_t : 15;
+ } CFDRFSTS_b[8];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */
+ uint32_t : 24;
+ } CFDRFPCTR_b[8];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */
+
+ struct
+ {
+ __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */
+ __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */
+ __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */
+ uint32_t : 1;
+ __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */
+ __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */
+ __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */
+ __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */
+ __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */
+ __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */
+ __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */
+ __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */
+ } CFDCFCC_b[6];
+ };
+ __IM uint32_t RESERVED3[18];
+
+ union
+ {
+ __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement
+ * Registers */
+
+ struct
+ {
+ __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */
+ __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */
+ __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */
+ uint32_t : 5;
+ __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */
+ uint32_t : 7;
+ __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */
+ uint32_t : 15;
+ } CFDCFCCE_b[6];
+ };
+ __IM uint32_t RESERVED4[18];
+
+ union
+ {
+ __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */
+
+ struct
+ {
+ __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */
+ __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */
+ __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */
+ __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */
+ __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */
+ uint32_t : 3;
+ __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */
+ __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */
+ __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */
+ __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */
+ uint32_t : 5;
+ __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */
+ uint32_t : 7;
+ } CFDCFSTS_b[6];
+ };
+ __IM uint32_t RESERVED5[18];
+
+ union
+ {
+ __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */
+ uint32_t : 24;
+ } CFDCFPCTR_b[6];
+ };
+ __IM uint32_t RESERVED6[18];
+
+ union
+ {
+ __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */
+ __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */
+ uint32_t : 18;
+ } CFDFESTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */
+ __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */
+ uint32_t : 18;
+ } CFDFFSTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */
+ __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */
+ uint32_t : 18;
+ } CFDFMSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */
+ uint32_t : 8;
+ __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */
+ uint32_t : 8;
+ } CFDRFISTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */
+
+ struct
+ {
+ __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */
+ uint32_t : 26;
+ } CFDCFRISTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */
+
+ struct
+ {
+ __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */
+ uint32_t : 26;
+ } CFDCFTISTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */
+ uint32_t : 26;
+ } CFDCFOFRISTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */
+ uint32_t : 26;
+ } CFDCFOFTISTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */
+
+ struct
+ {
+ __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */
+ uint32_t : 26;
+ } CFDCFMOWSTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */
+ __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */
+ uint32_t : 18;
+ } CFDFFFSTS_b;
+ };
+ __IM uint32_t RESERVED7[2];
+
+ union
+ {
+ __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */
+
+ struct
+ {
+ __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */
+ __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */
+ __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */
+ uint8_t : 5;
+ } CFDTMC_b[128];
+ };
+ __IM uint32_t RESERVED8[288];
+
+ union
+ {
+ __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */
+
+ struct
+ {
+ __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */
+ __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */
+ __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */
+ __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */
+ uint8_t : 3;
+ } CFDTMSTS_b[128];
+ };
+ __IM uint32_t RESERVED9[288];
+
+ union
+ {
+ __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */
+ uint32_t : 24;
+ } CFDTMTRSTS_b[4];
+ };
+ __IM uint32_t RESERVED10[36];
+
+ union
+ {
+ __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
+ * Status Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */
+ uint32_t : 24;
+ } CFDTMTARSTS_b[4];
+ };
+ __IM uint32_t RESERVED11[36];
+
+ union
+ {
+ __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */
+ uint32_t : 24;
+ } CFDTMTCSTS_b[4];
+ };
+ __IM uint32_t RESERVED12[36];
+
+ union
+ {
+ __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */
+ uint32_t : 24;
+ } CFDTMTASTS_b[4];
+ };
+ __IM uint32_t RESERVED13[36];
+
+ union
+ {
+ __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */
+ uint32_t : 24;
+ } CFDTMIEC_b[4];
+ };
+ __IM uint32_t RESERVED14[40];
+
+ union
+ {
+ __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */
+
+ struct
+ {
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
+ __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
+ uint32_t : 3;
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
+ __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
+ uint32_t : 3;
+ __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */
+ __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
+ __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
+ uint32_t : 13;
+ } CFDTXQCC0_b[2];
+ };
+ __IM uint32_t RESERVED15[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */
+
+ struct
+ {
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
+ uint32_t : 5;
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
+ uint32_t : 2;
+ __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
+ __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
+ __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
+ __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
+ uint32_t : 12;
+ } CFDTXQSTS0_b[2];
+ };
+ __IM uint32_t RESERVED16[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */
+
+ struct
+ {
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
+ uint32_t : 24;
+ } CFDTXQPCTR0_b[2];
+ };
+ __IM uint32_t RESERVED17[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */
+
+ struct
+ {
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
+ __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
+ uint32_t : 3;
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
+ __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
+ uint32_t : 3;
+ __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */
+ __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
+ __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
+ uint32_t : 13;
+ } CFDTXQCC1_b[2];
+ };
+ __IM uint32_t RESERVED18[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */
+
+ struct
+ {
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
+ uint32_t : 5;
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
+ uint32_t : 2;
+ __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
+ __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
+ __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
+ __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
+ uint32_t : 12;
+ } CFDTXQSTS1_b[2];
+ };
+ __IM uint32_t RESERVED19[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */
+
+ struct
+ {
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
+ uint32_t : 24;
+ } CFDTXQPCTR1_b[2];
+ };
+ __IM uint32_t RESERVED20[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */
+
+ struct
+ {
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
+ __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
+ uint32_t : 3;
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
+ __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
+ uint32_t : 3;
+ __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */
+ __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
+ __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
+ uint32_t : 13;
+ } CFDTXQCC2_b[2];
+ };
+ __IM uint32_t RESERVED21[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */
+
+ struct
+ {
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
+ uint32_t : 5;
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
+ uint32_t : 2;
+ __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
+ __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
+ __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
+ __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
+ uint32_t : 12;
+ } CFDTXQSTS2_b[2];
+ };
+ __IM uint32_t RESERVED22[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */
+
+ struct
+ {
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
+ uint32_t : 24;
+ } CFDTXQPCTR2_b[2];
+ };
+ __IM uint32_t RESERVED23[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */
+
+ struct
+ {
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
+ uint32_t : 4;
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
+ __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
+ uint32_t : 5;
+ __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
+ uint32_t : 13;
+ } CFDTXQCC3_b[2];
+ };
+ __IM uint32_t RESERVED24[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */
+
+ struct
+ {
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
+ uint32_t : 5;
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
+ uint32_t : 4;
+ __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
+ uint32_t : 13;
+ } CFDTXQSTS3_b[2];
+ };
+ __IM uint32_t RESERVED25[6];
+
+ union
+ {
+ __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */
+
+ struct
+ {
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
+ uint32_t : 24;
+ } CFDTXQPCTR3_b[2];
+ };
+ __IM uint32_t RESERVED26[6];
+
+ union
+ {
+ __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */
+ uint32_t : 24;
+ } CFDTXQESTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */
+ uint32_t : 1;
+ __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */
+ uint32_t : 25;
+ } CFDTXQFISTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */
+ uint32_t : 1;
+ __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */
+ uint32_t : 25;
+ } CFDTXQMSTS_b;
+ };
+ __IM uint32_t RESERVED27;
+
+ union
+ {
+ __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */
+ __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */
+ uint32_t : 24;
+ } CFDTXQISTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */
+ __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */
+ uint32_t : 24;
+ } CFDTXQOFTISTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */
+ uint32_t : 1;
+ __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */
+ uint32_t : 25;
+ } CFDTXQOFRISTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */
+
+ struct
+ {
+ __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */
+ __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */
+ uint32_t : 24;
+ } CFDTXQFSTS_b;
+ };
+ __IM uint32_t RESERVED28[24];
+
+ union
+ {
+ __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */
+
+ struct
+ {
+ __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */
+ uint32_t : 7;
+ __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */
+ __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */
+ __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */
+ __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */
+ uint32_t : 20;
+ } CFDTHLCC_b[2];
+ };
+ __IM uint32_t RESERVED29[6];
+
+ union
+ {
+ __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */
+
+ struct
+ {
+ __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */
+ __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */
+ __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */
+ __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */
+ uint32_t : 4;
+ __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */
+ uint32_t : 18;
+ } CFDTHLSTS_b[2];
+ };
+ __IM uint32_t RESERVED30[6];
+
+ union
+ {
+ __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */
+ uint32_t : 24;
+ } CFDTHLPCTR_b[2];
+ };
+ __IM uint32_t RESERVED31[46];
+
+ union
+ {
+ __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */
+ __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */
+ __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */
+ __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */
+ __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */
+ __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
+ * 0 */
+ __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
+ * 0 */
+ uint32_t : 1;
+ __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */
+ __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */
+ __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */
+ __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */
+ __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */
+ __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
+ * 1 */
+ __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
+ * 1 */
+ uint32_t : 17;
+ } CFDGTINTSTS0_b;
+ };
+ __IM uint32_t RESERVED32;
+
+ union
+ {
+ __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */
+ uint32_t : 14;
+ __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */
+ uint32_t : 6;
+ } CFDGTSTCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */
+
+ struct
+ {
+ __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */
+ uint32_t : 1;
+ __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */
+ uint32_t : 29;
+ } CFDGTSTCTR_b;
+ };
+ __IM uint32_t RESERVED33;
+
+ union
+ {
+ __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */
+
+ struct
+ {
+ __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */
+ uint32_t : 7;
+ __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */
+ uint32_t : 22;
+ } CFDGFDCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */
+
+ struct
+ {
+ __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */
+ uint32_t : 31;
+ } CFDGCRCCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */
+
+ struct
+ {
+ __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */
+ uint32_t : 16;
+ } CFDGLOCKK_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */
+
+ struct
+ {
+ __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */
+ uint32_t : 7;
+ __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */
+ __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */
+ __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */
+ __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */
+ uint32_t : 16;
+ } CFDGLOTB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */
+
+ struct
+ {
+ __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */
+ uint32_t : 7;
+ __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */
+ uint32_t : 13;
+ } CFDGAFLIGNENT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */
+
+ struct
+ {
+ __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */
+ uint32_t : 7;
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
+ uint32_t : 16;
+ } CFDGAFLIGNCTR_b;
+ };
+ __IM uint32_t RESERVED34;
+
+ union
+ {
+ __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */
+
+ struct
+ {
+ __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */
+ __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */
+ __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */
+ __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */
+ __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */
+ __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */
+ __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */
+ __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */
+ __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */
+ __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */
+ uint32_t : 22;
+ } CFDCDTCT_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */
+
+ struct
+ {
+ __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */
+ __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */
+ __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */
+ __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */
+ __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */
+ __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */
+ __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */
+ __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */
+ __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
+ * 0 */
+ __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel
+ * 1 */
+ uint32_t : 22;
+ } CFDCDTSTS_b;
+ };
+ __IM uint32_t RESERVED35[2];
+
+ union
+ {
+ __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */
+
+ struct
+ {
+ __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */
+ __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */
+ uint32_t : 6;
+ __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */
+ __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */
+ uint32_t : 6;
+ __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel
+ * 0 */
+ __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel
+ * 1 */
+ uint32_t : 14;
+ } CFDCDTTCT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */
+
+ struct
+ {
+ __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */
+ __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */
+ uint32_t : 6;
+ __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */
+ __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */
+ uint32_t : 6;
+ __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel
+ * 0 */
+ __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel
+ * 1 */
+ uint32_t : 14;
+ } CFDCDTTSTS_b;
+ };
+ __IM uint32_t RESERVED36[2];
+
+ union
+ {
+ __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */
+
+ struct
+ {
+ __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */
+ uint32_t : 5;
+ __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */
+ uint32_t : 5;
+ __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */
+ uint32_t : 5;
+ __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */
+ uint32_t : 1;
+ __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */
+ uint32_t : 1;
+ } CFDGRINTSTS_b[2];
+ };
+ __IM uint32_t RESERVED37[10];
+
+ union
+ {
+ __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */
+
+ struct
+ {
+ __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */
+ uint32_t : 7;
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
+ uint32_t : 16;
+ } CFDGRSTC_b;
+ };
+ __IM uint32_t RESERVED38[31];
+ __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */
+ __IM uint32_t RESERVED39[240];
+ __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */
+ __IM uint32_t RESERVED40[448];
+ __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */
+ __IM uint32_t RESERVED41[3072];
+ __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */
+ __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */
+ __IM uint32_t RESERVED42[1600];
+ __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */
+ __IM uint32_t RESERVED43[252];
+
+ union
+ {
+ __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */
+
+ struct
+ {
+ __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
+ } CFDRPGACC_b[64];
+ };
+ __IM uint32_t RESERVED44[7872];
+ __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */
+} R_CANFD_Type; /*!< Size = 81920 (0x14000) */
+
+/* =========================================================================================================================== */
+/* ================ R_CRC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
+ */
+
+typedef struct /*!< (@ 0x40108000) R_CRC Structure */
+{
+ union
+ {
+ __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */
+
+ struct
+ {
+ __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */
+ uint8_t : 3;
+ __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */
+ __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */
+ } CRCCR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */
+
+ struct
+ {
+ uint8_t : 6;
+ __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */
+ __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */
+ } CRCCR1_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */
+
+ struct
+ {
+ __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */
+ } CRCDIR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */
+
+ struct
+ {
+ __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
+ * ) */
+ } CRCDIR_BY_b;
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */
+
+ struct
+ {
+ __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */
+ } CRCDOR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */
+
+ struct
+ {
+ __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
+ * ) */
+ } CRCDOR_HA_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */
+
+ struct
+ {
+ __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */
+ } CRCDOR_BY_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */
+
+ struct
+ {
+ __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */
+ uint16_t : 2;
+ } CRCSAR_b;
+ };
+ __IM uint16_t RESERVED1;
+} R_CRC_Type; /*!< Size = 16 (0x10) */
+
+/* =========================================================================================================================== */
+/* ================ R_CTSU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Capacitive Touch Sensing Unit (R_CTSU)
+ */
+
+typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */
+{
+ union
+ {
+ __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */
+
+ struct
+ {
+ __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */
+ __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */
+ __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */
+ __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */
+ __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */
+ uint8_t : 2;
+ __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */
+ } CTSUCR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */
+ __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */
+ __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */
+ __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */
+ __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */
+ __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */
+ } CTSUCR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */
+
+ struct
+ {
+ __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
+ * setting: 3 (0011b) */
+ __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */
+ __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */
+ uint8_t : 1;
+ } CTSUSDPRS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */
+
+ struct
+ {
+ __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
+ * of these bits should be fixed to 00010000b. */
+ } CTSUSST_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */
+
+ struct
+ {
+ __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
+ * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
+ * bits = 00b).Note2: If the value of CTSUMCH0 was set to
+ * b'111111 in mode other than self-capacitor single scan
+ * mode, the measurement is stopped. */
+ uint8_t : 2;
+ } CTSUMCH0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */
+
+ struct
+ {
+ __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
+ * was set to b'111111, the measurement is stopped. */
+ uint8_t : 2;
+ } CTSUMCH1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */
+
+ struct
+ {
+ __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */
+ __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */
+ __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */
+ __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */
+ __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */
+ __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */
+ __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */
+ __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */
+ } CTSUCHAC_b[5];
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */
+
+ struct
+ {
+ __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */
+ __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */
+ } CTSUCHTRC_b[5];
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */
+
+ struct
+ {
+ __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
+ * be set to 00b. */
+ uint8_t : 2;
+ __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
+ * be set to 11b. */
+ uint8_t : 2;
+ } CTSUDCLKC_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */
+
+ struct
+ {
+ __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */
+ uint8_t : 1;
+ __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */
+ __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */
+ __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */
+ __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */
+ } CTSUST_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
+ * Control Register */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */
+ uint16_t : 4;
+ } CTSUSSC_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */
+
+ struct
+ {
+ __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
+ * CTSUSO ( 0 to 1023 ) */
+ __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */
+ } CTSUSO0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */
+
+ struct
+ {
+ __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
+ * is CTSUSO ( 0 to 255 ) */
+ __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
+ * CTSUSDPA + 1 ) x 2 */
+ __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */
+ uint16_t : 1;
+ } CTSUSO1_b;
+ };
+
+ union
+ {
+ __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */
+
+ struct
+ {
+ __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
+ * result of the CTSU. These bits indicate FFFFh when an overflow
+ * occurs. */
+ } CTSUSC_b;
+ };
+
+ union
+ {
+ __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */
+
+ struct
+ {
+ __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
+ * result of the reference ICO.These bits indicate FFFFh when
+ * an overflow occurs. */
+ } CTSURC_b;
+ };
+
+ union
+ {
+ __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */
+
+ struct
+ {
+ __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */
+ __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */
+ __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */
+ uint16_t : 2;
+ __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */
+ __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */
+ uint16_t : 7;
+ __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */
+ } CTSUERRS_b;
+ };
+ __IM uint16_t RESERVED;
+ __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */
+ __IM uint8_t RESERVED1;
+ __IM uint16_t RESERVED2;
+} R_CTSU_Type; /*!< Size = 36 (0x24) */
+
+/* =========================================================================================================================== */
+/* ================ R_DAC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief D/A Converter (R_DAC)
+ */
+
+typedef struct /*!< (@ 0x40171000) R_DAC Structure */
+{
+ union
+ {
+ __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */
+
+ struct
+ {
+ __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
+ * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL
+ * = 1, the low-order 4 bits are fixed to 0: left justified
+ * format. */
+ } DADR_b[2];
+ };
+
+ union
+ {
+ __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */
+
+ struct
+ {
+ uint8_t : 5;
+ __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */
+ __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */
+ __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */
+ } DACR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */
+ } DADPR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */
+ } DAADSCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */
+
+ struct
+ {
+ __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */
+ uint8_t : 5;
+ } DAVREFCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */
+
+ struct
+ {
+ uint8_t : 6;
+ __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */
+ __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */
+ } DAAMPCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */
+
+ struct
+ {
+ __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */
+ uint8_t : 7;
+ } DAPC_b;
+ };
+ __IM uint16_t RESERVED[9];
+
+ union
+ {
+ __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */
+
+ struct
+ {
+ uint8_t : 6;
+ __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
+ * to wait for stabilization of the output amplifier of D/A
+ * channel 0. When DAASW0 is set to 1, D/A conversion operates,
+ * but the conversion result D/A is not output from channel
+ * 0. When the DAASW0 bit is 0, the stabilization wait time
+ * stops, and the D/A conversion result of channel 0 is output
+ * through the output amplifier. */
+ __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
+ * to wait for stabilization of the output amplifier of D/A
+ * channel 1. When DAASW1 is set to 1, D/A conversion operates,
+ * but the conversion result D/A is not output from channel
+ * 1. When the DAASW1 bit is 0, the stabilization wait time
+ * stops, and the D/A conversion result of channel 1 is output
+ * through the output amplifier. */
+ } DAASWCR_b;
+ };
+ __IM uint8_t RESERVED1;
+ __IM uint16_t RESERVED2[2129];
+
+ union
+ {
+ __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */
+
+ struct
+ {
+ __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
+ * D/A and A/D synchronous conversions. Set bit [0] to 1 to
+ * select unit 0 as the target synchronous unit for the MCU.
+ * When setting the DAADSCR.DAADST bit to 1 for synchronous
+ * conversions, select the target unit in this register in
+ * advance. Only set the DAADUSR register while the ADCSR.ADST
+ * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+ * is set to 0. */
+ __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
+ * D/A and A/D synchronous conversions. Set bit [1] to 1 to
+ * select unit 1 as the target synchronous unit for the MCU.
+ * When setting the DAADSCR.DAADST bit to 1 for synchronous
+ * conversions, select the target unit in this register in
+ * advance. Only set the DAADUSR register while the ADCSR.ADST
+ * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+ * is set to 0. */
+ uint8_t : 6;
+ } DAADUSR_b;
+ };
+ __IM uint8_t RESERVED3;
+ __IM uint16_t RESERVED4;
+} R_DAC_Type; /*!< Size = 4292 (0x10c4) */
+
+/* =========================================================================================================================== */
+/* ================ R_DEBUG ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Debug Function (R_DEBUG)
+ */
+
+typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */
+{
+ union
+ {
+ __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */
+
+ struct
+ {
+ uint32_t : 28;
+ __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */
+ __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */
+ uint32_t : 2;
+ } DBGSTR_b;
+ };
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */
+
+ struct
+ {
+ __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */
+ __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */
+ uint32_t : 14;
+ __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */
+ __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */
+ __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */
+ uint32_t : 5;
+ __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */
+ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */
+ uint32_t : 5;
+ __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */
+ } DBGSTOPCR_b;
+ };
+} R_DEBUG_Type; /*!< Size = 20 (0x14) */
+
+/* =========================================================================================================================== */
+/* ================ R_DMA ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller Common (R_DMA)
+ */
+
+typedef struct /*!< (@ 0x40005200) R_DMA Structure */
+{
+ union
+ {
+ __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */
+
+ struct
+ {
+ __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */
+ uint8_t : 7;
+ } DMAST_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[15];
+
+ union
+ {
+ __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */
+
+ struct
+ {
+ __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */
+ uint32_t : 5;
+ __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */
+ uint32_t : 7;
+ __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */
+ uint32_t : 15;
+ } DMECHR_b;
+ };
+ __IM uint32_t RESERVED3[15];
+
+ union
+ {
+ __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */
+
+ struct
+ {
+ __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */
+ uint32_t : 7;
+ __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+ * IR flag is prohibited. */
+ uint32_t : 15;
+ } DELSR_b[8];
+ };
+} R_DMA_Type; /*!< Size = 160 (0xa0) */
+
+/* =========================================================================================================================== */
+/* ================ R_DMAC0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller (R_DMAC0)
+ */
+
+typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */
+{
+ union
+ {
+ __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct
+ {
+ __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */
+ } DMSAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct
+ {
+ __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */
+ } DMDAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */
+
+ struct
+ {
+ __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */
+ __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */
+ uint32_t : 6;
+ } DMCRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */
+
+ struct
+ {
+ __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
+ * transfer counter. */
+ __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
+ * repeat transfer operations. */
+ } DMCRB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */
+
+ struct
+ {
+ __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */
+ uint16_t : 6;
+ __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */
+ __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */
+ uint16_t : 1;
+ __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */
+ __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */
+ } DMTMD_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */
+
+ struct
+ {
+ __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
+ * Enable */
+ __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
+ * Enable */
+ __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */
+ __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */
+ __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */
+ uint8_t : 3;
+ } DMINT_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */
+
+ struct
+ {
+ __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the
+ * extended repeat area on the destination address. For details
+ * on the settings. */
+ __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */
+ __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */
+ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
+ * repeat area on the source address. For details on the settings. */
+ __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */
+ __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */
+ } DMAMD_b;
+ };
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */
+
+ struct
+ {
+ __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
+ * as the address update mode for transfer source or destination. */
+ } DMOFR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */
+
+ struct
+ {
+ __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */
+ uint8_t : 7;
+ } DMCNT_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */
+
+ struct
+ {
+ __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */
+ uint8_t : 3;
+ __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */
+ uint8_t : 3;
+ } DMREQ_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */
+
+ struct
+ {
+ __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */
+ uint8_t : 3;
+ __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */
+ uint8_t : 2;
+ __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */
+ } DMSTS_b;
+ };
+ __IM uint8_t RESERVED2;
+ __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */
+ __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */
+
+ union
+ {
+ __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */
+
+ struct
+ {
+ __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+ * mode */
+ __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+ * mode */
+ } DMSBS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */
+
+ struct
+ {
+ __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+ * mode */
+ __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+ * mode */
+ } DMDBS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */
+
+ struct
+ {
+ __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */
+ uint8_t : 7;
+ } DMBWR_b;
+ };
+ __IM uint8_t RESERVED3;
+ __IM uint16_t RESERVED4;
+} R_DMAC0_Type; /*!< Size = 52 (0x34) */
+
+/* =========================================================================================================================== */
+/* ================ R_DOC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct /*!< (@ 0x40109000) R_DOC Structure */
+{
+ union
+ {
+ __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
+
+ struct
+ {
+ __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
+ __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */
+ uint8_t : 2;
+ __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */
+ __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */
+ uint8_t : 1;
+ } DOCR_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */
+
+ struct
+ {
+ __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
+ * use in the operations are stored. */
+ } DODIR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */
+
+ struct
+ {
+ __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
+ * in data comparison mode. This register also stores the
+ * results of operations in data addition and data subtraction
+ * modes. */
+ } DODSR_b;
+ };
+} R_DOC_Type; /*!< Size = 6 (0x6) */
+
+/* =========================================================================================================================== */
+/* ================ R_DTC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Transfer Controller (R_DTC)
+ */
+
+typedef struct /*!< (@ 0x40005400) R_DTC Structure */
+{
+ union
+ {
+ __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */
+ uint8_t : 3;
+ } DTCCR_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */
+
+ struct
+ {
+ __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
+ * in the lower-order 10 bits. These bits are fixed to 0. */
+ } DTCVBR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */
+
+ struct
+ {
+ __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */
+ uint8_t : 7;
+ } DTCST_b;
+ };
+ __IM uint8_t RESERVED3;
+
+ union
+ {
+ __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */
+
+ struct
+ {
+ __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
+ * the vector number for the activating source when DTC transfer
+ * is in progress.The value is only valid if DTC transfer
+ * is in progress (the value of the ACT flag is 1) */
+ uint16_t : 7;
+ __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */
+ } DTCSTS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */
+ uint8_t : 3;
+ } DTCCR_SEC_b;
+ };
+ __IM uint8_t RESERVED4;
+ __IM uint16_t RESERVED5;
+ __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */
+ __IM uint32_t RESERVED6[2];
+
+ union
+ {
+ __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */
+
+ struct
+ {
+ __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */
+ __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */
+ uint32_t : 7;
+ __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */
+ uint32_t : 15;
+ } DTEVR_b;
+ };
+} R_DTC_Type; /*!< Size = 36 (0x24) */
+
+/* =========================================================================================================================== */
+/* ================ R_ELC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Controller (R_ELC)
+ */
+
+typedef struct /*!< (@ 0x40082000) R_ELC Structure */
+{
+ union
+ {
+ __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */
+ } ELCR_b;
+ };
+ __IM uint8_t RESERVED;
+ __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */
+ __IM uint16_t RESERVED1[5];
+ __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */
+ __IM uint16_t RESERVED2[4];
+
+ union
+ {
+ __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
+ * A */
+
+ struct
+ {
+ __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */
+ __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
+ * Attribution */
+ __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
+ * Attribution */
+ uint16_t : 13;
+ } ELCSARA_b;
+ };
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
+ * B */
+
+ struct
+ {
+ __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */
+ __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */
+ __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */
+ __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */
+ __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */
+ __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */
+ __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */
+ __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */
+ __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */
+ __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */
+ __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */
+ __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */
+ __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */
+ __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */
+ __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */
+ __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */
+ } ELCSARB_b;
+ };
+ __IM uint16_t RESERVED4;
+
+ union
+ {
+ __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
+ * C */
+
+ struct
+ {
+ __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */
+ __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */
+ __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */
+ uint16_t : 13;
+ } ELCSARC_b;
+ };
+} R_ELC_Type; /*!< Size = 126 (0x7e) */
+
+/* =========================================================================================================================== */
+/* ================ R_ETHERC0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet MAC Controller (R_ETHERC0)
+ */
+
+typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */
+{
+ union
+ {
+ __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */
+
+ struct
+ {
+ __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */
+ __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */
+ __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */
+ __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */
+ uint32_t : 1;
+ __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */
+ __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */
+ uint32_t : 2;
+ __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */
+ uint32_t : 2;
+ __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */
+ uint32_t : 3;
+ __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */
+ __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */
+ __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */
+ __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */
+ __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */
+ uint32_t : 11;
+ } ECMR_b;
+ };
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */
+
+ struct
+ {
+ __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
+ * maximum frame length. The minimum value that can be set
+ * is 1,518 bytes, and the maximum value that can be set is
+ * 2,048 bytes. Values that are less than 1,518 bytes are
+ * regarded as 1,518 bytes, and values larger than 2,048 bytes
+ * are regarded as 2,048 bytes. */
+ uint32_t : 20;
+ } RFLR_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */
+
+ struct
+ {
+ __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */
+ __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */
+ __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */
+ uint32_t : 1;
+ __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */
+ __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */
+ uint32_t : 26;
+ } ECSR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */
+ __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */
+ __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */
+ __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */
+ uint32_t : 26;
+ } ECSIPR_b;
+ };
+ __IM uint32_t RESERVED3;
+
+ union
+ {
+ __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */
+
+ struct
+ {
+ __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
+ * from the ETn_MDC pin to supply the management data clock
+ * to the MII or RMII. */
+ __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */
+ __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
+ * from the ETn_MDIO pin when the MMD bit is 1 (write). The
+ * value is not output when the MMD bit is 0 (read). */
+ __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
+ * of the ETn_MDIO pin. The write value should be 0. */
+ uint32_t : 28;
+ } PIR_b;
+ };
+ __IM uint32_t RESERVED4;
+
+ union
+ {
+ __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */
+
+ struct
+ {
+ __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
+ * by connecting the link signal output from the PHY-LSI to
+ * the ETn_LINKSTA pin. For details on the polarity, refer
+ * to the specifications of the connected PHY-LSI. */
+ uint32_t : 31;
+ } PSR_b;
+ };
+ __IM uint32_t RESERVED5[5];
+
+ union
+ {
+ __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */
+ uint32_t : 12;
+ } RDMLR_b;
+ };
+ __IM uint32_t RESERVED6[3];
+
+ union
+ {
+ __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */
+
+ struct
+ {
+ __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */
+ uint32_t : 27;
+ } IPGR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */
+
+ struct
+ {
+ __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
+ * of the pause_time parameter for a PAUSE frame that is automatically
+ * transmitted. Transmission is not performed until the set
+ * value multiplied by 512 bit time has elapsed. */
+ uint32_t : 16;
+ } APR_b;
+ };
+
+ union
+ {
+ __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */
+
+ struct
+ {
+ __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
+ * the pause_time parameter for a PAUSE frame that is manually
+ * transmitted. Transmission is not performed until the set
+ * value multiplied by 512 bit time has elapsed. The read
+ * value is undefined. */
+ uint32_t : 16;
+ } MPR_b;
+ };
+ __IM uint32_t RESERVED7;
+
+ union
+ {
+ __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */
+
+ struct
+ {
+ __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */
+ uint32_t : 24;
+ } RFCF_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */
+
+ struct
+ {
+ __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */
+ uint32_t : 16;
+ } TPAUSER_b;
+ };
+ __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */
+
+ union
+ {
+ __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */
+
+ struct
+ {
+ __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */
+ uint32_t : 16;
+ } BCFRR_b;
+ };
+ __IM uint32_t RESERVED8[20];
+
+ union
+ {
+ __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */
+
+ struct
+ {
+ __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
+ * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */
+ } MAHR_b;
+ };
+ __IM uint32_t RESERVED9;
+
+ union
+ {
+ __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */
+
+ struct
+ {
+ __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
+ * the lower 16 bits of the 48-bit MAC address. */
+ uint32_t : 16;
+ } MALR_b;
+ };
+ __IM uint32_t RESERVED10;
+
+ union
+ {
+ __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */
+
+ struct
+ {
+ __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
+ * is a counter indicating the number of frames that fail
+ * to be retransmitted. */
+ } TROCR_b;
+ };
+ __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */
+
+ union
+ {
+ __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */
+
+ struct
+ {
+ __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
+ * counter indicating the number of times a loss of carrier
+ * is detected during frame transmission. */
+ } LCCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */
+
+ struct
+ {
+ __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
+ * is a counter indicating the number of times a carrier is
+ * not detected during preamble transmission. */
+ } CNDCR_b;
+ };
+ __IM uint32_t RESERVED11;
+
+ union
+ {
+ __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */
+
+ struct
+ {
+ __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
+ * is a counter indicating the number of received frames where
+ * a CRC error has been detected. */
+ } CEFCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */
+
+ struct
+ {
+ __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
+ * is a counter indicating the number of times a frame receive
+ * error has occurred. */
+ } FRECR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */
+
+ struct
+ {
+ __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
+ * is a counter indicating the number of times a short frame
+ * that is shorter than 64 bytes has been received. */
+ } TSFRCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */
+
+ struct
+ {
+ __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
+ * is a counter indicating the number of times a long frame
+ * that is longer than the RFLR register value has been received. */
+ } TLFRCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */
+
+ struct
+ {
+ __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
+ * register is a counter indicating the number of times a
+ * frame has been received with the alignment error (frame
+ * is not an integral number of octets). */
+ } RFCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */
+
+ struct
+ {
+ __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
+ * MAFCR register is a counter indicating the number of times
+ * a frame where the multicast address is set has been received. */
+ } MAFCR_b;
+ };
+} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */
+
+/* =========================================================================================================================== */
+/* ================ R_ETHERC_EDMAC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
+ */
+
+typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */
+{
+ union
+ {
+ __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */
+
+ struct
+ {
+ __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */
+ uint32_t : 3;
+ __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */
+ __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
+ * applies to data for the transmit/receive buffer. It does
+ * not apply to transmit/receive descriptors and registers. */
+ uint32_t : 25;
+ } EDMR_b;
+ };
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */
+
+ struct
+ {
+ __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */
+ uint32_t : 31;
+ } EDTRR_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */
+
+ struct
+ {
+ __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */
+ uint32_t : 31;
+ } EDRRR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */
+
+ struct
+ {
+ __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
+ * set. Set the start address according to the descriptor
+ * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
+ * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
+ * boundary: Lower 6 bits = 000000b */
+ } TDLAR_b;
+ };
+ __IM uint32_t RESERVED3;
+
+ union
+ {
+ __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */
+
+ struct
+ {
+ __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
+ * set. Set the start address according to the descriptor
+ * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
+ * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
+ * boundary: Lower 6 bits = 000000b */
+ } RDLAR_b;
+ };
+ __IM uint32_t RESERVED4;
+
+ union
+ {
+ __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */
+
+ struct
+ {
+ __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */
+ __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */
+ __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */
+ __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */
+ __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */
+ uint32_t : 2;
+ __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */
+ __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */
+ __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */
+ __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */
+ __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */
+ uint32_t : 4;
+ __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */
+ __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */
+ __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */
+ __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */
+ __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */
+ __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */
+ __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
+ * in the ETHERCn.ECSR register is cleared, the ECI flag is
+ * also cleared. */
+ __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */
+ __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */
+ __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */
+ __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */
+ uint32_t : 3;
+ __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */
+ uint32_t : 1;
+ } EESR_b;
+ };
+ __IM uint32_t RESERVED5;
+
+ union
+ {
+ __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */
+ __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */
+ __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */
+ __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */
+ __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */
+ uint32_t : 2;
+ __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */
+ __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */
+ __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */
+ __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */
+ __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */
+ uint32_t : 4;
+ __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */
+ __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */
+ __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */
+ __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */
+ __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */
+ __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */
+ __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */
+ __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */
+ __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */
+ __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */
+ __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */
+ uint32_t : 3;
+ __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */
+ uint32_t : 1;
+ } EESIPR_b;
+ };
+ __IM uint32_t RESERVED6;
+
+ union
+ {
+ __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
+ * Register */
+
+ struct
+ {
+ uint32_t : 4;
+ __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */
+ uint32_t : 2;
+ __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */
+ uint32_t : 24;
+ } TRSCER_b;
+ };
+ __IM uint32_t RESERVED7;
+
+ union
+ {
+ __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */
+
+ struct
+ {
+ __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
+ * frames that are discarded and not transferred to the receive
+ * buffer during reception. */
+ uint32_t : 16;
+ } RMFCR_b;
+ };
+ __IM uint32_t RESERVED8;
+
+ union
+ {
+ __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */
+
+ struct
+ {
+ __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
+ * the set value multiplied by 4. Example: 00Dh: 52 bytes
+ * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */
+ uint32_t : 21;
+ } TFTR_b;
+ };
+ __IM uint32_t RESERVED9;
+
+ union
+ {
+ __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */
+
+ struct
+ {
+ __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */
+ uint32_t : 3;
+ __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */
+ uint32_t : 19;
+ } FDR_b;
+ };
+ __IM uint32_t RESERVED10;
+
+ union
+ {
+ __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */
+
+ struct
+ {
+ __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */
+ uint32_t : 31;
+ } RMCR_b;
+ };
+ __IM uint32_t RESERVED11[2];
+
+ union
+ {
+ __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */
+
+ struct
+ {
+ __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
+ * many times the transmit FIFO has underflowed. The counter
+ * stops when the counter value reaches FFFFh. */
+ uint32_t : 16;
+ } TFUCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */
+
+ struct
+ {
+ __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
+ * times the receive FIFO has overflowed. The counter stops
+ * when the counter value reaches FFFFh. */
+ uint32_t : 16;
+ } RFOCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */
+
+ struct
+ {
+ __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */
+ uint32_t : 31;
+ } IOSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */
+
+ struct
+ {
+ __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
+ * bytes of data is stored in the receive FIFO.) */
+ uint32_t : 13;
+ __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
+ * receive frames have been stored in the receive FIFO.) */
+ uint32_t : 13;
+ } FCFTR_b;
+ };
+ __IM uint32_t RESERVED12;
+
+ union
+ {
+ __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */
+
+ struct
+ {
+ __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */
+ uint32_t : 10;
+ __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */
+ uint32_t : 14;
+ } RPADIR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */
+
+ struct
+ {
+ __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
+ * the mode selected by the TIM bit to notify an interrupt. */
+ uint32_t : 3;
+ __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */
+ uint32_t : 27;
+ } TRIMD_b;
+ };
+ __IM uint32_t RESERVED13[18];
+
+ union
+ {
+ __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */
+
+ struct
+ {
+ __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
+ * indicates the last address that the EDMAC has written data
+ * to when writing to the receive buffer.Refer to the address
+ * indicated by the RBWAR register to recognize which address
+ * in the receive buffer the EDMAC is writing data to. Note
+ * that the address that the EDMAC is outputting to the receive
+ * buffer may not match the read value of the RBWAR register
+ * during data reception. */
+ } RBWAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */
+
+ struct
+ {
+ __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
+ * indicates the start address of the last fetched receive
+ * descriptor when the EDMAC fetches descriptor information
+ * from the receive descriptor.Refer to the address indicated
+ * by the RDFAR register to recognize which receive descriptor
+ * information the EDMAC is using for the current processing.
+ * Note that the address of the receive descriptor that the
+ * EDMAC fetches may not match the read value of the RDFAR
+ * register during data reception. */
+ } RDFAR_b;
+ };
+ __IM uint32_t RESERVED14;
+
+ union
+ {
+ __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */
+
+ struct
+ {
+ __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
+ * indicates the last address that the EDMAC has read data
+ * from when reading data from the transmit buffer.Refer to
+ * the address indicated by the TBRAR register to recognize
+ * which address in the transmit buffer the EDMAC is reading
+ * from. Note that the address that the EDMAC is outputting
+ * to the transmit buffer may not match the read value of
+ * the TBRAR register. */
+ } TBRAR_b;
+ };
+
+ union
+ {
+ __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */
+
+ struct
+ {
+ __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
+ * register indicates the start address of the last fetched
+ * transmit descriptor when the EDMAC fetches descriptor information
+ * from the transmit descriptor.Refer to the address indicated
+ * by the TDFAR register to recognize which transmit descriptor
+ * information the EDMAC is using for the current processing.
+ * Note that the address of the transmit descriptor that the
+ * EDMAC fetches may not match the read value of the TDFAR
+ * register. */
+ } TDFAR_b;
+ };
+} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */
+
+/* =========================================================================================================================== */
+/* ================ R_FACI_HP_CMD ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
+ */
+
+typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */
+{
+ union
+ {
+ __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
+ __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
+ };
+} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */
+
+/* =========================================================================================================================== */
+/* ================ R_FACI_HP ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface (R_FACI_HP)
+ */
+
+typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */
+{
+ __IM uint32_t RESERVED[4];
+
+ union
+ {
+ __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */
+
+ struct
+ {
+ uint8_t : 3;
+ __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */
+ __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */
+ uint8_t : 2;
+ __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */
+ } FASTAT_b;
+ };
+ __IM uint8_t RESERVED1;
+ __IM uint16_t RESERVED2;
+
+ union
+ {
+ __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */
+
+ struct
+ {
+ uint8_t : 3;
+ __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */
+ __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */
+ uint8_t : 2;
+ __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */
+ } FAEINT_b;
+ };
+ __IM uint8_t RESERVED3;
+ __IM uint16_t RESERVED4;
+
+ union
+ {
+ __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */
+
+ struct
+ {
+ __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */
+ uint8_t : 7;
+ } FRDYIE_b;
+ };
+ __IM uint8_t RESERVED5;
+ __IM uint16_t RESERVED6;
+ __IM uint32_t RESERVED7[5];
+
+ union
+ {
+ __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */
+
+ struct
+ {
+ __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area
+ * These bits can be written when FRDY bit of FSTATR register
+ * is '1'. Writing to these bits in FRDY = '0' is ignored. */
+ } FSADDR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */
+
+ struct
+ {
+ __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
+ * end address of target area in 'Blank Check' command. These
+ * bits can be written when FRDY bit of FSTATR register is
+ * '1'. Writing to these bits in FRDY = '0' is ignored. */
+ } FEADDR_b;
+ };
+ __IM uint32_t RESERVED8[3];
+
+ union
+ {
+ __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */
+
+ struct
+ {
+ __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
+ * is only possible when the FRDY bit in the FSTATR register
+ * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
+ * to this bit is only possible when 16 bits are written and
+ * the value written to the KEY bits is D9h.Written values
+ * are not retained by these bits (always read as 0x00).Only
+ * secure access can write to this register. Both secure access
+ * and non-secure read access are allowed. Non-secure writeaccess
+ * is denied, but TrustZo */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FMEPROT_b;
+ };
+ __IM uint16_t RESERVED9;
+ __IM uint32_t RESERVED10[12];
+
+ union
+ {
+ __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */
+
+ struct
+ {
+ __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
+ * written when the FRDY bit in the FSTATR register is 1.
+ * Writing to this bit is ignored when the FRDY bit is 0.Writing
+ * to this bit is only possible when 16 bits are written and
+ * the value written to the KEY[7:0] bits is 0x78.Written
+ * values are not retained by these bits (always read as 0x00). */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FBPROT0_b;
+ };
+ __IM uint16_t RESERVED11;
+
+ union
+ {
+ __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */
+
+ struct
+ {
+ __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit
+ * is only possible when the FRDY bit in the FSTATR register
+ * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
+ * to this bit is only possible when 16 bits are written and
+ * the value written to the KEY[7:0] bits is 0xB1.Written
+ * values are not retained by these bits (always read as 0x00). */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FBPROT1_b;
+ };
+ __IM uint16_t RESERVED12;
+
+ union
+ {
+ __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */
+
+ struct
+ {
+ uint32_t : 6;
+ __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */
+ uint32_t : 1;
+ __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */
+ __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */
+ __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */
+ __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */
+ __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */
+ __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */
+ __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */
+ __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */
+ uint32_t : 4;
+ __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */
+ __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */
+ __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */
+ __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */
+ uint32_t : 8;
+ } FSTATR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */
+
+ struct
+ {
+ __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
+ * FRDY bit in FSTATR register is '1'. Writing to this bit
+ * in FRDY = '0' is ignored. Writing to these bits is enabled
+ * only when this register is accessed in 16-bit size and
+ * H'AA is written to KEY bits */
+ uint16_t : 6;
+ __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
+ * FRDY bit in FSTATR register is '1'. Writing to this bit
+ * in FRDY = '0' is ignored. Writing to these bits is enabled
+ * only when this register is accessed in 16-bit size and
+ * H'AA is written to KEY bits. */
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FENTRYR_b;
+ };
+ __IM uint16_t RESERVED13;
+ __IM uint32_t RESERVED14;
+
+ union
+ {
+ __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */
+
+ struct
+ {
+ __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
+ * bit of FSTATR register is '1'. Writing to this bit in FRDY
+ * = '0' is ignored. Writing to these bits is enabled only
+ * when this register is accessed in 16-bit size and H'2D
+ * is written to KEY bits. */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FSUINITR_b;
+ };
+ __IM uint16_t RESERVED15;
+ __IM uint32_t RESERVED16[4];
+
+ union
+ {
+ __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */
+
+ struct
+ {
+ __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */
+ __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */
+ } FCMDR_b;
+ };
+ __IM uint16_t RESERVED17;
+ __IM uint32_t RESERVED18[11];
+
+ union
+ {
+ __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */
+
+ struct
+ {
+ __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */
+ uint8_t : 7;
+ } FBCCNT_b;
+ };
+ __IM uint8_t RESERVED19;
+ __IM uint16_t RESERVED20;
+
+ union
+ {
+ __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */
+
+ struct
+ {
+ __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */
+ uint8_t : 7;
+ } FBCSTAT_b;
+ };
+ __IM uint8_t RESERVED21;
+ __IM uint16_t RESERVED22;
+
+ union
+ {
+ __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */
+
+ struct
+ {
+ __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
+ * of the first programmed data which is found in 'Blank Check'
+ * command execution. */
+ uint32_t : 13;
+ } FPSADDR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */
+
+ struct
+ {
+ __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
+ * indicate the start sector address for setting the access
+ * window that is located in the configuration area. */
+ uint32_t : 4;
+ __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot
+ * Flag and Temporary Boot Swap Control and 'Config Clear'
+ * command execution */
+ __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits
+ * indicate the end sector address for setting the access
+ * window that is located in the configuration area. */
+ uint32_t : 4;
+ __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */
+ } FAWMON_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */
+
+ struct
+ {
+ __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */
+ uint16_t : 15;
+ } FCPSR_b;
+ };
+ __IM uint16_t RESERVED23;
+
+ union
+ {
+ __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */
+
+ struct
+ {
+ __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
+ * can be written when FRDY bit in FSTATR register is '1'.
+ * Writing to this bit in FRDY = '0' is ignored. Writing to
+ * these bits is enabled only when this register is accessed
+ * in 16-bit size and H'1E is written to KEY bits. */
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FPCKAR_b;
+ };
+ __IM uint16_t RESERVED24;
+
+ union
+ {
+ __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */
+
+ struct
+ {
+ __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY
+ * bit in FSTATR register is '1'. Writing to this bit in FRDY
+ * = '0' is ignored. Writing to these bits is enabled only
+ * when this register is accessed in 16-bit size and H'66
+ * is written to KEY bits. */
+ uint16_t : 6;
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
+ } FSUACR_b;
+ };
+ __IM uint16_t RESERVED25;
+} R_FACI_HP_Type; /*!< Size = 236 (0xec) */
+
+/* =========================================================================================================================== */
+/* ================ R_FCACHE ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Memory Cache (R_FCACHE)
+ */
+
+typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */
+{
+ __IM uint16_t RESERVED[128];
+
+ union
+ {
+ __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */
+
+ struct
+ {
+ __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */
+ uint16_t : 15;
+ } FCACHEE_b;
+ };
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */
+
+ struct
+ {
+ __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */
+ uint16_t : 15;
+ } FCACHEIV_b;
+ };
+ __IM uint16_t RESERVED2[11];
+
+ union
+ {
+ __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */
+
+ struct
+ {
+ __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */
+ uint8_t : 5;
+ } FLWT_b;
+ };
+ __IM uint8_t RESERVED3;
+ __IM uint16_t RESERVED4[17];
+
+ union
+ {
+ __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */
+
+ struct
+ {
+ __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */
+ uint16_t : 7;
+ __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */
+ uint16_t : 7;
+ } FSAR_b;
+ };
+} R_FCACHE_Type; /*!< Size = 322 (0x142) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer (R_GPT0)
+ */
+
+typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */
+{
+ union
+ {
+ __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */
+
+ struct
+ {
+ __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */
+ __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */
+ __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */
+ __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */
+ __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */
+ uint32_t : 3;
+ __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */
+ uint32_t : 16;
+ } GTWP_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */
+
+ struct
+ {
+ __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
+ * means counter running. */
+ } GTSTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */
+
+ struct
+ {
+ __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+ * counter status (GTCR.CST bit). 0 means counter runnning.
+ * 1 means counter stop. */
+ } GTSTP_b;
+ };
+
+ union
+ {
+ __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */
+
+ struct
+ {
+ __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */
+ __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */
+ } GTCLR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */
+
+ struct
+ {
+ __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */
+ __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */
+ __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * Counter Start Enable */
+ __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * Counter Start Enable */
+ __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */
+ __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */
+ uint32_t : 7;
+ __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */
+ } GTSSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */
+
+ struct
+ {
+ __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */
+ __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */
+ __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * Counter Stop Enable */
+ __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */
+ __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */
+ uint32_t : 7;
+ __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */
+ } GTPSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */
+
+ struct
+ {
+ __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */
+ __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */
+ __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * Counter Clear Enable */
+ __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */
+ __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
+ * Source Counter Clear Enable. */
+ __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
+ * Enable (This bit is only available in GPT324 to GPT329.
+ * In GPT320 to GPT323, this bit is read as 0. The write value
+ * should be 0.) */
+ uint32_t : 3;
+ __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */
+ } GTCSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */
+
+ struct
+ {
+ __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */
+ __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */
+ __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * Counter Count Up Enable */
+ __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */
+ __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */
+ uint32_t : 4;
+ } GTUPSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */
+
+ struct
+ {
+ __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */
+ __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */
+ __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * Counter Count Down Enable */
+ __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */
+ __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */
+ uint32_t : 4;
+ } GTDNSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+ * Register A */
+
+ struct
+ {
+ __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
+ * Enable */
+ __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
+ * Enable */
+ __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
+ * Enable */
+ __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
+ * Enable */
+ __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */
+ uint32_t : 8;
+ } GTICASR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+ * Register B */
+
+ struct
+ {
+ __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
+ * Enable */
+ __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
+ * Enable */
+ __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
+ * Enable */
+ __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
+ * Enable */
+ __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+ * GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */
+ uint32_t : 8;
+ } GTICBSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */
+
+ struct
+ {
+ __IOM uint32_t CST : 1; /*!< [0..0] Count Start */
+ uint32_t : 7;
+ __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */
+ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */
+ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */
+ __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */
+ uint32_t : 2;
+ __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */
+ __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */
+ uint32_t : 3;
+ __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */
+ __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */
+ uint32_t : 3;
+ } GTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */
+ __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */
+ uint32_t : 14;
+ __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */
+ __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */
+ __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
+ * percent Duty Setting */
+ uint32_t : 4;
+ __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */
+ __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */
+ __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
+ * percent Duty Setting */
+ uint32_t : 4;
+ } GTUDDTYC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */
+
+ struct
+ {
+ __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */
+ __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
+ * Clear Disable.(This bit is only available in GPT324 to
+ * GPT329. In GPT320 to GPT323, this bit is read as 0. The
+ * write value should be 0.) */
+ __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */
+ __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */
+ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */
+ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */
+ __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
+ * bit is only available in GPT324 to GPT329. In GPT320 to
+ * GPT323, this bit is read as 0. The write value should be
+ * 0.) */
+ __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */
+ __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */
+ __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */
+ __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */
+ uint32_t : 1;
+ __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */
+ __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */
+ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */
+ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */
+ __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
+ * bit is only available in GPT324 to GPT329. In GPT320 to
+ * GPT323, this bit is read as 0. The write value should be
+ * 0.) */
+ uint32_t : 1;
+ __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */
+ __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */
+ } GTIOR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+ * Clear Enable */
+ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+ * Clear Enable */
+ __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+ * Synchronous Clear Enable */
+ __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+ * Synchronous Clear Enable */
+ __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+ * Synchronous Clear Enable */
+ __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+ * Synchronous Clear Enable */
+ __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */
+ __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */
+ __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+ * Start Request Enable */
+ __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+ * Conversion Start Request Enable */
+ __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+ * Start Request Enable */
+ __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+ * Conversion Start Request Enable */
+ uint32_t : 4;
+ __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */
+ uint32_t : 2;
+ __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */
+ __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
+ __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
+ __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */
+ } GTINTAD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */
+
+ struct
+ {
+ __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */
+ __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */
+ __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */
+ __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */
+ __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */
+ __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */
+ __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */
+ __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */
+ __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
+ * for counting the number of times a timer interrupt has
+ * been skipped.) */
+ uint32_t : 4;
+ __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */
+ __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
+ * Request Interrupt Enable */
+ __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
+ * Start Request Flag */
+ __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
+ * Request Flag */
+ __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
+ * Start Request Flag */
+ uint32_t : 4;
+ __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */
+ uint32_t : 3;
+ __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */
+ __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
+ __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
+ __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */
+ } GTST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */
+
+ struct
+ {
+ __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */
+ __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */
+ __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */
+ __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */
+ uint32_t : 4;
+ __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */
+ uint32_t : 1;
+ __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */
+ uint32_t : 5;
+ __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */
+ __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */
+ __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */
+ __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+ * is read as 0. */
+ uint32_t : 1;
+ __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+ * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+ * at an underflow (in down-counting) or overflow (in up-counting)
+ * is performed. */
+ __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */
+ uint32_t : 1;
+ __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+ * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+ * at an underflow (in down-counting) or overflow (in up-counting)
+ * is performed. */
+ __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */
+ uint32_t : 1;
+ } GTBER_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+ * Start Request Skipping Setting Register */
+
+ struct
+ {
+ __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */
+ __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */
+ __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */
+ __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */
+ __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */
+ __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */
+ __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */
+ __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */
+ uint32_t : 1;
+ __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */
+ uint32_t : 1;
+ __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */
+ uint32_t : 17;
+ } GTITC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */
+
+ struct
+ {
+ __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */
+ } GTCNT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */
+
+ struct
+ {
+ __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */
+ } GTCCR_b[6];
+ };
+
+ union
+ {
+ __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */
+
+ struct
+ {
+ __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */
+ } GTPR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */
+
+ struct
+ {
+ __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */
+ } GTPBR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */
+ } GTPDBR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */
+
+ struct
+ {
+ __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */
+ } GTADTRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+ * A */
+
+ struct
+ {
+ __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */
+ } GTADTBRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+ * Register A */
+
+ struct
+ {
+ __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+ * A */
+ } GTADTDBRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */
+
+ struct
+ {
+ __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */
+ } GTADTRB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+ * B */
+
+ struct
+ {
+ __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */
+ } GTADTBRB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+ * Register B */
+
+ struct
+ {
+ __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+ * B */
+ } GTADTDBRB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */
+
+ struct
+ {
+ __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */
+ uint32_t : 3;
+ __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */
+ __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */
+ uint32_t : 2;
+ __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */
+ uint32_t : 23;
+ } GTDTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */
+
+ struct
+ {
+ __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */
+ } GTDVU_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */
+
+ struct
+ {
+ __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */
+ } GTDVD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */
+
+ struct
+ {
+ __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */
+ } GTDBU_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */
+
+ struct
+ {
+ __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */
+ } GTDBD_b;
+ };
+
+ union
+ {
+ __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+ * Status Register */
+
+ struct
+ {
+ __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */
+ uint32_t : 30;
+ } GTSOS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+ * Temporary Release Register */
+
+ struct
+ {
+ __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */
+ uint32_t : 31;
+ } GTSOTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+ * Signal Monitoring Register */
+
+ struct
+ {
+ __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+ * Enabling */
+ uint32_t : 7;
+ __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+ * Enabling */
+ uint32_t : 7;
+ } GTADSMR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+ * Counter Control Register */
+
+ struct
+ {
+ __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */
+ uint32_t : 2;
+ __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */
+ uint32_t : 4;
+ __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */
+ __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+ * select */
+ uint32_t : 2;
+ __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */
+ __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */
+ __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */
+ } GTEITC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+ * Setting Register 1 */
+
+ struct
+ {
+ __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+ * Extended Skipping Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+ * Extended Skipping Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */
+ uint32_t : 1;
+ } GTEITLI1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+ * Setting Register 2 */
+
+ struct
+ {
+ __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+ * Skipping Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+ * Skipping Function Select */
+ uint32_t : 25;
+ } GTEITLI2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+ * Setting Register */
+
+ struct
+ {
+ __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+ * Select */
+ uint32_t : 1;
+ __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+ * Select */
+ uint32_t : 1;
+ __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+ * Select */
+ uint32_t : 5;
+ __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+ * Function Select */
+ uint32_t : 1;
+ __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+ * Select */
+ uint32_t : 1;
+ __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+ * Select */
+ uint32_t : 1;
+ } GTEITLB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
+ * Function Setting Register */
+
+ struct
+ {
+ __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */
+ uint32_t : 1;
+ __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */
+ uint32_t : 6;
+ __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */
+ uint32_t : 1;
+ __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */
+ uint32_t : 6;
+ } GTICLF_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */
+
+ struct
+ {
+ __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */
+ uint32_t : 7;
+ __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */
+ uint32_t : 7;
+ __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */
+ uint32_t : 4;
+ } GTPC_b;
+ };
+ __IM uint32_t RESERVED[4];
+
+ union
+ {
+ __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+ * Control Channel Select Register */
+
+ struct
+ {
+ __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
+ * Select */
+ uint32_t : 22;
+ } GTSECSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+ * Control Register */
+
+ struct
+ {
+ __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */
+ __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */
+ __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */
+ __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */
+ uint32_t : 4;
+ __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */
+ __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */
+ __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */
+ __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */
+ uint32_t : 4;
+ __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */
+ __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */
+ uint32_t : 6;
+ __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */
+ __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */
+ uint32_t : 6;
+ } GTSECR_b;
+ };
+ __IM uint32_t RESERVED1[2];
+
+ union
+ {
+ __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */
+ __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+ * Disable */
+ uint32_t : 2;
+ __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+ * Enable */
+ __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+ * Enable */
+ uint32_t : 1;
+ __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+ * Enable */
+ __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+ * Enable */
+ uint32_t : 1;
+ __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+ * Disable */
+ __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+ * Transfer Disable */
+ uint32_t : 2;
+ __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */
+ __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */
+ __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */
+ __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */
+ uint32_t : 2;
+ } GTBER2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */
+
+ struct
+ {
+ __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */
+ uint32_t : 11;
+ __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */
+ uint32_t : 11;
+ } GTOLBR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+ * Capture Control Register */
+
+ struct
+ {
+ __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+ * to Other Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+ * to Other Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+ * Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+ * Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+ * Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+ * Channel GTCCRA Input Capture Source Enable */
+ __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+ * Source Enable */
+ __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+ * Source Enable */
+ __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+ * Capture Source Enable */
+ uint32_t : 5;
+ __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */
+ __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+ * to Other Channel GTCCRB Input Capture Source Enable */
+ __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+ * to Other Channel GTCCRB Input Capture Source Enable */
+ __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+ * Other Channel GTCCRB Input Capture Source Enable */
+ __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+ * Other Channel GTCCRB Input Capture Source Enable */
+ __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+ * Other Channel GTCCRb Input Capture Source Enable */
+ __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+ * Other Channel GTCCRB Input Capture Source Enable */
+ __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+ * Source Enable */
+ __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+ * Capture Source Enable */
+ __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+ * Capture Source Enable */
+ uint32_t : 5;
+ __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */
+ } GTICCR_b;
+ };
+} R_GPT0_Type; /*!< Size = 240 (0xf0) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT_OPS ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Output Phase Switching for GPT (R_GPT_OPS)
+ */
+
+typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */
+{
+ union
+ {
+ __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */
+
+ struct
+ {
+ __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
+ * by the software settings.This bit setting is valid when
+ * the OPSCR.FB bit = 1. */
+ __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
+ * by the software settings.This bit setting is valid when
+ * the OPSCR.FB bit = 1. */
+ __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
+ * by the software settings.This bit setting is valid when
+ * the OPSCR.FB bit = 1. */
+ uint32_t : 1;
+ __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+ * e settings (UF/VF/WF) */
+ __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+ * e settings (UF/VF/WF) */
+ __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+ * e settings (UF/VF/WF) */
+ uint32_t : 1;
+ __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */
+ uint32_t : 7;
+ __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the
+ * input phase from the software settings and external input. */
+ __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */
+ __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */
+ __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */
+ __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */
+ __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */
+ uint32_t : 2;
+ __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */
+ __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */
+ uint32_t : 2;
+ __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */
+ __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
+ * sampling clock setting of the external input. */
+ } OPSCR_b;
+ };
+} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT_POEG0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable for GPT (R_GPT_POEG0)
+ */
+
+typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */
+{
+ union
+ {
+ __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */
+
+ struct
+ {
+ __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */
+ __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */
+ __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */
+ __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */
+ __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only
+ * once after a reset. */
+ __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
+ * only once after a reset. */
+ uint32_t : 1;
+ __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
+ * only once after a reset. */
+ uint32_t : 2;
+ __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */
+ uint32_t : 11;
+ __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */
+ __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */
+ __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */
+ } POEGG_b;
+ };
+} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */
+
+/* =========================================================================================================================== */
+/* ================ R_ICU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller Unit (R_ICU)
+ */
+
+typedef struct /*!< (@ 0x40006000) R_ICU Structure */
+{
+ union
+ {
+ __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */
+
+ struct
+ {
+ __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */
+ uint8_t : 2;
+ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */
+ uint8_t : 1;
+ __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */
+ } IRQCR_b[16];
+ };
+ __IM uint32_t RESERVED[60];
+
+ union
+ {
+ __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */
+
+ struct
+ {
+ __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */
+ uint8_t : 3;
+ __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */
+ uint8_t : 1;
+ __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */
+ } NMICR_b;
+ };
+ __IM uint8_t RESERVED1;
+ __IM uint16_t RESERVED2;
+ __IM uint32_t RESERVED3[7];
+
+ union
+ {
+ __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */
+ __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */
+ __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */
+ __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */
+ __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */
+ uint16_t : 1;
+ __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */
+ __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */
+ __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */
+ __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */
+ __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */
+ __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */
+ __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */
+ __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */
+ uint16_t : 1;
+ __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */
+ } NMIER_b;
+ };
+ __IM uint16_t RESERVED4;
+ __IM uint32_t RESERVED5[3];
+
+ union
+ {
+ __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */
+
+ struct
+ {
+ __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */
+ __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */
+ __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */
+ __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */
+ __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */
+ uint16_t : 1;
+ __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */
+ __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */
+ __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */
+ __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */
+ __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */
+ __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */
+ __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */
+ __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */
+ uint16_t : 1;
+ __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */
+ } NMICLR_b;
+ };
+ __IM uint16_t RESERVED6;
+ __IM uint32_t RESERVED7[3];
+
+ union
+ {
+ __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */
+
+ struct
+ {
+ __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */
+ __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */
+ __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */
+ __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */
+ __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */
+ uint16_t : 1;
+ __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */
+ __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */
+ __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */
+ __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */
+ __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */
+ __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */
+ __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */
+ __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */
+ uint16_t : 1;
+ __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */
+ } NMISR_b;
+ };
+ __IM uint16_t RESERVED8;
+ __IM uint32_t RESERVED9[23];
+
+ union
+ {
+ __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */
+ __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */
+ __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */
+ __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */
+ __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */
+ __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */
+ uint32_t : 1;
+ __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */
+ __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */
+ __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */
+ __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */
+ __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */
+ __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */
+ __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */
+ __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
+ * enable */
+ __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
+ * enable */
+ __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */
+ } WUPEN_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */
+
+ struct
+ {
+ __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */
+ __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
+ * bit */
+ __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
+ * bit */
+ uint32_t : 29;
+ } WUPEN1_b;
+ };
+ __IM uint32_t RESERVED10[6];
+
+ union
+ {
+ __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */
+
+ struct
+ {
+ __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
+ * = 1) */
+ __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
+ * LPOPTEN bit = 1) */
+ uint8_t : 6;
+ } IELEN_b;
+ };
+ __IM uint8_t RESERVED11;
+ __IM uint16_t RESERVED12;
+ __IM uint32_t RESERVED13[15];
+
+ union
+ {
+ __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */
+
+ struct
+ {
+ __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */
+ uint16_t : 7;
+ } SELSR0_b;
+ };
+ __IM uint16_t RESERVED14;
+ __IM uint32_t RESERVED15[31];
+
+ union
+ {
+ __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */
+
+ struct
+ {
+ __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */
+ uint32_t : 7;
+ __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+ * IR flag is prohibited. */
+ uint32_t : 15;
+ } DELSR_b[8];
+ };
+ __IM uint32_t RESERVED16[24];
+
+ union
+ {
+ __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */
+
+ struct
+ {
+ __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event
+ * signal to be linked . */
+ uint32_t : 7;
+ __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */
+ uint32_t : 7;
+ __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */
+ uint32_t : 7;
+ } IELSR_b[96];
+ };
+} R_ICU_Type; /*!< Size = 1152 (0x480) */
+
+/* =========================================================================================================================== */
+/* ================ R_IIC0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface (R_IIC0)
+ */
+
+typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */
+{
+ union
+ {
+ __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */
+
+ struct
+ {
+ __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */
+ __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */
+ __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */
+ __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */
+ __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */
+ __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */
+ __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
+ * is initiated using the IICRST bit for a bus hang-up occurred
+ * during communication with the master device in slave mode,
+ * the states may become different between the slave device
+ * and the master device (due to the difference in the bit
+ * counter information). */
+ __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */
+ } ICCR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */
+
+ struct
+ {
+ uint8_t : 1;
+ __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
+ * condition issuance request) when the BBSY flag is set to
+ * 0 (bus free state). */
+ __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
+ * RS bit to 1 while issuing a stop condition. */
+ __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
+ * bit is not possible while the setting of the BBSY flag
+ * is 0 (bus free state).Note: Do not set the SP bit to 1
+ * while a restart condition is being issued. */
+ uint8_t : 1;
+ __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */
+ __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */
+ __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */
+ } ICCR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */
+
+ struct
+ {
+ __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */
+ __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */
+ __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
+ * / 2^CKS ) */
+ __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */
+ } ICMR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */
+
+ struct
+ {
+ __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */
+ __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */
+ __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */
+ uint8_t : 1;
+ __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */
+ __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */
+ } ICMR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */
+
+ struct
+ {
+ __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */
+ __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */
+ __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */
+ __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */
+ __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */
+ __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
+ * be sure to read the ICDRR beforehand. */
+ __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */
+ } ICMR3_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */
+
+ struct
+ {
+ __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */
+ __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */
+ __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */
+ __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */
+ __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */
+ __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */
+ __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */
+ __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */
+ } ICFER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */
+
+ struct
+ {
+ __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */
+ __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */
+ __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */
+ __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */
+ uint8_t : 1;
+ __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */
+ uint8_t : 1;
+ __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */
+ } ICSER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */
+ __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */
+ __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */
+ __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */
+ __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */
+ __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */
+ __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */
+ } ICIER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */
+
+ struct
+ {
+ __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */
+ __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */
+ __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */
+ __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */
+ uint8_t : 1;
+ __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */
+ uint8_t : 1;
+ __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */
+ } ICSR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */
+
+ struct
+ {
+ __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */
+ __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */
+ __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */
+ __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */
+ __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */
+ __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */
+ __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */
+ __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
+ } ICSR2_b;
+ };
+ __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */
+
+ union
+ {
+ __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */
+
+ struct
+ {
+ __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */
+ uint8_t : 3;
+ } ICBRL_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */
+
+ struct
+ {
+ __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */
+ uint8_t : 3;
+ } ICBRH_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */
+
+ struct
+ {
+ __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */
+ } ICDRT_b;
+ };
+
+ union
+ {
+ __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */
+
+ struct
+ {
+ __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */
+ } ICDRR_b;
+ };
+ __IM uint8_t RESERVED[2];
+
+ union
+ {
+ __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */
+
+ struct
+ {
+ __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */
+ uint8_t : 3;
+ __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */
+ __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */
+ __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */
+ __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */
+ } ICWUR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */
+
+ struct
+ {
+ __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */
+ __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */
+ __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */
+ uint8_t : 5;
+ } ICWUR2_b;
+ };
+} R_IIC0_Type; /*!< Size = 24 (0x18) */
+
+/* =========================================================================================================================== */
+/* ================ R_IWDT ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Independent Watchdog Timer (R_IWDT)
+ */
+
+typedef struct /*!< (@ 0x40083200) R_IWDT Structure */
+{
+ union
+ {
+ __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */
+
+ struct
+ {
+ __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
+ * 0xFF to this register. */
+ } IWDTRR_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */
+
+ struct
+ {
+ __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */
+ uint16_t : 2;
+ __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */
+ __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */
+ uint16_t : 2;
+ __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */
+ uint16_t : 2;
+ } IWDTCR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */
+
+ struct
+ {
+ __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */
+ __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
+ __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
+ } IWDTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */
+ } IWDTRCR_b;
+ };
+ __IM uint8_t RESERVED1;
+
+ union
+ {
+ __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */
+ } IWDTCSTPR_b;
+ };
+ __IM uint8_t RESERVED2;
+ __IM uint16_t RESERVED3;
+} R_IWDT_Type; /*!< Size = 12 (0xc) */
+
+/* =========================================================================================================================== */
+/* ================ R_I3C0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I3C Bus Interface (R_I3C0)
+ */
+
+typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */
+{
+ union
+ {
+ __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */
+
+ struct
+ {
+ __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */
+ uint32_t : 31;
+ } PRTS_b;
+ };
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */
+
+ struct
+ {
+ __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */
+ uint32_t : 31;
+ } CECTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */
+
+ struct
+ {
+ __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */
+ uint32_t : 6;
+ __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */
+ __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */
+ uint32_t : 20;
+ __IOM uint32_t ABT : 1; /*!< [29..29] Abort */
+ __IOM uint32_t RSM : 1; /*!< [30..30] Resume */
+ __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */
+ } BCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */
+ uint32_t : 8;
+ __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */
+ } MSDVAD_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */
+
+ struct
+ {
+ __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */
+ __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */
+ __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */
+ __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */
+ __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */
+ __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */
+ __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */
+ uint32_t : 9;
+ __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */
+ uint32_t : 15;
+ } RSTCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */
+
+ struct
+ {
+ uint32_t : 2;
+ __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */
+ uint32_t : 1;
+ __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */
+ uint32_t : 2;
+ __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */
+ uint32_t : 24;
+ } PRSST_b;
+ };
+ __IM uint32_t RESERVED2[2];
+
+ union
+ {
+ __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */
+ uint32_t : 21;
+ } INST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */
+ uint32_t : 21;
+ } INSTE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */
+
+ struct
+ {
+ uint32_t : 10;
+ __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */
+ uint32_t : 21;
+ } INIE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */
+
+ struct
+ {
+ uint32_t : 10;
+ __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */
+ uint32_t : 21;
+ } INSTFC_b;
+ };
+ __IM uint32_t RESERVED3;
+
+ union
+ {
+ __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */
+
+ struct
+ {
+ uint32_t : 19;
+ __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */
+ uint32_t : 8;
+ } DVCT_b;
+ };
+ __IM uint32_t RESERVED4[4];
+
+ union
+ {
+ __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */
+
+ struct
+ {
+ __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */
+ __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */
+ uint32_t : 1;
+ __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */
+ uint32_t : 28;
+ } IBINCTL_b;
+ };
+ __IM uint32_t RESERVED5;
+
+ union
+ {
+ __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */
+
+ struct
+ {
+ __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */
+ __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */
+ __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */
+ uint32_t : 5;
+ __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */
+ uint32_t : 3;
+ __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */
+ uint32_t : 1;
+ __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */
+ __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */
+ uint32_t : 16;
+ } BFCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */
+
+ struct
+ {
+ __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */
+ uint32_t : 4;
+ __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */
+ __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */
+ uint32_t : 8;
+ __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */
+ __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */
+ uint32_t : 15;
+ } SVCTL_b;
+ };
+ __IM uint32_t RESERVED6[2];
+
+ union
+ {
+ __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */
+
+ struct
+ {
+ __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */
+ uint32_t : 29;
+ } REFCKCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */
+
+ struct
+ {
+ __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */
+ __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */
+ __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */
+ uint32_t : 2;
+ __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */
+ uint32_t : 1;
+ __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */
+ } STDBR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */
+
+ struct
+ {
+ __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */
+ __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */
+ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */
+ uint32_t : 2;
+ __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */
+ uint32_t : 2;
+ } EXTBR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */
+
+ struct
+ {
+ __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */
+ uint32_t : 23;
+ } BFRECDT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */
+
+ struct
+ {
+ __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */
+ uint32_t : 23;
+ } BAVLCDT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */
+
+ struct
+ {
+ __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */
+ uint32_t : 14;
+ } BIDLCDT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */
+
+ struct
+ {
+ __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */
+ __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */
+ __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */
+ uint32_t : 1;
+ __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */
+ uint32_t : 3;
+ __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */
+ uint32_t : 4;
+ __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */
+ uint32_t : 16;
+ } OUTCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */
+
+ struct
+ {
+ __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */
+ __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */
+ uint32_t : 27;
+ } INCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */
+
+ struct
+ {
+ __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */
+ uint32_t : 2;
+ __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */
+ __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */
+ __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */
+ uint32_t : 24;
+ } TMOCTL_b;
+ };
+ __IM uint32_t RESERVED7;
+
+ union
+ {
+ __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */
+
+ struct
+ {
+ __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */
+ uint32_t : 3;
+ __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */
+ uint32_t : 1;
+ __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */
+ __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */
+ uint32_t : 24;
+ } WUCTL_b;
+ };
+ __IM uint32_t RESERVED8;
+
+ union
+ {
+ __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */
+
+ struct
+ {
+ __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */
+ __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */
+ __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */
+ uint32_t : 29;
+ } ACKCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */
+
+ struct
+ {
+ __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */
+ __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */
+ uint32_t : 30;
+ } SCSTRCTL_b;
+ };
+ __IM uint32_t RESERVED9[2];
+
+ union
+ {
+ __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */
+
+ struct
+ {
+ __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */
+ uint32_t : 12;
+ __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */
+ __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */
+ __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */
+ __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */
+ } SCSTLCTL_b;
+ };
+ __IM uint32_t RESERVED10[3];
+
+ union
+ {
+ __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */
+ } SVTDLG0_b;
+ };
+ __IM uint32_t RESERVED11[31];
+
+ union
+ {
+ __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */
+
+ struct
+ {
+ __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */
+ __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */
+ __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */
+ uint32_t : 29;
+ } CNDCTL_b;
+ };
+ __IM uint32_t RESERVED12[3];
+ __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */
+ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */
+ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */
+ __IM uint32_t RESERVED13[8];
+ __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */
+ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */
+ __IM uint32_t RESERVED14[3];
+
+ union
+ {
+ __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */
+
+ struct
+ {
+ __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */
+ __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */
+ __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */
+ __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */
+ } NQTHCTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
+ * Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */
+ uint32_t : 5;
+ __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */
+ uint32_t : 5;
+ __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */
+ uint32_t : 5;
+ __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */
+ uint32_t : 5;
+ } NTBTHCTL0_b;
+ };
+ __IM uint32_t RESERVED15[10];
+
+ union
+ {
+ __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */
+ uint32_t : 24;
+ } NRQTHCTL_b;
+ };
+ __IM uint32_t RESERVED16[3];
+
+ union
+ {
+ __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */
+
+ struct
+ {
+ __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */
+ __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */
+ __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */
+ uint32_t : 1;
+ __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */
+ uint32_t : 3;
+ __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */
+ uint32_t : 7;
+ __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */
+ uint32_t : 3;
+ __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */
+ uint32_t : 11;
+ } BST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */
+
+ struct
+ {
+ __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */
+ __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */
+ __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */
+ uint32_t : 1;
+ __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */
+ uint32_t : 3;
+ __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */
+ uint32_t : 7;
+ __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */
+ uint32_t : 3;
+ __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */
+ uint32_t : 11;
+ } BSTE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */
+ __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */
+ __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */
+ uint32_t : 3;
+ __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */
+ uint32_t : 7;
+ __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */
+ uint32_t : 3;
+ __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */
+ uint32_t : 11;
+ } BIE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */
+
+ struct
+ {
+ __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */
+ __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */
+ __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */
+ uint32_t : 1;
+ __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */
+ uint32_t : 3;
+ __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */
+ uint32_t : 7;
+ __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */
+ uint32_t : 3;
+ __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */
+ uint32_t : 11;
+ } BSTFC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */
+
+ struct
+ {
+ __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */
+ __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */
+ __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */
+ __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */
+ __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */
+ __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */
+ uint32_t : 3;
+ __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */
+ uint32_t : 10;
+ __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */
+ uint32_t : 11;
+ } NTST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */
+
+ struct
+ {
+ __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */
+ __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */
+ __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */
+ __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */
+ __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */
+ __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */
+ uint32_t : 3;
+ __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */
+ uint32_t : 10;
+ __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */
+ uint32_t : 11;
+ } NTSTE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */
+ __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */
+ __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */
+ __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */
+ __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */
+ __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */
+ uint32_t : 3;
+ __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */
+ uint32_t : 10;
+ __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */
+ uint32_t : 11;
+ } NTIE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */
+
+ struct
+ {
+ __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */
+ __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */
+ __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */
+ __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */
+ __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */
+ __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */
+ uint32_t : 3;
+ __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */
+ uint32_t : 10;
+ __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */
+ uint32_t : 11;
+ } NTSTFC_b;
+ };
+ __IM uint32_t RESERVED17[8];
+
+ union
+ {
+ __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */
+
+ struct
+ {
+ __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */
+ __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */
+ __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */
+ uint32_t : 29;
+ } BCST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */
+
+ struct
+ {
+ __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */
+ uint32_t : 4;
+ __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */
+ __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */
+ uint32_t : 8;
+ __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */
+ __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */
+ uint32_t : 15;
+ } SVST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */
+
+ struct
+ {
+ __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */
+ uint32_t : 31;
+ } WUST_b;
+ };
+ __IM uint32_t RESERVED18[2];
+
+ union
+ {
+ __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */
+
+ struct
+ {
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
+ uint32_t : 5;
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
+ uint32_t : 5;
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
+ } DATBAS0_b;
+ };
+ __IM uint32_t RESERVED19;
+
+ union
+ {
+ __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */
+
+ struct
+ {
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
+ uint32_t : 5;
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
+ uint32_t : 5;
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
+ } DATBAS1_b;
+ };
+ __IM uint32_t RESERVED20;
+
+ union
+ {
+ __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */
+
+ struct
+ {
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
+ uint32_t : 5;
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
+ uint32_t : 5;
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
+ } DATBAS2_b;
+ };
+ __IM uint32_t RESERVED21;
+
+ union
+ {
+ __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */
+
+ struct
+ {
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
+ uint32_t : 5;
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
+ uint32_t : 5;
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
+ } DATBAS3_b;
+ };
+ __IM uint32_t RESERVED22[24];
+
+ union
+ {
+ __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */
+
+ struct
+ {
+ __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */
+ uint32_t : 9;
+ __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */
+ uint32_t : 5;
+ __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */
+ __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */
+ } EXDATBAS_b;
+ };
+ __IM uint32_t RESERVED23[3];
+
+ union
+ {
+ __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */
+
+ struct
+ {
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
+ uint32_t : 1;
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
+ uint32_t : 3;
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
+ uint32_t : 9;
+ } SDATBAS0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
+ uint32_t : 1;
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
+ uint32_t : 3;
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
+ uint32_t : 9;
+ } SDATBAS1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */
+
+ struct
+ {
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
+ uint32_t : 1;
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
+ uint32_t : 3;
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
+ uint32_t : 9;
+ } SDATBAS2_b;
+ };
+ __IM uint32_t RESERVED24[5];
+
+ union
+ {
+ __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
+ uint32_t : 2;
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
+ uint32_t : 16;
+ } MSDCT0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
+ uint32_t : 2;
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
+ uint32_t : 16;
+ } MSDCT1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
+ uint32_t : 2;
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
+ uint32_t : 16;
+ } MSDCT2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
+ uint32_t : 2;
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
+ uint32_t : 16;
+ } MSDCT3_b;
+ };
+ __IM uint32_t RESERVED25[16];
+
+ union
+ {
+ __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */
+
+ struct
+ {
+ __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */
+ __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
+ __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */
+ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */
+ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */
+ uint32_t : 2;
+ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */
+ uint32_t : 16;
+ } SVDCT_b;
+ };
+ __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
+ * ID Low Register */
+ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
+ * ID High Register */
+ __IM uint32_t RESERVED26;
+
+ union
+ {
+ __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */
+ uint32_t : 1;
+ __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */
+ uint32_t : 2;
+ __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */
+ __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */
+ } SVDVAD0_b;
+ };
+ __IM uint32_t RESERVED27[7];
+
+ union
+ {
+ __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */
+
+ struct
+ {
+ __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */
+ __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */
+ uint32_t : 1;
+ __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */
+ uint32_t : 28;
+ } CSECMD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */
+
+ struct
+ {
+ __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */
+ uint32_t : 28;
+ } CEACTST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */
+
+ struct
+ {
+ __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */
+ uint32_t : 16;
+ } CMWLG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */
+
+ struct
+ {
+ __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */
+ __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */
+ uint32_t : 8;
+ } CMRLG_b;
+ };
+
+ union
+ {
+ __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */
+
+ struct
+ {
+ __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */
+ uint32_t : 24;
+ } CETSTMD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */
+
+ struct
+ {
+ __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */
+ uint32_t : 1;
+ __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */
+ __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */
+ __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */
+ uint32_t : 16;
+ } CGDVST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */
+
+ struct
+ {
+ __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */
+ uint32_t : 29;
+ } CMDSPW_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */
+
+ struct
+ {
+ __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */
+ __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */
+ uint32_t : 26;
+ } CMDSPR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */
+
+ struct
+ {
+ __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */
+ uint32_t : 7;
+ __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */
+ } CMDSPT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
+ * Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */
+ __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */
+ uint32_t : 8;
+ } CETSM_b;
+ };
+ __IM uint32_t RESERVED28[2];
+
+ union
+ {
+ __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */
+
+ struct
+ {
+ __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */
+ uint32_t : 2;
+ __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */
+ uint32_t : 24;
+ } BITCNT_b;
+ };
+ __IM uint32_t RESERVED29[4];
+
+ union
+ {
+ __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */
+
+ struct
+ {
+ __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */
+ __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */
+ __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */
+ __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */
+ uint32_t : 3;
+ } NQSTLV_b;
+ };
+
+ union
+ {
+ __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */
+
+ struct
+ {
+ __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */
+ __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */
+ uint32_t : 16;
+ } NDBSTLV0_b;
+ };
+ __IM uint32_t RESERVED30[9];
+
+ union
+ {
+ __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */
+
+ struct
+ {
+ __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */
+ uint32_t : 24;
+ } NRSQSTLV_b;
+ };
+ __IM uint32_t RESERVED31[2];
+
+ union
+ {
+ __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */
+
+ struct
+ {
+ __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */
+ __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */
+ __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */
+ __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */
+ uint32_t : 28;
+ } PRSTDBG_b;
+ };
+
+ union
+ {
+ __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */
+
+ struct
+ {
+ __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */
+ uint32_t : 24;
+ } MSERRCNT_b;
+ };
+} R_I3C0_Type; /*!< Size = 980 (0x3d4) */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_MMPU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Master MPU (R_MPU_MMPU)
+ */
+
+typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */
+{
+ __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */
+} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_SMPU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Slave MPU (R_MPU_SMPU)
+ */
+
+typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */
+{
+ union
+ {
+ __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */
+
+ struct
+ {
+ __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */
+ __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */
+ uint16_t : 6;
+ __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting
+ * of the PROTECT and OAD bit. */
+ } SMPUCTL_b;
+ };
+ __IM uint16_t RESERVED[7];
+ __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */
+} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_SPMON ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
+ */
+
+typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */
+{
+ __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */
+} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */
+
+/* =========================================================================================================================== */
+/* ================ R_MSTP ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System-Module Stop (R_MSTP)
+ */
+
+typedef struct /*!< (@ 0x40084000) R_MSTP Structure */
+{
+ union
+ {
+ __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */
+
+ struct
+ {
+ __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */
+
+ struct
+ {
+ __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */
+
+ struct
+ {
+ __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */
+
+ struct
+ {
+ __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */
+
+ struct
+ {
+ __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRE_b;
+ };
+} R_MSTP_Type; /*!< Size = 20 (0x14) */
+
+/* =========================================================================================================================== */
+/* ================ R_PORT0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (R_PORT0)
+ */
+
+typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */
+{
+ union
+ {
+ union
+ {
+ __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */
+ __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */
+ } PCNTR1_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */
+
+ struct
+ {
+ __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */
+ __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */
+ __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */
+ __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */
+ __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */
+ __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */
+ __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */
+ __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */
+ __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */
+ __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */
+ __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */
+ __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */
+ __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */
+ __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */
+ __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */
+ __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */
+ } PODR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */
+
+ struct
+ {
+ __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */
+ __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */
+ __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */
+ __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */
+ __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */
+ __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */
+ __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */
+ __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */
+ __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */
+ __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */
+ __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */
+ __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */
+ __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */
+ __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */
+ __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */
+ __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */
+ } PDR_b;
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */
+
+ struct
+ {
+ __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */
+ __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */
+ } PCNTR2_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */
+
+ struct
+ {
+ __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */
+ __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */
+ __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */
+ __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */
+ __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */
+ __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */
+ __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */
+ __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */
+ __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */
+ __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */
+ __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */
+ __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */
+ __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */
+ __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */
+ __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */
+ __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */
+ } EIDR_b;
+ };
+
+ union
+ {
+ __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */
+
+ struct
+ {
+ __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */
+ __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */
+ __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */
+ __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */
+ __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */
+ __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */
+ __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */
+ __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */
+ __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */
+ __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */
+ __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */
+ __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */
+ __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */
+ __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */
+ __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */
+ __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */
+ } PIDR_b;
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */
+
+ struct
+ {
+ __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */
+ __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */
+ } PCNTR3_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */
+
+ struct
+ {
+ __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */
+ __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */
+ __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */
+ __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */
+ __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */
+ __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */
+ __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */
+ __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */
+ __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */
+ __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */
+ __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */
+ __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */
+ __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */
+ __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */
+ __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */
+ __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */
+ } PORR_b;
+ };
+
+ union
+ {
+ __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */
+
+ struct
+ {
+ __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */
+ __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */
+ __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */
+ __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */
+ __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */
+ __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */
+ __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */
+ __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */
+ __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */
+ __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */
+ __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */
+ __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */
+ __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */
+ __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */
+ __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */
+ __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */
+ } POSR_b;
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */
+
+ struct
+ {
+ __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */
+ __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */
+ } PCNTR4_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */
+
+ struct
+ {
+ __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */
+ __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */
+ __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */
+ __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */
+ __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */
+ __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */
+ __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */
+ __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */
+ __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */
+ __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */
+ __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */
+ __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */
+ __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */
+ __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */
+ __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */
+ __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */
+ } EORR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */
+
+ struct
+ {
+ __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */
+ __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */
+ __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */
+ __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */
+ __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */
+ __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */
+ __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */
+ __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */
+ __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */
+ __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */
+ __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */
+ __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */
+ __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */
+ __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */
+ __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */
+ __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */
+ } EOSR_b;
+ };
+ };
+ };
+} R_PORT0_Type; /*!< Size = 16 (0x10) */
+
+/* =========================================================================================================================== */
+/* ================ R_PFS ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-PFS (R_PFS)
+ */
+
+typedef struct /*!< (@ 0x40080800) R_PFS Structure */
+{
+ union
+ {
+ __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */
+ __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */
+ };
+} R_PFS_Type; /*!< Size = 960 (0x3c0) */
+
+/* =========================================================================================================================== */
+/* ================ R_PMISC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-MISC (R_PMISC)
+ */
+
+typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */
+{
+ union
+ {
+ __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */
+ __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */
+ uint8_t : 2;
+ } PFENET_b;
+ };
+ __IM uint8_t RESERVED[2];
+
+ union
+ {
+ __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */
+
+ struct
+ {
+ uint8_t : 6;
+ __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
+ __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
+ } PWPR_b;
+ };
+ __IM uint8_t RESERVED1;
+
+ union
+ {
+ __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */
+
+ struct
+ {
+ uint8_t : 6;
+ __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
+ __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
+ } PWPRS_b;
+ };
+ __IM uint16_t RESERVED2[5];
+ __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */
+} R_PMISC_Type; /*!< Size = 40 (0x28) */
+
+/* =========================================================================================================================== */
+/* ================ R_QSPI ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Quad Serial Peripheral Interface (R_QSPI)
+ */
+
+typedef struct /*!< (@ 0x64000000) R_QSPI Structure */
+{
+ union
+ {
+ __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */
+ uint32_t : 1;
+ __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */
+ __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */
+ __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
+ * other than on byte boundaries */
+ __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
+ * input to CFGMD3. */
+ __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
+ * the serial interface */
+ __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */
+ __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */
+ uint32_t : 3;
+ __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */
+ uint32_t : 16;
+ } SFMSMD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */
+ __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */
+ __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */
+ uint32_t : 26;
+ } SFMSSC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention
+ * to the irregularity.)NOTE: When PCLKA multiplied by an
+ * odd number is selected, the high-level width of the SCK
+ * signal is longer than the low-level width by 1 x PCLKA
+ * before duty ratio correction. */
+ __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
+ * SCK signal */
+ uint32_t : 26;
+ } SFMSKC_b;
+ };
+
+ union
+ {
+ __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */
+
+ struct
+ {
+ __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
+ * (No combination other than the above is available.) */
+ uint32_t : 1;
+ __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */
+ __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */
+ uint32_t : 24;
+ } SFMSST_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */
+
+ struct
+ {
+ __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output
+ * to and from this port is converted to a SPIbus cycle. This
+ * port is accessible in the direct communication mode (DCOM=1)
+ * only.Access to this port is ignored in the ROM access mode. */
+ uint32_t : 24;
+ } SFMCOM_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */
+
+ struct
+ {
+ __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */
+ uint32_t : 31;
+ } SFMCMD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */
+
+ struct
+ {
+ __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */
+ uint32_t : 6;
+ __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication
+ * modeNOTE: Writing of 0 only is possible. Writing of 1 is
+ * ignored. */
+ uint32_t : 24;
+ } SFMCST_b;
+ };
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */
+
+ struct
+ {
+ __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */
+ uint32_t : 24;
+ } SFMSIC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */
+ uint32_t : 2;
+ __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
+ * Interface address width is selected 4 bytes. */
+ uint32_t : 27;
+ } SFMSAC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read
+ * instructions */
+ uint32_t : 2;
+ __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */
+ __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */
+ __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */
+ uint32_t : 16;
+ } SFMSDC_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */
+
+ struct
+ {
+ __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
+ * is required to be set by software separately. */
+ uint32_t : 2;
+ __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
+ * when Dual SPI protocol or Quad SPI protocol is selected. */
+ uint32_t : 27;
+ } SFMSPC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */
+
+ struct
+ {
+ uint32_t : 2;
+ __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */
+ uint32_t : 29;
+ } SFMPMD_b;
+ };
+ __IM uint32_t RESERVED2[499];
+
+ union
+ {
+ __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */
+
+ struct
+ {
+ uint32_t : 26;
+ __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
+ * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
+ * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */
+ } SFMCNT1_b;
+ };
+} R_QSPI_Type; /*!< Size = 2056 (0x808) */
+
+/* =========================================================================================================================== */
+/* ================ R_RTC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Realtime Clock (R_RTC)
+ */
+
+typedef struct /*!< (@ 0x40083000) R_RTC Structure */
+{
+ union
+ {
+ __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */
+
+ struct
+ {
+ __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */
+ __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */
+ __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */
+ __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */
+ __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */
+ __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */
+ __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */
+ uint8_t : 1;
+ } R64CNT_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */
+
+ struct
+ {
+ __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
+ * counter b7 to b0. */
+ } BCNT0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */
+
+ struct
+ {
+ __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
+ * a carry is generated, 1 is added to the tens place. */
+ __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */
+ uint8_t : 1;
+ } RSECCNT_b;
+ };
+ };
+ __IM uint8_t RESERVED1;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */
+
+ struct
+ {
+ __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
+ * counter b15 to b8. */
+ } BCNT1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */
+
+ struct
+ {
+ __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
+ * a carry is generated, 1 is added to the tens place. */
+ __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */
+ uint8_t : 1;
+ } RMINCNT_b;
+ };
+ };
+ __IM uint8_t RESERVED2;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */
+
+ struct
+ {
+ __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
+ * counter b23 to b16. */
+ } BCNT2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */
+
+ struct
+ {
+ __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
+ * carry is generated, 1 is added to the tens place. */
+ __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
+ * the ones place. */
+ __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
+ uint8_t : 1;
+ } RHRCNT_b;
+ };
+ };
+ __IM uint8_t RESERVED3;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */
+
+ struct
+ {
+ __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
+ * counter b31 to b24. */
+ } BCNT3_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */
+
+ struct
+ {
+ __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
+ uint8_t : 5;
+ } RWKCNT_b;
+ };
+ };
+ __IM uint8_t RESERVED4;
+
+ union
+ {
+ __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */
+
+ struct
+ {
+ __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
+ * is generated, 1 is added to the tens place. */
+ __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
+ * ones place. */
+ uint8_t : 2;
+ } RDAYCNT_b;
+ };
+ __IM uint8_t RESERVED5;
+
+ union
+ {
+ __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */
+
+ struct
+ {
+ __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
+ * a carry is generated, 1 is added to the tens place. */
+ __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
+ * the ones place. */
+ uint8_t : 3;
+ } RMONCNT_b;
+ };
+ __IM uint8_t RESERVED6;
+
+ union
+ {
+ __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */
+
+ struct
+ {
+ __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
+ * carry is generated, 1 is added to the tens place. */
+ __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
+ * ones place. When a carry is generated in the tens place,
+ * 1 is added to the hundreds place. */
+ uint16_t : 8;
+ } RYRCNT_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
+ * corresponding to 32-bit binary counter b7 to b0. */
+ } BCNT0AR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */
+
+ struct
+ {
+ __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */
+ __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RSECAR_b;
+ };
+ };
+ __IM uint8_t RESERVED7;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
+ * corresponding to 32-bit binary counter b15 to b8. */
+ } BCNT1AR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */
+ __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RMINAR_b;
+ };
+ };
+ __IM uint8_t RESERVED8;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
+ * counter b23 to b16. */
+ } BCNT2AR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */
+ __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */
+ __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RHRAR_b;
+ };
+ };
+ __IM uint8_t RESERVED9;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
+ * counter b31 to b24. */
+ } BCNT3AR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
+ uint8_t : 4;
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RWKAR_b;
+ };
+ };
+ __IM uint8_t RESERVED10;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */
+
+ struct
+ {
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
+ * for setting the alarm enable corresponding to 32-bit binary
+ * counter b7 to b0. */
+ } BCNT0AER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */
+ __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */
+ uint8_t : 1;
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RDAYAR_b;
+ };
+ };
+ __IM uint8_t RESERVED11;
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */
+
+ struct
+ {
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
+ * for setting the alarm enable corresponding to 32-bit binary
+ * counter b15 to b8. */
+ } BCNT1AER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */
+
+ struct
+ {
+ __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */
+ __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */
+ uint8_t : 2;
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RMONAR_b;
+ };
+ };
+ __IM uint8_t RESERVED12;
+
+ union
+ {
+ union
+ {
+ __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */
+
+ struct
+ {
+ __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
+ * for setting the alarm enable corresponding to 32-bit binary
+ * counter b23 to b16. */
+ uint16_t : 8;
+ } BCNT2AER_b;
+ };
+
+ union
+ {
+ __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */
+
+ struct
+ {
+ __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */
+ __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */
+ uint16_t : 8;
+ } RYRAR_b;
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */
+
+ struct
+ {
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
+ * for setting the alarm enable corresponding to 32-bit binary
+ * counter b31 to b24. */
+ } BCNT3AER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
+ } RYRAREN_b;
+ };
+ };
+ __IM uint8_t RESERVED13;
+ __IM uint16_t RESERVED14;
+
+ union
+ {
+ __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */
+ __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */
+ __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */
+ __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */
+ __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */
+ } RCR1_b;
+ };
+ __IM uint8_t RESERVED15;
+
+ union
+ {
+ __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */
+
+ struct
+ {
+ __IOM uint8_t START : 1; /*!< [0..0] Start */
+ __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */
+ __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */
+ __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */
+ __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
+ * the setting of this bit is disabled.) */
+ __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
+ * is selected, the setting of this bit is disabled.) */
+ __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */
+ __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */
+ } RCR2_b;
+ };
+ __IM uint8_t RESERVED16;
+ __IM uint16_t RESERVED17;
+
+ union
+ {
+ __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */
+
+ struct
+ {
+ __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */
+ uint8_t : 6;
+ __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */
+ } RCR4_b;
+ };
+ __IM uint8_t RESERVED18;
+
+ union
+ {
+ __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */
+
+ struct
+ {
+ __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
+ * clock from the LOCOclock, this bit sets the comparison
+ * value of the 128-Hz clock cycle. */
+ uint16_t : 15;
+ } RFRH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */
+
+ struct
+ {
+ __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
+ * clock from the main clock, this bit sets the comparison
+ * value of the 128-Hz clock cycle. */
+ } RFRL_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */
+
+ struct
+ {
+ __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value
+ * from the prescaler. */
+ __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */
+ } RADJ_b;
+ };
+ __IM uint8_t RESERVED19;
+ __IM uint16_t RESERVED20[8];
+ __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */
+ __IM uint16_t RESERVED21[5];
+ __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */
+} R_RTC_Type; /*!< Size = 128 (0x80) */
+
+/* =========================================================================================================================== */
+/* ================ R_SCI0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communications Interface (R_SCI0)
+ */
+
+typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */
+{
+ union
+ {
+ union
+ {
+ __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */
+
+ struct
+ {
+ __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
+ __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */
+ __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */
+ __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
+ __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
+ __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */
+ __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */
+ } SMR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */
+
+ struct
+ {
+ __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
+ __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */
+ __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
+ __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
+ __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */
+ __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */
+ } SMR_SMCI_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */
+
+ struct
+ {
+ __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */
+ } BRR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */
+
+ struct
+ {
+ __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
+ __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
+ __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
+ * mode when SMR.MP = 1) */
+ __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
+ __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
+ __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
+ } SCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */
+
+ struct
+ {
+ __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
+ __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
+ __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */
+ __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
+ __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
+ __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
+ } SCR_SMCI_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */
+
+ struct
+ {
+ __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */
+ } TDR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */
+
+ struct
+ {
+ __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */
+ __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
+ __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
+ __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
+ __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
+ } SSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */
+
+ struct
+ {
+ __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
+ * multi-processor) and FIFO selected) */
+ uint8_t : 1;
+ __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
+ __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
+ __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */
+ __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */
+ } SSR_FIFO_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */
+
+ struct
+ {
+ __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
+ * card interface mode. */
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
+ * mode. */
+ __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
+ __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
+ __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
+ __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
+ } SSR_SMCI_b;
+ };
+ };
+
+ union
+ {
+ __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */
+
+ struct
+ {
+ __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */
+ } RDR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */
+
+ struct
+ {
+ __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */
+ uint8_t : 1;
+ __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
+ * operation is to be in simple I2C mode. */
+ __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
+ * setting is invalid and a fixed data length of 8 bits is
+ * used in modes other than asynchronous mode.Set this bit
+ * to 1 if operation is to be in simple I2C mode. */
+ __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */
+ uint8_t : 2;
+ __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
+ * in combination with the SMR.BCP[1:0] bits */
+ } SCMR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */
+
+ struct
+ {
+ __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
+ * asynchronous mode). */
+ __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous
+ * mode). */
+ __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */
+ __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
+ * only in asynchronous mode and SCR.CKE[1]=0) */
+ __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
+ * mode) */
+ __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
+ * be 0 without simple I2C mode and asynchronous mode.)In
+ * asynchronous mode, for RXDn input only. In simple I2C mode,
+ * for RXDn/TxDn input. */
+ __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
+ * the CKE[1] bit in SCR is 0 in asynchronous mode). */
+ __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
+ * in asynchronous mode) */
+ } SEMR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */
+
+ struct
+ {
+ __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */
+ uint8_t : 5;
+ } SNFR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */
+
+ struct
+ {
+ __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */
+ uint8_t : 2;
+ __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
+ * signal from the on-chip baud rate generator. */
+ } SIMR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */
+
+ struct
+ {
+ __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */
+ __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */
+ uint8_t : 3;
+ __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */
+ uint8_t : 2;
+ } SIMR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */
+
+ struct
+ {
+ __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */
+ __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */
+ __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */
+ __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+ * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */
+ __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */
+ __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */
+ } SIMR3_b;
+ };
+
+ union
+ {
+ __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */
+
+ struct
+ {
+ __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
+ uint8_t : 7;
+ } SISR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */
+
+ struct
+ {
+ __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */
+ __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */
+ __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */
+ __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */
+ __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */
+ uint8_t : 1;
+ __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */
+ __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */
+ } SPMR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */
+
+ struct
+ {
+ __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */
+ } TDRHL_b;
+ };
+
+ union
+ {
+ __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */
+
+ struct
+ {
+ __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
+ __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
+ * mode and SMR.MP=1 and FIFO selected) */
+ uint16_t : 6;
+ } FTDRHL_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */
+
+ struct
+ {
+ __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode,
+ * and FIFO selected) */
+ __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
+ * mode and SMR.MP=1 and FIFO selected) */
+ uint8_t : 6;
+ } FTDRH_b;
+ };
+
+ union
+ {
+ __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */
+
+ struct
+ {
+ __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode,
+ * and FIFO selected) */
+ } FTDRL_b;
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */
+
+ struct
+ {
+ __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */
+ } RDRHL_b;
+ };
+
+ union
+ {
+ __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */
+
+ struct
+ {
+ __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
+ __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
+ * with SMR.MP=1 and FIFO selected) It can read multi-processor
+ * bit corresponded to serial receive data(RDATA[8:0]) */
+ __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */
+ __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */
+ __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */
+ __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */
+ __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */
+ uint16_t : 1;
+ } FRDRHL_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */
+
+ struct
+ {
+ __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
+ * with SMR.MP=1 and FIFO selected) It can read multi-processor
+ * bit corresponded to serial receive data(RDATA[8:0]) */
+ __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */
+ __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */
+ __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */
+ __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */
+ __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */
+ uint8_t : 1;
+ } FRDRH_b;
+ };
+
+ union
+ {
+ __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */
+
+ struct
+ {
+ __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
+ * When reading both of FRDRH register and FRDRL register,
+ * please read by an order of the FRDRH register and the FRDRL
+ * register. */
+ } FRDRL_b;
+ };
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */
+
+ struct
+ {
+ __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */
+ } MDDR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */
+
+ struct
+ {
+ __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */
+ uint8_t : 2;
+ __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */
+ __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */
+ uint8_t : 1;
+ __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
+ * multi-processor) */
+ __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
+ * mode(including multi-processor) */
+ } DCCR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */
+
+ struct
+ {
+ __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode) */
+ __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */
+ __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */
+ __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a
+ * reception data ready, the interrupt request is selected.) */
+ __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode) */
+ __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode) */
+ __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
+ * in asynchronous mode(including multi-processor) or clock
+ * synchronous mode) */
+ } FCR_b;
+ };
+
+ union
+ {
+ __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */
+
+ struct
+ {
+ __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
+ * data stored in FRDRH and FRDRL(Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode,
+ * while FCR.FM=1) */
+ uint16_t : 3;
+ __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
+ * data stored in FTDRH and FTDRL(Valid only in asynchronous
+ * mode(including multi-processor) or clock synchronous mode,
+ * while FCR.FM=1) */
+ uint16_t : 3;
+ } FDR_b;
+ };
+
+ union
+ {
+ __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */
+
+ struct
+ {
+ __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
+ uint16_t : 1;
+ __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with
+ * a framing error among the receive data stored in the receive
+ * FIFO data register (FRDRH and FRDRL). */
+ uint16_t : 1;
+ __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with
+ * a parity error among the receive data stored in the receive
+ * FIFO data register (FRDRH and FRDRL). */
+ uint16_t : 3;
+ } LSR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */
+
+ struct
+ {
+ __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match
+ * wake-up function */
+ uint16_t : 7;
+ } CDR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */
+
+ struct
+ {
+ __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
+ * is shown.) */
+ __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of
+ * TxD terminal is selected when SCR.TE = 0.) */
+ __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value
+ * of SPB2DT is output to TxD terminal.) */
+ uint8_t : 1;
+ __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */
+ __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */
+ __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */
+ __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */
+ } SPTR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */
+
+ struct
+ {
+ __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */
+ __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */
+ __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */
+ __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */
+ } ACTR_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */
+
+ struct
+ {
+ __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */
+ uint8_t : 7;
+ } ESMER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */
+
+ struct
+ {
+ uint8_t : 1;
+ __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */
+ __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */
+ __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */
+ uint8_t : 4;
+ } CR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */
+ __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */
+ __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */
+ __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */
+ __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */
+ } CR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */
+
+ struct
+ {
+ __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */
+ uint8_t : 1;
+ __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */
+ __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */
+ } CR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */
+
+ struct
+ {
+ __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */
+ uint8_t : 7;
+ } CR3_b;
+ };
+
+ union
+ {
+ __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */
+
+ struct
+ {
+ __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */
+ __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */
+ uint8_t : 2;
+ __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */
+ uint8_t : 3;
+ } PCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */
+
+ struct
+ {
+ __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */
+ __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */
+ __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */
+ __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */
+ __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */
+ __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */
+ uint8_t : 2;
+ } ICR_b;
+ };
+
+ union
+ {
+ __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */
+
+ struct
+ {
+ __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */
+ __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */
+ __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */
+ __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */
+ __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */
+ __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */
+ uint8_t : 2;
+ } STR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */
+
+ struct
+ {
+ __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */
+ __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */
+ __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */
+ __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */
+ __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */
+ __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */
+ uint8_t : 2;
+ } STCR_b;
+ };
+ __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */
+
+ union
+ {
+ __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */
+
+ struct
+ {
+ __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */
+ __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */
+ } CF0CR_b;
+ };
+ __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */
+ __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */
+ __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */
+
+ union
+ {
+ __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */
+
+ struct
+ {
+ __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */
+ __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */
+ __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */
+ __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */
+ __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */
+ __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */
+ __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */
+ __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */
+ } CF1CR_b;
+ };
+ __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */
+
+ union
+ {
+ __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */
+
+ struct
+ {
+ __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */
+ uint8_t : 7;
+ } TCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */
+
+ struct
+ {
+ __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */
+ uint8_t : 1;
+ __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */
+ __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */
+ uint8_t : 1;
+ } TMR_b;
+ };
+ __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */
+ __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */
+} R_SCI0_Type; /*!< Size = 52 (0x34) */
+
+/* =========================================================================================================================== */
+/* ================ R_SDHI0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SD/MMC Host Interface (R_SDHI0)
+ */
+
+typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */
+{
+ union
+ {
+ __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */
+
+ struct
+ {
+ __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
+ * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
+ * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */
+ __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */
+ __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
+ * in normal mode, see section 1.4.10, Example of SD_CMD Register
+ * Setting to select mode/response type. */
+ __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */
+ __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data
+ * is handled) */
+ __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
+ * with data is handled) */
+ __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
+ * transfer) */
+ uint32_t : 16;
+ } SD_CMD_b;
+ };
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */
+
+ struct
+ {
+ __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */
+ } SD_ARG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */
+ uint32_t : 16;
+ } SD_ARG1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */
+
+ struct
+ {
+ __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
+ * CMD12 is issued to halt the transfer through the SD host
+ * interface.However, if a command sequence is halted because
+ * of a communications error or timeout, CMD12 is not issued.
+ * Although continued buffer access is possible even after
+ * STP has been set to 1, the buffer access error bit (ERR5
+ * or ERR4) in SD_INFO2 will be set accordingly.- When STP
+ * has been set to 1 during transfer for single block write,
+ * the access end flag is set when SD_BUF becomes emp */
+ uint32_t : 7;
+ __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
+ * SD_CMD is set as follows to start the command sequence
+ * while SEC is set to 1, CMD12 is automatically issued to
+ * stop multi-block transfer with the number of blocks which
+ * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
+ * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
+ * automatically issued, multiple block transfer)When the
+ * command sequence is halted because of a communications
+ * error or timeout, CMD12 is not automatically i */
+ uint32_t : 23;
+ } SD_STOP_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */
+
+ struct
+ {
+ __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
+ * of this bit when the CBSY bit in SD_INFO2 is set to 1. */
+ } SD_SECCNT_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */
+ } SD_RSP10_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */
+ uint32_t : 16;
+ } SD_RSP1_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */
+ } SD_RSP32_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */
+ uint32_t : 16;
+ } SD_RSP3_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */
+ } SD_RSP54_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */
+ uint32_t : 16;
+ } SD_RSP5_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */
+ uint32_t : 8;
+ } SD_RSP76_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */
+
+ struct
+ {
+ __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */
+ uint32_t : 24;
+ } SD_RSP7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */
+
+ struct
+ {
+ __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */
+ uint32_t : 1;
+ __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */
+ __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */
+ __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */
+ __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */
+ uint32_t : 1;
+ __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */
+ __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */
+ __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */
+ __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */
+ uint32_t : 21;
+ } SD_INFO1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */
+ __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */
+ __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */
+ __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */
+ __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */
+ __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */
+ __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */
+ __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
+ * by SD_PORTSEL. */
+ __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */
+ __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */
+ uint32_t : 3;
+ __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
+ * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
+ * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
+ * cycles of SDCLK have elapsed after setting of the CBSY
+ * bit to 0 due to completion of the command sequence. */
+ __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */
+ __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */
+ uint32_t : 16;
+ } SD_INFO2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */
+
+ struct
+ {
+ __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */
+ uint32_t : 1;
+ __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */
+ __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */
+ __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */
+ uint32_t : 3;
+ __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */
+ __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */
+ uint32_t : 22;
+ } SD_INFO1_MASK_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */
+
+ struct
+ {
+ __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */
+ __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */
+ __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */
+ __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */
+ __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */
+ __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */
+ __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */
+ uint32_t : 1;
+ __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */
+ __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */
+ uint32_t : 5;
+ __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */
+ uint32_t : 16;
+ } SD_INFO2_MASK_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */
+
+ struct
+ {
+ __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */
+ __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */
+ __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */
+ uint32_t : 22;
+ } SD_CLK_CTRL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */
+
+ struct
+ {
+ __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
+ * and 512 bytes for the transfer of single blocks.In cases
+ * of multiple block transfer with automatic issuing of CMD12
+ * (CMD18 and CMD25), the only specifiable transfer data size
+ * is 512 bytes. Furthermore, in cases of multiple block transfer
+ * without automatic issuing of CMD12, as well as 512 bytes,
+ * 32, 64, 128, and 256 bytes are specifiable. However, in
+ * the reading of 32, 64, 128, and 256 bytes for the transfer
+ * of multiple blocks, this is restricted to mult */
+ uint32_t : 22;
+ } SD_SIZE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */
+
+ struct
+ {
+ __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */
+ __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */
+ __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
+ * timeout, software reset should be executed to terminate
+ * command sequence. */
+ uint32_t : 4;
+ __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */
+ uint32_t : 1;
+ __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
+ * and when the SOFT_RST.SDRST flag is 0. */
+ uint32_t : 16;
+ } SD_OPTION_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */
+
+ struct
+ {
+ __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command
+ * issued within a command sequence */
+ __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
+ * setting a command index in SD_CMD, this is Indicated in
+ * CMDE0. */
+ __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
+ * a command issued within a command sequence */
+ __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
+ * issued by setting a command index in SD_CMD, this is indicated
+ * in RSPLENE0. */
+ __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */
+ __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */
+ uint32_t : 2;
+ __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
+ * command issued within a command sequence */
+ __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
+ * by setting a command index in SD_CMD, this is indicated
+ * in RSPCRCE0. */
+ __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */
+ __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */
+ __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
+ * value is 010b) */
+ uint32_t : 17;
+ } SD_ERR_STS1_b;
+ };
+
+ union
+ {
+ __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */
+
+ struct
+ {
+ __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */
+ __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */
+ __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */
+ __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */
+ __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */
+ __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */
+ __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */
+ uint32_t : 25;
+ } SD_ERR_STS2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */
+
+ struct
+ {
+ __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
+ * data is written to this register. When reading from the
+ * SD card, the read data is read from this register. This
+ * register is internally connected to two 512-byte buffers.If
+ * both buffers are not empty when executing multiple block
+ * read, SD/MMC clock is stopped to suspend receiving data.
+ * When one of buffers is empty, SD/MMC clock is supplied
+ * to resume receiving data. */
+ } SD_BUF0_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */
+
+ struct
+ {
+ __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */
+ uint32_t : 1;
+ __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */
+ uint32_t : 5;
+ __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */
+ __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */
+ uint32_t : 22;
+ } SDIO_MODE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */
+
+ struct
+ {
+ __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */
+ uint32_t : 13;
+ __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */
+ __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */
+ uint32_t : 16;
+ } SDIO_INFO1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */
+
+ struct
+ {
+ __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */
+ uint32_t : 13;
+ __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */
+ __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */
+ uint32_t : 16;
+ } SDIO_INFO1_MASK_b;
+ };
+ __IM uint32_t RESERVED3[79];
+
+ union
+ {
+ __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */
+
+ struct
+ {
+ uint32_t : 1;
+ __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */
+ uint32_t : 30;
+ } SD_DMAEN_b;
+ };
+ __IM uint32_t RESERVED4[3];
+
+ union
+ {
+ __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */
+
+ struct
+ {
+ __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */
+ uint32_t : 31;
+ } SOFT_RST_b;
+ };
+ __IM uint32_t RESERVED5[2];
+
+ union
+ {
+ __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */
+ uint32_t : 23;
+ } SDIF_MODE_b;
+ };
+ __IM uint32_t RESERVED6[4];
+
+ union
+ {
+ __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */
+
+ struct
+ {
+ uint32_t : 6;
+ __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */
+ __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */
+ uint32_t : 24;
+ } EXT_SWAP_b;
+ };
+} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */
+
+/* =========================================================================================================================== */
+/* ================ R_SPI0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface (R_SPI0)
+ */
+
+typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */
+{
+ union
+ {
+ __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */
+
+ struct
+ {
+ __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */
+ __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */
+ __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */
+ __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */
+ __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */
+ __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */
+ __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */
+ __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */
+ } SPCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */
+
+ struct
+ {
+ __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */
+ __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */
+ __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */
+ __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */
+ __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */
+ __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */
+ __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */
+ __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */
+ } SSLP_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */
+
+ struct
+ {
+ __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */
+ __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */
+ uint8_t : 2;
+ __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */
+ __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */
+ uint8_t : 2;
+ } SPPCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */
+
+ struct
+ {
+ __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */
+ __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */
+ __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */
+ __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */
+ __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */
+ __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */
+ __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */
+ __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */
+ } SPSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */
+ __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */
+ __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */
+ };
+
+ union
+ {
+ __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */
+
+ struct
+ {
+ __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
+ * the SPCMD0 to SPCMD07 registers are to be referenced is
+ * changed in accordance with the sequence length that is
+ * set in these bits. The relationship among the setting of
+ * these bits, sequence length, and SPCMD0 to SPCMD7 registers
+ * referenced by the RSPI is shown above. However, the RSPI
+ * in slave mode always references SPCMD0. */
+ uint8_t : 5;
+ } SPSCR_b;
+ };
+
+ union
+ {
+ __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */
+
+ struct
+ {
+ __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */
+ uint8_t : 1;
+ __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */
+ uint8_t : 1;
+ } SPSSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */
+
+ struct
+ {
+ __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */
+ } SPBR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */
+
+ struct
+ {
+ __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */
+ __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */
+ __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */
+ __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */
+ __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */
+ uint8_t : 1;
+ } SPDCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */
+
+ struct
+ {
+ __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */
+ uint8_t : 5;
+ } SPCKD_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */
+
+ struct
+ {
+ __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */
+ uint8_t : 5;
+ } SSLND_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */
+
+ struct
+ {
+ __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */
+ uint8_t : 5;
+ } SPND_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */
+
+ struct
+ {
+ __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */
+ __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */
+ __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */
+ __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */
+ __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */
+ __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */
+ } SPCR2_b;
+ };
+
+ union
+ {
+ __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */
+
+ struct
+ {
+ __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */
+ __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */
+ __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */
+ __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */
+ __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */
+ __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */
+ __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */
+ __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */
+ __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ } SPCMD_b[8];
+ };
+
+ union
+ {
+ __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */
+
+ struct
+ {
+ __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
+ __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */
+ uint8_t : 6;
+ } SPDCR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */
+
+ struct
+ {
+ __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */
+ __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */
+ uint8_t : 2;
+ __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */
+ uint8_t : 3;
+ } SPCR3_b;
+ };
+ __IM uint16_t RESERVED;
+ __IM uint32_t RESERVED1[6];
+ __IM uint16_t RESERVED2;
+
+ union
+ {
+ __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */
+ uint16_t : 3;
+ __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */
+ uint16_t : 1;
+ __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */
+ } SPPR_b;
+ };
+} R_SPI0_Type; /*!< Size = 64 (0x40) */
+
+/* =========================================================================================================================== */
+/* ================ R_SRAM ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SRAM (R_SRAM)
+ */
+
+typedef struct /*!< (@ 0x40002000) R_SRAM Structure */
+{
+ union
+ {
+ __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */
+
+ struct
+ {
+ __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */
+ uint8_t : 7;
+ } PARIOAD_b;
+ };
+ __IM uint8_t RESERVED[3];
+
+ union
+ {
+ __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */
+
+ struct
+ {
+ __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */
+ __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
+ } SRAMPRCR_b;
+ };
+ __IM uint8_t RESERVED1[3];
+ __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */
+ __IM uint8_t RESERVED2[3];
+
+ union
+ {
+ __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */
+
+ struct
+ {
+ __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */
+ __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
+ } SRAMPRCR2_b;
+ };
+ __IM uint8_t RESERVED3[179];
+
+ union
+ {
+ __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */
+
+ struct
+ {
+ __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */
+ uint8_t : 6;
+ } ECCMODE_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */
+
+ struct
+ {
+ __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */
+ uint8_t : 7;
+ } ECC2STS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */
+
+ struct
+ {
+ __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */
+ uint8_t : 7;
+ } ECC1STSEN_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */
+
+ struct
+ {
+ __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */
+ uint8_t : 7;
+ } ECC1STS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */
+
+ struct
+ {
+ __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */
+ __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
+ } ECCPRCR_b;
+ };
+ __IM uint8_t RESERVED4[11];
+
+ union
+ {
+ __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */
+
+ struct
+ {
+ __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */
+ __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */
+ } ECCPRCR2_b;
+ };
+ __IM uint8_t RESERVED5[3];
+
+ union
+ {
+ __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */
+
+ struct
+ {
+ __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */
+ uint8_t : 7;
+ } ECCETST_b;
+ };
+ __IM uint8_t RESERVED6[3];
+
+ union
+ {
+ __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */
+
+ struct
+ {
+ __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */
+ uint8_t : 7;
+ } ECCOAD_b;
+ };
+} R_SRAM_Type; /*!< Size = 217 (0xd9) */
+
+/* =========================================================================================================================== */
+/* ================ R_BUS_B ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS_B)
+ */
+
+typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */
+{
+ __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
+ __IM uint32_t RESERVED[480];
+ __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
+
+ union
+ {
+ __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
+
+ struct
+ {
+ __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
+ } CSRECEN_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[543];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTFHBIU_b;
+ };
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTFLBIU_b;
+ };
+ __IM uint16_t RESERVED4;
+ __IM uint32_t RESERVED5[2];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTS0BIU_b;
+ };
+ __IM uint16_t RESERVED6;
+ __IM uint32_t RESERVED7[3];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPSBIU_b;
+ };
+ __IM uint16_t RESERVED8;
+ __IM uint32_t RESERVED9[3];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPLBIU_b;
+ };
+ __IM uint16_t RESERVED10;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPHBIU_b;
+ };
+ __IM uint16_t RESERVED11;
+ __IM uint32_t RESERVED12[2];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTEQBIU_b;
+ };
+ __IM uint16_t RESERVED13;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTEOBIU_b;
+ };
+ __IM uint16_t RESERVED14;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTECBIU_b;
+ };
+ __IM uint16_t RESERVED15;
+ __IM uint32_t RESERVED16[429];
+ __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */
+ __IM uint32_t RESERVED17[48];
+ __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */
+ __IM uint32_t RESERVED18[48];
+
+ union
+ {
+ __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS1ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED19;
+ __IM uint16_t RESERVED20;
+ __IM uint32_t RESERVED21;
+
+ union
+ {
+ __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS1ERRCLR_b;
+ };
+ __IM uint8_t RESERVED22;
+ __IM uint16_t RESERVED23;
+ __IM uint32_t RESERVED24;
+
+ union
+ {
+ __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS2ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED25;
+ __IM uint16_t RESERVED26;
+ __IM uint32_t RESERVED27;
+
+ union
+ {
+ __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS2ERRCLR_b;
+ };
+ __IM uint8_t RESERVED28;
+ __IM uint16_t RESERVED29;
+ __IM uint32_t RESERVED30;
+
+ union
+ {
+ __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS3ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED31;
+ __IM uint16_t RESERVED32;
+
+ union
+ {
+ __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */
+
+ struct
+ {
+ __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */
+ uint8_t : 7;
+ } DMACDTCERRSTAT_b;
+ };
+ __IM uint8_t RESERVED33;
+ __IM uint16_t RESERVED34;
+
+ union
+ {
+ __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS3ERRCLR_b;
+ };
+ __IM uint8_t RESERVED35;
+ __IM uint16_t RESERVED36;
+
+ union
+ {
+ __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */
+
+ struct
+ {
+ __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */
+ uint8_t : 7;
+ } DMACDTCERRCLR_b;
+ };
+ __IM uint8_t RESERVED37;
+ __IM uint16_t RESERVED38;
+
+ union
+ {
+ __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS4ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED39;
+ __IM uint16_t RESERVED40;
+ __IM uint32_t RESERVED41;
+
+ union
+ {
+ __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS4ERRCLR_b;
+ };
+ __IM uint8_t RESERVED42;
+ __IM uint16_t RESERVED43;
+} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */
+
+/* =========================================================================================================================== */
+/* ================ R_SSI0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
+ */
+
+typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */
+{
+ union
+ {
+ __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */
+
+ struct
+ {
+ __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */
+ __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */
+ uint32_t : 1;
+ __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
+ * of outputting serial data is rewritten to 0 but data transmission
+ * is not stopped. Write dummy data to the SSIFTDR not to
+ * generate a transmit underflow because the number of data
+ * in the transmit FIFO is decreasing. */
+ __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */
+ __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */
+ __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */
+ __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */
+ __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */
+ __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */
+ __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */
+ __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings
+ * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
+ * are prohibited. */
+ uint32_t : 1;
+ __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the
+ * bit clock frequency/2 fs. */
+ __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */
+ __IOM uint32_t FRM : 2; /*!< [23..22] Channels */
+ uint32_t : 1;
+ __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */
+ __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */
+ __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */
+ __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */
+ __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */
+ __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */
+ uint32_t : 1;
+ } SSICR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */
+
+ struct
+ {
+ __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */
+ __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */
+ __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */
+ __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */
+ __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */
+ uint32_t : 18;
+ __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */
+ __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
+ * Writable only to clear the flag. Confirm the value is 1
+ * and then write 0. */
+ __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
+ * Writable only to clear the flag. Confirm the value is 1
+ * and then write 0. */
+ __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
+ * Writable only to clear the flag. Confirm the value is 1
+ * and then write 0. */
+ __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
+ * Writable only to clear the flag. Confirm the value is 1
+ * and then write 0. */
+ uint32_t : 2;
+ } SSISR_b;
+ };
+ __IM uint32_t RESERVED[2];
+
+ union
+ {
+ __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */
+
+ struct
+ {
+ __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */
+ __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */
+ __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
+ * clearing either the RDF flag (see the description of the
+ * RDF bit for details) or RIE bit. */
+ __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
+ * clearing either the TDE flag (see the description of the
+ * TDE bit for details) or TIE bit. */
+ __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */
+ __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
+ * are the number of empty stages in SSIFTDR at which the
+ * TDE flag is set. */
+ uint32_t : 3;
+ __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */
+ uint32_t : 4;
+ __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */
+ uint32_t : 14;
+ __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */
+ } SSIFCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */
+
+ struct
+ {
+ __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
+ * is a 32-byte FIFO register, the maximum number of data
+ * bytes that can be read from it while the RDF flag is 1
+ * is indicated in the RDC[3:0] flags. If reading data from
+ * the SSIFRDR register is continued after all the data is
+ * read, undefined values will be read. */
+ uint32_t : 7;
+ __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
+ * units stored in SSIFRDR) */
+ uint32_t : 2;
+ __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
+ * is a 32-byte FIFO register, the maximum number of bytes
+ * that can be written to it while the TDE flag is 1 is 8
+ * - TDC[3:0]. If writing data to the SSIFTDR register is
+ * continued after all the data is written, writing will be
+ * invalid and an overflow occurs. */
+ uint32_t : 7;
+ __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
+ * data units stored in SSIFTDR) */
+ uint32_t : 2;
+ } SSIFSR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */
+
+ struct
+ {
+ __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
+ * eight stages of 32-bit registers for storing data to be
+ * serially transmitted. NOTE: that when the SSIFTDR register
+ * is full of data (32 bytes), the next data cannot be written
+ * to it. If writing is attempted, it will be ignored and
+ * an overflow occurs. */
+ } SSIFTDR_b;
+ };
+ __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */
+ __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */
+ };
+
+ union
+ {
+ union
+ {
+ __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */
+
+ struct
+ {
+ __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
+ * stages of 32-bit registers for storing serially received
+ * data. */
+ } SSIFRDR_b;
+ };
+ __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */
+ __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */
+ };
+
+ union
+ {
+ __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */
+
+ struct
+ {
+ __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */
+ uint32_t : 6;
+ __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */
+ __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
+ * Idle Status */
+ uint32_t : 22;
+ } SSIOFR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */
+
+ struct
+ {
+ __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */
+ uint32_t : 3;
+ __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */
+ uint32_t : 19;
+ } SSISCR_b;
+ };
+} R_SSI0_Type; /*!< Size = 40 (0x28) */
+
+/* =========================================================================================================================== */
+/* ================ R_SYSTEM ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Pins (R_SYSTEM)
+ */
+
+typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */
+{
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */
+
+ struct
+ {
+ uint16_t : 14;
+ __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */
+ __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */
+ } SBYCR_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[3];
+
+ union
+ {
+ __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */
+
+ struct
+ {
+ __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */
+ __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for
+ * usage. */
+ __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for
+ * usage. */
+ } MSTPCRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */
+ uint32_t : 1;
+ __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */
+ uint32_t : 1;
+ __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */
+ uint32_t : 1;
+ __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */
+ uint32_t : 1;
+ __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */
+ uint32_t : 5;
+ __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */
+ uint32_t : 1;
+ __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */
+ uint32_t : 1;
+ } SCKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */
+ uint8_t : 1;
+ } SCKDIVCR2_b;
+ };
+ __IM uint8_t RESERVED3;
+
+ union
+ {
+ __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */
+
+ struct
+ {
+ __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */
+ uint8_t : 5;
+ } SCKSCR_b;
+ };
+ __IM uint8_t RESERVED4;
+
+ union
+ {
+ __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */
+
+ struct
+ {
+ __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */
+ uint16_t : 2;
+ __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */
+ uint16_t : 3;
+ __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
+ * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
+ * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
+ * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
+ * 111011: x30.0 */
+ uint16_t : 2;
+ } PLLCCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */
+
+ struct
+ {
+ __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */
+ uint8_t : 7;
+ } PLLCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */
+
+ struct
+ {
+ __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */
+ uint8_t : 1;
+ __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */
+ } PLLCCR2_b;
+ };
+ __IM uint32_t RESERVED5;
+
+ union
+ {
+ __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */
+ uint8_t : 7;
+ } BCKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */
+
+ struct
+ {
+ __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
+ * is prohibited when SCKDIVCR.ICK selects division by 1 and
+ * SCKSCR.CKSEL[2:0] bits select thesystem clock source that
+ * is faster than 32 MHz (ICLK > 32 MHz). */
+ uint8_t : 7;
+ } MEMWAIT_b;
+ };
+
+ union
+ {
+ __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */
+
+ struct
+ {
+ __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */
+ uint8_t : 7;
+ } MOSCCR_b;
+ };
+ __IM uint8_t RESERVED6;
+ __IM uint16_t RESERVED7;
+
+ union
+ {
+ __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */
+
+ struct
+ {
+ __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */
+ uint8_t : 7;
+ } HOCOCR_b;
+ };
+ __IM uint8_t RESERVED8;
+
+ union
+ {
+ __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */
+
+ struct
+ {
+ __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */
+ uint8_t : 7;
+ } MOCOCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */
+ uint8_t : 7;
+ } FLLCR1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */
+
+ struct
+ {
+ __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
+ * FLL reference clock select */
+ uint16_t : 5;
+ } FLLCR2_b;
+ };
+
+ union
+ {
+ __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */
+
+ struct
+ {
+ __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
+ * bit value after a reset is 1 when the OFS1.HOCOEN bit is
+ * 0. It is 0 when the OFS1.HOCOEN bit is 1. */
+ uint8_t : 2;
+ __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */
+ uint8_t : 1;
+ __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */
+ __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */
+ uint8_t : 1;
+ } OSCSF_b;
+ };
+ __IM uint8_t RESERVED9;
+
+ union
+ {
+ __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */
+
+ struct
+ {
+ __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */
+ uint8_t : 1;
+ __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */
+ __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */
+ } CKOCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */
+ uint8_t : 3;
+ __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */
+ } TRCKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */
+
+ struct
+ {
+ __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */
+ uint8_t : 6;
+ __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */
+ } OSTDCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */
+
+ struct
+ {
+ __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */
+ uint8_t : 7;
+ } OSTDSR_b;
+ };
+ __IM uint16_t RESERVED10;
+ __IM uint32_t RESERVED11;
+
+ union
+ {
+ __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */
+
+ struct
+ {
+ __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */
+ uint16_t : 2;
+ __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */
+ uint16_t : 3;
+ __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */
+ uint16_t : 2;
+ } PLL2CCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */
+
+ struct
+ {
+ __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */
+ uint8_t : 7;
+ } PLL2CR_b;
+ };
+ __IM uint8_t RESERVED12;
+
+ union
+ {
+ __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */
+
+ struct
+ {
+ __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
+ * (valid only when LPOPTEN = 1) */
+ __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */
+ __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
+ * clock (valid only when LPOPT.LPOPTEN = 1) */
+ uint8_t : 3;
+ __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */
+ } LPOPT_b;
+ };
+ __IM uint8_t RESERVED13;
+ __IM uint16_t RESERVED14;
+
+ union
+ {
+ __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */
+ uint8_t : 4;
+ __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */
+ } SLCDSCKCR_b;
+ };
+ __IM uint8_t RESERVED15;
+
+ union
+ {
+ __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */
+
+ struct
+ {
+ __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */
+ uint8_t : 7;
+ } EBCKOCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */
+
+ struct
+ {
+ __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */
+ uint8_t : 7;
+ } SDCKOCR_b;
+ };
+ __IM uint32_t RESERVED16[3];
+ __IM uint8_t RESERVED17;
+
+ union
+ {
+ __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */
+
+ struct
+ {
+ __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+ * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+ * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+ +126 0111_1111 : +127These bits are added to original MOCO
+ * trimming bits */
+ } MOCOUTCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */
+
+ struct
+ {
+ __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+ * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+ * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+ +126 0111_1111 : +127These bits are added to original HOCO
+ * trimming bits */
+ } HOCOUTCR_b;
+ };
+ __IM uint8_t RESERVED18;
+ __IM uint32_t RESERVED19[2];
+
+ union
+ {
+ __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */
+ uint8_t : 5;
+ } USBCKDIVCR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */
+ uint8_t : 5;
+ } OCTACKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */
+ uint8_t : 5;
+ } SCISPICKDIVCR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */
+ uint8_t : 5;
+ } CANFDCKDIVCR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */
+ uint8_t : 5;
+ } GPTCKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */
+ uint8_t : 5;
+ } USB60CKDIVCR_b;
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */
+ uint8_t : 5;
+ } CECCKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */
+ uint8_t : 5;
+ } IICCKDIVCR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */
+
+ struct
+ {
+ __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */
+ uint8_t : 5;
+ } I3CCKDIVCR_b;
+ };
+ __IM uint16_t RESERVED20;
+
+ union
+ {
+ __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */
+ __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */
+ } USBCKCR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */
+ __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */
+ } OCTACKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */
+ __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */
+ } SCISPICKCR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */
+ __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */
+ } CANFDCKCR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */
+ __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */
+ } GPTCKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */
+
+ struct
+ {
+ __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */
+ uint8_t : 2;
+ __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */
+ __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */
+ } USB60CKCR_b;
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */
+ __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */
+ } CECCKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */
+ __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */
+ } IICCKCR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */
+ uint8_t : 3;
+ __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */
+ __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */
+ } I3CCKCR_b;
+ };
+ __IM uint16_t RESERVED21;
+ __IM uint32_t RESERVED22[3];
+
+ union
+ {
+ __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */
+ __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */
+ __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */
+ uint32_t : 29;
+ } SNZREQCR1_b;
+ };
+ __IM uint32_t RESERVED23;
+ __IM uint16_t RESERVED24;
+
+ union
+ {
+ __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */
+
+ struct
+ {
+ __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
+ * than in asynchronous mode. */
+ __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */
+ uint8_t : 5;
+ __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */
+ } SNZCR_b;
+ };
+ __IM uint8_t RESERVED25;
+
+ union
+ {
+ __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */
+
+ struct
+ {
+ __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */
+ __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */
+ __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */
+ __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */
+ __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */
+ __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */
+ __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */
+ __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
+ * to 1 other than in asynchronous mode. */
+ } SNZEDCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */
+ uint8_t : 7;
+ } SNZEDCR1_b;
+ };
+ __IM uint16_t RESERVED26;
+
+ union
+ {
+ __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */
+
+ struct
+ {
+ __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */
+ __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */
+ __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */
+ __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */
+ __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */
+ __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */
+ __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */
+ __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */
+ __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */
+ __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */
+ __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */
+ __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */
+ __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */
+ __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */
+ __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */
+ __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */
+ uint32_t : 1;
+ __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */
+ uint32_t : 4;
+ __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
+ * request */
+ __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
+ * request */
+ __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */
+ __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */
+ uint32_t : 2;
+ __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
+ * request */
+ __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
+ * snooze request */
+ __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
+ * snooze request */
+ uint32_t : 1;
+ } SNZREQCR_b;
+ };
+ __IM uint16_t RESERVED27;
+
+ union
+ {
+ __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */
+
+ struct
+ {
+ __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */
+ uint8_t : 3;
+ __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */
+ uint8_t : 3;
+ } FLSTOP_b;
+ };
+
+ union
+ {
+ __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */
+
+ struct
+ {
+ __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */
+ uint8_t : 6;
+ } PSMCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */
+
+ struct
+ {
+ __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */
+ uint8_t : 2;
+ __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */
+ uint8_t : 3;
+ } OPCCR_b;
+ };
+ __IM uint8_t RESERVED28;
+
+ union
+ {
+ __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */
+
+ struct
+ {
+ __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */
+ uint8_t : 4;
+ } MOSCWTCR_b;
+ };
+ __IM uint8_t RESERVED29[2];
+
+ union
+ {
+ __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */
+
+ struct
+ {
+ __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
+ * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */
+ uint8_t : 5;
+ } HOCOWTCR_b;
+ };
+ __IM uint16_t RESERVED30[2];
+
+ union
+ {
+ __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */
+
+ struct
+ {
+ __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */
+ uint8_t : 3;
+ __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */
+ uint8_t : 3;
+ } SOPCCR_b;
+ };
+ __IM uint8_t RESERVED31;
+ __IM uint32_t RESERVED32[5];
+
+ union
+ {
+ __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */
+
+ struct
+ {
+ __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
+ * only to clear the flag. Confirm the value is 1 and then
+ * write 0. */
+ __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
+ * clear the flag. Confirm the value is 1 and then write 0. */
+ __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
+ * the flag. Confirm the value is 1 and then write 0. */
+ uint16_t : 5;
+ __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
+ * clear the flag. Confirm the value is 1 and then write 0. */
+ __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
+ * the flag. Confirm the value is 1 and then write 0. */
+ __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */
+ uint16_t : 1;
+ __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */
+ } RSTSR1_b;
+ };
+ __IM uint16_t RESERVED33;
+ __IM uint32_t RESERVED34[3];
+
+ union
+ {
+ __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
+ * (UCLK). */
+ uint8_t : 7;
+ } USBCKCR_ALT_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */
+ uint8_t : 6;
+ __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */
+ } SDADCCKCR_b;
+ };
+ __IM uint16_t RESERVED35;
+ __IM uint32_t RESERVED36[3];
+
+ union
+ {
+ __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
+ __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
+ uint8_t : 5;
+ } LVD1CR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */
+
+ struct
+ {
+ __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+ * 0 can be written to this bit. After writing 0 to this bit,
+ * it takes 2 system clock cycles for the bit to be read as
+ * 0. */
+ __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */
+ uint8_t : 6;
+ } LVD1SR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
+ __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
+ uint8_t : 5;
+ } LVD2CR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */
+
+ struct
+ {
+ __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+ * 0 can be written to this bit. After writing 0 to this bit,
+ * it takes 2 system clock cycles for the bit to be read as
+ * 0. */
+ __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */
+ uint8_t : 6;
+ } LVD2SR_b;
+ };
+ __IM uint32_t RESERVED37[183];
+
+ union
+ {
+ __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */
+ uint32_t : 1;
+ __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */
+ __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */
+ __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */
+ __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */
+ __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */
+ __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */
+ __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */
+ __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */
+ uint32_t : 1;
+ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */
+ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */
+ uint32_t : 3;
+ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */
+ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */
+ uint32_t : 14;
+ } CGFSAR_b;
+ };
+ __IM uint32_t RESERVED38;
+
+ union
+ {
+ __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
+ uint32_t : 1;
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
+ uint32_t : 1;
+ __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */
+ uint32_t : 3;
+ __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */
+ __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */
+ uint32_t : 22;
+ } LPMSAR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
+ uint32_t : 30;
+ } LVDSAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
+ uint32_t : 29;
+ } RSTSAR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */
+
+ struct
+ {
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
+ uint32_t : 13;
+ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */
+ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */
+ __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */
+ __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */
+ __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */
+ __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */
+ __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */
+ __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */
+ uint32_t : 8;
+ } BBFSAR_b;
+ };
+ __IM uint32_t RESERVED39[3];
+
+ union
+ {
+ __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
+ * 0 */
+ __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
+ * 1 */
+ __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
+ * 2 */
+ __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
+ * 3 */
+ __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
+ * 4 */
+ __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
+ * 5 */
+ __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
+ * 6 */
+ __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
+ * 7 */
+ __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
+ * 8 */
+ __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
+ * 9 */
+ __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
+ * 10 */
+ __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
+ * 11 */
+ __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
+ * 12 */
+ __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
+ * 13 */
+ __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
+ * 14 */
+ __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
+ * 15 */
+ __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
+ * 16 */
+ __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
+ * 17 */
+ __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
+ * 18 */
+ __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
+ * 19 */
+ __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
+ * 20 */
+ uint32_t : 3;
+ __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
+ * 24 */
+ uint32_t : 1;
+ __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
+ * 26 */
+ __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
+ * 27 */
+ uint32_t : 4;
+ } DPFSAR_b;
+ };
+ __IM uint32_t RESERVED40[6];
+ __IM uint16_t RESERVED41;
+
+ union
+ {
+ __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */
+
+ struct
+ {
+ __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock
+ * generation circuit. */
+ __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating
+ * modes, the low power consumption modes and the battery
+ * backup function. */
+ uint16_t : 1;
+ __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */
+ __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */
+ uint16_t : 3;
+ __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */
+ } PRCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */
+
+ struct
+ {
+ __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */
+ uint8_t : 4;
+ __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */
+ __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */
+ } DPSBYCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */
+
+ struct
+ {
+ __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */
+ uint8_t : 2;
+ } DPSWCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */
+ } DPSIER0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */
+ __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */
+ } DPSIER1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */
+
+ struct
+ {
+ __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */
+ uint8_t : 3;
+ } DPSIER2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */
+
+ struct
+ {
+ __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */
+ __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */
+ uint8_t : 4;
+ } DPSIER3_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */
+ } DPSIFR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */
+ __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */
+ } DPSIFR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */
+
+ struct
+ {
+ __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */
+ __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */
+ __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */
+ __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */
+ __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */
+ uint8_t : 3;
+ } DPSIFR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */
+
+ struct
+ {
+ __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */
+ __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */
+ __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */
+ __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */
+ uint8_t : 4;
+ } DPSIFR3_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */
+ } DPSIEGR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */
+
+ struct
+ {
+ __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */
+ __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */
+ } DPSIEGR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */
+
+ struct
+ {
+ __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */
+ __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */
+ uint8_t : 2;
+ __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */
+ uint8_t : 3;
+ } DPSIEGR2_b;
+ };
+ __IM uint8_t RESERVED42;
+
+ union
+ {
+ __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */
+
+ struct
+ {
+ __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */
+ uint8_t : 6;
+ __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */
+ } SYOCDCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */
+
+ struct
+ {
+ __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */
+ uint8_t : 6;
+ } STCONR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */
+
+ struct
+ {
+ __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
+ * the flag. Confirm the value is 1 and then write 0. */
+ __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
+ * to clear the flag. Confirm the value is 1 and then write
+ * 0. */
+ uint8_t : 3;
+ __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
+ * clear the flag. Confirm the value is 1 and then write 0. */
+ } RSTSR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */
+
+ struct
+ {
+ __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */
+ uint8_t : 7;
+ } RSTSR2_b;
+ };
+ __IM uint8_t RESERVED43;
+
+ union
+ {
+ __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
+ * Register */
+
+ struct
+ {
+ uint8_t : 3;
+ __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */
+ __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */
+ __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */
+ __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
+ * Enable */
+ } MOMCR_b;
+ };
+ __IM uint16_t RESERVED44;
+
+ union
+ {
+ __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */
+
+ struct
+ {
+ __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */
+ uint8_t : 6;
+ } FWEPROR_b;
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */
+
+ struct
+ {
+ uint8_t : 5;
+ __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */
+ __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */
+ uint8_t : 1;
+ } LVCMPCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */
+
+ struct
+ {
+ __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+ * drop in voltage) */
+ uint8_t : 2;
+ __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */
+ } LVD1CMPCR_b;
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */
+
+ struct
+ {
+ __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+ * fall in voltage) */
+ __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
+ * fall in voltage) */
+ } LVDLVLR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */
+
+ struct
+ {
+ __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
+ * drop in voltage) */
+ uint8_t : 4;
+ __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */
+ } LVD2CMPCR_b;
+ };
+ };
+ __IM uint8_t RESERVED45;
+
+ union
+ {
+ __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */
+
+ struct
+ {
+ __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
+ __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
+ __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
+ uint8_t : 1;
+ __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
+ __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
+ __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
+ } LVD1CR0_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */
+
+ struct
+ {
+ __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
+ __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
+ __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
+ uint8_t : 1;
+ __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
+ __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
+ __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
+ } LVD2CR0_b;
+ };
+ __IM uint8_t RESERVED46;
+
+ union
+ {
+ __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */
+ uint8_t : 7;
+ } VBATTMNSELR_b;
+ };
+
+ union
+ {
+ __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */
+
+ struct
+ {
+ __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */
+ uint8_t : 7;
+ } VBATTMONR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */
+
+ struct
+ {
+ __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */
+ uint8_t : 7;
+ } VBTCR1_b;
+ };
+ __IM uint32_t RESERVED47[8];
+
+ union
+ {
+ union
+ {
+ __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */
+
+ struct
+ {
+ __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */
+ __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */
+ uint8_t : 2;
+ __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */
+ __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */
+ __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */
+ __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */
+ } DCDCCTL_b;
+ };
+
+ union
+ {
+ __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */
+
+ struct
+ {
+ __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */
+ __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */
+ uint8_t : 6;
+ } LDOSCR_b;
+ };
+ };
+
+ union
+ {
+ __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */
+
+ struct
+ {
+ __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */
+ uint8_t : 6;
+ } VCCSEL_b;
+ };
+ __IM uint16_t RESERVED48;
+
+ union
+ {
+ __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */
+
+ struct
+ {
+ __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */
+ uint8_t : 7;
+ } PL2LDOSCR_b;
+ };
+ __IM uint8_t RESERVED49;
+ __IM uint16_t RESERVED50;
+ __IM uint32_t RESERVED51[14];
+
+ union
+ {
+ __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */
+
+ struct
+ {
+ __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */
+ uint8_t : 7;
+ } SOSCCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */
+
+ struct
+ {
+ __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */
+ uint8_t : 6;
+ } SOMCR_b;
+ };
+ __IM uint16_t RESERVED52;
+ __IM uint32_t RESERVED53[3];
+
+ union
+ {
+ __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */
+
+ struct
+ {
+ __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */
+ uint8_t : 7;
+ } LOCOCR_b;
+ };
+ __IM uint8_t RESERVED54;
+
+ union
+ {
+ __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */
+
+ struct
+ {
+ __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+ * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+ * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+ +126 0111_1111 : +127These bits are added to original LOCO
+ * trimming bits */
+ } LOCOUTCR_b;
+ };
+ __IM uint8_t RESERVED55;
+ __IM uint32_t RESERVED56[7];
+
+ union
+ {
+ __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */
+ uint8_t : 1;
+ __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */
+ } VBTCR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */
+
+ struct
+ {
+ __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */
+ __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */
+ uint8_t : 2;
+ __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */
+ uint8_t : 3;
+ } VBTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */
+
+ struct
+ {
+ __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */
+ uint8_t : 7;
+ } VBTCMPCR_b;
+ };
+ __IM uint8_t RESERVED57;
+
+ union
+ {
+ __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
+ * Register */
+
+ struct
+ {
+ __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */
+ __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */
+ uint8_t : 6;
+ } VBTLVDICR_b;
+ };
+ __IM uint8_t RESERVED58;
+
+ union
+ {
+ __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */
+
+ struct
+ {
+ __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */
+ uint8_t : 7;
+ } VBTWCTLR_b;
+ };
+ __IM uint8_t RESERVED59;
+
+ union
+ {
+ __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */
+
+ struct
+ {
+ uint8_t : 1;
+ __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */
+ __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */
+ __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */
+ __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */
+ __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */
+ uint8_t : 2;
+ } VBTWCH0OTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */
+
+ struct
+ {
+ __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */
+ uint8_t : 1;
+ __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */
+ __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */
+ __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */
+ __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */
+ uint8_t : 2;
+ } VBTWCH1OTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */
+
+ struct
+ {
+ __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */
+ __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */
+ uint8_t : 1;
+ __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */
+ __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */
+ __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */
+ uint8_t : 2;
+ } VBTWCH2OTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */
+
+ struct
+ {
+ __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */
+ __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */
+ __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */
+ uint8_t : 5;
+ } VBTICTLR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */
+
+ struct
+ {
+ __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */
+ __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */
+ __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */
+ __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */
+ __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */
+ __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */
+ uint8_t : 2;
+ } VBTOCTLR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */
+
+ struct
+ {
+ __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */
+ __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */
+ __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */
+ __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */
+ __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */
+ __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */
+ uint8_t : 2;
+ } VBTWTER_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */
+
+ struct
+ {
+ __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */
+ __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */
+ __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */
+ uint8_t : 5;
+ } VBTWEGR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */
+
+ struct
+ {
+ __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */
+ __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */
+ __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */
+ __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */
+ __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */
+ __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */
+ uint8_t : 2;
+ } VBTWFR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */
+
+ struct
+ {
+ uint8_t : 3;
+ __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */
+ uint8_t : 4;
+ } VBTBER_b;
+ };
+ __IM uint8_t RESERVED60;
+ __IM uint16_t RESERVED61;
+ __IM uint32_t RESERVED62[15];
+
+ union
+ {
+ __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */
+
+ struct
+ {
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
+ * data powered by VBATT.The value of this register is retained
+ * even when VCC is not powered but VBATT is powered.VBTBKR
+ * is initialized by VBATT selected voltage power-on-reset. */
+ } VBTBKR_b[512];
+ };
+} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */
+
+/* =========================================================================================================================== */
+/* ================ R_TSN_CAL ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CAL)
+ */
+
+typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */
+{
+ union
+ {
+ __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */
+
+ struct
+ {
+ __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
+ * calibration converted value. */
+ } TSCDR_b;
+ };
+} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */
+
+/* =========================================================================================================================== */
+/* ================ R_TSN_CTRL ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CTRL)
+ */
+
+typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */
+{
+ union
+ {
+ __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */
+ uint8_t : 2;
+ __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */
+ } TSCR_b;
+ };
+} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */
+
+/* =========================================================================================================================== */
+/* ================ R_USB_FS0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Module (R_USB_FS0)
+ */
+
+typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */
+{
+ union
+ {
+ __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
+
+ struct
+ {
+ __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
+ uint16_t : 2;
+ __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */
+ __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
+ __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
+ __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
+ uint16_t : 1;
+ __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */
+ uint16_t : 1;
+ __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */
+ uint16_t : 5;
+ } SYSCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
+
+ struct
+ {
+ __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+ * access cycles) */
+ uint16_t : 12;
+ } BUSWAIT_b;
+ };
+
+ union
+ {
+ __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */
+
+ struct
+ {
+ __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
+ __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */
+ uint16_t : 2;
+ __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
+ * Selected. */
+ __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */
+ uint16_t : 7;
+ __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
+ * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+ * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+ * pin. */
+ } SYSSTS0_b;
+ };
+
+ union
+ {
+ __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
+
+ struct
+ {
+ __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
+ uint16_t : 15;
+ } PLLSTA_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
+
+ struct
+ {
+ __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
+ uint16_t : 1;
+ __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */
+ __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */
+ __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */
+ __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */
+ __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */
+ __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */
+ __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */
+ __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
+ * used when switching from device B to device A while in
+ * OTG mode. If the HNPBTOA bit is 1, the internal function
+ * control keeps the suspended state until the HNP processing
+ * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
+ * set. */
+ uint16_t : 4;
+ } DVSTCTR0_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
+
+ struct
+ {
+ __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
+ uint16_t : 12;
+ } TESTMODE_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
+ __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED3;
+ __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
+ __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED4;
+ __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
+ __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED5;
+ __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */
+ uint16_t : 1;
+ __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */
+ uint16_t : 2;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
+ uint16_t : 2;
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } CFIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } CFIFOCTR_b;
+ };
+ __IM uint32_t RESERVED6;
+
+ union
+ {
+ __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
+ uint16_t : 4;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
+ __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+ * Pipe Data is Read */
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } D0FIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } D0FIFOCTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
+ uint16_t : 4;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
+ __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+ * Pipe Data is Read */
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } D1FIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } D1FIFOCTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
+ __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
+ __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
+ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
+ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
+ __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
+ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
+ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
+ } INTENB0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
+
+ struct
+ {
+ __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
+ uint16_t : 3;
+ __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
+ __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
+ __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
+ uint16_t : 4;
+ __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
+ __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
+ uint16_t : 1;
+ __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
+ __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */
+ } INTENB1_b;
+ };
+ __IM uint16_t RESERVED7;
+
+ union
+ {
+ __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */
+ uint16_t : 6;
+ } BRDYENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */
+ uint16_t : 6;
+ } NRDYENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */
+ __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */
+ uint16_t : 6;
+ } BEMPENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */
+ __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
+ __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */
+ uint16_t : 1;
+ __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */
+ uint16_t : 7;
+ } SOFCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
+
+ struct
+ {
+ __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
+ __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
+ uint16_t : 1;
+ __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
+ __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
+ uint16_t : 2;
+ __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
+ uint16_t : 1;
+ __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
+ uint16_t : 3;
+ __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
+ } PHYSET_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
+
+ struct
+ {
+ __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
+ __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
+ __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
+ __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
+ __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
+ __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
+ __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
+ __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
+ __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
+ __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
+ __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
+ __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
+ } INTSTS0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
+
+ struct
+ {
+ __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */
+ uint16_t : 3;
+ __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
+ __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
+ __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
+ __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */
+ __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
+ __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */
+ } INTSTS1_b;
+ };
+ __IM uint16_t RESERVED8;
+
+ union
+ {
+ __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */
+ uint16_t : 6;
+ } BRDYSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */
+ __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */
+ uint16_t : 6;
+ } NRDYSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */
+ __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */
+ uint16_t : 6;
+ } BEMPSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
+
+ struct
+ {
+ __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */
+ uint16_t : 3;
+ __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */
+ __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
+ } FRMNUM_b;
+ };
+
+ union
+ {
+ __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
+
+ struct
+ {
+ __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
+ uint16_t : 12;
+ __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
+ } UFRMNUM_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
+
+ struct
+ {
+ __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate
+ * the USB address assigned by the host when the USBHS processed
+ * the SET_ADDRESS request successfully. */
+ uint16_t : 1;
+ __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
+ uint16_t : 5;
+ } USBADDR_b;
+ };
+ __IM uint16_t RESERVED9;
+
+ union
+ {
+ __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
+
+ struct
+ {
+ __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
+ * value. */
+ __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */
+ } USBREQ_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
+
+ struct
+ {
+ __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */
+ } USBVAL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
+
+ struct
+ {
+ __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */
+ } USBINDX_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
+
+ struct
+ {
+ __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */
+ } USBLENG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
+ uint16_t : 2;
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
+ uint16_t : 7;
+ } DCPCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+ struct
+ {
+ __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
+ * of data (maximum packet size) in payloads for the DCP. */
+ uint16_t : 5;
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
+ } DCPMAXP_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
+
+ struct
+ {
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
+ __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
+ uint16_t : 2;
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
+ uint16_t : 2;
+ __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
+ uint16_t : 2;
+ __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
+ } DCPCTR_b;
+ };
+ __IM uint16_t RESERVED10;
+
+ union
+ {
+ __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
+
+ struct
+ {
+ __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */
+ uint16_t : 12;
+ } PIPESEL_b;
+ };
+ __IM uint16_t RESERVED11;
+
+ union
+ {
+ __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
+
+ struct
+ {
+ __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
+ * for the selected pipe.Setting 0000b means unused pipe. */
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
+ uint16_t : 2;
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
+ uint16_t : 1;
+ __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
+ __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
+ uint16_t : 3;
+ __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
+ } PIPECFG_b;
+ };
+ __IM uint16_t RESERVED12;
+
+ union
+ {
+ __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+ struct
+ {
+ __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
+ * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
+ * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
+ * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
+ * 64 bytes (040h) (Bits [8:7] are not provided.) */
+ uint16_t : 3;
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
+ } PIPEMAXP_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
+
+ struct
+ {
+ __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
+ * error detection timing for the selected pipe in terms of
+ * frames, which is expressed as nth power of 2. */
+ uint16_t : 9;
+ __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
+ uint16_t : 3;
+ } PIPEPERI_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */
+
+ struct
+ {
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
+ uint16_t : 3;
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
+ __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */
+ __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */
+ uint16_t : 1;
+ __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+ * Split Transaction of the relevant pipe */
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+ * the CSSTS bit of the relevant pipe */
+ __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
+ } PIPE_CTR_b[9];
+ };
+ __IM uint16_t RESERVED13;
+ __IM uint32_t RESERVED14[3];
+ __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
+ __IM uint32_t RESERVED15[3];
+
+ union
+ {
+ __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */
+
+ struct
+ {
+ __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */
+ __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */
+ __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+ __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+ __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+ __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+ uint16_t : 1;
+ __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+ __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */
+ __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */
+ uint16_t : 6;
+ } USBBCCTRL0_b;
+ };
+ __IM uint16_t RESERVED16;
+ __IM uint32_t RESERVED17[4];
+
+ union
+ {
+ __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */
+
+ struct
+ {
+ __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */
+ uint16_t : 15;
+ } UCKSEL_b;
+ };
+ __IM uint16_t RESERVED18;
+ __IM uint32_t RESERVED19;
+
+ union
+ {
+ __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */
+
+ struct
+ {
+ __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */
+ uint16_t : 6;
+ __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */
+ uint16_t : 8;
+ } USBMC_b;
+ };
+ __IM uint16_t RESERVED20;
+
+ union
+ {
+ __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
+
+ struct
+ {
+ uint16_t : 6;
+ __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
+ __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
+ __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
+ uint16_t : 1;
+ } DEVADD_b[10];
+ };
+ __IM uint32_t RESERVED21[3];
+
+ union
+ {
+ __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */
+
+ struct
+ {
+ __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */
+ __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */
+ __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */
+ __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */
+ uint32_t : 28;
+ } PHYSLEW_b;
+ };
+ __IM uint32_t RESERVED22[3];
+
+ union
+ {
+ __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
+
+ struct
+ {
+ uint16_t : 7;
+ __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
+ uint16_t : 8;
+ } LPCTRL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
+
+ struct
+ {
+ uint16_t : 14;
+ __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
+ uint16_t : 1;
+ } LPSTS_b;
+ };
+ __IM uint32_t RESERVED23[15];
+
+ union
+ {
+ __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
+
+ struct
+ {
+ __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
+ __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
+ __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
+ __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
+ __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
+ __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
+ uint16_t : 2;
+ __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
+ __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
+ uint16_t : 6;
+ } BCCTRL_b;
+ };
+ __IM uint16_t RESERVED24;
+
+ union
+ {
+ __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
+
+ struct
+ {
+ __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
+ __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
+ __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+ * only when the L1RESPMD[1:0] value is 2'b11. */
+ __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+ * the L1 state together with the device state bits DVSQ[2:0]. */
+ __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+ * value used for L1NEGOMD.The format is the same as the HIRD
+ * field in HL1CTRL. */
+ uint16_t : 2;
+ __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
+ uint16_t : 1;
+ } PL1CTRL1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
+ __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
+ uint16_t : 3;
+ } PL1CTRL2_b;
+ };
+
+ union
+ {
+ __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
+
+ struct
+ {
+ __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
+ __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
+ uint16_t : 13;
+ } HL1CTRL1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
+
+ struct
+ {
+ __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+ * be set in the ADDR field of LPM token. */
+ uint16_t : 4;
+ __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
+ __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+ * value to be set in the RWE field of LPM token. */
+ uint16_t : 2;
+ __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+ * period at the time of L1 Resume. */
+ } HL1CTRL2_b;
+ };
+ __IM uint32_t RESERVED25[5];
+
+ union
+ {
+ __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+ * Register */
+
+ struct
+ {
+ uint32_t : 20;
+ __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+ * HS side of USB port. */
+ __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+ * HS side of USB port. */
+ uint32_t : 1;
+ __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+ * of USB port. */
+ uint32_t : 8;
+ } DPUSR0R_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+ struct
+ {
+ uint32_t : 4;
+ __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
+ __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
+ uint32_t : 1;
+ __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
+ uint32_t : 12;
+ __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
+ __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
+ uint32_t : 1;
+ __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
+ uint32_t : 8;
+ } DPUSR1R_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+ struct
+ {
+ __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
+ __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
+ uint16_t : 2;
+ __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+ * port. */
+ __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+ * port. */
+ uint16_t : 2;
+ __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
+ __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
+ uint16_t : 6;
+ } DPUSR2R_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+ struct
+ {
+ __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
+ __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
+ uint16_t : 14;
+ } DPUSRCR_b;
+ };
+ __IM uint32_t RESERVED26[165];
+
+ union
+ {
+ __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
+ * Monitor Register */
+
+ struct
+ {
+ __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */
+ __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */
+ uint32_t : 1;
+ __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */
+ __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */
+ uint32_t : 11;
+ __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+ __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */
+ uint32_t : 2;
+ __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
+ * of the USB. */
+ __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
+ * of the USB. */
+ uint32_t : 1;
+ __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
+ * USB. */
+ uint32_t : 8;
+ } DPUSR0R_FS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */
+ __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */
+ uint32_t : 2;
+ __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */
+ __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */
+ uint32_t : 1;
+ __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */
+ uint32_t : 8;
+ __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */
+ __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */
+ uint32_t : 2;
+ __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */
+ __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */
+ uint32_t : 1;
+ __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */
+ uint32_t : 8;
+ } DPUSR1R_FS_b;
+ };
+} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */
+
+/* =========================================================================================================================== */
+/* ================ R_WDT ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer (R_WDT)
+ */
+
+typedef struct /*!< (@ 0x40083400) R_WDT Structure */
+{
+ union
+ {
+ __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */
+
+ struct
+ {
+ __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
+ * of the WDT. */
+ } WDTRR_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */
+
+ struct
+ {
+ __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */
+ uint16_t : 2;
+ __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */
+ __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */
+ uint16_t : 2;
+ __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */
+ uint16_t : 2;
+ } WDTCR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */
+
+ struct
+ {
+ __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */
+ __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
+ __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
+ } WDTSR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */
+ } WDTRCR_b;
+ };
+ __IM uint8_t RESERVED1;
+
+ union
+ {
+ __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */
+
+ struct
+ {
+ uint8_t : 7;
+ __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */
+ } WDTCSTPR_b;
+ };
+ __IM uint8_t RESERVED2;
+ __IM uint16_t RESERVED3;
+} R_WDT_Type; /*!< Size = 12 (0xc) */
+
+/* =========================================================================================================================== */
+/* ================ R_TZF ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief TrustZone Filter (R_TZF)
+ */
+
+typedef struct /*!< (@ 0x40000E00) R_TZF Structure */
+{
+ union
+ {
+ __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */
+
+ struct
+ {
+ __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */
+ } TZFOAD_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */
+
+ struct
+ {
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
+ uint16_t : 7;
+ __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */
+ } TZFPT_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[94];
+
+ union
+ {
+ __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */
+ uint32_t : 31;
+ } TZFSAR_b;
+ };
+} R_TZF_Type; /*!< Size = 388 (0x184) */
+
+/* =========================================================================================================================== */
+/* ================ R_CACHE ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_CACHE (R_CACHE)
+ */
+
+typedef struct /*!< (@ 0x40007000) R_CACHE Structure */
+{
+ union
+ {
+ __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */
+
+ struct
+ {
+ __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */
+ uint32_t : 31;
+ } CCACTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */
+
+ struct
+ {
+ __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */
+ uint32_t : 31;
+ } CCAFCT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */
+ uint32_t : 30;
+ } CCALCF_b;
+ };
+ __IM uint32_t RESERVED[13];
+
+ union
+ {
+ __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */
+
+ struct
+ {
+ __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */
+ uint32_t : 31;
+ } SCACTL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */
+
+ struct
+ {
+ __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */
+ uint32_t : 31;
+ } SCAFCT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */
+ uint32_t : 30;
+ } SCALCF_b;
+ };
+ __IM uint32_t RESERVED1[109];
+
+ union
+ {
+ __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */
+ uint32_t : 31;
+ } CAPOAD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */
+
+ struct
+ {
+ __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */
+ __IOM uint32_t KW : 7; /*!< [7..1] Write key code */
+ uint32_t : 24;
+ } CAPRCR_b;
+ };
+} R_CACHE_Type; /*!< Size = 520 (0x208) */
+
+/* =========================================================================================================================== */
+/* ================ R_CPSCU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU System Security Control Unit (R_CPSCU)
+ */
+
+typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */
+{
+ union
+ {
+ __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */
+ __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */
+ __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */
+ uint32_t : 29;
+ } CSAR_b;
+ };
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */
+ __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
+ * 2 */
+ __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */
+ uint32_t : 29;
+ } SRAMSAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */
+ uint32_t : 28;
+ } STBRAMSAR_b;
+ };
+ __IM uint32_t RESERVED1[6];
+
+ union
+ {
+ __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */
+ uint32_t : 31;
+ } DTCSAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */
+ uint32_t : 31;
+ } DMACSAR_b;
+ };
+ __IM uint32_t RESERVED2[2];
+
+ union
+ {
+ __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */
+
+ struct
+ {
+ __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */
+ uint32_t : 16;
+ } ICUSARA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */
+
+ struct
+ {
+ __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */
+ uint32_t : 31;
+ } ICUSARB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */
+
+ struct
+ {
+ __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */
+ uint32_t : 24;
+ } ICUSARC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */
+
+ struct
+ {
+ __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */
+ uint32_t : 31;
+ } ICUSARD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */
+ uint32_t : 1;
+ __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */
+ __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */
+ __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */
+ uint32_t : 3;
+ __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */
+ __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */
+ uint32_t : 1;
+ __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */
+ __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */
+ __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */
+ __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */
+ __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */
+ } ICUSARE_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */
+
+ struct
+ {
+ __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */
+ __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */
+ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */
+ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */
+ uint32_t : 4;
+ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */
+ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */
+ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */
+ __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */
+ __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */
+ __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */
+ __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */
+ uint32_t : 17;
+ } ICUSARF_b;
+ };
+ __IM uint32_t RESERVED3[6];
+
+ union
+ {
+ __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */
+
+ struct
+ {
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */
+ } ICUSARG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */
+
+ struct
+ {
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */
+ } ICUSARH_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */
+
+ struct
+ {
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */
+ } ICUSARI_b;
+ };
+ __IM uint32_t RESERVED4[33];
+
+ union
+ {
+ __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */
+
+ struct
+ {
+ __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */
+ uint32_t : 31;
+ } BUSSARA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */
+
+ struct
+ {
+ __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */
+ uint32_t : 31;
+ } BUSSARB_b;
+ };
+ __IM uint32_t RESERVED5[10];
+
+ union
+ {
+ __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
+ * Register A */
+
+ struct
+ {
+ __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */
+ uint32_t : 24;
+ } MMPUSARA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
+ * Register B */
+
+ struct
+ {
+ __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */
+ uint32_t : 31;
+ } MMPUSARB_b;
+ };
+ __IM uint32_t RESERVED6[26];
+
+ union
+ {
+ __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */
+
+ struct
+ {
+ __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
+ * channel */
+ uint32_t : 24;
+ } DMASARA_b;
+ };
+ __IM uint32_t RESERVED7[3];
+
+ union
+ {
+ __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */
+
+ struct
+ {
+ __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */
+ uint32_t : 31;
+ } CPUDSAR_b;
+ };
+ __IM uint32_t RESERVED8[275];
+
+ union
+ {
+ __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */
+
+ struct
+ {
+ __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
+ * and ELCSRn */
+ uint32_t : 31;
+ } TEVTRCR_b;
+ };
+} R_CPSCU_Type; /*!< Size = 1540 (0x604) */
+
+/* =========================================================================================================================== */
+/* ================ R_CEC ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Consumer Electronics Control (R_CEC)
+ */
+
+typedef struct /*!< (@ 0x400AC000) R_CEC Structure */
+{
+ union
+ {
+ __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */
+
+ struct
+ {
+ __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */
+ __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device
+ * 1) */
+ __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device
+ * 2) */
+ __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */
+ __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */
+ __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */
+ __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */
+ __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */
+ __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */
+ __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device
+ * 3) */
+ __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */
+ __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device
+ * 3) */
+ __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */
+ __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */
+ __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */
+ uint16_t : 1;
+ } CADR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */
+
+ struct
+ {
+ __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */
+ __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
+ * Select */
+ __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */
+ __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */
+ __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */
+ __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */
+ } CECCTL1_b;
+ };
+ __IM uint8_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */
+
+ struct
+ {
+ __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */
+ uint16_t : 7;
+ } STATB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */
+ uint16_t : 7;
+ } STATL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */
+ uint16_t : 7;
+ } LGC0L_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */
+ uint16_t : 7;
+ } LGC1L_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */
+
+ struct
+ {
+ __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */
+ uint16_t : 7;
+ } DATB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */
+
+ struct
+ {
+ __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */
+ uint16_t : 7;
+ } NOMT_b;
+ };
+
+ union
+ {
+ __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */
+ uint16_t : 7;
+ } STATLL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */
+ uint16_t : 7;
+ } STATLH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */
+ uint16_t : 7;
+ } STATBL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */
+ uint16_t : 7;
+ } STATBH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */
+ uint16_t : 7;
+ } LGC0LL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */
+ uint16_t : 7;
+ } LGC0LH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */
+ uint16_t : 7;
+ } LGC1LL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */
+ uint16_t : 7;
+ } LGC1LH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */
+ uint16_t : 7;
+ } DATBL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */
+ uint16_t : 7;
+ } DATBH_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */
+
+ struct
+ {
+ __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */
+ uint16_t : 7;
+ } NOMP_b;
+ };
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */
+ __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */
+ uint8_t : 1;
+ __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */
+ } CECEXMD_b;
+ };
+ __IM uint8_t RESERVED2;
+
+ union
+ {
+ __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */
+
+ struct
+ {
+ __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */
+ __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */
+ uint8_t : 6;
+ } CECEXMON_b;
+ };
+ __IM uint8_t RESERVED3;
+ __IM uint16_t RESERVED4[10];
+ __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */
+ __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */
+
+ union
+ {
+ __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */
+
+ struct
+ {
+ __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */
+ __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */
+ __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */
+ __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */
+ __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */
+ __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */
+ __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */
+ uint8_t : 1;
+ } CECES_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */
+
+ struct
+ {
+ __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */
+ __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */
+ __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */
+ __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */
+ __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */
+ uint8_t : 2;
+ __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */
+ } CECS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */
+
+ struct
+ {
+ __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */
+ __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */
+ __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */
+ __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */
+ __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */
+ __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */
+ __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */
+ uint8_t : 1;
+ } CECFC_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */
+
+ struct
+ {
+ __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */
+ __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */
+ __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */
+ __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */
+ __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */
+ __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */
+ } CECCTL0_b;
+ };
+} R_CEC_Type; /*!< Size = 70 (0x46) */
+
+/* =========================================================================================================================== */
+/* ================ R_OSPI ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Octa Serial Peripheral Interface (R_OSPI)
+ */
+
+typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */
+{
+ union
+ {
+ __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */
+
+ struct
+ {
+ __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */
+ __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */
+ uint32_t : 16;
+ } DCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */
+
+ struct
+ {
+ __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */
+ __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */
+ __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */
+ __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */
+ } DAR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */
+
+ struct
+ {
+ __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */
+ __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */
+ uint32_t : 3;
+ __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */
+ __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */
+ __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */
+ __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */
+ __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */
+ __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */
+ __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */
+ uint32_t : 2;
+ } DCSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */
+
+ struct
+ {
+ __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */
+ __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */
+ } DSR_b[2];
+ };
+
+ union
+ {
+ __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */
+
+ struct
+ {
+ __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */
+ __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */
+ __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */
+ __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */
+ __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */
+ uint32_t : 4;
+ } MDTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */
+
+ struct
+ {
+ __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */
+ } ACTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */
+
+ struct
+ {
+ __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */
+ } ACAR_b[2];
+ };
+ __IM uint32_t RESERVED[4];
+
+ union
+ {
+ __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting
+ * in PCLKH units */
+ __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */
+ __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */
+ __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */
+ __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */
+ __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting
+ * in PCLKH units */
+ __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */
+ __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */
+ __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */
+ __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */
+ } DRCSTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting
+ * in PCLKH units */
+ __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */
+ __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */
+ __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */
+ __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */
+ __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting
+ * in PCLKH units */
+ __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */
+ __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */
+ __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */
+ __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */
+ } DWCSTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */
+ __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */
+ __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */
+ uint32_t : 16;
+ } DCSTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */
+
+ struct
+ {
+ __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */
+ __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */
+ __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */
+ __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */
+ uint32_t : 4;
+ __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device
+ * 0 */
+ __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device
+ * 1 */
+ __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */
+ uint32_t : 17;
+ __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */
+ } CDSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */
+
+ struct
+ {
+ __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */
+ __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */
+ __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */
+ __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */
+ } MDLR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */
+
+ struct
+ {
+ __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */
+ __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */
+ __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */
+ __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */
+ } MRWCR_b[2];
+ };
+
+ union
+ {
+ __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */
+
+ struct
+ {
+ __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */
+ __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */
+ __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */
+ __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */
+ __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */
+ __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */
+ __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */
+ uint32_t : 1;
+ __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */
+ __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */
+ __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */
+ __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */
+ __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */
+ __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */
+ __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */
+ uint32_t : 1;
+ } MRWCSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */
+
+ struct
+ {
+ __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */
+ __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */
+ uint32_t : 16;
+ } ESR_b;
+ };
+
+ union
+ {
+ __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */
+
+ struct
+ {
+ __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */
+ } CWNDR_b;
+ };
+
+ union
+ {
+ __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */
+
+ struct
+ {
+ __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */
+ __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */
+ __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */
+ __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */
+ } CWDR_b;
+ };
+
+ union
+ {
+ __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */
+
+ struct
+ {
+ __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */
+ __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */
+ __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */
+ __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */
+ } CRR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */
+
+ struct
+ {
+ __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */
+ __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */
+ uint32_t : 26;
+ } ACSR_b;
+ };
+ __IM uint32_t RESERVED1[5];
+
+ union
+ {
+ __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */
+
+ struct
+ {
+ __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are
+ * Low in single continuous write of OctaRAM. */
+ uint32_t : 7;
+ __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1
+ * are Low in single continuous read of OctaRAM. */
+ uint32_t : 7;
+ } DCSMXR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating
+ * size Register */
+
+ struct
+ {
+ __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single
+ * continuous write of device 0. */
+ uint32_t : 5;
+ __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single
+ * continuous write of device 1. */
+ uint32_t : 5;
+ } DWSCTSR_b;
+ };
+} R_OSPI_Type; /*!< Size = 132 (0x84) */
+
+/* =========================================================================================================================== */
+/* ================ R_USB_HS0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 High-Speed Module (R_USB_HS0)
+ */
+
+typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */
+{
+ union
+ {
+ __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
+
+ struct
+ {
+ __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
+ uint16_t : 3;
+ __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
+ __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
+ __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
+ __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */
+ __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */
+ uint16_t : 7;
+ } SYSCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
+
+ struct
+ {
+ __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+ * access cycles) */
+ uint16_t : 12;
+ } BUSWAIT_b;
+ };
+
+ union
+ {
+ __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */
+
+ struct
+ {
+ __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
+ __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */
+ uint16_t : 2;
+ __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
+ * Selected. */
+ __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */
+ uint16_t : 7;
+ __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe
+ * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+ * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+ * pin. */
+ } SYSSTS0_b;
+ };
+
+ union
+ {
+ __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
+
+ struct
+ {
+ __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
+ uint16_t : 15;
+ } PLLSTA_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
+
+ struct
+ {
+ __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
+ uint16_t : 1;
+ __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */
+ __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */
+ __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */
+ __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller
+ * Operation */
+ __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */
+ __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */
+ __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */
+ __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit
+ * when switching from device B to device A in OTGmode. If
+ * the HNPBTOA bit is 1, the internal function controlremains
+ * in the Suspend state until the HNP processing endseven
+ * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */
+ uint16_t : 4;
+ } DVSTCTR0_b;
+ };
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
+
+ struct
+ {
+ __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
+ uint16_t : 12;
+ } TESTMODE_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
+
+ struct
+ {
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or
+ * write transmit data to the FIFO buffer by accessing these
+ * bits. */
+ } CFIFO_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
+ __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED3;
+ __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
+
+ struct
+ {
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or
+ * write transmit data to the FIFO buffer by accessing these
+ * bits. */
+ } D0FIFO_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
+ __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED4;
+ __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ union
+ {
+ __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
+
+ struct
+ {
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write
+ * transmit data to the FIFO buffer by accessing these bits. */
+ } D1FIFO_b;
+ };
+
+ struct
+ {
+ union
+ {
+ __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
+ __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
+
+ struct
+ {
+ __IM uint8_t RESERVED5;
+ __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
+ };
+ };
+ };
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
+ uint16_t : 1;
+ __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */
+ uint16_t : 2;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
+ uint16_t : 2;
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } CFIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
+ * be accessed. */
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } CFIFOCTR_b;
+ };
+ __IM uint32_t RESERVED6;
+
+ union
+ {
+ __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
+ uint16_t : 4;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
+ __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+ * Pipe Data is Read */
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } D0FIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
+ * be accessed. */
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } D0FIFOCTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
+
+ struct
+ {
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
+ uint16_t : 4;
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
+ uint16_t : 1;
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
+ __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+ * Pipe Data is Read */
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
+ } D1FIFOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
+
+ struct
+ {
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
+ * data. */
+ uint16_t : 1;
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
+ * be accessed. */
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
+ } D1FIFOCTR_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
+ __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
+ __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
+ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
+ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
+ __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
+ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
+ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
+ } INTENB0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
+
+ struct
+ {
+ __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
+ uint16_t : 3;
+ __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
+ __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
+ __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
+ uint16_t : 1;
+ __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */
+ __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */
+ uint16_t : 1;
+ __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
+ __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
+ uint16_t : 1;
+ __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
+ __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */
+ } INTENB1_b;
+ };
+ __IM uint16_t RESERVED7;
+
+ union
+ {
+ __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */
+ uint16_t : 6;
+ } BRDYENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */
+ uint16_t : 6;
+ } NRDYENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */
+ uint16_t : 6;
+ } BEMPENB_b;
+ };
+
+ union
+ {
+ __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */
+ __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
+ __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be
+ * set only in the initial setting (before communications).The
+ * setting cannot be changed once communication starts. */
+ uint16_t : 1;
+ __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency
+ * can be improved by setting this bit to 1 if no low-speed
+ * device is connected directly or via FS-HUB to the USB port. */
+ uint16_t : 7;
+ } SOFCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
+
+ struct
+ {
+ __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
+ __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
+ uint16_t : 1;
+ __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
+ __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
+ uint16_t : 2;
+ __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
+ uint16_t : 1;
+ __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
+ uint16_t : 3;
+ __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
+ } PHYSET_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
+
+ struct
+ {
+ __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
+ __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
+ __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
+ __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
+ __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
+ __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
+ __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
+ __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
+ __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
+ __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
+ __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
+ __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
+ } INTSTS0_b;
+ };
+
+ union
+ {
+ __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
+
+ struct
+ {
+ __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */
+ uint16_t : 3;
+ __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
+ __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
+ __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
+ __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */
+ __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
+ uint16_t : 1;
+ __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
+ __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */
+ } INTSTS1_b;
+ };
+ __IM uint16_t RESERVED8;
+
+ union
+ {
+ __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */
+ uint16_t : 6;
+ } BRDYSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */
+ uint16_t : 6;
+ } NRDYSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
+
+ struct
+ {
+ __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */
+ uint16_t : 6;
+ } BEMPSTS_b;
+ };
+
+ union
+ {
+ __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
+
+ struct
+ {
+ __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */
+ uint16_t : 3;
+ __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */
+ __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
+ } FRMNUM_b;
+ };
+
+ union
+ {
+ __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
+
+ struct
+ {
+ __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
+ uint16_t : 12;
+ __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
+ } UFRMNUM_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
+ uint16_t : 5;
+ } USBADDR_b;
+ };
+ __IM uint16_t RESERVED9;
+
+ union
+ {
+ __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
+
+ struct
+ {
+ __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected
+ * : read-only Host controller selected : read-write */
+ __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected
+ * : read-only Host controller selected : read-write */
+ } USBREQ_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
+
+ struct
+ {
+ __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected
+ * : read-only Host controller selected : read-write */
+ } USBVAL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
+
+ struct
+ {
+ __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected
+ * : read-only Host controller selected : read-write */
+ } USBINDX_b;
+ };
+
+ union
+ {
+ __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
+
+ struct
+ {
+ __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected
+ * : read-only Host controller selected : read-write */
+ } USBLENG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
+
+ struct
+ {
+ uint16_t : 4;
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
+ uint16_t : 2;
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
+ uint16_t : 7;
+ } DCPCFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+ struct
+ {
+ __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data
+ * payload (maximum packet size) for the DCP. */
+ uint16_t : 5;
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
+ * destination function device for control transfer when the
+ * host controller function is selected. */
+ } DCPMAXP_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
+
+ struct
+ {
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
+ __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
+ uint16_t : 1;
+ __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */
+ uint16_t : 2;
+ __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
+ __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */
+ __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
+ } DCPCTR_b;
+ };
+ __IM uint16_t RESERVED10;
+ __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
+ __IM uint16_t RESERVED11;
+
+ union
+ {
+ __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
+
+ struct
+ {
+ __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
+ uint16_t : 2;
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
+ __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
+ __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
+ uint16_t : 3;
+ __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
+ } PIPECFG_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */
+
+ struct
+ {
+ __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number
+ * of the selected pipe (04h to 87h). */
+ uint16_t : 2;
+ __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */
+ uint16_t : 1;
+ } PIPEBUF_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+ struct
+ {
+ __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data
+ * payload (maximum packet size) for the selected pipe.A size
+ * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */
+ uint16_t : 1;
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
+ * peripheral device when the host controller function is
+ * selected. */
+ } PIPEMAXP_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
+
+ struct
+ {
+ __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the
+ * transfer interval timing for the selected pipe as n-th
+ * power of 2 of the frame timing. */
+ uint16_t : 9;
+ __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
+ uint16_t : 3;
+ } PIPEPERI_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */
+
+ struct
+ {
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for
+ * the next transaction of the relevant pipe. */
+ uint16_t : 3;
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe
+ * is being used for the USB bus */
+ __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected
+ * value of the sequence toggle bit for the next transaction
+ * of the relevant pipe */
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected
+ * value of the sequence toggle bit for the next transaction
+ * of the relevant pipe is set for DATA1 */
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected
+ * value of the sequence toggle bit for the next transaction
+ * of the relevant pipe is cleared to DATA0 */
+ __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto
+ * buffer clear mode for the relevant pipe */
+ __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto
+ * response mode for the relevant pipe. */
+ uint16_t : 1;
+ __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+ * Split Transaction of the relevant pipe */
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+ * the CSSTS bit of the relevant pipe */
+ __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO
+ * buffer status for the relevant pipe in the transmitting
+ * direction. */
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status
+ * for the relevant pipe. */
+ } PIPE_CTR_b[9];
+ };
+ __IM uint16_t RESERVED12;
+ __IM uint32_t RESERVED13[3];
+ __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
+ __IM uint32_t RESERVED14[11];
+
+ union
+ {
+ __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
+
+ struct
+ {
+ uint16_t : 6;
+ __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
+ __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
+ __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
+ uint16_t : 1;
+ } DEVADD_b[10];
+ };
+ __IM uint32_t RESERVED15[7];
+
+ union
+ {
+ __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
+
+ struct
+ {
+ uint16_t : 7;
+ __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
+ uint16_t : 8;
+ } LPCTRL_b;
+ };
+
+ union
+ {
+ __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
+
+ struct
+ {
+ uint16_t : 14;
+ __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
+ uint16_t : 1;
+ } LPSTS_b;
+ };
+ __IM uint32_t RESERVED16[15];
+
+ union
+ {
+ __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
+
+ struct
+ {
+ __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
+ __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
+ __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
+ __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
+ __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
+ __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
+ uint16_t : 2;
+ __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
+ __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
+ uint16_t : 6;
+ } BCCTRL_b;
+ };
+ __IM uint16_t RESERVED17;
+
+ union
+ {
+ __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
+
+ struct
+ {
+ __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
+ __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
+ __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+ * only when the L1RESPMD[1:0] value is 2'b11. */
+ __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+ * the L1 state together with the device state bits DVSQ[2:0]. */
+ __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+ * value used for L1NEGOMD.The format is the same as the HIRD
+ * field in HL1CTRL. */
+ uint16_t : 2;
+ __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
+ uint16_t : 1;
+ } PL1CTRL1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
+
+ struct
+ {
+ uint16_t : 8;
+ __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
+ __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
+ uint16_t : 3;
+ } PL1CTRL2_b;
+ };
+
+ union
+ {
+ __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
+
+ struct
+ {
+ __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
+ __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
+ uint16_t : 13;
+ } HL1CTRL1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
+
+ struct
+ {
+ __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+ * be set in the ADDR field of LPM token. */
+ uint16_t : 4;
+ __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
+ __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+ * value to be set in the RWE field of LPM token. */
+ uint16_t : 2;
+ __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+ * period at the time of L1 Resume. */
+ } HL1CTRL2_b;
+ };
+ __IM uint32_t RESERVED18;
+
+ union
+ {
+ __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */
+
+ struct
+ {
+ __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */
+ __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */
+ uint16_t : 3;
+ __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */
+ __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */
+ __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset
+ * value for adjusting the terminating resistance. */
+ uint16_t : 1;
+ } PHYTRIM1_b;
+ };
+
+ union
+ {
+ __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */
+
+ struct
+ {
+ __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */
+ uint16_t : 3;
+ __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */
+ __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */
+ uint16_t : 2;
+ __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */
+ uint16_t : 1;
+ } PHYTRIM2_b;
+ };
+ __IM uint32_t RESERVED19[3];
+
+ union
+ {
+ __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+ * Register */
+
+ struct
+ {
+ uint32_t : 20;
+ __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+ * HS side of USB port. */
+ __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+ * HS side of USB port. */
+ uint32_t : 1;
+ __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+ * of USB port. */
+ uint32_t : 8;
+ } DPUSR0R_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+ struct
+ {
+ uint32_t : 4;
+ __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
+ __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
+ uint32_t : 1;
+ __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
+ uint32_t : 12;
+ __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
+ __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
+ uint32_t : 1;
+ __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
+ uint32_t : 8;
+ } DPUSR1R_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+ struct
+ {
+ __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
+ __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
+ uint16_t : 2;
+ __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+ * port. */
+ __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+ * port. */
+ uint16_t : 2;
+ __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
+ __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
+ uint16_t : 6;
+ } DPUSR2R_b;
+ };
+
+ union
+ {
+ __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+ struct
+ {
+ __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
+ __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
+ uint16_t : 14;
+ } DPUSRCR_b;
+ };
+} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */
+
+/* =========================================================================================================================== */
+/* ================ R_AGTX0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */
+{
+ union
+ {
+ __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */
+ __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */
+ };
+} R_AGTX0_Type; /*!< Size = 20 (0x14) */
+
+/* =========================================================================================================================== */
+/* ================ R_FLAD ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Flash (R_FLAD)
+ */
+
+typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */
+{
+ __IM uint8_t RESERVED[64];
+
+ union
+ {
+ __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */
+
+ struct
+ {
+ __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */
+ } FCKMHZ_b;
+ };
+} R_FLAD_Type; /*!< Size = 65 (0x41) */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_ADC0_BASE 0x40170000UL
+ #define R_ADC1_BASE 0x40170200UL
+ #define R_PSCU_BASE 0x400E0000UL
+ #define R_BUS_BASE 0x40003000UL
+ #define R_CAC_BASE 0x40083600UL
+ #define R_CANFD_BASE 0x400B0000UL
+ #define R_CRC_BASE 0x40108000UL
+ #define R_CTSU_BASE 0x400D0000UL
+ #define R_DAC_BASE 0x40171000UL
+ #define R_DEBUG_BASE 0x4001B000UL
+ #define R_DMA_BASE 0x40005200UL
+ #define R_DMAC0_BASE 0x40005000UL
+ #define R_DMAC1_BASE 0x40005040UL
+ #define R_DMAC2_BASE 0x40005080UL
+ #define R_DMAC3_BASE 0x400050C0UL
+ #define R_DMAC4_BASE 0x40005100UL
+ #define R_DMAC5_BASE 0x40005140UL
+ #define R_DMAC6_BASE 0x40005180UL
+ #define R_DMAC7_BASE 0x400051C0UL
+ #define R_DOC_BASE 0x40109000UL
+ #define R_DTC_BASE 0x40005400UL
+ #define R_ELC_BASE 0x40082000UL
+ #define R_ETHERC0_BASE 0x40114100UL
+ #define R_ETHERC_EDMAC_BASE 0x40114000UL
+ #define R_FACI_HP_CMD_BASE 0x407E0000UL
+ #define R_FACI_HP_BASE 0x407FE000UL
+ #define R_FCACHE_BASE 0x4001C000UL
+ #define R_GPT0_BASE 0x40169000UL
+ #define R_GPT1_BASE 0x40169100UL
+ #define R_GPT2_BASE 0x40169200UL
+ #define R_GPT3_BASE 0x40169300UL
+ #define R_GPT4_BASE 0x40169400UL
+ #define R_GPT5_BASE 0x40169500UL
+ #define R_GPT6_BASE 0x40169600UL
+ #define R_GPT7_BASE 0x40169700UL
+ #define R_GPT8_BASE 0x40169800UL
+ #define R_GPT9_BASE 0x40169900UL
+ #define R_GPT10_BASE 0x40169A00UL
+ #define R_GPT11_BASE 0x40169B00UL
+ #define R_GPT12_BASE 0x40169C00UL
+ #define R_GPT13_BASE 0x40169D00UL
+ #define R_GPT_OPS_BASE 0x40169A00UL
+ #define R_GPT_POEG0_BASE 0x4008A000UL
+ #define R_GPT_POEG1_BASE 0x4008A100UL
+ #define R_GPT_POEG2_BASE 0x4008A200UL
+ #define R_GPT_POEG3_BASE 0x4008A300UL
+ #define R_ICU_BASE 0x40006000UL
+ #define R_IIC0_BASE 0x4009F000UL
+ #define R_IIC1_BASE 0x4009F100UL
+ #define R_IIC2_BASE 0x4009F200UL
+ #define R_IWDT_BASE 0x40083200UL
+ #define R_I3C0_BASE 0x4011F000UL
+ #define R_I3C1_BASE 0x4011F400UL
+ #define R_MPU_MMPU_BASE 0x40000000UL
+ #define R_MPU_SMPU_BASE 0x40000C00UL
+ #define R_MPU_SPMON_BASE 0x40000D00UL
+ #define R_MSTP_BASE 0x40084000UL
+ #define R_PORT0_BASE 0x40080000UL
+ #define R_PORT1_BASE 0x40080020UL
+ #define R_PORT2_BASE 0x40080040UL
+ #define R_PORT3_BASE 0x40080060UL
+ #define R_PORT4_BASE 0x40080080UL
+ #define R_PORT5_BASE 0x400800A0UL
+ #define R_PORT6_BASE 0x400800C0UL
+ #define R_PORT7_BASE 0x400800E0UL
+ #define R_PORT8_BASE 0x40080100UL
+ #define R_PORT9_BASE 0x40080120UL
+ #define R_PORT10_BASE 0x40080140UL
+ #define R_PORT11_BASE 0x40080160UL
+ #define R_PORT12_BASE 0x40080180UL
+ #define R_PORT13_BASE 0x400801A0UL
+ #define R_PORT14_BASE 0x400801C0UL
+ #define R_PFS_BASE 0x40080800UL
+ #define R_PMISC_BASE 0x40080D00UL
+ #define R_QSPI_BASE 0x64000000UL
+ #define R_RTC_BASE 0x40083000UL
+ #define R_SCI0_BASE 0x40118000UL
+ #define R_SCI1_BASE 0x40118100UL
+ #define R_SCI2_BASE 0x40118200UL
+ #define R_SCI3_BASE 0x40118300UL
+ #define R_SCI4_BASE 0x40118400UL
+ #define R_SCI5_BASE 0x40118500UL
+ #define R_SCI6_BASE 0x40118600UL
+ #define R_SCI7_BASE 0x40118700UL
+ #define R_SCI8_BASE 0x40118800UL
+ #define R_SCI9_BASE 0x40118900UL
+ #define R_SDHI0_BASE 0x40092000UL
+ #define R_SDHI1_BASE 0x40092400UL
+ #define R_SPI0_BASE 0x4011A000UL
+ #define R_SPI1_BASE 0x4011A100UL
+ #define R_SRAM_BASE 0x40002000UL
+ #define R_BUS_B_BASE 0x40003000UL
+ #define R_SSI0_BASE 0x4009D000UL
+ #define R_SSI1_BASE 0x4009D100UL
+ #define R_SYSTEM_BASE 0x4001E000UL
+ #define R_TSN_CAL_BASE 0x407FB17CUL
+ #define R_TSN_CTRL_BASE 0x400F3000UL
+ #define R_USB_FS0_BASE 0x40090000UL
+ #define R_WDT_BASE 0x40083400UL
+ #define R_TZF_BASE 0x40000E00UL
+ #define R_CACHE_BASE 0x40007000UL
+ #define R_CPSCU_BASE 0x40008000UL
+ #define R_CEC_BASE 0x400AC000UL
+ #define R_OSPI_BASE 0x400A6000UL
+ #define R_USB_HS0_BASE 0x40111000UL
+ #define R_AGTX0_BASE 0x400E8000UL
+ #define R_AGTX1_BASE 0x400E8100UL
+ #define R_AGTX2_BASE 0x400E8200UL
+ #define R_AGTX3_BASE 0x400E8300UL
+ #define R_AGTX4_BASE 0x400E8400UL
+ #define R_AGTX5_BASE 0x400E8500UL
+ #define R_AGTX6_BASE 0x400E8600UL
+ #define R_AGTX7_BASE 0x400E8700UL
+ #define R_AGTX8_BASE 0x400E8800UL
+ #define R_AGTX9_BASE 0x400E8900UL
+ #define R_FLAD_BASE 0x407FC000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
+ #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
+ #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
+
+/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */
+ #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
+ #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
+ #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
+ #define R_DAC ((R_DAC_Type *) R_DAC_BASE)
+ #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
+ #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
+ #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
+ #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
+ #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
+ #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
+ #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
+ #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
+ #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
+ #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
+ #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
+ #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
+ #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
+ #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
+ #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
+ #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
+ #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
+ #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
+ #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
+ #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
+ #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
+ #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
+ #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
+ #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
+ #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
+ #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
+ #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
+ #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
+ #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
+ #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
+ #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
+ #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
+ #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
+ #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
+ #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
+ #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
+ #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
+ #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
+ #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
+ #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
+ #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
+ #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
+ #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
+ #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
+ #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
+ #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
+ #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
+ #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
+ #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
+ #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
+ #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
+ #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
+ #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
+ #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
+ #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
+ #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
+ #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
+ #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
+ #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
+ #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
+ #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
+ #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
+ #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
+ #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
+ #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
+ #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
+ #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
+ #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
+ #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE)
+ #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
+ #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
+ #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
+ #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
+ #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
+ #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
+ #define R_TZF ((R_TZF_Type *) R_TZF_BASE)
+ #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
+ #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_CEC ((R_CEC_Type *) R_CEC_BASE)
+ #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
+ #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0 ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1 ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2 ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3 ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4 ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5 ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6 ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7 ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8 ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9 ((R_AGTX0_Type *) R_AGTX9_BASE)
+ #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* ========================================= End of section using anonymous unions ========================================= */
+ #if defined(__CC_ARM)
+ #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+ #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Cluster Section ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================ CSa ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== MOD ========================================================== */
+ #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
+ #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
+ #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
+ #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
+ #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
+ #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
+/* ========================================================= WCR1 ========================================================== */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
+/* ========================================================= WCR2 ========================================================== */
+ #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
+ #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
+ #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
+ #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
+ #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
+ #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
+ #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
+ #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
+ #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
+ #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
+
+/* =========================================================================================================================== */
+/* ================ CSb ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+ #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
+ #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
+ #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
+ #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
+ #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
+ #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
+/* ========================================================== REC ========================================================== */
+ #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
+ #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
+ #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
+ #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ SDRAM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SDCCR ========================================================= */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
+/* ======================================================== SDCMOD ========================================================= */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */
+/* ======================================================== SDAMOD ========================================================= */
+ #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */
+ #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */
+/* ======================================================== SDSELF ========================================================= */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */
+/* ======================================================== SDRFCR ========================================================= */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */
+/* ======================================================== SDRFEN ========================================================= */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */
+/* ========================================================= SDICR ========================================================= */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */
+/* ========================================================= SDIR ========================================================== */
+ #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */
+ #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */
+ #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */
+ #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */
+ #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */
+ #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */
+/* ========================================================= SDADR ========================================================= */
+ #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */
+ #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */
+/* ========================================================= SDTR ========================================================== */
+ #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */
+ #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */
+ #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */
+ #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */
+ #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */
+ #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */
+ #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */
+ #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */
+ #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */
+ #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */
+/* ========================================================= SDMOD ========================================================= */
+ #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */
+ #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */
+/* ========================================================= SDSR ========================================================== */
+ #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */
+ #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */
+ #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */
+ #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */
+ #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */
+ #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ BUSERR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ADD ========================================================== */
+ #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
+ #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= STAT ========================================================== */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ BUSM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CNT ========================================================== */
+ #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */
+ #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ BUSS ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CNT ========================================================== */
+ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */
+ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ CFDC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= NCFG ========================================================== */
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */
+/* ========================================================== CTR ========================================================== */
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */
+ #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+ #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */
+ #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+ #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */
+ #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */
+ #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */
+ #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */
+ #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */
+ #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */
+ #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */
+ #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */
+ #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */
+ #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */
+ #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */
+ #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */
+ #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */
+ #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */
+ #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
+/* ========================================================== STS ========================================================== */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */
+ #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */
+ #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */
+ #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */
+ #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */
+ #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */
+ #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */
+ #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERFL ========================================================== */
+ #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */
+ #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */
+ #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */
+ #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */
+ #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */
+ #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */
+ #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */
+ #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */
+ #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */
+ #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */
+ #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DCFG ========================================================== */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDCFG ========================================================= */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */
+/* ========================================================= FDCTR ========================================================= */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */
+/* ========================================================= FDCRC ========================================================= */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */
+/* ========================================================= BLCT ========================================================== */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */
+/* ========================================================= BLSTS ========================================================= */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDGAFL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */
+/* =========================================================== M =========================================================== */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */
+/* ========================================================== P0 =========================================================== */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== P1 =========================================================== */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDTHL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ACC0 ========================================================== */
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */
+/* ========================================================= ACC1 ========================================================== */
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ CFDRM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */
+ #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */
+ #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */
+ #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */
+ #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */
+ #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDRF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */
+ #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */
+ #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDCF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */
+ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */
+ #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDTM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */
+ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */
+ #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDCTR ========================================================= */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
+ #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ ELSEGR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BY =========================================================== */
+ #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */
+ #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */
+ #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */
+ #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ ELSR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== HA =========================================================== */
+ #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */
+ #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */
+
+/* =========================================================================================================================== */
+/* ================ SAR ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================== L =========================================================== */
+ #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */
+ #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */
+/* =========================================================== U =========================================================== */
+ #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */
+ #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */
+ #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */
+ #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */
+ #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */
+ #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ REGION ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================== C =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */
+ #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */
+ #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */
+ #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */
+ #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
+ #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
+/* =========================================================== S =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */
+ #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */
+/* =========================================================== E =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */
+ #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ MMPU ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CTL ========================================================== */
+ #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */
+ #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */
+ #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
+ #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
+/* ========================================================== PT =========================================================== */
+ #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
+ #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ SMPU ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================== R =========================================================== */
+ #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */
+ #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */
+ #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */
+ #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */
+ #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */
+ #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */
+ #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ SP ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== OAD ========================================================== */
+ #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+/* ========================================================== CTL ========================================================== */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
+/* ========================================================== PT =========================================================== */
+ #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
+/* ========================================================== SA =========================================================== */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== EA =========================================================== */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ PIN ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================= PmnPFS_BY ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
+/* ======================================================= PmnPFS_HA ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
+/* ======================================================== PmnPFS ========================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ PORT ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ VLSEL ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== VL1SEL ========================================================= */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ PMSAR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= PMSAR ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================ RTCCR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= RTCCR ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */
+ #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */
+ #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ CP ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= RSEC ========================================================== */
+ #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
+ #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
+ #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT0 ========================================================= */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */
+/* ========================================================= RMIN ========================================================== */
+ #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
+ #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
+ #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT1 ========================================================= */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */
+/* ========================================================== RHR ========================================================== */
+ #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */
+ #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
+ #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
+ #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT2 ========================================================= */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */
+/* ========================================================= RDAY ========================================================== */
+ #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
+ #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
+ #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT3 ========================================================= */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */
+/* ========================================================= RMON ========================================================== */
+ #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
+ #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
+ #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
+ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ CSa ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== MOD ========================================================== */
+ #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
+ #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
+ #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
+ #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
+ #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
+ #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
+/* ========================================================= WCR1 ========================================================== */
+ #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
+ #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
+ #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
+ #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
+ #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
+/* ========================================================= WCR2 ========================================================== */
+ #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
+ #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
+ #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
+ #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
+ #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
+ #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
+ #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
+ #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
+ #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
+ #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
+
+/* =========================================================================================================================== */
+/* ================ CSb ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+ #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
+ #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
+ #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
+ #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
+ #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
+ #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
+/* ========================================================== REC ========================================================== */
+ #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
+ #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
+ #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
+ #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ BUSERR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ADD ========================================================== */
+ #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
+ #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ERRRW ========================================================= */
+ #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */
+ #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ BUSTZFERR ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== TZFADD ========================================================= */
+ #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */
+ #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= TZFERRRW ======================================================== */
+ #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */
+ #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ PIPE_TR ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================== E =========================================================== */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */
+/* =========================================================== N =========================================================== */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */
+
+/* =========================================================================================================================== */
+/* ================ PIPE_TR ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================== E =========================================================== */
+ #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */
+ #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */
+ #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */
+/* =========================================================== N =========================================================== */
+ #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */
+ #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */
+
+/* =========================================================================================================================== */
+/* ================ CTRL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= AGTCR ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTMR1 ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */
+/* ======================================================== AGTMR2 ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
+/* ===================================================== AGTIOSEL_ALT ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
+/* ======================================================== AGTIOC ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTISR ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTCMSR ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
+/* ======================================================= AGTIOSEL ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ AGT16 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== AGT ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */
+/* ======================================================== AGTCMA ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */
+/* ======================================================== AGTCMB ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */
+
+/* =========================================================================================================================== */
+/* ================ AGT32 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== AGT ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== AGTCMA ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== AGTCMB ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================ R_ADC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ADCSR ========================================================= */
+ #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */
+ #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */
+ #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */
+ #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */
+ #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */
+ #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */
+ #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */
+ #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */
+ #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */
+ #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */
+ #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */
+/* ======================================================== ADANSA ========================================================= */
+ #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */
+ #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */
+/* ========================================================= ADADS ========================================================= */
+ #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */
+ #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */
+/* ========================================================= ADADC ========================================================= */
+ #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */
+ #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */
+ #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */
+ #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */
+/* ========================================================= ADCER ========================================================= */
+ #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */
+ #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */
+ #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */
+ #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */
+ #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */
+ #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */
+ #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */
+ #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */
+ #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */
+/* ======================================================== ADSTRGR ======================================================== */
+ #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */
+ #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */
+ #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */
+ #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */
+/* ======================================================== ADEXICR ======================================================== */
+ #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */
+ #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */
+ #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */
+ #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */
+ #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */
+ #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */
+ #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */
+ #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */
+ #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */
+/* ======================================================== ADANSB ========================================================= */
+ #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */
+ #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */
+/* ======================================================== ADDBLDR ======================================================== */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADTSDR ========================================================= */
+ #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */
+ #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADOCDR ========================================================= */
+ #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */
+ #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */
+/* ====================================================== ADRD_RIGHT ======================================================= */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */
+ #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */
+/* ======================================================= ADRD_LEFT ======================================================= */
+ #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */
+ #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
+/* ========================================================= ADDR ========================================================== */
+ #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+ #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADSHCR ========================================================= */
+ #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */
+ #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */
+ #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */
+ #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */
+ #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */
+/* ======================================================== ADDISCR ======================================================== */
+ #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */
+ #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */
+ #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADSHMSR ======================================================== */
+ #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */
+ #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */
+/* ======================================================== ADACSR ========================================================= */
+ #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */
+ #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */
+/* ======================================================== ADGSPCR ======================================================== */
+ #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */
+ #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */
+ #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */
+ #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */
+/* ========================================================= ADICR ========================================================= */
+ #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */
+ #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */
+/* ======================================================= ADDBLDRA ======================================================== */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADDBLDRB ======================================================== */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */
+/* ====================================================== ADHVREFCNT ======================================================= */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */
+/* ======================================================= ADWINMON ======================================================== */
+ #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */
+ #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */
+ #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */
+ #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */
+/* ======================================================== ADCMPCR ======================================================== */
+ #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */
+ #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */
+ #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */
+ #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */
+ #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */
+ #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */
+ #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */
+/* ====================================================== ADCMPANSER ======================================================= */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCMPLER ======================================================== */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCMPANSR ======================================================= */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADCMPLR ======================================================== */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCMPDR0 ======================================================== */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPDR1 ======================================================== */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADCMPSR ======================================================== */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCMPSER ======================================================== */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCMPBNSR ======================================================= */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADWINLLB ======================================================== */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADWINULB ======================================================== */
+ #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */
+ #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPBSR ======================================================== */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */
+/* ======================================================== ADSSTRL ======================================================== */
+ #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */
+ #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
+/* ======================================================== ADSSTRT ======================================================== */
+ #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */
+ #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
+/* ======================================================== ADSSTRO ======================================================== */
+ #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */
+ #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
+/* ======================================================== ADSSTR ========================================================= */
+ #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */
+ #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
+/* ======================================================== ADPGACR ======================================================== */
+ #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */
+ #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */
+ #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */
+ #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */
+ #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */
+ #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */
+ #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */
+ #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */
+ #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */
+ #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */
+ #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */
+ #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */
+ #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */
+ #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */
+ #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */
+ #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */
+ #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */
+/* ========================================================= ADRD ========================================================== */
+ #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */
+ #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */
+/* ========================================================= ADRST ========================================================= */
+ #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
+ #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
+/* ====================================================== VREFAMPCNT ======================================================= */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */
+ #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCALEXE ======================================================== */
+ #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */
+ #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */
+ #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */
+/* ======================================================== ADANIM ========================================================= */
+ #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */
+ #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */
+/* ======================================================= ADPGAGS0 ======================================================== */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADPGADCR0 ======================================================= */
+ #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */
+ #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */
+ #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */
+ #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */
+ #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */
+ #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */
+ #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */
+ #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */
+ #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */
+/* ========================================================= ADREF ========================================================= */
+ #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */
+ #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */
+ #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */
+/* ======================================================== ADEXREF ======================================================== */
+ #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */
+ #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */
+/* ======================================================= ADAMPOFF ======================================================== */
+ #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */
+ #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */
+/* ======================================================== ADTSTPR ======================================================== */
+ #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */
+ #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */
+ #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDDACER ======================================================== */
+ #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */
+ #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */
+ #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */
+ #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */
+ #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */
+ #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */
+/* ======================================================= ADEXTSTR ======================================================== */
+ #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */
+ #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */
+ #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */
+ #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */
+ #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */
+/* ======================================================== ADTSTRA ======================================================== */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */
+ #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */
+ #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */
+ #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADTSTRB ======================================================== */
+ #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */
+ #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */
+/* ======================================================== ADTSTRC ======================================================== */
+ #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */
+ #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */
+ #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */
+ #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */
+/* ======================================================== ADTSTRD ======================================================== */
+ #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */
+ #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADSWTSTR0 ======================================================= */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADSWTSTR1 ======================================================= */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADSWTSTR2 ======================================================= */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */
+/* ======================================================== ADSWCR ========================================================= */
+ #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */
+ #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */
+ #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */
+ #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */
+/* ======================================================== ADGSCS ========================================================= */
+ #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */
+ #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */
+ #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */
+ #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */
+/* ========================================================= ADSER ========================================================= */
+ #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */
+ #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */
+/* ======================================================== ADBUF0 ========================================================= */
+ #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF1 ========================================================= */
+ #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF2 ========================================================= */
+ #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF3 ========================================================= */
+ #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF4 ========================================================= */
+ #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF5 ========================================================= */
+ #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF6 ========================================================= */
+ #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF7 ========================================================= */
+ #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF8 ========================================================= */
+ #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF9 ========================================================= */
+ #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF10 ======================================================== */
+ #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF11 ======================================================== */
+ #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF12 ======================================================== */
+ #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF13 ======================================================== */
+ #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF14 ======================================================== */
+ #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUF15 ======================================================== */
+ #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
+ #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADBUFEN ======================================================== */
+ #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */
+ #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */
+/* ======================================================= ADBUFPTR ======================================================== */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */
+ #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */
+ #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */
+/* ======================================================= ADPGADBS0 ======================================================= */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */
+/* ======================================================= ADPGADBS1 ======================================================= */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */
+/* ======================================================= ADREFMON ======================================================== */
+ #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
+ #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
+ #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */
+ #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ R_PSCU ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= PSARB ========================================================= */
+ #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */
+ #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */
+ #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */
+ #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */
+ #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */
+ #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */
+ #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */
+ #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */
+ #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */
+ #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */
+ #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */
+ #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */
+ #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */
+ #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */
+ #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */
+ #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */
+ #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */
+ #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */
+ #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */
+ #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */
+ #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */
+ #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */
+ #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */
+ #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */
+/* ========================================================= PSARC ========================================================= */
+ #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */
+ #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */
+ #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */
+ #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */
+ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */
+ #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */
+ #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */
+ #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */
+ #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */
+ #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */
+/* ========================================================= PSARD ========================================================= */
+ #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */
+ #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */
+ #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */
+ #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */
+ #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */
+ #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */
+ #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */
+ #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */
+ #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */
+ #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */
+ #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */
+ #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */
+ #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */
+ #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */
+ #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */
+ #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */
+ #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */
+ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */
+/* ========================================================= PSARE ========================================================= */
+ #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */
+ #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */
+ #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */
+ #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */
+ #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */
+ #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */
+ #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */
+ #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */
+ #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */
+ #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */
+ #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */
+ #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */
+ #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */
+ #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */
+ #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */
+ #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */
+/* ========================================================= MSSAR ========================================================= */
+ #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */
+ #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */
+ #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */
+ #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */
+ #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */
+/* ======================================================= CFSAMONA ======================================================== */
+ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */
+ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */
+/* ======================================================= CFSAMONB ======================================================== */
+ #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */
+ #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */
+/* ======================================================== DFSAMON ======================================================== */
+ #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */
+ #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */
+/* ======================================================== SSAMONA ======================================================== */
+ #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */
+ #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */
+/* ======================================================== SSAMONB ======================================================== */
+ #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */
+ #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */
+/* ======================================================== DLMMON ========================================================= */
+ #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */
+ #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ R_BUS ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CSRECEN ======================================================== */
+ #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
+ #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
+ #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
+ #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_CAC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CACR0 ========================================================= */
+ #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */
+ #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */
+/* ========================================================= CACR1 ========================================================= */
+ #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */
+ #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */
+ #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
+ #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */
+ #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */
+ #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */
+ #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */
+ #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */
+/* ========================================================= CACR2 ========================================================= */
+ #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */
+ #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */
+ #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */
+ #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */
+ #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */
+ #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */
+ #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */
+ #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */
+/* ========================================================= CAICR ========================================================= */
+ #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */
+ #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */
+ #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */
+ #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */
+ #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */
+ #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */
+ #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */
+ #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */
+ #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */
+ #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */
+ #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */
+ #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CASTR ========================================================= */
+ #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */
+ #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */
+ #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */
+ #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */
+ #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */
+ #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */
+/* ======================================================== CAULVR ========================================================= */
+ #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */
+ #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */
+/* ======================================================== CALLVR ========================================================= */
+ #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */
+ #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */
+/* ======================================================== CACNTBR ======================================================== */
+ #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */
+ #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_CANFD ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CFDGCFG ======================================================== */
+ #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */
+ #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */
+ #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */
+ #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */
+ #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */
+ #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */
+ #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */
+ #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */
+ #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */
+ #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */
+ #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */
+/* ======================================================== CFDGCTR ======================================================== */
+ #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */
+ #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */
+ #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */
+ #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */
+ #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */
+ #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */
+ #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */
+ #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */
+ #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */
+ #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */
+/* ======================================================== CFDGSTS ======================================================== */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGERFL ======================================================== */
+ #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */
+ #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */
+ #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */
+ #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */
+ #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */
+ #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */
+ #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */
+ #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */
+ #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */
+ #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */
+ #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */
+ #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */
+/* ======================================================== CFDGTSC ======================================================== */
+ #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */
+ #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */
+/* ====================================================== CFDGAFLECTR ====================================================== */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDGAFLCFG0 ====================================================== */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */
+/* ======================================================== CFDRMNB ======================================================== */
+ #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */
+ #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */
+ #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */
+/* ======================================================= CFDRMND0 ======================================================== */
+ #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */
+ #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CFDRFCC ======================================================== */
+ #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */
+ #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */
+ #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */
+ #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */
+ #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */
+ #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */
+ #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDRFSTS ======================================================== */
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */
+ #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */
+ #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */
+ #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDRFPCTR ======================================================= */
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */
+/* ======================================================== CFDCFCC ======================================================== */
+ #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */
+ #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */
+ #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */
+ #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */
+ #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */
+ #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */
+ #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */
+ #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */
+ #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */
+ #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDCFCCE ======================================================== */
+ #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */
+ #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */
+ #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDCFSTS ======================================================== */
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */
+ #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */
+ #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */
+ #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDCFPCTR ======================================================= */
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDFESTS ======================================================== */
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */
+/* ======================================================= CFDFFSTS ======================================================== */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */
+/* ======================================================= CFDFMSTS ======================================================== */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */
+/* ======================================================= CFDRFISTS ======================================================= */
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDCFRISTS ======================================================= */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */
+/* ====================================================== CFDCFTISTS ======================================================= */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */
+/* ===================================================== CFDCFOFRISTS ====================================================== */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */
+/* ===================================================== CFDCFOFTISTS ====================================================== */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */
+/* ====================================================== CFDCFMOWSTS ====================================================== */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */
+/* ======================================================= CFDFFFSTS ======================================================= */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */
+/* ======================================================== CFDTMC ========================================================= */
+ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */
+ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */
+ #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */
+ #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDTMSTS ======================================================== */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTMTRSTS ======================================================= */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDTMTARSTS ====================================================== */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDTMTCSTS ======================================================= */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDTMTASTS ======================================================= */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTMIEC ======================================================== */
+ #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */
+ #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTXQCC0 ======================================================= */
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQSTS0 ======================================================= */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQPCTR0 ====================================================== */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTXQCC1 ======================================================= */
+ #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
+ #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQSTS1 ======================================================= */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQPCTR1 ====================================================== */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTXQCC2 ======================================================= */
+ #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
+ #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQSTS2 ======================================================= */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQPCTR2 ====================================================== */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTXQCC3 ======================================================= */
+ #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
+ #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQSTS3 ======================================================= */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTXQPCTR3 ====================================================== */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDTXQESTS ======================================================= */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */
+/* ====================================================== CFDTXQFISTS ====================================================== */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */
+/* ====================================================== CFDTXQMSTS ======================================================= */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */
+/* ====================================================== CFDTXQISTS ======================================================= */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */
+/* ===================================================== CFDTXQOFTISTS ===================================================== */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */
+/* ===================================================== CFDTXQOFRISTS ===================================================== */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */
+/* ====================================================== CFDTXQFSTS ======================================================= */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */
+/* ======================================================= CFDTHLCC ======================================================== */
+ #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */
+ #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */
+ #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */
+ #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */
+ #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDTHLSTS ======================================================= */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */
+/* ====================================================== CFDTHLPCTR ======================================================= */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */
+/* ===================================================== CFDGTINTSTS0 ====================================================== */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDGTSTCFG ======================================================= */
+ #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */
+ #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */
+/* ====================================================== CFDGTSTCTR ======================================================= */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGFDCFG ======================================================= */
+ #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */
+ #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */
+/* ====================================================== CFDGCRCCFG ======================================================= */
+ #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */
+ #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGLOCKK ======================================================= */
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */
+/* ======================================================= CFDGLOTB ======================================================== */
+ #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */
+ #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */
+ #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */
+ #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */
+ #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */
+ #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */
+/* ===================================================== CFDGAFLIGNENT ===================================================== */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */
+ #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */
+ #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */
+/* ===================================================== CFDGAFLIGNCTR ===================================================== */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDCDTCT ======================================================== */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDCDTSTS ======================================================= */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDCDTTCT ======================================================= */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDCDTTSTS ======================================================= */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDGRINTSTS ====================================================== */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */
+/* ======================================================= CFDGRSTC ======================================================== */
+ #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */
+ #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
+ #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDRPGACC ======================================================= */
+ #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
+ #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_CRC ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CRCCR0 ========================================================= */
+ #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */
+ #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */
+ #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */
+ #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */
+ #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */
+ #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */
+/* ======================================================== CRCCR1 ========================================================= */
+ #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */
+ #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */
+ #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */
+ #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */
+/* ======================================================== CRCDIR ========================================================= */
+ #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */
+ #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= CRCDIR_BY ======================================================= */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */
+/* ======================================================== CRCDOR ========================================================= */
+ #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */
+ #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= CRCDOR_HA ======================================================= */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */
+/* ======================================================= CRCDOR_BY ======================================================= */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */
+/* ======================================================== CRCSAR ========================================================= */
+ #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */
+ #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */
+
+/* =========================================================================================================================== */
+/* ================ R_CTSU ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CTSUCR0 ======================================================== */
+ #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */
+ #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */
+ #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */
+ #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */
+ #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */
+ #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */
+ #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */
+/* ======================================================== CTSUCR1 ======================================================== */
+ #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */
+ #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */
+ #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */
+ #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */
+ #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */
+ #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */
+ #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */
+/* ======================================================= CTSUSDPRS ======================================================= */
+ #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */
+ #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */
+ #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */
+ #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */
+/* ======================================================== CTSUSST ======================================================== */
+ #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */
+ #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */
+/* ======================================================= CTSUMCH0 ======================================================== */
+ #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */
+ #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */
+/* ======================================================= CTSUMCH1 ======================================================== */
+ #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */
+ #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */
+/* ======================================================= CTSUCHAC ======================================================== */
+ #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */
+ #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */
+/* ======================================================= CTSUCHTRC ======================================================= */
+ #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */
+ #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */
+/* ======================================================= CTSUDCLKC ======================================================= */
+ #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */
+ #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */
+ #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */
+/* ======================================================== CTSUST ========================================================= */
+ #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */
+ #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */
+ #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */
+ #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */
+ #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */
+ #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */
+/* ======================================================== CTSUSSC ======================================================== */
+ #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */
+ #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */
+/* ======================================================== CTSUSO0 ======================================================== */
+ #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */
+ #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */
+ #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */
+ #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */
+/* ======================================================== CTSUSO1 ======================================================== */
+ #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */
+ #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */
+ #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */
+ #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */
+ #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */
+/* ======================================================== CTSUSC ========================================================= */
+ #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */
+ #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */
+/* ======================================================== CTSURC ========================================================= */
+ #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */
+ #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */
+/* ======================================================= CTSUERRS ======================================================== */
+ #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */
+ #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */
+ #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */
+ #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */
+ #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */
+ #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */
+ #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */
+ #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */
+/* ======================================================= CTSUTRMR ======================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_DAC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DACR ========================================================== */
+ #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */
+ #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */
+ #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */
+ #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */
+/* ========================================================= DADR ========================================================== */
+ #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */
+ #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */
+/* ========================================================= DADPR ========================================================= */
+ #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */
+ #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */
+/* ======================================================== DAADSCR ======================================================== */
+ #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */
+ #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */
+/* ======================================================= DAVREFCR ======================================================== */
+ #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */
+ #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */
+/* ========================================================= DAPC ========================================================== */
+ #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */
+ #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */
+/* ======================================================== DAAMPCR ======================================================== */
+ #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */
+ #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */
+/* ======================================================== DAASWCR ======================================================== */
+ #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */
+ #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */
+ #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */
+ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */
+/* ======================================================== DAADUSR ======================================================== */
+ #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */
+ #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */
+ #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */
+ #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_DEBUG ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== DBGSTR ========================================================= */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */
+/* ======================================================= DBGSTOPCR ======================================================= */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_DMA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DMAST ========================================================= */
+ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */
+ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */
+/* ======================================================== DMECHR ========================================================= */
+ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */
+ #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */
+ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */
+ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */
+ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */
+ #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */
+/* ========================================================= DELSR ========================================================= */
+ #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
+ #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
+ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */
+ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */
+
+/* =========================================================================================================================== */
+/* ================ R_DMAC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DMSAR ========================================================= */
+ #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */
+ #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= DMDAR ========================================================= */
+ #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */
+ #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= DMCRA ========================================================= */
+ #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */
+ #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */
+ #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */
+ #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */
+/* ========================================================= DMCRB ========================================================= */
+ #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */
+ #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */
+ #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */
+ #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */
+/* ========================================================= DMTMD ========================================================= */
+ #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */
+ #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */
+ #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */
+ #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */
+ #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */
+ #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */
+/* ========================================================= DMINT ========================================================= */
+ #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */
+ #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */
+ #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */
+ #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */
+ #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */
+ #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAMD ========================================================= */
+ #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */
+ #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */
+ #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */
+ #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */
+ #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */
+ #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */
+ #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */
+ #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */
+ #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */
+ #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */
+/* ========================================================= DMOFR ========================================================= */
+ #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */
+ #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= DMCNT ========================================================= */
+ #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */
+ #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */
+/* ========================================================= DMREQ ========================================================= */
+ #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */
+ #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */
+ #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */
+/* ========================================================= DMSTS ========================================================= */
+ #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */
+ #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */
+ #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */
+ #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */
+ #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */
+/* ========================================================= DMSRR ========================================================= */
+/* ========================================================= DMDRR ========================================================= */
+/* ========================================================= DMSBS ========================================================= */
+ #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */
+ #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */
+ #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */
+ #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */
+/* ========================================================= DMDBS ========================================================= */
+ #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */
+ #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */
+ #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */
+ #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */
+/* ========================================================= DMBWR ========================================================= */
+ #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */
+ #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_DOC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DOCR ========================================================== */
+ #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */
+ #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
+ #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */
+ #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
+ #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */
+ #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */
+ #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
+ #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
+/* ========================================================= DODIR ========================================================= */
+ #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */
+ #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */
+/* ========================================================= DODSR ========================================================= */
+ #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */
+ #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_DTC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DTCCR ========================================================= */
+ #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */
+ #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */
+/* ======================================================== DTCVBR ========================================================= */
+ #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */
+ #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= DTCST ========================================================= */
+ #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */
+ #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */
+/* ======================================================== DTCSTS ========================================================= */
+ #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */
+ #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */
+ #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */
+ #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */
+/* ======================================================= DTCCR_SEC ======================================================= */
+ #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */
+ #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */
+/* ====================================================== DTCVBR_SEC ======================================================= */
+/* ========================================================= DTEVR ========================================================= */
+ #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */
+ #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */
+ #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */
+ #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */
+ #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */
+ #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_ELC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ELCR ========================================================== */
+ #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */
+ #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */
+/* ======================================================== ELCSARA ======================================================== */
+ #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */
+ #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */
+ #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */
+ #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
+/* ======================================================== ELCSARB ======================================================== */
+ #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */
+ #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */
+ #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */
+ #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */
+ #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */
+ #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */
+ #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */
+ #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */
+ #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */
+ #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */
+ #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */
+ #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */
+ #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */
+ #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */
+ #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */
+ #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */
+ #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */
+/* ======================================================== ELCSARC ======================================================== */
+ #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */
+ #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */
+ #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */
+ #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_ETHERC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ECMR ========================================================== */
+ #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */
+ #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */
+ #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */
+ #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */
+ #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */
+ #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */
+ #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */
+ #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */
+ #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */
+ #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */
+ #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */
+ #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */
+ #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */
+ #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */
+/* ========================================================= RFLR ========================================================== */
+ #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */
+ #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */
+/* ========================================================= ECSR ========================================================== */
+ #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */
+ #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */
+ #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */
+ #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */
+ #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */
+ #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */
+/* ======================================================== ECSIPR ========================================================= */
+ #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */
+ #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */
+ #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */
+ #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */
+/* ========================================================== PIR ========================================================== */
+ #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */
+ #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */
+ #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */
+ #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */
+ #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */
+ #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */
+/* ========================================================== PSR ========================================================== */
+ #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */
+ #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */
+/* ========================================================= RDMLR ========================================================= */
+ #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */
+ #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */
+/* ========================================================= IPGR ========================================================== */
+ #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */
+ #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */
+/* ========================================================== APR ========================================================== */
+ #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */
+ #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */
+/* ========================================================== MPR ========================================================== */
+ #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */
+ #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */
+/* ========================================================= RFCF ========================================================== */
+ #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */
+ #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */
+/* ======================================================== TPAUSER ======================================================== */
+ #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */
+ #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */
+/* ======================================================= TPAUSECR ======================================================== */
+/* ========================================================= BCFRR ========================================================= */
+ #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */
+ #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAHR ========================================================== */
+ #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */
+ #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= MALR ========================================================== */
+ #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */
+ #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */
+/* ========================================================= TROCR ========================================================= */
+ #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */
+ #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CDCR ========================================================== */
+/* ========================================================= LCCR ========================================================== */
+ #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */
+ #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CNDCR ========================================================= */
+ #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */
+ #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CEFCR ========================================================= */
+ #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */
+ #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= FRECR ========================================================= */
+ #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */
+ #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TSFRCR ========================================================= */
+ #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */
+ #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TLFRCR ========================================================= */
+ #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */
+ #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= RFCR ========================================================== */
+ #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */
+ #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= MAFCR ========================================================= */
+ #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */
+ #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_ETHERC_EDMAC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= EDMR ========================================================== */
+ #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */
+ #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */
+ #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */
+ #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */
+ #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */
+/* ========================================================= EDTRR ========================================================= */
+ #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */
+ #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */
+/* ========================================================= EDRRR ========================================================= */
+ #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */
+ #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */
+/* ========================================================= TDLAR ========================================================= */
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= RDLAR ========================================================= */
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= EESR ========================================================== */
+ #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */
+ #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */
+ #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */
+ #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */
+ #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */
+ #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */
+ #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */
+ #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */
+ #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */
+ #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */
+ #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */
+ #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */
+ #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */
+ #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */
+ #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */
+ #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */
+ #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */
+ #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */
+ #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */
+ #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */
+ #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */
+ #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */
+/* ======================================================== EESIPR ========================================================= */
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */
+/* ======================================================== TRSCER ========================================================= */
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */
+/* ========================================================= RMFCR ========================================================= */
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */
+/* ========================================================= TFTR ========================================================== */
+ #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */
+ #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */
+/* ========================================================== FDR ========================================================== */
+ #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */
+ #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */
+ #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */
+ #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */
+/* ========================================================= RMCR ========================================================== */
+ #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */
+ #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */
+/* ========================================================= TFUCR ========================================================= */
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */
+/* ========================================================= RFOCR ========================================================= */
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */
+/* ========================================================= IOSR ========================================================== */
+ #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */
+ #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */
+/* ========================================================= FCFTR ========================================================= */
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */
+/* ======================================================== RPADIR ========================================================= */
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */
+/* ========================================================= TRIMD ========================================================= */
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */
+/* ========================================================= RBWAR ========================================================= */
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= RDFAR ========================================================= */
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TBRAR ========================================================= */
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TDFAR ========================================================= */
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_FACI_HP_CMD ================ */
+/* =========================================================================================================================== */
+
+/* ====================================================== FACI_CMD16 ======================================================= */
+/* ======================================================= FACI_CMD8 ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================ R_FACI_HP ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== FASTAT ========================================================= */
+ #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */
+ #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */
+ #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */
+ #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */
+/* ======================================================== FAEINT ========================================================= */
+ #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */
+ #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */
+ #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */
+/* ======================================================== FRDYIE ========================================================= */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */
+/* ======================================================== FSADDR ========================================================= */
+ #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */
+ #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== FEADDR ========================================================= */
+ #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */
+ #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== FMEPROT ======================================================== */
+ #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */
+ #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */
+/* ======================================================== FBPROT0 ======================================================== */
+ #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */
+ #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */
+/* ======================================================== FBPROT1 ======================================================== */
+ #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */
+ #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */
+/* ======================================================== FSTATR ========================================================= */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */
+ #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */
+ #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */
+ #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */
+ #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */
+ #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */
+ #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */
+ #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */
+ #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */
+ #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */
+ #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */
+ #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */
+ #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */
+/* ======================================================== FENTRYR ======================================================== */
+ #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */
+/* ======================================================= FSUINITR ======================================================== */
+ #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */
+ #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */
+/* ========================================================= FCMDR ========================================================= */
+ #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */
+ #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */
+ #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */
+/* ======================================================== FBCCNT ========================================================= */
+ #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */
+ #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */
+/* ======================================================== FBCSTAT ======================================================== */
+ #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */
+ #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */
+/* ======================================================== FPSADDR ======================================================== */
+ #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */
+ #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */
+/* ======================================================== FAWMON ========================================================= */
+ #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */
+ #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */
+ #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */
+ #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */
+ #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */
+ #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */
+ #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */
+/* ========================================================= FCPSR ========================================================= */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */
+/* ======================================================== FPCKAR ========================================================= */
+ #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */
+ #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */
+/* ======================================================== FSUACR ========================================================= */
+ #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */
+ #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ R_FCACHE ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== FCACHEE ======================================================== */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */
+/* ======================================================= FCACHEIV ======================================================== */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */
+/* ========================================================= FLWT ========================================================== */
+ #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */
+ #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */
+/* ========================================================= FSAR ========================================================== */
+ #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */
+ #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */
+ #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */
+ #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= GTWP ========================================================== */
+ #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
+ #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
+ #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */
+ #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */
+ #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */
+ #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */
+ #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */
+ #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */
+/* ========================================================= GTSTR ========================================================= */
+ #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */
+ #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
+/* ========================================================= GTSTP ========================================================= */
+ #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */
+ #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
+/* ========================================================= GTCLR ========================================================= */
+ #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */
+ #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */
+/* ========================================================= GTSSR ========================================================= */
+ #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */
+ #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */
+ #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */
+ #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */
+ #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */
+ #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */
+ #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */
+ #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */
+ #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */
+ #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */
+ #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */
+ #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */
+ #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */
+/* ========================================================= GTPSR ========================================================= */
+ #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */
+ #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */
+ #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */
+ #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */
+ #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */
+ #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */
+ #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */
+ #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */
+ #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */
+ #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */
+ #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */
+ #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */
+ #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */
+/* ========================================================= GTCSR ========================================================= */
+ #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */
+ #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */
+ #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */
+ #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */
+ #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */
+ #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */
+ #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */
+ #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */
+ #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */
+ #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */
+ #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */
+ #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */
+ #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */
+ #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */
+ #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */
+/* ======================================================== GTUPSR ========================================================= */
+ #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */
+ #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */
+ #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */
+ #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */
+ #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */
+ #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */
+ #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */
+ #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */
+ #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */
+ #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */
+ #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */
+ #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */
+ #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */
+/* ======================================================== GTDNSR ========================================================= */
+ #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */
+ #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */
+ #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */
+ #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */
+ #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */
+ #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */
+ #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */
+ #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */
+ #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */
+ #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */
+ #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */
+ #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */
+ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */
+/* ======================================================== GTICASR ======================================================== */
+ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */
+ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */
+ #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */
+ #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */
+ #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */
+ #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */
+ #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */
+ #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */
+ #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */
+ #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */
+ #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */
+ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */
+/* ======================================================== GTICBSR ======================================================== */
+ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */
+ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */
+ #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */
+ #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */
+ #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */
+ #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */
+ #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */
+ #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */
+ #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */
+ #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */
+ #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */
+ #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */
+/* ========================================================= GTCR ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */
+ #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */
+ #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */
+ #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */
+ #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */
+ #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */
+ #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */
+ #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */
+ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */
+ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */
+/* ======================================================= GTUDDTYC ======================================================== */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */
+ #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */
+ #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */
+ #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */
+ #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */
+ #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */
+ #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */
+/* ========================================================= GTIOR ========================================================= */
+ #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */
+ #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */
+ #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */
+ #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */
+ #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */
+ #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */
+ #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */
+ #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */
+ #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */
+ #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */
+ #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */
+ #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */
+ #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */
+ #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */
+ #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */
+ #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */
+ #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */
+ #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */
+ #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */
+ #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */
+/* ======================================================== GTINTAD ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */
+ #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */
+ #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */
+ #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */
+ #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */
+ #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */
+ #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */
+ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */
+/* ========================================================= GTST ========================================================== */
+ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */
+ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */
+ #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */
+ #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */
+ #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */
+ #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */
+ #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */
+ #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */
+ #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */
+ #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */
+ #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */
+ #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */
+ #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */
+ #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */
+ #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */
+ #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */
+ #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */
+ #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */
+ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */
+ #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */
+/* ========================================================= GTBER ========================================================= */
+ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */
+ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */
+ #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */
+ #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */
+ #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */
+ #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */
+ #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */
+ #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */
+ #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */
+ #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */
+ #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */
+ #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */
+ #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */
+ #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */
+/* ========================================================= GTITC ========================================================= */
+ #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */
+ #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */
+ #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */
+ #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */
+ #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */
+ #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */
+ #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */
+ #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */
+ #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */
+ #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */
+ #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */
+/* ========================================================= GTCNT ========================================================= */
+ #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */
+ #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTCCR ========================================================= */
+ #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */
+ #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTPR ========================================================== */
+ #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */
+ #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTPBR ========================================================= */
+ #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */
+ #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== GTPDBR ========================================================= */
+ #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */
+ #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== GTADTRA ======================================================== */
+ #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */
+ #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== GTADTRB ======================================================== */
+ #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */
+ #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= GTADTBRA ======================================================== */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= GTADTBRB ======================================================== */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= GTADTDBRA ======================================================= */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= GTADTDBRB ======================================================= */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== GTDTCR ========================================================= */
+ #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */
+ #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */
+ #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */
+ #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */
+ #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */
+/* ========================================================= GTDVU ========================================================= */
+ #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
+ #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTDVD ========================================================= */
+ #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */
+ #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTDBU ========================================================= */
+ #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
+ #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTDBD ========================================================= */
+ #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */
+ #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= GTSOS ========================================================= */
+ #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */
+ #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */
+/* ======================================================== GTSOTR ========================================================= */
+ #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */
+ #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */
+/* ======================================================== GTADSMR ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */
+/* ======================================================== GTEITC ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */
+ #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */
+ #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */
+ #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */
+ #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */
+ #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */
+ #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */
+ #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */
+/* ======================================================= GTEITLI1 ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */
+ #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */
+ #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */
+ #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */
+ #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */
+ #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */
+ #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */
+ #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */
+ #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */
+/* ======================================================= GTEITLI2 ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */
+/* ======================================================== GTEITLB ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */
+/* ======================================================== GTICLF ========================================================= */
+ #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */
+ #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */
+ #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */
+ #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */
+ #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */
+ #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */
+ #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */
+/* ========================================================= GTPC ========================================================== */
+ #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */
+ #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */
+ #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */
+ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */
+/* ======================================================== GTSECSR ======================================================== */
+ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */
+ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */
+ #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */
+ #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */
+ #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */
+ #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */
+ #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */
+ #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */
+ #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */
+ #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */
+ #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */
+/* ======================================================== GTSECR ========================================================= */
+ #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */
+ #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */
+ #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */
+ #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */
+ #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */
+ #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */
+ #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */
+ #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */
+ #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */
+ #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */
+ #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */
+ #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */
+ #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */
+/* ======================================================== GTBER2 ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */
+ #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */
+ #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */
+ #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */
+ #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */
+ #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */
+ #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */
+ #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */
+ #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */
+ #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */
+ #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */
+ #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */
+ #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */
+ #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */
+ #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */
+ #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */
+ #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */
+ #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */
+ #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */
+ #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */
+ #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */
+/* ======================================================== GTOLBR ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */
+/* ======================================================== GTICCR ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */
+ #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */
+ #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */
+ #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */
+ #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */
+ #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */
+ #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */
+ #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */
+ #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */
+ #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */
+ #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */
+ #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */
+ #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */
+ #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */
+ #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */
+ #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */
+ #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */
+ #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */
+ #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */
+ #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */
+ #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */
+ #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */
+ #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT_OPS ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= OPSCR ========================================================= */
+ #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
+ #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
+ #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
+ #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */
+ #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */
+ #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
+ #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */
+ #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */
+ #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */
+ #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */
+ #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */
+ #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */
+ #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */
+ #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */
+ #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */
+ #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */
+ #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */
+ #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */
+ #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */
+ #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */
+ #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_GPT_POEG0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= POEGG ========================================================= */
+ #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
+ #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
+ #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
+ #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */
+ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */
+ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */
+ #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */
+ #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */
+ #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */
+ #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */
+ #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */
+ #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */
+ #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */
+ #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */
+ #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_ICU ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= IRQCR ========================================================= */
+ #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */
+ #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */
+ #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */
+ #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */
+ #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */
+/* ========================================================= NMISR ========================================================= */
+ #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */
+ #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */
+ #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */
+ #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */
+ #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */
+ #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */
+ #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */
+ #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */
+ #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */
+ #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */
+ #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */
+ #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */
+ #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */
+ #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */
+ #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */
+/* ========================================================= NMIER ========================================================= */
+ #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */
+ #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */
+ #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */
+ #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */
+ #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */
+ #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */
+ #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */
+ #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */
+ #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */
+ #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */
+ #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */
+ #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */
+ #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */
+ #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */
+ #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */
+/* ======================================================== NMICLR ========================================================= */
+ #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */
+ #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */
+ #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */
+ #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */
+ #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */
+ #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */
+ #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */
+ #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */
+ #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */
+ #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */
+ #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */
+ #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */
+ #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */
+ #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */
+ #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */
+/* ========================================================= NMICR ========================================================= */
+ #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */
+ #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */
+ #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */
+ #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */
+ #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */
+/* ========================================================= IELSR ========================================================= */
+ #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */
+ #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */
+ #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
+ #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
+ #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */
+ #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */
+/* ========================================================= DELSR ========================================================= */
+ #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
+ #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
+ #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */
+ #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */
+/* ======================================================== SELSR0 ========================================================= */
+ #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */
+ #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */
+/* ========================================================= WUPEN ========================================================= */
+ #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */
+ #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */
+ #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */
+ #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */
+ #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */
+ #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */
+ #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */
+ #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */
+ #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */
+ #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */
+/* ======================================================== WUPEN1 ========================================================= */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */
+/* ========================================================= IELEN ========================================================= */
+ #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */
+ #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */
+ #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_IIC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ICCR1 ========================================================= */
+ #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */
+ #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */
+ #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */
+ #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */
+ #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */
+ #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */
+ #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */
+ #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */
+ #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */
+/* ========================================================= ICCR2 ========================================================= */
+ #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */
+ #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */
+ #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */
+ #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */
+ #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */
+ #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */
+ #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */
+/* ========================================================= ICMR1 ========================================================= */
+ #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */
+ #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */
+ #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */
+ #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */
+ #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */
+ #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */
+/* ========================================================= ICMR2 ========================================================= */
+ #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */
+ #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */
+ #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */
+ #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */
+ #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */
+ #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */
+ #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */
+/* ========================================================= ICMR3 ========================================================= */
+ #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */
+ #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */
+ #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */
+ #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */
+ #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */
+ #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */
+ #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */
+ #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */
+/* ========================================================= ICFER ========================================================= */
+ #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */
+ #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */
+ #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */
+ #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */
+ #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */
+ #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */
+ #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */
+ #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */
+ #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */
+/* ========================================================= ICSER ========================================================= */
+ #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */
+ #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */
+ #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */
+ #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */
+ #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */
+ #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */
+ #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */
+/* ========================================================= ICIER ========================================================= */
+ #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */
+ #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */
+ #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */
+ #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */
+ #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */
+ #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */
+ #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */
+ #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */
+ #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */
+/* ========================================================= ICSR1 ========================================================= */
+ #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */
+ #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */
+ #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */
+ #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */
+ #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */
+ #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */
+ #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */
+/* ========================================================= ICSR2 ========================================================= */
+ #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
+ #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */
+ #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */
+ #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */
+ #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */
+ #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */
+ #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */
+ #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */
+ #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */
+/* ========================================================= ICBRL ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */
+ #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */
+/* ========================================================= ICBRH ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */
+ #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */
+/* ========================================================= ICDRT ========================================================= */
+ #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */
+ #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */
+/* ========================================================= ICDRR ========================================================= */
+ #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */
+ #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */
+/* ========================================================= ICWUR ========================================================= */
+ #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */
+ #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */
+ #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */
+ #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */
+ #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */
+ #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */
+/* ======================================================== ICWUR2 ========================================================= */
+ #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */
+ #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */
+ #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */
+ #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */
+ #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_IWDT ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== IWDTRR ========================================================= */
+ #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */
+ #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */
+/* ======================================================== IWDTCR ========================================================= */
+ #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */
+ #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */
+ #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */
+ #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */
+ #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */
+ #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */
+ #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */
+ #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */
+/* ======================================================== IWDTSR ========================================================= */
+ #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
+ #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
+ #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
+ #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
+ #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
+ #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
+/* ======================================================== IWDTRCR ======================================================== */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */
+/* ======================================================= IWDTCSTPR ======================================================= */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_I3C0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= PRTS ========================================================== */
+ #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
+ #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */
+/* ========================================================= CECTL ========================================================= */
+ #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */
+ #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */
+/* ========================================================= BCTL ========================================================== */
+ #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */
+ #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */
+ #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */
+ #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */
+ #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */
+ #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */
+ #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */
+/* ======================================================== MSDVAD ========================================================= */
+ #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */
+ #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */
+ #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */
+/* ======================================================== RSTCTL ========================================================= */
+ #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */
+ #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */
+ #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */
+ #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */
+ #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */
+ #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */
+ #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */
+ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */
+ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */
+/* ========================================================= PRSST ========================================================= */
+ #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */
+ #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */
+ #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */
+ #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */
+/* ========================================================= INST ========================================================== */
+ #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */
+ #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */
+/* ========================================================= INSTE ========================================================= */
+ #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */
+ #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */
+/* ========================================================= INIE ========================================================== */
+ #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */
+ #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */
+/* ======================================================== INSTFC ========================================================= */
+ #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */
+ #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */
+/* ========================================================= DVCT ========================================================== */
+ #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */
+ #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */
+/* ======================================================== IBINCTL ======================================================== */
+ #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */
+ #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */
+ #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */
+/* ========================================================= BFCTL ========================================================= */
+ #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */
+ #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */
+ #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */
+ #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */
+ #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */
+ #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */
+ #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */
+ #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */
+/* ========================================================= SVCTL ========================================================= */
+ #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */
+ #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */
+ #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */
+ #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */
+ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */
+ #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */
+/* ======================================================= REFCKCTL ======================================================== */
+ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */
+ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */
+/* ========================================================= STDBR ========================================================= */
+ #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */
+ #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */
+ #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */
+ #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */
+ #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */
+ #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */
+/* ========================================================= EXTBR ========================================================= */
+ #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */
+ #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */
+ #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */
+ #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */
+ #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */
+/* ======================================================== BFRECDT ======================================================== */
+ #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */
+ #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */
+/* ======================================================== BAVLCDT ======================================================== */
+ #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */
+ #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */
+/* ======================================================== BIDLCDT ======================================================== */
+ #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */
+ #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== OUTCTL ========================================================= */
+ #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */
+ #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */
+ #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */
+ #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */
+ #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */
+ #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */
+ #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */
+ #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */
+/* ========================================================= INCTL ========================================================= */
+ #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */
+ #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */
+ #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */
+ #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */
+/* ======================================================== TMOCTL ========================================================= */
+ #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */
+ #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */
+ #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */
+ #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */
+ #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */
+ #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */
+/* ========================================================= WUCTL ========================================================= */
+ #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */
+ #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */
+ #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */
+ #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */
+ #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */
+/* ======================================================== ACKCTL ========================================================= */
+ #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */
+ #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */
+ #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */
+ #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */
+ #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */
+ #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */
+/* ======================================================= SCSTRCTL ======================================================== */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */
+ #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */
+/* ======================================================= SCSTLCTL ======================================================== */
+ #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */
+ #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */
+ #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */
+ #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */
+ #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */
+ #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */
+/* ======================================================== SVTDLG0 ======================================================== */
+ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */
+ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */
+/* ======================================================== CNDCTL ========================================================= */
+ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */
+ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */
+ #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */
+ #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */
+/* ======================================================== NCMDQP ========================================================= */
+/* ======================================================== NRSPQP ========================================================= */
+/* ======================================================== NTDTBP0 ======================================================== */
+/* ======================================================== NIBIQP ========================================================= */
+/* ========================================================= NRSQP ========================================================= */
+/* ======================================================== NQTHCTL ======================================================== */
+ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */
+ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */
+ #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */
+ #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */
+/* ======================================================= NTBTHCTL0 ======================================================= */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */
+/* ======================================================= NRQTHCTL ======================================================== */
+ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */
+ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */
+/* ========================================================== BST ========================================================== */
+ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */
+ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */
+ #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */
+ #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */
+ #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */
+ #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */
+ #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */
+ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */
+/* ========================================================= BSTE ========================================================== */
+ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */
+ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */
+ #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */
+ #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */
+ #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */
+ #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */
+ #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */
+ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */
+/* ========================================================== BIE ========================================================== */
+ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */
+ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */
+ #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */
+ #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */
+ #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */
+ #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */
+ #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */
+ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */
+/* ========================================================= BSTFC ========================================================= */
+ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */
+ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */
+ #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */
+ #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */
+ #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */
+ #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */
+ #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */
+ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */
+/* ========================================================= NTST ========================================================== */
+ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */
+ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */
+ #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */
+ #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */
+ #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */
+ #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */
+ #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */
+ #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */
+ #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */
+/* ========================================================= NTSTE ========================================================= */
+ #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */
+ #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */
+ #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */
+ #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */
+ #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */
+ #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */
+ #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */
+ #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */
+ #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */
+/* ========================================================= NTIE ========================================================== */
+ #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */
+ #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */
+ #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */
+ #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */
+ #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */
+ #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */
+ #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */
+ #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */
+ #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */
+/* ======================================================== NTSTFC ========================================================= */
+ #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */
+ #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */
+ #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */
+ #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */
+ #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */
+ #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */
+ #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */
+ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */
+/* ========================================================= BCST ========================================================== */
+ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */
+ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */
+ #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */
+ #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */
+/* ========================================================= SVST ========================================================== */
+ #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */
+ #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */
+ #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */
+ #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */
+ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */
+ #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */
+/* ========================================================= WUST ========================================================== */
+ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */
+ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */
+/* ======================================================== DATBAS0 ======================================================== */
+ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+/* ======================================================== DATBAS1 ======================================================== */
+ #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+/* ======================================================== DATBAS2 ======================================================== */
+ #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+/* ======================================================== DATBAS3 ======================================================== */
+ #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+/* ======================================================= EXDATBAS ======================================================== */
+ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */
+ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */
+ #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */
+ #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */
+ #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */
+/* ======================================================= SDATBAS0 ======================================================== */
+ #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+/* ======================================================= SDATBAS1 ======================================================== */
+ #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+/* ======================================================= SDATBAS2 ======================================================== */
+ #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+/* ======================================================== MSDCT0 ========================================================= */
+ #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+/* ======================================================== MSDCT1 ========================================================= */
+ #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+/* ======================================================== MSDCT2 ========================================================= */
+ #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+/* ======================================================== MSDCT3 ========================================================= */
+ #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+/* ========================================================= SVDCT ========================================================= */
+ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
+ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
+ #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */
+ #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */
+ #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */
+ #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */
+ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */
+ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */
+/* ======================================================= SDCTPIDL ======================================================== */
+/* ======================================================= SDCTPIDH ======================================================== */
+/* ======================================================== SVDVAD0 ======================================================== */
+ #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */
+ #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */
+ #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */
+ #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */
+ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */
+/* ======================================================== CSECMD ========================================================= */
+ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */
+ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */
+ #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */
+ #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */
+/* ======================================================== CEACTST ======================================================== */
+ #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */
+ #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */
+/* ========================================================= CMWLG ========================================================= */
+ #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */
+ #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMRLG ========================================================= */
+ #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */
+ #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */
+ #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */
+/* ======================================================== CETSTMD ======================================================== */
+ #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */
+ #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */
+/* ======================================================== CGDVST ========================================================= */
+ #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */
+ #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */
+ #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */
+ #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */
+ #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */
+ #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */
+ #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */
+/* ======================================================== CMDSPW ========================================================= */
+ #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */
+ #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */
+/* ======================================================== CMDSPR ========================================================= */
+ #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */
+ #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */
+ #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */
+ #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */
+/* ======================================================== CMDSPT ========================================================= */
+ #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */
+ #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */
+ #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */
+ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */
+/* ========================================================= CETSM ========================================================= */
+ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */
+ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */
+ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */
+/* ======================================================== BITCNT ========================================================= */
+ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */
+ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */
+ #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */
+ #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */
+/* ======================================================== NQSTLV ========================================================= */
+ #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */
+ #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */
+ #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */
+ #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */
+ #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */
+/* ======================================================= NDBSTLV0 ======================================================== */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */
+ #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */
+/* ======================================================= NRSQSTLV ======================================================== */
+ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */
+ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */
+/* ======================================================== PRSTDBG ======================================================== */
+ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */
+ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */
+ #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */
+ #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */
+ #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */
+/* ======================================================= MSERRCNT ======================================================== */
+ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */
+ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_MMPU ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_SMPU ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SMPUCTL ======================================================== */
+ #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+ #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */
+ #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
+ #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_MPU_SPMON ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_MSTP ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== MSTPCRA ======================================================== */
+ #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */
+ #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */
+/* ======================================================== MSTPCRB ======================================================== */
+ #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */
+ #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */
+/* ======================================================== MSTPCRC ======================================================== */
+ #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */
+ #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */
+/* ======================================================== MSTPCRD ======================================================== */
+ #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */
+ #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */
+/* ======================================================== MSTPCRE ======================================================== */
+ #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */
+ #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_PORT0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PCNTR1 ========================================================= */
+ #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */
+ #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */
+ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */
+ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */
+/* ========================================================= PODR ========================================================== */
+ #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */
+ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
+/* ========================================================== PDR ========================================================== */
+ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */
+ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */
+/* ======================================================== PCNTR2 ========================================================= */
+ #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */
+ #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */
+ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
+ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */
+/* ========================================================= EIDR ========================================================== */
+ #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */
+ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */
+/* ========================================================= PIDR ========================================================== */
+ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
+ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */
+/* ======================================================== PCNTR3 ========================================================= */
+ #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */
+ #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */
+ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */
+ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */
+/* ========================================================= PORR ========================================================== */
+ #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */
+ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */
+/* ========================================================= POSR ========================================================== */
+ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */
+ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */
+/* ======================================================== PCNTR4 ========================================================= */
+ #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */
+ #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */
+ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
+ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */
+/* ========================================================= EORR ========================================================== */
+ #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */
+ #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */
+/* ========================================================= EOSR ========================================================== */
+ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
+ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_PFS ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_PMISC ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PFENET ========================================================= */
+ #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */
+ #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */
+ #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */
+ #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= PWPR ========================================================== */
+ #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
+ #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
+ #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
+ #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
+/* ========================================================= PWPRS ========================================================= */
+ #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
+ #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
+ #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
+ #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_QSPI ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SFMSMD ========================================================= */
+ #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */
+ #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */
+ #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */
+ #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */
+ #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */
+ #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */
+ #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */
+ #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */
+ #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */
+ #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */
+ #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */
+/* ======================================================== SFMSSC ========================================================= */
+ #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */
+ #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */
+ #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */
+ #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */
+/* ======================================================== SFMSKC ========================================================= */
+ #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */
+ #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */
+ #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */
+/* ======================================================== SFMSST ========================================================= */
+ #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */
+ #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */
+ #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */
+ #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */
+/* ======================================================== SFMCOM ========================================================= */
+ #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */
+ #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */
+/* ======================================================== SFMCMD ========================================================= */
+ #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */
+ #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */
+/* ======================================================== SFMCST ========================================================= */
+ #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */
+ #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */
+ #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== SFMSIC ========================================================= */
+ #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */
+ #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */
+/* ======================================================== SFMSAC ========================================================= */
+ #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */
+ #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */
+ #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */
+/* ======================================================== SFMSDC ========================================================= */
+ #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */
+ #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */
+ #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */
+ #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */
+ #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */
+ #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */
+/* ======================================================== SFMSPC ========================================================= */
+ #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */
+ #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */
+ #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */
+ #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */
+/* ======================================================== SFMPMD ========================================================= */
+ #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */
+ #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */
+/* ======================================================== SFMCNT1 ======================================================== */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */
+
+/* =========================================================================================================================== */
+/* ================ R_RTC ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== R64CNT ========================================================= */
+ #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */
+ #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */
+ #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */
+ #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */
+ #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */
+ #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */
+ #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */
+ #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */
+ #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */
+/* ========================================================= BCNT0 ========================================================= */
+ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */
+ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */
+/* ======================================================== RSECCNT ======================================================== */
+ #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
+ #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
+ #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT1 ========================================================= */
+ #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */
+ #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */
+/* ======================================================== RMINCNT ======================================================== */
+ #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
+ #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
+ #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT2 ========================================================= */
+ #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */
+ #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */
+/* ======================================================== RHRCNT ========================================================= */
+ #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */
+ #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
+ #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
+ #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
+/* ========================================================= BCNT3 ========================================================= */
+ #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */
+ #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */
+/* ======================================================== RWKCNT ========================================================= */
+ #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
+ #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
+/* ======================================================== RDAYCNT ======================================================== */
+ #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
+ #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
+ #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== RMONCNT ======================================================== */
+ #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
+ #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
+ #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
+ #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== RYRCNT ========================================================= */
+ #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
+ #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
+ #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
+ #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== BCNT0AR ======================================================== */
+ #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */
+ #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */
+/* ======================================================== RSECAR ========================================================= */
+ #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
+ #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
+ #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== BCNT1AR ======================================================== */
+ #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */
+ #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */
+/* ======================================================== RMINAR ========================================================= */
+ #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
+ #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
+ #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
+ #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== BCNT2AR ======================================================== */
+ #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */
+ #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */
+/* ========================================================= RHRAR ========================================================= */
+ #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */
+ #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
+ #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
+ #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== BCNT3AR ======================================================== */
+ #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */
+ #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */
+/* ========================================================= RWKAR ========================================================= */
+ #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
+ #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
+/* ======================================================= BCNT0AER ======================================================== */
+ #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
+ #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
+/* ======================================================== RDAYAR ========================================================= */
+ #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
+ #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
+ #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
+ #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
+/* ======================================================= BCNT1AER ======================================================== */
+ #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
+ #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
+/* ======================================================== RMONAR ========================================================= */
+ #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+ #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
+ #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
+ #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
+ #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
+/* ======================================================= BCNT2AER ======================================================== */
+ #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
+ #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
+/* ========================================================= RYRAR ========================================================= */
+ #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
+ #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
+ #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
+ #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
+/* ======================================================= BCNT3AER ======================================================== */
+ #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
+ #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
+/* ======================================================== RYRAREN ======================================================== */
+ #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */
+ #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
+/* ========================================================= RCR1 ========================================================== */
+ #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */
+ #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */
+ #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */
+ #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */
+ #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */
+ #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */
+ #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */
+/* ========================================================= RCR2 ========================================================== */
+ #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */
+ #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */
+ #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */
+ #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */
+ #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */
+ #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */
+ #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */
+ #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */
+ #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= RCR4 ========================================================== */
+ #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */
+ #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */
+ #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */
+ #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */
+/* ========================================================= RFRH ========================================================== */
+ #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */
+ #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */
+/* ========================================================= RFRL ========================================================== */
+ #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */
+ #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */
+/* ========================================================= RADJ ========================================================== */
+ #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */
+ #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */
+ #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */
+ #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */
+
+/* =========================================================================================================================== */
+/* ================ R_SCI0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SMR ========================================================== */
+ #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */
+ #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */
+ #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */
+ #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */
+ #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */
+ #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */
+ #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */
+ #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
+/* ======================================================= SMR_SMCI ======================================================== */
+ #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */
+ #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */
+ #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */
+ #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */
+ #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */
+ #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */
+ #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */
+ #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
+/* ========================================================== BRR ========================================================== */
+ #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */
+ #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */
+/* ========================================================== SCR ========================================================== */
+ #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */
+ #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */
+ #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */
+ #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */
+ #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
+ #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
+ #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */
+ #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
+/* ======================================================= SCR_SMCI ======================================================== */
+ #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */
+ #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */
+ #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */
+ #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */
+ #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
+ #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
+ #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */
+ #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
+/* ========================================================== TDR ========================================================== */
+ #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */
+ #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */
+/* ========================================================== SSR ========================================================== */
+ #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
+ #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
+ #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */
+ #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */
+ #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */
+ #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */
+ #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */
+ #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
+ #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
+/* ======================================================= SSR_FIFO ======================================================== */
+ #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */
+ #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */
+ #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */
+ #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */
+ #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */
+ #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */
+ #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */
+ #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
+/* ======================================================= SSR_SMCI ======================================================== */
+ #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
+ #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
+ #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */
+ #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */
+ #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */
+ #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */
+ #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */
+ #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
+ #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
+/* ========================================================== RDR ========================================================== */
+ #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */
+ #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */
+/* ========================================================= SCMR ========================================================== */
+ #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */
+ #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */
+ #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */
+ #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */
+ #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */
+ #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */
+/* ========================================================= SEMR ========================================================== */
+ #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */
+ #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */
+ #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */
+ #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */
+ #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */
+ #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */
+ #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */
+ #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */
+ #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */
+/* ========================================================= SNFR ========================================================== */
+ #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */
+ #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */
+/* ========================================================= SIMR1 ========================================================= */
+ #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */
+ #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */
+ #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */
+ #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */
+/* ========================================================= SIMR2 ========================================================= */
+ #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */
+ #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */
+ #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */
+ #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
+/* ========================================================= SIMR3 ========================================================= */
+ #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */
+ #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
+ #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */
+ #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
+ #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
+ #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */
+ #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */
+ #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
+/* ========================================================= SISR ========================================================== */
+ #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
+ #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
+/* ========================================================= SPMR ========================================================== */
+ #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */
+ #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */
+ #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */
+ #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */
+ #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */
+ #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */
+ #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */
+ #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */
+/* ========================================================= TDRHL ========================================================= */
+ #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */
+ #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */
+/* ======================================================== FTDRHL ========================================================= */
+ #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
+ #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
+ #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
+/* ========================================================= FTDRH ========================================================= */
+ #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */
+ #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */
+ #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */
+/* ========================================================= FTDRL ========================================================= */
+ #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */
+ #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */
+/* ========================================================= RDRHL ========================================================= */
+ #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */
+ #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */
+/* ======================================================== FRDRHL ========================================================= */
+ #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */
+ #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */
+ #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */
+ #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */
+ #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */
+ #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */
+ #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+ #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
+/* ========================================================= FRDRH ========================================================= */
+ #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */
+ #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */
+ #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */
+ #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */
+ #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */
+ #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */
+ #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */
+ #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */
+/* ========================================================= FRDRL ========================================================= */
+ #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */
+ #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */
+/* ========================================================= MDDR ========================================================== */
+ #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */
+ #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */
+/* ========================================================= DCCR ========================================================== */
+ #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */
+ #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */
+ #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */
+ #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */
+ #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */
+ #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */
+ #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */
+ #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */
+/* ========================================================== FCR ========================================================== */
+ #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */
+ #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */
+ #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */
+ #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */
+ #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */
+ #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */
+ #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */
+ #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */
+ #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */
+ #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+ #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */
+ #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */
+/* ========================================================== FDR ========================================================== */
+ #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */
+ #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */
+ #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */
+ #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */
+/* ========================================================== LSR ========================================================== */
+ #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */
+ #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */
+ #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */
+ #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */
+ #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */
+ #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+ #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+ #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
+/* ========================================================= SPTR ========================================================== */
+ #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */
+ #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */
+ #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */
+ #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */
+ #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */
+ #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */
+ #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */
+ #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */
+/* ========================================================= ACTR ========================================================== */
+ #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */
+ #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */
+ #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */
+ #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */
+ #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */
+ #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */
+ #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */
+/* ========================================================= ESMER ========================================================= */
+ #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */
+ #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */
+/* ========================================================== CR0 ========================================================== */
+ #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */
+ #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */
+ #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */
+ #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+ #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */
+ #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */
+ #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */
+ #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */
+ #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */
+ #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */
+ #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */
+/* ========================================================== CR2 ========================================================== */
+ #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */
+ #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */
+ #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */
+ #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */
+ #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */
+ #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */
+/* ========================================================== CR3 ========================================================== */
+ #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */
+ #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */
+/* ========================================================== PCR ========================================================== */
+ #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */
+ #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */
+ #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */
+ #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */
+ #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
+/* ========================================================== ICR ========================================================== */
+ #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */
+ #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */
+ #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */
+ #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */
+ #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */
+ #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */
+ #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+ #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */
+ #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */
+ #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */
+ #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */
+ #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */
+ #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */
+ #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */
+/* ========================================================= STCR ========================================================== */
+ #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */
+ #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */
+ #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */
+ #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */
+ #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */
+ #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */
+ #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */
+ #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */
+/* ========================================================= CF0DR ========================================================= */
+/* ========================================================= CF0CR ========================================================= */
+ #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */
+ #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */
+ #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */
+ #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */
+ #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */
+ #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */
+ #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */
+ #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */
+ #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */
+/* ========================================================= CF0RR ========================================================= */
+/* ======================================================== PCF1DR ========================================================= */
+/* ======================================================== SCF1DR ========================================================= */
+/* ========================================================= CF1CR ========================================================= */
+ #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */
+ #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */
+ #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */
+ #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */
+ #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */
+ #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */
+ #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */
+ #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */
+ #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */
+ #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */
+/* ========================================================= CF1RR ========================================================= */
+/* ========================================================== TCR ========================================================== */
+ #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */
+ #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
+/* ========================================================== TMR ========================================================== */
+ #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */
+ #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */
+ #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */
+ #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */
+ #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
+ #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */
+/* ========================================================= TPRE ========================================================== */
+/* ========================================================= TCNT ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_SDHI0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SD_CMD ========================================================= */
+ #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */
+ #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */
+ #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */
+ #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */
+ #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */
+ #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */
+ #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */
+ #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */
+ #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */
+ #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */
+ #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */
+/* ======================================================== SD_ARG ========================================================= */
+ #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */
+ #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SD_ARG1 ======================================================== */
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */
+/* ======================================================== SD_STOP ======================================================== */
+ #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */
+ #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */
+ #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */
+/* ======================================================= SD_SECCNT ======================================================= */
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= SD_RSP10 ======================================================== */
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SD_RSP1 ======================================================== */
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */
+/* ======================================================= SD_RSP32 ======================================================== */
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SD_RSP3 ======================================================== */
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */
+/* ======================================================= SD_RSP54 ======================================================== */
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SD_RSP5 ======================================================== */
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */
+/* ======================================================= SD_RSP76 ======================================================== */
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */
+/* ======================================================== SD_RSP7 ======================================================== */
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */
+/* ======================================================= SD_INFO1 ======================================================== */
+ #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */
+ #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */
+ #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */
+ #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */
+ #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */
+ #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */
+ #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */
+ #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */
+ #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */
+ #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */
+/* ======================================================= SD_INFO2 ======================================================== */
+ #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */
+ #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */
+ #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */
+ #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */
+ #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */
+ #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */
+ #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */
+ #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */
+ #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */
+ #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */
+ #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */
+ #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */
+ #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */
+/* ===================================================== SD_INFO1_MASK ===================================================== */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */
+/* ===================================================== SD_INFO2_MASK ===================================================== */
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */
+/* ====================================================== SD_CLK_CTRL ====================================================== */
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */
+/* ======================================================== SD_SIZE ======================================================== */
+ #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+ #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */
+/* ======================================================= SD_OPTION ======================================================= */
+ #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */
+ #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */
+ #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */
+ #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
+ #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */
+/* ====================================================== SD_ERR_STS1 ====================================================== */
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */
+/* ====================================================== SD_ERR_STS2 ====================================================== */
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */
+/* ======================================================== SD_BUF0 ======================================================== */
+ #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */
+ #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= SDIO_MODE ======================================================= */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */
+ #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */
+ #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */
+/* ====================================================== SDIO_INFO1 ======================================================= */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== SDIO_INFO1_MASK ==================================================== */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */
+/* ======================================================= SD_DMAEN ======================================================== */
+ #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */
+ #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+/* ======================================================= SOFT_RST ======================================================== */
+ #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */
+ #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */
+/* ======================================================= SDIF_MODE ======================================================= */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */
+/* ======================================================= EXT_SWAP ======================================================== */
+ #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */
+ #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */
+ #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */
+ #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_SPI0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SPCR ========================================================== */
+ #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */
+ #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */
+ #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */
+ #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */
+ #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */
+ #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */
+ #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */
+ #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */
+ #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */
+/* ========================================================= SSLP ========================================================== */
+ #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
+ #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
+ #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
+ #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
+ #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */
+ #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */
+ #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */
+ #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */
+ #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */
+/* ========================================================= SPPCR ========================================================= */
+ #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */
+ #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */
+ #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */
+ #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */
+ #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */
+/* ========================================================= SPSR ========================================================== */
+ #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */
+ #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */
+ #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */
+ #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */
+ #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */
+ #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */
+ #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */
+ #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */
+ #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */
+/* ========================================================= SPDR ========================================================== */
+/* ======================================================== SPDR_HA ======================================================== */
+/* ======================================================== SPDR_BY ======================================================== */
+/* ========================================================= SPSCR ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */
+ #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
+/* ========================================================= SPBR ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */
+ #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */
+/* ========================================================= SPDCR ========================================================= */
+ #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */
+ #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */
+ #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */
+ #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */
+ #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */
+ #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */
+ #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */
+/* ========================================================= SPCKD ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
+ #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
+/* ========================================================= SSLND ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */
+ #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
+/* ========================================================= SPND ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */
+ #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
+/* ========================================================= SPCR2 ========================================================= */
+ #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */
+ #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */
+ #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */
+ #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */
+ #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */
+ #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */
+ #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */
+/* ========================================================= SPCMD ========================================================= */
+ #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */
+ #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */
+ #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */
+ #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+ #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+/* ======================================================== SPDCR2 ========================================================= */
+ #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
+ #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */
+ #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */
+/* ========================================================= SPSSR ========================================================= */
+ #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */
+ #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */
+ #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */
+ #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */
+/* ========================================================= SPCR3 ========================================================= */
+ #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */
+ #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */
+ #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */
+ #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
+/* ========================================================= SPPR ========================================================== */
+ #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */
+ #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */
+ #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */
+ #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */
+ #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */
+ #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ R_SRAM ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PARIOAD ======================================================== */
+ #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+/* ======================================================= SRAMPRCR ======================================================== */
+ #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
+ #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */
+/* ======================================================= SRAMWTSC ======================================================== */
+/* ======================================================== ECCMODE ======================================================== */
+ #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */
+ #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */
+/* ======================================================== ECC2STS ======================================================== */
+ #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */
+ #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ECC1STSEN ======================================================= */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */
+/* ======================================================== ECC1STS ======================================================== */
+ #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */
+ #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */
+/* ======================================================== ECCPRCR ======================================================== */
+ #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
+ #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */
+/* ======================================================= ECCPRCR2 ======================================================== */
+ #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */
+ #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */
+/* ======================================================== ECCETST ======================================================== */
+ #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */
+ #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */
+/* ======================================================== ECCOAD ========================================================= */
+ #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+/* ======================================================= SRAMPRCR2 ======================================================= */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */
+ #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */
+ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
+
+/* =========================================================================================================================== */
+/* ================ R_BUS_B ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== BUSSCNTFHBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTFLBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTS0BIU ====================================================== */
+ #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTPSBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTPLBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTPHBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTEQBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTEOBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTECBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ====================================================== BUS1ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS2ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS3ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS4ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS1ERRCLR ======================================================= */
+ #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS2ERRCLR ======================================================= */
+ #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS3ERRCLR ======================================================= */
+ #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS4ERRCLR ======================================================= */
+ #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ==================================================== DMACDTCERRSTAT ===================================================== */
+ #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */
+ #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */
+/* ===================================================== DMACDTCERRCLR ===================================================== */
+ #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */
+ #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */
+/* ======================================================== CSRECEN ======================================================== */
+ #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
+ #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
+ #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_SSI0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SSICR ========================================================= */
+ #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */
+ #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */
+ #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */
+ #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */
+ #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */
+ #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */
+ #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */
+ #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */
+ #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */
+ #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */
+ #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */
+ #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */
+ #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */
+ #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */
+ #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */
+ #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */
+ #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */
+ #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */
+ #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */
+ #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */
+ #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */
+ #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */
+ #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */
+ #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */
+ #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */
+/* ========================================================= SSISR ========================================================= */
+ #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */
+ #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */
+ #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */
+ #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */
+ #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */
+ #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */
+ #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */
+ #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */
+ #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */
+ #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */
+ #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */
+ #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */
+ #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */
+/* ======================================================== SSIFCR ========================================================= */
+ #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */
+ #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */
+ #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */
+ #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */
+ #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */
+ #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */
+ #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */
+ #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */
+ #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */
+ #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */
+ #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */
+ #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */
+/* ======================================================== SSIFSR ========================================================= */
+ #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */
+ #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */
+ #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */
+ #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */
+ #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */
+ #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */
+ #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */
+/* ======================================================== SSIFTDR ======================================================== */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= SSIFTDR16 ======================================================= */
+/* ======================================================= SSIFTDR8 ======================================================== */
+/* ======================================================== SSIFRDR ======================================================== */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= SSIFRDR16 ======================================================= */
+/* ======================================================= SSIFRDR8 ======================================================== */
+/* ======================================================== SSIOFR ========================================================= */
+ #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */
+ #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */
+ #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */
+ #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */
+ #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */
+/* ======================================================== SSISCR ========================================================= */
+ #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */
+ #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */
+ #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */
+ #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */
+
+/* =========================================================================================================================== */
+/* ================ R_SYSTEM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SBYCR ========================================================= */
+ #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */
+ #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */
+ #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */
+/* ======================================================== MSTPCRA ======================================================== */
+ #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */
+ #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */
+/* ======================================================= SCKDIVCR ======================================================== */
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */
+/* ======================================================= SCKDIVCR2 ======================================================= */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */
+/* ======================================================== SCKSCR ========================================================= */
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */
+/* ======================================================== PLLCCR ========================================================= */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */
+/* ========================================================= PLLCR ========================================================= */
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== PLLCCR2 ======================================================== */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */
+/* ========================================================= BCKCR ========================================================= */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */
+/* ======================================================== MEMWAIT ======================================================== */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */
+/* ======================================================== MOSCCR ========================================================= */
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== HOCOCR ========================================================= */
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== MOCOCR ========================================================= */
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== FLLCR1 ========================================================= */
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */
+/* ======================================================== FLLCR2 ========================================================= */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */
+/* ========================================================= OSCSF ========================================================= */
+ #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */
+ #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */
+ #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */
+/* ========================================================= CKOCR ========================================================= */
+ #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */
+ #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */
+ #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */
+ #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */
+/* ======================================================== TRCKCR ========================================================= */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */
+ #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */
+/* ======================================================== OSTDCR ========================================================= */
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */
+/* ======================================================== OSTDSR ========================================================= */
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */
+/* ========================================================= LPOPT ========================================================= */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */
+ #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */
+/* ======================================================= SLCDSCKCR ======================================================= */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */
+/* ======================================================== EBCKOCR ======================================================== */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */
+/* ======================================================== SDCKOCR ======================================================== */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */
+/* ======================================================= MOCOUTCR ======================================================== */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */
+/* ======================================================= HOCOUTCR ======================================================== */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */
+/* ========================================================= SNZCR ========================================================= */
+ #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */
+ #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */
+/* ======================================================== SNZEDCR ======================================================== */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */
+/* ======================================================= SNZREQCR ======================================================== */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
+/* ======================================================== FLSTOP ========================================================= */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */
+/* ========================================================= PSMCR ========================================================= */
+ #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */
+ #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */
+/* ========================================================= OPCCR ========================================================= */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */
+ #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */
+/* ======================================================== SOPCCR ========================================================= */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */
+/* ======================================================= MOSCWTCR ======================================================== */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */
+/* ======================================================= HOCOWTCR ======================================================== */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */
+/* ======================================================== RSTSR1 ========================================================= */
+ #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */
+ #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */
+ #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */
+ #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */
+ #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */
+ #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */
+ #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */
+/* ======================================================== STCONR ========================================================= */
+ #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */
+ #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */
+/* ======================================================== LVD1CR1 ======================================================== */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
+/* ======================================================== LVD2CR1 ======================================================== */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
+/* ====================================================== USBCKCR_ALT ====================================================== */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= SDADCCKCR ======================================================= */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */
+/* ======================================================== LVD1SR ========================================================= */
+ #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */
+ #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */
+ #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
+/* ======================================================== LVD2SR ========================================================= */
+ #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */
+ #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */
+ #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
+/* ========================================================= PRCR ========================================================== */
+ #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
+ #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
+ #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
+ #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
+ #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
+ #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIER0 ======================================================== */
+ #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
+ #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIER1 ======================================================== */
+ #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
+ #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIER2 ======================================================== */
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIER3 ======================================================== */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIFR0 ======================================================== */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIFR1 ======================================================== */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIFR2 ======================================================== */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSIFR3 ======================================================== */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */
+/* ======================================================= DPSIEGR0 ======================================================== */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
+/* ======================================================= DPSIEGR1 ======================================================== */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
+/* ======================================================= DPSIEGR2 ======================================================== */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSBYCR ======================================================== */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */
+/* ======================================================== SYOCDCR ======================================================== */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */
+/* ========================================================= MOMCR ========================================================= */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */
+ #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */
+ #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */
+ #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */
+/* ======================================================== RSTSR0 ========================================================= */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */
+ #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */
+/* ======================================================== RSTSR2 ========================================================= */
+ #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */
+ #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */
+/* ======================================================== LVCMPCR ======================================================== */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
+/* ======================================================= LVD1CMPCR ======================================================= */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
+/* ======================================================== LVDLVLR ======================================================== */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
+/* ======================================================= LVD2CMPCR ======================================================= */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
+/* ======================================================== LVD1CR0 ======================================================== */
+ #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
+ #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
+ #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
+ #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
+/* ======================================================== LVD2CR0 ======================================================== */
+ #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
+ #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
+ #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
+ #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTCR1 ========================================================= */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== DCDCCTL ======================================================== */
+ #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */
+ #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */
+ #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */
+/* ======================================================== VCCSEL ========================================================= */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */
+/* ======================================================== LDOSCR ========================================================= */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */
+/* ======================================================= PL2LDOSCR ======================================================= */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */
+/* ======================================================== SOSCCR ========================================================= */
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */
+/* ========================================================= SOMCR ========================================================= */
+ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */
+ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */
+/* ======================================================== LOCOCR ========================================================= */
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */
+/* ======================================================= LOCOUTCR ======================================================== */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */
+/* ======================================================== VBTCR2 ========================================================= */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */
+/* ========================================================= VBTSR ========================================================= */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */
+ #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */
+/* ======================================================= VBTCMPCR ======================================================== */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */
+/* ======================================================= VBTLVDICR ======================================================= */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */
+/* ======================================================= VBTWCTLR ======================================================== */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */
+/* ====================================================== VBTWCH0OTSR ====================================================== */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */
+/* ====================================================== VBTWCH1OTSR ====================================================== */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */
+/* ====================================================== VBTWCH2OTSR ====================================================== */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */
+/* ======================================================= VBTICTLR ======================================================== */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */
+/* ======================================================= VBTOCTLR ======================================================== */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTWTER ======================================================== */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */
+ #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */
+ #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */
+ #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTWEGR ======================================================== */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTWFR ========================================================= */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */
+ #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */
+ #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */
+ #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTBKR ========================================================= */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
+/* ======================================================== FWEPROR ======================================================== */
+ #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */
+ #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */
+/* ======================================================== PLL2CCR ======================================================== */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */
+/* ======================================================== PLL2CR ========================================================= */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */
+/* ====================================================== USBCKDIVCR ======================================================= */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== OCTACKDIVCR ====================================================== */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */
+/* ===================================================== SCISPICKDIVCR ===================================================== */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */
+/* ===================================================== CANFDCKDIVCR ====================================================== */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== GPTCKDIVCR ======================================================= */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */
+/* ===================================================== USB60CKDIVCR ====================================================== */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== CECCKDIVCR ======================================================= */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== I3CCKDIVCR ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== IICCKDIVCR ======================================================= */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */
+/* ======================================================== USBCKCR ======================================================== */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================= OCTACKCR ======================================================== */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */
+/* ====================================================== SCISPICKCR ======================================================= */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================= CANFDCKCR ======================================================= */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== GPTCKCR ======================================================== */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================= USB60CKCR ======================================================= */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== CECCKCR ======================================================== */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== IICCKCR ======================================================== */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== I3CCKCR ======================================================== */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================= SNZREQCR1 ======================================================= */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */
+/* ======================================================= SNZEDCR1 ======================================================== */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */
+/* ======================================================== CGFSAR ========================================================= */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
+/* ======================================================== LPMSAR ========================================================= */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */
+/* ======================================================== LVDSAR ========================================================= */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+/* ======================================================== RSTSAR ========================================================= */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+/* ======================================================== BBFSAR ========================================================= */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */
+/* ======================================================== DPFSAR ========================================================= */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */
+/* ======================================================== DPSWCR ========================================================= */
+ #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */
+ #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */
+/* ====================================================== VBATTMNSELR ====================================================== */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= VBATTMONR ======================================================= */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */
+/* ======================================================== VBTBER ========================================================= */
+ #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */
+ #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_TSN_CAL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= TSCDR ========================================================= */
+ #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */
+ #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */
+
+/* =========================================================================================================================== */
+/* ================ R_TSN_CTRL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= TSCR ========================================================== */
+ #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */
+ #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */
+ #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */
+ #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_USB_FS0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SYSCFG ========================================================= */
+ #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */
+ #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */
+ #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */
+ #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */
+ #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */
+ #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */
+ #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */
+ #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */
+/* ======================================================== BUSWAIT ======================================================== */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */
+/* ======================================================== SYSSTS0 ======================================================== */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */
+ #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */
+ #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */
+ #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */
+/* ======================================================== PLLSTA ========================================================= */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */
+/* ======================================================= DVSTCTR0 ======================================================== */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */
+ #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */
+ #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */
+/* ======================================================= TESTMODE ======================================================== */
+ #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */
+ #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */
+/* ======================================================== CFIFOL ========================================================= */
+/* ======================================================== CFIFOLL ======================================================== */
+/* ========================================================= CFIFO ========================================================= */
+/* ======================================================== CFIFOH ========================================================= */
+/* ======================================================== CFIFOHH ======================================================== */
+/* ======================================================== D0FIFOL ======================================================== */
+/* ======================================================= D0FIFOLL ======================================================== */
+/* ======================================================== D0FIFO ========================================================= */
+/* ======================================================== D0FIFOH ======================================================== */
+/* ======================================================= D0FIFOHH ======================================================== */
+/* ======================================================== D1FIFOL ======================================================== */
+/* ======================================================= D1FIFOLL ======================================================== */
+/* ======================================================== D1FIFO ========================================================= */
+/* ======================================================== D1FIFOH ======================================================== */
+/* ======================================================= D1FIFOHH ======================================================== */
+/* ======================================================= CFIFOSEL ======================================================== */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= CFIFOCTR ======================================================== */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================= D0FIFOSEL ======================================================= */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= D0FIFOCTR ======================================================= */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================= D1FIFOSEL ======================================================= */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= D1FIFOCTR ======================================================= */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================== INTENB0 ======================================================== */
+ #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */
+ #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */
+ #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */
+ #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */
+ #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */
+ #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */
+ #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */
+ #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */
+ #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */
+/* ======================================================== INTENB1 ======================================================== */
+ #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */
+ #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */
+ #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */
+ #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */
+ #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */
+ #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */
+ #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */
+ #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BRDYENB ======================================================== */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */
+/* ======================================================== NRDYENB ======================================================== */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */
+/* ======================================================== BEMPENB ======================================================== */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */
+/* ======================================================== SOFCFG ========================================================= */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */
+ #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */
+ #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */
+/* ======================================================== PHYSET ========================================================= */
+ #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */
+ #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */
+ #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */
+ #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
+ #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */
+ #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */
+ #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */
+ #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */
+/* ======================================================== INTSTS0 ======================================================== */
+ #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */
+ #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */
+ #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */
+ #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */
+ #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */
+ #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */
+ #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */
+ #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */
+ #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */
+ #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
+ #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */
+ #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */
+ #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */
+ #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */
+/* ======================================================== INTSTS1 ======================================================== */
+ #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */
+ #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */
+ #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */
+ #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */
+ #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */
+ #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */
+ #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */
+ #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */
+ #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BRDYSTS ======================================================== */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== NRDYSTS ======================================================== */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== BEMPSTS ======================================================== */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */
+/* ======================================================== FRMNUM ========================================================= */
+ #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */
+ #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */
+ #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */
+ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */
+/* ======================================================== UFRMNUM ======================================================== */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */
+/* ======================================================== USBADDR ======================================================== */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */
+ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */
+ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */
+/* ======================================================== USBREQ ========================================================= */
+ #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
+ #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+/* ======================================================== USBVAL ========================================================= */
+ #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */
+ #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
+/* ======================================================== USBINDX ======================================================== */
+ #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
+ #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
+/* ======================================================== USBLENG ======================================================== */
+ #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */
+ #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
+/* ======================================================== DCPCFG ========================================================= */
+ #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
+ #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+ #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+/* ======================================================== DCPMAXP ======================================================== */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
+ #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */
+/* ======================================================== DCPCTR ========================================================= */
+ #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
+ #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */
+ #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
+ #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
+ #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
+ #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
+ #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */
+ #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */
+ #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
+/* ======================================================== PIPESEL ======================================================== */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== PIPECFG ======================================================== */
+ #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */
+ #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */
+ #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */
+ #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+ #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */
+ #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */
+/* ======================================================= PIPEMAXP ======================================================== */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */
+/* ======================================================= PIPEPERI ======================================================== */
+ #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */
+ #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */
+ #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */
+/* ======================================================= PIPE_CTR ======================================================== */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */
+ #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
+/* ======================================================== DEVADD ========================================================= */
+ #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */
+ #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */
+ #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */
+ #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */
+ #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */
+/* ====================================================== USBBCCTRL0 ======================================================= */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */
+/* ======================================================== UCKSEL ========================================================= */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */
+/* ========================================================= USBMC ========================================================= */
+ #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */
+ #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */
+ #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */
+/* ======================================================== PHYSLEW ======================================================== */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */
+/* ======================================================== LPCTRL ========================================================= */
+ #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */
+ #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */
+/* ========================================================= LPSTS ========================================================= */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */
+/* ======================================================== BCCTRL ========================================================= */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */
+/* ======================================================= PL1CTRL1 ======================================================== */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */
+/* ======================================================= PL1CTRL2 ======================================================== */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */
+/* ======================================================= HL1CTRL1 ======================================================== */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */
+/* ======================================================= HL1CTRL2 ======================================================== */
+ #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */
+ #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */
+/* ======================================================== DPUSR0R ======================================================== */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSR1R ======================================================== */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSR2R ======================================================== */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */
+ #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */
+ #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSRCR ======================================================== */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */
+/* ====================================================== DPUSR0R_FS ======================================================= */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */
+/* ====================================================== DPUSR1R_FS ======================================================= */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_WDT ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= WDTRR ========================================================= */
+ #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */
+ #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */
+/* ========================================================= WDTCR ========================================================= */
+ #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */
+ #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */
+ #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */
+ #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */
+ #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */
+ #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */
+ #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */
+ #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */
+/* ========================================================= WDTSR ========================================================= */
+ #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
+ #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
+ #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
+ #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
+ #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
+ #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
+/* ======================================================== WDTRCR ========================================================= */
+ #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */
+ #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */
+/* ======================================================= WDTCSTPR ======================================================== */
+ #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */
+ #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_TZF ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== TZFOAD ========================================================= */
+ #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+ #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ========================================================= TZFPT ========================================================= */
+ #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
+ #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
+ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ======================================================== TZFSAR ========================================================= */
+ #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */
+ #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_CACHE ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CCACTL ========================================================= */
+ #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */
+ #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */
+/* ======================================================== CCAFCT ========================================================= */
+ #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */
+ #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */
+/* ======================================================== CCALCF ========================================================= */
+ #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */
+ #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */
+/* ======================================================== SCACTL ========================================================= */
+ #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */
+ #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */
+/* ======================================================== SCAFCT ========================================================= */
+ #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */
+ #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */
+/* ======================================================== SCALCF ========================================================= */
+ #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */
+ #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */
+/* ======================================================== CAPOAD ========================================================= */
+ #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
+ #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPRCR ========================================================= */
+ #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */
+ #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */
+ #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
+ #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
+
+/* =========================================================================================================================== */
+/* ================ R_CPSCU ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CSAR ========================================================== */
+ #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */
+ #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */
+ #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */
+ #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */
+/* ======================================================== SRAMSAR ======================================================== */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */
+/* ======================================================= STBRAMSAR ======================================================= */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */
+/* ======================================================== DTCSAR ========================================================= */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */
+/* ======================================================== DMACSAR ======================================================== */
+ #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */
+ #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */
+/* ======================================================== ICUSARA ======================================================== */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */
+/* ======================================================== ICUSARB ======================================================== */
+ #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */
+ #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */
+/* ======================================================== ICUSARC ======================================================== */
+ #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */
+ #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */
+/* ======================================================== ICUSARD ======================================================== */
+ #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */
+ #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== ICUSARE ======================================================== */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */
+/* ======================================================== ICUSARF ======================================================== */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */
+/* ======================================================== ICUSARG ======================================================== */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== ICUSARH ======================================================== */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== ICUSARI ======================================================== */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== BUSSARA ======================================================== */
+ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */
+ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BUSSARB ======================================================== */
+ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */
+ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */
+/* ======================================================= MMPUSARA ======================================================== */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */
+/* ======================================================= MMPUSARB ======================================================== */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */
+/* ======================================================== DMASARA ======================================================== */
+ #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */
+ #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */
+/* ======================================================== CPUDSAR ======================================================== */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */
+/* ======================================================== TEVTRCR ======================================================== */
+ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */
+ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_CEC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CADR ========================================================== */
+ #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */
+ #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */
+ #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */
+ #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */
+ #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */
+ #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */
+ #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */
+ #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */
+ #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */
+ #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */
+ #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */
+ #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */
+ #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */
+ #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */
+ #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */
+ #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */
+ #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */
+/* ======================================================== CECCTL1 ======================================================== */
+ #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */
+ #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */
+ #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */
+ #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */
+ #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */
+ #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */
+ #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */
+ #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */
+ #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */
+/* ========================================================= STATB ========================================================= */
+ #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */
+ #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */
+/* ========================================================= STATL ========================================================= */
+ #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */
+ #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */
+/* ========================================================= LGC0L ========================================================= */
+ #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */
+ #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */
+/* ========================================================= LGC1L ========================================================= */
+ #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */
+ #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */
+/* ========================================================= DATB ========================================================== */
+ #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */
+ #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */
+/* ========================================================= NOMT ========================================================== */
+ #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */
+ #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */
+/* ======================================================== STATLL ========================================================= */
+ #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */
+ #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */
+/* ======================================================== STATLH ========================================================= */
+ #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */
+ #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */
+/* ======================================================== STATBL ========================================================= */
+ #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */
+ #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */
+/* ======================================================== STATBH ========================================================= */
+ #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */
+ #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */
+/* ======================================================== LGC0LL ========================================================= */
+ #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */
+ #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */
+/* ======================================================== LGC0LH ========================================================= */
+ #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */
+ #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */
+/* ======================================================== LGC1LL ========================================================= */
+ #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */
+ #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */
+/* ======================================================== LGC1LH ========================================================= */
+ #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */
+ #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */
+/* ========================================================= DATBL ========================================================= */
+ #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */
+ #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */
+/* ========================================================= DATBH ========================================================= */
+ #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */
+ #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */
+/* ========================================================= NOMP ========================================================== */
+ #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */
+ #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */
+/* ======================================================== CECEXMD ======================================================== */
+ #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */
+ #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */
+ #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= CECEXMON ======================================================== */
+ #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */
+ #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */
+ #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */
+/* ========================================================= CTXD ========================================================== */
+/* ========================================================= CRXD ========================================================== */
+/* ========================================================= CECES ========================================================= */
+ #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */
+ #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */
+ #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */
+ #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */
+ #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */
+ #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */
+ #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */
+ #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */
+/* ========================================================= CECS ========================================================== */
+ #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */
+ #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */
+ #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */
+ #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */
+ #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */
+ #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */
+ #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */
+/* ========================================================= CECFC ========================================================= */
+ #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */
+ #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */
+ #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */
+ #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */
+ #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */
+ #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */
+ #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */
+ #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */
+/* ======================================================== CECCTL0 ======================================================== */
+ #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */
+ #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */
+ #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */
+ #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */
+ #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */
+ #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */
+ #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */
+ #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */
+ #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_OSPI ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== DCR ========================================================== */
+ #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */
+ #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */
+ #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */
+/* ========================================================== DAR ========================================================== */
+ #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */
+ #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */
+ #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */
+ #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */
+ #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */
+/* ========================================================= DCSR ========================================================== */
+ #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */
+ #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */
+ #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */
+ #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */
+ #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */
+ #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */
+ #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */
+ #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */
+ #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */
+ #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */
+ #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */
+/* ========================================================== DSR ========================================================== */
+ #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */
+ #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */
+ #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */
+ #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */
+/* ========================================================= MDTR ========================================================== */
+ #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */
+ #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */
+ #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */
+ #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */
+ #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */
+ #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */
+ #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */
+ #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */
+/* ========================================================= ACTR ========================================================== */
+ #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */
+ #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ACAR ========================================================== */
+ #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */
+ #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DRCSTR ========================================================= */
+ #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */
+ #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */
+ #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */
+ #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */
+ #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */
+ #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */
+ #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */
+ #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */
+ #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */
+ #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */
+ #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */
+ #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */
+ #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */
+ #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */
+/* ======================================================== DWCSTR ========================================================= */
+ #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */
+ #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */
+ #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */
+ #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */
+ #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */
+ #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */
+ #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */
+ #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */
+ #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */
+ #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */
+ #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */
+ #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */
+ #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */
+ #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */
+/* ========================================================= DCSTR ========================================================= */
+ #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */
+ #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */
+ #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */
+ #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */
+ #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */
+/* ========================================================= CDSR ========================================================== */
+ #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */
+ #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */
+ #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */
+ #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */
+ #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */
+ #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */
+ #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */
+ #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */
+ #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */
+ #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */
+ #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */
+ #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */
+ #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */
+ #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */
+/* ========================================================= MDLR ========================================================== */
+ #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */
+ #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */
+ #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */
+ #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */
+ #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */
+/* ========================================================= MRWCR ========================================================= */
+ #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */
+ #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */
+ #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */
+ #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */
+ #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */
+/* ======================================================== MRWCSR ========================================================= */
+ #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */
+ #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */
+ #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */
+ #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */
+ #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */
+ #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */
+ #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */
+ #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */
+ #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */
+ #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */
+ #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */
+ #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */
+ #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */
+ #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */
+ #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */
+ #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */
+/* ========================================================== ESR ========================================================== */
+ #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */
+ #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */
+ #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */
+ #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */
+/* ========================================================= CWNDR ========================================================= */
+ #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */
+ #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CWDR ========================================================== */
+ #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */
+ #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */
+ #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */
+ #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */
+ #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */
+/* ========================================================== CRR ========================================================== */
+ #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */
+ #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */
+ #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */
+ #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */
+ #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */
+ #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */
+/* ========================================================= ACSR ========================================================== */
+ #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */
+ #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */
+ #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */
+ #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */
+/* ======================================================== DCSMXR ========================================================= */
+ #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */
+ #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */
+ #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */
+ #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */
+/* ======================================================== DWSCTSR ======================================================== */
+ #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */
+ #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */
+ #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */
+ #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */
+
+/* =========================================================================================================================== */
+/* ================ R_USB_HS0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SYSCFG ========================================================= */
+ #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */
+ #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */
+ #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */
+ #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */
+ #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */
+ #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */
+ #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */
+/* ======================================================== BUSWAIT ======================================================== */
+ #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */
+ #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */
+/* ======================================================== SYSSTS0 ======================================================== */
+ #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */
+ #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */
+ #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */
+ #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */
+ #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */
+ #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */
+/* ======================================================== PLLSTA ========================================================= */
+ #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */
+ #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */
+/* ======================================================= DVSTCTR0 ======================================================== */
+ #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */
+ #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */
+ #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */
+ #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */
+ #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */
+ #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */
+ #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */
+ #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */
+ #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */
+ #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */
+/* ======================================================= TESTMODE ======================================================== */
+ #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */
+ #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */
+/* ========================================================= CFIFO ========================================================= */
+ #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
+ #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CFIFOL ========================================================= */
+/* ======================================================== CFIFOH ========================================================= */
+/* ======================================================== CFIFOLL ======================================================== */
+/* ======================================================== CFIFOHH ======================================================== */
+/* ======================================================== D0FIFO ========================================================= */
+ #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
+ #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== D0FIFOL ======================================================== */
+/* ======================================================== D0FIFOH ======================================================== */
+/* ======================================================= D0FIFOLL ======================================================== */
+/* ======================================================= D0FIFOHH ======================================================== */
+/* ======================================================== D1FIFO ========================================================= */
+ #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
+ #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== D1FIFOL ======================================================== */
+/* ======================================================== D1FIFOH ======================================================== */
+/* ======================================================= D1FIFOLL ======================================================== */
+/* ======================================================= D1FIFOHH ======================================================== */
+/* ======================================================= CFIFOSEL ======================================================== */
+ #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */
+ #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= CFIFOCTR ======================================================== */
+ #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================= D0FIFOSEL ======================================================= */
+ #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
+ #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
+ #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= D0FIFOCTR ======================================================= */
+ #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================= D1FIFOSEL ======================================================= */
+ #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
+ #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
+ #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
+ #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
+ #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
+ #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
+ #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
+ #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
+/* ======================================================= D1FIFOCTR ======================================================= */
+ #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
+ #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
+ #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
+ #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
+ #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
+/* ======================================================== INTENB0 ======================================================== */
+ #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */
+ #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */
+ #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */
+ #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */
+ #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */
+ #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */
+ #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */
+ #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */
+ #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */
+/* ======================================================== INTENB1 ======================================================== */
+ #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */
+ #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */
+ #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */
+ #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */
+ #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */
+ #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */
+ #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */
+ #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */
+ #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */
+ #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */
+ #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BRDYENB ======================================================== */
+ #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */
+ #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */
+/* ======================================================== NRDYENB ======================================================== */
+ #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */
+ #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */
+/* ======================================================== BEMPENB ======================================================== */
+ #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */
+ #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */
+/* ======================================================== SOFCFG ========================================================= */
+ #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */
+ #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */
+ #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */
+ #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */
+ #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */
+/* ======================================================== PHYSET ========================================================= */
+ #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */
+ #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */
+ #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */
+ #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
+ #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */
+ #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */
+ #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */
+ #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */
+/* ======================================================== INTSTS0 ======================================================== */
+ #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */
+ #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */
+ #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */
+ #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */
+ #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */
+ #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */
+ #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */
+ #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */
+ #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */
+ #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
+ #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */
+ #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */
+ #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */
+ #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */
+/* ======================================================== INTSTS1 ======================================================== */
+ #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */
+ #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */
+ #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */
+ #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */
+ #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */
+ #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */
+ #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */
+ #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */
+ #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */
+ #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */
+ #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BRDYSTS ======================================================== */
+ #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */
+ #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */
+/* ======================================================== NRDYSTS ======================================================== */
+ #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */
+ #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */
+/* ======================================================== BEMPSTS ======================================================== */
+ #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */
+ #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */
+/* ======================================================== FRMNUM ========================================================= */
+ #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */
+ #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */
+ #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */
+ #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */
+/* ======================================================== UFRMNUM ======================================================== */
+ #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */
+ #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */
+ #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */
+/* ======================================================== USBADDR ======================================================== */
+ #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */
+ #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */
+/* ======================================================== USBREQ ========================================================= */
+ #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
+ #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
+ #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
+ #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+/* ======================================================== USBVAL ========================================================= */
+ #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */
+ #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
+/* ======================================================== USBINDX ======================================================== */
+ #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
+ #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
+/* ======================================================== USBLENG ======================================================== */
+ #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */
+ #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
+/* ======================================================== DCPCFG ========================================================= */
+ #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
+ #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
+ #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+ #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+/* ======================================================== DCPMAXP ======================================================== */
+ #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
+ #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
+ #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */
+/* ======================================================== DCPCTR ========================================================= */
+ #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
+ #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */
+ #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
+ #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
+ #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */
+ #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
+ #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
+ #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
+ #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
+ #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */
+ #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */
+ #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */
+ #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
+/* ======================================================== PIPESEL ======================================================== */
+/* ======================================================== PIPECFG ======================================================== */
+ #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */
+ #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */
+ #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */
+ #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
+ #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
+ #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+ #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */
+ #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */
+/* ======================================================== PIPEBUF ======================================================== */
+ #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */
+ #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */
+ #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */
+ #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */
+/* ======================================================= PIPEMAXP ======================================================== */
+ #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
+ #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
+ #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */
+/* ======================================================= PIPEPERI ======================================================== */
+ #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */
+ #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */
+ #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */
+/* ======================================================= PIPE_CTR ======================================================== */
+ #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
+ #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */
+ #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
+ #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
+ #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */
+ #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */
+ #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
+ #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
+ #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
+ #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
+ #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */
+ #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
+/* ======================================================== DEVADD ========================================================= */
+ #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */
+ #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */
+ #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */
+ #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */
+ #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */
+/* ======================================================== LPCTRL ========================================================= */
+ #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */
+ #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */
+/* ========================================================= LPSTS ========================================================= */
+ #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */
+ #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */
+/* ======================================================== BCCTRL ========================================================= */
+ #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */
+ #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */
+ #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */
+ #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */
+ #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */
+ #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */
+ #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */
+ #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */
+ #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */
+/* ======================================================= PL1CTRL1 ======================================================== */
+ #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */
+ #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */
+ #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
+ #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */
+ #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */
+ #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */
+ #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */
+/* ======================================================= PL1CTRL2 ======================================================== */
+ #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */
+ #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */
+ #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */
+/* ======================================================= HL1CTRL1 ======================================================== */
+ #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */
+ #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */
+ #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */
+/* ======================================================= HL1CTRL2 ======================================================== */
+ #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */
+ #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */
+ #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */
+ #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */
+ #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */
+/* ======================================================= PHYTRIM1 ======================================================== */
+ #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */
+ #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */
+ #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */
+ #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */
+ #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */
+ #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */
+ #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */
+ #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */
+/* ======================================================= PHYTRIM2 ======================================================== */
+ #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */
+ #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */
+ #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */
+ #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */
+ #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */
+ #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */
+ #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */
+/* ======================================================== DPUSR0R ======================================================== */
+ #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */
+ #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */
+ #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */
+ #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSR1R ======================================================== */
+ #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */
+ #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */
+ #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */
+ #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */
+ #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */
+ #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */
+ #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSR2R ======================================================== */
+ #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */
+ #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */
+ #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */
+ #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */
+ #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */
+ #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */
+ #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */
+/* ======================================================== DPUSRCR ======================================================== */
+ #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */
+ #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */
+ #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */
+ #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_AGTX0 ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================ R_FLAD ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== FCKMHZ ========================================================= */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif /* R7FA6M5BH_H */
+
+/** @} */ /* End of group R7FA6M5BH */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
deleted file mode 100644
index 8542eaa843..0000000000
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
+++ /dev/null
@@ -1,623 +0,0 @@
-#ifndef __BASE_ADDRESSES_H
-#define __BASE_ADDRESSES_H
-
-#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Peripheral Address Map ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
-
- #define R_ACMPHS0_BASE 0x400F4000
- #define R_ACMPHS1_BASE 0x400F4100
- #define R_ACMPHS2_BASE 0x400F4200
- #define R_ACMPHS3_BASE 0x400F4300
- #define R_MPU_BASE 0x40000000
- #define R_TZF_BASE 0x40000E00
- #define R_SRAM_BASE 0x40002000
- #define R_BUS_BASE 0x40003000
- #define R_DMAC0_BASE 0x40005000
- #define R_DMAC1_BASE 0x40005040
- #define R_DMAC2_BASE 0x40005080
- #define R_DMAC3_BASE 0x400050C0
- #define R_DMAC4_BASE 0x40005100
- #define R_DMAC5_BASE 0x40005140
- #define R_DMAC6_BASE 0x40005180
- #define R_DMAC7_BASE 0x400051C0
- #define R_DMA_BASE 0x40005200
- #define R_DTC_BASE 0x40005400
- #define R_ICU_BASE 0x40006000
- #define R_CACHE_BASE 0x40007000
- #define R_CPSCU_BASE 0x40008000
- #define R_DBG_BASE 0x4001B000
- #define R_FCACHE_BASE 0x4001C000
- #define R_SYSC_BASE 0x4001E000
- #define R_TSN_CAL_BASE 0x407FB17C
- #define R_TSN_CTRL_BASE 0x400F3000
- #define R_ELC_BASE 0x40082000
- #define R_TC_BASE 0x40083000
- #define R_IWDT_BASE 0x40083200
- #define R_WDT_BASE 0x40083400
- #define R_CAC_BASE 0x40083600
- #define R_MSTP_BASE 0x40084000
- #define R_KINT_BASE 0x40085000
- #define R_POEG_BASE 0x4008A000
- #define R_USB_FS0_BASE 0x40090000
- #define R_USB_HS0_BASE 0x40111000
- #define R_SDHI0_BASE 0x40092000
- #define R_SSI0_BASE 0x4009D000
- #define R_IIC0_BASE 0x4009F000
- #define R_IIC0WU_BASE 0x4009F014
- #define R_IIC1_BASE 0x4009F100
- #define R_OSPI_BASE 0x400A6000
- #define R_CAN0_BASE 0x400A8000
- #define R_CAN1_BASE 0x400A9000
- #define R_CEC_BASE 0x400AC000
- #define R_CANFD_BASE 0x400B0000
- #define R_CTSU_BASE 0x400D0000
- #define R_PSCU_BASE 0x400E0000
- #define R_AGT0_BASE 0x400E8000
- #define R_AGT1_BASE 0x400E8100
- #define R_AGT2_BASE 0x400E8200
- #define R_AGT3_BASE 0x400E8300
- #define R_AGT4_BASE 0x400E8400
- #define R_AGT5_BASE 0x400E8500
- #define R_AGTW0_BASE 0x400E8000
- #define R_AGTW1_BASE 0x400E8100
- #define R_TSN_CTRL_BASE 0x400F3000
- #define R_CRC_BASE 0x40108000
- #define R_DOC_BASE 0x40109000
- #define R_ETHERC_EDMAC_BASE 0x40114000
- #define R_ETHERC0_BASE 0x40114100
- #define R_SCI0_BASE 0x40118000
- #define R_SCI1_BASE 0x40118100
- #define R_SCI2_BASE 0x40118200
- #define R_SCI3_BASE 0x40118300
- #define R_SCI4_BASE 0x40118400
- #define R_SCI5_BASE 0x40118500
- #define R_SCI6_BASE 0x40118600
- #define R_SCI7_BASE 0x40118700
- #define R_SCI8_BASE 0x40118800
- #define R_SCI9_BASE 0x40118900
- #define R_SPI0_BASE 0x4011A000
- #define R_SPI1_BASE 0x4011A100
- #define R_SPI_B0_BASE 0x4011A000
- #define R_SPI_B1_BASE 0x4011A100
- #define R_GPT320_BASE 0x40169000
- #define R_GPT321_BASE 0x40169100
- #define R_GPT322_BASE 0x40169200
- #define R_GPT323_BASE 0x40169300
- #define R_GPT164_BASE 0x40169400
- #define R_GPT165_BASE 0x40169500
- #define R_GPT166_BASE 0x40169600
- #define R_GPT167_BASE 0x40169700
- #define R_GPT168_BASE 0x40169800
- #define R_GPT169_BASE 0x40169900
- #define R_GPT_OPS_BASE 0x40169A00
- #define R_GPT_ODC_BASE 0x4016A000
- #define R_GPT_GTCLK_BASE 0x40169B00
- #define R_ADC120_BASE 0x40170000
- #define R_ADC121_BASE 0x40170200
-
-/* Not included in SVD */
- #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
- #define R_DAC120_BASE 0x40172000
- #define R_DAC121_BASE 0x40172100
- #else
- #define R_DAC12_BASE 0x40171000
- #endif
- #define R_FLAD_BASE 0x407FC000
- #define R_FACI_HP_CMD_BASE 0x407E0000
- #define R_FACI_HP_BASE 0x407FE000
- #define R_QSPI_BASE 0x64000000
- #define R_TFU_BASE 0x40021000
-
-/* Not included in SVD */
- #if (2U == BSP_FEATURE_IOPORT_VERSION)
- #define R_PORT0_BASE 0x4001F000
- #define R_PORT1_BASE 0x4001F020
- #define R_PORT2_BASE 0x4001F040
- #define R_PORT10_BASE 0x4001F140
- #define R_PORT11_BASE 0x4001F160
- #define R_PORT12_BASE 0x4001F180
- #define R_PORT13_BASE 0x4001F1A0
- #define R_PORT14_BASE 0x4001F1C0
- #define R_PFS_BASE 0x4001F800
- #define R_PMISC_BASE 0x4001FD00
- #else
- #define R_PORT0_BASE 0x40080000
- #define R_PORT1_BASE 0x40080020
- #define R_PORT2_BASE 0x40080040
- #define R_PORT3_BASE 0x40080060
- #define R_PORT4_BASE 0x40080080
- #define R_PORT5_BASE 0x400800A0
- #define R_PORT6_BASE 0x400800C0
- #define R_PORT7_BASE 0x400800E0
- #define R_PORT8_BASE 0x40080100
- #define R_PORT9_BASE 0x40080120
- #define R_PORT10_BASE 0x40080140
- #define R_PORT11_BASE 0x40080160
- #define R_PFS_BASE 0x40080800
- #define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
- #endif
- #define R_GPT_POEG0_BASE 0x4008A000
- #define R_GPT_POEG1_BASE 0x4008A100
- #define R_GPT_POEG2_BASE 0x4008A200
- #define R_GPT_POEG3_BASE 0x4008A300
-
- #define R_RTC_BASE 0x40083000
-
- #define R_I3C0_BASE 0x4011F000
- #define R_I3C1_BASE 0x4011F400
-
-/** @} */ /* End of group Device_Peripheral_peripheralAddr */
-
-/* =========================================================================================================================== */
-/* ================ Peripheral declaration ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-// #define R_MPU ((R_MPU_Type *) R_MPU_BASE)
- #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
- #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
- #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
- #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
- #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
- #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
- #define R_TZF ((R_TZF_Type *) R_TZF_BASE)
- #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
- #define R_BUS ((R_BUS_B_Type *) R_BUS_BASE)
- #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
- #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
- #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
- #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
- #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
- #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
- #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
- #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
- #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
- #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
- #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
- #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
- #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
- #define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
- #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
- #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
- #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
- #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
- #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
- #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
- #define R_TC ((R_TC_Type *) R_TC_BASE)
- #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
- #define R_KINT ((R_KINT_Type *) R_KINT_BASE)
- #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
- #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
- #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
- #define R_POEG ((R_POEG_Type *) R_POEG_BASE)
- #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
- #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
- #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
- #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
- #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
- #define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
- #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
- #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
- #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
- #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
- #define R_CEC ((R_CEC_Type *) R_CEC_BASE)
- #if BSP_FEATURE_CANFD_LITE
- #define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE)
- #else
- #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
- #endif
- #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
- #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
- #if BSP_FEATURE_AGT_HAS_AGTW
- #define R_AGT0 ((R_AGTW0_Type *) R_AGT0_BASE)
- #define R_AGT1 ((R_AGTW0_Type *) R_AGT1_BASE)
- #define R_AGT2 ((R_AGTW0_Type *) R_AGT2_BASE)
- #define R_AGT3 ((R_AGTW0_Type *) R_AGT3_BASE)
- #define R_AGT4 ((R_AGTW0_Type *) R_AGT4_BASE)
- #define R_AGT5 ((R_AGTW0_Type *) R_AGT5_BASE)
- #else
- #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
- #endif
- #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
- #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
- #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
- #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
- #if (2U == BSP_FEATURE_DOC_VERSION)
- #define R_DOC_B ((R_DOC_B_Type *) R_DOC_BASE)
- #else
- #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
- #endif
- #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
- #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
- #if (2U == BSP_FEATURE_SCI_VERSION)
- #define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE)
- #define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE)
- #define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE)
- #define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE)
- #define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE)
- #define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE)
- #else
- #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
- #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
- #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
- #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
- #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
- #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
- #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
- #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
- #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
- #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
- #endif
- #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
- #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
- #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE)
- #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE)
- #define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
- #define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
- #define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
- #define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
- #define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
- #define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
- #define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
- #define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
- #define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
- #define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
- #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
- #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
- #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE)
- #define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
- #define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
- #define R_ADC_B ((R_ADC_B0_Type *) R_ADC120_BASE)
- #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
- #define R_DAC0 ((R_DAC_Type *) R_DAC120_BASE)
- #define R_DAC1 ((R_DAC_Type *) R_DAC121_BASE)
- #else
- #define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
- #endif
- #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
- #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
- #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
- #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
- #define R_TFU ((R_TFU_Type *) R_TFU_BASE)
- #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
- #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
-
-/* Not in SVD. */
-
- #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
- #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
- #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
- #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
- #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
- #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
- #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
- #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
- #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
- #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
- #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
- #if (2U == BSP_FEATURE_IOPORT_VERSION)
- #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
- #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
- #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
- #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
- #endif
- #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
- #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
-
- #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
- #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
- #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
- #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
-
- #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
-
-/** @} */ /* End of group Device_Peripheral_declaration */
-
-#else
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Peripheral Address Map ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
-
- #define R_ACMPHS0_BASE 0x40085000
- #define R_ACMPHS1_BASE 0x40085100
- #define R_ACMPHS2_BASE 0x40085200
- #define R_ACMPHS3_BASE 0x40085300
- #define R_ACMPHS4_BASE 0x40085400
- #define R_ACMPHS5_BASE 0x40085500
- #define R_ACMPLP_BASE 0x40085E00
- #define R_ADC0_BASE 0x4005C000
- #define R_ADC1_BASE 0x4005C200
- #define R_AGT0_BASE 0x40084000
- #define R_AGT1_BASE 0x40084100
- #define R_AGTW0_BASE 0x40084000
- #define R_AGTW1_BASE 0x40084100
- #define R_BUS_BASE 0x40003000
- #define R_CAC_BASE 0x40044600
- #define R_CAN0_BASE 0x40050000
- #define R_CAN1_BASE 0x40051000
- #define R_CRC_BASE 0x40074000
- #define R_CTSU_BASE 0x40081000
- #define R_CTSU2_BASE 0x40082000
- #define R_DAC_BASE 0x4005E000
- #define R_DAC8_BASE 0x4009E000
- #define R_DALI0_BASE 0x4008F000
- #define R_DEBUG_BASE 0x4001B000
- #define R_DMA_BASE 0x40005200
- #define R_DMAC0_BASE 0x40005000
- #define R_DMAC1_BASE 0x40005040
- #define R_DMAC2_BASE 0x40005080
- #define R_DMAC3_BASE 0x400050C0
- #define R_DMAC4_BASE 0x40005100
- #define R_DMAC5_BASE 0x40005140
- #define R_DMAC6_BASE 0x40005180
- #define R_DMAC7_BASE 0x400051C0
- #define R_DOC_BASE 0x40054100
- #define R_DRW_BASE 0x400E4000
- #define R_DTC_BASE 0x40005400
- #define R_ELC_BASE 0x40041000
- #define R_ETHERC0_BASE 0x40064100
- #define R_ETHERC_EDMAC_BASE 0x40064000
- #define R_PTP_EDMAC_BASE 0x40064400
- #define R_ETHERC_EPTPC_BASE 0x40065800
- #define R_ETHERC_EPTPC1_BASE 0x40065C00
- #define R_ETHERC_EPTPC_CFG_BASE 0x40064500
- #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000
- #define R_FACI_HP_CMD_BASE 0x407E0000
- #define R_FACI_HP_BASE 0x407FE000
- #define R_FACI_LP_BASE 0x407EC000
- #define R_CTSUTRIM_BASE 0x407EC000
- #define R_FCACHE_BASE 0x4001C000
- #define R_GLCDC_BASE 0x400E0000
- #define R_GPT0_BASE 0x40078000
- #define R_GPT1_BASE 0x40078100
- #define R_GPT2_BASE 0x40078200
- #define R_GPT3_BASE 0x40078300
- #define R_GPT4_BASE 0x40078400
- #define R_GPT5_BASE 0x40078500
- #define R_GPT6_BASE 0x40078600
- #define R_GPT7_BASE 0x40078700
- #define R_GPT8_BASE 0x40078800
- #define R_GPT9_BASE 0x40078900
- #define R_GPT10_BASE 0x40078A00
- #define R_GPT11_BASE 0x40078B00
- #define R_GPT12_BASE 0x40078C00
- #define R_GPT13_BASE 0x40078D00
- #define R_GPT_ODC_BASE 0x4007B000
- #define R_GPT_OPS_BASE 0x40078FF0
- #define R_GPT_POEG0_BASE 0x40042000
- #define R_GPT_POEG1_BASE 0x40042100
- #define R_GPT_POEG2_BASE 0x40042200
- #define R_GPT_POEG3_BASE 0x40042300
- #define R_I3C0_BASE 0x40083000
- #define R_ICU_BASE 0x40006000
- #define R_IIC0_BASE 0x40053000
- #define R_IIC1_BASE 0x40053100
- #define R_IIC2_BASE 0x40053200
- #define R_IRDA_BASE 0x40070F00
- #define R_IWDT_BASE 0x40044400
- #define R_JPEG_BASE 0x400E6000
- #define R_KINT_BASE 0x40080000
- #define R_MMF_BASE 0x40001000
- #define R_MPU_MMPU_BASE 0x40000000
- #define R_MPU_SMPU_BASE 0x40000C00
- #define R_MPU_SPMON_BASE 0x40000D00
- #define R_MSTP_BASE (0x40047000 - 4U) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
- #define R_OPAMP_BASE 0x40086000
- #define R_OPAMP2_BASE 0x400867F8
- #define R_PDC_BASE 0x40094000
- #define R_PORT0_BASE 0x40040000
- #define R_PORT1_BASE 0x40040020
- #define R_PORT2_BASE 0x40040040
- #define R_PORT3_BASE 0x40040060
- #define R_PORT4_BASE 0x40040080
- #define R_PORT5_BASE 0x400400A0
- #define R_PORT6_BASE 0x400400C0
- #define R_PORT7_BASE 0x400400E0
- #define R_PORT8_BASE 0x40040100
- #define R_PORT9_BASE 0x40040120
- #define R_PORT10_BASE 0x40040140
- #define R_PORT11_BASE 0x40040160
- #define R_PFS_BASE 0x40040800
- #define R_PMISC_BASE 0x40040D00
- #define R_QSPI_BASE 0x64000000
- #define R_RTC_BASE 0x40044000
- #define R_SCI0_BASE 0x40070000
- #define R_SCI1_BASE 0x40070020
- #define R_SCI2_BASE 0x40070040
- #define R_SCI3_BASE 0x40070060
- #define R_SCI4_BASE 0x40070080
- #define R_SCI5_BASE 0x400700A0
- #define R_SCI6_BASE 0x400700C0
- #define R_SCI7_BASE 0x400700E0
- #define R_SCI8_BASE 0x40070100
- #define R_SCI9_BASE 0x40070120
- #define R_SDADC0_BASE 0x4009C000
- #define R_SDHI0_BASE 0x40062000
- #define R_SDHI1_BASE 0x40062400
- #define R_SLCDC_BASE 0x40082000
- #define R_SPI0_BASE 0x40072000
- #define R_SPI1_BASE 0x40072100
- #define R_SRAM_BASE 0x40002000
- #define R_SRC_BASE 0x40048000
- #define R_SSI0_BASE 0x4004E000
- #define R_SSI1_BASE 0x4004E100
- #define R_SYSTEM_BASE 0x4001E000
- #define R_TSN_BASE 0x407EC000
- #define R_TSN_CAL_BASE 0x407FB17C
- #define R_TSN_CTRL_BASE 0x4005D000
- #define R_USB_FS0_BASE 0x40090000
- #define R_USB_HS0_BASE 0x40060000
- #define R_WDT_BASE 0x40044200
-
-/** @} */ /* End of group Device_Peripheral_peripheralAddr */
-
-/* =========================================================================================================================== */
-/* ================ Peripheral declaration ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
- #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
- #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
- #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
- #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
- #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
- #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
- #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE)
- #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
- #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
- #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
- #define R_BUS ((R_BUS_Type *) R_BUS_BASE)
- #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
- #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
- #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
- #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
- #if (2U == BSP_FEATURE_CTSU_VERSION)
- #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE)
- #else
- #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
- #endif
- #define R_DAC ((R_DAC_Type *) R_DAC_BASE)
- #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE)
- #define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE)
- #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
- #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
- #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
- #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
- #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
- #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
- #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
- #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
- #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
- #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
- #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
- #define R_DRW ((R_DRW_Type *) R_DRW_BASE)
- #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
- #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
- #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
- #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
- #define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE)
- #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
- #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE)
- #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
- #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
- #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
- #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
- #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE)
- #define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
- #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
- #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE)
- #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
- #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
- #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
- #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
- #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
- #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
- #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
- #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
- #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
- #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
- #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
- #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
- #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
- #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
- #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
- #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
- #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
- #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
- #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
- #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
- #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
- #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
- #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
- #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
- #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
- #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE)
- #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
- #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE)
- #define R_KINT ((R_KINT_Type *) R_KINT_BASE)
- #define R_MMF ((R_MMF_Type *) R_MMF_BASE)
- #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
- #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
- #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
- #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
- #if (2U == BSP_FEATURE_OPAMP_BASE_ADDRESS)
- #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE)
- #else
- #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE)
- #endif
- #define R_PDC ((R_PDC_Type *) R_PDC_BASE)
- #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
- #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
- #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
- #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
- #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
- #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
- #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
- #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
- #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
- #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
- #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
- #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
- #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
- #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
- #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
- #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
- #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
- #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
- #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
- #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
- #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
- #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
- #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
- #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
- #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
- #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
- #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE)
- #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
- #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
- #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE)
- #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
- #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
- #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
- #define R_SRC ((R_SRC_Type *) R_SRC_BASE)
- #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
- #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
- #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
- #define R_TSN ((R_TSN_Type *) R_TSN_BASE)
- #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
- #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
- #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
- #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
- #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
-
-/** @} */ /* End of group Device_Peripheral_declaration */
-
-#endif
-
-#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
index a48f6d2926..cf586331f9 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -56,6 +56,56 @@ extern "C" {
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
+ #if BSP_MCU_GROUP_RA2A1
+ #include "R7FA2A1AB.h"
+ #elif BSP_MCU_GROUP_RA2E1
+ #include "R7FA2E1A9.h"
+ #elif BSP_MCU_GROUP_RA2E2
+ #include "R7FA2E2A7.h"
+ #elif BSP_MCU_GROUP_RA2L1
+ #include "R7FA2L1AB.h"
+ #elif BSP_MCU_GROUP_RA4E1
+ #include "R7FA4E10D.h"
+ #elif BSP_MCU_GROUP_RA4E2
+ #include "R7FA4E2B9.h"
+ #elif BSP_MCU_GROUP_RA4M1
+ #include "R7FA4M1AB.h"
+ #elif BSP_MCU_GROUP_RA4M2
+ #include "R7FA4M2AD.h"
+ #elif BSP_MCU_GROUP_RA4M3
+ #include "R7FA4M3AF.h"
+ #elif BSP_MCU_GROUP_RA4T1
+ #include "R7FA4T1BB.h"
+ #elif BSP_MCU_GROUP_RA4W1
+ #include "R7FA4W1AD.h"
+ #elif BSP_MCU_GROUP_RA6E1
+ #include "R7FA6E10F.h"
+ #elif BSP_MCU_GROUP_RA6E2
+ #include "R7FA6E2BB.h"
+ #elif BSP_MCU_GROUP_RA6M1
+ #include "R7FA6M1AD.h"
+ #elif BSP_MCU_GROUP_RA6M2
+ #include "R7FA6M2AF.h"
+ #elif BSP_MCU_GROUP_RA6M3
+ #include "R7FA6M3AH.h"
+ #elif BSP_MCU_GROUP_RA6M4
+ #include "R7FA6M4AF.h"
+ #elif BSP_MCU_GROUP_RA6M5
+ #include "R7FA6M5BH.h"
+ #elif BSP_MCU_GROUP_RA6T1
+ #include "R7FA6T1AD.h"
+ #elif BSP_MCU_GROUP_RA6T2
+ #include "R7FA6T2BD.h"
+ #elif BSP_MCU_GROUP_RA6T3
+ #include "R7FA6T3BB.h"
+ #else
+ #if __has_include("renesas_internal.h")
+ #include "renesas_internal.h"
+ #else
+ #warning "Unsupported MCU"
+ #endif
+ #endif
+
#if __ARM_ARCH_7EM__
#define RENESAS_CORTEX_M4
#elif __ARM_ARCH_6M__
@@ -64,46584 +114,12 @@ extern "C" {
#define RENESAS_CORTEX_M23
#elif __ARM_ARCH_8M_MAIN__
#define RENESAS_CORTEX_M33
+ #elif __ARM_ARCH_8_1M_MAIN__
+ #define RENESAS_CORTEX_M85
#else
#warning Unsupported Architecture
#endif
-/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
- #ifdef RENESAS_CORTEX_M4
- #define __MPU_PRESENT 1 /*!< MPU present or not */
- #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
- #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
- #define __FPU_PRESENT 1 /*!< FPU present or not */
- #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
- #elif defined(RENESAS_CORTEX_M0PLUS)
- #define __MPU_PRESENT 1 /*!< MPU present or not */
- #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
- #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
- #define __FPU_PRESENT 0 /*!< FPU present or not */
- #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */
- #include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */
- #elif defined(RENESAS_CORTEX_M23)
- #define __MPU_PRESENT 1 /*!< MPU present or not */
- #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
- #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
- #define __FPU_PRESENT 0 /*!< FPU present or not */
- #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */
- #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */
- #elif defined(RENESAS_CORTEX_M33)
- #define __MPU_PRESENT 1 /*!< MPU present or not */
- #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
- #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
- #define __FPU_PRESENT 1 /*!< FPU present or not */
- #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */
- #define __DSP_PRESENT 1 /*!< DSP present or not */
- #include "core_cm33.h" /*!< Cortex-M33 processor and core peripherals */
- #endif
-
- #include "system.h" /*!< System */
-
- #ifndef __IM /*!< Fallback for older CMSIS versions */
- #define __IM __I
- #endif
- #ifndef __OM /*!< Fallback for older CMSIS versions */
- #define __OM __O
- #endif
- #ifndef __IOM /*!< Fallback for older CMSIS versions */
- #define __IOM __IO
- #endif
-
-/* ======================================== Start of section using anonymous unions ======================================== */
- #if defined(__CC_ARM)
- #pragma push
- #pragma anon_unions
- #elif defined(__ICCARM__)
- #pragma language=extended
- #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wc11-extensions"
- #pragma clang diagnostic ignored "-Wreserved-id-macro"
- #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
- #pragma clang diagnostic ignored "-Wnested-anon-types"
- #elif defined(__GNUC__)
-
-/* anonymous unions are enabled by default */
- #elif defined(__TMS470__)
-
-/* anonymous unions are enabled by default */
- #elif defined(__TASKING__)
- #pragma warning 586
- #elif defined(__CSMC__)
-
-/* anonymous unions are enabled by default */
- #else
- #warning Not supported compiler type
- #endif
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Cluster Section ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_clusters
- * @{
- */
-
-/**
- * @brief R_BUS_CSa [CSa] (CS Registers)
- */
-typedef struct
-{
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
-
- struct
- {
- __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
- uint16_t : 2;
- __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
- uint16_t : 4;
- __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
- __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
- uint16_t : 5;
- __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
- } MOD_b;
- };
-
- union
- {
- __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
-
- struct
- {
- __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
- * is valid only when the PWENB bit in CSnMOD is set to 1. */
- uint32_t : 5;
- __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
- * is valid only when the PRENB bit in CSnMOD is set to 1. */
- uint32_t : 5;
- __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
- uint32_t : 3;
- __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
- uint32_t : 3;
- } WCR1_b;
- };
-
- union
- {
- __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
-
- struct
- {
- __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
- uint32_t : 2;
- __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
- uint32_t : 1;
- __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
- uint32_t : 1;
- __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
- uint32_t : 1;
- __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
- uint32_t : 1;
- } WCR2_b;
- };
- __IM uint32_t RESERVED1;
-} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_CSb [CSb] (CS Registers)
- */
-typedef struct
-{
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
-
- struct
- {
- __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
- uint16_t : 3;
- __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
- uint16_t : 2;
- __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
- uint16_t : 3;
- __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
- uint16_t : 3;
- } CR_b;
- };
- __IM uint16_t RESERVED1[3];
-
- union
- {
- __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
-
- struct
- {
- __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
- uint16_t : 4;
- __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
- uint16_t : 4;
- } REC_b;
- };
- __IM uint16_t RESERVED2[2];
-} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */
-
- struct
- {
- __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */
- uint8_t : 3;
- __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */
- uint8_t : 2;
- } SDCCR_b;
- };
-
- union
- {
- __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */
-
- struct
- {
- __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */
- uint8_t : 7;
- } SDCMOD_b;
- };
-
- union
- {
- __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */
-
- struct
- {
- __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */
- uint8_t : 7;
- } SDAMOD_b;
- };
- __IM uint8_t RESERVED;
- __IM uint32_t RESERVED1[3];
-
- union
- {
- __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */
-
- struct
- {
- __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */
- uint8_t : 7;
- } SDSELF_b;
- };
- __IM uint8_t RESERVED2;
- __IM uint16_t RESERVED3;
-
- union
- {
- __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */
-
- struct
- {
- __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */
- __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
- * Setting. ( REFW+1 Cycles ) */
- } SDRFCR_b;
- };
-
- union
- {
- __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */
-
- struct
- {
- __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */
- uint8_t : 7;
- } SDRFEN_b;
- };
- __IM uint8_t RESERVED4;
- __IM uint32_t RESERVED5[2];
-
- union
- {
- __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */
-
- struct
- {
- __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */
- uint8_t : 7;
- } SDICR_b;
- };
- __IM uint8_t RESERVED6;
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */
-
- struct
- {
- __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */
- __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */
- __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
- * ) */
- uint16_t : 5;
- } SDIR_b;
- };
- __IM uint16_t RESERVED8;
- __IM uint32_t RESERVED9[6];
-
- union
- {
- __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */
-
- struct
- {
- __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */
- uint8_t : 6;
- } SDADR_b;
- };
- __IM uint8_t RESERVED10;
- __IM uint16_t RESERVED11;
-
- union
- {
- __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */
-
- struct
- {
- __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */
- uint32_t : 5;
- __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */
- __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */
- __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */
- uint32_t : 2;
- __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */
- uint32_t : 13;
- } SDTR_b;
- };
-
- union
- {
- __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */
-
- struct
- {
- __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
- * set command is issued. */
- uint16_t : 1;
- } SDMOD_b;
- };
- __IM uint16_t RESERVED12;
- __IM uint32_t RESERVED13;
-
- union
- {
- __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */
-
- struct
- {
- __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */
- uint8_t : 2;
- __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */
- __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */
- uint8_t : 3;
- } SDSR_b;
- };
- __IM uint8_t RESERVED14;
- __IM uint16_t RESERVED15;
-} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */
-
-/**
- * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
-
- struct
- {
- __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
- * an error address. */
- } ADD_b;
- };
-
- union
- {
- __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */
-
- struct
- {
- __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */
- uint8_t : 6;
- __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */
- } STAT_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[2];
-} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */
-
- struct
- {
- uint16_t : 15;
- __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */
- } CNT_b;
- };
- __IM uint16_t RESERVED;
-} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */
-
- struct
- {
- uint16_t : 4;
- __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */
- uint16_t : 10;
- } CNT_b;
- };
- __IM uint16_t RESERVED;
-} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_CAN0_MB [MB] (Mailbox)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */
-
- struct
- {
- __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */
- __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */
- uint32_t : 1;
- __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */
- __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */
- } ID_b;
- };
-
- union
- {
- __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */
-
- struct
- {
- __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */
- uint16_t : 12;
- } DL_b;
- };
-
- union
- {
- __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */
-
- struct
- {
- __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN
- * message data. Transmission or reception starts from DATA0.
- * The bit order on the CAN bus is MSB-first, and transmission
- * or reception starts from bit 7 */
- } D_b[8];
- };
-
- union
- {
- __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */
-
- struct
- {
- __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter
- * value of the time stamp when received messages are stored
- * in the mailbox. */
- __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter
- * value of the time stamp when received messages are stored
- * in the mailbox. */
- } TS_b;
- };
-} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */
-
- struct
- {
- __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */
- __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */
- __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */
- __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */
- } NCFG_b;
- };
-
- union
- {
- __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */
-
- struct
- {
- __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */
- __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */
- __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */
- uint32_t : 4;
- __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */
- __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */
- __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */
- __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */
- __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */
- __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */
- __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */
- __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */
- __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */
- __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */
- __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */
- __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
- * enable */
- uint32_t : 1;
- __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */
- __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */
- __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */
- __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */
- __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */
- __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */
- __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */
- __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */
- __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */
- } CTR_b;
- };
-
- union
- {
- __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */
-
- struct
- {
- __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */
- __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */
- __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */
- __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */
- __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */
- __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */
- __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */
- __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */
- __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */
- uint32_t : 7;
- __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */
- __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */
- } STS_b;
- };
-
- union
- {
- __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */
-
- struct
- {
- __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */
- __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */
- __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */
- __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */
- __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */
- __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */
- __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */
- __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */
- __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */
- __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */
- __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */
- __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */
- __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */
- __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */
- __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */
- uint32_t : 1;
- __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */
- uint32_t : 1;
- } ERFL_b;
- };
-} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */
-
- struct
- {
- __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */
- __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */
- uint32_t : 3;
- __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */
- uint32_t : 4;
- __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */
- uint32_t : 4;
- } DCFG_b;
- };
-
- union
- {
- __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */
-
- struct
- {
- __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */
- uint32_t : 5;
- __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */
- __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */
- __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */
- uint32_t : 5;
- __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */
- __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */
- __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */
- __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */
- uint32_t : 1;
- __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */
- __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */
- __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */
- __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */
- } FDCFG_b;
- };
-
- union
- {
- __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */
-
- struct
- {
- __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */
- __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */
- uint32_t : 30;
- } FDCTR_b;
- };
-
- union
- {
- __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */
- __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */
- __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */
- uint32_t : 5;
- __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */
- __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */
- __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */
- } FDSTS_b;
- };
-
- union
- {
- __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */
-
- struct
- {
- __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */
- uint32_t : 3;
- __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */
- uint32_t : 4;
- } FDCRC_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */
-
- struct
- {
- __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */
- uint32_t : 7;
- __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */
- uint32_t : 23;
- } BLCT_b;
- };
-
- union
- {
- __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */
-
- struct
- {
- uint32_t : 3;
- __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */
- } BLSTS_b;
- };
-} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */
-
-/**
- * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */
-
- struct
- {
- __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */
- __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */
- __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */
- __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */
-
- struct
- {
- __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */
- __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */
- __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */
- __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */
- } M_b;
- };
-
- union
- {
- __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */
-
- struct
- {
- __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */
- __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination
- * 0 */
- __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination
- * 1 */
- __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination
- * 2 */
- __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */
- __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
- * Pointer */
- uint32_t : 2;
- __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */
- __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */
- } P0_b;
- };
-
- union
- {
- __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */
-
- struct
- {
- __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */
- uint32_t : 18;
- } P1_b;
- };
-} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */
-
- struct
- {
- __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */
- __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */
- uint32_t : 5;
- __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */
- __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */
- } ACC0_b;
- };
-
- union
- {
- __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */
-
- struct
- {
- __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */
- __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */
- uint32_t : 14;
- } ACC1_b;
- };
-} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */
-
-/**
- * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */
-
- struct
- {
- __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */
- uint32_t : 1;
- __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */
- __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */
-
- struct
- {
- __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */
- uint32_t : 12;
- __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */
- __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */
- uint32_t : 6;
- __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */
-
- struct
- {
- __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */
- } DF_b[64];
- };
- __IM uint32_t RESERVED[13];
-} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */
-
-/**
- * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */
-
- struct
- {
- __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */
- uint32_t : 1;
- __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */
- __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */
-
- struct
- {
- __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */
- uint32_t : 12;
- __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */
- __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */
- uint32_t : 6;
- __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */
-
- struct
- {
- __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */
- } DF_b[64];
- };
- __IM uint32_t RESERVED[13];
-} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */
-
-/**
- * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
-
- struct
- {
- __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
- uint32_t : 1;
- __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
- __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
-
- struct
- {
- __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
- uint32_t : 12;
- __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
-
- struct
- {
- __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
- __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
- uint32_t : 6;
- __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
-
- struct
- {
- __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
- } DF_b[64];
- };
- __IM uint32_t RESERVED[13];
-} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */
-
-/**
- * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */
-
- struct
- {
- __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */
- uint32_t : 1;
- __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */
- __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */
-
- struct
- {
- __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */
- uint32_t : 12;
- __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */
-
- struct
- {
- __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */
- __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */
- uint32_t : 6;
- __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */
- } FDCTR_b;
- };
-
- union
- {
- __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */
-
- struct
- {
- __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */
- } DF_b[64];
- };
- __IM uint32_t RESERVED[13];
-} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */
-
-/**
- * @brief R_CANFDL_CFDC [CFDC] (Channel Control/Status)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */
-
- struct
- {
- __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */
- __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */
- __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */
- __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */
- } NCFG_b;
- };
-
- union
- {
- __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */
-
- struct
- {
- __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */
- __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */
- __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */
- uint32_t : 4;
- __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */
- __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */
- __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */
- __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */
- __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */
- __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */
- __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */
- __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */
- __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */
- __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */
- __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */
- __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
- * enable */
- uint32_t : 1;
- __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */
- __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */
- __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */
- __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */
- uint32_t : 3;
- __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */
- __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */
- } CTR_b;
- };
-
- union
- {
- __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */
-
- struct
- {
- __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */
- __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */
- __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */
- __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */
- __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */
- __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */
- __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */
- __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */
- __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */
- uint32_t : 7;
- __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */
- __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */
- } STS_b;
- };
-
- union
- {
- __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */
-
- struct
- {
- __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */
- __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */
- __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */
- __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */
- __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */
- __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */
- __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */
- __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */
- __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */
- __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */
- __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */
- __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */
- __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */
- __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */
- __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */
- uint32_t : 1;
- __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */
- uint32_t : 1;
- } ERFL_b;
- };
-} R_CANFDL_CFDC_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_CANFDL_CFDC2 [CFDC2] (Channel Configuration Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */
-
- struct
- {
- __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */
- __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */
- uint32_t : 3;
- __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */
- uint32_t : 4;
- __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */
- uint32_t : 4;
- } DCFG_b;
- };
-
- union
- {
- __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */
-
- struct
- {
- __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */
- uint32_t : 5;
- __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */
- __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */
- __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */
- uint32_t : 5;
- __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */
- uint32_t : 4;
- __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */
- __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */
- __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */
- uint32_t : 1;
- } FDCFG_b;
- };
-
- union
- {
- __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */
-
- struct
- {
- __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */
- __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */
- uint32_t : 30;
- } FDCTR_b;
- };
-
- union
- {
- __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */
- __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */
- __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */
- uint32_t : 5;
- __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */
- __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */
- __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */
- } FDSTS_b;
- };
-
- union
- {
- __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */
-
- struct
- {
- __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */
- uint32_t : 3;
- __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */
- uint32_t : 4;
- } FDCRC_b;
- };
- __IM uint32_t RESERVED[3];
-} R_CANFDL_CFDC2_Type; /*!< Size = 32 (0x20) */
-
-/**
- * @brief R_CANFDL_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */
-
- struct
- {
- __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */
- __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */
- __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */
- __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */
-
- struct
- {
- __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */
- __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */
- __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */
- __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */
- } M_b;
- };
-
- union
- {
- __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */
-
- struct
- {
- __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */
- uint32_t : 3;
- __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */
- __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
- * Pointer */
- uint32_t : 2;
- __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */
- __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */
- } P0_b;
- };
-
- union
- {
- __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */
-
- struct
- {
- __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */
- uint32_t : 23;
- } P1_b;
- };
-} R_CANFDL_CFDGAFL_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_CANFDL_CFDTHL [CFDTHL] (Channel TX History List)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */
-
- struct
- {
- __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */
- __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */
- uint32_t : 6;
- __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */
- } ACC0_b;
- };
-
- union
- {
- __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */
-
- struct
- {
- __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */
- __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */
- uint32_t : 14;
- } ACC1_b;
- };
-} R_CANFDL_CFDTHL_Type; /*!< Size = 8 (0x8) */
-
-/**
- * @brief R_CANFDL_CFDRF [CFDRF] (RX FIFO Access Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */
-
- struct
- {
- __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */
- uint32_t : 1;
- __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */
- __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */
-
- struct
- {
- __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */
- uint32_t : 12;
- __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */
- __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */
- uint32_t : 6;
- __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */
-
- struct
- {
- __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */
- } DF_b[64];
- };
-} R_CANFDL_CFDRF_Type; /*!< Size = 76 (0x4c) */
-
-/**
- * @brief R_CANFDL_CFDCF [CFDCF] (Common FIFO Access Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
-
- struct
- {
- __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
- uint32_t : 1;
- __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
- __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
-
- struct
- {
- __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
- uint32_t : 12;
- __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
-
- struct
- {
- __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
- __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
- uint32_t : 6;
- __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
-
- struct
- {
- __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
- } DF_b[64];
- };
-} R_CANFDL_CFDCF_Type; /*!< Size = 76 (0x4c) */
-
-/**
- * @brief R_CANFDL_CFDTM [CFDTM] (TX Message Buffer Access Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */
-
- struct
- {
- __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */
- uint32_t : 1;
- __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */
- __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */
-
- struct
- {
- __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */
- uint32_t : 12;
- __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */
-
- struct
- {
- __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */
- __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */
- uint32_t : 6;
- __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */
- } FDCTR_b;
- };
-
- union
- {
- __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */
-
- struct
- {
- __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */
- } DF_b[64];
- };
-} R_CANFDL_CFDTM_Type; /*!< Size = 76 (0x4c) */
-
-/**
- * @brief R_CANFDL_CFDRMC_RM [RM] (RX Message Buffer Access Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */
-
- struct
- {
- __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */
- uint32_t : 1;
- __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */
- __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */
- } ID_b;
- };
-
- union
- {
- __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */
-
- struct
- {
- __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */
- uint32_t : 12;
- __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */
- } PTR_b;
- };
-
- union
- {
- __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */
-
- struct
- {
- __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */
- __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
- __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */
- uint32_t : 5;
- __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */
- uint32_t : 6;
- __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */
- } FDSTS_b;
- };
-
- union
- {
- __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */
-
- struct
- {
- __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */
- } DF_b[64];
- };
-} R_CANFDL_CFDRMC_RM_Type; /*!< Size = 76 (0x4c) */
-
-/**
- * @brief R_CANFDL_CFDRMC [CFDRMC] (RX Message Buffer Access Clusters)
- */
-typedef struct
-{
- __IOM R_CANFDL_CFDRMC_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */
- __IM uint32_t RESERVED[104];
-} R_CANFDL_CFDRMC_Type; /*!< Size = 1024 (0x400) */
-
-/**
- * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
- */
-typedef struct
-{
- union
- {
- __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */
-
- struct
- {
- __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */
- uint8_t : 5;
- __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */
- __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */
- } BY_b;
- };
- #if (2U == BSP_FEATURE_ELC_VERSION)
- __IM uint8_t RESERVED[3];
- #else
- __IM uint8_t RESERVED;
- #endif
-} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */
-
-/**
- * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */
-
- struct
- {
- __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */
- uint16_t : 7;
- } HA_b;
- };
- __IM uint16_t RESERVED;
-} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */
-
- struct
- {
- __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the start time of the pulse output timer in nanoseconds. */
- } STTRU_b;
- };
-
- union
- {
- __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */
-
- struct
- {
- __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the start time of the pulse output timer in nanoseconds. */
- } STTRL_b;
- };
-
- union
- {
- __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */
-
- struct
- {
- __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in
- * nanoseconds. Set a value that is equivalent to at least
- * four cycles of the STCA clock. */
- uint32_t : 2;
- } CYCR_b;
- };
-
- union
- {
- __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */
-
- struct
- {
- __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse
- * signal from the timer in nanoseconds. Set a value that
- * is equivalent to at least two cycles of the STCA clock. */
- uint32_t : 3;
- } PLSR_b;
- };
-} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */
-
- struct
- {
- __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
- * bits of the local MAC address for Ethernet port 0. */
- uint32_t : 8;
- } MACRU_b;
- };
-
- union
- {
- __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */
-
- struct
- {
- __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
- * bits of the local MAC address for Ethernet port 0. */
- uint32_t : 8;
- } MACRL_b;
- };
-} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */
-
-/**
- * @brief R_GLCDC_BG [BG] (Background Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */
-
- struct
- {
- __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */
- uint32_t : 7;
- __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to
- * internal operations */
- uint32_t : 7;
- __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */
- uint32_t : 15;
- } EN_b;
- };
-
- union
- {
- __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period
- * Register */
-
- struct
- {
- __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period
- * on the basis of pixel clock (PXCLK). */
- uint32_t : 5;
- __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period
- * on the basis of line. */
- uint32_t : 5;
- } PERI_b;
- };
-
- union
- {
- __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position
- * Register */
-
- struct
- {
- __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion
- * position on the basis of pixel clock (PXCLK). */
- uint32_t : 12;
- __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion
- * position on the basis of line. */
- uint32_t : 12;
- } SYNC_b;
- };
-
- union
- {
- __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical
- * Size Register */
-
- struct
- {
- __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis
- * of line */
- uint32_t : 5;
- __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position
- * on the basis of line */
- uint32_t : 5;
- } VSIZE_b;
- };
-
- union
- {
- __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal
- * Size Register */
-
- struct
- {
- __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the
- * basis of pixel clock (PXCLK) Note: When serial RGB is selected
- * as the output format for the output control block, add
- * two to the horizontal enable signal width and set the resulting
- * value to this field. */
- uint32_t : 5;
- __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position
- * on the basis of pixel clock (PXCLK). */
- uint32_t : 5;
- } HSIZE_b;
- };
-
- union
- {
- __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */
-
- struct
- {
- __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned;
- * 8-bit integer */
- __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned;
- * 8-bit integer */
- __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned;
- * 8-bit integer. */
- uint32_t : 8;
- } BGC_b;
- };
-
- union
- {
- __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */
-
- struct
- {
- __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */
- uint32_t : 7;
- __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal
- * monitor. The signal state for controlling reflection of
- * the register values to the internal operations upon assertion
- * of the vertical synchronization signal. */
- uint32_t : 7;
- __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */
- uint32_t : 15;
- } MON_b;
- };
-} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */
-
-/**
- * @brief R_GLCDC_GR [GR] (Layer Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */
-
- struct
- {
- __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection
- * to internal operations. Reflection of the register values
- * to the internal operation at the assertion of the vertical
- * synchronization signal (VS). */
- uint32_t : 31;
- } VEN_b;
- };
-
- union
- {
- __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */
-
- struct
- {
- __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */
- uint32_t : 31;
- } FLMRD_b;
- };
-
- union
- {
- __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */
-
- struct
- {
- __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer
- * data) access */
- uint32_t : 30;
- } FLM1_b;
- };
-
- union
- {
- __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */
-
- struct
- {
- __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer
- * data) Set the head address in the frame buffer where graphics
- * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed
- * to 0 during 64-byte burst transfer. */
- } FLM2_b;
- };
-
- union
- {
- __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data
- * (frame buffer data) Signed; 16-bit integer */
- } FLM3_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */
-
- struct
- {
- __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing
- * graphics data (frame buffer data), where one transfer is
- * defined as 16-beat burst access (64-byte boundary) */
- __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data
- * (frame buffer data). */
- uint32_t : 5;
- } FLM5_b;
- };
-
- union
- {
- __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */
-
- struct
- {
- uint32_t : 28;
- __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer
- * data). */
- uint32_t : 1;
- } FLM6_b;
- };
-
- union
- {
- __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */
-
- struct
- {
- __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */
- uint32_t : 2;
- __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */
- uint32_t : 3;
- __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area
- * alpha blending. */
- uint32_t : 3;
- __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */
- uint32_t : 19;
- } AB1_b;
- };
-
- union
- {
- __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */
-
- struct
- {
- __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */
- uint32_t : 5;
- __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */
- uint32_t : 5;
- } AB2_b;
- };
-
- union
- {
- __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */
-
- struct
- {
- __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */
- uint32_t : 5;
- __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */
- uint32_t : 5;
- } AB3_b;
- };
-
- union
- {
- __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */
-
- struct
- {
- __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image
- * area. */
- uint32_t : 5;
- __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending
- * image area */
- uint32_t : 5;
- } AB4_b;
- };
-
- union
- {
- __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */
-
- struct
- {
- __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending
- * image area. */
- uint32_t : 5;
- __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha
- * blending image area. */
- uint32_t : 5;
- } AB5_b;
- };
-
- union
- {
- __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */
-
- struct
- {
- __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */
- uint32_t : 8;
- __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular
- * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction)
- * [7:0]: Variation (absolute value) */
- uint32_t : 7;
- } AB6_b;
- };
-
- union
- {
- __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */
-
- struct
- {
- __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */
- uint32_t : 15;
- __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular
- * area. */
- uint32_t : 8;
- } AB7_b;
- };
-
- union
- {
- __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */
-
- struct
- {
- __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned;
- * 8 bits. */
- __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned;
- * 8 bits. */
- __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned;
- * 8 bits. */
- uint32_t : 8;
- } AB8_b;
- };
-
- union
- {
- __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */
-
- struct
- {
- __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement
- * Unsigned; 8 bits. */
- __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement
- * Unsigned; 8 bits. */
- __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement
- * Unsigned; 8 bits. */
- __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */
- } AB9_b;
- };
- __IM uint32_t RESERVED1[2];
-
- union
- {
- __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */
-
- struct
- {
- __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */
- __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */
- __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */
- uint32_t : 8;
- } BASE_b;
- };
-
- union
- {
- __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */
-
- struct
- {
- __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */
- uint32_t : 5;
- __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */
- uint32_t : 15;
- } CLUTINT_b;
- };
-
- union
- {
- __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */
-
- struct
- {
- __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */
- uint32_t : 15;
- __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */
- uint32_t : 15;
- } MON_b;
- };
- __IM uint32_t RESERVED2[42];
-} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */
-
-/**
- * @brief R_GLCDC_GAM [GAM] (Gamma Settings)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */
-
- struct
- {
- __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection
- * to internal operations. The register values to be reflected
- * to the internal operations at the assertion of the vertical
- * synchronization signal (VS). */
- uint32_t : 31;
- } LATCH_b;
- };
-
- union
- {
- __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */
-
- struct
- {
- __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */
- uint32_t : 31;
- } GAM_SW_b;
- };
-
- union
- {
- __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */
-
- struct
- {
- __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */
- uint32_t : 5;
- __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */
- uint32_t : 5;
- } LUT_b[8];
- };
-
- union
- {
- __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */
-
- struct
- {
- __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */
- __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */
- __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */
- uint32_t : 2;
- } AREA_b[5];
- };
- __IM uint32_t RESERVED;
-} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */
-
-/**
- * @brief R_GLCDC_OUT [OUT] (Output Control Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control
- * Register */
-
- struct
- {
- __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection
- * to internal operations. The register values to be reflected
- * to the internal operations at the assertion of the vertical
- * synchronization signal (VS). */
- uint32_t : 31;
- } VLATCH_b;
- };
-
- union
- {
- __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */
-
- struct
- {
- __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */
- uint32_t : 2;
- __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */
- uint32_t : 3;
- __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */
- uint32_t : 2;
- __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */
- uint32_t : 10;
- __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */
- uint32_t : 3;
- __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */
- uint32_t : 3;
- } SET_b;
- };
-
- union
- {
- __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register
- * 1 */
-
- struct
- {
- __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits;
- +512 with offset; integer */
- uint32_t : 22;
- } BRIGHT1_b;
- };
-
- union
- {
- __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register
- * 2 */
-
- struct
- {
- __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits;
- +512 with offset; integer */
- uint32_t : 6;
- __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10
- * bits; +512 with offset; integer */
- uint32_t : 6;
- } BRIGHT2_b;
- };
-
- union
- {
- __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */
-
- struct
- {
- __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits
- * fixed point */
- __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits
- * fixed point */
- __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8
- * bits fixed point. */
- uint32_t : 8;
- } CONTRAST_b;
- };
-
- union
- {
- __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction
- * Register */
-
- struct
- {
- __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit
- * integer */
- uint32_t : 2;
- __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit
- * integer */
- uint32_t : 2;
- __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit
- * integer */
- uint32_t : 2;
- __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned
- * 2-bit integer */
- uint32_t : 2;
- __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */
- uint32_t : 2;
- __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */
- uint32_t : 10;
- } PDTHA_b;
- };
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */
-
- struct
- {
- uint32_t : 3;
- __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */
- __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */
- __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */
- __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */
- uint32_t : 1;
- __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */
- uint32_t : 3;
- __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */
- uint32_t : 19;
- } CLKPHASE_b;
- };
-} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */
-
-/**
- * @brief R_GLCDC_TCON [TCON] (Timing Control Registers)
- */
-typedef struct
-{
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */
-
- struct
- {
- __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference
- * timing Sets the offset from the assertion of the internal
- * horizontal synchronization signal in terms of pixels. */
- uint32_t : 5;
- __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing
- * Sets the delay from the assertion of the internal horizontal
- * synchronization signal in terms of pixels. */
- uint32_t : 5;
- } TIM_b;
- };
-
- union
- {
- __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */
-
- struct
- {
- __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion
- * width. */
- uint32_t : 5;
- __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */
- uint32_t : 5;
- } STVA1_b;
- };
-
- union
- {
- __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */
-
- struct
- {
- __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by
- * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
- * register) pin */
- uint32_t : 1;
- __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */
- uint32_t : 27;
- } STVA2_b;
- };
-
- union
- {
- __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */
-
- struct
- {
- __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion
- * width. */
- uint32_t : 5;
- __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */
- uint32_t : 5;
- } STVB1_b;
- };
-
- union
- {
- __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */
-
- struct
- {
- __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by
- * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
- * register) pin */
- uint32_t : 1;
- __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */
- uint32_t : 27;
- } STVB2_b;
- };
-
- union
- {
- __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */
-
- struct
- {
- __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion
- * width. */
- uint32_t : 5;
- __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */
- uint32_t : 5;
- } STHA1_b;
- };
-
- union
- {
- __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */
-
- struct
- {
- __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
- * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
- * register) pin. */
- uint32_t : 1;
- __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */
- uint32_t : 3;
- __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */
- uint32_t : 23;
- } STHA2_b;
- };
-
- union
- {
- __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */
-
- struct
- {
- __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion
- * width. */
- uint32_t : 5;
- __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */
- uint32_t : 5;
- } STHB1_b;
- };
-
- union
- {
- __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */
-
- struct
- {
- __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
- * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
- * register) pin. */
- uint32_t : 1;
- __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */
- uint32_t : 3;
- __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */
- uint32_t : 23;
- } STHB2_b;
- };
-
- union
- {
- __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */
-
- struct
- {
- __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */
- uint32_t : 31;
- } DE_b;
- };
-} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */
-
-/**
- * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control
- * Register */
-
- struct
- {
- __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */
- __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */
- __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */
- uint32_t : 29;
- } DTCTEN_b;
- };
-
- union
- {
- __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable
- * Control Register */
-
- struct
- {
- __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */
- __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */
- __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */
- uint32_t : 29;
- } INTEN_b;
- };
-
- union
- {
- __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */
-
- struct
- {
- __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */
- __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */
- __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */
- uint32_t : 29;
- } STCLR_b;
- };
-
- union
- {
- __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */
-
- struct
- {
- __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */
- __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */
- __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */
- uint32_t : 29;
- } STMON_b;
- };
-
- union
- {
- __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock
- * Control Register */
-
- struct
- {
- __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1
- * for details about setting value. Note: Settings that are
- * not listed in table 2.7.1 are prohibited. */
- __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing
- * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to
- * 0. */
- uint32_t : 1;
- __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */
- uint32_t : 3;
- __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same
- * value as OUT_SET.FRQSEL[1]. */
- uint32_t : 3;
- __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */
- } PANEL_CLK_b;
- };
-} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */
-
-/**
- * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */
-
- struct
- {
- __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */
- uint16_t : 11;
- } A_b;
- };
-
- union
- {
- __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */
-
- struct
- {
- __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */
- uint16_t : 11;
- } B_b;
- };
-} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */
-
- struct
- {
- __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
- * Address = { SVA9,SVA8,SVA[7:0] } */
- } L_b;
- };
-
- union
- {
- __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */
-
- struct
- {
- __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */
- __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */
- __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */
- uint8_t : 5;
- } U_b;
- };
-} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */
-
-/**
- * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */
-
- struct
- {
- __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */
- __IOM uint16_t RP : 1; /*!< [1..1] Read protection */
- __IOM uint16_t WP : 1; /*!< [2..2] Write protection */
- uint16_t : 13;
- } C_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */
-
- struct
- {
- __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE:
- * The low-order 2 bits are fixed to 0. */
- } S_b;
- };
-
- union
- {
- __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */
-
- struct
- {
- __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region
- * end, for use in region determination.NOTE: The low-order
- * 2 bits are fixed to 1. */
- } E_b;
- };
- __IM uint32_t RESERVED1;
-} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */
-
- struct
- {
- __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */
- __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */
- uint16_t : 6;
- __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
- * stored. */
- } CTL_b;
- };
- __IM uint16_t RESERVED;
- __IM uint32_t RESERVED1[63];
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */
-
- struct
- {
- __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
- * stored. */
- } PT_b;
- };
- __IM uint32_t RESERVED3[63];
- __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */
-} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */
-
-/**
- * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */
-
- struct
- {
- uint16_t : 2;
- __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */
- __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */
- __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */
- __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */
- __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */
- __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */
- uint16_t : 4;
- __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */
- __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
- * is read as 1. The write value should be 1.) */
- __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */
- __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */
- } R_b;
- };
- __IM uint16_t RESERVED;
-} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
- * Register */
-
- struct
- {
- __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
- * stored. */
- } OAD_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */
-
- struct
- {
- __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */
- uint16_t : 7;
- __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */
- uint16_t : 7;
- } CTL_b;
- };
-
- union
- {
- __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */
-
- struct
- {
- __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
- * stored. */
- } PT_b;
- };
-
- union
- {
- __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */
-
- struct
- {
- __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
- * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
- * The low-order 2 bits are fixed to 0. */
- } SA_b;
- };
-
- union
- {
- __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */
-
- struct
- {
- __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
- * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
- * The low-order 2 bits are fixed to 1. */
- } EA_b;
- };
-} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3])
- */
-typedef struct
-{
- __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */
- __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */
- __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */
-} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */
-
-/**
- * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */
-
- struct
- {
- __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */
- uint8_t : 3;
- } P_b;
- };
-
- union
- {
- __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */
-
- struct
- {
- __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */
- uint8_t : 3;
- } N_b;
- };
-} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */
-
-/**
- * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
- */
-typedef struct
-{
- union
- {
- union
- {
- __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */
-
- struct
- {
- __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */
- __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */
- __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */
- uint32_t : 1;
- __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */
- __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */
- __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
- uint32_t : 3;
- __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
- __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */
- __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */
- __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */
- __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */
- uint32_t : 7;
- __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
- * function. For individual pin functions, see the MPC table */
- uint32_t : 3;
- } PmnPFS_b;
- };
-
- struct
- {
- union
- {
- struct
- {
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */
-
- struct
- {
- __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */
- __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */
- __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */
- uint16_t : 1;
- __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */
- __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */
- __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
- uint16_t : 3;
- __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
- __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */
- __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */
- __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */
- } PmnPFS_HA_b;
- };
- };
-
- struct
- {
- __IM uint16_t RESERVED1;
- __IM uint8_t RESERVED2;
-
- union
- {
- __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */
-
- struct
- {
- __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */
- __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */
- __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */
- uint8_t : 1;
- __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */
- __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */
- __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
- uint8_t : 1;
- } PmnPFS_BY_b;
- };
- };
- };
- };
- };
-} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief R_PFS_PORT [PORT] (Port [0..14])
- */
-typedef struct
-{
- __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */
-} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */
-
-/**
- * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
- */
-typedef struct
-{
- __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */
-
- #if (2U == BSP_FEATURE_IOPORT_VERSION)
- __IM uint16_t RESERVED;
- #endif
-} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */
-
-/**
- * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
- */
-typedef struct
-{
- union
- {
- __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */
-
- struct
- {
- __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */
- __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */
- uint8_t : 1;
- __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */
- uint8_t : 2;
- } RTCCR_b;
- };
- __IM uint8_t RESERVED;
-} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */
-
-/**
- * @brief R_RTC_CP [CP] (Capture registers)
- */
-typedef struct
-{
- __IM uint8_t RESERVED[2];
-
- union
- {
- union
- {
- __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */
-
- struct
- {
- __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of
- * seconds */
- __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
- * seconds */
- uint8_t : 1;
- } RSEC_b;
- };
-
- union
- {
- __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */
-
- struct
- {
- __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
- * value when a time capture event is detected. */
- } BCNT0_b;
- };
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- union
- {
- __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */
-
- struct
- {
- __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
- * minutes */
- __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
- * minutes */
- uint8_t : 1;
- } RMIN_b;
- };
-
- union
- {
- __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */
-
- struct
- {
- __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
- * value when a time capture event is detected. */
- } BCNT1_b;
- };
- };
- __IM uint8_t RESERVED2;
-
- union
- {
- union
- {
- __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */
-
- struct
- {
- __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
- * minutes */
- __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
- * minutes */
- __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */
- uint8_t : 1;
- } RHR_b;
- };
-
- union
- {
- __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */
-
- struct
- {
- __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
- * value when a time capture event is detected. */
- } BCNT2_b;
- };
- };
- __IM uint8_t RESERVED3[3];
-
- union
- {
- union
- {
- __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */
-
- struct
- {
- __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */
- __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */
- uint8_t : 2;
- } RDAY_b;
- };
-
- union
- {
- __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */
-
- struct
- {
- __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
- * value when a time capture event is detected. */
- } BCNT3_b;
- };
- };
- __IM uint8_t RESERVED4;
-
- union
- {
- __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */
-
- struct
- {
- __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */
- __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of
- * months */
- uint8_t : 3;
- } RMON_b;
- };
- __IM uint8_t RESERVED5[3];
-} R_RTC_CP_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_B_CSa [CSa] (CS Registers)
- */
-typedef struct
-{
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
-
- struct
- {
- __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
- uint16_t : 2;
- __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
- uint16_t : 4;
- __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
- __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
- uint16_t : 5;
- __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
- } MOD_b;
- };
-
- union
- {
- __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
-
- struct
- {
- __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
- * is valid only when the PWENB bit in CSnMOD is set to 1. */
- uint32_t : 5;
- __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
- * is valid only when the PRENB bit in CSnMOD is set to 1. */
- uint32_t : 5;
- __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
- uint32_t : 3;
- __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
- uint32_t : 3;
- } WCR1_b;
- };
-
- union
- {
- __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
-
- struct
- {
- __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
- uint32_t : 1;
- __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
- uint32_t : 2;
- __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
- uint32_t : 1;
- __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
- uint32_t : 1;
- __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
- uint32_t : 1;
- __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
- uint32_t : 1;
- } WCR2_b;
- };
- __IM uint32_t RESERVED1;
-} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_B_CSb [CSb] (CS Registers)
- */
-typedef struct
-{
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
-
- struct
- {
- __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
- uint16_t : 3;
- __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
- uint16_t : 2;
- __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
- uint16_t : 3;
- __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
- uint16_t : 3;
- } CR_b;
- };
- __IM uint16_t RESERVED1[3];
-
- union
- {
- __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
-
- struct
- {
- __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
- uint16_t : 4;
- __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
- uint16_t : 4;
- } REC_b;
- };
- __IM uint16_t RESERVED2[2];
-} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
-
- struct
- {
- __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
- * an error address. */
- } ADD_b;
- };
-
- union
- {
- __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */
-
- struct
- {
- __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */
- uint8_t : 7;
- } ERRRW_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[2];
-} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers)
- */
-typedef struct
-{
- union
- {
- __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */
-
- struct
- {
- __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs,
- * It stores an error address. */
- } TZFADD_b;
- };
-
- union
- {
- __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */
-
- struct
- {
- __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the
- * time of the error */
- uint8_t : 7;
- } TZFERRRW_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[2];
-} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */
-
-/**
- * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */
- __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */
- uint16_t : 6;
- } E_b;
- };
-
- union
- {
- __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */
-
- struct
- {
- __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */
- } N_b;
- };
-} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
-
-/**
- * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
- */
-typedef struct
-{
- union
- {
- __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */
- __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */
- } E_b;
- };
-
- union
- {
- __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */
-
- struct
- {
- __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */
- } N_b;
- };
-} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
-
-/** @} */ /* End of group Device_Peripheral_clusters */
-
-/* =========================================================================================================================== */
-/* ================ Device Specific Peripheral Section ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
-
-/* =========================================================================================================================== */
-/* ================ R_ACMPHS0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief High-Speed Analog Comparator (R_ACMPHS0)
- */
-
-typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */
-{
- union
- {
- __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */
-
- struct
- {
- __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */
- __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */
- __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */
- __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */
- __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */
- __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */
- } CMPCTL_b;
- };
- __IM uint8_t RESERVED[3];
-
- union
- {
- __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */
-
- struct
- {
- __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */
- uint8_t : 4;
- } CMPSEL0_b;
- };
- __IM uint8_t RESERVED1[3];
-
- union
- {
- __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */
-
- struct
- {
- __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */
- uint8_t : 2;
- } CMPSEL1_b;
- };
- __IM uint8_t RESERVED2[3];
-
- union
- {
- __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */
-
- struct
- {
- __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */
- uint8_t : 7;
- } CMPMON_b;
- };
- __IM uint8_t RESERVED3[3];
-
- union
- {
- __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */
-
- struct
- {
- __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */
- uint8_t : 6;
- __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */
- } CPIOC_b;
- };
-} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */
-
-/* =========================================================================================================================== */
-/* ================ R_ACMPLP ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Low-Power Analog Comparator (R_ACMPLP)
- */
-
-typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */
-{
- union
- {
- __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */
-
- struct
- {
- __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */
- __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */
- __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */
- __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */
- __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */
- __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */
- __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */
- __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */
- } COMPMDR_b;
- };
-
- union
- {
- __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */
-
- struct
- {
- __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */
- __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */
- __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */
- __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */
- __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */
- __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */
- } COMPFIR_b;
- };
-
- union
- {
- __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */
-
- struct
- {
- uint8_t : 1;
- __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */
- __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */
- uint8_t : 2;
- __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */
- __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */
- __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */
- } COMPOCR_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */
-
- struct
- {
- __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */
- uint8_t : 1;
- __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */
- uint8_t : 1;
- } COMPSEL0_b;
- };
-
- union
- {
- __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */
-
- struct
- {
- __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */
- uint8_t : 1;
- __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */
- __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */
- } COMPSEL1_b;
- };
-} R_ACMPLP_Type; /*!< Size = 6 (0x6) */
-
-/* =========================================================================================================================== */
-/* ================ R_ADC0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief A/D Converter (R_ADC0)
- */
-
-typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */
-{
- union
- {
- __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */
-
- struct
- {
- __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
- * input channel for double triggered operation. The setting
- * is only effective while double trigger mode is selected. */
- uint16_t : 1;
- __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */
- __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */
- __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */
- __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */
- __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */
- uint16_t : 1;
- __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */
- __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */
- __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */
- } ADCSR_b;
- };
-
- union
- {
- __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */
-
- struct
- {
- __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
- * "1" while scanning. */
- uint8_t : 6;
- __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */
- } ADREF_b;
- };
-
- union
- {
- __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */
-
- struct
- {
- __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */
- uint8_t : 7;
- } ADEXREF_b;
- };
-
- union
- {
- __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */
-
- struct
- {
- __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */
- __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */
- __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */
- __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */
- __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */
- __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */
- __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */
- __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */
- __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */
- __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */
- __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */
- __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */
- __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */
- __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */
- __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */
- __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */
- } ADANSA_b[2];
- };
-
- union
- {
- __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
- * Select Register */
-
- struct
- {
- __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */
- __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */
- } ADADS_b[2];
- };
-
- union
- {
- __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
- * Register */
-
- struct
- {
- __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
- * at the only setting of ADC[2:0] bits = 001b or 011b. When
- * average mode is selected by setting the ADADC.AVEE bit
- * to 1, do not set the addition count to three times (ADADC.ADC[2:0]
- * = 010b) */
- uint8_t : 4;
- __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
- * by setting the ADADC.AVEE bit to 0, set the addition count
- * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
- * can only be used with 12-bit accuracy selected. NOTE: AVEE
- * bit is valid at the only setting of ADC[2:0] bits = 001b
- * or 011b. When average mode is selected by setting the ADADC.AVEE
- * bit to 1, do not set the addition count to three times
- * (ADADC.ADC[2:0] = 010b) */
- } ADADC_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */
-
- struct
- {
- uint16_t : 1;
- __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */
- uint16_t : 1;
- __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */
- __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */
- uint16_t : 2;
- __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */
- __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */
- __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */
- uint16_t : 2;
- __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */
- __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */
- } ADCER_b;
- };
-
- union
- {
- __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */
-
- struct
- {
- __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
- * the A/D conversion start trigger for group B in group scan
- * mode. */
- uint16_t : 2;
- __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
- * start trigger in single scan mode and continuous mode.
- * In group scan mode, the A/D conversion start trigger for
- * group A is selected. */
- uint16_t : 2;
- } ADSTRGR_b;
- };
-
- union
- {
- __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */
-
- struct
- {
- __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
- * Mode Select */
- __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
- * Mode Select */
- uint16_t : 6;
- __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */
- __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */
- __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
- * Group B in group scan mode. */
- __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
- * Group B in group scan mode. */
- uint16_t : 2;
- __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */
- __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */
- } ADEXICR_b;
- };
-
- union
- {
- __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */
-
- struct
- {
- __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */
- __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */
- __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */
- __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */
- __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */
- __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */
- __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */
- __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */
- __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */
- __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */
- __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */
- __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */
- __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */
- __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */
- __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */
- __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */
- } ADANSB_b[2];
- };
-
- union
- {
- __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */
-
- struct
- {
- __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
- * result of A/D conversion in response to the second trigger
- * in double trigger mode. */
- } ADDBLDR_b;
- };
-
- union
- {
- __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */
-
- struct
- {
- __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
- * A/D conversion result of temperature sensor output. */
- } ADTSDR_b;
- };
-
- union
- {
- __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */
-
- struct
- {
- __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
- * A/D result of internal reference voltage. */
- } ADOCDR_b;
- };
-
- union
- {
- union
- {
- __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */
-
- struct
- {
- __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for
- * data determine ADCER.ADRFMT and ADCER.ADPRC. */
- __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */
- } ADRD_RIGHT_b;
- };
-
- union
- {
- __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */
-
- struct
- {
- __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
- __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
- * data determine ADCER.ADRFMT and ADCER.ADPRC. */
- } ADRD_LEFT_b;
- };
- };
-
- union
- {
- __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */
-
- struct
- {
- __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for
- * storing the result of A/D conversion. */
- } ADDR_b[28];
- };
- __IM uint16_t RESERVED1[5];
-
- union
- {
- __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */
-
- struct
- {
- __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */
- } ADAMPOFF_b;
- };
-
- union
- {
- __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */
-
- struct
- {
- __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */
- __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */
- uint8_t : 6;
- } ADTSTPR_b;
- };
-
- union
- {
- __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */
-
- struct
- {
- __IOM uint16_t WRION : 5; /*!< [4..0] WRION */
- uint16_t : 3;
- __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */
- uint16_t : 2;
- __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */
- } ADDDACER_b;
- };
-
- union
- {
- __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */
-
- struct
- {
- __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
- * Setting Set the sampling time (4 to 255 states) */
- __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */
- __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */
- __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */
- uint16_t : 5;
- } ADSHCR_b;
- };
-
- union
- {
- __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */
-
- struct
- {
- __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
- * only for channel. */
- uint16_t : 1;
- __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */
- uint16_t : 2;
- __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
- * for adjustment to hardening of process. */
- uint16_t : 1;
- __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
- * power save bit for A/D hard macro to hardening of process. */
- __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
- * bit for A/D hard macro to hardening of process. */
- __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
- * bit for A/D hard macro to hardening of process. */
- } ADEXTSTR_b;
- };
-
- union
- {
- __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */
-
- struct
- {
- __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */
- __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
- * amplifier test.Refreshing the pressure switch that opens
- * for the DAC output voltage charge period when the amplifier
- * of the S&H circuit is tested only for the channel is set. */
- uint16_t : 1;
- __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control
- * bit. */
- __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control
- * bit */
- uint16_t : 1;
- __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
- * module Details are described to the bit explanation. */
- __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
- * bit explanation. */
- } ADTSTRA_b;
- };
-
- union
- {
- __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */
-
- struct
- {
- __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
- * corresponds to ADVAL 14:0 input of A/D analog module. */
- uint16_t : 1;
- } ADTSTRB_b;
- };
-
- union
- {
- __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */
-
- struct
- {
- __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
- * analog module. */
- uint16_t : 4;
- __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */
- uint16_t : 3;
- } ADTSTRC_b;
- };
-
- union
- {
- __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */
-
- struct
- {
- __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
- * corresponds to ADVAL 16 input of A/D analog module. */
- uint16_t : 15;
- } ADTSTRD_b;
- };
-
- union
- {
- __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */
-
- struct
- {
- __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */
- __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */
- __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */
- __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */
- __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */
- __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */
- uint16_t : 10;
- } ADSWTSTR0_b;
- };
-
- union
- {
- __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */
-
- struct
- {
- __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */
- __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */
- __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */
- __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */
- __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */
- __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */
- uint16_t : 10;
- } ADSWTSTR1_b;
- };
-
- union
- {
- __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */
-
- struct
- {
- __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit
- * (ANEX0 switch) */
- __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit
- * (ANEX1 switch). */
- uint16_t : 2;
- __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */
- __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */
- __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */
- uint16_t : 1;
- __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */
- __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */
- __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */
- __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */
- __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */
- uint16_t : 3;
- } ADSWTSTR2_b;
- };
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */
-
- struct
- {
- __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */
- __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */
- uint8_t : 3;
- } ADDISCR_b;
- };
-
- union
- {
- __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */
-
- struct
- {
- __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
- * the pressure switch in A/D analog module is set. */
- uint8_t : 1;
- __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */
- uint8_t : 1;
- } ADSWCR_b;
- };
-
- union
- {
- __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */
-
- struct
- {
- __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
- * Select */
- uint8_t : 7;
- } ADSHMSR_b;
- };
-
- union
- {
- __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */
-
- struct
- {
- __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */
- uint8_t : 6;
- } ADICR_b;
- };
-
- union
- {
- __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */
-
- struct
- {
- uint8_t : 1;
- __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */
- uint8_t : 6;
- } ADACSR_b;
- };
- __IM uint8_t RESERVED3;
-
- union
- {
- __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */
-
- struct
- {
- __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS
- * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
- * set to 01b (group scan mode). If the bits are set to any
- * other values, proper operation is not guaranteed. */
- __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
- * when PGS = 0.) */
- uint16_t : 6;
- __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */
- uint16_t : 6;
- __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
- * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
- * has been set to 1, single scan is performed continuously
- * for group B regardless of the setting of the GBRSCN bit. */
- } ADGSPCR_b;
- };
-
- union
- {
- __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
- * Scan) */
-
- struct
- {
- __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */
- __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */
- } ADGSCS_b;
- };
-
- union
- {
- __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */
-
- struct
- {
- __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
- * the result of A/D conversion in response to the respective
- * triggers during extended operation in double trigger mode. */
- } ADDBLDRA_b;
- };
-
- union
- {
- __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */
-
- struct
- {
- __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
- * the result of A/D conversion in response to the respective
- * triggers during extended operation in double trigger mode. */
- } ADDBLDRB_b;
- };
-
- union
- {
- __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */
- } ADSER_b;
- };
- __IM uint8_t RESERVED4;
-
- union
- {
- __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
- * Control Register */
-
- struct
- {
- __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */
- uint8_t : 2;
- __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */
- uint8_t : 2;
- __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
- } ADHVREFCNT_b;
- };
- __IM uint8_t RESERVED5;
-
- union
- {
- __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
- * Register */
-
- struct
- {
- __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination
- * result.This bit is valid when both window A operation and
- * window B operation are enabled. */
- uint8_t : 3;
- __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */
- __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */
- uint8_t : 2;
- } ADWINMON_b;
- };
- __IM uint8_t RESERVED6;
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */
-
- struct
- {
- __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
- * are valid when both window A and window B are enabled (CMPAE
- * = 1 and CMPBE = 1). */
- uint16_t : 7;
- __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */
- uint16_t : 1;
- __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */
- uint16_t : 1;
- __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */
- __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */
- __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */
- } ADCMPCR_b;
- };
-
- union
- {
- __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
- * Select Register */
-
- struct
- {
- __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */
- __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */
- uint8_t : 6;
- } ADCMPANSER_b;
- };
-
- union
- {
- __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
- * Comparison Condition Setting Register */
-
- struct
- {
- __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
- * Condition Select */
- __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
- * Select */
- uint8_t : 6;
- } ADCMPLER_b;
- };
-
- union
- {
- __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
- * Register */
-
- struct
- {
- __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */
- __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */
- __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */
- __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */
- __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */
- __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */
- __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */
- __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */
- __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */
- __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */
- __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */
- __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */
- __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */
- __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */
- __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */
- __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */
- } ADCMPANSR_b[2];
- };
-
- union
- {
- __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
- * Setting Register */
-
- struct
- {
- __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */
- __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */
- __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */
- __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */
- __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */
- __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */
- __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */
- __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */
- __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */
- __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */
- __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */
- __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */
- __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */
- __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */
- __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */
- __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */
- } ADCMPLR_b[2];
- };
-
- union
- {
- __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
- * Setting Register */
-
- struct
- {
- __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
- * compare window A function is used. ADCMPDR0 sets the lower-side
- * level of window A. */
- } ADCMPDR0_b;
- };
-
- union
- {
- __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
- * Setting Register */
-
- struct
- {
- __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
- * compare window A function is used. ADCMPDR1 sets the upper-side
- * level of window A.. */
- } ADCMPDR1_b;
- };
-
- union
- {
- __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
- * Register */
-
- struct
- {
- __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */
- __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */
- } ADCMPSR_b[2];
- };
-
- union
- {
- __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
- * Channel Status Register */
-
- struct
- {
- __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
- * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
- * this bit indicates the temperature sensor output comparison
- * result. When window A operation is disabled (ADCMPCR.CMPAE
- * = 0b), comparison conditions for CMPSTTSA are not met any
- * time. */
- __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
- * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
- * this bit indicates the temperature sensor output comparison
- * result. When window A operation is disabled (ADCMPCR.CMPAE
- * = 0b), comparison conditions for CMPSTTSA are not met any
- * time. */
- uint8_t : 6;
- } ADCMPSER_b;
- };
- __IM uint8_t RESERVED8;
-
- union
- {
- __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
- * Register */
-
- struct
- {
- __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that
- * compares it on the condition of compare window B is selected. */
- uint8_t : 1;
- __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */
- } ADCMPBNSR_b;
- };
- __IM uint8_t RESERVED9;
-
- union
- {
- __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
- * Setting Register */
-
- struct
- {
- __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
- * used to set the lower level of the window B. */
- } ADWINLLB_b;
- };
-
- union
- {
- __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
- * Setting Register */
-
- struct
- {
- __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
- * used to set the higher level of the window B. */
- } ADWINULB_b;
- };
-
- union
- {
- __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */
-
- struct
- {
- __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows
- * the comparative result of CH (AN000-AN027, temperature
- * sensor, and internal reference voltage) made the object
- * of window B relation condition. */
- uint8_t : 7;
- } ADCMPBSR_b;
- };
- __IM uint8_t RESERVED10;
- __IM uint16_t RESERVED11;
-
- union
- {
- __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF0_b;
- };
-
- union
- {
- __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF1_b;
- };
-
- union
- {
- __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF2_b;
- };
-
- union
- {
- __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF3_b;
- };
-
- union
- {
- __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF4_b;
- };
-
- union
- {
- __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF5_b;
- };
-
- union
- {
- __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF6_b;
- };
-
- union
- {
- __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF7_b;
- };
-
- union
- {
- __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF8_b;
- };
-
- union
- {
- __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF9_b;
- };
-
- union
- {
- __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF10_b;
- };
-
- union
- {
- __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF11_b;
- };
-
- union
- {
- __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF12_b;
- };
-
- union
- {
- __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF13_b;
- };
-
- union
- {
- __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF14_b;
- };
-
- union
- {
- __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */
-
- struct
- {
- __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
- * registers that sequentially store all A/D converted values.
- * The automatic clear function is not applied to these registers. */
- } ADBUF15_b;
- };
-
- union
- {
- __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */
-
- struct
- {
- __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */
- uint8_t : 7;
- } ADBUFEN_b;
- };
- __IM uint8_t RESERVED12;
-
- union
- {
- __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */
-
- struct
- {
- __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of
- * data buffer to which the next A/D converted data is transferred. */
- __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */
- uint8_t : 3;
- } ADBUFPTR_b;
- };
- __IM uint8_t RESERVED13;
- __IM uint16_t RESERVED14[4];
- __IM uint8_t RESERVED15;
-
- union
- {
- __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */
-
- struct
- {
- __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */
- } ADSSTRL_b;
- };
-
- union
- {
- __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */
-
- struct
- {
- __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */
- } ADSSTRT_b;
- };
-
- union
- {
- __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */
-
- struct
- {
- __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */
- } ADSSTRO_b;
- };
-
- union
- {
- __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */
-
- struct
- {
- __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */
- } ADSSTR_b[16];
- };
-
- union
- {
- __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */
-
- struct
- {
- __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */
- __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */
- __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */
- __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */
- uint16_t : 12;
- } ADANIM_b;
- };
-
- union
- {
- __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */
-
- struct
- {
- uint8_t : 6;
- __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */
- __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */
- } ADCALEXE_b;
- };
- __IM uint8_t RESERVED16;
-
- union
- {
- __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
- * Register */
-
- struct
- {
- __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */
- __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */
- __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */
- __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */
- uint8_t : 2;
- __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
- } VREFAMPCNT_b;
- };
- __IM uint8_t RESERVED17;
- __IM uint16_t RESERVED18;
-
- union
- {
- __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */
-
- struct
- {
- __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */
- } ADRD_b;
- };
-
- union
- {
- __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */
-
- struct
- {
- __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
- uint8_t : 6;
- } ADRST_b;
- };
- __IM uint8_t RESERVED19;
- __IM uint16_t RESERVED20[82];
-
- union
- {
- __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */
-
- struct
- {
- __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */
- __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */
- __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */
- __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */
- __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */
- __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */
- __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */
- __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */
- __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */
- __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */
- __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */
- __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */
- __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */
- __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */
- __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */
- __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */
- } ADPGACR_b;
- };
-
- union
- {
- __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
- * Register 0 */
-
- struct
- {
- __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
- * b) when the shingle end is input and each PGA P000 is set.
- * When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
- * sets the gain magnification when the differential motion
- * is input by the combination with ADPGSDCR0.P000DG 1:0. */
- __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
- * b) when the shingle end is input and each PGA P001 is set.
- * When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
- * sets the gain magnification when the differential motion
- * is input by the combination with ADPGSDCR0.P001DG 1:0. */
- __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
- * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
- * each PGA P002 is set. When the differential motion is input,
- * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
- * the differential motion is input by the combination with
- * ADPGSDCR0.P002DG 1:0. */
- __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
- * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
- * each PGA P003 is set. When the differential motion is input,
- * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
- * the differential motion is input by the combination with
- * ADPGSDCR0.P003DG 1:0. */
- } ADPGAGS0_b;
- };
- __IM uint16_t RESERVED21[6];
-
- union
- {
- __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
- * Input Control Register */
-
- struct
- {
- __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
- * bits are used, set {P000DEN, P000GEN} to 11b. */
- uint16_t : 1;
- __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */
- __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
- * bits are used, set {P001DEN, P001GEN} to 11b. */
- uint16_t : 1;
- __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */
- __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
- * bits are used, set {P002DEN, P002GEN} to 11b. */
- uint16_t : 1;
- __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */
- __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
- * bits are used, set {P003DEN, P003GEN} to 11b. */
- uint16_t : 1;
- __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */
- } ADPGADCR0_b;
- };
- __IM uint16_t RESERVED22;
-
- union
- {
- __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
- * Input Bias Select Register 0 */
-
- struct
- {
- __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
- * SelectNOTE: This bit selects the input bias voltage value
- * when differential inputs are used. */
- uint8_t : 7;
- } ADPGADBS0_b;
- };
-
- union
- {
- __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
- * Input Bias Select Register 1 */
-
- struct
- {
- __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
- * This bit selects the input bias voltage value when differential
- * inputs are used. */
- uint8_t : 7;
- } ADPGADBS1_b;
- };
- __IM uint16_t RESERVED23[21];
-
- union
- {
- __IOM uint8_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */
-
- struct
- {
- __IOM uint8_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */
- uint8_t : 5;
- } ADREFMON_b;
- };
- __IM uint8_t RESERVED24;
- __IM uint16_t RESERVED25;
-} R_ADC0_Type; /*!< Size = 484 (0x1e4) */
-
-/* =========================================================================================================================== */
-/* ================ R_PSCU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Peripheral Security Control Unit (R_PSCU)
- */
-
-typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */
-{
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */
-
- struct
- {
- uint32_t : 1;
- __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */
- __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */
- __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */
- uint32_t : 2;
- __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */
- __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */
- __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */
- __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */
- uint32_t : 1;
- __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */
- __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */
- uint32_t : 2;
- __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
- * bit security attribution */
- __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */
- uint32_t : 1;
- __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */
- __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */
- uint32_t : 2;
- __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */
- __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */
- __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */
- __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */
- __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */
- __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */
- __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */
- __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */
- __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */
- __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */
- } PSARB_b;
- };
-
- union
- {
- __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */
-
- struct
- {
- __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */
- __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */
- uint32_t : 1;
- __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */
- uint32_t : 4;
- __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */
- uint32_t : 3;
- __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */
- __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */
- uint32_t : 6;
- __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */
- uint32_t : 6;
- __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */
- uint32_t : 3;
- __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */
- } PSARC_b;
- };
-
- union
- {
- __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */
-
- struct
- {
- __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */
- __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */
- __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */
- __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */
- uint32_t : 7;
- __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */
- __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */
- __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */
- __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */
- __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */
- __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */
- uint32_t : 2;
- __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */
- __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */
- uint32_t : 1;
- __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */
- uint32_t : 2;
- __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */
- __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */
- __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */
- __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */
- uint32_t : 3;
- } PSARD_b;
- };
-
- union
- {
- __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */
-
- struct
- {
- __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */
- __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */
- __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */
- uint32_t : 11;
- __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */
- __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */
- uint32_t : 6;
- __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */
- __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */
- __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */
- __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */
- __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */
- __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */
- __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */
- __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */
- __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */
- __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */
- } PSARE_b;
- };
-
- union
- {
- __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */
-
- struct
- {
- __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */
- __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */
- __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */
- __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */
- uint32_t : 28;
- } MSSAR_b;
- };
-
- union
- {
- __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
- * A */
-
- struct
- {
- uint32_t : 15;
- __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */
- uint32_t : 8;
- } CFSAMONA_b;
- };
-
- union
- {
- __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
- * B */
-
- struct
- {
- uint32_t : 10;
- __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */
- uint32_t : 8;
- } CFSAMONB_b;
- };
-
- union
- {
- __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */
-
- struct
- {
- uint32_t : 10;
- __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */
- uint32_t : 16;
- } DFSAMON_b;
- };
-
- union
- {
- __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */
-
- struct
- {
- uint32_t : 13;
- __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */
- uint32_t : 11;
- } SSAMONA_b;
- };
-
- union
- {
- __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */
-
- struct
- {
- uint32_t : 10;
- __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */
- uint32_t : 11;
- } SSAMONB_b;
- };
-
- union
- {
- __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */
-
- struct
- {
- __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */
- uint32_t : 28;
- } DLMMON_b;
- };
-} R_PSCU_Type; /*!< Size = 48 (0x30) */
-
-/* =========================================================================================================================== */
-/* ================ R_AGT0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */
-{
- union
- {
- __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */
-
- struct
- {
- __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
- * to the TSTOP bit in the AGTCRn register, the 16-bit counter
- * is forcibly stopped and set to FFFFH. */
- } AGT_b;
- };
-
- union
- {
- __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */
-
- struct
- {
- __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
- * written to the TSTOP bit in the AGTCRn register, set to
- * FFFFH */
- } AGTCMA_b;
- };
-
- union
- {
- __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */
-
- struct
- {
- __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
- * written to the TSTOP bit in the AGTCR register, set to
- * FFFFH */
- } AGTCMB_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */
-
- struct
- {
- __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */
- __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */
- __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */
- uint8_t : 1;
- __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */
- __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */
- __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */
- __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */
- } AGTCR_b;
- };
-
- union
- {
- __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */
-
- struct
- {
- __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */
- __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */
- __IOM uint8_t TCK : 3; /*!< [6..4] Count source */
- uint8_t : 1;
- } AGTMR1_b;
- };
-
- union
- {
- __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */
-
- struct
- {
- __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
- * ratio */
- uint8_t : 4;
- __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */
- } AGTMR2_b;
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */
-
- struct
- {
- __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
- * mode. */
- uint8_t : 1;
- __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */
- uint8_t : 1;
- __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */
- __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */
- } AGTIOC_b;
- };
-
- union
- {
- __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */
-
- struct
- {
- uint8_t : 2;
- __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */
- uint8_t : 5;
- } AGTISR_b;
- };
-
- union
- {
- __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */
-
- struct
- {
- __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
- __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */
- __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */
- uint8_t : 1;
- __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
- __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */
- __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */
- uint8_t : 1;
- } AGTCMSR_b;
- };
-
- union
- {
- __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */
-
- struct
- {
- __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */
- uint8_t : 2;
- __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
- uint8_t : 3;
- } AGTIOSEL_b;
- };
-} R_AGT0_Type; /*!< Size = 16 (0x10) */
-
-/* =========================================================================================================================== */
-/* ================ R_AGTW0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGTW0)
- */
-
- #ifndef BSP_OVERRIDE_REG_R_AGTW0_TYPE
-
-typedef struct /*!< (@ 0x40084000) R_AGTW0 Structure */
-{
- union
- {
- __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */
-
- struct
- {
- __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
- * to the TSTOP bit in the AGTCRn register, the 16-bit counter
- * is forcibly stopped and set to FFFFH. */
- } AGT_b;
- };
-
- union
- {
- __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */
-
- struct
- {
- __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
- * written to the TSTOP bit in the AGTCRn register, set to
- * FFFFH */
- } AGTCMA_b;
- };
-
- union
- {
- __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */
-
- struct
- {
- __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
- * written to the TSTOP bit in the AGTCR register, set to
- * FFFFH */
- } AGTCMB_b;
- };
-
- union
- {
- __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */
-
- struct
- {
- __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */
- __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */
- __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */
- uint8_t : 1;
- __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */
- __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */
- __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */
- __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */
- } AGTCR_b;
- };
-
- union
- {
- __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */
-
- struct
- {
- __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */
- __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */
- __IOM uint8_t TCK : 3; /*!< [6..4] Count source */
- uint8_t : 1;
- } AGTMR1_b;
- };
-
- union
- {
- __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */
-
- struct
- {
- __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
- * ratio */
- uint8_t : 4;
- __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */
- } AGTMR2_b;
- };
-
- union
- {
- __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
- uint8_t : 3;
- } AGTIOSEL_b;
- };
-
- union
- {
- __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */
-
- struct
- {
- __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
- * mode. */
- uint8_t : 1;
- __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */
- uint8_t : 1;
- __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */
- __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */
- } AGTIOC_b;
- };
-
- union
- {
- __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */
-
- struct
- {
- uint8_t : 2;
- __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */
- uint8_t : 5;
- } AGTISR_b;
- };
-
- union
- {
- __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */
-
- struct
- {
- __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
- __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */
- __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */
- uint8_t : 1;
- __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
- __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */
- __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */
- uint8_t : 1;
- } AGTCMSR_b;
- };
- __IM uint8_t RESERVED;
-} R_AGTW0_Type; /*!< Size = 20 (0x14) */
-
- #endif
-
-/* =========================================================================================================================== */
-/* ================ R_BUS ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Bus Interface (R_BUS)
- */
-
-typedef struct /*!< (@ 0x40003000) R_BUS Structure */
-{
- __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
- __IM uint32_t RESERVED[480];
- __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
-
- union
- {
- __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
-
- struct
- {
- __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
- } CSRECEN_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[223];
- __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */
- __IM uint32_t RESERVED3[235];
- __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */
- __IM uint32_t RESERVED4[58];
- __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */
- __IM uint32_t RESERVED5[432];
- __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */
-} R_BUS_Type; /*!< Size = 6320 (0x18b0) */
-
-/* =========================================================================================================================== */
-/* ================ R_CAC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
- */
-
-typedef struct /*!< (@ 0x40044600) R_CAC Structure */
-{
- union
- {
- __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */
-
- struct
- {
- __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */
- uint8_t : 7;
- } CACR0_b;
- };
-
- union
- {
- __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */
-
- struct
- {
- __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */
- __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */
- __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */
- __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */
- } CACR1_b;
- };
-
- union
- {
- __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */
-
- struct
- {
- __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */
- __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */
- __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
- * Select */
- __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */
- } CACR2_b;
- };
-
- union
- {
- __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */
-
- struct
- {
- __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */
- __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */
- __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */
- uint8_t : 1;
- __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */
- __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */
- __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */
- uint8_t : 1;
- } CAICR_b;
- };
-
- union
- {
- __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */
-
- struct
- {
- __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */
- __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */
- __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */
- uint8_t : 5;
- } CASTR_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */
-
- struct
- {
- __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
- * the upper-limit value of the frequency. */
- } CAULVR_b;
- };
-
- union
- {
- __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */
-
- struct
- {
- __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
- * the lower-limit value of the frequency. */
- } CALLVR_b;
- };
-
- union
- {
- __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */
-
- struct
- {
- __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
- * the counter value at the time a valid reference signal
- * edge is input */
- } CACNTBR_b;
- };
-} R_CAC_Type; /*!< Size = 12 (0xc) */
-
-/* =========================================================================================================================== */
-/* ================ R_CAN0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Controller Area Network (CAN) Module (R_CAN0)
- */
-
-typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */
-{
- __IM uint32_t RESERVED[128];
- __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */
-
- union
- {
- __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */
-
- struct
- {
- __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */
- __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */
- uint32_t : 3;
- } MKR_b[8];
- };
-
- union
- {
- __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */
-
- struct
- {
- __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */
- __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */
- uint32_t : 1;
- __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */
- __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */
- } FIDCR_b[2];
- };
-
- union
- {
- __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */
-
- struct
- {
- __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */
- __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */
- __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */
- __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */
- __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */
- __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */
- __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */
- __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */
- __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */
- __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */
- __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */
- __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */
- __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */
- __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */
- __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */
- __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */
- __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */
- __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */
- __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */
- __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */
- __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */
- __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */
- __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */
- __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */
- __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */
- __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */
- __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */
- __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */
- __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */
- __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */
- __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */
- __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */
- } MKIVLR_b;
- };
-
- union
- {
- union
- {
- __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */
- __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */
- __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */
- __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */
- __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */
- __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */
- __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */
- __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */
- __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */
- __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */
- __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */
- __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */
- __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */
- __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */
- __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */
- __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */
- __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */
- __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */
- __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */
- __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */
- __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */
- __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */
- __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */
- __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */
- __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */
- __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */
- __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */
- __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */
- __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */
- __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */
- __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */
- __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */
- } MIER_b;
- };
-
- union
- {
- __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox
- * Mode */
-
- struct
- {
- __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */
- __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */
- __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */
- __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */
- __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */
- __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */
- __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */
- __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */
- __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */
- __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */
- __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */
- __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */
- __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */
- __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */
- __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */
- __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */
- __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */
- __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */
- __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */
- __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */
- __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */
- __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */
- __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */
- __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */
- __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */
- __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */
- uint32_t : 2;
- __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */
- __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */
- uint32_t : 2;
- } MIER_FIFO_b;
- };
- };
- __IM uint32_t RESERVED1[252];
-
- union
- {
- union
- {
- __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */
-
- struct
- {
- __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */
- __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox
- * setting enabled) */
- __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting
- * enabled) */
- uint8_t : 1;
- __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */
- uint8_t : 1;
- __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */
- __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */
- } MCTL_TX_b[32];
- };
-
- union
- {
- __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */
-
- struct
- {
- __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */
- __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting
- * enabled) */
- __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */
- uint8_t : 1;
- __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */
- uint8_t : 1;
- __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */
- __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */
- } MCTL_RX_b[32];
- };
- };
-
- union
- {
- __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */
-
- struct
- {
- __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */
- __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */
- __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */
- __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */
- __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */
- __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */
- __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */
- __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */
- __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */
- __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */
- uint16_t : 2;
- } CTLR_b;
- };
-
- union
- {
- __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */
-
- struct
- {
- __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */
- __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */
- __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */
- __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */
- __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */
- __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */
- __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */
- __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */
- __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */
- __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */
- __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */
- __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */
- __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */
- __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */
- __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */
- uint16_t : 1;
- } STR_b;
- };
-
- union
- {
- __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */
-
- struct
- {
- __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */
- uint32_t : 7;
- __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */
- uint32_t : 1;
- __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */
- uint32_t : 2;
- __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the
- * frequency of the CAN communication clock (fCANCLK). */
- uint32_t : 2;
- __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */
- } BCR_b;
- };
-
- union
- {
- __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */
-
- struct
- {
- __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */
- __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */
- __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */
- __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */
- __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */
- __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */
- } RFCR_b;
- };
-
- union
- {
- __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */
-
- struct
- {
- __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented
- * by writing FFh to RFPCR. */
- } RFPCR_b;
- };
-
- union
- {
- __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */
-
- struct
- {
- __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */
- __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */
- uint8_t : 2;
- __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */
- __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */
- } TFCR_b;
- };
-
- union
- {
- __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */
-
- struct
- {
- __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented
- * by writing FFh to TFPCR. */
- } TFPCR_b;
- };
-
- union
- {
- __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */
-
- struct
- {
- __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */
- __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */
- __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */
- __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */
- __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */
- __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */
- __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */
- __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */
- } EIER_b;
- };
-
- union
- {
- __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */
-
- struct
- {
- __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */
- __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */
- __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */
- __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */
- __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */
- __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */
- __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */
- __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */
- } EIFR_b;
- };
-
- union
- {
- __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */
-
- struct
- {
- __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements
- * the counter value according to the error status of the
- * CAN module during reception. */
- } RECR_b;
- };
-
- union
- {
- __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */
-
- struct
- {
- __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements
- * the counter value according to the error status of the
- * CAN module during transmission. */
- } TECR_b;
- };
-
- union
- {
- __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */
-
- struct
- {
- __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */
- __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */
- __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */
- __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */
- __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */
- __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */
- __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */
- __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */
- } ECSR_b;
- };
-
- union
- {
- __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */
-
- struct
- {
- __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel
- * number is output to MSSR. */
- } CSSR_b;
- };
-
- union
- {
- __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */
-
- struct
- {
- __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output
- * the smallest mailbox number that is searched in each mode
- * of MSMR. */
- uint8_t : 2;
- __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */
- } MSSR_b;
- };
-
- union
- {
- __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */
-
- struct
- {
- __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */
- uint8_t : 6;
- } MSMR_b;
- };
-
- union
- {
- __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */
-
- struct
- {
- __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */
- } TSR_b;
- };
-
- union
- {
- __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */
-
- struct
- {
- __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written,
- * the value converted for data table search can be read. */
- } AFSR_b;
- };
-
- union
- {
- __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */
-
- struct
- {
- __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */
- __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */
- uint8_t : 5;
- } TCR_b;
- };
- __IM uint8_t RESERVED2;
- __IM uint16_t RESERVED3;
-} R_CAN0_Type; /*!< Size = 2140 (0x85c) */
-
-/* =========================================================================================================================== */
-/* ================ R_CANFD ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD)
- */
-
-typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */
-{
- __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */
- __IM uint32_t RESERVED[25];
-
- union
- {
- __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */
-
- struct
- {
- __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */
- __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */
- __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */
- __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */
- __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */
- __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */
- uint32_t : 2;
- __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */
- __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */
- __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */
- __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */
- } CFDGCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */
-
- struct
- {
- __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */
- __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */
- uint32_t : 5;
- __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */
- __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */
- __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */
- __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */
- uint32_t : 2;
- __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */
- __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */
- __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */
- __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */
- uint32_t : 14;
- } CFDGCTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */
-
- struct
- {
- __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */
- __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */
- __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */
- __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */
- uint32_t : 28;
- } CFDGSTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */
-
- struct
- {
- __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */
- __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */
- __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */
- __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */
- __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */
- __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */
- __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */
- uint32_t : 1;
- __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */
- __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */
- uint32_t : 6;
- __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */
- __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */
- uint32_t : 14;
- } CFDGERFL_b;
- };
-
- union
- {
- __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */
-
- struct
- {
- __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */
- uint32_t : 16;
- } CFDGTSC_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */
-
- struct
- {
- __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */
- uint32_t : 4;
- __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */
- uint32_t : 23;
- } CFDGAFLECTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
- * 0 */
-
- struct
- {
- __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */
- uint32_t : 7;
- __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */
- uint32_t : 7;
- } CFDGAFLCFG0_b;
- };
- __IM uint32_t RESERVED1[3];
-
- union
- {
- __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */
-
- struct
- {
- __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */
- __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */
- uint32_t : 21;
- } CFDRMNB_b;
- };
-
- union
- {
- __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */
-
- struct
- {
- __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */
- } CFDRMND0_b;
- };
- __IM uint32_t RESERVED2[3];
-
- union
- {
- __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */
-
- struct
- {
- __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */
- __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */
- uint32_t : 2;
- __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */
- uint32_t : 1;
- __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */
- uint32_t : 1;
- __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */
- __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */
- __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */
- uint32_t : 15;
- } CFDRFCC_b[8];
- };
-
- union
- {
- __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */
-
- struct
- {
- __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */
- __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */
- __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */
- __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */
- uint32_t : 4;
- __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */
- __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */
- uint32_t : 15;
- } CFDRFSTS_b[8];
- };
-
- union
- {
- __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */
-
- struct
- {
- __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */
- uint32_t : 24;
- } CFDRFPCTR_b[8];
- };
-
- union
- {
- __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */
-
- struct
- {
- __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */
- __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */
- __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */
- uint32_t : 1;
- __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */
- __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */
- __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */
- __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */
- __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */
- __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */
- __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */
- __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */
- } CFDCFCC_b[6];
- };
- __IM uint32_t RESERVED3[18];
-
- union
- {
- __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement
- * Registers */
-
- struct
- {
- __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */
- __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */
- __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */
- uint32_t : 5;
- __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */
- uint32_t : 7;
- __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */
- uint32_t : 15;
- } CFDCFCCE_b[6];
- };
- __IM uint32_t RESERVED4[18];
-
- union
- {
- __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */
-
- struct
- {
- __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */
- __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */
- __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */
- __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */
- __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */
- uint32_t : 3;
- __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */
- __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */
- __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */
- __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */
- uint32_t : 5;
- __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */
- uint32_t : 7;
- } CFDCFSTS_b[6];
- };
- __IM uint32_t RESERVED5[18];
-
- union
- {
- __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */
-
- struct
- {
- __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */
- uint32_t : 24;
- } CFDCFPCTR_b[6];
- };
- __IM uint32_t RESERVED6[18];
-
- union
- {
- __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */
-
- struct
- {
- __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */
- __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */
- uint32_t : 18;
- } CFDFESTS_b;
- };
-
- union
- {
- __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */
-
- struct
- {
- __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */
- __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */
- uint32_t : 18;
- } CFDFFSTS_b;
- };
-
- union
- {
- __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */
-
- struct
- {
- __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */
- __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */
- uint32_t : 18;
- } CFDFMSTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */
-
- struct
- {
- __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */
- uint32_t : 8;
- __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */
- uint32_t : 8;
- } CFDRFISTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */
-
- struct
- {
- __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */
- uint32_t : 26;
- } CFDCFRISTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */
-
- struct
- {
- __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */
- uint32_t : 26;
- } CFDCFTISTS_b;
- };
-
- union
- {
- __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
- * Register */
-
- struct
- {
- __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */
- uint32_t : 26;
- } CFDCFOFRISTS_b;
- };
-
- union
- {
- __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
- * Register */
-
- struct
- {
- __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */
- uint32_t : 26;
- } CFDCFOFTISTS_b;
- };
-
- union
- {
- __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */
-
- struct
- {
- __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */
- uint32_t : 26;
- } CFDCFMOWSTS_b;
- };
-
- union
- {
- __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */
-
- struct
- {
- __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */
- __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */
- uint32_t : 18;
- } CFDFFFSTS_b;
- };
- __IM uint32_t RESERVED7[2];
-
- union
- {
- __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */
-
- struct
- {
- __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */
- __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */
- __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */
- uint8_t : 5;
- } CFDTMC_b[128];
- };
- __IM uint32_t RESERVED8[288];
-
- union
- {
- __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */
-
- struct
- {
- __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */
- __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */
- __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */
- __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */
- uint8_t : 3;
- } CFDTMSTS_b[128];
- };
- __IM uint32_t RESERVED9[288];
-
- union
- {
- __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
- * Register */
-
- struct
- {
- __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */
- uint32_t : 24;
- } CFDTMTRSTS_b[4];
- };
- __IM uint32_t RESERVED10[36];
-
- union
- {
- __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
- * Status Register */
-
- struct
- {
- __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */
- uint32_t : 24;
- } CFDTMTARSTS_b[4];
- };
- __IM uint32_t RESERVED11[36];
-
- union
- {
- __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
- * Register */
-
- struct
- {
- __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */
- uint32_t : 24;
- } CFDTMTCSTS_b[4];
- };
- __IM uint32_t RESERVED12[36];
-
- union
- {
- __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */
-
- struct
- {
- __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */
- uint32_t : 24;
- } CFDTMTASTS_b[4];
- };
- __IM uint32_t RESERVED13[36];
-
- union
- {
- __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration
- * Register */
-
- struct
- {
- __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */
- uint32_t : 24;
- } CFDTMIEC_b[4];
- };
- __IM uint32_t RESERVED14[40];
-
- union
- {
- __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */
-
- struct
- {
- __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
- __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
- uint32_t : 3;
- __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
- __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
- uint32_t : 3;
- __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */
- __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
- __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
- uint32_t : 13;
- } CFDTXQCC0_b[2];
- };
- __IM uint32_t RESERVED15[6];
-
- union
- {
- __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */
-
- struct
- {
- __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
- __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
- __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
- uint32_t : 5;
- __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
- uint32_t : 2;
- __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
- __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
- __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
- __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
- uint32_t : 12;
- } CFDTXQSTS0_b[2];
- };
- __IM uint32_t RESERVED16[6];
-
- union
- {
- __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */
-
- struct
- {
- __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
- uint32_t : 24;
- } CFDTXQPCTR0_b[2];
- };
- __IM uint32_t RESERVED17[6];
-
- union
- {
- __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */
-
- struct
- {
- __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
- __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
- uint32_t : 3;
- __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
- __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
- uint32_t : 3;
- __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */
- __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
- __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
- uint32_t : 13;
- } CFDTXQCC1_b[2];
- };
- __IM uint32_t RESERVED18[6];
-
- union
- {
- __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */
-
- struct
- {
- __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
- __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
- __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
- uint32_t : 5;
- __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
- uint32_t : 2;
- __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
- __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
- __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
- __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
- uint32_t : 12;
- } CFDTXQSTS1_b[2];
- };
- __IM uint32_t RESERVED19[6];
-
- union
- {
- __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */
-
- struct
- {
- __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
- uint32_t : 24;
- } CFDTXQPCTR1_b[2];
- };
- __IM uint32_t RESERVED20[6];
-
- union
- {
- __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */
-
- struct
- {
- __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
- __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */
- uint32_t : 3;
- __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
- __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
- uint32_t : 3;
- __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */
- __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */
- __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
- uint32_t : 13;
- } CFDTXQCC2_b[2];
- };
- __IM uint32_t RESERVED21[6];
-
- union
- {
- __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */
-
- struct
- {
- __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
- __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
- __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
- uint32_t : 5;
- __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
- uint32_t : 2;
- __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */
- __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */
- __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
- __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */
- uint32_t : 12;
- } CFDTXQSTS2_b[2];
- };
- __IM uint32_t RESERVED22[6];
-
- union
- {
- __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */
-
- struct
- {
- __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
- uint32_t : 24;
- } CFDTXQPCTR2_b[2];
- };
- __IM uint32_t RESERVED23[6];
-
- union
- {
- __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */
-
- struct
- {
- __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
- uint32_t : 4;
- __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
- __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */
- uint32_t : 5;
- __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */
- uint32_t : 13;
- } CFDTXQCC3_b[2];
- };
- __IM uint32_t RESERVED24[6];
-
- union
- {
- __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */
-
- struct
- {
- __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
- __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
- __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
- uint32_t : 5;
- __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
- uint32_t : 4;
- __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */
- uint32_t : 13;
- } CFDTXQSTS3_b[2];
- };
- __IM uint32_t RESERVED25[6];
-
- union
- {
- __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */
-
- struct
- {
- __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
- uint32_t : 24;
- } CFDTXQPCTR3_b[2];
- };
- __IM uint32_t RESERVED26[6];
-
- union
- {
- __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */
-
- struct
- {
- __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */
- uint32_t : 24;
- } CFDTXQESTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */
-
- struct
- {
- __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */
- uint32_t : 1;
- __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */
- uint32_t : 25;
- } CFDTXQFISTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */
-
- struct
- {
- __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */
- uint32_t : 1;
- __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */
- uint32_t : 25;
- } CFDTXQMSTS_b;
- };
- __IM uint32_t RESERVED27;
-
- union
- {
- __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */
-
- struct
- {
- __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */
- __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */
- uint32_t : 24;
- } CFDTXQISTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */
-
- struct
- {
- __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */
- __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */
- uint32_t : 24;
- } CFDTXQOFTISTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */
-
- struct
- {
- __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */
- uint32_t : 1;
- __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */
- uint32_t : 25;
- } CFDTXQOFRISTS_b;
- };
-
- union
- {
- __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */
-
- struct
- {
- __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */
- __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */
- uint32_t : 24;
- } CFDTXQFSTS_b;
- };
- __IM uint32_t RESERVED28[24];
-
- union
- {
- __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */
-
- struct
- {
- __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */
- uint32_t : 7;
- __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */
- __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */
- __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */
- __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */
- uint32_t : 20;
- } CFDTHLCC_b[2];
- };
- __IM uint32_t RESERVED29[6];
-
- union
- {
- __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */
-
- struct
- {
- __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */
- __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */
- __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */
- __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */
- uint32_t : 4;
- __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */
- uint32_t : 18;
- } CFDTHLSTS_b[2];
- };
- __IM uint32_t RESERVED30[6];
-
- union
- {
- __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */
-
- struct
- {
- __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */
- uint32_t : 24;
- } CFDTHLPCTR_b[2];
- };
- __IM uint32_t RESERVED31[46];
-
- union
- {
- __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */
-
- struct
- {
- __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */
- __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */
- __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */
- __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */
- __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */
- __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
- * 0 */
- __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
- * 0 */
- uint32_t : 1;
- __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */
- __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */
- __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */
- __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */
- __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */
- __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
- * 1 */
- __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
- * 1 */
- uint32_t : 17;
- } CFDGTINTSTS0_b;
- };
- __IM uint32_t RESERVED32;
-
- union
- {
- __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */
-
- struct
- {
- __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */
- uint32_t : 14;
- __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */
- uint32_t : 6;
- } CFDGTSTCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */
-
- struct
- {
- __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */
- uint32_t : 1;
- __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */
- uint32_t : 29;
- } CFDGTSTCTR_b;
- };
- __IM uint32_t RESERVED33;
-
- union
- {
- __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */
-
- struct
- {
- __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */
- uint32_t : 7;
- __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */
- uint32_t : 22;
- } CFDGFDCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */
-
- struct
- {
- __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */
- uint32_t : 31;
- } CFDGCRCCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */
-
- struct
- {
- __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */
- uint32_t : 16;
- } CFDGLOCKK_b;
- };
-
- union
- {
- __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */
-
- struct
- {
- __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */
- uint32_t : 7;
- __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */
- __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */
- __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */
- __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */
- uint32_t : 16;
- } CFDGLOTB_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */
-
- struct
- {
- __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */
- uint32_t : 7;
- __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */
- uint32_t : 13;
- } CFDGAFLIGNENT_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */
-
- struct
- {
- __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */
- uint32_t : 7;
- __OM uint32_t KEY : 8; /*!< [15..8] Key code */
- uint32_t : 16;
- } CFDGAFLIGNCTR_b;
- };
- __IM uint32_t RESERVED34;
-
- union
- {
- __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */
-
- struct
- {
- __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */
- __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */
- __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */
- __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */
- __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */
- __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */
- __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */
- __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */
- __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */
- __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */
- uint32_t : 22;
- } CFDCDTCT_b;
- };
-
- union
- {
- __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */
-
- struct
- {
- __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */
- __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */
- __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */
- __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */
- __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */
- __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */
- __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */
- __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */
- __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
- * 0 */
- __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel
- * 1 */
- uint32_t : 22;
- } CFDCDTSTS_b;
- };
- __IM uint32_t RESERVED35[2];
-
- union
- {
- __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */
-
- struct
- {
- __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */
- __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */
- uint32_t : 6;
- __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */
- __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */
- uint32_t : 6;
- __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel
- * 0 */
- __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel
- * 1 */
- uint32_t : 14;
- } CFDCDTTCT_b;
- };
-
- union
- {
- __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */
-
- struct
- {
- __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */
- __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */
- uint32_t : 6;
- __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */
- __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */
- uint32_t : 6;
- __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel
- * 0 */
- __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel
- * 1 */
- uint32_t : 14;
- } CFDCDTTSTS_b;
- };
- __IM uint32_t RESERVED36[2];
-
- union
- {
- __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */
-
- struct
- {
- __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */
- uint32_t : 5;
- __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */
- uint32_t : 5;
- __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */
- uint32_t : 5;
- __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */
- uint32_t : 1;
- __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */
- uint32_t : 1;
- } CFDGRINTSTS_b[2];
- };
- __IM uint32_t RESERVED37[10];
-
- union
- {
- __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */
-
- struct
- {
- __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */
- uint32_t : 7;
- __OM uint32_t KEY : 8; /*!< [15..8] Key code */
- uint32_t : 16;
- } CFDGRSTC_b;
- };
- __IM uint32_t RESERVED38[31];
- __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */
- __IM uint32_t RESERVED39[240];
- __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */
- __IM uint32_t RESERVED40[448];
- __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */
- __IM uint32_t RESERVED41[3072];
- __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */
- __IOM R_CANFD_CFDCF_Type CFDCF[5]; /*!< (@ 0x00006400) Common FIFO Access Registers */
- __IM uint32_t RESERVED42[1632];
- __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */
- __IM uint32_t RESERVED43[252];
-
- union
- {
- __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */
-
- struct
- {
- __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
- } CFDRPGACC_b[64];
- };
- __IM uint32_t RESERVED44[7872];
- __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */
-} R_CANFD_Type; /*!< Size = 81920 (0x14000) */
-
-/* =========================================================================================================================== */
-/* ================ R_CANFDL ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFDL)
- */
-
-typedef struct /*!< (@ 0x400B0000) R_CANFDL Structure */
-{
- __IOM R_CANFDL_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */
-
- struct
- {
- __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */
- __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */
- __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */
- __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */
- __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */
- __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */
- uint32_t : 2;
- __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */
- __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */
- uint32_t : 3;
- __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */
- } CFDGCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */
-
- struct
- {
- __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */
- __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */
- uint32_t : 5;
- __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */
- __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */
- __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */
- __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */
- uint32_t : 4;
- __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */
- uint32_t : 15;
- } CFDGCTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */
-
- struct
- {
- __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */
- __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */
- __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */
- __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */
- uint32_t : 28;
- } CFDGSTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */
-
- struct
- {
- __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */
- __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */
- __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */
- __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */
- uint32_t : 12;
- __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */
- uint32_t : 15;
- } CFDGERFL_b;
- };
-
- union
- {
- __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */
-
- struct
- {
- __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */
- uint32_t : 16;
- } CFDGTSC_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */
-
- struct
- {
- __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */
- uint32_t : 4;
- __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */
- uint32_t : 23;
- } CFDGAFLECTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
- * 0 */
-
- struct
- {
- __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */
- uint32_t : 7;
- __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */
- uint32_t : 7;
- } CFDGAFLCFG0_b;
- };
-
- union
- {
- __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */
-
- struct
- {
- __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */
- __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */
- uint32_t : 21;
- } CFDRMNB_b;
- };
-
- union
- {
- __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */
-
- struct
- {
- __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */
- } CFDRMND0_b;
- };
-
- union
- {
- __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
- * Register */
-
- struct
- {
- __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */
- } CFDRMIEC_b;
- };
-
- union
- {
- __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */
-
- struct
- {
- __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */
- __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */
- uint32_t : 2;
- __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */
- uint32_t : 1;
- __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */
- uint32_t : 1;
- __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */
- __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */
- uint32_t : 16;
- } CFDRFCC_b[2];
- };
-
- union
- {
- __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */
-
- struct
- {
- __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */
- __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */
- __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */
- __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */
- uint32_t : 4;
- __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */
- uint32_t : 16;
- } CFDRFSTS_b[2];
- };
-
- union
- {
- __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */
-
- struct
- {
- __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */
- uint32_t : 24;
- } CFDRFPCTR_b[2];
- };
-
- union
- {
- __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */
-
- struct
- {
- __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */
- __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */
- __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */
- uint32_t : 1;
- __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */
- __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */
- __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */
- __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */
- __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */
- __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */
- __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */
- __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */
- } CFDCFCC_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */
-
- struct
- {
- __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */
- __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */
- __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */
- __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */
- __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */
- uint32_t : 3;
- __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */
- uint32_t : 16;
- } CFDCFSTS_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */
-
- struct
- {
- __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */
- uint32_t : 24;
- } CFDCFPCTR_b[1];
- };
-
- union
- {
- __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */
-
- struct
- {
- __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */
- uint32_t : 6;
- __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */
- uint32_t : 23;
- } CFDFESTS_b;
- };
-
- union
- {
- __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */
-
- struct
- {
- __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */
- uint32_t : 6;
- __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */
- uint32_t : 23;
- } CFDFFSTS_b;
- };
-
- union
- {
- __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */
-
- struct
- {
- __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */
- uint32_t : 6;
- __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */
- uint32_t : 23;
- } CFDFMSTS_b;
- };
-
- union
- {
- __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */
-
- struct
- {
- __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */
- uint32_t : 31;
- } CFDRFISTS_b;
- };
-
- union
- {
- __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */
-
- struct
- {
- __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */
- __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */
- __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */
- uint8_t : 5;
- } CFDTMC_b[4];
- };
-
- union
- {
- __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */
-
- struct
- {
- __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */
- __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */
- __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */
- __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */
- uint8_t : 3;
- } CFDTMSTS_b[4];
- };
-
- union
- {
- __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
- * Register */
-
- struct
- {
- __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */
- uint32_t : 28;
- } CFDTMTRSTS_b[1];
- };
-
- union
- {
- __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
- * Status Register */
-
- struct
- {
- __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */
- uint32_t : 28;
- } CFDTMTARSTS_b[1];
- };
-
- union
- {
- __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
- * Register */
-
- struct
- {
- __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */
- uint32_t : 28;
- } CFDTMTCSTS_b[1];
- };
-
- union
- {
- __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */
-
- struct
- {
- __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */
- uint32_t : 28;
- } CFDTMTASTS_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
- * Register */
-
- struct
- {
- __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */
- uint32_t : 28;
- } CFDTMIEC_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */
-
- struct
- {
- __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
- uint32_t : 4;
- __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
- __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */
- uint32_t : 22;
- } CFDTXQCC0_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */
-
- struct
- {
- __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
- __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
- __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
- uint32_t : 5;
- __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
- uint32_t : 18;
- } CFDTXQSTS0_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */
-
- struct
- {
- __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
- uint32_t : 24;
- } CFDTXQPCTR0_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */
-
- struct
- {
- __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */
- uint32_t : 7;
- __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */
- __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */
- __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */
- uint32_t : 21;
- } CFDTHLCC_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */
-
- struct
- {
- __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */
- __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */
- __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */
- __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */
- uint32_t : 4;
- __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */
- uint32_t : 18;
- } CFDTHLSTS_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */
-
- struct
- {
- __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */
- uint32_t : 24;
- } CFDTHLPCTR_b[1];
- };
-
- union
- {
- __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */
-
- struct
- {
- __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */
- __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */
- __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */
- __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */
- __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */
- uint32_t : 27;
- } CFDGTINTSTS0_b;
- };
-
- union
- {
- __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */
- uint32_t : 6;
- } CFDGTSTCFG_b;
- };
-
- union
- {
- __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */
-
- struct
- {
- uint32_t : 2;
- __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */
- uint32_t : 29;
- } CFDGTSTCTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */
-
- struct
- {
- __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */
- uint32_t : 7;
- __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */
- uint32_t : 22;
- } CFDGFDCFG_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */
-
- struct
- {
- __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */
- uint32_t : 16;
- } CFDGLOCKK_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */
-
- struct
- {
- __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */
- uint32_t : 27;
- } CFDGAFLIGNENT_b;
- };
-
- union
- {
- __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */
-
- struct
- {
- __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */
- uint32_t : 7;
- __OM uint32_t KEY : 8; /*!< [15..8] Key code */
- uint32_t : 16;
- } CFDGAFLIGNCTR_b;
- };
-
- union
- {
- __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */
-
- struct
- {
- __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */
- __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */
- uint32_t : 6;
- __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */
- uint32_t : 23;
- } CFDCDTCT_b;
- };
-
- union
- {
- __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */
-
- struct
- {
- __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */
- __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */
- uint32_t : 6;
- __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
- * 0 */
- uint32_t : 23;
- } CFDCDTSTS_b;
- };
- __IM uint32_t RESERVED3[2];
-
- union
- {
- __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */
-
- struct
- {
- __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */
- uint32_t : 7;
- __OM uint32_t KEY : 8; /*!< [15..8] Key code */
- uint32_t : 16;
- } CFDGRSTC_b;
- };
- __IM uint32_t RESERVED4[9];
- __IOM R_CANFDL_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */
- __IOM R_CANFDL_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */
- __IM uint32_t RESERVED5[24];
-
- union
- {
- __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */
-
- struct
- {
- __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
- } CFDRPGACC_b[64];
- };
- __IM uint32_t RESERVED6[104];
- __IOM R_CANFDL_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */
- __IOM R_CANFDL_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */
- __IOM R_CANFDL_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */
- __IM uint32_t RESERVED7[3];
- __IOM R_CANFDL_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */
- __IM uint32_t RESERVED8[118];
- __IOM R_CANFDL_CFDRMC_Type CFDRMC[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */
-} R_CANFDL_Type; /*!< Size = 6432 (0x1920) */
-
-/* =========================================================================================================================== */
-/* ================ R_CRC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
- */
-
-typedef struct /*!< (@ 0x40074000) R_CRC Structure */
-{
- union
- {
- __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */
-
- struct
- {
- __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */
- uint8_t : 3;
- __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */
- __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */
- } CRCCR0_b;
- };
-
- union
- {
- __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */
- __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */
- } CRCCR1_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- union
- {
- __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */
-
- struct
- {
- __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */
- } CRCDIR_b;
- };
-
- union
- {
- __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */
-
- struct
- {
- __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
- * ) */
- } CRCDIR_BY_b;
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */
-
- struct
- {
- __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */
- } CRCDOR_b;
- };
-
- union
- {
- __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */
-
- struct
- {
- __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
- * ) */
- } CRCDOR_HA_b;
- };
-
- union
- {
- __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */
-
- struct
- {
- __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */
- } CRCDOR_BY_b;
- };
- };
-
- union
- {
- __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */
-
- struct
- {
- __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */
- uint16_t : 2;
- } CRCSAR_b;
- };
- __IM uint16_t RESERVED1;
-} R_CRC_Type; /*!< Size = 16 (0x10) */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Capacitive Touch Sensing Unit (R_CTSU)
- */
-
-typedef struct /*!< (@ 0x40081000) R_CTSU Structure */
-{
- union
- {
- __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */
-
- struct
- {
- __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */
- __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */
- __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */
- __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */
- __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */
- uint8_t : 2;
- __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */
- } CTSUCR0_b;
- };
-
- union
- {
- __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */
-
- struct
- {
- __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */
- __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */
- __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */
- __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */
- __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */
- __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */
- } CTSUCR1_b;
- };
-
- union
- {
- __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */
-
- struct
- {
- __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
- * setting: 3 (0011b) */
- __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */
- __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */
- uint8_t : 1;
- } CTSUSDPRS_b;
- };
-
- union
- {
- __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */
-
- struct
- {
- __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
- * of these bits should be fixed to 00010000b. */
- } CTSUSST_b;
- };
-
- union
- {
- __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */
-
- struct
- {
- __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
- * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
- * bits = 00b).Note2: If the value of CTSUMCH0 was set to
- * b'111111 in mode other than self-capacitor single scan
- * mode, the measurement is stopped. */
- uint8_t : 2;
- } CTSUMCH0_b;
- };
-
- union
- {
- __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */
-
- struct
- {
- __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
- * was set to b'111111, the measurement is stopped. */
- uint8_t : 2;
- } CTSUMCH1_b;
- };
-
- union
- {
- __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */
-
- struct
- {
- __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */
- __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */
- __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */
- __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */
- __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */
- __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */
- __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */
- __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */
- } CTSUCHAC_b[5];
- };
-
- union
- {
- __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */
-
- struct
- {
- __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */
- __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */
- } CTSUCHTRC_b[5];
- };
-
- union
- {
- __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */
-
- struct
- {
- __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
- * be set to 00b. */
- uint8_t : 2;
- __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
- * be set to 11b. */
- uint8_t : 2;
- } CTSUDCLKC_b;
- };
-
- union
- {
- __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */
-
- struct
- {
- __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */
- uint8_t : 1;
- __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */
- __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */
- __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */
- __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */
- } CTSUST_b;
- };
-
- union
- {
- __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
- * Control Register */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */
- uint16_t : 4;
- } CTSUSSC_b;
- };
-
- union
- {
- __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */
-
- struct
- {
- __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
- * CTSUSO ( 0 to 1023 ) */
- __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */
- } CTSUSO0_b;
- };
-
- union
- {
- __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */
-
- struct
- {
- __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
- * is CTSUSO ( 0 to 255 ) */
- __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
- * CTSUSDPA + 1 ) x 2 */
- __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */
- uint16_t : 1;
- } CTSUSO1_b;
- };
-
- union
- {
- __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */
-
- struct
- {
- __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
- * result of the CTSU. These bits indicate FFFFh when an overflow
- * occurs. */
- } CTSUSC_b;
- };
-
- union
- {
- __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */
-
- struct
- {
- __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
- * result of the reference ICO.These bits indicate FFFFh when
- * an overflow occurs. */
- } CTSURC_b;
- };
-
- union
- {
- __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */
-
- struct
- {
- __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */
- __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */
- __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */
- uint16_t : 2;
- __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */
- __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */
- uint16_t : 7;
- __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */
- } CTSUERRS_b;
- };
- __IM uint16_t RESERVED;
- __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2;
-} R_CTSU_Type; /*!< Size = 36 (0x24) */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSU2 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Capacitive Touch Sensing Unit (R_CTSU2)
- */
-
-typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */
-{
- union
- {
- union
- {
- __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */
-
- struct
- {
- __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */
- __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */
- __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */
- __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */
- __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */
- __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */
- __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */
- __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power On Control */
- __IOM uint32_t CSW : 1; /*!< [9..9] TSCAP Pin Enable */
- __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */
- __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */
- __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */
- __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */
- __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */
- __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */
- __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */
- __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Load Control During Measurement */
- __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */
- __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */
- __IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */
- __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */
- __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */
- __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */
- } CTSUCRA_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */
-
- struct
- {
- __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */
- __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUCRAH; /*!< (@ 0x00000002) CTSU Control Register A */
-
- struct
- {
- __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */
- __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */
- };
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */
-
- struct
- {
- __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control */
- __IOM uint32_t PRMODE : 2; /*!< [5..4] Phase Control Period */
- __IOM uint32_t SOFF : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable */
- __IOM uint32_t PROFF : 1; /*!< [7..7] Drive Pulse Phase Control */
- __IOM uint32_t SST : 8; /*!< [15..8] Wait Time Sensor Stabilization */
- uint32_t : 8;
- __IOM uint32_t SSMOD : 3; /*!< [26..24] Spread Spectrum Modulation Frequency */
- uint32_t : 1;
- __IOM uint32_t SSCNT : 2; /*!< [29..28] Adjusting the SUCLK frequency */
- uint32_t : 2;
- } CTSUCRB_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */
-
- struct
- {
- __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */
- __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */
-
- struct
- {
- __IM uint8_t RESERVED;
- __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */
- };
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */
-
- struct
- {
- __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */
- uint32_t : 2;
- __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */
- uint32_t : 2;
- __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */
- __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */
- __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */
- __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */
- uint32_t : 12;
- } CTSUMCH_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */
-
- struct
- {
- __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */
- __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */
- __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */
-
- struct
- {
- __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */
- uint32_t : 1;
- __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */
- uint32_t : 1;
- __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */
- uint32_t : 2;
- __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */
- __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */
- } CTSUCHACA_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */
-
- struct
- {
- __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */
- __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */
-
- struct
- {
- __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */
- __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */
- };
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */
-
- struct
- {
- __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */
- __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */
- __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */
- __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */
- uint32_t : 28;
- } CTSUCHACB_b;
- };
- __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */
- __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
- * A */
-
- struct
- {
- __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */
- uint32_t : 1;
- __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */
- uint32_t : 1;
- __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */
- uint32_t : 2;
- __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */
- __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */
- } CTSUCHTRCA_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
- * A */
-
- struct
- {
- __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
- * A */
- __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register
- * A */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
- * A */
-
- struct
- {
- __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
- * A */
- __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register
- * A */
- };
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
- * B */
-
- struct
- {
- __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */
- __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */
- __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */
- __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */
- uint32_t : 28;
- } CTSUCHTRCB_b;
- };
- __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
- * B */
- __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
- * B */
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */
-
- struct
- {
- __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */
- uint32_t : 3;
- __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */
- __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */
- __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */
- __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */
- uint32_t : 1;
- __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */
- __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */
- __IOM uint32_t SUOVF : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag */
- __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */
- __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */
- uint32_t : 10;
- } CTSUSR_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */
-
- struct
- {
- __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */
- __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */
- };
- };
-
- union
- {
- __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */
- __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */
-
- struct
- {
- __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */
- __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */
- uint32_t : 2;
- __IOM uint32_t SSDIV : 4; /*!< [23..20] Spread Spectrum Frequency */
- __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */
- } CTSUSO_b;
- };
-
- struct
- {
- __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */
- __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */
- };
- };
-
- union
- {
- union
- {
- __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */
-
- struct
- {
- __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */
- __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter */
- } CTSUSCNT_b;
- };
- __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */
-
- struct
- {
- uint32_t : 2;
- __IOM uint32_t TSOD : 1; /*!< [2..2] TS Pins Fixed Output */
- __IOM uint32_t DRV : 1; /*!< [3..3] Power Supply Calibration Select */
- __IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select */
- __IOM uint32_t SUCLKEN : 1; /*!< [6..6] SUCLK Forced Oscillation Control */
- __IOM uint32_t TSOC : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit */
- __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter */
- __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */
- __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */
- __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */
- uint32_t : 4;
- __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */
- __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */
- uint32_t : 1;
- __IOM uint32_t DACMSEL : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select */
- __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration */
- __IOM uint32_t SUMSEL : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration
- * Select */
- __IOM uint32_t SUCARRY : 1; /*!< [27..27] Current Control Oscillator Input Current Adjustment
- * for SUCLK */
- __IOM uint32_t DACCLK : 1; /*!< [28..28] Modulation Clock Select for Offset Current Circuits */
- __IOM uint32_t CCOCLK : 1; /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator
- * Input Current of SUCLK */
- __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator
- * for Measurement */
- __IOM uint32_t TXREV : 1; /*!< [31..31] Transmit Pin Inverted Output */
- } CTSUCALIB_b;
- };
-
- struct
- {
- __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */
- __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */
-
- struct
- {
- __IOM uint32_t SUADJ0 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */
- __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */
- __IOM uint32_t SUADJ1 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */
- __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */
- } CTSUSUCLKA_b;
- };
-
- struct
- {
- __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */
- __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */
-
- struct
- {
- __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */
- __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */
- __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */
- __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */
- } CTSUSUCLKB_b;
- };
-
- struct
- {
- __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */
- __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */
- };
- };
-
- union
- {
- union
- {
- __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */
-
- struct
- {
- __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */
- uint32_t : 16;
- } CTSUCFCCNT_b;
- };
- __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */
- };
-} R_CTSU2_Type; /*!< Size = 56 (0x38) */
-
-/* =========================================================================================================================== */
-/* ================ R_DAC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief D/A Converter (R_DAC)
- */
-
-typedef struct /*!< (@ 0x4005E000) R_DAC Structure */
-{
- union
- {
- __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */
-
- struct
- {
- __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
- * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL
- * = 1, the low-order 4 bits are fixed to 0: left justified
- * format. */
- } DADR_b[2];
- };
-
- union
- {
- __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */
-
- struct
- {
- uint8_t : 5;
- __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */
- __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */
- __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */
- } DACR_b;
- };
-
- union
- {
- __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */
- } DADPR_b;
- };
-
- union
- {
- __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */
- } DAADSCR_b;
- };
-
- union
- {
- __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */
-
- struct
- {
- __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */
- uint8_t : 5;
- } DAVREFCR_b;
- };
-
- union
- {
- __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */
- __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */
- } DAAMPCR_b;
- };
-
- union
- {
- __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */
-
- struct
- {
- __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */
- uint8_t : 7;
- } DAPC_b;
- };
- __IM uint16_t RESERVED[9];
-
- union
- {
- __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
- * to wait for stabilization of the output amplifier of D/A
- * channel 0. When DAASW0 is set to 1, D/A conversion operates,
- * but the conversion result D/A is not output from channel
- * 0. When the DAASW0 bit is 0, the stabilization wait time
- * stops, and the D/A conversion result of channel 0 is output
- * through the output amplifier. */
- __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
- * to wait for stabilization of the output amplifier of D/A
- * channel 1. When DAASW1 is set to 1, D/A conversion operates,
- * but the conversion result D/A is not output from channel
- * 1. When the DAASW1 bit is 0, the stabilization wait time
- * stops, and the D/A conversion result of channel 1 is output
- * through the output amplifier. */
- } DAASWCR_b;
- };
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2[2129];
-
- union
- {
- __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for
- * D/A and A/D synchronous conversions. Set bit [1] to 1 to
- * select unit 1 as the target synchronous unit for the MCU.
- * When setting the DAADSCR.DAADST bit to 1 for synchronous
- * conversions, select the target unit in this register in
- * advance. Only set the DAADUSR register while the ADCSR.ADST
- * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
- * is set to 0. */
- uint8_t : 1;
- } DAADUSR_b;
- };
- __IM uint8_t RESERVED3;
- __IM uint16_t RESERVED4;
-} R_DAC_Type; /*!< Size = 4292 (0x10c4) */
-
-/* =========================================================================================================================== */
-/* ================ R_DAC8 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief 8-Bit D/A Converter (R_DAC8)
- */
-
-typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */
-{
- union
- {
- __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */
-
- struct
- {
- __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */
- } DACS_b[2];
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */
-
- struct
- {
- __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */
- __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */
- uint8_t : 2;
- __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */
- __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */
- uint8_t : 2;
- } DAM_b;
- };
- __IM uint8_t RESERVED1[2];
-
- union
- {
- __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */
-
- struct
- {
- __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */
- uint8_t : 7;
- } DACADSCR_b;
- };
-
- union
- {
- __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */
-
- struct
- {
- __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */
- uint8_t : 7;
- } DACPC_b;
- };
-} R_DAC8_Type; /*!< Size = 8 (0x8) */
-
-/* =========================================================================================================================== */
-/* ================ R_DALI0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Digital Addressable Lighting Interface (R_DALI0)
- */
-
-typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */
-{
- union
- {
- __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register
- * 1 */
-
- struct
- {
- __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing
- * violation threshold value 1.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- uint16_t : 1;
- __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing
- * violation threshold value 2.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- } BTVTHR1_b;
- };
-
- union
- {
- __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register
- * 2 */
-
- struct
- {
- __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing
- * violation threshold value 3.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing
- * violation threshold value 4.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- } BTVTHR2_b;
- };
-
- union
- {
- __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register
- * 3 */
-
- struct
- {
- __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing
- * violation threshold value 5.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- uint16_t : 8;
- } BTVTHR3_b;
- };
-
- union
- {
- __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register
- * 4 */
-
- struct
- {
- __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing
- * violation threshold value 6.Note 1. These bits must be
- * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
- * bit is 0. */
- uint16_t : 7;
- } BTVTHR4_b;
- };
-
- union
- {
- __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */
-
- struct
- {
- __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold
- * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 2;
- __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold
- * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 2;
- } COLTHR1_b;
- };
-
- union
- {
- __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */
-
- struct
- {
- __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold
- * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 1;
- __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold
- * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 1;
- } COLTHR2_b;
- };
-
- union
- {
- __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */
-
- struct
- {
- __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold
- * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 1;
- __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold
- * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 1;
- } COLTHR3_b;
- };
-
- union
- {
- __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */
-
- struct
- {
- __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold
- * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold
- * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- } COLTHR4_b;
- };
-
- union
- {
- __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */
-
- struct
- {
- __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold
- * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE
- * bit is 0 and the DALI0.CTR1.TE bit is 0. */
- uint16_t : 8;
- } COLTHR5_b;
- };
-
- union
- {
- __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */
-
- struct
- {
- __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */
- __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */
- uint16_t : 2;
- __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */
- uint16_t : 1;
- } CNFR1_b;
- };
-
- union
- {
- __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */
-
- struct
- {
- __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified
- * only when the DALI0.STR1.BBF bit is 0. */
- __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified
- * only when the DALI0.STR1.BBF bit is 0. */
- __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified
- * only when the DALI0.STR1.BBF bit is 0. */
- __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified
- * only when the DALI0.STR1.BBF bit is 0. */
- __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified
- * only when the DALI0.STR1.BBF bit is 0. */
- __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only
- * when the DALI0.STR1.BBF bit is 0. */
- uint16_t : 10;
- } CNFR2_b;
- };
-
- union
- {
- __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */
-
- struct
- {
- __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */
- uint16_t : 9;
- } TXWR1_b;
- };
- __IM uint16_t RESERVED[3];
-
- union
- {
- __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */
-
- struct
- {
- __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */
- } TDR1H_b;
- };
-
- union
- {
- __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */
-
- struct
- {
- __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */
- } TDR1L_b;
- };
-
- union
- {
- __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */
-
- struct
- {
- __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */
- uint16_t : 15;
- } TRSTR1_b;
- };
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */
-
- struct
- {
- __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */
- __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */
- uint16_t : 6;
- __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */
- __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */
- __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */
- __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */
- __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */
- uint16_t : 3;
- } CTR1_b;
- };
-
- union
- {
- __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */
-
- struct
- {
- __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only
- * when the DALI0.CTR1.TE bit is 0. */
- __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only
- * when the DALI0.CTR1.TE bit is 0. */
- uint16_t : 14;
- } TXDCTR1_b;
- };
- __IM uint16_t RESERVED2[2];
-
- union
- {
- __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */
-
- struct
- {
- __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */
- } RDR1H_b;
- };
-
- union
- {
- __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */
-
- struct
- {
- __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */
- } RDR1L_b;
- };
-
- union
- {
- __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */
-
- struct
- {
- __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */
- __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */
- __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */
- __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */
- __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */
- __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */
- __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */
- __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */
- __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */
- __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */
- __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length
- * for data received successfully */
- } STR1_b;
- };
- __IM uint16_t RESERVED3;
-
- union
- {
- __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */
-
- struct
- {
- __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */
- __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */
- uint16_t : 5;
- __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */
- __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after
- * the DRX0 pin is synchronized */
- __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */
- __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */
- uint16_t : 2;
- } COLR1_b;
- };
- __IM uint16_t RESERVED4;
-
- union
- {
- __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */
-
- struct
- {
- __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */
- __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */
- __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */
- __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */
- __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */
- __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
- * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */
- __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */
- __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */
- __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */
- __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */
- uint16_t : 6;
- } FECR1_b;
- };
-
- union
- {
- __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */
-
- struct
- {
- __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software
- * reset. */
- uint16_t : 15;
- } SWRR1_b;
- };
-} R_DALI0_Type; /*!< Size = 62 (0x3e) */
-
-/* =========================================================================================================================== */
-/* ================ R_DEBUG ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Debug Function (R_DEBUG)
- */
-
-typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */
-{
- union
- {
- __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */
-
- struct
- {
- uint32_t : 28;
- __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */
- __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */
- uint32_t : 2;
- } DBGSTR_b;
- };
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */
-
- struct
- {
- __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */
- __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */
- uint32_t : 14;
- __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */
- __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */
- __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */
- uint32_t : 5;
- __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */
- __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */
- uint32_t : 5;
- __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */
- } DBGSTOPCR_b;
- };
-} R_DEBUG_Type; /*!< Size = 20 (0x14) */
-
-/* =========================================================================================================================== */
-/* ================ R_DMA ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief DMA Controller Common (R_DMA)
- */
-
-typedef struct /*!< (@ 0x40005200) R_DMA Structure */
-{
- union
- {
- __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */
-
- struct
- {
- __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */
- uint8_t : 7;
- } DMAST_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[15];
-
- union
- {
- __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */
-
- struct
- {
- __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */
- uint32_t : 5;
- __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */
- uint32_t : 7;
- __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */
- uint32_t : 15;
- } DMECHR_b;
- };
-} R_DMA_Type; /*!< Size = 68 (0x44) */
-
-/* =========================================================================================================================== */
-/* ================ R_DMAC0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief DMA Controller (R_DMAC0)
- */
-
-typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */
-{
- union
- {
- __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */
-
- struct
- {
- __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */
- } DMSAR_b;
- };
-
- union
- {
- __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */
-
- struct
- {
- __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */
- } DMDAR_b;
- };
-
- union
- {
- __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */
-
- struct
- {
- __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */
- __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */
- uint32_t : 6;
- } DMCRA_b;
- };
-
- union
- {
- __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */
-
- struct
- {
- __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or
- * repeat transfer operations. */
- } DMCRB_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */
-
- struct
- {
- __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */
- uint16_t : 6;
- __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */
- __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */
- uint16_t : 1;
- __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */
- __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */
- } DMTMD_b;
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */
-
- struct
- {
- __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
- * Enable */
- __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
- * Enable */
- __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */
- __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */
- __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */
- uint8_t : 3;
- } DMINT_b;
- };
-
- union
- {
- __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */
-
- struct
- {
- __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the
- * extended repeat area on the destination address. For details
- * on the settings. */
- __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */
- __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */
- __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
- * repeat area on the source address. For details on the settings. */
- __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */
- __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */
- } DMAMD_b;
- };
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */
-
- struct
- {
- __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
- * as the address update mode for transfer source or destination. */
- } DMOFR_b;
- };
-
- union
- {
- __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */
-
- struct
- {
- __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */
- uint8_t : 7;
- } DMCNT_b;
- };
-
- union
- {
- __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */
-
- struct
- {
- __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */
- uint8_t : 3;
- __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */
- uint8_t : 3;
- } DMREQ_b;
- };
-
- union
- {
- __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */
-
- struct
- {
- __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */
- uint8_t : 3;
- __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */
- uint8_t : 2;
- __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */
- } DMSTS_b;
- };
- __IM uint8_t RESERVED3;
- __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */
- __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */
-
- union
- {
- __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */
-
- struct
- {
- __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
- * mode */
- __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
- * mode */
- } DMSBS_b;
- };
-
- union
- {
- __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */
-
- struct
- {
- __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
- * mode */
- __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
- * mode */
- } DMDBS_b;
- };
-
- union
- {
- __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */
-
- struct
- {
- __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */
- uint8_t : 7;
- } DMBWR_b;
- };
- __IM uint8_t RESERVED4;
- __IM uint16_t RESERVED5;
-} R_DMAC0_Type; /*!< Size = 52 (0x34) */
-
-/* =========================================================================================================================== */
-/* ================ R_DOC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Data Operation Circuit (R_DOC)
- */
-
-typedef struct /*!< (@ 0x40054100) R_DOC Structure */
-{
- union
- {
- __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
-
- struct
- {
- __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
- __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */
- uint8_t : 2;
- __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */
- __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */
- uint8_t : 1;
- } DOCR_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */
-
- struct
- {
- __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
- * use in the operations are stored. */
- } DODIR_b;
- };
-
- union
- {
- __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */
-
- struct
- {
- __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
- * in data comparison mode. This register also stores the
- * results of operations in data addition and data subtraction
- * modes. */
- } DODSR_b;
- };
-} R_DOC_Type; /*!< Size = 6 (0x6) */
-
-/* =========================================================================================================================== */
-/* ================ R_DRW ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief 2D Drawing Engine (R_DRW)
- */
-
-typedef struct /*!< (@ 0x400E4000) R_DRW Structure */
-{
- union
- {
- union
- {
- __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */
-
- struct
- {
- __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */
- __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */
- __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */
- __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */
- __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */
- __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */
- __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */
- __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */
- __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */
- __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */
- __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */
- __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */
- __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */
- __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */
- __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */
- __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */
- __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */
- __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */
- __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */
- __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */
- __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */
- __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */
- __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per
- * scanline */
- __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line
- * span start */
- uint32_t : 8;
- } CONTROL_b;
- };
-
- union
- {
- __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */
-
- struct
- {
- __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */
- __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */
- __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */
- __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */
- __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */
- __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */
- __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */
- uint32_t : 1;
- __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */
- __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */
- __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */
- uint32_t : 21;
- } STATUS_b;
- };
- };
-
- union
- {
- union
- {
- __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */
-
- struct
- {
- __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and
- * COLOR2 depending on PATTERN and pattern index) */
- __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha
- * to blend between COLOR1 and COLOR2 */
- __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default
- * U limiter.Limiter 5 can be combined with limiter 6 to form
- * a quadratic limiter which can be used to make quadratic
- * pattern functions to draw radial patterns. */
- __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */
- __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT
- * above for description */
- __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel
- * blending mode (USEACB = 1) */
- __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel
- * blending mode (USEACB = 1) */
- __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above
- * description. */
- __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per
- * default) */
- __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor
- * is 1 per default) */
- __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted
- * (meaning 1-a or 1-1 depending on BSF) */
- __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will
- * be inverted (meaning 1-a or 1-1 depending on BDF) */
- __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */
- __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes
- * what happens if the U limiter (x direction in texture space)
- * calculates a U value outside of the used texture */
- __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes
- * what happens if the V limiter (y direction in texture space)
- * calculates a V value outside of the used texture */
- __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */
- __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */
- __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000:
- * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011:
- * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44)
- * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8),
- * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4),
- * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2),
- * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1),
- * 1 bit indexed color/luminance */
- __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */
- __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha
- * source' for the framebuffer(USEACB = 0)Blend alpha in color
- * 2 instead of framebuffer alpha((USEACB = 1))In not alpha
- * channel blending mode (USEACB = 0):Set the 'alpha source'
- * for the framebuffer.In alpha channel blending mode (USEACB
- * = 1):Blend alpha in color 2 instead of framebuffer alpha00B:
- * BC2A = 1: use alpha from framebuffer as destination (DST_A)else:
- * BC2A = 0: use alpha in color 2 as destination (DST_A) */
- __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */
- __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */
- __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */
- __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */
- __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB
- * = 1) */
- __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel
- * (USEACB = 1) */
- __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */
- } CONTROL2_b;
- };
-
- union
- {
- __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */
-
- struct
- {
- __IM uint32_t REV : 12; /*!< [11..0] Revision number */
- uint32_t : 5;
- __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */
- __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */
- __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */
- __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */
- __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */
- uint32_t : 1;
- __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */
- __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */
- __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */
- uint32_t : 1;
- __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */
- uint32_t : 4;
- } HWREVISION_b;
- };
- };
- __IM uint32_t RESERVED[2];
-
- union
- {
- __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L1START_b;
- };
-
- union
- {
- __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L2START_b;
- };
-
- union
- {
- __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L3START_b;
- };
-
- union
- {
- __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L4START_b;
- };
-
- union
- {
- __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L5START_b;
- };
-
- union
- {
- __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */
-
- struct
- {
- __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */
- } L6START_b;
- };
-
- union
- {
- __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L1XADD_b;
- };
-
- union
- {
- __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L2XADD_b;
- };
-
- union
- {
- __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L3XADD_b;
- };
-
- union
- {
- __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L4XADD_b;
- };
-
- union
- {
- __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L5XADD_b;
- };
-
- union
- {
- __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */
- } L6XADD_b;
- };
-
- union
- {
- __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L1YADD_b;
- };
-
- union
- {
- __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L2YADD_b;
- };
-
- union
- {
- __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L3YADD_b;
- };
-
- union
- {
- __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L4YADD_b;
- };
-
- union
- {
- __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L5YADD_b;
- };
-
- union
- {
- __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */
- } L6YADD_b;
- };
-
- union
- {
- __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */
-
- struct
- {
- __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */
- } L1BAND_b;
- };
-
- union
- {
- __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */
-
- struct
- {
- __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */
- } L2BAND_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */
-
- struct
- {
- __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */
- __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */
- __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */
- __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF:
- * opaque) */
- } COLOR1_b;
- };
-
- union
- {
- __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */
-
- struct
- {
- __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */
- __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */
- __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */
- __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF:
- * opaque) */
- } COLOR2_b;
- };
- __IM uint32_t RESERVED2[2];
-
- union
- {
- __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */
-
- struct
- {
- __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */
- uint32_t : 24;
- } PATTERN_b;
- };
-
- union
- {
- __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */
-
- struct
- {
- __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
- * 1024 */
- __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
- * to 1024 */
- } SIZE_b;
- };
-
- union
- {
- __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */
-
- struct
- {
- __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used
- * to render bottom-up instead of top-down */
- __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */
- } PITCH_b;
- };
-
- union
- {
- __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */
-
- struct
- {
- __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */
- } ORIGIN_b;
- };
- __IM uint32_t RESERVED3[3];
-
- union
- {
- __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */
-
- struct
- {
- __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */
- } LUSTART_b;
- };
-
- union
- {
- __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */
- } LUXADD_b;
- };
-
- union
- {
- __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */
-
- struct
- {
- __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */
- } LUYADD_b;
- };
-
- union
- {
- __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */
-
- struct
- {
- __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */
- } LVSTARTI_b;
- };
-
- union
- {
- __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */
-
- struct
- {
- __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */
- uint32_t : 16;
- } LVSTARTF_b;
- };
-
- union
- {
- __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */
-
- struct
- {
- __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */
- } LVXADDI_b;
- };
-
- union
- {
- __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */
-
- struct
- {
- __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */
- } LVYADDI_b;
- };
-
- union
- {
- __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */
-
- struct
- {
- __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */
- __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */
- } LVYXADDF_b;
- };
- __IM uint32_t RESERVED4;
-
- union
- {
- __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */
-
- struct
- {
- __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */
- } TEXPITCH_b;
- };
-
- union
- {
- __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */
-
- struct
- {
- __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture
- * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width
- * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX
- * = 1):all widths up to 2048 are allowed. */
- __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height
- * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY =
- * 0): texture_height must be a power of 2In texture clamping
- * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024
- * are allowed. */
- } TEXMASK_b;
- };
-
- union
- {
- __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */
-
- struct
- {
- __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */
- } TEXORIGIN_b;
- };
-
- union
- {
- __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */
-
- struct
- {
- __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */
- __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */
- __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */
- __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */
- __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */
- __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */
- uint32_t : 26;
- } IRQCTL_b;
- };
-
- union
- {
- __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */
-
- struct
- {
- __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */
- __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */
- __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */
- __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */
- uint32_t : 28;
- } CACHECTL_b;
- };
-
- union
- {
- __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */
-
- struct
- {
- __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */
- } DLISTSTART_b;
- };
-
- union
- {
- __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */
-
- struct
- {
- __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
- * = 0000 0000H. */
- } PERFCOUNT1_b;
- };
-
- union
- {
- __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */
-
- struct
- {
- __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
- * = 0000 0000H. */
- } PERFCOUNT2_b;
- };
-
- union
- {
- __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */
-
- struct
- {
- __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1
- * register. */
- __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2
- * register */
- } PERFTRIGGER_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */
-
- struct
- {
- __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */
- uint32_t : 24;
- } TEXCLADDR_b;
- };
-
- union
- {
- __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */
-
- struct
- {
- __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */
- } TEXCLDATA_b;
- };
-
- union
- {
- __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */
-
- struct
- {
- __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0]
- * is or'ed with the original index */
- uint32_t : 24;
- } TEXCLOFFSET_b;
- };
-
- union
- {
- __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */
-
- struct
- {
- __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */
- __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */
- __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */
- uint32_t : 8;
- } COLKEY_b;
- };
-} R_DRW_Type; /*!< Size = 236 (0xec) */
-
-/* =========================================================================================================================== */
-/* ================ R_DTC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Data Transfer Controller (R_DTC)
- */
-
-typedef struct /*!< (@ 0x40005400) R_DTC Structure */
-{
- union
- {
- __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */
- uint8_t : 3;
- } DTCCR_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */
-
- struct
- {
- __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
- * in the lower-order 10 bits. These bits are fixed to 0. */
- } DTCVBR_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */
-
- struct
- {
- __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */
- uint8_t : 7;
- } DTCST_b;
- };
- __IM uint8_t RESERVED3;
-
- union
- {
- __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */
-
- struct
- {
- __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
- * the vector number for the activating source when DTC transfer
- * is in progress.The value is only valid if DTC transfer
- * is in progress (the value of the ACT flag is 1) */
- uint16_t : 7;
- __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */
- } DTCSTS_b;
- };
-
- union
- {
- __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */
- uint8_t : 3;
- } DTCCR_SEC_b;
- };
- __IM uint8_t RESERVED4;
- __IM uint16_t RESERVED5;
- __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */
- __IM uint32_t RESERVED6[2];
-
- union
- {
- __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */
-
- struct
- {
- __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */
- __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */
- uint32_t : 7;
- __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */
- uint32_t : 15;
- } DTEVR_b;
- };
-} R_DTC_Type; /*!< Size = 36 (0x24) */
-
-/* =========================================================================================================================== */
-/* ================ R_ELC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Event Link Controller (R_ELC)
- */
-
- #ifndef BSP_OVERRIDE_REG_R_ELC_TYPE
-
-typedef struct /*!< (@ 0x40041000) R_ELC Structure */
-{
- union
- {
- __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */
- } ELCR_b;
- };
- __IM uint8_t RESERVED;
- __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */
- __IM uint16_t RESERVED1[5];
- __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */
- __IM uint16_t RESERVED2[4];
-
- union
- {
- __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
- * A */
-
- struct
- {
- __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */
- __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
- * Attribution */
- __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
- * Attribution */
- uint16_t : 13;
- } ELCSARA_b;
- };
- __IM uint16_t RESERVED3;
-
- union
- {
- __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
- * B */
-
- struct
- {
- __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */
- __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */
- __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */
- __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */
- __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */
- __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */
- __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */
- __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */
- __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */
- __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */
- __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */
- __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */
- __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */
- __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */
- __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */
- __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */
- } ELCSARB_b;
- };
- __IM uint16_t RESERVED4;
-
- union
- {
- __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
- * C */
-
- struct
- {
- __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */
- __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */
- __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */
- uint16_t : 13;
- } ELCSARC_b;
- };
-} R_ELC_Type; /*!< Size = 126 (0x7e) */
-
- #endif
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Ethernet MAC Controller (R_ETHERC0)
- */
-
-typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */
-{
- union
- {
- __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */
-
- struct
- {
- __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */
- __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */
- __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */
- __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */
- uint32_t : 1;
- __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */
- __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */
- uint32_t : 2;
- __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */
- uint32_t : 2;
- __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */
- uint32_t : 3;
- __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */
- __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */
- __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */
- __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */
- __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */
- uint32_t : 11;
- } ECMR_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */
-
- struct
- {
- __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
- * maximum frame length. The minimum value that can be set
- * is 1,518 bytes, and the maximum value that can be set is
- * 2,048 bytes. Values that are less than 1,518 bytes are
- * regarded as 1,518 bytes, and values larger than 2,048 bytes
- * are regarded as 2,048 bytes. */
- uint32_t : 20;
- } RFLR_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */
-
- struct
- {
- __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */
- __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */
- __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */
- uint32_t : 1;
- __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */
- __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */
- uint32_t : 26;
- } ECSR_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */
- __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */
- __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */
- __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */
- uint32_t : 26;
- } ECSIPR_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */
-
- struct
- {
- __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
- * from the ETn_MDC pin to supply the management data clock
- * to the MII or RMII. */
- __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */
- __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
- * from the ETn_MDIO pin when the MMD bit is 1 (write). The
- * value is not output when the MMD bit is 0 (read). */
- __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
- * of the ETn_MDIO pin. The write value should be 0. */
- uint32_t : 28;
- } PIR_b;
- };
- __IM uint32_t RESERVED4;
-
- union
- {
- __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */
-
- struct
- {
- __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
- * by connecting the link signal output from the PHY-LSI to
- * the ETn_LINKSTA pin. For details on the polarity, refer
- * to the specifications of the connected PHY-LSI. */
- uint32_t : 31;
- } PSR_b;
- };
- __IM uint32_t RESERVED5[5];
-
- union
- {
- __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
- * Setting Register */
-
- struct
- {
- __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */
- uint32_t : 12;
- } RDMLR_b;
- };
- __IM uint32_t RESERVED6[3];
-
- union
- {
- __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */
-
- struct
- {
- __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" */
- uint32_t : 27;
- } IPGR_b;
- };
-
- union
- {
- __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */
-
- struct
- {
- __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
- * of the pause_time parameter for a PAUSE frame that is automatically
- * transmitted. Transmission is not performed until the set
- * value multiplied by 512 bit time has elapsed. */
- uint32_t : 16;
- } APR_b;
- };
-
- union
- {
- __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */
-
- struct
- {
- __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
- * the pause_time parameter for a PAUSE frame that is manually
- * transmitted. Transmission is not performed until the set
- * value multiplied by 512 bit time has elapsed. The read
- * value is undefined. */
- uint32_t : 16;
- } MPR_b;
- };
- __IM uint32_t RESERVED7;
-
- union
- {
- __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */
-
- struct
- {
- __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */
- uint32_t : 24;
- } RFCF_b;
- };
-
- union
- {
- __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */
-
- struct
- {
- __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */
- uint32_t : 16;
- } TPAUSER_b;
- };
- __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */
-
- union
- {
- __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */
-
- struct
- {
- __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */
- uint32_t : 16;
- } BCFRR_b;
- };
- __IM uint32_t RESERVED8[20];
-
- union
- {
- __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */
-
- struct
- {
- __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
- * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */
- } MAHR_b;
- };
- __IM uint32_t RESERVED9;
-
- union
- {
- __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */
-
- struct
- {
- __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
- * the lower 16 bits of the 48-bit MAC address. */
- uint32_t : 16;
- } MALR_b;
- };
- __IM uint32_t RESERVED10;
-
- union
- {
- __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */
-
- struct
- {
- __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
- * is a counter indicating the number of frames that fail
- * to be retransmitted. */
- } TROCR_b;
- };
- __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */
-
- union
- {
- __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */
-
- struct
- {
- __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
- * counter indicating the number of times a loss of carrier
- * is detected during frame transmission. */
- } LCCR_b;
- };
-
- union
- {
- __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */
-
- struct
- {
- __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
- * is a counter indicating the number of times a carrier is
- * not detected during preamble transmission. */
- } CNDCR_b;
- };
- __IM uint32_t RESERVED11;
-
- union
- {
- __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */
-
- struct
- {
- __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
- * is a counter indicating the number of received frames where
- * a CRC error has been detected. */
- } CEFCR_b;
- };
-
- union
- {
- __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */
-
- struct
- {
- __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
- * is a counter indicating the number of times a frame receive
- * error has occurred. */
- } FRECR_b;
- };
-
- union
- {
- __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */
-
- struct
- {
- __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
- * is a counter indicating the number of times a short frame
- * that is shorter than 64 bytes has been received. */
- } TSFRCR_b;
- };
-
- union
- {
- __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */
-
- struct
- {
- __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
- * is a counter indicating the number of times a long frame
- * that is longer than the RFLR register value has been received. */
- } TLFRCR_b;
- };
-
- union
- {
- __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */
-
- struct
- {
- __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
- * register is a counter indicating the number of times a
- * frame has been received with the alignment error (frame
- * is not an integral number of octets). */
- } RFCR_b;
- };
-
- union
- {
- __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */
-
- struct
- {
- __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
- * MAFCR register is a counter indicating the number of times
- * a frame where the multicast address is set has been received. */
- } MAFCR_b;
- };
-} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EDMAC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
- */
-
-typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */
-{
- union
- {
- __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */
-
- struct
- {
- __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */
- uint32_t : 3;
- __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */
- __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
- * applies to data for the transmit/receive buffer. It does
- * not apply to transmit/receive descriptors and registers. */
- uint32_t : 25;
- } EDMR_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */
-
- struct
- {
- __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */
- uint32_t : 31;
- } EDTRR_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */
-
- struct
- {
- __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */
- uint32_t : 31;
- } EDRRR_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */
-
- struct
- {
- __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
- * set. Set the start address according to the descriptor
- * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
- * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
- * boundary: Lower 6 bits = 000000b */
- } TDLAR_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */
-
- struct
- {
- __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
- * set. Set the start address according to the descriptor
- * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
- * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
- * boundary: Lower 6 bits = 000000b */
- } RDLAR_b;
- };
- __IM uint32_t RESERVED4;
-
- union
- {
- __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */
-
- struct
- {
- __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */
- __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */
- __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */
- __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */
- __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */
- uint32_t : 2;
- __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */
- __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */
- __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */
- __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */
- __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */
- uint32_t : 4;
- __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */
- __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */
- __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */
- __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */
- __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */
- __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */
- __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
- * in the ETHERCn.ECSR register is cleared, the ECI flag is
- * also cleared. */
- __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */
- __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */
- __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */
- __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */
- uint32_t : 3;
- __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */
- uint32_t : 1;
- } EESR_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */
- __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */
- __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */
- __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */
- __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */
- uint32_t : 2;
- __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */
- __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */
- __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */
- __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */
- __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */
- uint32_t : 4;
- __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */
- __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */
- __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */
- __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */
- __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */
- __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */
- __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */
- __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */
- __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */
- __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */
- __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */
- uint32_t : 3;
- __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */
- uint32_t : 1;
- } EESIPR_b;
- };
- __IM uint32_t RESERVED6;
-
- union
- {
- __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
- * Register */
-
- struct
- {
- uint32_t : 4;
- __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */
- uint32_t : 2;
- __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */
- uint32_t : 24;
- } TRSCER_b;
- };
- __IM uint32_t RESERVED7;
-
- union
- {
- __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */
-
- struct
- {
- __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
- * frames that are discarded and not transferred to the receive
- * buffer during reception. */
- uint32_t : 16;
- } RMFCR_b;
- };
- __IM uint32_t RESERVED8;
-
- union
- {
- __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */
-
- struct
- {
- __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
- * the set value multiplied by 4. Example: 00Dh: 52 bytes
- * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */
- uint32_t : 21;
- } TFTR_b;
- };
- __IM uint32_t RESERVED9;
-
- union
- {
- __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */
-
- struct
- {
- __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */
- uint32_t : 3;
- __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */
- uint32_t : 19;
- } FDR_b;
- };
- __IM uint32_t RESERVED10;
-
- union
- {
- __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */
-
- struct
- {
- __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */
- uint32_t : 31;
- } RMCR_b;
- };
- __IM uint32_t RESERVED11[2];
-
- union
- {
- __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */
-
- struct
- {
- __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
- * many times the transmit FIFO has underflowed. The counter
- * stops when the counter value reaches FFFFh. */
- uint32_t : 16;
- } TFUCR_b;
- };
-
- union
- {
- __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */
-
- struct
- {
- __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
- * times the receive FIFO has overflowed. The counter stops
- * when the counter value reaches FFFFh. */
- uint32_t : 16;
- } RFOCR_b;
- };
-
- union
- {
- __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */
-
- struct
- {
- __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */
- uint32_t : 31;
- } IOSR_b;
- };
-
- union
- {
- __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */
-
- struct
- {
- __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
- * bytes of data is stored in the receive FIFO.) */
- uint32_t : 13;
- __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
- * receive frames have been stored in the receive FIFO.) */
- uint32_t : 13;
- } FCFTR_b;
- };
- __IM uint32_t RESERVED12;
-
- union
- {
- __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */
-
- struct
- {
- __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */
- uint32_t : 10;
- __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */
- uint32_t : 14;
- } RPADIR_b;
- };
-
- union
- {
- __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */
-
- struct
- {
- __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
- * the mode selected by the TIM bit to notify an interrupt. */
- uint32_t : 3;
- __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */
- uint32_t : 27;
- } TRIMD_b;
- };
- __IM uint32_t RESERVED13[18];
-
- union
- {
- __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */
-
- struct
- {
- __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
- * indicates the last address that the EDMAC has written data
- * to when writing to the receive buffer.Refer to the address
- * indicated by the RBWAR register to recognize which address
- * in the receive buffer the EDMAC is writing data to. Note
- * that the address that the EDMAC is outputting to the receive
- * buffer may not match the read value of the RBWAR register
- * during data reception. */
- } RBWAR_b;
- };
-
- union
- {
- __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */
-
- struct
- {
- __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
- * indicates the start address of the last fetched receive
- * descriptor when the EDMAC fetches descriptor information
- * from the receive descriptor.Refer to the address indicated
- * by the RDFAR register to recognize which receive descriptor
- * information the EDMAC is using for the current processing.
- * Note that the address of the receive descriptor that the
- * EDMAC fetches may not match the read value of the RDFAR
- * register during data reception. */
- } RDFAR_b;
- };
- __IM uint32_t RESERVED14;
-
- union
- {
- __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */
-
- struct
- {
- __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
- * indicates the last address that the EDMAC has read data
- * from when reading data from the transmit buffer.Refer to
- * the address indicated by the TBRAR register to recognize
- * which address in the transmit buffer the EDMAC is reading
- * from. Note that the address that the EDMAC is outputting
- * to the transmit buffer may not match the read value of
- * the TBRAR register. */
- } TBRAR_b;
- };
-
- union
- {
- __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */
-
- struct
- {
- __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
- * register indicates the start address of the last fetched
- * transmit descriptor when the EDMAC fetches descriptor information
- * from the transmit descriptor.Refer to the address indicated
- * by the TDFAR register to recognize which transmit descriptor
- * information the EDMAC is using for the current processing.
- * Note that the address of the transmit descriptor that the
- * EDMAC fetches may not match the read value of the TDFAR
- * register. */
- } TDFAR_b;
- };
-} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Ethernet PTP Controller (R_ETHERC_EPTPC)
- */
-
-typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */
-{
- union
- {
- __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */
-
- struct
- {
- __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */
- __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */
- __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */
- uint32_t : 1;
- __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */
- __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */
- __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */
- uint32_t : 5;
- __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */
- uint32_t : 1;
- __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */
- uint32_t : 1;
- __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */
- __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */
- uint32_t : 14;
- } SYSR_b;
- };
-
- union
- {
- __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */
-
- struct
- {
- __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */
- __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */
- __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */
- uint32_t : 1;
- __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */
- __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */
- __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */
- uint32_t : 5;
- __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */
- uint32_t : 1;
- __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */
- uint32_t : 1;
- __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */
- __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */
- uint32_t : 14;
- } SYIPR_b;
- };
- __IM uint32_t RESERVED[2];
-
- union
- {
- __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */
-
- struct
- {
- __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
- * bits of the local MAC address. */
- uint32_t : 8;
- } SYMACRU_b;
- };
-
- union
- {
- __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */
-
- struct
- {
- __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
- * of the local MAC address. */
- uint32_t : 8;
- } SYMACRL_b;
- };
-
- union
- {
- __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */
-
- struct
- {
- __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the
- * control field in the LLC sublayer when generating IEEE802.3
- * frames. */
- uint32_t : 24;
- } SYLLCCTLR_b;
- };
-
- union
- {
- __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */
-
- struct
- {
- __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */
- } SYIPADDRR_b;
- };
- __IM uint32_t RESERVED1[8];
-
- union
- {
- __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */
-
- struct
- {
- __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the
- * versionPTP field value of the PTP v2 header.When a message
- * is received, this value is compared with the versionPTP
- * field of the received frame.In generating messages, the
- * value is used for the versionPTP field of the frame for
- * transmission.Set these bits to 0010b (PTP v2). */
- __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set
- * the transportSpecific field value of the PTP v2 header.When
- * a message is received, this value is compared with the
- * transportSpecific field of the received frame.In generating
- * messages, the value is used for the transportSpecific field
- * of the frame for transmission.Set these bits to 0000b (IEEE
- * 1588). */
- uint32_t : 24;
- } SYSPVRR_b;
- };
-
- union
- {
- __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */
-
- struct
- {
- __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to
- * set the domainNumber field value of the PTP v2 header.When
- * a message is received, this value is compared with the
- * domainNumber field of the received frame as a condition
- * for PTP reception processing.In generating messages, the
- * value is used for the domainNumber field of the frame for
- * transmission. */
- uint32_t : 24;
- } SYDOMR_b;
- };
- __IM uint32_t RESERVED2[2];
-
- union
- {
- __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */
-
- struct
- {
- __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the
- * leap61 member of timePropertiesDS. */
- __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the
- * leap59 member of timePropertiesDS. */
- __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical
- * value of the currentUtcOffsetValid member of timePropertiesDS. */
- __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value
- * of the ptpTimescale member of timePropertiesDS. */
- __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value
- * of the timeTraceable member of timePropertiesDS. */
- __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical
- * value of the frequencyTraceable member of timePropertiesDS. */
- uint32_t : 2;
- __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */
- uint32_t : 1;
- __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */
- uint32_t : 2;
- __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */
- __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */
- uint32_t : 17;
- } ANFR_b;
- };
-
- union
- {
- __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */
- __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */
- __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */
- uint32_t : 2;
- __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */
- __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */
- uint32_t : 17;
- } SYNFR_b;
- };
-
- union
- {
- __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */
-
- struct
- {
- uint32_t : 10;
- __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */
- uint32_t : 2;
- __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */
- __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */
- uint32_t : 17;
- } DYRQFR_b;
- };
-
- union
- {
- __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */
- __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */
- __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */
- uint32_t : 2;
- __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */
- __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */
- uint32_t : 17;
- } DYRPFR_b;
- };
-
- union
- {
- __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */
-
- struct
- {
- __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the clock-ID of your port. */
- } SYCIDRU_b;
- };
-
- union
- {
- __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */
-
- struct
- {
- __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the clock-ID of your port. */
- } SYCIDRL_b;
- };
-
- union
- {
- __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */
-
- struct
- {
- __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting
- * for the port number of the local port. */
- uint32_t : 16;
- } SYPNUMR_b;
- };
- __IM uint32_t RESERVED3[5];
-
- union
- {
- __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */
-
- struct
- {
- __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */
- __OM uint32_t STUP : 1; /*!< [1..1] State Update */
- __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */
- uint32_t : 29;
- } SYRVLDR_b;
- };
- __IM uint32_t RESERVED4[3];
-
- union
- {
- __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */
-
- struct
- {
- __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */
- __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */
- uint32_t : 2;
- __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */
- __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */
- __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */
- uint32_t : 1;
- __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */
- __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */
- __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */
- uint32_t : 1;
- __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */
- __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */
- __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */
- uint32_t : 1;
- __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */
- __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */
- __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */
- uint32_t : 1;
- __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */
- __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */
- __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */
- uint32_t : 1;
- __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */
- __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */
- __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */
- uint32_t : 1;
- __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */
- __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */
- __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */
- uint32_t : 1;
- } SYRFL1R_b;
- };
-
- union
- {
- __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */
-
- struct
- {
- __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */
- __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */
- uint32_t : 2;
- __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */
- __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */
- uint32_t : 22;
- __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */
- __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */
- uint32_t : 2;
- } SYRFL2R_b;
- };
-
- union
- {
- __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */
-
- struct
- {
- __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */
- uint32_t : 3;
- __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */
- uint32_t : 3;
- __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */
- uint32_t : 3;
- __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */
- uint32_t : 19;
- } SYTRENR_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */
-
- struct
- {
- __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the clock-ID of the master clock. */
- } MTCIDU_b;
- };
-
- union
- {
- __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */
-
- struct
- {
- __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the clock-ID of the master clock. */
- } MTCIDL_b;
- };
-
- union
- {
- __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */
-
- struct
- {
- __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the
- * setting for the port number of the master clock. */
- uint32_t : 16;
- } MTPID_b;
- };
- __IM uint32_t RESERVED6[5];
-
- union
- {
- __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */
-
- struct
- {
- __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits
- * set the interval for the transmission of Announce messages. */
- __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits
- * set the interval for the transmission of Sync messages.
- * The setting is also placed in the logMessageInterval field
- * of transmitted Sync messages. */
- __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req
- * Transmission Interval SettingThe bits set the average interval
- * for the transmission of Delay_Req messages and the interval
- * for the transmission of Pdelay_Req messages.The setting
- * is also placed in the logMessageInterval field of Delay_Resp
- * messages. */
- uint32_t : 8;
- } SYTLIR_b;
- };
-
- union
- {
- __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication
- * Register */
-
- struct
- {
- __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese
- * bits indicate the logMessageInterval field value of a received
- * Announce message. */
- __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese
- * bits indicate the logMessageInterval field value of a received
- * Sync message. */
- __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese
- * bits indicate the logMessageInterval field value of a received
- * Delay_Resp message. */
- uint32_t : 8;
- } SYRLIR_b;
- };
-
- union
- {
- __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */
-
- struct
- {
- __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the
- * calculated offsetFromMaster value. */
- } OFMRU_b;
- };
-
- union
- {
- __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */
-
- struct
- {
- __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
- * offsetFromMaster value. */
- } OFMRL_b;
- };
-
- union
- {
- __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */
-
- struct
- {
- __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the
- * calculated meanPathDelay value. */
- } MPDRU_b;
- };
-
- union
- {
- __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */
-
- struct
- {
- __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
- * meanPathDelay value. */
- } MPDRL_b;
- };
- __IM uint32_t RESERVED7[2];
-
- union
- {
- __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */
-
- struct
- {
- __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are
- * used to set the value of the grandmasterPriority2 fields
- * of Announce messages. */
- uint32_t : 8;
- __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits
- * are used to set the value of the grandmasterPriority1 fields
- * of Announce messages. */
- uint32_t : 8;
- } GMPR_b;
- };
-
- union
- {
- __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */
-
- struct
- {
- __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality
- * fields of Announce messages. The correspondence between
- * bits and the grandmasterClockQuality fields is as listed
- * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15
- * to b0: offsetScaledLogVariance */
- } GMCQR_b;
- };
-
- union
- {
- __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */
-
- struct
- {
- __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the value of the grandmasterIdentity fields of
- * Announce messages. */
- } GMIDRU_b;
- };
-
- union
- {
- __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */
-
- struct
- {
- __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the value of the grandmasterIdentity fields of Announce
- * messages. */
- } GMIDRL_b;
- };
-
- union
- {
- __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */
-
- struct
- {
- __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the
- * timeSource fields of Announce messages. */
- uint32_t : 8;
- __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value
- * of the currentUtcOffset fields of Announce messages. */
- } CUOTSR_b;
- };
-
- union
- {
- __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */
-
- struct
- {
- __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value
- * of the stepsRemoved fields of Announce messages. */
- uint32_t : 16;
- } SRR_b;
- };
- __IM uint32_t RESERVED8[2];
-
- union
- {
- __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting
- * Registers */
-
- struct
- {
- __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
- * bits of the destination MAC address for PTP-primary messages. */
- uint32_t : 8;
- } PPMACRU_b;
- };
-
- union
- {
- __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting
- * Registers */
-
- struct
- {
- __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
- * of the destination MAC address for PTP-primary messages. */
- uint32_t : 8;
- } PPMACRL_b;
- };
-
- union
- {
- __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */
-
- struct
- {
- __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
- * bits of the destination MAC address for PTP-pdelay messages. */
- uint32_t : 8;
- } PDMACRU_b;
- };
-
- union
- {
- __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */
-
- struct
- {
- __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
- * of the destination MAC address for PTP-pdelay messages. */
- uint32_t : 8;
- } PDMACRL_b;
- };
-
- union
- {
- __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */
-
- struct
- {
- __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the
- * setting for the EtherType field value for frames in the
- * Ethernet II format. */
- uint32_t : 16;
- } PETYPER_b;
- };
- __IM uint32_t RESERVED9[3];
-
- union
- {
- __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting
- * Register */
-
- struct
- {
- __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
- * for PTPprimary messages. */
- } PPIPR_b;
- };
-
- union
- {
- __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting
- * Register */
-
- struct
- {
- __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
- * for PTPpdelay messages. */
- } PDIPR_b;
- };
-
- union
- {
- __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */
-
- struct
- {
- __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold
- * the setting for the value of the TOS field within the IPv4
- * headers of PTP event messages. */
- uint32_t : 24;
- } PETOSR_b;
- };
-
- union
- {
- __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */
-
- struct
- {
- __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits
- * hold the setting for the value of the TOS field within
- * the IPv4 headers of PTP general messages. */
- uint32_t : 24;
- } PGTOSR_b;
- };
-
- union
- {
- __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */
-
- struct
- {
- __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits
- * hold the setting for the value of the TTL field within
- * the IPv4 headers of PTP-primary messages. */
- uint32_t : 24;
- } PPTTLR_b;
- };
-
- union
- {
- __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */
-
- struct
- {
- __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the
- * setting for the value of the TTL field within the IPv4
- * headers of PTP-pdelay messages. */
- uint32_t : 24;
- } PDTTLR_b;
- };
-
- union
- {
- __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number
- * Setting Register */
-
- struct
- {
- __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese
- * bits hold the setting for the value of the destination
- * port number field within the UDP headers of PTP event messages. */
- uint32_t : 16;
- } PEUDPR_b;
- };
-
- union
- {
- __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number
- * Setting Register */
-
- struct
- {
- __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits
- * hold the setting for the value of the destination port
- * number field within the UDP headers of PTP general messages. */
- uint32_t : 16;
- } PGUDPR_b;
- };
-
- union
- {
- __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */
-
- struct
- {
- __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these
- * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */
- __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits
- * is only effective when EXTPRM=0 and ENB=1. */
- __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits
- * is only effective when EXTPRM=0. */
- uint32_t : 13;
- __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */
- uint32_t : 15;
- } FFLTR_b;
- };
- __IM uint32_t RESERVED10[7];
-
- union
- {
- __IOM uint32_t FMAC0RU; /*!< (@ 0x00000160) Frame Reception Filter MAC Address 0 Setting
- * Register Upper */
-
- struct
- {
- __IOM uint32_t FMAC0RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
- * MAC address for received multicast frames. */
- uint32_t : 8;
- } FMAC0RU_b;
- };
-
- union
- {
- __IOM uint32_t FMAC0RL; /*!< (@ 0x00000164) Frame Reception Filter MAC Address 0 Setting
- * Register Lower */
-
- struct
- {
- __IOM uint32_t FMAC0RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
- * MAC address for received multicast frames. */
- uint32_t : 8;
- } FMAC0RL_b;
- };
-
- union
- {
- __IOM uint32_t FMAC1RU; /*!< (@ 0x00000168) Frame Reception Filter MAC Address 1 Setting
- * Register Upper */
-
- struct
- {
- __IOM uint32_t FMAC1RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
- * MAC address for received multicast frames. */
- uint32_t : 8;
- } FMAC1RU_b;
- };
-
- union
- {
- __IOM uint32_t FMAC1RL; /*!< (@ 0x0000016C) Frame Reception Filter MAC Address 1 Setting
- * Register Lower */
-
- struct
- {
- __IOM uint32_t FMAC1RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
- * MAC address for received multicast frames. */
- uint32_t : 8;
- } FMAC1RL_b;
- };
- __IM uint32_t RESERVED11[20];
-
- union
- {
- __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */
-
- struct
- {
- __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
- * bits of the asymmetric delay value. */
- uint32_t : 16;
- } DASYMRU_b;
- };
-
- union
- {
- __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */
-
- struct
- {
- __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the asymmetric delay value. */
- } DASYMRL_b;
- };
-
- union
- {
- __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */
-
- struct
- {
- __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold
- * the setting for the time stamp latency (ns) for the input
- * ports. */
- __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold
- * the setting for the time stamp latency (ns) for the output
- * ports. */
- } TSLATR_b;
- };
-
- union
- {
- __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */
-
- struct
- {
- __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are
- * used to set the time from the completion of one transmission
- * to the start of the next in cycles of the transmission
- * clock. A value n in these bits means that a transmission
- * interval of n cycles will be secured.No interval is secured
- * if the setting is 00h.We recommend the setting 28h (40
- * cycles). */
- uint32_t : 4;
- __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */
- uint32_t : 3;
- __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */
- uint32_t : 3;
- __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */
- uint32_t : 11;
- } SYCONFR_b;
- };
-
- union
- {
- __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */
-
- struct
- {
- __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */
- __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */
- uint32_t : 30;
- } SYFORMR_b;
- };
-
- union
- {
- __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */
-
- struct
- {
- __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response
- * message not being received within n x 1024 (ns), where
- * n is the setting, is judged to represent a timeout. */
- } RSTOUTR_b;
- };
-} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC_CFG ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG)
- */
-
-typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */
-{
- union
- {
- __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */
-
- struct
- {
- __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */
- uint32_t : 31;
- } PTRSTR_b;
- };
-
- union
- {
- __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */
-
- struct
- {
- __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */
- uint32_t : 5;
- __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */
- uint32_t : 21;
- } STCSELR_b;
- };
-
- union
- {
- __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */
-
- struct
- {
- __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */
- uint32_t : 15;
- __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */
- uint32_t : 15;
- } BYPASS_b;
- };
-} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC_COMMON ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON)
- */
-
-typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */
-{
- union
- {
- __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */
-
- struct
- {
- __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */
- __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */
- __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */
- __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */
- uint32_t : 12;
- __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */
- __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */
- __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */
- __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */
- __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */
- __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */
- uint32_t : 10;
- } MIESR_b;
- };
-
- union
- {
- __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */
-
- struct
- {
- __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */
- __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */
- __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */
- __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */
- uint32_t : 12;
- __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt
- * Request Permission */
- __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt
- * Request Permission */
- __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt
- * Request Permission */
- __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt
- * Request Permission */
- __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt
- * Request Permission */
- __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt
- * Request Permission */
- uint32_t : 10;
- } MIEIPR_b;
- };
- __IM uint32_t RESERVED[2];
-
- union
- {
- __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission
- * Register */
-
- struct
- {
- __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output
- * Enable */
- uint32_t : 2;
- __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output
- * Enable */
- __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output
- * Enable */
- uint32_t : 2;
- __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt
- * Request Permission */
- uint32_t : 7;
- __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt
- * Request Permission */
- uint32_t : 7;
- } ELIPPR_b;
- };
-
- union
- {
- __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic
- * Clearing Register */
-
- struct
- {
- __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */
- __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */
- __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */
- __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */
- __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */
- __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */
- uint32_t : 2;
- __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */
- __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */
- __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */
- __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */
- __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */
- __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */
- uint32_t : 2;
- __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */
- uint32_t : 7;
- __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */
- uint32_t : 7;
- } ELIPACR_b;
- };
- __IM uint32_t RESERVED1[10];
-
- union
- {
- __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */
-
- struct
- {
- __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */
- __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */
- uint32_t : 1;
- __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */
- __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */
- uint32_t : 27;
- } STSR_b;
- };
-
- union
- {
- __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */
-
- struct
- {
- __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */
- __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */
- uint32_t : 1;
- __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */
- __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */
- uint32_t : 27;
- } STIPR_b;
- };
- __IM uint32_t RESERVED2[2];
-
- union
- {
- __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */
-
- struct
- {
- __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */
- uint32_t : 30;
- } STCFR_b;
- };
-
- union
- {
- __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */
-
- struct
- {
- __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */
- uint32_t : 5;
- __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */
- uint32_t : 1;
- __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */
- __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */
- __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */
- uint32_t : 4;
- __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */
- __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */
- uint32_t : 2;
- } STMR_b;
- };
-
- union
- {
- __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */
-
- struct
- {
- __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns),
- * where n is the setting, leads to a timeout for reception
- * of Sync messages, leading to the STSR.SYNTOUT flag being
- * set to 1. */
- } SYNTOR_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */
-
- struct
- {
- __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */
- __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */
- __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */
- __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */
- __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */
- __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */
- uint32_t : 26;
- } IPTSELR_b;
- };
-
- union
- {
- __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */
-
- struct
- {
- __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */
- __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */
- __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */
- __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */
- __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */
- __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */
- uint32_t : 26;
- } MITSELR_b;
- };
-
- union
- {
- __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */
-
- struct
- {
- __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */
- __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */
- __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */
- __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */
- __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */
- __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */
- uint32_t : 26;
- } ELTSELR_b;
- };
-
- union
- {
- __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */
-
- struct
- {
- __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the
- * value of this bit while the SYNSTARTR.STR bit is 1. */
- uint32_t : 31;
- } STCHSELR_b;
- };
- __IM uint32_t RESERVED4[4];
-
- union
- {
- __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */
-
- struct
- {
- __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */
- uint32_t : 31;
- } SYNSTARTR_b;
- };
-
- union
- {
- __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive
- * Register */
-
- struct
- {
- __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */
- uint32_t : 31;
- } LCIVLDR_b;
- };
- __IM uint32_t RESERVED5[2];
-
- union
- {
- __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */
-
- struct
- {
- __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the threshold for detection of loss of synchronization. */
- } SYNTDARU_b;
- };
-
- union
- {
- __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */
-
- struct
- {
- __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the threshold for detection of loss of synchronization. */
- } SYNTDARL_b;
- };
-
- union
- {
- __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */
-
- struct
- {
- __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
- * bits of the threshold for detection of synchronization. */
- } SYNTDBRU_b;
- };
-
- union
- {
- __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */
-
- struct
- {
- __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the threshold for detection of synchronization. */
- } SYNTDBRL_b;
- };
- __IM uint32_t RESERVED6[4];
-
- union
- {
- __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */
-
- struct
- {
- __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
- * bits of the integer portion of the initial value for the
- * local timer counter. */
- uint32_t : 16;
- } LCIVRU_b;
- };
-
- union
- {
- __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */
-
- struct
- {
- __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the integer portion of the initial value for the local
- * timer counter. */
- } LCIVRM_b;
- };
-
- union
- {
- __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */
-
- struct
- {
- __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion
- * of the initial value of the local timer counter in nanoseconds. */
- } LCIVRL_b;
- };
- __IM uint32_t RESERVED7[26];
-
- union
- {
- __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */
-
- struct
- {
- __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */
- uint32_t : 31;
- } GETW10R_b;
- };
-
- union
- {
- __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
- * bits of the limit for the positive gradient. */
- uint32_t : 1;
- } PLIMITRU_b;
- };
-
- union
- {
- __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
- * bits of the limit for the positive gradient. */
- } PLIMITRM_b;
- };
-
- union
- {
- __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the limit for the positive gradient. */
- } PLIMITRL_b;
- };
-
- union
- {
- __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
- * bits of the limit for the negative gradient. */
- uint32_t : 1;
- } MLIMITRU_b;
- };
-
- union
- {
- __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
- * bits of the limit for the negative gradient. */
- } MLIMITRM_b;
- };
-
- union
- {
- __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */
-
- struct
- {
- __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
- * of the limit for the negative gradient. */
- } MLIMITRL_b;
- };
-
- union
- {
- __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */
-
- struct
- {
- __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching
- * is directed, values of various statistical information
- * read before completion of information fetching are not
- * guaranteed. */
- uint32_t : 31;
- } GETINFOR_b;
- };
- __IM uint32_t RESERVED8[11];
-
- union
- {
- __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */
-
- struct
- {
- __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits
- * of the integer portion of the local timer counter's value. */
- uint32_t : 16;
- } LCCVRU_b;
- };
-
- union
- {
- __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */
-
- struct
- {
- __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
- * the integer portion of the local timer counter's value. */
- } LCCVRM_b;
- };
-
- union
- {
- __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */
-
- struct
- {
- __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of
- * the local timer counter's value (in nanoseconds). */
- } LCCVRL_b;
- };
- __IM uint32_t RESERVED9[37];
-
- union
- {
- __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
- * of the positive gradient value. */
- } PW10VRU_b;
- };
-
- union
- {
- __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
- * of the positive gradient value. */
- } PW10VRM_b;
- };
-
- union
- {
- __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
- * the positive gradient value. */
- } PW10VRL_b;
- };
- __IM uint32_t RESERVED10[45];
-
- union
- {
- __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
- * of the negative gradient value. */
- } MW10RU_b;
- };
-
- union
- {
- __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
- * of the negative gradient value. */
- } MW10RM_b;
- };
-
- union
- {
- __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */
-
- struct
- {
- __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
- * the negative gradient value. */
- } MW10RL_b;
- };
- __IM uint32_t RESERVED11[9];
- __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */
- __IM uint32_t RESERVED12[7];
-
- union
- {
- __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */
-
- struct
- {
- __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */
- __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */
- __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */
- __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */
- __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */
- __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */
- uint32_t : 26;
- } TMSTARTR_b;
- };
- __IM uint32_t RESERVED13[32];
-
- union
- {
- __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */
-
- struct
- {
- __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */
- __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */
- __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */
- __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */
- uint32_t : 4;
- __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */
- uint32_t : 19;
- __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */
- __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */
- uint32_t : 2;
- } PRSR_b;
- };
-
- union
- {
- __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */
-
- struct
- {
- __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */
- __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */
- __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */
- __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */
- uint32_t : 4;
- __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */
- uint32_t : 19;
- __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */
- __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */
- uint32_t : 2;
- } PRIPR_b;
- };
- __IM uint32_t RESERVED14[2];
- __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */
-
- union
- {
- __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */
-
- struct
- {
- __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */
- uint32_t : 30;
- } TRNDISR_b;
- };
- __IM uint32_t RESERVED15[3];
-
- union
- {
- __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */
-
- struct
- {
- __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */
- uint32_t : 7;
- __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */
- __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */
- uint32_t : 22;
- } TRNMR_b;
- };
-
- union
- {
- __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */
-
- struct
- {
- __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read
- * data from the relay FIFO in cut-through mode (specified
- * as the number of bytes)NOTE1: A value cannot be set in
- * the lower-order 2 bits. These bits are fixed to 0.NOTE2:
- * A value of less than 96 bytes cannot be set. */
- uint32_t : 21;
- } TRNCTTDR_b;
- };
-} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_HP_CMD ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
- */
-
-typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */
-{
- union
- {
- __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
- __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
- };
-} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_HP ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Flash Application Command Interface (R_FACI_HP)
- */
-
-typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */
-{
- __IM uint32_t RESERVED[4];
-
- union
- {
- __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */
-
- struct
- {
- __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */
- uint8_t : 2;
- __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */
- __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */
- uint8_t : 2;
- __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */
- } FASTAT_b;
- };
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */
-
- struct
- {
- __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */
- uint8_t : 2;
- __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */
- __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */
- uint8_t : 2;
- __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */
- } FAEINT_b;
- };
- __IM uint8_t RESERVED3;
- __IM uint16_t RESERVED4;
-
- union
- {
- __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */
-
- struct
- {
- __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */
- uint8_t : 7;
- } FRDYIE_b;
- };
- __IM uint8_t RESERVED5;
- __IM uint16_t RESERVED6;
- __IM uint32_t RESERVED7[5];
-
- union
- {
- __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */
-
- struct
- {
- __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area
- * These bits can be written when FRDY bit of FSTATR register
- * is "1". Writing to these bits in FRDY = "0" is ignored. */
- } FSADDR_b;
- };
-
- union
- {
- __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */
-
- struct
- {
- __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
- * end address of target area in "Blank Check" command. These
- * bits can be written when FRDY bit of FSTATR register is
- * "1". Writing to these bits in FRDY = "0" is ignored. */
- } FEADDR_b;
- };
- __IM uint32_t RESERVED8[3];
-
- union
- {
- __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */
-
- struct
- {
- __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
- * is only possible when the FRDY bit in the FSTATR register
- * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
- * to this bit is only possible when 16 bits are written and
- * the value written to the KEY bits is D9h.Written values
- * are not retained by these bits (always read as 0x00).Only
- * secure access can write to this register. Both secure access
- * and non-secure read access are allowed. Non-secure writeaccess
- * is denied, but Trust */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FMEPROT_b;
- };
- __IM uint16_t RESERVED9;
- __IM uint32_t RESERVED10[12];
-
- union
- {
- __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */
-
- struct
- {
- __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
- * written when the FRDY bit in the FSTATR register is 1.
- * Writing to this bit is ignored when the FRDY bit is 0.Writing
- * to this bit is only possible when 16 bits are written and
- * the value written to the KEY[7:0] bits is 0x78.Written
- * values are not retained by these bits (always read as 0x00). */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FBPROT0_b;
- };
- __IM uint16_t RESERVED11;
-
- union
- {
- __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */
-
- struct
- {
- __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit
- * is only possible when the FRDY bit in the FSTATR register
- * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
- * to this bit is only possible when 16 bits are written and
- * the value written to the KEY[7:0] bits is 0xB1.Written
- * values are not retained by these bits (always read as 0x00). */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FBPROT1_b;
- };
- __IM uint16_t RESERVED12;
-
- union
- {
- __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */
-
- struct
- {
- uint32_t : 6;
- __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */
- uint32_t : 1;
- __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */
- __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */
- __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */
- __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */
- __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */
- __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */
- __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */
- __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */
- uint32_t : 4;
- __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */
- __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */
- __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */
- __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */
- uint32_t : 8;
- } FSTATR_b;
- };
-
- union
- {
- __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */
-
- struct
- {
- __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
- * FRDY bit in FSTATR register is "1". Writing to this bit
- * in FRDY = "0" is ignored. Writing to these bits is enabled
- * only when this register is accessed in 16-bit size and
- * H'AA is written to KEY bits */
- uint16_t : 6;
- __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
- * FRDY bit in FSTATR register is "1". Writing to this bit
- * in FRDY = "0" is ignored. Writing to these bits is enabled
- * only when this register is accessed in 16-bit size and
- * H'AA is written to KEY bits. */
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FENTRYR_b;
- };
- __IM uint16_t RESERVED13;
- __IM uint32_t RESERVED14;
-
- union
- {
- __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */
-
- struct
- {
- __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
- * bit of FSTATR register is "1". Writing to this bit in FRDY
- * = "0" is ignored. Writing to these bits is enabled only
- * when this register is accessed in 16-bit size and H'2D
- * is written to KEY bits. */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FSUINITR_b;
- };
- __IM uint16_t RESERVED15;
- __IM uint32_t RESERVED16[4];
-
- union
- {
- __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */
-
- struct
- {
- __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */
- __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */
- } FCMDR_b;
- };
- __IM uint16_t RESERVED17;
- __IM uint32_t RESERVED18[7];
-
- union
- {
- __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */
-
- struct
- {
- __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */
- uint16_t : 8;
- } FPESTAT_b;
- };
- __IM uint16_t RESERVED19;
- __IM uint32_t RESERVED20[3];
-
- union
- {
- __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */
-
- struct
- {
- __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */
- uint8_t : 7;
- } FBCCNT_b;
- };
- __IM uint8_t RESERVED21;
- __IM uint16_t RESERVED22;
-
- union
- {
- __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */
-
- struct
- {
- __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */
- uint8_t : 7;
- } FBCSTAT_b;
- };
- __IM uint8_t RESERVED23;
- __IM uint16_t RESERVED24;
-
- union
- {
- __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */
-
- struct
- {
- __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
- * of the first programmed data which is found in "Blank Check"
- * command execution. */
- uint32_t : 13;
- } FPSADDR_b;
- };
-
- union
- {
- __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */
-
- struct
- {
- __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
- * indicate the start sector address for setting the access
- * window that is located in the configuration area. */
- uint32_t : 4;
- __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot
- * Flag and Temporary Boot Swap Control and "Config Clear"
- * command execution */
- __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits
- * indicate the end sector address for setting the access
- * window that is located in the configuration area. */
- uint32_t : 4;
- __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */
- } FAWMON_b;
- };
-
- union
- {
- __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */
-
- struct
- {
- __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */
- uint16_t : 15;
- } FCPSR_b;
- };
- __IM uint16_t RESERVED25;
-
- union
- {
- __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */
-
- struct
- {
- __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
- * can be written when FRDY bit in FSTATR register is "1".
- * Writing to this bit in FRDY = "0" is ignored. Writing to
- * these bits is enabled only when this register is accessed
- * in 16-bit size and H'1E is written to KEY bits. */
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FPCKAR_b;
- };
- __IM uint16_t RESERVED26;
-
- union
- {
- __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */
-
- struct
- {
- __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY
- * bit in FSTATR register is "1". Writing to this bit in FRDY
- * = "0" is ignored. Writing to these bits is enabled only
- * when this register is accessed in 16-bit size and H'66
- * is written to KEY bits. */
- uint16_t : 6;
- __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
- } FSUACR_b;
- };
- __IM uint16_t RESERVED27;
-} R_FACI_HP_Type; /*!< Size = 236 (0xec) */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_LP ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Flash Application Command Interface (R_FACI_LP)
- */
-
-typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */
-{
- __IM uint32_t RESERVED[36];
- __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2;
- __IM uint32_t RESERVED3[27];
-
- union
- {
- __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */
-
- struct
- {
- uint8_t : 1;
- __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
- * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
- * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */
- uint8_t : 1;
- __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */
- __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to
- * the description of the FMS0 bit. */
- uint8_t : 1;
- __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */
- __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
- * of the FMS0 bit. */
- } FPMCR_b;
- };
- __IM uint8_t RESERVED4;
- __IM uint16_t RESERVED5;
-
- union
- {
- __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */
-
- struct
- {
- __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */
- uint8_t : 7;
- } FASR_b;
- };
- __IM uint8_t RESERVED6;
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */
-
- struct
- {
- __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */
- } FSARL_b;
- };
- __IM uint16_t RESERVED8;
- __IM uint32_t RESERVED9;
-
- union
- {
- __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */
-
- struct
- {
- __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */
- uint16_t : 4;
- __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */
- } FSARH_b;
- };
- __IM uint16_t RESERVED10;
-
- union
- {
- __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */
-
- struct
- {
- __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */
- __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */
- uint8_t : 1;
- __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */
- __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */
- } FCR_b;
- };
- __IM uint8_t RESERVED11;
- __IM uint16_t RESERVED12;
-
- union
- {
- __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */
-
- struct
- {
- __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */
- } FEARL_b;
- };
- __IM uint16_t RESERVED13;
- __IM uint32_t RESERVED14;
-
- union
- {
- __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */
-
- struct
- {
- __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */
- uint32_t : 4;
- __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */
- uint32_t : 16;
- } FEARH_b;
- };
-
- union
- {
- __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */
-
- struct
- {
- __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */
- uint32_t : 31;
- } FRESETR_b;
- };
-
- union
- {
- __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */
-
- struct
- {
- __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */
- __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */
- __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */
- __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */
- __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */
- __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */
- uint32_t : 26;
- } FSTATR00_b;
- };
-
- union
- {
- __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */
-
- struct
- {
- uint32_t : 1;
- __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */
- uint32_t : 4;
- __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */
- __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */
- uint32_t : 24;
- } FSTATR1_b;
- };
-
- union
- {
- __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */
-
- struct
- {
- __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */
- uint32_t : 16;
- } FWBL0_b;
- };
- __IM uint32_t RESERVED15;
-
- union
- {
- __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */
-
- struct
- {
- __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */
- uint32_t : 16;
- } FWBH0_b;
- };
-
- union
- {
- __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */
-
- struct
- {
- __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */
- __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */
- uint32_t : 1;
- __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */
- uint32_t : 28;
- } FSTATR01_b;
- };
-
- union
- {
- __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */
-
- struct
- {
- __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */
- uint32_t : 16;
- } FWBL1_b;
- };
-
- union
- {
- __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */
-
- struct
- {
- __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */
- uint32_t : 16;
- } FWBH1_b;
- };
-
- union
- {
- __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */
-
- struct
- {
- __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */
- uint32_t : 16;
- } FRBL1_b;
- };
-
- union
- {
- __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */
-
- struct
- {
- __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */
- uint32_t : 16;
- } FRBH1_b;
- };
- __IM uint32_t RESERVED16[12];
-
- union
- {
- __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */
-
- struct
- {
- __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */
- uint32_t : 24;
- } FPR_b;
- };
-
- union
- {
- __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */
-
- struct
- {
- __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */
- uint32_t : 31;
- } FPSR_b;
- };
-
- union
- {
- __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */
-
- struct
- {
- __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */
- uint32_t : 16;
- } FRBL0_b;
- };
- __IM uint32_t RESERVED17;
-
- union
- {
- __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */
-
- struct
- {
- __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */
- uint32_t : 16;
- } FRBH0_b;
- };
- __IM uint32_t RESERVED18[11];
-
- union
- {
- __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */
-
- struct
- {
- uint32_t : 8;
- __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */
- uint32_t : 5;
- __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */
- uint32_t : 17;
- } FSCMR_b;
- };
- __IM uint32_t RESERVED19;
-
- union
- {
- __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */
-
- struct
- {
- __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */
- uint32_t : 20;
- } FAWSMR_b;
- };
- __IM uint32_t RESERVED20;
-
- union
- {
- __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */
-
- struct
- {
- __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */
- uint32_t : 20;
- } FAWEMR_b;
- };
- __IM uint32_t RESERVED21;
-
- union
- {
- __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */
-
- struct
- {
- __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */
- __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */
- uint32_t : 24;
- } FISR_b;
- };
-
- union
- {
- __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */
-
- struct
- {
- __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */
- uint32_t : 4;
- __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */
- uint32_t : 24;
- } FEXCR_b;
- };
-
- union
- {
- __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */
-
- struct
- {
- __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */
- uint32_t : 16;
- } FEAML_b;
- };
- __IM uint32_t RESERVED22;
-
- union
- {
- __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */
-
- struct
- {
- __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */
- uint32_t : 16;
- } FEAMH_b;
- };
- __IM uint32_t RESERVED23;
-
- union
- {
- __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */
-
- struct
- {
- __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */
- __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */
- __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */
- __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */
- __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */
- __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */
- uint32_t : 26;
- } FSTATR2_b;
- };
- __IM uint32_t RESERVED24[3951];
- __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */
- __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */
- __IM uint32_t RESERVED25[3];
- __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */
- __IM uint8_t RESERVED26;
- __IM uint16_t RESERVED27;
- __IM uint32_t RESERVED28;
- __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */
- __IM uint8_t RESERVED29;
- __IM uint16_t RESERVED30;
-} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSUTRIM ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief CTSU Trimming Registers (R_CTSUTRIM)
- */
-
-typedef struct /*!< (@ 0x407EC000) R_CTSUTRIM Structure */
-{
- __IM uint32_t RESERVED[233];
-
- union
- {
- __IOM uint32_t CTSUTRIMA; /*!< (@ 0x000003A4) CTSU Trimming Register A */
-
- struct
- {
- __IOM uint32_t RTRIM : 8; /*!< [7..0] CTSU Reference Resistance Adjustment */
- __IOM uint32_t DACTRIM : 8; /*!< [15..8] Linearity Adjustment of Offset Current */
- __IOM uint32_t SUADJD : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */
- __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
- * (120k) */
- } CTSUTRIMA_b;
- };
-
- union
- {
- __IOM uint32_t CTSUTRIMB; /*!< (@ 0x000003A8) CTSU Trimming Register B */
-
- struct
- {
- __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance
- * (7.5k) */
- __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance
- * (15k) */
- __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance
- * (30k) */
- __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
- * (60k) */
- } CTSUTRIMB_b;
- };
-} R_CTSUTRIM_Type; /*!< Size = 940 (0x3ac) */
-
-/* =========================================================================================================================== */
-/* ================ R_FCACHE ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Flash Memory Cache (R_FCACHE)
- */
-
-typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */
-{
- __IM uint16_t RESERVED[128];
-
- union
- {
- __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */
-
- struct
- {
- __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */
- uint16_t : 15;
- } FCACHEE_b;
- };
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */
-
- struct
- {
- __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */
- uint16_t : 15;
- } FCACHEIV_b;
- };
- __IM uint16_t RESERVED2[11];
-
- union
- {
- __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */
-
- struct
- {
- __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */
- uint8_t : 5;
- } FLWT_b;
- };
- __IM uint8_t RESERVED3;
- __IM uint16_t RESERVED4[17];
-
- union
- {
- __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */
-
- struct
- {
- __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */
- uint16_t : 7;
- __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */
- uint16_t : 7;
- } FSAR_b;
- };
-} R_FCACHE_Type; /*!< Size = 322 (0x142) */
-
-/* =========================================================================================================================== */
-/* ================ R_GLCDC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Graphics LCD Controller (R_GLCDC)
- */
-
-typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */
-{
- union
- {
- __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */
-
- struct
- {
- __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
- * m Plane */
- } GR1_CLUT0_b[256];
- };
-
- union
- {
- __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */
-
- struct
- {
- __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
- * m Plane */
- } GR1_CLUT1_b[256];
- };
-
- union
- {
- __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */
-
- struct
- {
- __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
- * m Plane */
- } GR2_CLUT0_b[256];
- };
-
- union
- {
- __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */
-
- struct
- {
- __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */
- __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
- * m Plane */
- } GR2_CLUT1_b[256];
- };
- __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */
- __IM uint32_t RESERVED[57];
- __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */
- __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */
- __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */
- __IM uint32_t RESERVED1[6];
- __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */
- __IM uint32_t RESERVED2[5];
- __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */
-} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief General PWM Timer (R_GPT0)
- */
-
-typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */
-{
- union
- {
- __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */
-
- struct
- {
- __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */
- __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */
- __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */
- __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */
- __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */
- uint32_t : 3;
- __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */
- uint32_t : 16;
- } GTWP_b;
- };
-
- union
- {
- __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */
-
- struct
- {
- __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter stop. 1
- * means counter running. */
- uint32_t : 18;
- } GTSTR_b;
- };
-
- union
- {
- __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */
-
- struct
- {
- __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
- * counter status (GTCR.CST bit). 0 means counter runnning.
- * 1 means counter stop. */
- uint32_t : 18;
- } GTSTP_b;
- };
-
- union
- {
- __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */
-
- struct
- {
- __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */
- __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */
- __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */
- __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */
- __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */
- __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */
- __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */
- __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */
- __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */
- __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */
- __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */
- __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */
- __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */
- __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */
- uint32_t : 18;
- } GTCLR_b;
- };
-
- union
- {
- __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */
-
- struct
- {
- __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */
- __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */
- __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * Counter Start Enable */
- __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * Counter Start Enable */
- __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * Counter Start Enable */
- __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * Counter Start Enable */
- __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * Counter Start Enable */
- __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * Counter Start Enable */
- __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * Counter Start Enable */
- __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * Counter Start Enable */
- __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */
- __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */
- uint32_t : 7;
- __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */
- } GTSSR_b;
- };
-
- union
- {
- __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */
-
- struct
- {
- __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */
- __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */
- __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * Counter Stop Enable */
- __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * Counter Stop Enable */
- __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * Counter Stop Enable */
- __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * Counter Stop Enable */
- __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * Counter Stop Enable */
- __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * Counter Stop Enable */
- __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * Counter Stop Enable */
- __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * Counter Stop Enable */
- __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */
- __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */
- uint32_t : 7;
- __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */
- } GTPSR_b;
- };
-
- union
- {
- __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */
-
- struct
- {
- __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */
- __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */
- __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * Counter Clear Enable */
- __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * Counter Clear Enable */
- __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * Counter Clear Enable */
- __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * Counter Clear Enable */
- __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * Counter Clear Enable */
- __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * Counter Clear Enable */
- __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * Counter Clear Enable */
- __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * Counter Clear Enable */
- __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */
- __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */
- uint32_t : 7;
- __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */
- } GTCSR_b;
- };
-
- union
- {
- __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */
-
- struct
- {
- __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */
- __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */
- __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * Counter Count Up Enable */
- __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * Counter Count Up Enable */
- __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * Counter Count Up Enable */
- __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * Counter Count Up Enable */
- __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * Counter Count Up Enable */
- __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * Counter Count Up Enable */
- __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * Counter Count Up Enable */
- __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * Counter Count Up Enable */
- __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */
- __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */
- uint32_t : 4;
- } GTUPSR_b;
- };
-
- union
- {
- __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */
-
- struct
- {
- __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */
- __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */
- __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * Counter Count Down Enable */
- __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * Counter Count Down Enable */
- __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */
- __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */
- uint32_t : 4;
- } GTDNSR_b;
- };
-
- union
- {
- __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
- * Register A */
-
- struct
- {
- __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
- * Enable */
- __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
- * Enable */
- __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
- * Enable */
- __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
- * Enable */
- __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */
- __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */
- uint32_t : 8;
- } GTICASR_b;
- };
-
- union
- {
- __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
- * Register B */
-
- struct
- {
- __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
- * Enable */
- __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
- * Enable */
- __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
- * Enable */
- __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
- * Enable */
- __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
- * GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */
- __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */
- uint32_t : 8;
- } GTICBSR_b;
- };
-
- union
- {
- __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */
-
- struct
- {
- __IOM uint32_t CST : 1; /*!< [0..0] Count Start */
- uint32_t : 15;
- __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */
- uint32_t : 4;
- __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */
- uint32_t : 5;
- } GTCR_b;
- };
-
- union
- {
- __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
- * Register */
-
- struct
- {
- __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */
- __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */
- uint32_t : 14;
- __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */
- __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */
- __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
- * percent Duty Setting */
- uint32_t : 4;
- __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */
- __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */
- __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
- * percent Duty Setting */
- uint32_t : 4;
- } GTUDDTYC_b;
- };
-
- union
- {
- __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */
-
- struct
- {
- __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */
- uint32_t : 1;
- __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */
- __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */
- __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */
- __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */
- uint32_t : 2;
- __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */
- __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */
- __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */
- uint32_t : 1;
- __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */
- __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */
- __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */
- __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */
- uint32_t : 2;
- __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */
- __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */
- } GTIOR_b;
- };
-
- union
- {
- __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */
-
- struct
- {
- uint32_t : 24;
- __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */
- uint32_t : 2;
- __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */
- __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
- __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
- __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */
- } GTINTAD_b;
- };
-
- union
- {
- __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */
-
- struct
- {
- __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */
- __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */
- __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */
- __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */
- __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */
- __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */
- __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */
- __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */
- __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
- * for counting the number of times a timer interrupt has
- * been skipped.) */
- uint32_t : 4;
- __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */
- __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
- * Request Interrupt Enable */
- __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
- * Start Request Flag */
- __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
- * Request Flag */
- __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
- * Start Request Flag */
- uint32_t : 4;
- __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */
- uint32_t : 3;
- __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */
- __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
- __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
- __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */
- } GTST_b;
- };
-
- union
- {
- __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */
-
- struct
- {
- __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */
- __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */
- __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */
- __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */
- uint32_t : 12;
- __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */
- __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */
- __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */
- __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
- * is read as 0. */
- uint32_t : 1;
- __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
- * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
- * at an underflow (in down-counting) or overflow (in up-counting)
- * is performed. */
- __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */
- uint32_t : 1;
- __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
- * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
- * at an underflow (in down-counting) or overflow (in up-counting)
- * is performed. */
- __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */
- uint32_t : 1;
- } GTBER_b;
- };
-
- union
- {
- __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
- * Start Request Skipping Setting Register */
-
- struct
- {
- __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */
- __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */
- __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */
- __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */
- __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */
- __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */
- __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */
- __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */
- uint32_t : 1;
- __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */
- uint32_t : 1;
- __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */
- uint32_t : 17;
- } GTITC_b;
- };
-
- union
- {
- __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */
-
- struct
- {
- __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */
- } GTCNT_b;
- };
-
- union
- {
- __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */
-
- struct
- {
- __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */
- } GTCCR_b[6];
- };
-
- union
- {
- __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */
-
- struct
- {
- __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */
- } GTPR_b;
- };
-
- union
- {
- __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */
-
- struct
- {
- __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */
- } GTPBR_b;
- };
-
- union
- {
- __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
- * Register */
-
- struct
- {
- __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */
- } GTPDBR_b;
- };
-
- union
- {
- __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */
-
- struct
- {
- __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */
- } GTADTRA_b;
- };
-
- union
- {
- __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
- * A */
-
- struct
- {
- __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */
- } GTADTBRA_b;
- };
-
- union
- {
- __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
- * Register A */
-
- struct
- {
- __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
- * A */
- } GTADTDBRA_b;
- };
-
- union
- {
- __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */
-
- struct
- {
- __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */
- } GTADTRB_b;
- };
-
- union
- {
- __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
- * B */
-
- struct
- {
- __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */
- } GTADTBRB_b;
- };
-
- union
- {
- __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
- * Register B */
-
- struct
- {
- __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
- * B */
- } GTADTDBRB_b;
- };
-
- union
- {
- __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */
-
- struct
- {
- __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */
- uint32_t : 3;
- __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */
- __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */
- uint32_t : 2;
- __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */
- uint32_t : 23;
- } GTDTCR_b;
- };
-
- union
- {
- __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */
-
- struct
- {
- __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */
- } GTDVU_b;
- };
-
- union
- {
- __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */
-
- struct
- {
- __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */
- } GTDVD_b;
- };
-
- union
- {
- __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */
-
- struct
- {
- __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */
- } GTDBU_b;
- };
-
- union
- {
- __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */
-
- struct
- {
- __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */
- } GTDBD_b;
- };
-
- union
- {
- __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
- * Status Register */
-
- struct
- {
- __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */
- uint32_t : 30;
- } GTSOS_b;
- };
-
- union
- {
- __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
- * Temporary Release Register */
-
- struct
- {
- __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */
- uint32_t : 31;
- } GTSOTR_b;
- };
- __IM uint32_t RESERVED[5];
-
- union
- {
- __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
- * Function Setting Register */
-
- struct
- {
- __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */
- uint32_t : 1;
- __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */
- uint32_t : 6;
- __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */
- uint32_t : 1;
- __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */
- uint32_t : 6;
- } GTICLF_b;
- };
-
- union
- {
- __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */
-
- struct
- {
- __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */
- uint32_t : 7;
- __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */
- uint32_t : 7;
- __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */
- uint32_t : 4;
- } GTPC_b;
- };
- __IM uint32_t RESERVED1[4];
-
- union
- {
- __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
- * Control Channel Select Register */
-
- struct
- {
- __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
- * Select */
- __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
- * Select */
- uint32_t : 22;
- } GTSECSR_b;
- };
-
- union
- {
- __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
- * Control Register */
-
- struct
- {
- __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */
- __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */
- uint32_t : 6;
- __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */
- __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */
- uint32_t : 6;
- __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */
- uint32_t : 7;
- __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */
- uint32_t : 7;
- } GTSECR_b;
- };
-} R_GPT0_Type; /*!< Size = 216 (0xd8) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_GTCLK ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief GTCLK (R_GPT_GTCLK)
- */
-
-typedef struct /*!< (@ 0x40169B00) R_GPT_GTCLK Structure */
-{
- union
- {
- __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */
-
- struct
- {
- __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */
- uint32_t : 31;
- } GTCLKCR_b;
- };
-} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_ODC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief PWM Delay Generation Circuit (R_GPT_ODC)
- */
-
-typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */
-{
- union
- {
- __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */
-
- struct
- {
- __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */
- __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */
- uint16_t : 6;
- __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */
- uint16_t : 7;
- } GTDLYCR1_b;
- };
-
- union
- {
- __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */
-
- struct
- {
- __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */
- __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */
- __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */
- __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */
- uint16_t : 4;
- __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */
- __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */
- __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */
- __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */
- __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */
- uint16_t : 3;
- } GTDLYCR2_b;
- };
- __IM uint16_t RESERVED[10];
- __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */
- __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */
-} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_OPS ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Output Phase Switching for GPT (R_GPT_OPS)
- */
-
-typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */
-{
- union
- {
- __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */
-
- struct
- {
- __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
- * by the software settings.This bit setting is valid when
- * the OPSCR.FB bit = 1. */
- __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
- * by the software settings.This bit setting is valid when
- * the OPSCR.FB bit = 1. */
- __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
- * by the software settings.This bit setting is valid when
- * the OPSCR.FB bit = 1. */
- uint32_t : 1;
- __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
- * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
- * e settings (UF/VF/WF) */
- __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
- * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
- * e settings (UF/VF/WF) */
- __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
- * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
- * e settings (UF/VF/WF) */
- uint32_t : 1;
- __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */
- uint32_t : 7;
- __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the
- * input phase from the software settings and external input. */
- __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */
- __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */
- __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */
- __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */
- __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */
- uint32_t : 2;
- __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */
- __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */
- uint32_t : 2;
- __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */
- __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
- * sampling clock setting of the external input. */
- } OPSCR_b;
- };
-} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_POEG0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Port Output Enable for GPT (R_GPT_POEG0)
- */
-
-typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */
-{
- union
- {
- __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */
-
- struct
- {
- __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */
- __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */
- __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */
- __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */
- __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only
- * once after a reset. */
- __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
- * only once after a reset. */
- __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
- * only once after a reset. */
- uint32_t : 1;
- __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
- * only once after a reset. */
- uint32_t : 2;
- __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */
- uint32_t : 11;
- __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */
- __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */
- __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */
- } POEGG_b;
- };
-} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */
-
-/* =========================================================================================================================== */
-/* ================ R_ICU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Interrupt Controller Unit (R_ICU)
- */
-
-typedef struct /*!< (@ 0x40006000) R_ICU Structure */
-{
- union
- {
- __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */
-
- struct
- {
- __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */
- uint8_t : 2;
- __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */
- uint8_t : 1;
- __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */
- } IRQCR_b[16];
- };
- __IM uint32_t RESERVED[60];
-
- union
- {
- __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */
-
- struct
- {
- __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */
- uint8_t : 3;
- __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */
- uint8_t : 1;
- __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */
- } NMICR_b;
- };
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2;
- __IM uint32_t RESERVED3[7];
-
- union
- {
- __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */
- __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */
- __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */
- __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */
- __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */
- __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */
- __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */
- __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */
- __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */
- __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */
- __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */
- __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */
- uint16_t : 1;
- __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */
- } NMIER_b;
- };
- __IM uint16_t RESERVED4;
- __IM uint32_t RESERVED5[3];
-
- union
- {
- __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */
-
- struct
- {
- __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */
- __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */
- __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */
- __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */
- __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */
- uint16_t : 1;
- __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */
- __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */
- __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */
- __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */
- __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */
- __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */
- __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */
- __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */
- uint16_t : 1;
- __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */
- } NMICLR_b;
- };
- __IM uint16_t RESERVED6;
- __IM uint32_t RESERVED7[3];
-
- union
- {
- __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */
-
- struct
- {
- __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */
- __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */
- __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */
- __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */
- __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */
- uint16_t : 1;
- __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */
- __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */
- __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */
- __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */
- __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */
- __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */
- __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */
- __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */
- uint16_t : 1;
- __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */
- } NMISR_b;
- };
- __IM uint16_t RESERVED8;
- __IM uint32_t RESERVED9[23];
-
- union
- {
- __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */
- __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */
- __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */
- __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */
- __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */
- __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */
- uint32_t : 1;
- __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */
- __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */
- __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */
- __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */
- __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */
- __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */
- __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */
- __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
- * enable */
- __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
- * enable */
- __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */
- } WUPEN_b;
- };
-
- union
- {
- __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */
-
- struct
- {
- __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */
- __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
- * bit */
- __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
- * bit */
- uint32_t : 29;
- } WUPEN1_b;
- };
- __IM uint32_t RESERVED10[6];
-
- union
- {
- __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */
-
- struct
- {
- __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
- * = 1) */
- __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
- * LPOPTEN bit = 1) */
- uint8_t : 6;
- } IELEN_b;
- };
- __IM uint8_t RESERVED11;
- __IM uint16_t RESERVED12;
- __IM uint32_t RESERVED13[15];
-
- union
- {
- __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */
-
- struct
- {
- __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */
- uint16_t : 7;
- } SELSR0_b;
- };
- __IM uint16_t RESERVED14;
- __IM uint32_t RESERVED15[31];
-
- union
- {
- __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */
-
- struct
- {
- __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */
- uint32_t : 7;
- __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
- * IR flag is prohibited. */
- uint32_t : 15;
- } DELSR_b[8];
- };
- __IM uint32_t RESERVED16[24];
-
- union
- {
- __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */
-
- struct
- {
- __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event
- * signal to be linked . */
- uint32_t : 7;
- __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */
- uint32_t : 7;
- __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */
- uint32_t : 7;
- } IELSR_b[96];
- };
-} R_ICU_Type; /*!< Size = 1152 (0x480) */
-
-/* =========================================================================================================================== */
-/* ================ R_IIC0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I2C Bus Interface (R_IIC0)
- */
-
-typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */
-{
- union
- {
- __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */
-
- struct
- {
- __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */
- __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */
- __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */
- __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */
- __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */
- __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */
- __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
- * is initiated using the IICRST bit for a bus hang-up occurred
- * during communication with the master device in slave mode,
- * the states may become different between the slave device
- * and the master device (due to the difference in the bit
- * counter information). */
- __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */
- } ICCR1_b;
- };
-
- union
- {
- __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */
-
- struct
- {
- uint8_t : 1;
- __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
- * condition issuance request) when the BBSY flag is set to
- * 0 (bus free state). */
- __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
- * RS bit to 1 while issuing a stop condition. */
- __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
- * bit is not possible while the setting of the BBSY flag
- * is 0 (bus free state).Note: Do not set the SP bit to 1
- * while a restart condition is being issued. */
- uint8_t : 1;
- __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */
- __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */
- __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */
- } ICCR2_b;
- };
-
- union
- {
- __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */
-
- struct
- {
- __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */
- __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */
- __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
- * / 2^CKS ) */
- __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */
- } ICMR1_b;
- };
-
- union
- {
- __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */
-
- struct
- {
- __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */
- __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */
- __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */
- uint8_t : 1;
- __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */
- __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */
- } ICMR2_b;
- };
-
- union
- {
- __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */
-
- struct
- {
- __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */
- __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */
- __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */
- __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */
- __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */
- __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
- * be sure to read the ICDRR beforehand. */
- __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */
- } ICMR3_b;
- };
-
- union
- {
- __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */
-
- struct
- {
- __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */
- __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */
- __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */
- __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */
- __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */
- __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */
- __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */
- __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */
- } ICFER_b;
- };
-
- union
- {
- __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */
-
- struct
- {
- __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */
- __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */
- __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */
- __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */
- uint8_t : 1;
- __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */
- uint8_t : 1;
- __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */
- } ICSER_b;
- };
-
- union
- {
- __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */
-
- struct
- {
- __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */
- __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */
- __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */
- __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */
- __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */
- __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */
- __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */
- __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */
- } ICIER_b;
- };
-
- union
- {
- __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */
-
- struct
- {
- __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */
- __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */
- __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */
- __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */
- uint8_t : 1;
- __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */
- uint8_t : 1;
- __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */
- } ICSR1_b;
- };
-
- union
- {
- __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */
-
- struct
- {
- __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */
- __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */
- __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */
- __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */
- __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */
- __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */
- __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */
- __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
- } ICSR2_b;
- };
- __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */
-
- union
- {
- __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */
-
- struct
- {
- __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */
- uint8_t : 3;
- } ICBRL_b;
- };
-
- union
- {
- __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */
-
- struct
- {
- __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */
- uint8_t : 3;
- } ICBRH_b;
- };
-
- union
- {
- __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */
-
- struct
- {
- __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */
- } ICDRT_b;
- };
-
- union
- {
- __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */
-
- struct
- {
- __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */
- } ICDRR_b;
- };
- __IM uint8_t RESERVED[2];
-
- union
- {
- __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */
-
- struct
- {
- __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */
- uint8_t : 3;
- __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */
- __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */
- __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */
- __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */
- } ICWUR_b;
- };
-
- union
- {
- __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */
-
- struct
- {
- __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */
- __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */
- __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */
- uint8_t : 5;
- } ICWUR2_b;
- };
-} R_IIC0_Type; /*!< Size = 24 (0x18) */
-
-/* =========================================================================================================================== */
-/* ================ R_IRDA ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief IrDA Interface (R_IRDA)
- */
-
-typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */
-{
- union
- {
- __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */
-
- struct
- {
- uint8_t : 2;
- __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */
- __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */
- uint8_t : 3;
- __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */
- } IRCR_b;
- };
-} R_IRDA_Type; /*!< Size = 1 (0x1) */
-
-/* =========================================================================================================================== */
-/* ================ R_IWDT ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Independent Watchdog Timer (R_IWDT)
- */
-
-typedef struct /*!< (@ 0x40044400) R_IWDT Structure */
-{
- union
- {
- __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */
-
- struct
- {
- __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
- * 0xFF to this register. */
- } IWDTRR_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */
-
- struct
- {
- __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */
- __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
- __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
- } IWDTSR_b;
- };
-} R_IWDT_Type; /*!< Size = 6 (0x6) */
-
-/* =========================================================================================================================== */
-/* ================ R_JPEG ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief JPEG Codec (R_JPEG)
- */
-
-typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */
-{
- union
- {
- __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */
-
- struct
- {
- __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */
- __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between
- * processing for compression and for decompression, be sure
- * to reset this module in advance by setting the JCUSRST
- * bit in the software reset control register 2 (SWRSTCR2)
- * of the power-downmodes. */
- uint8_t : 4;
- } JCMOD_b;
- };
-
- union
- {
- __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */
-
- struct
- {
- __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing,
- * set this bit to 1. Do not write this bit to 1 again while
- * this module is in operation. */
- __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped
- * state caused by requests to read the image size and pixel
- * format (enabled by the INT3 bit in JINTE0), set this bit
- * to 1. */
- __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only
- * for the interrupt sources corresponding to bits INS6, INS5,
- * and INS3 in JINTS0. To clear an interrupt request, set
- * this bit to 1 */
- uint8_t : 4;
- __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the
- * bus reset command should not be issued. */
- } JCCMD_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */
-
- struct
- {
- __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE:
- * Read-only in Decompression. */
- __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component
- * NOTE: Read-only in Decompression. */
- __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component
- * NOTE: Read-only in Decompression. */
- uint8_t : 2;
- } JCQTN_b;
- };
-
- union
- {
- __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */
-
- struct
- {
- __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component
- * NOTE: Read-only in Decompression. */
- __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE:
- * Read-only in Decompression. */
- __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component
- * NOTE: Read-only in Decompression. */
- __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE:
- * Read-only in Decompression. */
- __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component
- * NOTE: Read-only in Decompression. */
- __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE:
- * Read-only in Decompression. */
- uint8_t : 2;
- } JCHTN_b;
- };
-
- union
- {
- __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */
-
- struct
- {
- __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper
- * and lower bytes are set to 00h, neither a DRI nor an RST
- * marker is placed.NOTE: Read-only in Decompression. */
- } JCDRIU_b;
- };
-
- union
- {
- __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */
-
- struct
- {
- __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper
- * and lower bytes are set to 00h, neither a DRI nor an RST
- * marker is placed.NOTE: Read-only in Decompression. */
- } JCDRID_b;
- };
-
- union
- {
- __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */
-
- struct
- {
- __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process,
- * a downloaded value from the JPEG coded data is set. NOTE:
- * Read-only in Decompression. */
- } JCVSZU_b;
- };
-
- union
- {
- __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */
-
- struct
- {
- __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process,
- * a downloaded value from the JPEG coded data is set. NOTE:
- * Read-only in Decompression. */
- } JCVSZD_b;
- };
-
- union
- {
- __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */
-
- struct
- {
- __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression
- * process, a downloaded value from the JPEG coded data is
- * set. NOTE: Read-only in Decompression. */
- } JCHSZU_b;
- };
-
- union
- {
- __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */
-
- struct
- {
- __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression
- * process, a downloaded value from the JPEG coded data is
- * set. NOTE: Read-only in Decompression. */
- } JCHSZD_b;
- };
-
- union
- {
- __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */
-
- struct
- {
- __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed
- * The values of this register are reset before compression
- * starts.NOTE: Read-only in Decompression. */
- } JCDTCU_b;
- };
-
- union
- {
- __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */
-
- struct
- {
- __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe
- * values of this register are reset before compression starts.
- * NOTE: Read-only in Decompression. */
- } JCDTCM_b;
- };
-
- union
- {
- __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */
-
- struct
- {
- __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe
- * values of this register are reset before compression starts.NOTE:
- * Read-only in Decompression. */
- } JCDTCD_b;
- };
-
- union
- {
- __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */
-
- struct
- {
- uint8_t : 3;
- __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it
- * has been determined that the image size and the subsampling
- * setting of the compressed data can be read through analyzing
- * the data. */
- uint8_t : 1;
- __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the
- * final number of MCU data in the Huffman-coding segment
- * is not correct in decompression. When this bit is not set
- * to enable interrupt generation, an error code is not returned. */
- __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the
- * total number of data in the Huffman-coding segment is not
- * correct in decompression. When this bit is not set to enable
- * interrupt generation, an error code is not returned. */
- __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the
- * number of data in the restart interval of the Huffman-coding
- * segment is not correct in decompression.When this bit is
- * not set to enable interrupt generation, an error code is
- * not returned. */
- } JINTE0_b;
- };
-
- union
- {
- __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */
-
- struct
- {
- uint8_t : 3;
- __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format
- * can be read. When an interrupt occurs, this module stops
- * processing and the state is indicated by the JCRST register.
- * To make this module resume processing, set the JPEG core
- * process stop clear command bit (JRST) in JCCMD. */
- uint8_t : 1;
- __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */
- __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression
- * process normally. */
- uint8_t : 1;
- } JINTS0_b;
- };
-
- union
- {
- __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */
-
- struct
- {
- __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error
- * which has occurred in the compressed data analysis for
- * decompression. */
- uint8_t : 4;
- } JCDERR_b;
- };
-
- union
- {
- __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */
-
- struct
- {
- __IM uint8_t RST : 1; /*!< [0..0] Operating State */
- uint8_t : 7;
- } JCRST_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[11];
-
- union
- {
- __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */
-
- struct
- {
- __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */
- uint32_t : 1;
- __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */
- __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid
- * only when the count mode for stopping the input of image
- * data lines is on. Setting this bit to 1 resumes reading
- * input image data. This bit is always read as 0. */
- __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data
- * Lines This bit is only valid when the count mode for stopping
- * the input of image data lines is on. Set this bit before
- * writing 1 to the data-line resume command bit. */
- uint32_t : 1;
- __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression
- * is swapped. */
- uint32_t : 21;
- } JIFECNT_b;
- };
-
- union
- {
- __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */
-
- struct
- {
- __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The
- * lower three bits should be set to 0. */
- } JIFESA_b;
- };
-
- union
- {
- __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */
-
- struct
- {
- __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower
- * three bits should be set to 0. */
- uint32_t : 17;
- } JIFESOFST_b;
- };
-
- union
- {
- __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address
- * Register */
-
- struct
- {
- __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The
- * lower three bits should be set to 0. */
- } JIFEDA_b;
- };
-
- union
- {
- __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count
- * Register */
-
- struct
- {
- __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line
- * units) The lower three bits should be set to 0. */
- uint32_t : 16;
- } JIFESLC_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */
-
- struct
- {
- __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is
- * swapped. */
- uint32_t : 1;
- __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */
- __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid
- * only when the count mode for stopping the output of image
- * data lines is on. Setting this bit to 1 resumes writing
- * image data. This bit is always read as 0. */
- __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image
- * Data Lines This bit is only valid when the count mode for
- * stopping the output of image data lines is on. Set this
- * bit before writing 1 to the data-line resume command bit. */
- uint32_t : 1;
- __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression
- * is swapped. */
- uint32_t : 1;
- __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */
- __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only
- * when the count mode for stopping the input of coded data
- * is on. Setting this bit to 1 resumes reading input coded
- * data. This bit is always read as 0. */
- __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed
- * This bit is only valid when the count mode for stopping
- * the input of coded data is on. Set this bit before writing
- * 1 to the data resume command bit. */
- uint32_t : 9;
- __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */
- __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output
- * image data. */
- __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image
- * data. */
- uint32_t : 2;
- } JIFDCNT_b;
- };
-
- union
- {
- __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */
-
- struct
- {
- __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source
- * Address (in 8-byte units) The lower three bits should be
- * set to 0. */
- } JIFDSA_b;
- };
-
- union
- {
- __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */
-
- struct
- {
- __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The
- * lower three bits should be set to 0. */
- uint32_t : 17;
- } JIFDDOFST_b;
- };
-
- union
- {
- __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address
- * Register */
-
- struct
- {
- __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units)
- * The lower three bits should be set to 0. */
- } JIFDDA_b;
- };
-
- union
- {
- __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count
- * Register */
-
- struct
- {
- __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units)
- * The lower three bits should be set to 0. */
- uint32_t : 16;
- } JIFDSDC_b;
- };
-
- union
- {
- __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line
- * Count Register */
-
- struct
- {
- __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three
- * bits should be set to 0. These bits are read as0.Number
- * of input image data lines to be read, in 8-line units. */
- uint32_t : 16;
- } JIFDDLC_b;
- };
-
- union
- {
- __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */
-
- struct
- {
- __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */
- uint32_t : 24;
- } JIFDADT_b;
- };
- __IM uint32_t RESERVED4[6];
-
- union
- {
- __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */
-
- struct
- {
- __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt
- * request (JDTI) when the DOUTLF bit in JINTS1 is set to
- * 1 */
- __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt
- * request (JDTI) when the JINF bit in JINTS1 is set to 1. */
- __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt
- * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */
- uint32_t : 2;
- __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt
- * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */
- __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt
- * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */
- uint32_t : 25;
- } JINTE1_b;
- };
-
- union
- {
- __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */
-
- struct
- {
- __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number
- * of lines of output image data indicated by JIFDDLC have
- * been written. This bit is only valid when the DOUTLC bit
- * in JIFDCNT is set to 1. */
- __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data
- * indicated by JIFDSDC is read in decompression. This bit
- * is valid only when the JINC bit in JIFDCNT is set to 1. */
- __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data
- * is written in decompression. */
- uint32_t : 2;
- __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data
- * lines indicated by JIFESLC is read in compression. This
- * bit is valid only when the DINLC bit in JIFECNT is set
- * to 1. */
- __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data
- * is written in compression. */
- uint32_t : 25;
- } JINTS1_b;
- };
- __IM uint32_t RESERVED5[27];
- __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */
- __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */
- __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */
- __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */
- __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */
- __IM uint32_t RESERVED6;
- __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */
- __IM uint16_t RESERVED7;
- __IM uint32_t RESERVED8[11];
- __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */
- __IM uint32_t RESERVED9;
- __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */
- __IM uint16_t RESERVED10;
-} R_JPEG_Type; /*!< Size = 980 (0x3d4) */
-
-/* =========================================================================================================================== */
-/* ================ R_KINT ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Key Interrupt Function (R_KINT)
- */
-
-typedef struct /*!< (@ 0x40080000) R_KINT Structure */
-{
- union
- {
- __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */
-
- struct
- {
- __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */
- uint8_t : 6;
- __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */
- } KRCTL_b;
- };
- __IM uint8_t RESERVED[3];
-
- union
- {
- __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */
-
- struct
- {
- __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */
- __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */
- __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */
- __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */
- __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */
- __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */
- __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */
- __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */
- } KRF_b;
- };
- __IM uint8_t RESERVED1[3];
-
- union
- {
- __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */
-
- struct
- {
- __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */
- __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */
- __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */
- __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */
- __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */
- __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */
- __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */
- __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */
- } KRM_b;
- };
-} R_KINT_Type; /*!< Size = 9 (0x9) */
-
-/* =========================================================================================================================== */
-/* ================ R_I3C0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I3C Bus Interface (R_I3C0)
- */
-
-typedef struct /*!< (@ 0x40083000) R_I3C0 Structure */
-{
- union
- {
- __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */
-
- struct
- {
- __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */
- uint32_t : 31;
- } PRTS_b;
- };
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */
-
- struct
- {
- __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */
- uint32_t : 31;
- } CECTL_b;
- };
-
- union
- {
- __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */
-
- struct
- {
- __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */
- uint32_t : 6;
- __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */
- __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */
- uint32_t : 20;
- __IOM uint32_t ABT : 1; /*!< [29..29] Abort */
- __IOM uint32_t RSM : 1; /*!< [30..30] Resume */
- __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */
- } BCTL_b;
- };
-
- union
- {
- __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */
- uint32_t : 8;
- __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */
- } MSDVAD_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */
-
- struct
- {
- __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */
- __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */
- __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */
- __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */
- __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */
- __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */
- __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */
- uint32_t : 9;
- __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */
- uint32_t : 15;
- } RSTCTL_b;
- };
-
- union
- {
- __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */
-
- struct
- {
- uint32_t : 2;
- __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */
- uint32_t : 1;
- __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */
- uint32_t : 2;
- __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */
- uint32_t : 24;
- } PRSST_b;
- };
- __IM uint32_t RESERVED2[2];
-
- union
- {
- __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */
-
- struct
- {
- uint32_t : 10;
- __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */
- uint32_t : 21;
- } INST_b;
- };
-
- union
- {
- __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */
-
- struct
- {
- uint32_t : 10;
- __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */
- uint32_t : 21;
- } INSTE_b;
- };
-
- union
- {
- __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */
-
- struct
- {
- uint32_t : 10;
- __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */
- uint32_t : 21;
- } INIE_b;
- };
-
- union
- {
- __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */
-
- struct
- {
- uint32_t : 10;
- __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */
- uint32_t : 21;
- } INSTFC_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */
-
- struct
- {
- uint32_t : 19;
- __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */
- uint32_t : 8;
- } DVCT_b;
- };
- __IM uint32_t RESERVED4[4];
-
- union
- {
- __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */
-
- struct
- {
- __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */
- __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */
- uint32_t : 1;
- __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */
- uint32_t : 28;
- } IBINCTL_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */
-
- struct
- {
- __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */
- __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */
- __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */
- uint32_t : 5;
- __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */
- uint32_t : 3;
- __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */
- uint32_t : 1;
- __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */
- __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */
- uint32_t : 16;
- } BFCTL_b;
- };
-
- union
- {
- __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */
-
- struct
- {
- __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */
- uint32_t : 4;
- __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */
- __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */
- uint32_t : 8;
- __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */
- __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */
- uint32_t : 15;
- } SVCTL_b;
- };
- __IM uint32_t RESERVED6[2];
-
- union
- {
- __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */
-
- struct
- {
- __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */
- uint32_t : 29;
- } REFCKCTL_b;
- };
-
- union
- {
- __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */
-
- struct
- {
- __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */
- __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */
- __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */
- uint32_t : 2;
- __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */
- uint32_t : 1;
- __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */
- } STDBR_b;
- };
-
- union
- {
- __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */
-
- struct
- {
- __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */
- __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */
- __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */
- uint32_t : 2;
- __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */
- uint32_t : 2;
- } EXTBR_b;
- };
-
- union
- {
- __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */
-
- struct
- {
- __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */
- uint32_t : 23;
- } BFRECDT_b;
- };
-
- union
- {
- __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */
-
- struct
- {
- __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */
- uint32_t : 23;
- } BAVLCDT_b;
- };
-
- union
- {
- __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */
-
- struct
- {
- __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */
- uint32_t : 14;
- } BIDLCDT_b;
- };
-
- union
- {
- __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */
-
- struct
- {
- __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */
- __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */
- __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */
- uint32_t : 1;
- __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */
- uint32_t : 3;
- __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */
- uint32_t : 4;
- __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */
- uint32_t : 16;
- } OUTCTL_b;
- };
-
- union
- {
- __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */
-
- struct
- {
- __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */
- __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */
- uint32_t : 27;
- } INCTL_b;
- };
-
- union
- {
- __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */
-
- struct
- {
- __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */
- uint32_t : 2;
- __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */
- __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */
- __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */
- uint32_t : 24;
- } TMOCTL_b;
- };
- __IM uint32_t RESERVED7[3];
-
- union
- {
- __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */
-
- struct
- {
- __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */
- __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */
- __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */
- uint32_t : 29;
- } ACKCTL_b;
- };
-
- union
- {
- __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */
-
- struct
- {
- __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */
- __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */
- uint32_t : 30;
- } SCSTRCTL_b;
- };
- __IM uint32_t RESERVED8[2];
-
- union
- {
- __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */
-
- struct
- {
- __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */
- uint32_t : 12;
- __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */
- __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */
- __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */
- __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */
- } SCSTLCTL_b;
- };
- __IM uint32_t RESERVED9[3];
-
- union
- {
- __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */
- } SVTDLG0_b;
- };
- __IM uint32_t RESERVED10[31];
-
- union
- {
- __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */
-
- struct
- {
- __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */
- __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */
- __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */
- uint32_t : 29;
- } CNDCTL_b;
- };
- __IM uint32_t RESERVED11[3];
- __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */
- __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */
- __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */
- __IM uint32_t RESERVED12[8];
- __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */
- __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */
- __IM uint32_t RESERVED13[3];
-
- union
- {
- __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */
-
- struct
- {
- __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */
- __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */
- __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */
- __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */
- } NQTHCTL_b;
- };
-
- union
- {
- __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
- * Register 0 */
-
- struct
- {
- __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */
- uint32_t : 5;
- __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */
- uint32_t : 5;
- __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */
- uint32_t : 5;
- __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */
- uint32_t : 5;
- } NTBTHCTL0_b;
- };
- __IM uint32_t RESERVED14[10];
-
- union
- {
- __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
- * Register */
-
- struct
- {
- __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */
- uint32_t : 24;
- } NRQTHCTL_b;
- };
- __IM uint32_t RESERVED15[3];
-
- union
- {
- __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */
-
- struct
- {
- __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */
- __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */
- __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */
- uint32_t : 1;
- __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */
- uint32_t : 3;
- __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */
- uint32_t : 7;
- __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */
- uint32_t : 3;
- __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */
- uint32_t : 11;
- } BST_b;
- };
-
- union
- {
- __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */
-
- struct
- {
- __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */
- __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */
- __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */
- uint32_t : 1;
- __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */
- uint32_t : 3;
- __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */
- uint32_t : 7;
- __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */
- uint32_t : 3;
- __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */
- uint32_t : 11;
- } BSTE_b;
- };
-
- union
- {
- __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */
- __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */
- __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */
- uint32_t : 1;
- __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */
- uint32_t : 3;
- __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */
- uint32_t : 7;
- __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */
- uint32_t : 3;
- __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */
- uint32_t : 11;
- } BIE_b;
- };
-
- union
- {
- __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */
-
- struct
- {
- __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */
- __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */
- __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */
- uint32_t : 1;
- __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */
- uint32_t : 3;
- __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */
- uint32_t : 7;
- __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */
- uint32_t : 3;
- __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */
- uint32_t : 11;
- } BSTFC_b;
- };
-
- union
- {
- __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */
-
- struct
- {
- __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */
- __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */
- __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */
- __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */
- __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */
- __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */
- uint32_t : 3;
- __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */
- uint32_t : 10;
- __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */
- uint32_t : 11;
- } NTST_b;
- };
-
- union
- {
- __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */
-
- struct
- {
- __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */
- __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */
- __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */
- __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */
- __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */
- __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */
- uint32_t : 3;
- __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */
- uint32_t : 10;
- __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */
- uint32_t : 11;
- } NTSTE_b;
- };
-
- union
- {
- __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */
- __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */
- __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */
- __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */
- __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */
- __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */
- uint32_t : 3;
- __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */
- uint32_t : 10;
- __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */
- uint32_t : 11;
- } NTIE_b;
- };
-
- union
- {
- __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */
-
- struct
- {
- __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */
- __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */
- __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */
- __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */
- __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */
- __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */
- uint32_t : 3;
- __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */
- uint32_t : 10;
- __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */
- uint32_t : 11;
- } NTSTFC_b;
- };
- __IM uint32_t RESERVED16[8];
-
- union
- {
- __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */
-
- struct
- {
- __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */
- __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */
- __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */
- uint32_t : 29;
- } BCST_b;
- };
-
- union
- {
- __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */
-
- struct
- {
- __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */
- uint32_t : 4;
- __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */
- __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */
- uint32_t : 8;
- __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */
- __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */
- uint32_t : 15;
- } SVST_b;
- };
- __IM uint32_t RESERVED17[3];
-
- union
- {
- __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */
-
- struct
- {
- __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
- uint32_t : 5;
- __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
- __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
- __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
- __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
- __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
- uint32_t : 5;
- __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
- __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
- } DATBAS0_b;
- };
- __IM uint32_t RESERVED18;
-
- union
- {
- __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */
-
- struct
- {
- __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
- uint32_t : 5;
- __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
- __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
- __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
- __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
- __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
- uint32_t : 5;
- __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
- __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
- } DATBAS1_b;
- };
- __IM uint32_t RESERVED19;
-
- union
- {
- __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */
-
- struct
- {
- __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
- uint32_t : 5;
- __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
- __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
- __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
- __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
- __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
- uint32_t : 5;
- __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
- __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
- } DATBAS2_b;
- };
- __IM uint32_t RESERVED20;
-
- union
- {
- __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */
-
- struct
- {
- __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
- uint32_t : 5;
- __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
- __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
- __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
- __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
- __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
- uint32_t : 5;
- __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
- __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
- } DATBAS3_b;
- };
- __IM uint32_t RESERVED21[24];
-
- union
- {
- __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */
-
- struct
- {
- __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */
- uint32_t : 9;
- __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */
- uint32_t : 5;
- __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */
- __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */
- } EXDATBAS_b;
- };
- __IM uint32_t RESERVED22[3];
-
- union
- {
- __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */
-
- struct
- {
- __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
- __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
- uint32_t : 1;
- __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
- uint32_t : 3;
- __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
- uint32_t : 9;
- } SDATBAS0_b;
- };
-
- union
- {
- __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */
-
- struct
- {
- __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
- __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
- uint32_t : 1;
- __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
- uint32_t : 3;
- __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
- uint32_t : 9;
- } SDATBAS1_b;
- };
-
- union
- {
- __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */
-
- struct
- {
- __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
- __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
- uint32_t : 1;
- __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
- uint32_t : 3;
- __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
- uint32_t : 9;
- } SDATBAS2_b;
- };
- __IM uint32_t RESERVED23[5];
-
- union
- {
- __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
- __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
- __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
- __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
- uint32_t : 2;
- __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
- uint32_t : 16;
- } MSDCT0_b;
- };
-
- union
- {
- __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
- __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
- __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
- __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
- uint32_t : 2;
- __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
- uint32_t : 16;
- } MSDCT1_b;
- };
-
- union
- {
- __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
- __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
- __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
- __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
- uint32_t : 2;
- __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
- uint32_t : 16;
- } MSDCT2_b;
- };
-
- union
- {
- __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
- __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
- __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
- __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
- uint32_t : 2;
- __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
- uint32_t : 16;
- } MSDCT3_b;
- };
- __IM uint32_t RESERVED24[16];
-
- union
- {
- __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */
-
- struct
- {
- __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */
- __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
- __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */
- __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */
- __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */
- uint32_t : 2;
- __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */
- uint32_t : 16;
- } SVDCT_b;
- };
- __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
- * ID Low Register */
- __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
- * ID High Register */
- __IM uint32_t RESERVED25;
-
- union
- {
- __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */
-
- struct
- {
- uint32_t : 16;
- __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */
- uint32_t : 1;
- __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */
- uint32_t : 2;
- __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */
- __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */
- } SVDVAD0_b;
- };
- __IM uint32_t RESERVED26[7];
-
- union
- {
- __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */
-
- struct
- {
- __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */
- __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */
- uint32_t : 1;
- __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */
- uint32_t : 28;
- } CSECMD_b;
- };
-
- union
- {
- __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */
-
- struct
- {
- __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */
- uint32_t : 28;
- } CEACTST_b;
- };
-
- union
- {
- __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */
-
- struct
- {
- __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */
- uint32_t : 16;
- } CMWLG_b;
- };
-
- union
- {
- __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */
-
- struct
- {
- __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */
- __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */
- uint32_t : 8;
- } CMRLG_b;
- };
-
- union
- {
- __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */
-
- struct
- {
- __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */
- uint32_t : 24;
- } CETSTMD_b;
- };
-
- union
- {
- __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */
-
- struct
- {
- __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */
- uint32_t : 1;
- __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */
- __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device’s current Activity Mode */
- __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */
- uint32_t : 16;
- } CGDVST_b;
- };
-
- union
- {
- __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */
-
- struct
- {
- __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */
- uint32_t : 29;
- } CMDSPW_b;
- };
-
- union
- {
- __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */
-
- struct
- {
- __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */
- __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */
- uint32_t : 26;
- } CMDSPR_b;
- };
-
- union
- {
- __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */
-
- struct
- {
- __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */
- uint32_t : 7;
- __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */
- } CMDSPT_b;
- };
-
- union
- {
- __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
- * Register */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */
- __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */
- uint32_t : 8;
- } CETSM_b;
- };
- __IM uint32_t RESERVED27[2];
-
- union
- {
- __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */
-
- struct
- {
- __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */
- uint32_t : 2;
- __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */
- uint32_t : 24;
- } BITCNT_b;
- };
- __IM uint32_t RESERVED28[4];
-
- union
- {
- __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */
-
- struct
- {
- __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */
- __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */
- __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */
- __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */
- uint32_t : 3;
- } NQSTLV_b;
- };
-
- union
- {
- __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */
-
- struct
- {
- __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */
- __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */
- uint32_t : 16;
- } NDBSTLV0_b;
- };
- __IM uint32_t RESERVED29[9];
-
- union
- {
- __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */
-
- struct
- {
- __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */
- uint32_t : 24;
- } NRSQSTLV_b;
- };
- __IM uint32_t RESERVED30[2];
-
- union
- {
- __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */
-
- struct
- {
- __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */
- __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */
- __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */
- __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */
- uint32_t : 28;
- } PRSTDBG_b;
- };
-
- union
- {
- __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */
-
- struct
- {
- __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */
- uint32_t : 24;
- } MSERRCNT_b;
- };
-} R_I3C0_Type; /*!< Size = 980 (0x3d4) */
-
-/* =========================================================================================================================== */
-/* ================ R_MMF ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Memory Mirror Function (R_MMF)
- */
-
-typedef struct /*!< (@ 0x40001000) R_MMF Structure */
-{
- union
- {
- __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */
-
- struct
- {
- uint32_t : 7;
- __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot
- * be set in the low-order 7 bits. These bits are fixed to
- * 0. */
- uint32_t : 1;
- __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */
- } MMSFR_b;
- };
-
- union
- {
- __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */
-
- struct
- {
- __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */
- uint32_t : 23;
- __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */
- } MMEN_b;
- };
-} R_MMF_Type; /*!< Size = 8 (0x8) */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_MMPU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Bus Master MPU (R_MPU_MMPU)
- */
-
-typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */
-{
- __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */
-} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_SMPU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Bus Slave MPU (R_MPU_SMPU)
- */
-
-typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */
-{
- union
- {
- __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */
-
- struct
- {
- __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */
- __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */
- uint16_t : 6;
- __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting
- * of the PROTECT and OAD bit. */
- } SMPUCTL_b;
- };
- __IM uint16_t RESERVED[7];
- __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */
-} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_SPMON ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
- */
-
-typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */
-{
- __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */
-} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */
-
-/* =========================================================================================================================== */
-/* ================ R_MSTP ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief System-Module Stop (R_MSTP)
- */
-
-typedef struct /*!< (@ 0x40047000) R_MSTP Structure */
-{
- union
- {
- __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */
-
- struct
- {
- __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */
- uint32_t : 6;
- __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */
- uint32_t : 14;
- __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */
- uint32_t : 9;
- } MSTPCRA_b;
- };
-
- union
- {
- __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */
-
- struct
- {
- uint32_t : 1;
- __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */
- __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */
- __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */
- __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */
- __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */
- __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */
- __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */
- __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */
- __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */
- __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */
- __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */
- uint32_t : 2;
- __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */
- __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */
- uint32_t : 2;
- __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */
- __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */
- __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */
- __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */
- __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */
- __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */
- __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */
- __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */
- __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */
- __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */
- } MSTPCRB_b;
- };
-
- union
- {
- __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */
-
- struct
- {
- __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */
- __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */
- __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */
- __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */
- __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */
- __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */
- __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */
- __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */
- __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */
- __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */
- __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */
- __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */
- __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */
- uint32_t : 5;
- __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */
- __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */
- uint32_t : 5;
- __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */
- __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */
- uint32_t : 2;
- __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */
- } MSTPCRC_b;
- };
-
- union
- {
- __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */
-
- struct
- {
- __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module
- * Stop */
- __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module
- * Stop */
- __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state
- * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
- * In case the count source is sub-clock or LOCO, this bit
- * should be set to 1 except when accessing the registers
- * of AGT1. */
- __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state
- * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
- * In case the count source is sub-clock or LOCO, this bit
- * should be set to 1 except when accessing the registers
- * of AGT0. */
- uint32_t : 1;
- __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */
- __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */
- uint32_t : 4;
- __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */
- __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */
- __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */
- __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */
- __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */
- __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */
- __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */
- __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */
- __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */
- __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */
- __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */
- __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */
- __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */
- __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */
- __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */
- uint32_t : 1;
- __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */
- } MSTPCRD_b;
- };
-
- union
- {
- __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */
-
- struct
- {
- uint32_t : 4;
- __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */
- uint32_t : 9;
- __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module
- * Stop */
- __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module
- * Stop */
- uint32_t : 6;
- __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */
- __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */
- __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */
- __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */
- __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */
- __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */
- __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */
- __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */
- __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */
- __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */
- } MSTPCRE_b;
- };
-} R_MSTP_Type; /*!< Size = 20 (0x14) */
-
-/* =========================================================================================================================== */
-/* ================ R_OPAMP ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Operational Amplifier (R_OPAMP)
- */
-
-typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */
-{
- __IM uint8_t RESERVED[8];
-
- union
- {
- __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */
-
- struct
- {
- __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */
- __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */
- __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */
- uint8_t : 4;
- __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */
- } AMPMC_b;
- };
-
- union
- {
- __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */
-
- struct
- {
- __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger
- * control */
- __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger
- * control */
- __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger
- * control */
- __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger
- * control */
- } AMPTRM_b;
- };
-
- union
- {
- __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select
- * Register */
-
- struct
- {
- __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the
- * AMPTRS register after setting the AMPTRM register. */
- uint8_t : 6;
- } AMPTRS_b;
- };
-
- union
- {
- __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */
-
- struct
- {
- __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */
- __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */
- __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */
- __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */
- uint8_t : 3;
- __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference
- * current circuit */
- } AMPC_b;
- };
-
- union
- {
- __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */
-
- struct
- {
- __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */
- __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */
- __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */
- __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */
- uint8_t : 4;
- } AMPMON_b;
- };
- __IM uint8_t RESERVED1;
- __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier
- * [0..3] */
-
- union
- {
- __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control
- * register */
-
- struct
- {
- __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */
- __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */
- __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */
- uint8_t : 5;
- } AMPCPC_b;
- };
- __IM uint8_t RESERVED2[4];
-
- union
- {
- __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable
- * Register */
-
- struct
- {
- __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */
- __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */
- __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */
- uint8_t : 5;
- } AMPUOTE_b;
- };
- __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */
-} R_OPAMP_Type; /*!< Size = 38 (0x26) */
-
-/* =========================================================================================================================== */
-/* ================ R_PDC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Parallel Data Capture Unit (R_PDC)
- */
-
-typedef struct /*!< (@ 0x40094000) R_PDC Structure */
-{
- union
- {
- __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */
-
- struct
- {
- __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */
- __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */
- __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */
- __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */
- __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */
- __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */
- __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */
- __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */
- __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */
- __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */
- __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */
- __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */
- __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */
- uint32_t : 17;
- } PCCR0_b;
- };
-
- union
- {
- __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */
-
- struct
- {
- __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */
- uint32_t : 31;
- } PCCR1_b;
- };
-
- union
- {
- __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */
-
- struct
- {
- __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */
- __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */
- __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */
- __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */
- __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */
- __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */
- __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */
- uint32_t : 25;
- } PCSR_b;
- };
-
- union
- {
- __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */
-
- struct
- {
- __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */
- __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */
- uint32_t : 30;
- } PCMONR_b;
- };
-
- union
- {
- __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */
-
- struct
- {
- __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the
- * storage of captured data. The PCDR register is a 4-byte
- * space to which the FIFO is mapped, and four bytes of data
- * are read from the PCDR register at a time. */
- } PCDR_b;
- };
-
- union
- {
- __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */
-
- struct
- {
- __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line
- * where capture is to start. */
- uint32_t : 4;
- __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */
- uint32_t : 4;
- } VCR_b;
- };
-
- union
- {
- __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */
-
- struct
- {
- __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position
- * in bytes where capture is to start. */
- uint32_t : 4;
- __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture
- * horizontally. */
- uint32_t : 4;
- } HCR_b;
- };
-} R_PDC_Type; /*!< Size = 28 (0x1c) */
-
-/* =========================================================================================================================== */
-/* ================ R_PORT0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I/O Ports (R_PORT0)
- */
-
-typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */
-{
- union
- {
- union
- {
- __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */
-
- struct
- {
- __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */
- __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */
- } PCNTR1_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */
-
- struct
- {
- __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */
- __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */
- __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */
- __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */
- __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */
- __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */
- __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */
- __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */
- __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */
- __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */
- __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */
- __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */
- __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */
- __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */
- __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */
- __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */
- } PODR_b;
- };
-
- union
- {
- __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */
-
- struct
- {
- __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */
- __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */
- __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */
- __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */
- __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */
- __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */
- __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */
- __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */
- __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */
- __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */
- __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */
- __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */
- __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */
- __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */
- __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */
- __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */
- } PDR_b;
- };
- };
- };
-
- union
- {
- union
- {
- __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */
-
- struct
- {
- __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */
- __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */
- } PCNTR2_b;
- };
-
- struct
- {
- union
- {
- __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */
-
- struct
- {
- __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */
- __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */
- __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */
- __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */
- __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */
- __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */
- __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */
- __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */
- __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */
- __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */
- __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */
- __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */
- __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */
- __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */
- __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */
- __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */
- } EIDR_b;
- };
-
- union
- {
- __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */
-
- struct
- {
- __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */
- __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */
- __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */
- __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */
- __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */
- __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */
- __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */
- __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */
- __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */
- __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */
- __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */
- __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */
- __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */
- __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */
- __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */
- __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */
- } PIDR_b;
- };
- };
- };
-
- union
- {
- union
- {
- __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */
-
- struct
- {
- __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */
- __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */
- } PCNTR3_b;
- };
-
- struct
- {
- union
- {
- __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */
-
- struct
- {
- __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */
- __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */
- __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */
- __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */
- __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */
- __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */
- __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */
- __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */
- __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */
- __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */
- __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */
- __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */
- __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */
- __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */
- __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */
- __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */
- } PORR_b;
- };
-
- union
- {
- __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */
-
- struct
- {
- __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */
- __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */
- __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */
- __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */
- __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */
- __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */
- __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */
- __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */
- __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */
- __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */
- __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */
- __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */
- __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */
- __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */
- __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */
- __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */
- } POSR_b;
- };
- };
- };
-
- union
- {
- union
- {
- __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */
-
- struct
- {
- __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */
- __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */
- } PCNTR4_b;
- };
-
- struct
- {
- union
- {
- __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */
-
- struct
- {
- __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */
- __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */
- __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */
- __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */
- __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */
- __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */
- __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */
- __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */
- __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */
- __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */
- __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */
- __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */
- __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */
- __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */
- __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */
- __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */
- } EORR_b;
- };
-
- union
- {
- __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */
-
- struct
- {
- __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */
- __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */
- __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */
- __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */
- __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */
- __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */
- __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */
- __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */
- __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */
- __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */
- __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */
- __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */
- __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */
- __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */
- __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */
- __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */
- } EOSR_b;
- };
- };
- };
-} R_PORT0_Type; /*!< Size = 16 (0x10) */
-
-/* =========================================================================================================================== */
-/* ================ R_PFS ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I/O Ports-PFS (R_PFS)
- */
-
-typedef struct /*!< (@ 0x40040800) R_PFS Structure */
-{
- __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */
-} R_PFS_Type; /*!< Size = 960 (0x3c0) */
-
-/* =========================================================================================================================== */
-/* ================ R_PMISC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I/O Ports-MISC (R_PMISC)
- */
-
- #ifndef BSP_OVERRIDE_REG_R_PMISC_TYPE
-
-typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */
-{
- union
- {
- __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */
- __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */
- uint8_t : 2;
- } PFENET_b;
- };
- __IM uint8_t RESERVED[2];
-
- union
- {
- __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
- __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
- } PWPR_b;
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */
-
- struct
- {
- uint8_t : 6;
- __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
- __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
- } PWPRS_b;
- };
- __IM uint16_t RESERVED2[5];
- __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */
-} R_PMISC_Type; /*!< Size = 40 (0x28) */
-
- #endif
-
-/* =========================================================================================================================== */
-/* ================ R_QSPI ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Quad Serial Peripheral Interface (R_QSPI)
- */
-
-typedef struct /*!< (@ 0x64000000) R_QSPI Structure */
-{
- union
- {
- __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */
-
- struct
- {
- __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */
- uint32_t : 1;
- __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */
- __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */
- __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
- * other than on byte boundaries */
- __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
- * input to CFGMD3. */
- __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
- * the serial interface */
- __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */
- __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */
- uint32_t : 3;
- __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */
- uint32_t : 16;
- } SFMSMD_b;
- };
-
- union
- {
- __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */
-
- struct
- {
- __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */
- __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */
- __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */
- uint32_t : 26;
- } SFMSSC_b;
- };
-
- union
- {
- __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */
-
- struct
- {
- __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention
- * to the irregularity.)NOTE: When PCLKA multiplied by an
- * odd number is selected, the high-level width of the SCK
- * signal is longer than the low-level width by 1 x PCLKA
- * before duty ratio correction. */
- __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
- * SCK signal */
- uint32_t : 26;
- } SFMSKC_b;
- };
-
- union
- {
- __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */
-
- struct
- {
- __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
- * (No combination other than the above is available.) */
- uint32_t : 1;
- __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */
- __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */
- uint32_t : 24;
- } SFMSST_b;
- };
-
- union
- {
- __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */
-
- struct
- {
- __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output
- * to and from this port is converted to a SPIbus cycle. This
- * port is accessible in the direct communication mode (DCOM=1)
- * only.Access to this port is ignored in the ROM access mode. */
- uint32_t : 24;
- } SFMCOM_b;
- };
-
- union
- {
- __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */
-
- struct
- {
- __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */
- uint32_t : 31;
- } SFMCMD_b;
- };
-
- union
- {
- __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */
-
- struct
- {
- __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */
- uint32_t : 6;
- __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication
- * modeNOTE: Writing of 0 only is possible. Writing of 1 is
- * ignored. */
- uint32_t : 24;
- } SFMCST_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */
-
- struct
- {
- __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */
- uint32_t : 24;
- } SFMSIC_b;
- };
-
- union
- {
- __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */
-
- struct
- {
- __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */
- uint32_t : 2;
- __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
- * Interface address width is selected 4 bytes. */
- uint32_t : 27;
- } SFMSAC_b;
- };
-
- union
- {
- __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */
-
- struct
- {
- __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read
- * instructions */
- uint32_t : 2;
- __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */
- __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */
- __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */
- uint32_t : 16;
- } SFMSDC_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */
-
- struct
- {
- __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
- * is required to be set by software separately. */
- uint32_t : 2;
- __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
- * when Dual SPI protocol or Quad SPI protocol is selected. */
- uint32_t : 27;
- } SFMSPC_b;
- };
-
- union
- {
- __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */
-
- struct
- {
- uint32_t : 2;
- __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */
- uint32_t : 29;
- } SFMPMD_b;
- };
- __IM uint32_t RESERVED2[499];
-
- union
- {
- __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */
-
- struct
- {
- uint32_t : 26;
- __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
- * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
- * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */
- } SFMCNT1_b;
- };
-} R_QSPI_Type; /*!< Size = 2056 (0x808) */
-
-/* =========================================================================================================================== */
-/* ================ R_RTC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Realtime Clock (R_RTC)
- */
-
-typedef struct /*!< (@ 0x40044000) R_RTC Structure */
-{
- union
- {
- __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */
-
- struct
- {
- __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */
- __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */
- __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */
- __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */
- __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */
- __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */
- __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */
- uint8_t : 1;
- } R64CNT_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- union
- {
- __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */
-
- struct
- {
- __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
- * a carry is generated, 1 is added to the tens place. */
- __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */
- uint8_t : 1;
- } RSECCNT_b;
- };
-
- union
- {
- __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */
-
- struct
- {
- __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
- * counter b7 to b0. */
- } BCNT0_b;
- };
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- union
- {
- __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */
-
- struct
- {
- __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
- * a carry is generated, 1 is added to the tens place. */
- __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */
- uint8_t : 1;
- } RMINCNT_b;
- };
-
- union
- {
- __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */
-
- struct
- {
- __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
- * counter b15 to b8. */
- } BCNT1_b;
- };
- };
- __IM uint8_t RESERVED2;
-
- union
- {
- union
- {
- __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */
-
- struct
- {
- __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
- * carry is generated, 1 is added to the tens place. */
- __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
- * the ones place. */
- __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
- uint8_t : 1;
- } RHRCNT_b;
- };
-
- union
- {
- __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */
-
- struct
- {
- __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
- * counter b23 to b16. */
- } BCNT2_b;
- };
- };
- __IM uint8_t RESERVED3;
-
- union
- {
- union
- {
- __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */
-
- struct
- {
- __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
- uint8_t : 5;
- } RWKCNT_b;
- };
-
- union
- {
- __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */
-
- struct
- {
- __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
- * counter b31 to b24. */
- } BCNT3_b;
- };
- };
- __IM uint8_t RESERVED4;
-
- union
- {
- __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */
-
- struct
- {
- __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
- * is generated, 1 is added to the tens place. */
- __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
- * ones place. */
- uint8_t : 2;
- } RDAYCNT_b;
- };
- __IM uint8_t RESERVED5;
-
- union
- {
- __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */
-
- struct
- {
- __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
- * a carry is generated, 1 is added to the tens place. */
- __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
- * the ones place. */
- uint8_t : 3;
- } RMONCNT_b;
- };
- __IM uint8_t RESERVED6;
-
- union
- {
- __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */
-
- struct
- {
- __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
- * carry is generated, 1 is added to the tens place. */
- __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
- * ones place. When a carry is generated in the tens place,
- * 1 is added to the hundreds place. */
- uint16_t : 8;
- } RYRCNT_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */
-
- struct
- {
- __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */
- __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RSECAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */
-
- struct
- {
- __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
- * corresponding to 32-bit binary counter b7 to b0. */
- } BCNT0AR_b;
- };
- };
- __IM uint8_t RESERVED7;
-
- union
- {
- union
- {
- __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */
-
- struct
- {
- __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */
- __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RMINAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */
-
- struct
- {
- __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
- * corresponding to 32-bit binary counter b15 to b8. */
- } BCNT1AR_b;
- };
- };
- __IM uint8_t RESERVED8;
-
- union
- {
- union
- {
- __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */
-
- struct
- {
- __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */
- __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */
- __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RHRAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */
-
- struct
- {
- __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
- * counter b23 to b16. */
- } BCNT2AR_b;
- };
- };
- __IM uint8_t RESERVED9;
-
- union
- {
- union
- {
- __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */
-
- struct
- {
- __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
- uint8_t : 4;
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RWKAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */
-
- struct
- {
- __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
- * counter b31 to b24. */
- } BCNT3AR_b;
- };
- };
- __IM uint8_t RESERVED10;
-
- union
- {
- union
- {
- __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */
-
- struct
- {
- __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */
- __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */
- uint8_t : 1;
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RDAYAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */
-
- struct
- {
- __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
- * for setting the alarm enable corresponding to 32-bit binary
- * counter b7 to b0. */
- } BCNT0AER_b;
- };
- };
- __IM uint8_t RESERVED11;
-
- union
- {
- union
- {
- __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */
-
- struct
- {
- __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */
- __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */
- uint8_t : 2;
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RMONAR_b;
- };
-
- union
- {
- __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */
-
- struct
- {
- __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
- * for setting the alarm enable corresponding to 32-bit binary
- * counter b15 to b8. */
- } BCNT1AER_b;
- };
- };
- __IM uint8_t RESERVED12;
-
- union
- {
- union
- {
- __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */
-
- struct
- {
- __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */
- __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */
- uint16_t : 8;
- } RYRAR_b;
- };
-
- union
- {
- __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */
-
- struct
- {
- __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
- * for setting the alarm enable corresponding to 32-bit binary
- * counter b23 to b16. */
- uint16_t : 8;
- } BCNT2AER_b;
- };
- };
-
- union
- {
- union
- {
- __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
- } RYRAREN_b;
- };
-
- union
- {
- __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */
-
- struct
- {
- __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
- * for setting the alarm enable corresponding to 32-bit binary
- * counter b31 to b24. */
- } BCNT3AER_b;
- };
- };
- __IM uint8_t RESERVED13;
- __IM uint16_t RESERVED14;
-
- union
- {
- __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */
-
- struct
- {
- __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */
- __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */
- __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */
- __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */
- __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */
- } RCR1_b;
- };
- __IM uint8_t RESERVED15;
-
- union
- {
- __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */
-
- struct
- {
- __IOM uint8_t START : 1; /*!< [0..0] Start */
- __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */
- __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */
- __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */
- __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
- * the setting of this bit is disabled.) */
- __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
- * is selected, the setting of this bit is disabled.) */
- __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */
- __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */
- } RCR2_b;
- };
- __IM uint8_t RESERVED16;
- __IM uint16_t RESERVED17;
-
- union
- {
- __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */
-
- struct
- {
- __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */
- uint8_t : 6;
- __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */
- } RCR4_b;
- };
- __IM uint8_t RESERVED18;
-
- union
- {
- __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */
-
- struct
- {
- __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
- * clock from the LOCOclock, this bit sets the comparison
- * value of the 128-Hz clock cycle. */
- uint16_t : 15;
- } RFRH_b;
- };
-
- union
- {
- __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */
-
- struct
- {
- __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
- * clock from the main clock, this bit sets the comparison
- * value of the 128-Hz clock cycle. */
- } RFRL_b;
- };
-
- union
- {
- __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */
-
- struct
- {
- __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value
- * from the prescaler. */
- __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */
- } RADJ_b;
- };
- __IM uint8_t RESERVED19;
- __IM uint16_t RESERVED20[8];
- __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */
- __IM uint16_t RESERVED21[5];
- __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */
-} R_RTC_Type; /*!< Size = 128 (0x80) */
-
-/* =========================================================================================================================== */
-/* ================ R_SCI0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Serial Communications Interface (R_SCI0)
- */
-
-typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */
-{
- union
- {
- union
- {
- __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */
-
- struct
- {
- __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
- __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */
- __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */
- __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
- __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
- __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */
- __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */
- } SMR_b;
- };
-
- union
- {
- __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */
-
- struct
- {
- __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
- __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */
- __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
- __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
- __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */
- __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */
- } SMR_SMCI_b;
- };
- };
-
- union
- {
- __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */
-
- struct
- {
- __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */
- } BRR_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */
-
- struct
- {
- __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
- __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
- __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
- * mode when SMR.MP = 1) */
- __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
- __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
- __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
- __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
- } SCR_b;
- };
-
- union
- {
- __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */
-
- struct
- {
- __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
- __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
- __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */
- __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
- __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
- __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
- __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
- } SCR_SMCI_b;
- };
- };
-
- union
- {
- __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */
-
- struct
- {
- __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */
- } TDR_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */
-
- struct
- {
- __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */
- __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */
- __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
- __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
- __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
- __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
- __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
- __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
- } SSR_b;
- };
-
- union
- {
- __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */
-
- struct
- {
- __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
- * multi-processor) and FIFO selected) */
- uint8_t : 1;
- __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
- __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
- __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
- __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
- __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */
- __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */
- } SSR_FIFO_b;
- };
-
- union
- {
- __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */
-
- struct
- {
- __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
- * card interface mode. */
- __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
- * mode. */
- __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
- __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
- __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
- __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
- __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
- __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
- } SSR_SMCI_b;
- };
- };
-
- union
- {
- __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */
-
- struct
- {
- __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */
- } RDR_b;
- };
-
- union
- {
- __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */
-
- struct
- {
- __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */
- uint8_t : 1;
- __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
- * operation is to be in simple I2C mode. */
- __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
- * setting is invalid and a fixed data length of 8 bits is
- * used in modes other than asynchronous mode.Set this bit
- * to 1 if operation is to be in simple I2C mode. */
- __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */
- uint8_t : 2;
- __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
- * in combination with the SMR.BCP[1:0] bits */
- } SCMR_b;
- };
-
- union
- {
- __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */
-
- struct
- {
- uint8_t : 2;
- __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */
- __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
- * only in asynchronous mode and SCR.CKE[1]=0) */
- __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
- * mode) */
- __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
- * be 0 without simple I2C mode and asynchronous mode.)In
- * asynchronous mode, for RXDn input only. In simple I2C mode,
- * for RXDn/TxDn input. */
- __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
- * the CKE[1] bit in SCR is 0 in asynchronous mode). */
- __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
- * in asynchronous mode) */
- } SEMR_b;
- };
-
- union
- {
- __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */
-
- struct
- {
- __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */
- uint8_t : 5;
- } SNFR_b;
- };
-
- union
- {
- __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */
-
- struct
- {
- __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */
- uint8_t : 2;
- __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
- * signal from the on-chip baud rate generator. */
- } SIMR1_b;
- };
-
- union
- {
- __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */
-
- struct
- {
- __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */
- __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */
- uint8_t : 3;
- __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */
- uint8_t : 2;
- } SIMR2_b;
- };
-
- union
- {
- __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */
-
- struct
- {
- __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */
- __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */
- __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */
- __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
- * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */
- __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */
- __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */
- } SIMR3_b;
- };
-
- union
- {
- __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */
-
- struct
- {
- __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
- uint8_t : 7;
- } SISR_b;
- };
-
- union
- {
- __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */
-
- struct
- {
- __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */
- __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */
- __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */
- __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */
- __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */
- uint8_t : 1;
- __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */
- __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */
- } SPMR_b;
- };
-
- union
- {
- union
- {
- __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */
-
- struct
- {
- __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */
- } TDRHL_b;
- };
-
- union
- {
- __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */
-
- struct
- {
- __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode, and FIFO selected) */
- __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
- * mode and SMR.MP=1 and FIFO selected) */
- uint16_t : 6;
- } FTDRHL_b;
- };
-
- struct
- {
- union
- {
- __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */
-
- struct
- {
- __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode,
- * and FIFO selected) */
- __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
- * mode and SMR.MP=1 and FIFO selected) */
- uint8_t : 6;
- } FTDRH_b;
- };
-
- union
- {
- __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */
-
- struct
- {
- __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode,
- * and FIFO selected) */
- } FTDRL_b;
- };
- };
- };
-
- union
- {
- union
- {
- __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */
-
- struct
- {
- __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */
- } RDRHL_b;
- };
-
- union
- {
- __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */
-
- struct
- {
- __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode, and FIFO selected) */
- __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
- * with SMR.MP=1 and FIFO selected) It can read multi-processor
- * bit corresponded to serial receive data(RDATA[8:0]) */
- __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */
- __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */
- __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */
- __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */
- __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */
- uint16_t : 1;
- } FRDRHL_b;
- };
-
- struct
- {
- union
- {
- __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */
-
- struct
- {
- __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode, and FIFO selected) */
- __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
- * with SMR.MP=1 and FIFO selected) It can read multi-processor
- * bit corresponded to serial receive data(RDATA[8:0]) */
- __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */
- __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */
- __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */
- __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */
- __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */
- uint8_t : 1;
- } FRDRH_b;
- };
-
- union
- {
- __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */
-
- struct
- {
- __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
- * When reading both of FRDRH register and FRDRL register,
- * please read by an order of the FRDRH register and the FRDRL
- * register. */
- } FRDRL_b;
- };
- };
- };
-
- union
- {
- __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */
-
- struct
- {
- __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */
- } MDDR_b;
- };
-
- union
- {
- __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */
-
- struct
- {
- __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */
- uint8_t : 2;
- __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */
- __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */
- uint8_t : 1;
- __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
- * multi-processor) */
- __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
- * mode(including multi-processor) */
- } DCCR_b;
- };
-
- union
- {
- __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */
-
- struct
- {
- __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode) */
- __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */
- __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */
- __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a
- * reception data ready, the interrupt request is selected.) */
- __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode) */
- __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode) */
- __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
- * in asynchronous mode(including multi-processor) or clock
- * synchronous mode) */
- } FCR_b;
- };
-
- union
- {
- __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */
-
- struct
- {
- __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
- * data stored in FRDRH and FRDRL(Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode,
- * while FCR.FM=1) */
- uint16_t : 3;
- __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
- * data stored in FTDRH and FTDRL(Valid only in asynchronous
- * mode(including multi-processor) or clock synchronous mode,
- * while FCR.FM=1) */
- uint16_t : 3;
- } FDR_b;
- };
-
- union
- {
- __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */
-
- struct
- {
- __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
- * multi-processor) or clock synchronous mode, and FIFO selected) */
- uint16_t : 1;
- __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with
- * a framing error among the receive data stored in the receive
- * FIFO data register (FRDRH and FRDRL). */
- uint16_t : 1;
- __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with
- * a parity error among the receive data stored in the receive
- * FIFO data register (FRDRH and FRDRL). */
- uint16_t : 3;
- } LSR_b;
- };
-
- union
- {
- __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */
-
- struct
- {
- __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match
- * wake-up function */
- uint16_t : 7;
- } CDR_b;
- };
-
- union
- {
- __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */
-
- struct
- {
- __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
- * is shown.) */
- __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of
- * TxD terminal is selected when SCR.TE = 0.) */
- __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value
- * of SPB2DT is output to TxD terminal.) */
- uint8_t : 1;
- __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */
- __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */
- __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */
- __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */
- } SPTR_b;
- };
-
- union
- {
- __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */
-
- struct
- {
- __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */
- __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */
- __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */
- __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */
- } ACTR_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */
-
- struct
- {
- __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */
- uint8_t : 7;
- } ESMER_b;
- };
-
- union
- {
- __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */
-
- struct
- {
- uint8_t : 1;
- __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */
- __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */
- __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */
- uint8_t : 4;
- } CR0_b;
- };
-
- union
- {
- __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */
-
- struct
- {
- __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */
- __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */
- __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */
- __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */
- __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */
- } CR1_b;
- };
-
- union
- {
- __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */
-
- struct
- {
- __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */
- uint8_t : 1;
- __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */
- __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */
- } CR2_b;
- };
-
- union
- {
- __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */
-
- struct
- {
- __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */
- uint8_t : 7;
- } CR3_b;
- };
-
- union
- {
- __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */
-
- struct
- {
- __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */
- __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */
- uint8_t : 2;
- __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */
- uint8_t : 3;
- } PCR_b;
- };
-
- union
- {
- __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */
-
- struct
- {
- __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */
- __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */
- __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */
- __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */
- __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */
- __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */
- uint8_t : 2;
- } ICR_b;
- };
-
- union
- {
- __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */
-
- struct
- {
- __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */
- __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */
- __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */
- __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */
- __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */
- __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */
- uint8_t : 2;
- } STR_b;
- };
-
- union
- {
- __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */
-
- struct
- {
- __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */
- __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */
- __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */
- __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */
- __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */
- __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */
- uint8_t : 2;
- } STCR_b;
- };
- __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */
-
- union
- {
- __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */
-
- struct
- {
- __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */
- __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */
- } CF0CR_b;
- };
- __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */
- __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */
- __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */
-
- union
- {
- __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */
-
- struct
- {
- __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */
- __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */
- __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */
- __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */
- __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */
- __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */
- __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */
- __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */
- } CF1CR_b;
- };
- __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */
-
- union
- {
- __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */
-
- struct
- {
- __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */
- uint8_t : 7;
- } TCR_b;
- };
-
- union
- {
- __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */
-
- struct
- {
- __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */
- uint8_t : 1;
- __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */
- __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */
- uint8_t : 1;
- } TMR_b;
- };
- __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */
- __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */
-} R_SCI0_Type; /*!< Size = 52 (0x34) */
-
-/* =========================================================================================================================== */
-/* ================ R_SDADC0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief R_SDADC0 (R_SDADC0)
- */
-
-typedef struct /*!< (@ 0x4009C000) R_SDADC0 Structure */
-{
- union
- {
- __IOM uint16_t STC1; /*!< (@ 0x00000000) Startup Control Register 1 */
-
- struct
- {
- __IOM uint16_t CLKDIV : 4; /*!< [3..0] SDADC24 Reference Clock Division */
- uint16_t : 3;
- __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select */
- __IOM uint16_t VSBIAS : 4; /*!< [11..8] Reference voltage select */
- uint16_t : 3;
- __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select */
- } STC1_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint8_t STC2; /*!< (@ 0x00000004) Startup Control Register 2 */
-
- struct
- {
- __IOM uint8_t BGRPON : 1; /*!< [0..0] BGR part power control */
- __IOM uint8_t ADCPON : 1; /*!< [1..1] ADREG forced power-down */
- __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part */
- uint8_t : 5;
- } STC2_b;
- };
- __IM uint8_t RESERVED1;
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint32_t PGAC[5]; /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register */
-
- struct
- {
- __IOM uint32_t PGAGC : 5; /*!< [4..0] Gain selection of a programmable gain instrumentation
- * amplifier ( Gset1, Gset2, Gtotal ) */
- __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select */
- __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select */
- uint32_t : 1;
- __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select */
- __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select */
- __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count
- * (N) in AUTOSCAN */
- __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count
- * (N) in AUTOSCAN */
- __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged */
- __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing */
- __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select */
- uint32_t : 1;
- __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable */
- __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of
- * A/D conversions in ADSCAN */
- } PGAC_b[5];
- };
-
- union
- {
- __IOM uint32_t ADC1; /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1 */
-
- struct
- {
- __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode */
- uint32_t : 3;
- __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal */
- uint32_t : 3;
- __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer */
- uint32_t : 3;
- __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection */
- __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting */
- uint32_t : 2;
- __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable */
- uint32_t : 11;
- } ADC1_b;
- };
-
- union
- {
- __IOM uint8_t ADC2; /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2 */
-
- struct
- {
- __IOM uint8_t SDADST : 1; /*!< [0..0] Control of A/D conversion */
- uint8_t : 7;
- } ADC2_b;
- };
- __IM uint8_t RESERVED3;
- __IM uint16_t RESERVED4;
-
- union
- {
- __IOM uint32_t ADCR; /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register */
-
- struct
- {
- __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result */
- __IM uint32_t SDADCRS : 1; /*!< [24..24] Status of an A/D conversion result */
- __IM uint32_t SDADCRC : 3; /*!< [27..25] Channel number for an A/D conversion result */
- uint32_t : 4;
- } ADCR_b;
- };
-
- union
- {
- __IM uint32_t ADAR; /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register */
-
- struct
- {
- __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value */
- __IM uint32_t SDADMVS : 1; /*!< [24..24] Status of an A/D conversion result */
- __IM uint32_t SDADMVC : 3; /*!< [27..25] Channel number for an A/D conversion result */
- uint32_t : 4;
- } ADAR_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint8_t CLBC; /*!< (@ 0x00000030) Calibration Control Register */
-
- struct
- {
- __IOM uint8_t CLBMD : 2; /*!< [1..0] These bits are read as 0. The write value should be 0. */
- uint8_t : 6;
- } CLBC_b;
- };
- __IM uint8_t RESERVED6;
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint8_t CLBSTR; /*!< (@ 0x00000034) Calibration Start Control Register */
-
- struct
- {
- __IOM uint8_t CLBST : 1; /*!< [0..0] Calibration start control */
- uint8_t : 7;
- } CLBSTR_b;
- };
- __IM uint8_t RESERVED8;
- __IM uint16_t RESERVED9;
- __IM uint32_t RESERVED10;
-
- union
- {
- __IM uint8_t CLBSSR; /*!< (@ 0x0000003C) Calibration Status Register */
-
- struct
- {
- __IM uint8_t CLBSS : 1; /*!< [0..0] Calibration status */
- uint8_t : 7;
- } CLBSSR_b;
- };
- __IM uint8_t RESERVED11;
- __IM uint16_t RESERVED12;
-} R_SDADC0_Type; /*!< Size = 64 (0x40) */
-
-/* =========================================================================================================================== */
-/* ================ R_SDHI0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief SD/MMC Host Interface (R_SDHI0)
- */
-
-typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */
-{
- union
- {
- __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */
-
- struct
- {
- __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
- * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
- * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */
- __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */
- __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
- * in normal mode, see section 1.4.10, Example of SD_CMD Register
- * Setting to select mode/response type. */
- __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */
- __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data
- * is handled) */
- __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
- * with data is handled) */
- __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
- * transfer) */
- uint32_t : 16;
- } SD_CMD_b;
- };
- __IM uint32_t RESERVED;
-
- union
- {
- __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */
-
- struct
- {
- __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */
- } SD_ARG_b;
- };
-
- union
- {
- __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */
-
- struct
- {
- __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */
- uint32_t : 16;
- } SD_ARG1_b;
- };
-
- union
- {
- __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */
-
- struct
- {
- __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
- * CMD12 is issued to halt the transfer through the SD host
- * interface.However, if a command sequence is halted because
- * of a communications error or timeout, CMD12 is not issued.
- * Although continued buffer access is possible even after
- * STP has been set to 1, the buffer access error bit (ERR5
- * or ERR4) in SD_INFO2 will be set accordingly.- When STP
- * has been set to 1 during transfer for single block write,
- * the access end flag is set when SD_BUF becomes e */
- uint32_t : 7;
- __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
- * SD_CMD is set as follows to start the command sequence
- * while SEC is set to 1, CMD12 is automatically issued to
- * stop multi-block transfer with the number of blocks which
- * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
- * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
- * automatically issued, multiple block transfer)When the
- * command sequence is halted because of a communications
- * error or timeout, CMD12 is not automatically */
- uint32_t : 23;
- } SD_STOP_b;
- };
-
- union
- {
- __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */
-
- struct
- {
- __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
- * of this bit when the CBSY bit in SD_INFO2 is set to 1. */
- } SD_SECCNT_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */
-
- struct
- {
- __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */
- } SD_RSP10_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */
-
- struct
- {
- __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */
- uint32_t : 16;
- } SD_RSP1_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */
-
- struct
- {
- __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */
- } SD_RSP32_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */
-
- struct
- {
- __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */
- uint32_t : 16;
- } SD_RSP3_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */
-
- struct
- {
- __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */
- } SD_RSP54_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */
-
- struct
- {
- __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */
- uint32_t : 16;
- } SD_RSP5_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */
-
- struct
- {
- __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */
- uint32_t : 8;
- } SD_RSP76_b;
- };
-
- union
- {
- __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */
-
- struct
- {
- __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */
- uint32_t : 24;
- } SD_RSP7_b;
- };
-
- union
- {
- __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */
-
- struct
- {
- __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */
- uint32_t : 1;
- __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */
- __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */
- __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */
- __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */
- uint32_t : 1;
- __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */
- __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */
- __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */
- __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */
- uint32_t : 21;
- } SD_INFO1_b;
- };
-
- union
- {
- __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */
-
- struct
- {
- __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */
- __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */
- __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */
- __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */
- __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */
- __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */
- __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */
- __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
- * by SD_PORTSEL. */
- __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */
- __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */
- uint32_t : 3;
- __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
- * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
- * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
- * cycles of SDCLK have elapsed after setting of the CBSY
- * bit to 0 due to completion of the command sequence. */
- __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */
- __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */
- uint32_t : 16;
- } SD_INFO2_b;
- };
-
- union
- {
- __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */
-
- struct
- {
- __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */
- uint32_t : 1;
- __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */
- __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */
- __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */
- uint32_t : 3;
- __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */
- __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */
- uint32_t : 22;
- } SD_INFO1_MASK_b;
- };
-
- union
- {
- __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */
-
- struct
- {
- __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */
- __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */
- __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */
- __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */
- __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */
- __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */
- __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */
- uint32_t : 1;
- __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */
- __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */
- uint32_t : 5;
- __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */
- uint32_t : 16;
- } SD_INFO2_MASK_b;
- };
-
- union
- {
- __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */
-
- struct
- {
- __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */
- __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */
- __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */
- uint32_t : 22;
- } SD_CLK_CTRL_b;
- };
-
- union
- {
- __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */
-
- struct
- {
- __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
- * and 512 bytes for the transfer of single blocks.In cases
- * of multiple block transfer with automatic issuing of CMD12
- * (CMD18 and CMD25), the only specifiable transfer data size
- * is 512 bytes. Furthermore, in cases of multiple block transfer
- * without automatic issuing of CMD12, as well as 512 bytes,
- * 32, 64, 128, and 256 bytes are specifiable. However, in
- * the reading of 32, 64, 128, and 256 bytes for the transfer
- * of multiple blocks, this is restricted to mu */
- uint32_t : 22;
- } SD_SIZE_b;
- };
-
- union
- {
- __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */
-
- struct
- {
- __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */
- __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */
- __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
- * timeout, software reset should be executed to terminate
- * command sequence. */
- uint32_t : 4;
- __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */
- uint32_t : 1;
- __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
- * and when the SOFT_RST.SDRST flag is 0. */
- uint32_t : 16;
- } SD_OPTION_b;
- };
- __IM uint32_t RESERVED1;
-
- union
- {
- __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */
-
- struct
- {
- __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command
- * issued within a command sequence */
- __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
- * setting a command index in SD_CMD, this is Indicated in
- * CMDE0. */
- __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
- * a command issued within a command sequence */
- __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
- * issued by setting a command index in SD_CMD, this is indicated
- * in RSPLENE0. */
- __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */
- __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */
- uint32_t : 2;
- __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
- * command issued within a command sequence */
- __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
- * by setting a command index in SD_CMD, this is indicated
- * in RSPCRCE0. */
- __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */
- __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */
- __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
- * value is 010b) */
- uint32_t : 17;
- } SD_ERR_STS1_b;
- };
-
- union
- {
- __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */
-
- struct
- {
- __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */
- __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */
- __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */
- __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */
- __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */
- __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */
- __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */
- uint32_t : 25;
- } SD_ERR_STS2_b;
- };
-
- union
- {
- __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */
-
- struct
- {
- __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
- * data is written to this register. When reading from the
- * SD card, the read data is read from this register. This
- * register is internally connected to two 512-byte buffers.If
- * both buffers are not empty when executing multiple block
- * read, SD/MMC clock is stopped to suspend receiving data.
- * When one of buffers is empty, SD/MMC clock is supplied
- * to resume receiving data. */
- } SD_BUF0_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */
-
- struct
- {
- __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */
- uint32_t : 1;
- __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */
- uint32_t : 5;
- __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */
- __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */
- uint32_t : 22;
- } SDIO_MODE_b;
- };
-
- union
- {
- __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */
-
- struct
- {
- __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */
- uint32_t : 13;
- __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */
- __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */
- uint32_t : 16;
- } SDIO_INFO1_b;
- };
-
- union
- {
- __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */
-
- struct
- {
- __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */
- uint32_t : 13;
- __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */
- __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */
- uint32_t : 16;
- } SDIO_INFO1_MASK_b;
- };
- __IM uint32_t RESERVED3[79];
-
- union
- {
- __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */
-
- struct
- {
- uint32_t : 1;
- __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */
- uint32_t : 30;
- } SD_DMAEN_b;
- };
- __IM uint32_t RESERVED4[3];
-
- union
- {
- __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */
-
- struct
- {
- __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */
- uint32_t : 31;
- } SOFT_RST_b;
- };
- __IM uint32_t RESERVED5[2];
-
- union
- {
- __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */
- uint32_t : 23;
- } SDIF_MODE_b;
- };
- __IM uint32_t RESERVED6[4];
-
- union
- {
- __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */
-
- struct
- {
- uint32_t : 6;
- __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */
- __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */
- uint32_t : 24;
- } EXT_SWAP_b;
- };
-} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */
-
-/* =========================================================================================================================== */
-/* ================ R_SLCDC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Segment LCD Controller/Driver (R_SLCDC)
- */
-
-typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */
-{
- union
- {
- __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */
-
- struct
- {
- __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */
- __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */
- __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */
- __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */
- } LCDM0_b;
- };
-
- union
- {
- __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */
-
- struct
- {
- __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */
- uint8_t : 2;
- __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */
- __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */
- __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation
- * enable/disable */
- __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */
- __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */
- } LCDM1_b;
- };
-
- union
- {
- __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */
-
- struct
- {
- __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */
- uint8_t : 2;
- } LCDC0_b;
- };
-
- union
- {
- __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */
-
- struct
- {
- __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */
- uint8_t : 3;
- } VLCD_b;
- };
- __IM uint8_t RESERVED[252];
-
- union
- {
- __IOM uint8_t SEG[64]; /*!< (@ 0x00000100) LCD Display Data Array */
-
- struct
- {
- __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */
- __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */
- } SEG_b[64];
- };
-} R_SLCDC_Type; /*!< Size = 320 (0x140) */
-
-/* =========================================================================================================================== */
-/* ================ R_SPI0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Serial Peripheral Interface (R_SPI0)
- */
-
-typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */
-{
- union
- {
- __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */
-
- struct
- {
- __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */
- __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */
- __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */
- __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */
- __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */
- __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */
- __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */
- __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */
- } SPCR_b;
- };
-
- union
- {
- __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */
-
- struct
- {
- __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */
- __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */
- __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */
- __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */
- __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */
- __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */
- __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */
- __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */
- } SSLP_b;
- };
-
- union
- {
- __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */
-
- struct
- {
- __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */
- __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */
- uint8_t : 2;
- __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */
- __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */
- uint8_t : 2;
- } SPPCR_b;
- };
-
- union
- {
- __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */
-
- struct
- {
- __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */
- __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */
- __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */
- __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */
- __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */
- __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */
- __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */
- __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */
- } SPSR_b;
- };
-
- union
- {
- __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */
- __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */
- __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */
- };
-
- union
- {
- __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */
-
- struct
- {
- __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
- * the SPCMD0 to SPCMD07 registers are to be referenced is
- * changed in accordance with the sequence length that is
- * set in these bits. The relationship among the setting of
- * these bits, sequence length, and SPCMD0 to SPCMD7 registers
- * referenced by the RSPI is shown above. However, the RSPI
- * in slave mode always references SPCMD0. */
- uint8_t : 5;
- } SPSCR_b;
- };
-
- union
- {
- __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */
-
- struct
- {
- __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */
- uint8_t : 1;
- __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */
- uint8_t : 1;
- } SPSSR_b;
- };
-
- union
- {
- __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */
-
- struct
- {
- __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */
- } SPBR_b;
- };
-
- union
- {
- __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */
-
- struct
- {
- __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */
- __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */
- __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */
- __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */
- __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */
- uint8_t : 1;
- } SPDCR_b;
- };
-
- union
- {
- __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */
-
- struct
- {
- __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */
- uint8_t : 5;
- } SPCKD_b;
- };
-
- union
- {
- __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */
-
- struct
- {
- __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */
- uint8_t : 5;
- } SSLND_b;
- };
-
- union
- {
- __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */
-
- struct
- {
- __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */
- uint8_t : 5;
- } SPND_b;
- };
-
- union
- {
- __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */
-
- struct
- {
- __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */
- __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */
- __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */
- __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */
- __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */
- __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */
- } SPCR2_b;
- };
-
- union
- {
- __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */
-
- struct
- {
- __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */
- __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */
- __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */
- __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */
- __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */
- __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */
- __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */
- __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */
- __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- } SPCMD_b[8];
- };
-
- union
- {
- __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */
-
- struct
- {
- __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
- __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */
- uint8_t : 6;
- } SPDCR2_b;
- };
-
- union
- {
- __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */
-
- struct
- {
- __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */
- __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */
- uint8_t : 2;
- __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */
- uint8_t : 3;
- } SPCR3_b;
- };
- __IM uint16_t RESERVED;
- __IM uint32_t RESERVED1[6];
- __IM uint16_t RESERVED2;
-
- union
- {
- __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */
-
- struct
- {
- uint16_t : 4;
- __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */
- uint16_t : 3;
- __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */
- uint16_t : 1;
- __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */
- } SPPR_b;
- };
-} R_SPI0_Type; /*!< Size = 64 (0x40) */
-
-/* =========================================================================================================================== */
-/* ================ R_SRAM ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief SRAM (R_SRAM)
- */
-
-typedef struct /*!< (@ 0x40002000) R_SRAM Structure */
-{
- union
- {
- __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */
-
- struct
- {
- __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */
- uint8_t : 7;
- } PARIOAD_b;
- };
- __IM uint8_t RESERVED[3];
-
- union
- {
- __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */
-
- struct
- {
- __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */
- __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
- } SRAMPRCR_b;
- };
- __IM uint8_t RESERVED1[3];
- __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */
- __IM uint8_t RESERVED2[3];
-
- union
- {
- __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */
-
- struct
- {
- __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */
- __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
- } SRAMPRCR2_b;
- };
- __IM uint8_t RESERVED3[179];
-
- union
- {
- __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */
-
- struct
- {
- __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */
- uint8_t : 6;
- } ECCMODE_b;
- };
-
- union
- {
- __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */
-
- struct
- {
- __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */
- uint8_t : 7;
- } ECC2STS_b;
- };
-
- union
- {
- __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */
-
- struct
- {
- __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */
- uint8_t : 7;
- } ECC1STSEN_b;
- };
-
- union
- {
- __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */
-
- struct
- {
- __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */
- uint8_t : 7;
- } ECC1STS_b;
- };
-
- union
- {
- __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */
-
- struct
- {
- __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */
- __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */
- } ECCPRCR_b;
- };
- __IM uint8_t RESERVED4[11];
-
- union
- {
- __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */
-
- struct
- {
- __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */
- __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */
- } ECCPRCR2_b;
- };
- __IM uint8_t RESERVED5[3];
-
- union
- {
- __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */
-
- struct
- {
- __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */
- uint8_t : 7;
- } ECCETST_b;
- };
- __IM uint8_t RESERVED6[3];
-
- union
- {
- __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */
-
- struct
- {
- __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */
- uint8_t : 7;
- } ECCOAD_b;
- };
-} R_SRAM_Type; /*!< Size = 217 (0xd9) */
-
-/* =========================================================================================================================== */
-/* ================ R_BUS_B ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Bus Interface (R_BUS_B)
- */
-
-typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */
-{
- __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
- __IM uint32_t RESERVED[480];
- __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
-
- union
- {
- __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
-
- struct
- {
- __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
- __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
- } CSRECEN_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[543];
-
- union
- {
- __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTFHBIU_b;
- };
- __IM uint16_t RESERVED3;
-
- union
- {
- __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTFLBIU_b;
- };
- __IM uint16_t RESERVED4;
- __IM uint32_t RESERVED5[2];
-
- union
- {
- __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTS0BIU_b;
- };
- __IM uint16_t RESERVED6;
- __IM uint32_t RESERVED7[3];
-
- union
- {
- __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
- uint16_t : 15;
- } BUSSCNTPSBIU_b;
- };
- __IM uint16_t RESERVED8;
- __IM uint32_t RESERVED9[3];
-
- union
- {
- __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
- uint16_t : 15;
- } BUSSCNTPLBIU_b;
- };
- __IM uint16_t RESERVED10;
-
- union
- {
- __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
- uint16_t : 15;
- } BUSSCNTPHBIU_b;
- };
- __IM uint16_t RESERVED11;
- __IM uint32_t RESERVED12[2];
-
- union
- {
- __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTEQBIU_b;
- };
- __IM uint16_t RESERVED13;
-
- union
- {
- __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTEOBIU_b;
- };
- __IM uint16_t RESERVED14;
-
- union
- {
- __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */
-
- struct
- {
- __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
- uint16_t : 14;
- } BUSSCNTECBIU_b;
- };
- __IM uint16_t RESERVED15;
- __IM uint32_t RESERVED16[429];
- __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */
- __IM uint32_t RESERVED17[48];
- __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */
- __IM uint32_t RESERVED18[48];
-
- union
- {
- __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */
-
- struct
- {
- __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
- __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
- uint8_t : 1;
- __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
- __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
- uint8_t : 3;
- } BUS1ERRSTAT_b;
- };
- __IM uint8_t RESERVED19;
- __IM uint16_t RESERVED20;
- __IM uint32_t RESERVED21;
-
- union
- {
- __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */
-
- struct
- {
- __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
- __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
- uint8_t : 1;
- __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
- __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
- uint8_t : 3;
- } BUS1ERRCLR_b;
- };
- __IM uint8_t RESERVED22;
- __IM uint16_t RESERVED23;
- __IM uint32_t RESERVED24;
-
- union
- {
- __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */
-
- struct
- {
- __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
- __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
- uint8_t : 1;
- __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
- __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
- uint8_t : 3;
- } BUS2ERRSTAT_b;
- };
- __IM uint8_t RESERVED25;
- __IM uint16_t RESERVED26;
- __IM uint32_t RESERVED27;
-
- union
- {
- __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */
-
- struct
- {
- __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
- __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
- uint8_t : 1;
- __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
- __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
- uint8_t : 3;
- } BUS2ERRCLR_b;
- };
- __IM uint8_t RESERVED28;
- __IM uint16_t RESERVED29;
- __IM uint32_t RESERVED30;
-
- union
- {
- __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */
-
- struct
- {
- __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
- __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
- uint8_t : 1;
- __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
- __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
- uint8_t : 3;
- } BUS3ERRSTAT_b;
- };
- __IM uint8_t RESERVED31;
- __IM uint16_t RESERVED32;
-
- union
- {
- __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */
-
- struct
- {
- __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */
- uint8_t : 7;
- } DMACDTCERRSTAT_b;
- };
- __IM uint8_t RESERVED33;
- __IM uint16_t RESERVED34;
-
- union
- {
- __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */
-
- struct
- {
- __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
- __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
- uint8_t : 1;
- __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
- __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
- uint8_t : 3;
- } BUS3ERRCLR_b;
- };
- __IM uint8_t RESERVED35;
- __IM uint16_t RESERVED36;
-
- union
- {
- __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */
-
- struct
- {
- __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */
- uint8_t : 7;
- } DMACDTCERRCLR_b;
- };
- __IM uint8_t RESERVED37;
- __IM uint16_t RESERVED38;
-
- union
- {
- __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */
-
- struct
- {
- __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
- __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
- uint8_t : 1;
- __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
- __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
- uint8_t : 3;
- } BUS4ERRSTAT_b;
- };
- __IM uint8_t RESERVED39;
- __IM uint16_t RESERVED40;
- __IM uint32_t RESERVED41;
-
- union
- {
- __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */
-
- struct
- {
- __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
- __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
- uint8_t : 1;
- __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
- __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
- uint8_t : 3;
- } BUS4ERRCLR_b;
- };
- __IM uint8_t RESERVED42;
- __IM uint16_t RESERVED43;
-} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */
-
-/* =========================================================================================================================== */
-/* ================ R_SRC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Sampling Rate Converter (R_SRC)
- */
-
-typedef struct /*!< (@ 0x40048000) R_SRC Structure */
-{
- union
- {
- __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */
-
- struct
- {
- __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */
- uint32_t : 10;
- } SRCFCTR_b[5552];
- };
- __IM uint32_t RESERVED[588];
-
- union
- {
- __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */
-
- struct
- {
- __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to
- * input the data before sampling rate conversion. All the
- * bits are read as 0. */
- } SRCID_b;
- };
-
- union
- {
- __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */
-
- struct
- {
- __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output
- * the data after sampling rate conversion. The data in the
- * 16-stage output data FIFO is read through SRCOD. When the
- * number of data in the output data FIFO is zero after the
- * start of conversion, the value previously read is read
- * again. */
- } SRCOD_b;
- };
-
- union
- {
- __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */
-
- struct
- {
- __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */
- uint16_t : 6;
- __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */
- __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */
- uint16_t : 6;
- } SRCIDCTRL_b;
- };
-
- union
- {
- __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */
-
- struct
- {
- __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */
- uint16_t : 6;
- __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */
- __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */
- __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */
- uint16_t : 5;
- } SRCODCTRL_b;
- };
-
- union
- {
- __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */
-
- struct
- {
- __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */
- uint16_t : 1;
- __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */
- __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */
- __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */
- __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */
- __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */
- __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */
- __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */
- } SRCCTRL_b;
- };
-
- union
- {
- __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */
-
- struct
- {
- __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */
- __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */
- __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */
- __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */
- __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */
- __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */
- uint16_t : 1;
- __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units
- * in the input FIFO. */
- __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data
- * units in the output FIFO. */
- } SRCSTAT_b;
- };
-} R_SRC_Type; /*!< Size = 24576 (0x6000) */
-
-/* =========================================================================================================================== */
-/* ================ R_SSI0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
- */
-
-typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */
-{
- union
- {
- __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */
-
- struct
- {
- __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */
- __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */
- uint32_t : 1;
- __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
- * of outputting serial data is rewritten to 0 but data transmission
- * is not stopped. Write dummy data to the SSIFTDR not to
- * generate a transmit underflow because the number of data
- * in the transmit FIFO is decreasing. */
- __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */
- __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */
- __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */
- __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */
- __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */
- __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */
- __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */
- __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings
- * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
- * are prohibited. */
- uint32_t : 1;
- __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the
- * bit clock frequency/2 fs. */
- __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */
- __IOM uint32_t FRM : 2; /*!< [23..22] Channels */
- uint32_t : 1;
- __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */
- __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */
- __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */
- __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */
- __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */
- __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */
- uint32_t : 1;
- } SSICR_b;
- };
-
- union
- {
- __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */
-
- struct
- {
- __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */
- __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */
- __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */
- __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */
- __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */
- uint32_t : 18;
- __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */
- __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
- * Writable only to clear the flag. Confirm the value is 1
- * and then write 0. */
- __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
- * Writable only to clear the flag. Confirm the value is 1
- * and then write 0. */
- __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
- * Writable only to clear the flag. Confirm the value is 1
- * and then write 0. */
- __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
- * Writable only to clear the flag. Confirm the value is 1
- * and then write 0. */
- uint32_t : 2;
- } SSISR_b;
- };
- __IM uint32_t RESERVED[2];
-
- union
- {
- __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */
-
- struct
- {
- __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */
- __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */
- __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
- * clearing either the RDF flag (see the description of the
- * RDF bit for details) or RIE bit. */
- __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
- * clearing either the TDE flag (see the description of the
- * TDE bit for details) or TIE bit. */
- __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */
- __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
- * are the number of empty stages in SSIFTDR at which the
- * TDE flag is set. */
- uint32_t : 3;
- __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */
- uint32_t : 4;
- __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */
- uint32_t : 14;
- __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */
- } SSIFCR_b;
- };
-
- union
- {
- __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */
-
- struct
- {
- __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
- * is a 32-byte FIFO register, the maximum number of data
- * bytes that can be read from it while the RDF flag is 1
- * is indicated in the RDC[3:0] flags. If reading data from
- * the SSIFRDR register is continued after all the data is
- * read, undefined values will be read. */
- uint32_t : 7;
- __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
- * units stored in SSIFRDR) */
- uint32_t : 2;
- __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
- * is a 32-byte FIFO register, the maximum number of bytes
- * that can be written to it while the TDE flag is 1 is 8
- * - TDC[3:0]. If writing data to the SSIFTDR register is
- * continued after all the data is written, writing will be
- * invalid and an overflow occurs. */
- uint32_t : 7;
- __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
- * data units stored in SSIFTDR) */
- uint32_t : 2;
- } SSIFSR_b;
- };
-
- union
- {
- union
- {
- __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */
-
- struct
- {
- __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
- * eight stages of 32-bit registers for storing data to be
- * serially transmitted. NOTE: that when the SSIFTDR register
- * is full of data (32 bytes), the next data cannot be written
- * to it. If writing is attempted, it will be ignored and
- * an overflow occurs. */
- } SSIFTDR_b;
- };
- __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */
- __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */
- };
-
- union
- {
- union
- {
- __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */
-
- struct
- {
- __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
- * stages of 32-bit registers for storing serially received
- * data. */
- } SSIFRDR_b;
- };
- __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */
- __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */
- };
-
- union
- {
- __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */
-
- struct
- {
- __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */
- uint32_t : 6;
- __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */
- __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
- * Idle Status */
- uint32_t : 22;
- } SSIOFR_b;
- };
-
- union
- {
- __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */
-
- struct
- {
- __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */
- uint32_t : 3;
- __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */
- uint32_t : 19;
- } SSISCR_b;
- };
-} R_SSI0_Type; /*!< Size = 40 (0x28) */
-
-/* =========================================================================================================================== */
-/* ================ R_SYSTEM ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief System Pins (R_SYSTEM)
- */
-
-typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */
-{
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */
-
- struct
- {
- uint16_t : 14;
- __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */
- __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */
- } SBYCR_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[3];
-
- union
- {
- __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */
-
- struct
- {
- __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */
- __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */
- uint32_t : 3;
- __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */
- __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */
- __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */
- uint32_t : 14;
- __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */
- uint32_t : 9;
- } MSTPCRA_b;
- };
-
- union
- {
- __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */
-
- struct
- {
- __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */
- uint32_t : 1;
- __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */
- uint32_t : 1;
- __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */
- uint32_t : 1;
- __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */
- uint32_t : 1;
- __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */
- uint32_t : 5;
- __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */
- uint32_t : 1;
- __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */
- uint32_t : 1;
- } SCKDIVCR_b;
- };
-
- union
- {
- __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */
- uint8_t : 1;
- } SCKDIVCR2_b;
- };
- __IM uint8_t RESERVED3;
-
- union
- {
- __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */
-
- struct
- {
- __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */
- uint8_t : 5;
- } SCKSCR_b;
- };
- __IM uint8_t RESERVED4;
-
- union
- {
- __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */
-
- struct
- {
- __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */
- uint16_t : 2;
- __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */
- uint16_t : 3;
- __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
- * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
- * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
- * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
- * 111011: x30.0 */
- uint16_t : 2;
- } PLLCCR_b;
- };
-
- union
- {
- __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */
-
- struct
- {
- __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */
- uint8_t : 7;
- } PLLCR_b;
- };
-
- union
- {
- __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */
-
- struct
- {
- __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */
- uint8_t : 1;
- __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */
- } PLLCCR2_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */
-
- struct
- {
- __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */
- uint8_t : 7;
- } BCKCR_b;
- };
-
- union
- {
- __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */
-
- struct
- {
- __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
- * is prohibited when SCKDIVCR.ICK selects division by 1 and
- * SCKSCR.CKSEL[2:0] bits select thesystem clock source that
- * is faster than 32 MHz (ICLK > 32 MHz). */
- uint8_t : 7;
- } MEMWAIT_b;
- };
-
- union
- {
- __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */
-
- struct
- {
- __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */
- uint8_t : 7;
- } MOSCCR_b;
- };
- __IM uint8_t RESERVED6;
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */
-
- struct
- {
- __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */
- uint8_t : 7;
- } HOCOCR_b;
- };
- __IM uint8_t RESERVED8;
-
- union
- {
- __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */
-
- struct
- {
- __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */
- uint8_t : 7;
- } MOCOCR_b;
- };
-
- union
- {
- __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */
-
- struct
- {
- __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */
- uint8_t : 7;
- } FLLCR1_b;
- };
-
- union
- {
- __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */
-
- struct
- {
- __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
- * FLL reference clock select */
- uint16_t : 5;
- } FLLCR2_b;
- };
-
- union
- {
- __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */
-
- struct
- {
- __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
- * bit value after a reset is 1 when the OFS1.HOCOEN bit is
- * 0. It is 0 when the OFS1.HOCOEN bit is 1. */
- uint8_t : 2;
- __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */
- uint8_t : 1;
- __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */
- __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */
- uint8_t : 1;
- } OSCSF_b;
- };
- __IM uint8_t RESERVED9;
-
- union
- {
- __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */
-
- struct
- {
- __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */
- uint8_t : 1;
- __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */
- __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */
- } CKOCR_b;
- };
-
- union
- {
- __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */
-
- struct
- {
- __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */
- uint8_t : 3;
- __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */
- } TRCKCR_b;
- };
-
- union
- {
- __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */
-
- struct
- {
- __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */
- uint8_t : 6;
- __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */
- } OSTDCR_b;
- };
-
- union
- {
- __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */
-
- struct
- {
- __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */
- uint8_t : 7;
- } OSTDSR_b;
- };
- __IM uint16_t RESERVED10;
- __IM uint32_t RESERVED11;
-
- union
- {
- __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */
-
- struct
- {
- __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */
- uint16_t : 2;
- __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */
- uint16_t : 3;
- __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */
- uint16_t : 2;
- } PLL2CCR_b;
- };
-
- union
- {
- __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */
-
- struct
- {
- __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */
- uint8_t : 7;
- } PLL2CR_b;
- };
- __IM uint8_t RESERVED12;
-
- union
- {
- __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */
-
- struct
- {
- __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
- * (valid only when LPOPTEN = 1) */
- __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */
- __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
- * clock (valid only when LPOPT.LPOPTEN = 1) */
- uint8_t : 3;
- __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */
- } LPOPT_b;
- };
- __IM uint8_t RESERVED13;
- __IM uint16_t RESERVED14;
-
- union
- {
- __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */
-
- struct
- {
- __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */
- uint8_t : 4;
- __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */
- } SLCDSCKCR_b;
- };
- __IM uint8_t RESERVED15;
-
- union
- {
- __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */
-
- struct
- {
- __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */
- uint8_t : 7;
- } EBCKOCR_b;
- };
-
- union
- {
- __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */
-
- struct
- {
- __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */
- uint8_t : 7;
- } SDCKOCR_b;
- };
- __IM uint32_t RESERVED16[3];
- __IM uint8_t RESERVED17;
-
- union
- {
- __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */
-
- struct
- {
- __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
- * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
- * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
- +126 0111_1111 : +127These bits are added to original MOCO
- * trimming bits */
- } MOCOUTCR_b;
- };
-
- union
- {
- __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */
-
- struct
- {
- __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
- * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
- * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
- +126 0111_1111 : +127These bits are added to original HOCO
- * trimming bits */
- } HOCOUTCR_b;
- };
- __IM uint8_t RESERVED18;
- __IM uint32_t RESERVED19[2];
-
- union
- {
- __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */
- uint8_t : 5;
- } USBCKDIVCR_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */
- uint8_t : 5;
- } OCTACKDIVCR_b;
- };
-
- union
- {
- __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */
- uint8_t : 5;
- } SCISPICKDIVCR_b;
- };
- };
-
- union
- {
- __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */
- uint8_t : 5;
- } CANFDCKDIVCR_b;
- };
-
- union
- {
- __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */
- uint8_t : 5;
- } GPTCKDIVCR_b;
- };
-
- union
- {
- __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */
-
- struct
- {
- __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */
- uint8_t : 5;
- } IICCKDIVCR_b;
- };
- __IM uint8_t RESERVED20;
- __IM uint16_t RESERVED21;
-
- union
- {
- __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */
-
- struct
- {
- __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */
- __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */
- } USBCKCR_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */
-
- struct
- {
- __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */
- __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */
- } OCTACKCR_b;
- };
-
- union
- {
- __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */
-
- struct
- {
- __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */
- __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */
- } SCISPICKCR_b;
- };
- };
-
- union
- {
- __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */
-
- struct
- {
- __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */
- __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */
- } CANFDCKCR_b;
- };
-
- union
- {
- __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */
-
- struct
- {
- __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */
- __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */
- } GPTCKCR_b;
- };
-
- union
- {
- __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */
-
- struct
- {
- __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */
- __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */
- } IICCKCR_b;
- };
- __IM uint8_t RESERVED22;
- __IM uint16_t RESERVED23;
- __IM uint32_t RESERVED24[3];
-
- union
- {
- __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */
-
- struct
- {
- __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */
- __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */
- __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */
- uint32_t : 29;
- } SNZREQCR1_b;
- };
- __IM uint32_t RESERVED25;
- __IM uint16_t RESERVED26;
-
- union
- {
- __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */
-
- struct
- {
- __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
- * than in asynchronous mode. */
- __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */
- uint8_t : 5;
- __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */
- } SNZCR_b;
- };
- __IM uint8_t RESERVED27;
-
- union
- {
- __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */
-
- struct
- {
- __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */
- __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */
- __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */
- __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */
- __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */
- __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */
- __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */
- __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
- * to 1 other than in asynchronous mode. */
- } SNZEDCR_b;
- };
-
- union
- {
- __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */
-
- struct
- {
- __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */
- uint8_t : 7;
- } SNZEDCR1_b;
- };
- __IM uint16_t RESERVED28;
-
- union
- {
- __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */
-
- struct
- {
- __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */
- __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */
- __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */
- __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */
- __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */
- __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */
- __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */
- __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */
- __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */
- __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */
- __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */
- __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */
- __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */
- __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */
- __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */
- __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */
- uint32_t : 1;
- __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */
- uint32_t : 4;
- __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
- * request */
- __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
- * request */
- __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */
- __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */
- uint32_t : 2;
- __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
- * request */
- __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
- * snooze request */
- __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
- * snooze request */
- uint32_t : 1;
- } SNZREQCR_b;
- };
- __IM uint16_t RESERVED29;
-
- union
- {
- __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */
-
- struct
- {
- __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */
- uint8_t : 3;
- __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */
- uint8_t : 3;
- } FLSTOP_b;
- };
-
- union
- {
- __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */
-
- struct
- {
- __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */
- uint8_t : 6;
- } PSMCR_b;
- };
-
- union
- {
- __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */
-
- struct
- {
- __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */
- uint8_t : 2;
- __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */
- uint8_t : 3;
- } OPCCR_b;
- };
- __IM uint8_t RESERVED30;
-
- union
- {
- __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */
-
- struct
- {
- __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */
- uint8_t : 4;
- } MOSCWTCR_b;
- };
- __IM uint8_t RESERVED31[2];
-
- union
- {
- __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */
-
- struct
- {
- __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
- * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */
- uint8_t : 5;
- } HOCOWTCR_b;
- };
- __IM uint16_t RESERVED32[2];
-
- union
- {
- __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */
-
- struct
- {
- __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */
- uint8_t : 3;
- __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */
- uint8_t : 3;
- } SOPCCR_b;
- };
- __IM uint8_t RESERVED33;
- __IM uint32_t RESERVED34[5];
-
- union
- {
- __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */
-
- struct
- {
- __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
- * only to clear the flag. Confirm the value is 1 and then
- * write 0. */
- __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
- * clear the flag. Confirm the value is 1 and then write 0. */
- __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
- * the flag. Confirm the value is 1 and then write 0. */
- uint16_t : 5;
- __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
- * clear the flag. Confirm the value is 1 and then write 0. */
- __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
- * the flag. Confirm the value is 1 and then write 0. */
- __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */
- uint16_t : 1;
- __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */
- } RSTSR1_b;
- };
- __IM uint16_t RESERVED35;
- __IM uint32_t RESERVED36[3];
-
- union
- {
- __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */
-
- struct
- {
- __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
- * (UCLK). */
- uint8_t : 7;
- } USBCKCR_ALT_b;
- };
-
- union
- {
- __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
- * Register */
-
- struct
- {
- __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */
- uint8_t : 6;
- __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */
- } SDADCCKCR_b;
- };
- __IM uint16_t RESERVED37;
- __IM uint32_t RESERVED38[3];
-
- union
- {
- __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */
-
- struct
- {
- __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
- __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
- uint8_t : 5;
- } LVD1CR1_b;
- };
-
- union
- {
- __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */
-
- struct
- {
- __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
- * 0 can be written to this bit. After writing 0 to this bit,
- * it takes 2 system clock cycles for the bit to be read as
- * 0. */
- __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */
- uint8_t : 6;
- } LVD1SR_b;
- };
-
- union
- {
- __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */
-
- struct
- {
- __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
- __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
- uint8_t : 5;
- } LVD2CR1_b;
- };
-
- union
- {
- __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */
-
- struct
- {
- __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
- * 0 can be written to this bit. After writing 0 to this bit,
- * it takes 2 system clock cycles for the bit to be read as
- * 0. */
- __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */
- uint8_t : 6;
- } LVD2SR_b;
- };
- __IM uint32_t RESERVED39[183];
-
- union
- {
- __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
- * Register */
-
- struct
- {
- __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */
- uint32_t : 1;
- __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */
- __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */
- __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */
- __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */
- __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */
- __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */
- __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */
- __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */
- uint32_t : 1;
- __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */
- __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */
- uint32_t : 3;
- __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */
- __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */
- uint32_t : 14;
- } CGFSAR_b;
- };
- __IM uint32_t RESERVED40;
-
- union
- {
- __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */
-
- struct
- {
- __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
- uint32_t : 1;
- __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
- uint32_t : 1;
- __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */
- uint32_t : 3;
- __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */
- __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */
- uint32_t : 22;
- } LPMSAR_b;
- };
-
- union
- {
- union
- {
- __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */
-
- struct
- {
- __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
- __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
- uint32_t : 30;
- } LVDSAR_b;
- };
-
- union
- {
- __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */
-
- struct
- {
- __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
- __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
- __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
- uint32_t : 29;
- } RSTSAR_b;
- };
- };
-
- union
- {
- __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */
-
- struct
- {
- __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */
- __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */
- __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */
- uint32_t : 13;
- __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */
- __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */
- __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */
- __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */
- __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */
- __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */
- __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */
- __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */
- uint32_t : 8;
- } BBFSAR_b;
- };
- __IM uint32_t RESERVED41[3];
-
- union
- {
- __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
- * Register */
-
- struct
- {
- __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
- * 0 */
- __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
- * 1 */
- __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
- * 2 */
- __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
- * 3 */
- __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
- * 4 */
- __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
- * 5 */
- __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
- * 6 */
- __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
- * 7 */
- __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
- * 8 */
- __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
- * 9 */
- __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
- * 10 */
- __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
- * 11 */
- __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
- * 12 */
- __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
- * 13 */
- __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
- * 14 */
- __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
- * 15 */
- __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
- * 16 */
- __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
- * 17 */
- __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
- * 18 */
- __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
- * 19 */
- __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
- * 20 */
- uint32_t : 3;
- __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
- * 24 */
- uint32_t : 1;
- __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
- * 26 */
- __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
- * 27 */
- uint32_t : 4;
- } DPFSAR_b;
- };
- __IM uint32_t RESERVED42[6];
- __IM uint16_t RESERVED43;
-
- union
- {
- __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */
-
- struct
- {
- __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock
- * generation circuit. */
- __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating
- * modes, the low power consumption modes and the battery
- * backup function. */
- uint16_t : 1;
- __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */
- __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */
- uint16_t : 3;
- __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */
- } PRCR_b;
- };
-
- union
- {
- __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */
-
- struct
- {
- __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */
- uint8_t : 4;
- __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */
- __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */
- } DPSBYCR_b;
- };
-
- union
- {
- __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */
-
- struct
- {
- __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */
- uint8_t : 2;
- } DPSWCR_b;
- };
-
- union
- {
- __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */
-
- struct
- {
- __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */
- } DPSIER0_b;
- };
-
- union
- {
- __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */
-
- struct
- {
- __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */
- __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */
- } DPSIER1_b;
- };
-
- union
- {
- __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */
-
- struct
- {
- __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */
- __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */
- __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */
- __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */
- __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */
- uint8_t : 3;
- } DPSIER2_b;
- };
-
- union
- {
- __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */
-
- struct
- {
- __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */
- __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */
- __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */
- __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */
- uint8_t : 4;
- } DPSIER3_b;
- };
-
- union
- {
- __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */
-
- struct
- {
- __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */
- } DPSIFR0_b;
- };
-
- union
- {
- __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */
-
- struct
- {
- __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */
- __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */
- } DPSIFR1_b;
- };
-
- union
- {
- __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */
-
- struct
- {
- __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */
- __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */
- __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */
- __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */
- __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */
- uint8_t : 3;
- } DPSIFR2_b;
- };
-
- union
- {
- __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */
-
- struct
- {
- __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */
- __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */
- __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */
- __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */
- uint8_t : 4;
- } DPSIFR3_b;
- };
-
- union
- {
- __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */
-
- struct
- {
- __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */
- } DPSIEGR0_b;
- };
-
- union
- {
- __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */
-
- struct
- {
- __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */
- __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */
- } DPSIEGR1_b;
- };
-
- union
- {
- __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */
-
- struct
- {
- __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */
- __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */
- uint8_t : 2;
- __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */
- uint8_t : 3;
- } DPSIEGR2_b;
- };
- __IM uint8_t RESERVED44;
-
- union
- {
- __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */
-
- struct
- {
- __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */
- uint8_t : 6;
- __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */
- } SYOCDCR_b;
- };
-
- union
- {
- __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */
-
- struct
- {
- __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */
- uint8_t : 6;
- } STCONR_b;
- };
-
- union
- {
- __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */
-
- struct
- {
- __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
- * the flag. Confirm the value is 1 and then write 0. */
- __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
- * to clear the flag. Confirm the value is 1 and then write
- * 0. */
- uint8_t : 3;
- __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
- * clear the flag. Confirm the value is 1 and then write 0. */
- } RSTSR0_b;
- };
-
- union
- {
- __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */
-
- struct
- {
- __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */
- uint8_t : 7;
- } RSTSR2_b;
- };
- __IM uint8_t RESERVED45;
-
- union
- {
- __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
- * Register */
-
- struct
- {
- uint8_t : 3;
- __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */
- __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */
- __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */
- __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
- * Enable */
- } MOMCR_b;
- };
- __IM uint16_t RESERVED46;
-
- union
- {
- __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */
-
- struct
- {
- __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */
- uint8_t : 6;
- } FWEPROR_b;
- };
-
- union
- {
- union
- {
- __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */
-
- struct
- {
- uint8_t : 5;
- __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */
- __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */
- uint8_t : 1;
- } LVCMPCR_b;
- };
-
- union
- {
- __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */
-
- struct
- {
- __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
- * drop in voltage) */
- uint8_t : 2;
- __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */
- } LVD1CMPCR_b;
- };
- };
-
- union
- {
- union
- {
- __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */
-
- struct
- {
- __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
- * fall in voltage) */
- __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
- * fall in voltage) */
- } LVDLVLR_b;
- };
-
- union
- {
- __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */
-
- struct
- {
- __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
- * drop in voltage) */
- uint8_t : 4;
- __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */
- } LVD2CMPCR_b;
- };
- };
- __IM uint8_t RESERVED47;
-
- union
- {
- __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */
-
- struct
- {
- __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
- __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
- __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
- uint8_t : 1;
- __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
- __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
- __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
- } LVD1CR0_b;
- };
-
- union
- {
- __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */
-
- struct
- {
- __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
- __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
- __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
- uint8_t : 1;
- __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
- __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
- __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
- } LVD2CR0_b;
- };
- __IM uint8_t RESERVED48;
-
- union
- {
- __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
- * Register */
-
- struct
- {
- __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */
- uint8_t : 7;
- } VBATTMNSELR_b;
- };
-
- union
- {
- __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */
-
- struct
- {
- __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */
- uint8_t : 7;
- } VBATTMONR_b;
- };
-
- union
- {
- __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */
-
- struct
- {
- __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */
- uint8_t : 7;
- } VBTCR1_b;
- };
- __IM uint32_t RESERVED49[8];
-
- union
- {
- __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */
-
- struct
- {
- __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */
- __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */
- uint8_t : 2;
- __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */
- __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */
- __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */
- __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */
- } DCDCCTL_b;
- };
-
- union
- {
- __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */
-
- struct
- {
- __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */
- uint8_t : 6;
- } VCCSEL_b;
- };
- __IM uint16_t RESERVED50;
- __IM uint32_t RESERVED51[15];
-
- union
- {
- __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */
-
- struct
- {
- __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */
- uint8_t : 7;
- } SOSCCR_b;
- };
-
- union
- {
- __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */
-
- struct
- {
- __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */
- uint8_t : 6;
- } SOMCR_b;
- };
- __IM uint16_t RESERVED52;
- __IM uint32_t RESERVED53[3];
-
- union
- {
- __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */
-
- struct
- {
- __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */
- uint8_t : 7;
- } LOCOCR_b;
- };
- __IM uint8_t RESERVED54;
-
- union
- {
- __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */
-
- struct
- {
- __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
- * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
- * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
- +126 0111_1111 : +127These bits are added to original LOCO
- * trimming bits */
- } LOCOUTCR_b;
- };
- __IM uint8_t RESERVED55;
- __IM uint32_t RESERVED56[7];
-
- union
- {
- __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */
- uint8_t : 1;
- __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */
- } VBTCR2_b;
- };
-
- union
- {
- __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */
-
- struct
- {
- __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */
- __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */
- uint8_t : 2;
- __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */
- uint8_t : 3;
- } VBTSR_b;
- };
-
- union
- {
- __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */
-
- struct
- {
- __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */
- uint8_t : 7;
- } VBTCMPCR_b;
- };
- __IM uint8_t RESERVED57;
-
- union
- {
- __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
- * Register */
-
- struct
- {
- __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */
- __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */
- uint8_t : 6;
- } VBTLVDICR_b;
- };
- __IM uint8_t RESERVED58;
-
- union
- {
- __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */
-
- struct
- {
- __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */
- uint8_t : 7;
- } VBTWCTLR_b;
- };
- __IM uint8_t RESERVED59;
-
- union
- {
- __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */
-
- struct
- {
- uint8_t : 1;
- __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */
- __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */
- __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */
- __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */
- __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */
- uint8_t : 2;
- } VBTWCH0OTSR_b;
- };
-
- union
- {
- __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */
-
- struct
- {
- __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */
- uint8_t : 1;
- __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */
- __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */
- __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */
- __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */
- uint8_t : 2;
- } VBTWCH1OTSR_b;
- };
-
- union
- {
- __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */
-
- struct
- {
- __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */
- __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */
- uint8_t : 1;
- __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */
- __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */
- __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */
- uint8_t : 2;
- } VBTWCH2OTSR_b;
- };
-
- union
- {
- __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */
-
- struct
- {
- __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */
- __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */
- __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */
- uint8_t : 5;
- } VBTICTLR_b;
- };
-
- union
- {
- __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */
-
- struct
- {
- __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */
- __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */
- __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */
- __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */
- __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */
- __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */
- uint8_t : 2;
- } VBTOCTLR_b;
- };
-
- union
- {
- __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */
-
- struct
- {
- __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */
- __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */
- __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */
- __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */
- __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */
- __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */
- uint8_t : 2;
- } VBTWTER_b;
- };
-
- union
- {
- __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */
-
- struct
- {
- __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */
- __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */
- __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */
- uint8_t : 5;
- } VBTWEGR_b;
- };
-
- union
- {
- __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */
-
- struct
- {
- __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */
- __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */
- __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */
- __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */
- __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */
- __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */
- uint8_t : 2;
- } VBTWFR_b;
- };
-
- union
- {
- __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */
-
- struct
- {
- uint8_t : 3;
- __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */
- uint8_t : 4;
- } VBTBER_b;
- };
- __IM uint8_t RESERVED60;
- __IM uint16_t RESERVED61;
- __IM uint32_t RESERVED62[15];
-
- union
- {
- __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */
-
- struct
- {
- __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
- * data powered by VBATT.The value of this register is retained
- * even when VCC is not powered but VBATT is powered.VBTBKR
- * is initialized by VBATT selected voltage power-on-reset. */
- } VBTBKR_b[512];
- };
-} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Temperature Sensor (R_TSN)
- */
-
-typedef struct /*!< (@ 0x407EC000) R_TSN Structure */
-{
- __IM uint8_t RESERVED[552];
-
- union
- {
- __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
- * L */
-
- struct
- {
- __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
- } TSCDRL_b;
- };
-
- union
- {
- __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
- * H */
-
- struct
- {
- __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the
- * convertedvalue. */
- } TSCDRH_b;
- };
-} R_TSN_Type; /*!< Size = 554 (0x22a) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN_CAL ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Temperature Sensor (R_TSN_CAL)
- */
-
-typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */
-{
- union
- {
- __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */
-
- struct
- {
- __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
- * calibration converted value. */
- } TSCDR_b;
- };
-} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN_CTRL ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Temperature Sensor (R_TSN_CTRL)
- */
-
-typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */
-{
- union
- {
- __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */
- uint8_t : 2;
- __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */
- } TSCR_b;
- };
-} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */
-
-/* =========================================================================================================================== */
-/* ================ R_USB_FS0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief USB 2.0 Module (R_USB_FS0)
- */
-
-typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */
-{
- union
- {
- __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
-
- struct
- {
- __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
- uint16_t : 2;
- __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */
- __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
- __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
- __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
- uint16_t : 1;
- __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */
- uint16_t : 1;
- __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */
- uint16_t : 5;
- } SYSCFG_b;
- };
-
- union
- {
- __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
-
- struct
- {
- __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
- * access cycles) */
- uint16_t : 12;
- } BUSWAIT_b;
- };
-
- union
- {
- __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */
-
- struct
- {
- __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
- __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */
- uint16_t : 2;
- __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
- * Selected. */
- __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */
- uint16_t : 7;
- __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
- * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
- * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
- * pin. */
- } SYSSTS0_b;
- };
-
- union
- {
- __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
-
- struct
- {
- __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
- uint16_t : 15;
- } PLLSTA_b;
- };
-
- union
- {
- __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
-
- struct
- {
- __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
- uint16_t : 1;
- __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */
- __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */
- __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */
- __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */
- __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */
- __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */
- __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */
- __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
- * used when switching from device B to device A while in
- * OTG mode. If the HNPBTOA bit is 1, the internal function
- * control keeps the suspended state until the HNP processing
- * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
- * set. */
- uint16_t : 4;
- } DVSTCTR0_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
-
- struct
- {
- __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
- uint16_t : 12;
- } TESTMODE_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
- __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED3;
- __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
- __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED4;
- __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
- __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED5;
- __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */
- uint16_t : 1;
- __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */
- uint16_t : 2;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
- uint16_t : 2;
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } CFIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } CFIFOCTR_b;
- };
- __IM uint32_t RESERVED6;
-
- union
- {
- __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
- uint16_t : 4;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
- __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
- __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
- * Pipe Data is Read */
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } D0FIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } D0FIFOCTR_b;
- };
-
- union
- {
- __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
- uint16_t : 4;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
- __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
- __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
- * Pipe Data is Read */
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } D1FIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } D1FIFOCTR_b;
- };
-
- union
- {
- __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
- __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
- __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
- __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
- __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
- __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
- __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
- __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
- } INTENB0_b;
- };
-
- union
- {
- __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
-
- struct
- {
- __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
- uint16_t : 3;
- __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
- __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
- __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
- uint16_t : 4;
- __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
- __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
- __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */
- } INTENB1_b;
- };
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */
- uint16_t : 6;
- } BRDYENB_b;
- };
-
- union
- {
- __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */
- uint16_t : 6;
- } NRDYENB_b;
- };
-
- union
- {
- __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */
- uint16_t : 6;
- } BEMPENB_b;
- };
-
- union
- {
- __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */
-
- struct
- {
- uint16_t : 4;
- __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */
- __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
- __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */
- uint16_t : 1;
- __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */
- uint16_t : 7;
- } SOFCFG_b;
- };
-
- union
- {
- __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
-
- struct
- {
- __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
- __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
- uint16_t : 1;
- __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
- __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
- uint16_t : 2;
- __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
- uint16_t : 1;
- __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
- uint16_t : 3;
- __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
- } PHYSET_b;
- };
-
- union
- {
- __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
-
- struct
- {
- __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
- __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
- __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
- __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
- __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
- __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
- __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
- __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
- __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
- __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
- __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
- __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
- } INTSTS0_b;
- };
-
- union
- {
- __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
-
- struct
- {
- __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */
- uint16_t : 3;
- __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
- __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
- __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
- __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */
- __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
- __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */
- } INTSTS1_b;
- };
- __IM uint16_t RESERVED8;
-
- union
- {
- __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */
- uint16_t : 6;
- } BRDYSTS_b;
- };
-
- union
- {
- __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */
- uint16_t : 6;
- } NRDYSTS_b;
- };
-
- union
- {
- __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */
- uint16_t : 6;
- } BEMPSTS_b;
- };
-
- union
- {
- __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
-
- struct
- {
- __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */
- uint16_t : 3;
- __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */
- __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
- } FRMNUM_b;
- };
-
- union
- {
- __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
-
- struct
- {
- __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
- uint16_t : 12;
- __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
- } UFRMNUM_b;
- };
-
- union
- {
- __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
-
- struct
- {
- __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate
- * the USB address assigned by the host when the USBHS processed
- * the SET_ADDRESS request successfully. */
- uint16_t : 1;
- __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
- uint16_t : 5;
- } USBADDR_b;
- };
- __IM uint16_t RESERVED9;
-
- union
- {
- __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
-
- struct
- {
- __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
- * value. */
- __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */
- } USBREQ_b;
- };
-
- union
- {
- __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
-
- struct
- {
- __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */
- } USBVAL_b;
- };
-
- union
- {
- __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
-
- struct
- {
- __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */
- } USBINDX_b;
- };
-
- union
- {
- __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
-
- struct
- {
- __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */
- } USBLENG_b;
- };
-
- union
- {
- __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
-
- struct
- {
- uint16_t : 4;
- __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
- uint16_t : 2;
- __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
- __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
- uint16_t : 7;
- } DCPCFG_b;
- };
-
- union
- {
- __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
-
- struct
- {
- __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
- * of data (maximum packet size) in payloads for the DCP. */
- uint16_t : 5;
- __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
- } DCPMAXP_b;
- };
-
- union
- {
- __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
-
- struct
- {
- __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
- __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
- uint16_t : 2;
- __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
- __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
- __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
- __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
- uint16_t : 2;
- __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
- uint16_t : 2;
- __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */
- __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
- } DCPCTR_b;
- };
- __IM uint16_t RESERVED10;
-
- union
- {
- __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
-
- struct
- {
- __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */
- uint16_t : 12;
- } PIPESEL_b;
- };
- __IM uint16_t RESERVED11;
-
- union
- {
- __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
-
- struct
- {
- __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
- * for the selected pipe.Setting 0000b means unused pipe. */
- __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
- uint16_t : 2;
- __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
- uint16_t : 1;
- __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
- __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
- uint16_t : 3;
- __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
- } PIPECFG_b;
- };
- __IM uint16_t RESERVED12;
-
- union
- {
- __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
-
- struct
- {
- __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
- * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
- * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
- * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
- * 64 bytes (040h) (Bits [8:7] are not provided.) */
- uint16_t : 3;
- __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
- } PIPEMAXP_b;
- };
-
- union
- {
- __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
-
- struct
- {
- __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
- * error detection timing for the selected pipe in terms of
- * frames, which is expressed as nth power of 2. */
- uint16_t : 9;
- __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
- uint16_t : 3;
- } PIPEPERI_b;
- };
-
- union
- {
- __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */
-
- struct
- {
- __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
- uint16_t : 3;
- __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
- __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */
- __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
- __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
- __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */
- __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */
- uint16_t : 1;
- __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
- * Split Transaction of the relevant pipe */
- __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
- * the CSSTS bit of the relevant pipe */
- __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */
- __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
- } PIPE_CTR_b[9];
- };
- __IM uint16_t RESERVED13;
- __IM uint32_t RESERVED14[3];
- __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
- __IM uint32_t RESERVED15[3];
-
- union
- {
- __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */
-
- struct
- {
- __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */
- __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */
- __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
- __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
- __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
- __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */
- uint16_t : 1;
- __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
- __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */
- __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */
- uint16_t : 6;
- } USBBCCTRL0_b;
- };
- __IM uint16_t RESERVED16;
- __IM uint32_t RESERVED17[4];
-
- union
- {
- __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */
-
- struct
- {
- __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */
- uint16_t : 15;
- } UCKSEL_b;
- };
- __IM uint16_t RESERVED18;
- __IM uint32_t RESERVED19;
-
- union
- {
- __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */
-
- struct
- {
- __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */
- uint16_t : 6;
- __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */
- uint16_t : 8;
- } USBMC_b;
- };
- __IM uint16_t RESERVED20;
-
- union
- {
- __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
-
- struct
- {
- uint16_t : 6;
- __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
- __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
- __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
- uint16_t : 1;
- } DEVADD_b[10];
- };
- __IM uint32_t RESERVED21[3];
-
- union
- {
- __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */
-
- struct
- {
- __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */
- __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */
- __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */
- __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */
- uint32_t : 28;
- } PHYSLEW_b;
- };
- __IM uint32_t RESERVED22[3];
-
- union
- {
- __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
-
- struct
- {
- uint16_t : 7;
- __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
- uint16_t : 8;
- } LPCTRL_b;
- };
-
- union
- {
- __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
-
- struct
- {
- uint16_t : 14;
- __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
- uint16_t : 1;
- } LPSTS_b;
- };
- __IM uint32_t RESERVED23[15];
-
- union
- {
- __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
-
- struct
- {
- __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
- __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
- __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
- __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
- __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
- __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
- uint16_t : 2;
- __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
- __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
- uint16_t : 6;
- } BCCTRL_b;
- };
- __IM uint16_t RESERVED24;
-
- union
- {
- __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
-
- struct
- {
- __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
- __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
- __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
- * only when the L1RESPMD[1:0] value is 2'b11. */
- __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
- * the L1 state together with the device state bits DVSQ[2:0]. */
- __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
- * value used for L1NEGOMD.The format is the same as the HIRD
- * field in HL1CTRL. */
- uint16_t : 2;
- __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
- uint16_t : 1;
- } PL1CTRL1_b;
- };
-
- union
- {
- __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
- __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
- uint16_t : 3;
- } PL1CTRL2_b;
- };
-
- union
- {
- __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
-
- struct
- {
- __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
- __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
- uint16_t : 13;
- } HL1CTRL1_b;
- };
-
- union
- {
- __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
-
- struct
- {
- __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
- * be set in the ADDR field of LPM token. */
- uint16_t : 4;
- __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
- __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
- * value to be set in the RWE field of LPM token. */
- uint16_t : 2;
- __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
- * period at the time of L1 Resume. */
- } HL1CTRL2_b;
- };
- __IM uint32_t RESERVED25[5];
-
- union
- {
- __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
- * Register */
-
- struct
- {
- uint32_t : 20;
- __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
- * HS side of USB port. */
- __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
- * HS side of USB port. */
- uint32_t : 1;
- __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
- * of USB port. */
- uint32_t : 8;
- } DPUSR0R_b;
- };
-
- union
- {
- __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
-
- struct
- {
- uint32_t : 4;
- __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
- __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
- uint32_t : 1;
- __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
- uint32_t : 12;
- __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
- __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
- uint32_t : 1;
- __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
- uint32_t : 8;
- } DPUSR1R_b;
- };
-
- union
- {
- __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
-
- struct
- {
- __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
- __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
- uint16_t : 2;
- __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
- * port. */
- __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
- * port. */
- uint16_t : 2;
- __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
- __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
- uint16_t : 6;
- } DPUSR2R_b;
- };
-
- union
- {
- __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
-
- struct
- {
- __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
- __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
- uint16_t : 14;
- } DPUSRCR_b;
- };
- __IM uint32_t RESERVED26[165];
-
- union
- {
- __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
- * Monitor Register */
-
- struct
- {
- __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */
- __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */
- uint32_t : 1;
- __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */
- __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */
- uint32_t : 11;
- __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
- __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */
- uint32_t : 2;
- __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
- * of the USB. */
- __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
- * of the USB. */
- uint32_t : 1;
- __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
- * USB. */
- uint32_t : 8;
- } DPUSR0R_FS_b;
- };
-
- union
- {
- __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
- * Register */
-
- struct
- {
- __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */
- __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */
- uint32_t : 2;
- __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */
- __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */
- uint32_t : 1;
- __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */
- uint32_t : 8;
- __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */
- __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */
- uint32_t : 2;
- __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */
- __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */
- uint32_t : 1;
- __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */
- uint32_t : 8;
- } DPUSR1R_FS_b;
- };
-} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */
-
-/* =========================================================================================================================== */
-/* ================ R_USB_HS0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief USB 2.0 Module (R_USB_HS0)
- */
-
-typedef struct /*!< (@ 0x40090000) R_USB_HS0 Structure */
-{
- union
- {
- __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
-
- struct
- {
- __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
- uint16_t : 3;
- __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
- __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
- __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
- __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */
- __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */
- uint16_t : 1;
- __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */
- } SYSCFG_b;
- };
-
- union
- {
- __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
-
- struct
- {
- __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
- * access cycles) */
- } BUSWAIT_b;
- };
-
- union
- {
- __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */
-
- struct
- {
- __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
- __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */
- uint16_t : 2;
- __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
- * Selected. */
- __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */
- uint16_t : 7;
- __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
- * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
- * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
- * pin. */
- } SYSSTS0_b;
- };
-
- union
- {
- __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
-
- struct
- {
- __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
- } PLLSTA_b;
- };
-
- union
- {
- __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
-
- struct
- {
- __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
- uint16_t : 1;
- __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */
- __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */
- __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */
- __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */
- __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */
- __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */
- __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */
- __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
- * used when switching from device B to device A while in
- * OTG mode. If the HNPBTOA bit is 1, the internal function
- * control keeps the suspended state until the HNP processing
- * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
- * set. */
- } DVSTCTR0_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
-
- struct
- {
- __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
- } TESTMODE_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
- __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED3;
- __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
- __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED4;
- __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
-
- struct
- {
- union
- {
- __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
- __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
- };
-
- union
- {
- __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
-
- struct
- {
- __IM uint8_t RESERVED5;
- __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
- };
- };
- };
- };
-
- union
- {
- __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */
- uint16_t : 1;
- __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */
- uint16_t : 2;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
- uint16_t : 2;
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } CFIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } CFIFOCTR_b;
- };
- __IM uint32_t RESERVED6;
-
- union
- {
- __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
- uint16_t : 4;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
- __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
- __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
- * Pipe Data is Read */
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } D0FIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } D0FIFOCTR_b;
- };
-
- union
- {
- __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
-
- struct
- {
- __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
- uint16_t : 4;
- __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
- uint16_t : 1;
- __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
- __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
- __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
- * Pipe Data is Read */
- __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
- __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
- } D1FIFOSEL_b;
- };
-
- union
- {
- __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
-
- struct
- {
- __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
- * data. */
- uint16_t : 1;
- __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
- __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
- __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
- } D1FIFOCTR_b;
- };
-
- union
- {
- __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
- __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
- __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
- __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
- __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
- __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
- __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
- __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
- } INTENB0_b;
- };
-
- union
- {
- __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
-
- struct
- {
- __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
- uint16_t : 3;
- __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
- __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
- __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */
- __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
- __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
- uint16_t : 1;
- __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
- __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */
- } INTENB1_b;
- };
- __IM uint16_t RESERVED7;
-
- union
- {
- __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */
- } BRDYENB_b;
- };
-
- union
- {
- __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */
- } NRDYENB_b;
- };
-
- union
- {
- __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
-
- struct
- {
- __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */
- __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */
- } BEMPENB_b;
- };
-
- union
- {
- __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */
-
- struct
- {
- uint16_t : 4;
- __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */
- __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
- __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */
- uint16_t : 1;
- __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */
- } SOFCFG_b;
- };
-
- union
- {
- __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
-
- struct
- {
- __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
- __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
- uint16_t : 1;
- __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
- __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
- uint16_t : 2;
- __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
- uint16_t : 1;
- __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
- uint16_t : 3;
- __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
- } PHYSET_b;
- };
-
- union
- {
- __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
-
- struct
- {
- __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
- __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
- __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
- __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
- __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
- __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
- __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
- __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
- __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
- __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
- __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
- __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
- } INTSTS0_b;
- };
-
- union
- {
- __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
-
- struct
- {
- __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */
- uint16_t : 3;
- __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
- __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
- __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
- __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */
- __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
- uint16_t : 1;
- __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
- __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */
- } INTSTS1_b;
- };
- __IM uint16_t RESERVED8;
-
- union
- {
- __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */
- } BRDYSTS_b;
- };
-
- union
- {
- __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */
- __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */
- } NRDYSTS_b;
- };
-
- union
- {
- __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
-
- struct
- {
- __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */
- __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */
- } BEMPSTS_b;
- };
-
- union
- {
- __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
-
- struct
- {
- __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */
- uint16_t : 3;
- __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */
- __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
- } FRMNUM_b;
- };
-
- union
- {
- __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
-
- struct
- {
- __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
- uint16_t : 12;
- __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
- } UFRMNUM_b;
- };
-
- union
- {
- __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
-
- struct
- {
- __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate
- * the USB address assigned by the host when the USBHS processed
- * the SET_ADDRESS request successfully. */
- uint16_t : 1;
- __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
- } USBADDR_b;
- };
- __IM uint16_t RESERVED9;
-
- union
- {
- __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
-
- struct
- {
- __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
- * value. */
- __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */
- } USBREQ_b;
- };
-
- union
- {
- __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
-
- struct
- {
- __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */
- } USBVAL_b;
- };
-
- union
- {
- __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
-
- struct
- {
- __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */
- } USBINDX_b;
- };
-
- union
- {
- __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
-
- struct
- {
- __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */
- } USBLENG_b;
- };
-
- union
- {
- __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
-
- struct
- {
- uint16_t : 4;
- __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
- uint16_t : 2;
- __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
- __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
- } DCPCFG_b;
- };
-
- union
- {
- __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
-
- struct
- {
- __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
- * of data (maximum packet size) in payloads for the DCP. */
- uint16_t : 5;
- __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
- } DCPMAXP_b;
- };
-
- union
- {
- __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
-
- struct
- {
- __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
- __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
- uint16_t : 1;
- __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */
- __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
- __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
- __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
- __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
- uint16_t : 2;
- __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
- __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */
- __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */
- __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */
- __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
- } DCPCTR_b;
- };
- __IM uint16_t RESERVED10;
-
- union
- {
- __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
-
- struct
- {
- __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */
- } PIPESEL_b;
- };
- __IM uint16_t RESERVED11;
-
- union
- {
- __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
-
- struct
- {
- __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
- * for the selected pipe.Setting 0000b means unused pipe. */
- __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
- uint16_t : 2;
- __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
- __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
- __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
- __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
- uint16_t : 3;
- __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
- } PIPECFG_b;
- };
-
- union
- {
- __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A)Pipe Buffer Register */
-
- struct
- {
- __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the
- * selected pipe (04h to 87h). */
- uint16_t : 2;
- __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */
- } PIPEBUF_b; /*!< BitSize */
- };
-
- union
- {
- __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
-
- struct
- {
- __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
- * 1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
- * (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not
- * provided.)PIPE6 to PIPE9: 1 byte (001h) to
- * 64 bytes (040h) (Bits [10:7] are not provided.) */
- uint16_t : 1;
- __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
- } PIPEMAXP_b;
- };
-
- union
- {
- __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
-
- struct
- {
- __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
- * error detection timing for the selected pipe in terms of
- * frames, which is expressed as nth power of 2. */
- uint16_t : 9;
- __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
- } PIPEPERI_b;
- };
-
- union
- {
- __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */
-
- struct
- {
- __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
- uint16_t : 3;
- __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
- __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */
- __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
- __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
- __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */
- __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */
- uint16_t : 1;
- __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
- * Split Transaction of the relevant pipe */
- __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
- * the CSSTS bit of the relevant pipe */
- __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */
- __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
- } PIPE_CTR_b[9];
- };
- __IM uint16_t RESERVED13;
- __IM uint32_t RESERVED14[3];
- __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
- __IM uint32_t RESERVED15[11];
-
- union
- {
- __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
-
- struct
- {
- uint16_t : 6;
- __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
- __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
- __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
- } DEVADD_b[10];
- };
- __IM uint16_t RESERVED16;
- __IM uint32_t RESERVED17[6];
-
- union
- {
- __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
-
- struct
- {
- uint16_t : 7;
- __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
- } LPCTRL_b;
- };
-
- union
- {
- __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
-
- struct
- {
- uint16_t : 14;
- __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
- } LPSTS_b;
- };
- __IM uint32_t RESERVED18[15];
-
- union
- {
- __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
-
- struct
- {
- __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
- __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
- __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
- __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
- __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
- __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
- uint16_t : 2;
- __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
- __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
- } BCCTRL_b;
- };
- __IM uint16_t RESERVED19;
-
- union
- {
- __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
-
- struct
- {
- __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
- __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
- __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
- * only when the L1RESPMD[1:0] value is 2'b11. */
- __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
- * the L1 state together with the device state bits DVSQ[2:0]. */
- __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
- * value used for L1NEGOMD.The format is the same as the HIRD
- * field in HL1CTRL. */
- uint16_t : 2;
- __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
- } PL1CTRL1_b;
- };
-
- union
- {
- __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
-
- struct
- {
- uint16_t : 8;
- __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
- __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
- } PL1CTRL2_b;
- };
-
- union
- {
- __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
-
- struct
- {
- __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
- __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
- } HL1CTRL1_b;
- };
-
- union
- {
- __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
-
- struct
- {
- __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
- * be set in the ADDR field of LPM token. */
- uint16_t : 4;
- __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
- __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
- * value to be set in the RWE field of LPM token. */
- uint16_t : 2;
- __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
- * period at the time of L1 Resume. */
- } HL1CTRL2_b;
- };
- __IM uint32_t RESERVED20;
-
- union
- {
- __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150)PHY Timing Register 1 */
-
- struct
- {
- __IOM uint16_t DRISE : 2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function */
- __IOM uint16_t DFALL : 2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function */
- uint16_t : 3;
- __IOM uint16_t PCOMPENB : 1; /*!< [7..7]PVDD Start-up Detection */
- __IOM uint16_t HSIUP : 4; /*!< [11..8]HS Output Level Setting */
- __IOM uint16_t IMPOFFSET : 3; /*!< [14..12]terminating resistance offset value setting.Offset value for
- * adjusting the terminating resistance. */
- } PHYTRIM1_b; /*!< BitSize */
- };
-
- union
- {
- __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152)PHY Timing Register 2 */
-
- struct
- {
- __IOM uint16_t SQU : 4; /*!< [3..0]Squelch Detection Level */
- uint16_t : 3;
- __IOM uint16_t HSRXENMO : 1; /*!< [7..7]HS Receive Enable Control Mode */
- __IOM uint16_t PDR : 2; /*!< [9..8]HS Output Adjustment Function */
- uint16_t : 2;
- __IOM uint16_t DIS : 3; /*!< [14..12]Disconnect Detection Level */
- } PHYTRIM2_b; /*!< BitSize */
- };
- __IM uint32_t RESERVED21[3];
-
- union
- {
- __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
- * Register */
-
- struct
- {
- uint32_t : 20;
- __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
- * HS side of USB port. */
- __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
- * HS side of USB port. */
- uint32_t : 1;
- __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
- * of USB port. */
- } DPUSR0R_b;
- };
-
- union
- {
- __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
-
- struct
- {
- uint32_t : 4;
- __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
- __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
- uint32_t : 1;
- __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
- uint32_t : 12;
- __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
- __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
- uint32_t : 1;
- __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
- } DPUSR1R_b;
- };
-
- union
- {
- __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
-
- struct
- {
- __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
- __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
- uint16_t : 2;
- __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
- * port. */
- __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
- * port. */
- uint16_t : 2;
- __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
- __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
- } DPUSR2R_b;
- };
-
- union
- {
- __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
-
- struct
- {
- __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
- __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
- } DPUSRCR_b;
- };
-} R_USB_HS0_Type; /*!< Size = 1032 (0x408) */
-
-/* =========================================================================================================================== */
-/* ================ R_WDT ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Watchdog Timer (R_WDT)
- */
-
-typedef struct /*!< (@ 0x40044200) R_WDT Structure */
-{
- union
- {
- __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */
-
- struct
- {
- __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
- * of the WDT. */
- } WDTRR_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */
-
- struct
- {
- __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */
- uint16_t : 2;
- __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */
- __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */
- uint16_t : 2;
- __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */
- uint16_t : 2;
- } WDTCR_b;
- };
-
- union
- {
- __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */
-
- struct
- {
- __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */
- __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
- __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
- } WDTSR_b;
- };
-
- union
- {
- __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */
- } WDTRCR_b;
- };
- __IM uint8_t RESERVED1;
-
- union
- {
- __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */
-
- struct
- {
- uint8_t : 7;
- __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */
- } WDTCSTPR_b;
- };
- __IM uint8_t RESERVED2;
- __IM uint16_t RESERVED3;
-} R_WDT_Type; /*!< Size = 12 (0xc) */
-
-/* =========================================================================================================================== */
-/* ================ R_TZF ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief TrustZone Filter (R_TZF)
- */
-
-typedef struct /*!< (@ 0x40000E00) R_TZF Structure */
-{
- union
- {
- __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */
-
- struct
- {
- __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */
- } TZFOAD_b;
- };
- __IM uint16_t RESERVED;
-
- union
- {
- __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */
-
- struct
- {
- __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
- uint16_t : 7;
- __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */
- } TZFPT_b;
- };
- __IM uint16_t RESERVED1;
- __IM uint32_t RESERVED2[94];
-
- union
- {
- __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */
-
- struct
- {
- __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */
- uint32_t : 31;
- } TZFSAR_b;
- };
-} R_TZF_Type; /*!< Size = 388 (0x184) */
-
-/* =========================================================================================================================== */
-/* ================ R_CACHE ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief R_CACHE (R_CACHE)
- */
-
-typedef struct /*!< (@ 0x40007000) R_CACHE Structure */
-{
- union
- {
- __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */
-
- struct
- {
- __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */
- uint32_t : 31;
- } CCACTL_b;
- };
-
- union
- {
- __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */
-
- struct
- {
- __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */
- uint32_t : 31;
- } CCAFCT_b;
- };
-
- union
- {
- __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */
-
- struct
- {
- __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */
- uint32_t : 30;
- } CCALCF_b;
- };
- __IM uint32_t RESERVED[13];
-
- union
- {
- __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */
-
- struct
- {
- __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */
- uint32_t : 31;
- } SCACTL_b;
- };
-
- union
- {
- __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */
-
- struct
- {
- __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */
- uint32_t : 31;
- } SCAFCT_b;
- };
-
- union
- {
- __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */
-
- struct
- {
- __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */
- uint32_t : 30;
- } SCALCF_b;
- };
- __IM uint32_t RESERVED1[109];
-
- union
- {
- __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
- * Register */
-
- struct
- {
- __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */
- uint32_t : 31;
- } CAPOAD_b;
- };
-
- union
- {
- __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */
-
- struct
- {
- __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */
- __IOM uint32_t KW : 7; /*!< [7..1] Write key code */
- uint32_t : 24;
- } CAPRCR_b;
- };
-} R_CACHE_Type; /*!< Size = 520 (0x208) */
-
-/* =========================================================================================================================== */
-/* ================ R_CPSCU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief CPU System Security Control Unit (R_CPSCU)
- */
-
-typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */
-{
- union
- {
- __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */
-
- struct
- {
- __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */
- __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */
- __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */
- uint32_t : 29;
- } CSAR_b;
- };
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */
-
- struct
- {
- __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */
- __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
- * 2 */
- __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */
- uint32_t : 29;
- } SRAMSAR_b;
- };
-
- union
- {
- __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */
-
- struct
- {
- __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */
- uint32_t : 28;
- } STBRAMSAR_b;
- };
- __IM uint32_t RESERVED1[6];
-
- union
- {
- __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */
-
- struct
- {
- __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */
- uint32_t : 31;
- } DTCSAR_b;
- };
-
- union
- {
- __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */
-
- struct
- {
- __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */
- uint32_t : 31;
- } DMACSAR_b;
- };
- __IM uint32_t RESERVED2[2];
-
- union
- {
- __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */
-
- struct
- {
- __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */
- uint32_t : 16;
- } ICUSARA_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */
-
- struct
- {
- __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */
- uint32_t : 31;
- } ICUSARB_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */
-
- struct
- {
- __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */
- uint32_t : 24;
- } ICUSARC_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */
-
- struct
- {
- __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */
- uint32_t : 31;
- } ICUSARD_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */
- uint32_t : 1;
- __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */
- __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */
- uint32_t : 4;
- __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */
- __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */
- uint32_t : 1;
- __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */
- __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */
- __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */
- __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */
- __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */
- } ICUSARE_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */
-
- struct
- {
- __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */
- __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */
- __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */
- uint32_t : 29;
- } ICUSARF_b;
- };
- __IM uint32_t RESERVED3[6];
-
- union
- {
- __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */
-
- struct
- {
- __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */
- } ICUSARG_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */
-
- struct
- {
- __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */
- } ICUSARH_b;
- };
-
- union
- {
- __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */
-
- struct
- {
- __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */
- } ICUSARI_b;
- };
- __IM uint32_t RESERVED4[33];
-
- union
- {
- __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */
-
- struct
- {
- __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */
- uint32_t : 31;
- } BUSSARA_b;
- };
-
- union
- {
- __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */
-
- struct
- {
- __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */
- uint32_t : 31;
- } BUSSARB_b;
- };
- __IM uint32_t RESERVED5[10];
-
- union
- {
- __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
- * Register A */
-
- struct
- {
- __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */
- uint32_t : 24;
- } MMPUSARA_b;
- };
-
- union
- {
- __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
- * Register B */
-
- struct
- {
- __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */
- uint32_t : 31;
- } MMPUSARB_b;
- };
- __IM uint32_t RESERVED6[30];
-
- union
- {
- __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */
-
- struct
- {
- __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */
- uint32_t : 31;
- } CPUDSAR_b;
- };
-} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */
-
-/* =========================================================================================================================== */
-/* ================ R_CEC ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Consumer Electronics Control (R_CEC)
- */
-
-typedef struct /*!< (@ 0x400AC000) R_CEC Structure */
-{
- union
- {
- __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */
-
- struct
- {
- __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */
- __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device
- * 1) */
- __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device
- * 2) */
- __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */
- __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */
- __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */
- __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */
- __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */
- __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */
- __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device
- * 3) */
- __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */
- __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device
- * 3) */
- __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */
- __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */
- __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */
- uint16_t : 1;
- } CADR_b;
- };
-
- union
- {
- __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */
-
- struct
- {
- __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */
- __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
- * Select */
- __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */
- __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */
- __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */
- __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */
- } CECCTL1_b;
- };
- __IM uint8_t RESERVED;
-
- union
- {
- __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */
-
- struct
- {
- __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */
- uint16_t : 7;
- } STATB_b;
- };
-
- union
- {
- __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */
- uint16_t : 7;
- } STATL_b;
- };
-
- union
- {
- __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */
- uint16_t : 7;
- } LGC0L_b;
- };
-
- union
- {
- __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */
- uint16_t : 7;
- } LGC1L_b;
- };
-
- union
- {
- __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */
-
- struct
- {
- __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */
- uint16_t : 7;
- } DATB_b;
- };
-
- union
- {
- __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */
-
- struct
- {
- __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */
- uint16_t : 7;
- } NOMT_b;
- };
-
- union
- {
- __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */
- uint16_t : 7;
- } STATLL_b;
- };
-
- union
- {
- __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */
- uint16_t : 7;
- } STATLH_b;
- };
-
- union
- {
- __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */
- uint16_t : 7;
- } STATBL_b;
- };
-
- union
- {
- __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */
- uint16_t : 7;
- } STATBH_b;
- };
-
- union
- {
- __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */
- uint16_t : 7;
- } LGC0LL_b;
- };
-
- union
- {
- __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */
- uint16_t : 7;
- } LGC0LH_b;
- };
-
- union
- {
- __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */
- uint16_t : 7;
- } LGC1LL_b;
- };
-
- union
- {
- __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */
- uint16_t : 7;
- } LGC1LH_b;
- };
-
- union
- {
- __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */
- uint16_t : 7;
- } DATBL_b;
- };
-
- union
- {
- __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
- * Register */
-
- struct
- {
- __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */
- uint16_t : 7;
- } DATBH_b;
- };
-
- union
- {
- __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */
-
- struct
- {
- __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */
- uint16_t : 7;
- } NOMP_b;
- };
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */
-
- struct
- {
- uint8_t : 4;
- __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */
- __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */
- uint8_t : 1;
- __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */
- } CECEXMD_b;
- };
- __IM uint8_t RESERVED2;
-
- union
- {
- __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */
-
- struct
- {
- __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */
- __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */
- uint8_t : 6;
- } CECEXMON_b;
- };
- __IM uint8_t RESERVED3;
- __IM uint16_t RESERVED4[10];
- __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */
- __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */
-
- union
- {
- __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */
-
- struct
- {
- __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */
- __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */
- __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */
- __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */
- __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */
- __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */
- __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */
- uint8_t : 1;
- } CECES_b;
- };
-
- union
- {
- __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */
-
- struct
- {
- __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */
- __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */
- __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */
- __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */
- __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */
- uint8_t : 2;
- __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */
- } CECS_b;
- };
-
- union
- {
- __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */
-
- struct
- {
- __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */
- __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */
- __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */
- __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */
- __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */
- __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */
- __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */
- uint8_t : 1;
- } CECFC_b;
- };
-
- union
- {
- __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */
-
- struct
- {
- __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */
- __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */
- __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */
- __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */
- __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */
- __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */
- } CECCTL0_b;
- };
-} R_CEC_Type; /*!< Size = 70 (0x46) */
-
-/* =========================================================================================================================== */
-/* ================ R_OSPI ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Octa Serial Peripheral Interface (R_OSPI)
- */
-
-typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */
-{
- union
- {
- __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */
-
- struct
- {
- __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */
- __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */
- uint32_t : 16;
- } DCR_b;
- };
-
- union
- {
- __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */
-
- struct
- {
- __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */
- __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */
- __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */
- __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */
- } DAR_b;
- };
-
- union
- {
- __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */
-
- struct
- {
- __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */
- __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */
- uint32_t : 3;
- __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */
- __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */
- __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */
- __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */
- __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */
- __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */
- __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */
- uint32_t : 2;
- } DCSR_b;
- };
-
- union
- {
- __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */
-
- struct
- {
- __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */
- __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */
- } DSR_b[2];
- };
-
- union
- {
- __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */
-
- struct
- {
- __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */
- __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */
- __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */
- __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */
- __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */
- uint32_t : 4;
- } MDTR_b;
- };
-
- union
- {
- __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */
-
- struct
- {
- __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */
- } ACTR_b;
- };
-
- union
- {
- __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */
-
- struct
- {
- __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */
- } ACAR_b[2];
- };
- __IM uint32_t RESERVED[4];
-
- union
- {
- __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting
- * Register */
-
- struct
- {
- __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting
- * in PCLKH units */
- __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */
- __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */
- __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */
- __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */
- __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting
- * in PCLKH units */
- __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */
- __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */
- __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */
- __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */
- } DRCSTR_b;
- };
-
- union
- {
- __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting
- * Register */
-
- struct
- {
- __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting
- * in PCLKH units */
- __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */
- __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */
- __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */
- __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */
- __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting
- * in PCLKH units */
- __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */
- __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */
- __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */
- __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */
- } DWCSTR_b;
- };
-
- union
- {
- __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */
-
- struct
- {
- uint32_t : 8;
- __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */
- __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */
- __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */
- uint32_t : 16;
- } DCSTR_b;
- };
-
- union
- {
- __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */
-
- struct
- {
- __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */
- __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */
- __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */
- __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */
- uint32_t : 4;
- __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device
- * 0 */
- __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device
- * 1 */
- __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */
- uint32_t : 17;
- __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */
- } CDSR_b;
- };
-
- union
- {
- __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */
-
- struct
- {
- __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */
- __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */
- __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */
- __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */
- } MDLR_b;
- };
-
- union
- {
- __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */
-
- struct
- {
- __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */
- __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */
- __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */
- __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */
- } MRWCR_b[2];
- };
-
- union
- {
- __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */
-
- struct
- {
- __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */
- __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */
- __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */
- __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */
- __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */
- __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */
- __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */
- uint32_t : 1;
- __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */
- __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */
- __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */
- __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */
- __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */
- __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */
- __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */
- uint32_t : 1;
- } MRWCSR_b;
- };
-
- union
- {
- __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */
-
- struct
- {
- __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */
- __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */
- uint32_t : 16;
- } ESR_b;
- };
-
- union
- {
- __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */
-
- struct
- {
- __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */
- } CWNDR_b;
- };
-
- union
- {
- __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */
-
- struct
- {
- __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */
- __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */
- __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */
- __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */
- } CWDR_b;
- };
-
- union
- {
- __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */
-
- struct
- {
- __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */
- __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */
- __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */
- __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */
- } CRR_b;
- };
-
- union
- {
- __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */
-
- struct
- {
- __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */
- __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */
- uint32_t : 26;
- } ACSR_b;
- };
- __IM uint32_t RESERVED1[5];
-
- union
- {
- __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */
-
- struct
- {
- __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are
- * Low in single continuous write of OctaRAM. */
- uint32_t : 7;
- __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1
- * are Low in single continuous read of OctaRAM. */
- uint32_t : 7;
- } DCSMXR_b;
- };
-
- union
- {
- __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating
- * size Register */
-
- struct
- {
- __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single
- * continuous write of device 0. */
- uint32_t : 5;
- __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single
- * continuous write of device 1. */
- uint32_t : 5;
- } DWSCTSR_b;
- };
-} R_OSPI_Type; /*!< Size = 132 (0x84) */
-
-/* =========================================================================================================================== */
-/* ================ R_ADC_B0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief 12-bit A/D Converter (R_ADC_B0)
- */
-
-typedef struct /*!< (@ 0x40170000) R_ADC_B0 Structure */
-{
- union
- {
- __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */
-
- struct
- {
- __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */
- uint32_t : 31;
- } ADCLKENR_b;
- };
-
- union
- {
- __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */
-
- struct
- {
- __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */
- uint32_t : 31;
- } ADCLKSR_b;
- };
-
- union
- {
- __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */
-
- struct
- {
- __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */
- uint32_t : 14;
- __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */
- uint32_t : 13;
- } ADCLKCR_b;
- };
-
- union
- {
- __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */
-
- struct
- {
- __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */
- uint32_t : 5;
- __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */
- __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */
- uint32_t : 14;
- } ADSYCR_b;
- };
- __IM uint32_t RESERVED[4];
-
- union
- {
- __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */
- __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */
- uint32_t : 30;
- } ADERINTCR_b;
- };
-
- union
- {
- __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */
- __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */
- uint32_t : 30;
- } ADOVFINTCR_b;
- };
-
- union
- {
- __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */
- __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */
- uint32_t : 14;
- } ADCALINTCR_b;
- };
- __IM uint32_t RESERVED1[5];
-
- union
- {
- __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */
-
- struct
- {
- __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */
- uint32_t : 4;
- __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */
- uint32_t : 20;
- } ADMDR_b;
- };
-
- union
- {
- __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */
-
- struct
- {
- __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */
- __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */
- __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */
- __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */
- uint32_t : 4;
- __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */
- __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */
- __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */
- __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */
- uint32_t : 20;
- } ADGSPCR_b;
- };
-
- union
- {
- __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */
-
- struct
- {
- __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */
- uint32_t : 23;
- } ADSGER_b;
- };
-
- union
- {
- __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */
-
- struct
- {
- __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */
- uint32_t : 6;
- } ADSGCR0_b;
- };
-
- union
- {
- __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */
-
- struct
- {
- __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */
- uint32_t : 6;
- __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */
- uint32_t : 6;
- } ADSGCR1_b;
- };
-
- union
- {
- __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */
-
- struct
- {
- __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */
- uint32_t : 30;
- } ADSGCR2_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t ADIEn : 10; /*!< [9..0] Scan Group n Scan End Interrupt Enable */
- uint32_t : 22;
- } ADINTCR_b;
- };
- __IM uint32_t RESERVED3[24];
-
- union
- {
- __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT0_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC0_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT0_b;
- };
- __IM uint32_t RESERVED4;
-
- union
- {
- __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT1_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC1_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT1_b;
- };
- __IM uint32_t RESERVED5;
-
- union
- {
- __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT2_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC2_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT2_b;
- };
- __IM uint32_t RESERVED6;
-
- union
- {
- __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT3_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC3_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT3_b;
- };
- __IM uint32_t RESERVED7;
-
- union
- {
- __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT4_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC4_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT4_b;
- };
- __IM uint32_t RESERVED8;
-
- union
- {
- __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT5_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC5_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT5_b;
- };
- __IM uint32_t RESERVED9;
-
- union
- {
- __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT6_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC6_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT6_b;
- };
- __IM uint32_t RESERVED10;
-
- union
- {
- __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT7_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC7_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT7_b;
- };
- __IM uint32_t RESERVED11;
-
- union
- {
- __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */
-
- struct
- {
- __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
- __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
- uint32_t : 30;
- } ADTRGEXT8_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */
-
- struct
- {
- __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
- uint32_t : 26;
- } ADTRGELC8_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */
-
- struct
- {
- __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
- uint32_t : 6;
- __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
- uint32_t : 6;
- } ADTRGGPT8_b;
- };
- __IM uint32_t RESERVED12[29];
-
- union
- {
- __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */
-
- struct
- {
- __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */
- uint32_t : 8;
- __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */
- uint32_t : 8;
- } ADTRGDLR0_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */
-
- struct
- {
- __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */
- uint32_t : 8;
- __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */
- uint32_t : 8;
- } ADTRGDLR1_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */
-
- struct
- {
- __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */
- uint32_t : 8;
- __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */
- uint32_t : 8;
- } ADTRGDLR2_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */
-
- struct
- {
- __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */
- uint32_t : 8;
- __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */
- uint32_t : 8;
- } ADTRGDLR3_b;
- };
-
- union
- {
- __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */
-
- struct
- {
- __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */
- uint32_t : 24;
- } ADTRGDLR4_b;
- };
- __IM uint32_t RESERVED13[11];
-
- union
- {
- __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register
- * 0 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR0_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register
- * 1 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR1_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register
- * 2 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR2_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register
- * 3 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR3_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register
- * 4 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR4_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register
- * 5 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR5_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register
- * 6 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR6_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register
- * 7 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR7_b;
- };
-
- union
- {
- __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register
- * 8 */
-
- struct
- {
- __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
- uint32_t : 13;
- __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
- uint32_t : 3;
- __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
- __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
- uint32_t : 2;
- __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
- uint32_t : 4;
- } ADSGDCR8_b;
- };
- __IM uint32_t RESERVED14[7];
-
- union
- {
- __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */
-
- struct
- {
- __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */
- uint32_t : 6;
- __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */
- uint32_t : 6;
- } ADSSTR0_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */
-
- struct
- {
- __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */
- uint32_t : 6;
- __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */
- uint32_t : 6;
- } ADSSTR1_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */
-
- struct
- {
- __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */
- uint32_t : 6;
- __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */
- uint32_t : 6;
- } ADSSTR2_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */
-
- struct
- {
- __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */
- uint32_t : 6;
- __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */
- uint32_t : 6;
- } ADSSTR3_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */
-
- struct
- {
- __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */
- uint32_t : 6;
- __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */
- uint32_t : 6;
- } ADSSTR4_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */
-
- struct
- {
- __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */
- uint32_t : 6;
- __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */
- uint32_t : 6;
- } ADSSTR5_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */
-
- struct
- {
- __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */
- uint32_t : 6;
- __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */
- uint32_t : 6;
- } ADSSTR6_b;
- };
-
- union
- {
- __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */
-
- struct
- {
- __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */
- uint32_t : 6;
- __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */
- uint32_t : 6;
- } ADSSTR7_b;
- };
-
- union
- {
- __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */
-
- struct
- {
- __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */
- uint32_t : 2;
- __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */
- uint32_t : 18;
- } ADCNVSTR_b;
- };
-
- union
- {
- __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */
-
- struct
- {
- __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */
- uint32_t : 6;
- __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */
- uint32_t : 10;
- } ADCALSTCR_b;
- };
- __IM uint32_t RESERVED15[6];
-
- union
- {
- __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control
- * Register 0 */
-
- struct
- {
- __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */
- __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */
- __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */
- uint32_t : 29;
- } ADSHCR0_b;
- };
- __IM uint32_t RESERVED16;
-
- union
- {
- __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State
- * Register 0 */
-
- struct
- {
- __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */
- uint32_t : 8;
- __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to
- * 2 */
- uint32_t : 13;
- } ADSHSTR0_b;
- };
-
- union
- {
- __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control
- * Register 1 */
-
- struct
- {
- __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */
- __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */
- __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */
- uint32_t : 29;
- } ADSHCR1_b;
- };
- __IM uint32_t RESERVED17;
-
- union
- {
- __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State
- * Register 1 */
-
- struct
- {
- __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */
- uint32_t : 8;
- __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to
- * 6 */
- uint32_t : 13;
- } ADSHSTR1_b;
- };
- __IM uint32_t RESERVED18[6];
-
- union
- {
- __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration
- * State Register */
-
- struct
- {
- __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling
- * Time Configuration */
- uint32_t : 8;
- __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration
- * Holding Time Configuration */
- uint32_t : 13;
- } ADCALSHCR_b;
- };
- __IM uint32_t RESERVED19[3];
-
- union
- {
- __IOM uint32_t ADPGACR[4]; /*!< (@ 0x000002C0) Programmable Gain Amplifier Control Register
- * [0..3] */
-
- struct
- {
- uint32_t : 1;
- __IOM uint32_t PGADEN : 1; /*!< [1..1] PGA Unit n Input Mode Select */
- __IOM uint32_t PGASEL1 : 1; /*!< [2..2] PGA Unit n Transit Enable */
- __IOM uint32_t PGAENAMP : 1; /*!< [3..3] PGA Unit n Enable */
- uint32_t : 12;
- __IOM uint32_t PGAGEN : 1; /*!< [16..16] PGA Unit n Gain Setting Enable */
- uint32_t : 3;
- __IOM uint32_t PGADG : 2; /*!< [21..20] PGA Unit n Differential Input Gain Setting */
- uint32_t : 2;
- __IOM uint32_t PGAGAIN : 4; /*!< [27..24] PGA Unit n Gain Setting */
- uint32_t : 4;
- } ADPGACR_b[4];
- };
- __IM uint32_t RESERVED20[12];
-
- union
- {
- __IOM uint32_t ADPGAMONCR; /*!< (@ 0x00000300) Programable Gain Amp Monitor Output Control Register */
-
- struct
- {
- __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Signal Selection */
- uint32_t : 13;
- __IOM uint32_t MONSEL0 : 1; /*!< [16..16] PGA Unit 0 Monitor Output Enable */
- __IOM uint32_t MONSEL1 : 1; /*!< [17..17] PGA Unit 1 Monitor Output Enable */
- __IOM uint32_t MONSEL2 : 1; /*!< [18..18] PGA Unit 2 Monitor Output Enable */
- __IOM uint32_t MONSEL3 : 1; /*!< [19..19] PGA Unit 3 Monitor Output Enable */
- uint32_t : 12;
- } ADPGAMONCR_b;
- };
- __IM uint32_t RESERVED21[7];
-
- union
- {
- __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */
-
- struct
- {
- __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */
- uint32_t : 31;
- } ADREFCR_b;
- };
- __IM uint32_t RESERVED22[15];
-
- union
- {
- __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR0_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR1_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR2_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR3_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR4_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR5_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR6_b;
- };
-
- union
- {
- __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */
-
- struct
- {
- __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
- uint32_t : 16;
- } ADUOFTR7_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR0_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR1_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR2_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR3_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR4_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR5_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR6_b;
- };
-
- union
- {
- __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */
-
- struct
- {
- __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
- uint32_t : 8;
- } ADUGTR7_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */
- uint32_t : 23;
- } ADLIMINTCR_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR0_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR1_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR2_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR3_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR4_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR5_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR6_b;
- };
-
- union
- {
- __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */
-
- struct
- {
- __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
- __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
- } ADLIMTR7_b;
- };
- __IM uint32_t RESERVED23[15];
-
- union
- {
- __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */
-
- struct
- {
- __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */
- uint32_t : 24;
- } ADCMPENR_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */
-
- struct
- {
- __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */
- uint32_t : 28;
- } ADCMPINTCR_b;
- };
-
- union
- {
- __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register
- * 0 */
-
- struct
- {
- __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */
- uint32_t : 14;
- __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */
- uint32_t : 8;
- } ADCCMPCR0_b;
- };
-
- union
- {
- __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register
- * 1 */
-
- struct
- {
- __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */
- uint32_t : 14;
- __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */
- uint32_t : 8;
- } ADCCMPCR1_b;
- };
- __IM uint32_t RESERVED24[14];
-
- union
- {
- __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */
-
- struct
- {
- __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */
- uint32_t : 6;
- } ADCMPMDR0_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */
-
- struct
- {
- __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */
- uint32_t : 6;
- __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */
- uint32_t : 6;
- } ADCMPMDR1_b;
- };
- __IM uint32_t RESERVED25[2];
-
- union
- {
- __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR0_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR1_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR2_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR3_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR4_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR5_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR6_b;
- };
-
- union
- {
- __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */
-
- struct
- {
- __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
- __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
- } ADCMPTBR7_b;
- };
- __IM uint32_t RESERVED26[18];
-
- union
- {
- __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */
-
- struct
- {
- __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */
- __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */
- __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */
- __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */
- __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */
- __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */
- __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */
- __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */
- __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */
- uint32_t : 23;
- } ADFIFOCR_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */
-
- struct
- {
- __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */
- __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */
- uint32_t : 23;
- } ADFIFOINTCR_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */
-
- struct
- {
- __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- } ADFIFOINTLR0_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */
-
- struct
- {
- __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- } ADFIFOINTLR1_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */
-
- struct
- {
- __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- } ADFIFOINTLR2_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */
-
- struct
- {
- __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */
- uint32_t : 12;
- } ADFIFOINTLR3_b;
- };
-
- union
- {
- __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */
-
- struct
- {
- __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */
- uint32_t : 28;
- } ADFIFOINTLR4_b;
- };
- __IM uint32_t RESERVED27[73];
-
- union
- {
- __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register
- * 0 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR0_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register
- * 0 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA0_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register
- * 0 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB0_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register
- * 0 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC0_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register
- * 1 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR1_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register
- * 1 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA1_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register
- * 1 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB1_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register
- * 1 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC1_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register
- * 2 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR2_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register
- * 2 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA2_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register
- * 2 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB2_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register
- * 2 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC2_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register
- * 3 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR3_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register
- * 3 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA3_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register
- * 3 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB3_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register
- * 3 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC3_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register
- * 4 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR4_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register
- * 4 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA4_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register
- * 4 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB4_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register
- * 4 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC4_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register
- * 5 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR5_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register
- * 5 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA5_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register
- * 5 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB5_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register
- * 5 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC5_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register
- * 6 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR6_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register
- * 6 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA6_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register
- * 6 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB6_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register
- * 6 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC6_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register
- * 7 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR7_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register
- * 7 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA7_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register
- * 7 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB7_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register
- * 7 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC7_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register
- * 8 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR8_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register
- * 8 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA8_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register
- * 8 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB8_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register
- * 8 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC8_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register
- * 9 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR9_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register
- * 9 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA9_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register
- * 9 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB9_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register
- * 9 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC9_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register
- * 10 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR10_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register
- * 10 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA10_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register
- * 10 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB10_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register
- * 10 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC10_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register
- * 11 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR11_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register
- * 11 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA11_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register
- * 11 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB11_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register
- * 11 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC11_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register
- * 12 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR12_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register
- * 12 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA12_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register
- * 12 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB12_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register
- * 12 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC12_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register
- * 13 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR13_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register
- * 13 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA13_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register
- * 13 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB13_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register
- * 13 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC13_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register
- * 14 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR14_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register
- * 14 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA14_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register
- * 14 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB14_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register
- * 14 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC14_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register
- * 15 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR15_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register
- * 15 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA15_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register
- * 15 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB15_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register
- * 15 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC15_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register
- * 16 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR16_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register
- * 16 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA16_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register
- * 16 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB16_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register
- * 16 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC16_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register
- * 17 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR17_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register
- * 17 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA17_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register
- * 17 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB17_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register
- * 17 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC17_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register
- * 18 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR18_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register
- * 18 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA18_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register
- * 18 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB18_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register
- * 18 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC18_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register
- * 19 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR19_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register
- * 19 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA19_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register
- * 19 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB19_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register
- * 19 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC19_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register
- * 20 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR20_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register
- * 20 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA20_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register
- * 20 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB20_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register
- * 20 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC20_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register
- * 21 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR21_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register
- * 21 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA21_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register
- * 21 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB21_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register
- * 21 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC21_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register
- * 22 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR22_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register
- * 22 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA22_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register
- * 22 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB22_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register
- * 22 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC22_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register
- * 23 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR23_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register
- * 23 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA23_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register
- * 23 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB23_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register
- * 23 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC23_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register
- * 24 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR24_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register
- * 24 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA24_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register
- * 24 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB24_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register
- * 24 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC24_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register
- * 25 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR25_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register
- * 25 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA25_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register
- * 25 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB25_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register
- * 25 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC25_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register
- * 26 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR26_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register
- * 26 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA26_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register
- * 26 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB26_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register
- * 26 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC26_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register
- * 27 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR27_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register
- * 27 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA27_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register
- * 27 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB27_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register
- * 27 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC27_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register
- * 28 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR28_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register
- * 28 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA28_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register
- * 28 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB28_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register
- * 28 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC28_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register
- * 29 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR29_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register
- * 29 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA29_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register
- * 29 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB29_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register
- * 29 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC29_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register
- * 30 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR30_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register
- * 30 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA30_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register
- * 30 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB30_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register
- * 30 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC30_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register
- * 31 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR31_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register
- * 31 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA31_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register
- * 31 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB31_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register
- * 31 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC31_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register
- * 32 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR32_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register
- * 32 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA32_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register
- * 32 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB32_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register
- * 32 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC32_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR33; /*!< (@ 0x00000810) A/D Conversion Channel Configuration Register
- * 33 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR33_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA33; /*!< (@ 0x00000814) A/D Conversion Data Operation Control A Register
- * 33 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA33_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB33; /*!< (@ 0x00000818) A/D Conversion Data Operation Control B Register
- * 33 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB33_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC33; /*!< (@ 0x0000081C) A/D Conversion Data Operation Control C Register
- * 33 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC33_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR34; /*!< (@ 0x00000820) A/D Conversion Channel Configuration Register
- * 34 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR34_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA34; /*!< (@ 0x00000824) A/D Conversion Data Operation Control A Register
- * 34 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA34_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB34; /*!< (@ 0x00000828) A/D Conversion Data Operation Control B Register
- * 34 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB34_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC34; /*!< (@ 0x0000082C) A/D Conversion Data Operation Control C Register
- * 34 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC34_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR35; /*!< (@ 0x00000830) A/D Conversion Channel Configuration Register
- * 35 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR35_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA35; /*!< (@ 0x00000834) A/D Conversion Data Operation Control A Register
- * 35 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA35_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB35; /*!< (@ 0x00000838) A/D Conversion Data Operation Control B Register
- * 35 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB35_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC35; /*!< (@ 0x0000083C) A/D Conversion Data Operation Control C Register
- * 35 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC35_b;
- };
-
- union
- {
- __IOM uint32_t ADCHCR36; /*!< (@ 0x00000840) A/D Conversion Channel Configuration Register
- * 36 */
-
- struct
- {
- __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
- uint32_t : 3;
- __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
- __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
- __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
- uint32_t : 12;
- } ADCHCR36_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRA36; /*!< (@ 0x00000844) A/D Conversion Data Operation Control A Register
- * 36 */
-
- struct
- {
- uint32_t : 16;
- __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
- uint32_t : 4;
- __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
- uint32_t : 4;
- } ADDOPCRA36_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRB36; /*!< (@ 0x00000848) A/D Conversion Data Operation Control B Register
- * 36 */
-
- struct
- {
- __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
- uint32_t : 6;
- __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
- uint32_t : 4;
- __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
- uint32_t : 8;
- } ADDOPCRB36_b;
- };
-
- union
- {
- __IOM uint32_t ADDOPCRC36; /*!< (@ 0x0000084C) A/D Conversion Data Operation Control C Register
- * 36 */
-
- struct
- {
- __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
- uint32_t : 12;
- __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
- uint32_t : 2;
- __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
- uint32_t : 11;
- } ADDOPCRC36_b;
- };
- __IM uint32_t RESERVED28[236];
-
- union
- {
- __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */
-
- struct
- {
- __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control
- * bits */
- uint32_t : 5;
- __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control
- * bits */
- uint32_t : 21;
- } ADCALSTR_b;
- };
- __IM uint32_t RESERVED29;
-
- union
- {
- __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */
-
- struct
- {
- __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */
- uint32_t : 23;
- } ADTRGENR_b;
- };
- __IM uint32_t RESERVED30;
-
- union
- {
- __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */
-
- struct
- {
- __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */
- uint32_t : 23;
- } ADSYSTR_b;
- };
- __IM uint32_t RESERVED31[3];
-
- union
- {
- __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */
-
- struct
- {
- __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */
- uint32_t : 31;
- } ADSTR_b[9];
- };
- __IM uint32_t RESERVED32[7];
-
- union
- {
- __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */
-
- struct
- {
- __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */
- uint32_t : 7;
- __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */
- uint32_t : 23;
- } ADSTOPR_b;
- };
- __IM uint32_t RESERVED33[7];
-
- union
- {
- __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */
-
- struct
- {
- __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */
- __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */
- uint32_t : 14;
- __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */
- __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */
- uint32_t : 14;
- } ADSR_b;
- };
-
- union
- {
- __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */
-
- struct
- {
- __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */
- uint32_t : 23;
- } ADGRSR_b;
- };
-
- union
- {
- __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */
-
- struct
- {
- __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */
- __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */
- uint32_t : 30;
- } ADERSR_b;
- };
-
- union
- {
- __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */
-
- struct
- {
- __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */
- __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */
- uint32_t : 30;
- } ADERSCR_b;
- };
- __IM uint32_t RESERVED34[2];
-
- union
- {
- __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */
-
- struct
- {
- __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */
- __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */
- uint32_t : 30;
- } ADCALENDSR_b;
- };
-
- union
- {
- __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */
-
- struct
- {
- __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */
- __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */
- uint32_t : 30;
- } ADCALENDSCR_b;
- };
-
- union
- {
- __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */
-
- struct
- {
- __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */
- __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */
- uint32_t : 30;
- } ADOVFERSR_b;
- };
-
- union
- {
- __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register
- * 0 */
-
- struct
- {
- __IM uint32_t OFVCHFn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag */
- uint32_t : 3;
- } ADOVFCHSR0_b;
- };
- __IM uint32_t RESERVED35[2];
-
- union
- {
- __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status
- * Register */
-
- struct
- {
- __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag bit */
- __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag bit */
- __IM uint32_t OVFEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag bit */
- uint32_t : 2;
- __IM uint32_t OVFEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag bit */
- __IM uint32_t OVFEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag bit */
- __IM uint32_t OVFEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag bit */
- __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag bit */
- uint32_t : 23;
- } ADOVFEXSR_b;
- };
-
- union
- {
- __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */
-
- struct
- {
- __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */
- __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */
- uint32_t : 30;
- } ADOVFERSCR_b;
- };
-
- union
- {
- __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear
- * Register 0 */
-
- struct
- {
- __OM uint32_t OVFCHCn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag Clear */
- uint32_t : 3;
- } ADOVFCHSCR0_b;
- };
- __IM uint32_t RESERVED36[2];
-
- union
- {
- __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status
- * Clear Register */
-
- struct
- {
- __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag Clear */
- __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag Clear */
- __OM uint32_t OVFEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag Clear */
- uint32_t : 2;
- __OM uint32_t OVFEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag Clear */
- __OM uint32_t OVFEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag Clear */
- __OM uint32_t OVFEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag Clear */
- __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag Clear */
- uint32_t : 23;
- } ADOVFEXSCR_b;
- };
- __IM uint32_t RESERVED37[2];
-
- union
- {
- __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */
-
- struct
- {
- __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */
- uint32_t : 12;
- __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */
- uint32_t : 12;
- } ADFIFOSR0_b;
- };
-
- union
- {
- __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */
-
- struct
- {
- __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */
- uint32_t : 12;
- __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */
- uint32_t : 12;
- } ADFIFOSR1_b;
- };
-
- union
- {
- __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */
-
- struct
- {
- __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */
- uint32_t : 12;
- __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */
- uint32_t : 12;
- } ADFIFOSR2_b;
- };
-
- union
- {
- __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */
-
- struct
- {
- __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */
- uint32_t : 12;
- __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */
- uint32_t : 12;
- } ADFIFOSR3_b;
- };
-
- union
- {
- __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */
-
- struct
- {
- __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */
- uint32_t : 28;
- } ADFIFOSR4_b;
- };
- __IM uint32_t RESERVED38[3];
-
- union
- {
- __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */
-
- struct
- {
- __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */
- uint32_t : 23;
- } ADFIFODCR_b;
- };
-
- union
- {
- __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */
-
- struct
- {
- __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */
- uint32_t : 7;
- __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */
- uint32_t : 7;
- } ADFIFOERSR_b;
- };
-
- union
- {
- __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */
-
- struct
- {
- __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */
- uint32_t : 7;
- __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */
- uint32_t : 7;
- } ADFIFOERSCR_b;
- };
- __IM uint32_t RESERVED39;
-
- union
- {
- __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */
-
- struct
- {
- __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */
- uint32_t : 24;
- } ADCMPTBSR_b;
- };
-
- union
- {
- __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */
-
- struct
- {
- __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */
- uint32_t : 24;
- } ADCMPTBSCR_b;
- };
-
- union
- {
- __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */
-
- struct
- {
- __IM uint32_t CMPCHFn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag */
- uint32_t : 3;
- } ADCMPCHSR0_b;
- };
- __IM uint32_t RESERVED40[2];
-
- union
- {
- __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */
-
- struct
- {
- __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag */
- __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag */
- __IM uint32_t CMPEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag */
- uint32_t : 2;
- __IM uint32_t CMPEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag */
- __IM uint32_t CMPEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag */
- __IM uint32_t CMPEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag */
- __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag */
- uint32_t : 23;
- } ADCMPEXSR_b;
- };
-
- union
- {
- __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */
-
- struct
- {
- __OM uint32_t CMPCHCn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag Clear bit */
- uint32_t : 3;
- } ADCMPCHSCR0_b;
- };
- __IM uint32_t RESERVED41[2];
-
- union
- {
- __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */
-
- struct
- {
- __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag Clear bit */
- __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag Clear
- * bit */
- __OM uint32_t CMPEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag
- * Clear bit */
- uint32_t : 2;
- __OM uint32_t CMPEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag Clear bit */
- __OM uint32_t CMPEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag Clear bit */
- __OM uint32_t CMPEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag Clear bit */
- __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag Clear bit */
- uint32_t : 23;
- } ADCMPEXSCR_b;
- };
-
- union
- {
- __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */
-
- struct
- {
- __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */
- uint32_t : 23;
- } ADLIMGRSR_b;
- };
-
- union
- {
- __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */
-
- struct
- {
- __IM uint32_t LIMCHFn : 29; /*!< [28..0] Analog Channel No. n : Limiter Clip Flag bit */
- uint32_t : 3;
- } ADLIMCHSR0_b;
- };
- __IM uint32_t RESERVED42[2];
-
- union
- {
- __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */
-
- struct
- {
- __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag bit */
- __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag bit */
- __IM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
- * bit */
- uint32_t : 2;
- __IM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag bit */
- __IM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag bit */
- __IM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag bit */
- __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag bit */
- uint32_t : 23;
- } ADLIMEXSR_b;
- };
-
- union
- {
- __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */
-
- struct
- {
- __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */
- uint32_t : 23;
- } ADLIMGRSCR_b;
- };
-
- union
- {
- __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */
-
- struct
- {
- __OM uint32_t LIMCHCn : 29; /*!< [28..0] Analog Channel No. n Limiter Clip Flag Clear bit */
- uint32_t : 3;
- } ADLIMCHSCR0_b;
- };
- __IM uint32_t RESERVED43[2];
-
- union
- {
- __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */
-
- struct
- {
- __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag Clear */
- __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag Clear */
- __OM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
- * Clear */
- uint32_t : 2;
- __OM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag Clear */
- __OM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag Clear */
- __OM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag Clear */
- __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag Clear */
- uint32_t : 23;
- } ADLIMEXSCR_b;
- };
-
- union
- {
- __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */
-
- struct
- {
- __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */
- uint32_t : 23;
- } ADSCANENDSR_b;
- };
-
- union
- {
- __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */
-
- struct
- {
- __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */
- uint32_t : 23;
- } ADSCANENDSCR_b;
- };
- __IM uint32_t RESERVED44[170];
-
- union
- {
- __IM uint32_t ADDR[29]; /*!< (@ 0x00001000) A/D Data Register [0..28] */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */
- uint32_t : 15;
- __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */
- } ADDR_b[29];
- };
- __IM uint32_t RESERVED45[67];
-
- union
- {
- __IM uint32_t ADEXDR[9]; /*!< (@ 0x00001180) A/D Extended Analog Data Register [0..8] */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */
- uint32_t : 8;
- __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */
- uint32_t : 4;
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */
- } ADEXDR_b[9];
- };
- __IM uint32_t RESERVED46[23];
-
- union
- {
- __IM uint32_t ADFIFODR0; /*!< (@ 0x00001200) FIFO Data Register 0 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR0_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR1; /*!< (@ 0x00001204) FIFO Data Register 1 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR1_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR2; /*!< (@ 0x00001208) FIFO Data Register 2 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR2_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR3; /*!< (@ 0x0000120C) FIFO Data Register 3 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR3_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR4; /*!< (@ 0x00001210) FIFO Data Register 4 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR4_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR5; /*!< (@ 0x00001214) FIFO Data Register 5 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR5_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR6; /*!< (@ 0x00001218) FIFO Data Register 6 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR6_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR7; /*!< (@ 0x0000121C) FIFO Data Register 7 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR7_b;
- };
-
- union
- {
- __IM uint32_t ADFIFODR8; /*!< (@ 0x00001220) FIFO Data Register 8 */
-
- struct
- {
- __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
- uint32_t : 8;
- __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
- __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
- } ADFIFODR8_b;
- };
-} R_ADC_B0_Type; /*!< Size = 4644 (0x1224) */
-
-/* =========================================================================================================================== */
-/* ================ R_DOC_B ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Data Operation Circuit (R_DOC_B)
- */
-
-typedef struct /*!< (@ 0x40109000) R_DOC_B Structure */
-{
- union
- {
- __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
-
- struct
- {
- __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
- uint8_t : 1;
- __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */
- __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */
- __IOM uint8_t DOPCIE : 1; /*!< [7..7] Data Operation Circuit Interrupt Enable */
- } DOCR_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */
-
- struct
- {
- __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */
- uint8_t : 7;
- } DOSR_b;
- };
- __IM uint8_t RESERVED2;
- __IM uint16_t RESERVED3;
-
- union
- {
- __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */
-
- struct
- {
- __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */
- uint8_t : 7;
- } DOSCR_b;
- };
- __IM uint8_t RESERVED4;
- __IM uint16_t RESERVED5;
- __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */
- __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */
- __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */
-} R_DOC_B_Type; /*!< Size = 24 (0x18) */
-
-/* =========================================================================================================================== */
-/* ================ R_SCI_B0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Serial Communication Interface 0 (R_SCI_B0)
- */
-
-typedef struct /*!< (@ 0x40118000) R_SCI_B0 Structure */
-{
- union
- {
- __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */
-
- struct
- {
- __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */
- __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */
- __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */
- __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */
- __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */
- uint32_t : 11;
- __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */
- uint32_t : 2;
- __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */
- __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */
- uint32_t : 3;
- } RDR_b;
- };
-
- union
- {
- __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */
-
- struct
- {
- __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */
- __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */
- uint32_t : 2;
- __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */
- uint32_t : 19;
- } TDR_b;
- };
-
- union
- {
- __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */
-
- struct
- {
- __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */
- uint32_t : 3;
- __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */
- uint32_t : 3;
- __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */
- __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */
- __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */
- uint32_t : 5;
- __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */
- uint32_t : 3;
- __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */
- __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */
- uint32_t : 2;
- __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */
- uint32_t : 7;
- } CCR0_b;
- };
-
- union
- {
- __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */
-
- struct
- {
- __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */
- __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */
- uint32_t : 2;
- __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */
- __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */
- uint32_t : 2;
- __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */
- __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */
- uint32_t : 2;
- __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */
- __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */
- uint32_t : 2;
- __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */
- uint32_t : 3;
- __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */
- uint32_t : 3;
- __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */
- uint32_t : 1;
- __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */
- uint32_t : 3;
- } CCR1_b;
- };
-
- union
- {
- __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */
-
- struct
- {
- __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */
- uint32_t : 1;
- __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */
- __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */
- __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */
- uint32_t : 1;
- __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */
- __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */
- uint32_t : 3;
- __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */
- uint32_t : 2;
- __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */
- } CCR2_b;
- };
-
- union
- {
- __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */
- __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */
- uint32_t : 5;
- __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */
- __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */
- uint32_t : 2;
- __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */
- __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */
- __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */
- __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */
- __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */
- __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */
- __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */
- __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */
- uint32_t : 2;
- __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */
- uint32_t : 2;
- __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */
- __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */
- uint32_t : 2;
- } CCR3_b;
- };
-
- union
- {
- __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */
-
- struct
- {
- __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */
- uint32_t : 7;
- __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */
- __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */
- uint32_t : 6;
- __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */
- __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */
- __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */
- __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */
- } CCR4_b;
- };
-
- union
- {
- __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */
-
- struct
- {
- __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */
- uint8_t : 3;
- __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */
- uint8_t : 3;
- } CESR_b;
- };
- __IM uint8_t RESERVED;
- __IM uint16_t RESERVED1;
-
- union
- {
- __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */
-
- struct
- {
- __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */
- uint32_t : 3;
- __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */
- __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */
- uint32_t : 3;
- __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */
- uint32_t : 2;
- __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */
- __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */
- __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */
- uint32_t : 1;
- __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */
- __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */
- uint32_t : 8;
- } ICR_b;
- };
-
- union
- {
- __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */
-
- struct
- {
- __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */
- uint32_t : 7;
- __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */
- uint32_t : 2;
- __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */
- __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */
- uint32_t : 2;
- __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */
- __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */
- uint32_t : 3;
- } FCR_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */
-
- struct
- {
- __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */
- __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */
- __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */
- uint32_t : 1;
- __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */
- __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */
- __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */
- uint32_t : 1;
- __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */
- __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */
- uint32_t : 2;
- __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */
- __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */
- uint32_t : 2;
- __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */
- __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */
- __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */
- uint32_t : 5;
- } MCR_b;
- };
-
- union
- {
- __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */
-
- struct
- {
- __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */
- uint32_t : 7;
- __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */
- uint32_t : 3;
- __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */
- uint32_t : 11;
- } DCR_b;
- };
-
- union
- {
- __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */
-
- struct
- {
- __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */
- uint32_t : 6;
- __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */
- __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */
- __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */
- __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */
- __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */
- __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */
- __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */
- uint32_t : 2;
- __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */
- __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */
- __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */
- uint32_t : 1;
- __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */
- uint32_t : 6;
- } XCR0_b;
- };
-
- union
- {
- __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */
-
- struct
- {
- __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */
- uint32_t : 3;
- __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */
- __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */
- uint32_t : 2;
- __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */
- __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */
- __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */
- } XCR1_b;
- };
-
- union
- {
- __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */
-
- struct
- {
- __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */
- __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */
- __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */
- } XCR2_b;
- };
- __IM uint32_t RESERVED3[2];
-
- union
- {
- __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */
-
- struct
- {
- uint32_t : 4;
- __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
- uint32_t : 10;
- __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */
- __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */
- __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */
- __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */
- uint32_t : 5;
- __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */
- uint32_t : 1;
- __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */
- __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */
- __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */
- __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */
- __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */
- __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */
- } CSR_b;
- };
-
- union
- {
- __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */
-
- struct
- {
- __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
- uint32_t : 2;
- __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
- * Flag */
- uint32_t : 28;
- } ISR_b;
- };
-
- union
- {
- __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */
-
- struct
- {
- __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */
- uint32_t : 7;
- __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */
- uint32_t : 2;
- __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */
- uint32_t : 2;
- __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */
- uint32_t : 2;
- } FRSR_b;
- };
-
- union
- {
- __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */
-
- struct
- {
- __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */
- uint32_t : 26;
- } FTSR_b;
- };
-
- union
- {
- __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */
-
- struct
- {
- __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */
- __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */
- __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */
- uint32_t : 1;
- __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */
- uint32_t : 1;
- __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */
- uint32_t : 25;
- } MSR_b;
- };
-
- union
- {
- __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */
-
- struct
- {
- __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */
- __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */
- uint32_t : 6;
- __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */
- __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */
- __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */
- __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */
- __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */
- __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */
- __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */
- __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */
- __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */
- __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */
- } XSR0_b;
- };
-
- union
- {
- __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */
-
- struct
- {
- __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */
- uint32_t : 16;
- } XSR1_b;
- };
- __IM uint32_t RESERVED4;
-
- union
- {
- __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */
-
- struct
- {
- uint32_t : 4;
- __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */
- uint32_t : 11;
- __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */
- __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */
- __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */
- uint32_t : 5;
- __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */
- uint32_t : 1;
- __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */
- __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */
- __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */
- __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */
- uint32_t : 1;
- __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */
- } CFCLR_b;
- };
-
- union
- {
- __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */
-
- struct
- {
- uint32_t : 3;
- __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */
- uint32_t : 28;
- } ICFCLR_b;
- };
-
- union
- {
- __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */
-
- struct
- {
- __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */
- uint32_t : 31;
- } FFCLR_b;
- };
-
- union
- {
- __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */
-
- struct
- {
- __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */
- __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */
- __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */
- uint32_t : 1;
- __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */
- uint32_t : 27;
- } MFCLR_b;
- };
-
- union
- {
- __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */
-
- struct
- {
- uint32_t : 8;
- __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */
- __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */
- __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */
- __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */
- __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */
- __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */
- __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */
- __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */
- uint32_t : 16;
- } XFCLR_b;
- };
-} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */
-
-/* =========================================================================================================================== */
-/* ================ R_SPI_B0 ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Serial Peripheral Interface 0 (R_SPI_B0)
- */
-
-typedef struct /*!< (@ 0x4011A000) R_SPI_B0 Structure */
-{
- __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */
-
- union
- {
- __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */
-
- struct
- {
- __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */
- uint32_t : 5;
- __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */
- uint32_t : 5;
- __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */
- uint32_t : 5;
- __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */
- uint32_t : 5;
- } SPDECR_b;
- };
-
- union
- {
- __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */
-
- struct
- {
- __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */
- uint32_t : 6;
- __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */
- __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */
- __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */
- uint32_t : 1;
- __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */
- __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */
- __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */
- __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */
- uint32_t : 1;
- __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */
- __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */
- __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */
- __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */
- __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */
- __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */
- uint32_t : 2;
- __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */
- __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */
- uint32_t : 2;
- __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */
- __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */
- __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */
- } SPCR_b;
- };
-
- union
- {
- __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */
-
- struct
- {
- __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */
- uint32_t : 1;
- __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */
- __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */
- __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */
- __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */
- __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */
- uint32_t : 2;
- __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */
- __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */
- uint32_t : 10;
- } SPCR2_b;
- };
-
- union
- {
- __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */
-
- struct
- {
- __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */
- __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */
- __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */
- __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */
- uint32_t : 4;
- __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */
- uint32_t : 8;
- __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */
- uint32_t : 5;
- } SPCR3_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD0_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD1_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD2_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD3_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD4_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD5_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD6_b;
- };
-
- union
- {
- __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */
-
- struct
- {
- __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
- __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
- __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
- uint32_t : 3;
- __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
- uint32_t : 4;
- __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
- __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
- __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
- __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
- __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
- uint32_t : 3;
- __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
- uint32_t : 5;
- } SPCMD7_b;
- };
- __IM uint32_t RESERVED[3];
-
- union
- {
- __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */
-
- struct
- {
- __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
- uint32_t : 2;
- __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */
- __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */
- uint32_t : 3;
- __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */
- uint32_t : 22;
- } SPDCR_b;
- };
-
- union
- {
- __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */
-
- struct
- {
- __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */
- uint32_t : 6;
- __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */
- uint32_t : 22;
- } SPDCR2_b;
- };
- __IM uint32_t RESERVED1[2];
-
- union
- {
- __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */
-
- struct
- {
- uint32_t : 8;
- __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */
- uint32_t : 1;
- __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */
- uint32_t : 8;
- __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */
- __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */
- __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */
- __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */
- __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */
- __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */
- __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */
- __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */
- __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */
- } SPSR_b;
- };
- __IM uint32_t RESERVED2;
-
- union
- {
- __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */
-
- struct
- {
- __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */
- uint32_t : 29;
- } SPTFSR_b;
- };
-
- union
- {
- __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */
-
- struct
- {
- __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */
- uint32_t : 29;
- } SPRFSR_b;
- };
-
- union
- {
- __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */
-
- struct
- {
- __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */
- uint32_t : 31;
- } SPPSR_b;
- };
- __IM uint32_t RESERVED3;
-
- union
- {
- __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */
-
- struct
- {
- uint32_t : 23;
- __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */
- __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */
- uint32_t : 1;
- __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */
- __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */
- __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */
- __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */
- __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */
- __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */
- } SPSRC_b;
- };
-
- union
- {
- __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */
-
- struct
- {
- __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */
- uint32_t : 31;
- } SPFCR_b;
- };
-} R_SPI_B0_Type; /*!< Size = 112 (0x70) */
-
-/* =========================================================================================================================== */
-/* ================ R_TFU ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Trigonometric Function Unit (TFU) (R_TFU)
- */
-
-typedef struct /*!< (@ 0x90003000) R_TFU Structure */
-{
- __IM uint32_t RESERVED[4];
-
- union
- {
- __IOM float SCDT0; /*!< (@ 0x00000010) TBD */
-
- struct
- {
- __IOM uint32_t SCDT0 : 32; /*!< [31..0] TBD */
- } SCDT0_b;
- };
-
- union
- {
- __IOM float SCDT1; /*!< (@ 0x00000014) TBD */
-
- struct
- {
- __IOM uint32_t SCDT1 : 32; /*!< [31..0] TBD */
- } SCDT1_b;
- };
-
- union
- {
- __IOM float ATDT0; /*!< (@ 0x00000018) TBD */
-
- struct
- {
- __IOM uint32_t ATDT0 : 32; /*!< [31..0] TBD */
- } ATDT0_b;
- };
-
- union
- {
- __IOM float ATDT1; /*!< (@ 0x0000001C) TBD */
-
- struct
- {
- __IOM uint32_t ATDT1 : 32; /*!< [31..0] TBD */
- } ATDT1_b;
- };
-} R_TFU_Type; /*!< Size = 32 (0x20) */
-
-/** @} */ /* End of group Device_Peripheral_peripherals */
-
- #ifdef BSP_OVERRIDE_REG_HEADER
- #include BSP_OVERRIDE_REG_HEADER
- #endif
-
- #include "base_addresses.h"
-
-/* ========================================= End of section using anonymous unions ========================================= */
- #if defined(__CC_ARM)
- #pragma pop
- #elif defined(__ICCARM__)
-
-/* leave anonymous unions enabled */
- #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic pop
- #elif defined(__GNUC__)
-
-/* anonymous unions are enabled by default */
- #elif defined(__TMS470__)
-
-/* anonymous unions are enabled by default */
- #elif defined(__TASKING__)
- #pragma warning restore
- #elif defined(__CSMC__)
-
-/* anonymous unions are enabled by default */
- #endif
-
-/* =========================================================================================================================== */
-/* ================ Pos/Mask Cluster Section ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup PosMask_clusters
- * @{
- */
-
-/* =========================================================================================================================== */
-/* ================ CSa ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== MOD ========================================================== */
- #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
- #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
- #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
- #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
- #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
- #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
- #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
- #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
- #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
- #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
-/* ========================================================= WCR1 ========================================================== */
- #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
- #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
- #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
- #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
- #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
- #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
- #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
-/* ========================================================= WCR2 ========================================================== */
- #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
- #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
- #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
- #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
- #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
- #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
- #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
- #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
- #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
- #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
- #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
-
-/* =========================================================================================================================== */
-/* ================ CSb ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== CR =========================================================== */
- #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
- #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
- #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
- #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
- #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
- #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
- #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
- #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
-/* ========================================================== REC ========================================================== */
- #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
- #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
- #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
- #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ SDRAM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SDCCR ========================================================= */
- #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
- #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
- #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
- #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
-/* ======================================================== SDCMOD ========================================================= */
- #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */
- #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */
-/* ======================================================== SDAMOD ========================================================= */
- #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */
- #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */
-/* ======================================================== SDSELF ========================================================= */
- #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */
- #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */
-/* ======================================================== SDRFCR ========================================================= */
- #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */
- #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */
- #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */
- #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */
-/* ======================================================== SDRFEN ========================================================= */
- #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */
- #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */
-/* ========================================================= SDICR ========================================================= */
- #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */
- #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */
-/* ========================================================= SDIR ========================================================== */
- #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */
- #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */
- #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */
- #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */
- #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */
- #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */
-/* ========================================================= SDADR ========================================================= */
- #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */
- #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */
-/* ========================================================= SDTR ========================================================== */
- #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */
- #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */
- #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */
- #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */
- #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */
- #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */
- #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */
- #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */
- #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */
- #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */
-/* ========================================================= SDMOD ========================================================= */
- #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */
- #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */
-/* ========================================================= SDSR ========================================================== */
- #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */
- #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */
- #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */
- #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */
- #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */
- #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ BUSERR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ADD ========================================================== */
- #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
- #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= STAT ========================================================== */
- #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */
- #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */
- #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ BUSM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== CNT ========================================================== */
- #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */
- #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ BUSS ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== CNT ========================================================== */
- #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */
- #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ MB ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */
- #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */
- #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */
- #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */
- #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */
- #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */
- #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */
- #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */
-/* ========================================================== DL =========================================================== */
- #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */
- #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */
-/* =========================================================== D =========================================================== */
- #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */
-/* ========================================================== TS =========================================================== */
- #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */
- #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */
- #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */
- #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= NCFG ========================================================== */
- #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */
- #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */
- #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */
- #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */
- #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */
- #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */
- #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */
-/* ========================================================== CTR ========================================================== */
- #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */
- #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */
- #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */
- #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
- #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */
- #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
- #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */
- #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */
- #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */
- #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */
- #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */
- #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */
- #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */
- #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */
- #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */
- #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */
- #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */
- #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */
- #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */
- #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */
- #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */
- #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */
- #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */
- #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */
- #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
-/* ========================================================== STS ========================================================== */
- #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */
- #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */
- #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */
- #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */
- #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */
- #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */
- #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */
- #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */
- #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */
- #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */
- #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */
- #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */
-/* ========================================================= ERFL ========================================================== */
- #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */
- #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */
- #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */
- #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */
- #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */
- #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */
- #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */
- #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */
- #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */
- #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */
- #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */
- #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */
- #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */
- #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */
- #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */
- #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */
- #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDC2 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DCFG ========================================================== */
- #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */
- #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */
- #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */
- #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */
- #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDCFG ========================================================= */
- #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */
- #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */
- #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */
- #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */
- #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */
- #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */
- #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */
- #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */
- #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */
- #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */
- #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */
- #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */
- #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */
-/* ========================================================= FDCTR ========================================================= */
- #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */
- #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */
- #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
- #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */
- #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */
- #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */
- #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */
- #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */
- #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */
-/* ========================================================= FDCRC ========================================================= */
- #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */
- #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */
- #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */
- #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */
-/* ========================================================= BLCT ========================================================== */
- #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */
- #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */
- #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */
-/* ========================================================= BLSTS ========================================================= */
- #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */
- #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDGAFL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */
- #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */
- #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */
- #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */
- #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */
-/* =========================================================== M =========================================================== */
- #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */
- #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */
- #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */
- #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */
- #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */
-/* ========================================================== P0 =========================================================== */
- #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */
- #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */
- #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */
- #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */
- #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */
- #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */
- #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== P1 =========================================================== */
- #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */
- #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDTHL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ACC0 ========================================================== */
- #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */
- #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */
- #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */
- #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */
- #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */
- #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */
-/* ========================================================= ACC1 ========================================================== */
- #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */
- #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */
- #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */
- #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ CFDRM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */
- #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */
- #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */
- #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */
- #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */
- #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */
- #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */
- #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */
- #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */
- #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */
- #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */
- #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */
- #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDRF ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */
- #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */
- #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */
- #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */
- #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */
- #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */
- #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */
- #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */
- #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */
- #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */
- #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */
- #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */
- #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDCF ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */
- #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */
- #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */
- #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */
- #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */
- #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */
- #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */
- #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */
- #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */
- #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */
- #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */
- #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */
- #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDTM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */
- #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */
- #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */
- #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */
- #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */
- #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */
- #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDCTR ========================================================= */
- #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */
- #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */
- #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */
- #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */
- #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */
- #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
- #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= NCFG ========================================================== */
- #define R_CANFDL_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */
- #define R_CANFDL_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */
- #define R_CANFDL_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */
- #define R_CANFDL_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */
- #define R_CANFDL_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */
- #define R_CANFDL_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */
- #define R_CANFDL_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */
-/* ========================================================== CTR ========================================================== */
- #define R_CANFDL_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */
- #define R_CANFDL_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */
- #define R_CANFDL_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */
- #define R_CANFDL_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
- #define R_CANFDL_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */
- #define R_CANFDL_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
- #define R_CANFDL_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */
- #define R_CANFDL_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */
- #define R_CANFDL_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */
- #define R_CANFDL_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */
- #define R_CANFDL_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */
- #define R_CANFDL_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */
- #define R_CANFDL_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */
- #define R_CANFDL_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */
- #define R_CANFDL_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */
- #define R_CANFDL_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */
- #define R_CANFDL_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */
- #define R_CANFDL_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */
- #define R_CANFDL_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */
- #define R_CANFDL_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */
- #define R_CANFDL_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */
- #define R_CANFDL_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
-/* ========================================================== STS ========================================================== */
- #define R_CANFDL_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */
- #define R_CANFDL_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */
- #define R_CANFDL_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */
- #define R_CANFDL_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */
- #define R_CANFDL_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */
- #define R_CANFDL_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */
- #define R_CANFDL_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */
- #define R_CANFDL_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */
- #define R_CANFDL_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */
- #define R_CANFDL_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */
- #define R_CANFDL_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */
- #define R_CANFDL_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */
-/* ========================================================= ERFL ========================================================== */
- #define R_CANFDL_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */
- #define R_CANFDL_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */
- #define R_CANFDL_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */
- #define R_CANFDL_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */
- #define R_CANFDL_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */
- #define R_CANFDL_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */
- #define R_CANFDL_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */
- #define R_CANFDL_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */
- #define R_CANFDL_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */
- #define R_CANFDL_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */
- #define R_CANFDL_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */
- #define R_CANFDL_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */
- #define R_CANFDL_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */
- #define R_CANFDL_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */
- #define R_CANFDL_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */
- #define R_CANFDL_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */
- #define R_CANFDL_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDC2 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DCFG ========================================================== */
- #define R_CANFDL_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */
- #define R_CANFDL_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */
- #define R_CANFDL_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */
- #define R_CANFDL_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */
- #define R_CANFDL_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */
- #define R_CANFDL_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */
- #define R_CANFDL_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDCFG ========================================================= */
- #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */
- #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */
- #define R_CANFDL_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */
- #define R_CANFDL_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */
- #define R_CANFDL_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */
- #define R_CANFDL_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */
- #define R_CANFDL_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */
- #define R_CANFDL_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */
- #define R_CANFDL_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */
-/* ========================================================= FDCTR ========================================================= */
- #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */
- #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */
- #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFDL_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
- #define R_CANFDL_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */
- #define R_CANFDL_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */
- #define R_CANFDL_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */
- #define R_CANFDL_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */
- #define R_CANFDL_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */
- #define R_CANFDL_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */
-/* ========================================================= FDCRC ========================================================= */
- #define R_CANFDL_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */
- #define R_CANFDL_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */
- #define R_CANFDL_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */
- #define R_CANFDL_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ CFDGAFL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFDL_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */
- #define R_CANFDL_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */
- #define R_CANFDL_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */
- #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */
- #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */
-/* =========================================================== M =========================================================== */
- #define R_CANFDL_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */
- #define R_CANFDL_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */
- #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */
- #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */
- #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */
-/* ========================================================== P0 =========================================================== */
- #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */
- #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */
- #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */
- #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */
- #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */
- #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */
- #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */
- #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== P1 =========================================================== */
- #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */
- #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDTHL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ACC0 ========================================================== */
- #define R_CANFDL_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */
- #define R_CANFDL_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */
- #define R_CANFDL_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */
- #define R_CANFDL_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */
- #define R_CANFDL_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */
-/* ========================================================= ACC1 ========================================================== */
- #define R_CANFDL_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */
- #define R_CANFDL_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */
- #define R_CANFDL_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */
- #define R_CANFDL_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ CFDRF ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFDL_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */
- #define R_CANFDL_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */
- #define R_CANFDL_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */
- #define R_CANFDL_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFDL_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */
- #define R_CANFDL_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */
- #define R_CANFDL_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */
- #define R_CANFDL_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFDL_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */
- #define R_CANFDL_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */
- #define R_CANFDL_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */
- #define R_CANFDL_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */
- #define R_CANFDL_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */
- #define R_CANFDL_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFDL_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */
- #define R_CANFDL_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDCF ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFDL_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */
- #define R_CANFDL_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */
- #define R_CANFDL_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */
- #define R_CANFDL_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFDL_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */
- #define R_CANFDL_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */
- #define R_CANFDL_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */
- #define R_CANFDL_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFDL_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */
- #define R_CANFDL_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */
- #define R_CANFDL_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */
- #define R_CANFDL_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */
- #define R_CANFDL_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */
- #define R_CANFDL_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFDL_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */
- #define R_CANFDL_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDTM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFDL_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */
- #define R_CANFDL_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */
- #define R_CANFDL_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */
- #define R_CANFDL_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFDL_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */
- #define R_CANFDL_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */
- #define R_CANFDL_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */
- #define R_CANFDL_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDCTR ========================================================= */
- #define R_CANFDL_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */
- #define R_CANFDL_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */
- #define R_CANFDL_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */
- #define R_CANFDL_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */
- #define R_CANFDL_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */
- #define R_CANFDL_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFDL_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
- #define R_CANFDL_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ RM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ID =========================================================== */
- #define R_CANFDL_CFDRMC_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */
- #define R_CANFDL_CFDRMC_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */
- #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */
- #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */
- #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */
-/* ========================================================== PTR ========================================================== */
- #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */
- #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */
- #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */
- #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */
-/* ========================================================= FDSTS ========================================================= */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */
- #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */
-/* ========================================================== DF =========================================================== */
- #define R_CANFDL_CFDRMC_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */
- #define R_CANFDL_CFDRMC_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ CFDRMC ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================ ELSEGR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== BY =========================================================== */
- #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */
- #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */
- #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */
- #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */
- #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */
- #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ ELSR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== HA =========================================================== */
- #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */
- #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */
-
-/* =========================================================================================================================== */
-/* ================ TM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= STTRU ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos (0UL) /*!< TMSTTRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= STTRL ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos (0UL) /*!< TMSTTRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= CYCR ========================================================== */
- #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos (0UL) /*!< TMCYCR (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff) */
-/* ========================================================= PLSR ========================================================== */
- #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos (0UL) /*!< TMPLSR (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff) */
-
-/* =========================================================================================================================== */
-/* ================ PR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= MACRU ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos (0UL) /*!< PRMACRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff) */
-/* ========================================================= MACRL ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos (0UL) /*!< PRMACRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff) */
-
-/* =========================================================================================================================== */
-/* ================ BG ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== EN =========================================================== */
- #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */
- #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */
- #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */
- #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */
- #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */
- #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
-/* ========================================================= PERI ========================================================== */
- #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */
- #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */
- #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */
-/* ========================================================= SYNC ========================================================== */
- #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */
- #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */
- #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */
- #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */
-/* ========================================================= VSIZE ========================================================= */
- #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */
- #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */
- #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */
-/* ========================================================= HSIZE ========================================================= */
- #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */
- #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */
- #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */
-/* ========================================================== BGC ========================================================== */
- #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */
- #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */
- #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */
- #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */
- #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */
-/* ========================================================== MON ========================================================== */
- #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */
- #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */
- #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */
- #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */
- #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */
- #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ GR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== VEN ========================================================== */
- #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */
- #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */
-/* ========================================================= FLMRD ========================================================= */
- #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */
- #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */
-/* ========================================================= FLM1 ========================================================== */
- #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */
- #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */
-/* ========================================================= FLM2 ========================================================== */
- #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */
- #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= FLM3 ========================================================== */
- #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */
- #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */
-/* ========================================================= FLM5 ========================================================== */
- #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */
- #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */
- #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */
-/* ========================================================= FLM6 ========================================================== */
- #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */
- #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */
-/* ========================================================== AB1 ========================================================== */
- #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */
- #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */
- #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */
- #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */
- #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */
- #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */
- #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */
- #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */
-/* ========================================================== AB2 ========================================================== */
- #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */
- #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */
- #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */
-/* ========================================================== AB3 ========================================================== */
- #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */
- #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */
- #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */
-/* ========================================================== AB4 ========================================================== */
- #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */
- #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */
- #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */
-/* ========================================================== AB5 ========================================================== */
- #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */
- #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */
- #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */
-/* ========================================================== AB6 ========================================================== */
- #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */
- #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */
- #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */
- #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */
-/* ========================================================== AB7 ========================================================== */
- #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */
- #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */
- #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */
-/* ========================================================== AB8 ========================================================== */
- #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */
- #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */
- #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */
- #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */
-/* ========================================================== AB9 ========================================================== */
- #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */
- #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */
- #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */
- #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */
- #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */
-/* ========================================================= BASE ========================================================== */
- #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */
- #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */
- #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */
- #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */
-/* ======================================================== CLUTINT ======================================================== */
- #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */
- #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */
- #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */
-/* ========================================================== MON ========================================================== */
- #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */
- #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */
- #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */
- #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ GAM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= LATCH ========================================================= */
- #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */
- #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */
-/* ======================================================== GAM_SW ========================================================= */
- #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */
- #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */
-/* ========================================================== LUT ========================================================== */
- #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */
- #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */
-/* ========================================================= AREA ========================================================== */
- #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */
- #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */
-
-/* =========================================================================================================================== */
-/* ================ OUT ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== VLATCH ========================================================= */
- #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */
- #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */
-/* ========================================================== SET ========================================================== */
- #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */
- #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */
- #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */
- #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */
- #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */
- #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */
- #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */
-/* ======================================================== BRIGHT1 ======================================================== */
- #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */
- #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */
-/* ======================================================== BRIGHT2 ======================================================== */
- #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */
- #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */
- #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */
- #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */
-/* ======================================================= CONTRAST ======================================================== */
- #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */
- #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */
- #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */
- #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */
- #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */
- #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */
-/* ========================================================= PDTHA ========================================================= */
- #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */
- #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */
- #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */
- #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */
- #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */
- #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */
- #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */
- #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */
-/* ======================================================= CLKPHASE ======================================================== */
- #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */
- #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */
- #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */
- #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */
- #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */
- #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */
- #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */
- #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ TCON ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== TIM ========================================================== */
- #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */
- #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
- #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */
-/* ========================================================= STVA1 ========================================================= */
- #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */
- #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */
- #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */
-/* ========================================================= STVB1 ========================================================= */
- #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */
- #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */
- #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */
-/* ========================================================= STVA2 ========================================================= */
- #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */
- #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */
-/* ========================================================= STVB2 ========================================================= */
- #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */
- #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */
-/* ========================================================= STHA1 ========================================================= */
- #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */
- #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */
- #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */
-/* ========================================================= STHB1 ========================================================= */
- #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */
- #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */
- #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */
- #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */
-/* ========================================================= STHA2 ========================================================= */
- #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */
- #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */
- #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */
-/* ========================================================= STHB2 ========================================================= */
- #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */
- #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */
- #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */
-/* ========================================================== DE =========================================================== */
- #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */
- #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ SYSCNT ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== DTCTEN ========================================================= */
- #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */
- #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */
- #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */
- #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */
-/* ========================================================= INTEN ========================================================= */
- #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */
- #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */
- #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */
- #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */
-/* ========================================================= STCLR ========================================================= */
- #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */
- #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */
- #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */
- #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */
-/* ========================================================= STMON ========================================================= */
- #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */
- #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */
- #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */
- #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */
-/* ======================================================= PANEL_CLK ======================================================= */
- #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */
- #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */
-
-/* =========================================================================================================================== */
-/* ================ GTDLYR ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== A =========================================================== */
- #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */
- #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */
-/* =========================================================== B =========================================================== */
- #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */
- #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */
-
-/* =========================================================================================================================== */
-/* ================ SAR ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== L =========================================================== */
- #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */
- #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */
-/* =========================================================== U =========================================================== */
- #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */
- #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */
- #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */
- #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */
- #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */
- #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ REGION ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== C =========================================================== */
- #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */
- #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */
- #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */
- #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */
- #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
- #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
-/* =========================================================== S =========================================================== */
- #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */
- #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */
-/* =========================================================== E =========================================================== */
- #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */
- #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ MMPU ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== CTL ========================================================== */
- #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */
- #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */
- #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
- #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
-/* ========================================================== PT =========================================================== */
- #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
- #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ SMPU ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== R =========================================================== */
- #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */
- #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */
- #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */
- #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */
- #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */
- #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */
- #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */
- #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */
- #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */
- #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */
- #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ SP ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== OAD ========================================================== */
- #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
-/* ========================================================== CTL ========================================================== */
- #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */
- #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */
- #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
- #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
-/* ========================================================== PT =========================================================== */
- #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
- #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
-/* ========================================================== SA =========================================================== */
- #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */
- #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */
-/* ========================================================== EA =========================================================== */
- #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */
- #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ AMP ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== OS =========================================================== */
-/* ========================================================== PS =========================================================== */
-/* ========================================================== MS =========================================================== */
-
-/* =========================================================================================================================== */
-/* ================ AMPOT ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== P =========================================================== */
- #define R_OPAMP_AMPOT_P_TRMP_Pos (0UL) /*!< TRMP (Bit 0) */
- #define R_OPAMP_AMPOT_P_TRMP_Msk (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f) */
-/* =========================================================== N =========================================================== */
- #define R_OPAMP_AMPOT_N_TRMN_Pos (0UL) /*!< TRMN (Bit 0) */
- #define R_OPAMP_AMPOT_N_TRMN_Msk (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f) */
-
-/* =========================================================================================================================== */
-/* ================ PIN ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================= PmnPFS_BY ======================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
-/* ======================================================= PmnPFS_HA ======================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
- #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
-/* ======================================================== PmnPFS ========================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
- #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */
- #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */
- #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */
- #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
- #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */
- #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
- #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
- #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
- #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
- #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
- #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
- #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
- #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */
- #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */
- #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */
- #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ PORT ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================ PMSAR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= PMSAR ========================================================= */
-
-/* =========================================================================================================================== */
-/* ================ RTCCR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= RTCCR ========================================================= */
- #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */
- #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */
- #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */
- #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */
- #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */
- #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ CP ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= RSEC ========================================================== */
- #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
- #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
- #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
- #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT0 ========================================================= */
- #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */
- #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */
-/* ========================================================= RMIN ========================================================== */
- #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
- #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
- #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
- #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT1 ========================================================= */
- #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */
- #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */
-/* ========================================================== RHR ========================================================== */
- #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */
- #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
- #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
- #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
- #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT2 ========================================================= */
- #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */
- #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */
-/* ========================================================= RDAY ========================================================== */
- #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
- #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
- #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
- #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT3 ========================================================= */
- #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */
- #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */
-/* ========================================================= RMON ========================================================== */
- #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
- #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
- #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
- #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ CSa ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== MOD ========================================================== */
- #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
- #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
- #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
- #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
- #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
- #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
-/* ========================================================= WCR1 ========================================================== */
- #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
- #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
- #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
- #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
- #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
- #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
- #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
-/* ========================================================= WCR2 ========================================================== */
- #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
- #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
- #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
- #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
- #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
- #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
- #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
- #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
- #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
- #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
- #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
-
-/* =========================================================================================================================== */
-/* ================ CSb ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== CR =========================================================== */
- #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
- #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
- #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
- #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
- #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
- #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
-/* ========================================================== REC ========================================================== */
- #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
- #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
- #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
- #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ BUSERR ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== ADD ========================================================== */
- #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
- #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= ERRRW ========================================================= */
- #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */
- #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ BUSTZFERR ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== TZFADD ========================================================= */
- #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */
- #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= TZFERRRW ======================================================== */
- #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */
- #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ PIPE_TR ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================== E =========================================================== */
- #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */
- #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */
- #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */
-/* =========================================================== N =========================================================== */
- #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */
- #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */
-
-/** @} */ /* End of group PosMask_clusters */
-
-/* =========================================================================================================================== */
-/* ================ Pos/Mask Peripheral Section ================ */
-/* =========================================================================================================================== */
-
-/** @addtogroup PosMask_peripherals
- * @{
- */
-
-/* =========================================================================================================================== */
-/* ================ R_ACMPHS0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CMPCTL ========================================================= */
- #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */
- #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */
- #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */
- #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */
- #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */
- #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */
- #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */
- #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */
- #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */
- #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */
- #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */
- #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */
-/* ======================================================== CMPSEL0 ======================================================== */
- #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */
- #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== CMPSEL1 ======================================================== */
- #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */
- #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */
-/* ======================================================== CMPMON ========================================================= */
- #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */
- #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */
-/* ========================================================= CPIOC ========================================================= */
- #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */
- #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */
- #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */
- #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_ACMPLP ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== COMPMDR ======================================================== */
- #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */
- #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */
- #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */
- #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */
- #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */
- #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */
- #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */
- #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */
- #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */
-/* ======================================================== COMPFIR ======================================================== */
- #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */
- #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */
- #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */
- #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */
- #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */
- #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */
- #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */
- #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */
-/* ======================================================== COMPOCR ======================================================== */
- #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */
- #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */
- #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */
- #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */
- #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */
- #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */
-/* ======================================================= COMPSEL0 ======================================================== */
- #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */
- #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */
- #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */
- #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */
-/* ======================================================= COMPSEL1 ======================================================== */
- #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */
- #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */
- #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */
- #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */
- #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */
- #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */
-
-/* =========================================================================================================================== */
-/* ================ R_ADC0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ADCSR ========================================================= */
- #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */
- #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */
- #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */
- #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */
- #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */
- #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */
- #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */
- #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */
- #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */
- #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */
- #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */
-/* ======================================================== ADANSA ========================================================= */
- #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */
- #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */
-/* ========================================================= ADADS ========================================================= */
- #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */
- #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */
-/* ========================================================= ADADC ========================================================= */
- #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */
- #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */
- #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */
- #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */
-/* ========================================================= ADCER ========================================================= */
- #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */
- #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */
- #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */
- #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */
- #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */
- #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */
- #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */
- #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */
- #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */
-/* ======================================================== ADSTRGR ======================================================== */
- #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */
- #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */
- #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */
- #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */
-/* ======================================================== ADEXICR ======================================================== */
- #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */
- #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */
- #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */
- #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */
- #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */
- #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */
- #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */
- #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */
- #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */
-/* ======================================================== ADANSB ========================================================= */
- #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */
- #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */
-/* ======================================================== ADDBLDR ======================================================== */
- #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */
- #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADTSDR ========================================================= */
- #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */
- #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADOCDR ========================================================= */
- #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */
- #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */
-/* ====================================================== ADRD_RIGHT ======================================================= */
- #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */
- #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */
- #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */
-/* ======================================================= ADRD_LEFT ======================================================= */
- #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */
- #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */
- #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
- #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
-/* ========================================================= ADDR ========================================================== */
- #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
- #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADSHCR ========================================================= */
- #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */
- #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */
- #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */
- #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */
- #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */
-/* ======================================================== ADDISCR ======================================================== */
- #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */
- #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */
- #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADSHMSR ======================================================== */
- #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */
- #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */
-/* ======================================================== ADACSR ========================================================= */
- #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */
- #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */
-/* ======================================================== ADGSPCR ======================================================== */
- #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */
- #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */
- #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */
- #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */
- #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */
-/* ========================================================= ADICR ========================================================= */
- #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */
- #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */
-/* ======================================================= ADDBLDRA ======================================================== */
- #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */
- #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADDBLDRB ======================================================== */
- #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */
- #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */
-/* ====================================================== ADHVREFCNT ======================================================= */
- #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
- #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */
- #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */
- #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */
-/* ======================================================= ADWINMON ======================================================== */
- #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */
- #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */
- #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */
- #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */
-/* ======================================================== ADCMPCR ======================================================== */
- #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */
- #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */
- #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */
- #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */
- #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */
- #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */
- #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */
-/* ====================================================== ADCMPANSER ======================================================= */
- #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */
- #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */
- #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCMPLER ======================================================== */
- #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */
- #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */
- #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCMPANSR ======================================================= */
- #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */
- #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */
-/* ======================================================== ADCMPLR ======================================================== */
- #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */
- #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCMPDR0 ======================================================== */
- #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */
- #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPDR1 ======================================================== */
- #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */
- #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADCMPSR ======================================================== */
- #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */
- #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCMPSER ======================================================== */
- #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */
- #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */
- #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCMPBNSR ======================================================= */
- #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */
- #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */
- #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADWINLLB ======================================================== */
- #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */
- #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADWINULB ======================================================== */
- #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */
- #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPBSR ======================================================== */
- #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */
- #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */
-/* ======================================================== ADSSTRL ======================================================== */
- #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */
- #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
-/* ======================================================== ADSSTRT ======================================================== */
- #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */
- #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
-/* ======================================================== ADSSTRO ======================================================== */
- #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */
- #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
-/* ======================================================== ADSSTR ========================================================= */
- #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */
- #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
-/* ======================================================== ADPGACR ======================================================== */
- #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */
- #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */
- #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */
- #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */
- #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */
- #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */
- #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */
- #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */
- #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */
- #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */
- #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */
- #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */
- #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */
- #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */
- #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */
- #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */
- #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */
-/* ========================================================= ADRD ========================================================== */
- #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */
- #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */
-/* ========================================================= ADRST ========================================================= */
- #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
- #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
-/* ====================================================== VREFAMPCNT ======================================================= */
- #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */
- #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */
- #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */
- #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
- #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
- #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */
- #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */
- #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCALEXE ======================================================== */
- #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */
- #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */
- #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */
-/* ======================================================== ADANIM ========================================================= */
- #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */
- #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */
-/* ======================================================= ADPGAGS0 ======================================================== */
- #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */
- #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */
- #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */
- #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */
- #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */
- #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */
- #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */
- #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADPGADCR0 ======================================================= */
- #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */
- #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */
- #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */
- #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */
- #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */
- #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */
- #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */
- #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */
- #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */
-/* ========================================================= ADREF ========================================================= */
- #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */
- #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */
- #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */
-/* ======================================================== ADEXREF ======================================================== */
- #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */
- #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */
-/* ======================================================= ADAMPOFF ======================================================== */
- #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */
- #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */
-/* ======================================================== ADTSTPR ======================================================== */
- #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */
- #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */
- #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDDACER ======================================================== */
- #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */
- #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */
- #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */
- #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */
- #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */
- #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */
-/* ======================================================= ADEXTSTR ======================================================== */
- #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */
- #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */
- #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */
- #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */
- #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */
- #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */
- #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */
- #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */
- #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */
-/* ======================================================== ADTSTRA ======================================================== */
- #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */
- #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */
- #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */
- #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */
- #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */
- #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */
- #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */
- #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */
- #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADTSTRB ======================================================== */
- #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */
- #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */
-/* ======================================================== ADTSTRC ======================================================== */
- #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */
- #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */
- #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */
- #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */
-/* ======================================================== ADTSTRD ======================================================== */
- #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */
- #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADSWTSTR0 ======================================================= */
- #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */
- #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */
- #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */
- #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */
- #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */
- #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */
- #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADSWTSTR1 ======================================================= */
- #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */
- #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */
- #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */
- #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */
- #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */
- #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */
- #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADSWTSTR2 ======================================================= */
- #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */
- #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */
- #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */
- #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */
- #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */
- #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */
- #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */
- #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */
- #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */
- #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */
- #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */
- #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */
-/* ======================================================== ADSWCR ========================================================= */
- #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */
- #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */
- #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */
- #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */
-/* ======================================================== ADGSCS ========================================================= */
- #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */
- #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */
- #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */
- #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */
-/* ========================================================= ADSER ========================================================= */
- #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */
- #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */
-/* ======================================================== ADBUF0 ========================================================= */
- #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF1 ========================================================= */
- #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF2 ========================================================= */
- #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF3 ========================================================= */
- #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF4 ========================================================= */
- #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF5 ========================================================= */
- #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF6 ========================================================= */
- #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF7 ========================================================= */
- #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF8 ========================================================= */
- #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF9 ========================================================= */
- #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF10 ======================================================== */
- #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF11 ======================================================== */
- #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF12 ======================================================== */
- #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF13 ======================================================== */
- #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF14 ======================================================== */
- #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUF15 ======================================================== */
- #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
- #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADBUFEN ======================================================== */
- #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */
- #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */
-/* ======================================================= ADBUFPTR ======================================================== */
- #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */
- #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */
- #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */
- #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */
-/* ======================================================= ADPGADBS0 ======================================================= */
- #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */
- #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */
-/* ======================================================= ADPGADBS1 ======================================================= */
- #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */
- #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */
-/* ======================================================= ADREFMON ======================================================== */
- #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
- #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
-
-/* =========================================================================================================================== */
-/* ================ R_PSCU ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= PSARB ========================================================= */
- #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */
- #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */
- #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */
- #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */
- #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */
- #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */
- #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */
- #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */
- #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */
- #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */
- #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */
- #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */
- #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */
- #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */
- #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */
- #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */
- #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */
- #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */
- #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */
- #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */
- #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */
- #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */
- #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */
- #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */
-/* ========================================================= PSARC ========================================================= */
- #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */
- #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */
- #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */
- #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */
- #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */
- #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */
- #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */
- #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */
- #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */
- #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */
-/* ========================================================= PSARD ========================================================= */
- #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */
- #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */
- #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */
- #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */
- #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */
- #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */
- #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */
- #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */
- #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */
- #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */
- #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */
- #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */
- #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */
- #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */
- #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */
- #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */
- #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */
- #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */
-/* ========================================================= PSARE ========================================================= */
- #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */
- #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */
- #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */
- #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */
- #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */
- #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */
- #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */
- #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */
- #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */
- #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */
- #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */
- #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */
- #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */
- #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */
- #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */
- #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */
- #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */
-/* ========================================================= MSSAR ========================================================= */
- #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */
- #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */
- #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */
- #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */
- #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */
- #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */
- #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */
- #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */
-/* ======================================================= CFSAMONA ======================================================== */
- #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */
- #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */
-/* ======================================================= CFSAMONB ======================================================== */
- #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */
- #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */
-/* ======================================================== DFSAMON ======================================================== */
- #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */
- #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */
-/* ======================================================== SSAMONA ======================================================== */
- #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */
- #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */
-/* ======================================================== SSAMONB ======================================================== */
- #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */
- #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */
-/* ======================================================== DLMMON ========================================================= */
- #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */
- #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ R_AGT0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== AGT ========================================================== */
- #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
- #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */
-/* ======================================================== AGTCMA ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
- #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */
-/* ======================================================== AGTCMB ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
- #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */
-/* ========================================================= AGTCR ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
- #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
- #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
- #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */
- #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
- #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
- #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
- #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTMR1 ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */
- #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */
- #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
- #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */
- #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */
-/* ======================================================== AGTMR2 ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
- #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
- #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
-/* ======================================================== AGTIOC ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */
- #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */
- #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
- #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
- #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
- #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTISR ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */
- #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTCMSR ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
- #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
- #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
- #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
- #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
-/* ======================================================= AGTIOSEL ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */
- #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
- #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ R_AGTW0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== AGT ========================================================== */
- #define R_AGTW0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
- #define R_AGTW0_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== AGTCMA ========================================================= */
- #define R_AGTW0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
- #define R_AGTW0_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== AGTCMB ========================================================= */
- #define R_AGTW0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
- #define R_AGTW0_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= AGTCR ========================================================= */
- #define R_AGTW0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
- #define R_AGTW0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
- #define R_AGTW0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
- #define R_AGTW0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */
- #define R_AGTW0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
- #define R_AGTW0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
- #define R_AGTW0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
- #define R_AGTW0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTMR1 ========================================================= */
- #define R_AGTW0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */
- #define R_AGTW0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */
- #define R_AGTW0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
- #define R_AGTW0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */
- #define R_AGTW0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */
-/* ======================================================== AGTMR2 ========================================================= */
- #define R_AGTW0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
- #define R_AGTW0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
- #define R_AGTW0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
-/* ======================================================== AGTIOC ========================================================= */
- #define R_AGTW0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */
- #define R_AGTW0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */
- #define R_AGTW0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
- #define R_AGTW0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
- #define R_AGTW0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
- #define R_AGTW0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */
- #define R_AGTW0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTISR ========================================================= */
- #define R_AGTW0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */
- #define R_AGTW0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */
-/* ======================================================== AGTCMSR ======================================================== */
- #define R_AGTW0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
- #define R_AGTW0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
- #define R_AGTW0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
- #define R_AGTW0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
- #define R_AGTW0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
- #define R_AGTW0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
- #define R_AGTW0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
- #define R_AGTW0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
-/* ======================================================= AGTIOSEL ======================================================== */
- #define R_AGTW0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */
- #define R_AGTW0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_BUS ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CSRECEN ======================================================== */
- #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
- #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
- #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
- #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_CAC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= CACR0 ========================================================= */
- #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */
- #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */
-/* ========================================================= CACR1 ========================================================= */
- #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */
- #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */
- #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
- #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */
- #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */
- #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */
- #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */
- #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */
-/* ========================================================= CACR2 ========================================================= */
- #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */
- #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */
- #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */
- #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */
- #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */
- #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */
- #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */
- #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */
-/* ========================================================= CAICR ========================================================= */
- #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */
- #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */
- #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */
- #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */
- #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */
- #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */
- #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */
- #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */
- #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */
- #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */
- #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */
- #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */
-/* ========================================================= CASTR ========================================================= */
- #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */
- #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */
- #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */
- #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */
- #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */
- #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */
-/* ======================================================== CAULVR ========================================================= */
- #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */
- #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */
-/* ======================================================== CALLVR ========================================================= */
- #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */
- #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */
-/* ======================================================== CACNTBR ======================================================== */
- #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */
- #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_CAN0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== MKR ========================================================== */
- #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */
- #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */
- #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */
- #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */
-/* ========================================================= FIDCR ========================================================= */
- #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */
- #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */
- #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */
- #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */
- #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */
- #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */
- #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */
- #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */
-/* ======================================================== MKIVLR ========================================================= */
- #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */
- #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */
- #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */
- #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */
- #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */
- #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */
- #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */
- #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */
- #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */
- #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */
- #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */
- #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */
- #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */
- #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */
- #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */
- #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */
- #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */
- #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */
- #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */
- #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */
- #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */
- #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */
- #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */
- #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */
- #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */
- #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */
- #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */
- #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */
- #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */
- #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */
- #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */
- #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */
- #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */
-/* ========================================================= MIER ========================================================== */
- #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */
- #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */
- #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */
- #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */
- #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */
- #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */
- #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */
- #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */
- #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */
- #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */
- #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */
- #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */
- #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */
- #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */
- #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */
- #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */
- #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */
- #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */
- #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */
- #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */
- #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */
- #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */
- #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */
- #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */
- #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */
- #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */
- #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */
- #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */
- #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */
- #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */
- #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */
- #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */
- #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */
-/* ======================================================= MIER_FIFO ======================================================= */
- #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */
- #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */
- #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */
- #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */
- #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */
- #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */
- #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */
- #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */
- #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */
- #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */
- #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */
- #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */
- #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */
- #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */
- #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */
- #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */
- #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */
- #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */
- #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */
- #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */
- #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */
- #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */
- #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */
- #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */
- #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */
- #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */
- #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */
- #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */
- #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */
- #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */
-/* ======================================================== MCTL_TX ======================================================== */
- #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */
- #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */
- #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */
- #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */
- #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */
- #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */
- #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */
-/* ======================================================== MCTL_RX ======================================================== */
- #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */
- #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */
- #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */
- #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */
- #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */
- #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */
- #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */
- #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */
-/* ========================================================= CTLR ========================================================== */
- #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */
- #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */
- #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */
- #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */
- #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */
- #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */
- #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */
- #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */
- #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */
- #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */
- #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */
- #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */
- #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */
- #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */
- #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */
- #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */
- #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */
- #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */
- #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */
- #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */
-/* ========================================================== STR ========================================================== */
- #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */
- #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */
- #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */
- #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */
- #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */
- #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */
- #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */
- #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */
- #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */
- #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */
- #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */
- #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */
- #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */
- #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */
- #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */
- #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */
- #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */
-/* ========================================================== BCR ========================================================== */
- #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */
- #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */
- #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */
- #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */
- #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */
- #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */
- #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */
- #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */
- #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */
- #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */
-/* ========================================================= RFCR ========================================================== */
- #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */
- #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */
- #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */
- #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */
- #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */
- #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */
- #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */
- #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */
- #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */
- #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */
- #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */
- #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
-/* ========================================================= RFPCR ========================================================= */
- #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */
- #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */
-/* ========================================================= TFCR ========================================================== */
- #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */
- #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */
- #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */
- #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */
- #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */
- #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */
- #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */
- #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */
-/* ========================================================= TFPCR ========================================================= */
- #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */
- #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */
-/* ========================================================= EIER ========================================================== */
- #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */
- #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */
- #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */
- #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */
- #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */
- #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */
- #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */
- #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */
- #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */
-/* ========================================================= EIFR ========================================================== */
- #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */
- #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */
- #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */
- #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */
- #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */
- #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */
- #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */
- #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */
- #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */
- #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */
-/* ========================================================= RECR ========================================================== */
- #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */
- #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */
-/* ========================================================= TECR ========================================================== */
- #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */
- #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */
-/* ========================================================= ECSR ========================================================== */
- #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */
- #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */
- #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */
- #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */
- #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */
- #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */
- #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */
- #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */
- #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */
- #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */
-/* ========================================================= CSSR ========================================================== */
- #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */
- #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */
-/* ========================================================= MSSR ========================================================== */
- #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */
- #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */
- #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */
- #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */
-/* ========================================================= MSMR ========================================================== */
- #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */
- #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */
-/* ========================================================== TSR ========================================================== */
- #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */
- #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */
-/* ========================================================= AFSR ========================================================== */
- #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */
- #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */
-/* ========================================================== TCR ========================================================== */
- #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */
- #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */
- #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */
- #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_CANFD ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CFDGCFG ======================================================== */
- #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */
- #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */
- #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */
- #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */
- #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */
- #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */
- #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */
- #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */
- #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */
- #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */
- #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */
-/* ======================================================== CFDGCTR ======================================================== */
- #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */
- #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */
- #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */
- #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */
- #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */
- #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */
- #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */
- #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */
- #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */
- #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */
- #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */
-/* ======================================================== CFDGSTS ======================================================== */
- #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */
- #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */
- #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */
- #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */
- #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGERFL ======================================================== */
- #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */
- #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */
- #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */
- #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */
- #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */
- #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */
- #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */
- #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */
- #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */
- #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */
- #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */
- #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */
-/* ======================================================== CFDGTSC ======================================================== */
- #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */
- #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */
-/* ====================================================== CFDGAFLECTR ====================================================== */
- #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */
- #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */
- #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDGAFLCFG0 ====================================================== */
- #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */
- #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */
- #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */
- #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */
-/* ======================================================== CFDRMNB ======================================================== */
- #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */
- #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */
- #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */
-/* ======================================================= CFDRMND0 ======================================================== */
- #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */
- #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== CFDRFCC ======================================================== */
- #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */
- #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */
- #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */
- #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */
- #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */
- #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */
- #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */
- #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDRFSTS ======================================================== */
- #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */
- #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */
- #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */
- #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */
- #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */
- #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */
- #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDRFPCTR ======================================================= */
- #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */
- #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */
-/* ======================================================== CFDCFCC ======================================================== */
- #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */
- #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */
- #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */
- #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */
- #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */
- #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */
- #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */
- #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */
- #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */
- #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */
- #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */
- #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */
- #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDCFCCE ======================================================== */
- #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */
- #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */
- #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */
- #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */
- #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */
- #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDCFSTS ======================================================== */
- #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */
- #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */
- #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */
- #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */
- #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */
- #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */
- #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */
- #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */
- #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */
- #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */
- #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDCFPCTR ======================================================= */
- #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */
- #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDFESTS ======================================================== */
- #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */
- #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */
- #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */
-/* ======================================================= CFDFFSTS ======================================================== */
- #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */
- #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */
- #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */
-/* ======================================================= CFDFMSTS ======================================================== */
- #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */
- #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */
- #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */
-/* ======================================================= CFDRFISTS ======================================================= */
- #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */
- #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */
- #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDCFRISTS ======================================================= */
- #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */
- #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */
-/* ====================================================== CFDCFTISTS ======================================================= */
- #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */
- #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */
-/* ===================================================== CFDCFOFRISTS ====================================================== */
- #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */
- #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */
-/* ===================================================== CFDCFOFTISTS ====================================================== */
- #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */
- #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */
-/* ====================================================== CFDCFMOWSTS ====================================================== */
- #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */
- #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */
-/* ======================================================= CFDFFFSTS ======================================================= */
- #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */
- #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */
- #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */
- #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */
-/* ======================================================== CFDTMC ========================================================= */
- #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */
- #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */
- #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */
- #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDTMSTS ======================================================== */
- #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */
- #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */
- #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */
- #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */
- #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTMTRSTS ======================================================= */
- #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */
- #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDTMTARSTS ====================================================== */
- #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */
- #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDTMTCSTS ======================================================= */
- #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */
- #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDTMTASTS ======================================================= */
- #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */
- #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTMIEC ======================================================== */
- #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */
- #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTXQCC0 ======================================================= */
- #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
- #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
- #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
- #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
- #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
- #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
- #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
- #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
- #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQSTS0 ======================================================= */
- #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
- #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
- #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
- #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
- #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
- #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
- #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
- #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
- #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
- #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQPCTR0 ====================================================== */
- #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
- #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTXQCC1 ======================================================= */
- #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
- #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
- #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
- #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
- #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
- #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
- #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
- #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
- #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQSTS1 ======================================================= */
- #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
- #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
- #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
- #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
- #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
- #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
- #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
- #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
- #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
- #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQPCTR1 ====================================================== */
- #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
- #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTXQCC2 ======================================================= */
- #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
- #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */
- #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
- #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
- #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
- #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */
- #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */
- #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
- #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQSTS2 ======================================================= */
- #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
- #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
- #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
- #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
- #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
- #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */
- #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */
- #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
- #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */
- #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQPCTR2 ====================================================== */
- #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
- #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTXQCC3 ======================================================= */
- #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
- #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
- #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
- #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
- #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */
- #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */
- #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQSTS3 ======================================================= */
- #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
- #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
- #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
- #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
- #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
- #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */
- #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTXQPCTR3 ====================================================== */
- #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
- #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDTXQESTS ======================================================= */
- #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */
- #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */
-/* ====================================================== CFDTXQFISTS ====================================================== */
- #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */
- #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */
- #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */
-/* ====================================================== CFDTXQMSTS ======================================================= */
- #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */
- #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */
- #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */
-/* ====================================================== CFDTXQISTS ======================================================= */
- #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */
- #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */
- #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */
-/* ===================================================== CFDTXQOFTISTS ===================================================== */
- #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */
- #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */
- #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */
-/* ===================================================== CFDTXQOFRISTS ===================================================== */
- #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */
- #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */
- #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */
-/* ====================================================== CFDTXQFSTS ======================================================= */
- #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */
- #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */
- #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */
- #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */
-/* ======================================================= CFDTHLCC ======================================================== */
- #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */
- #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */
- #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */
- #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */
- #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */
- #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDTHLSTS ======================================================= */
- #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */
- #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */
- #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */
- #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */
- #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */
- #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */
-/* ====================================================== CFDTHLPCTR ======================================================= */
- #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */
- #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */
-/* ===================================================== CFDGTINTSTS0 ====================================================== */
- #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */
- #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */
- #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */
- #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */
- #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */
- #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */
- #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */
- #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */
- #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */
- #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */
- #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */
- #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */
- #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */
- #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */
- #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDGTSTCFG ======================================================= */
- #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */
- #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */
- #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */
- #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */
-/* ====================================================== CFDGTSTCTR ======================================================= */
- #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */
- #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */
- #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGFDCFG ======================================================= */
- #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */
- #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */
- #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */
-/* ====================================================== CFDGCRCCFG ======================================================= */
- #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */
- #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGLOCKK ======================================================= */
- #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
- #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */
-/* ======================================================= CFDGLOTB ======================================================== */
- #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */
- #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */
- #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */
- #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */
- #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */
- #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */
-/* ===================================================== CFDGAFLIGNENT ===================================================== */
- #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */
- #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */
- #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */
- #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */
-/* ===================================================== CFDGAFLIGNCTR ===================================================== */
- #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */
- #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDCDTCT ======================================================== */
- #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */
- #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */
- #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */
- #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */
- #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */
- #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */
- #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */
- #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */
- #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */
- #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */
- #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDCDTSTS ======================================================= */
- #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */
- #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */
- #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */
- #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDCDTTCT ======================================================= */
- #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */
- #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */
- #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */
- #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */
- #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */
- #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */
- #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDCDTTSTS ======================================================= */
- #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */
- #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */
- #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */
- #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */
- #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */
- #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */
- #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDGRINTSTS ====================================================== */
- #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */
- #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */
- #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */
- #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */
- #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */
- #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */
- #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */
-/* ======================================================= CFDGRSTC ======================================================== */
- #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */
- #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
- #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDRPGACC ======================================================= */
- #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
- #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_CANFDL ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CFDGCFG ======================================================== */
- #define R_CANFDL_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */
- #define R_CANFDL_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */
- #define R_CANFDL_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */
- #define R_CANFDL_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */
- #define R_CANFDL_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */
- #define R_CANFDL_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */
- #define R_CANFDL_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */
- #define R_CANFDL_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */
- #define R_CANFDL_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */
- #define R_CANFDL_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */
- #define R_CANFDL_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */
-/* ======================================================== CFDGCTR ======================================================== */
- #define R_CANFDL_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */
- #define R_CANFDL_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */
- #define R_CANFDL_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */
- #define R_CANFDL_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */
- #define R_CANFDL_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */
- #define R_CANFDL_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */
- #define R_CANFDL_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */
- #define R_CANFDL_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */
-/* ======================================================== CFDGSTS ======================================================== */
- #define R_CANFDL_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */
- #define R_CANFDL_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */
- #define R_CANFDL_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */
- #define R_CANFDL_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */
- #define R_CANFDL_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGERFL ======================================================== */
- #define R_CANFDL_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */
- #define R_CANFDL_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */
- #define R_CANFDL_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */
- #define R_CANFDL_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */
- #define R_CANFDL_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */
- #define R_CANFDL_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */
-/* ======================================================== CFDGTSC ======================================================== */
- #define R_CANFDL_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */
- #define R_CANFDL_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */
-/* ====================================================== CFDGAFLECTR ====================================================== */
- #define R_CANFDL_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */
- #define R_CANFDL_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */
- #define R_CANFDL_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */
- #define R_CANFDL_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDGAFLCFG0 ====================================================== */
- #define R_CANFDL_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */
- #define R_CANFDL_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */
- #define R_CANFDL_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */
- #define R_CANFDL_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */
-/* ======================================================== CFDRMNB ======================================================== */
- #define R_CANFDL_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */
- #define R_CANFDL_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */
- #define R_CANFDL_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */
- #define R_CANFDL_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */
-/* ======================================================= CFDRMND0 ======================================================== */
- #define R_CANFDL_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */
- #define R_CANFDL_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= CFDRMIEC ======================================================== */
- #define R_CANFDL_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */
- #define R_CANFDL_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== CFDRFCC ======================================================== */
- #define R_CANFDL_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */
- #define R_CANFDL_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */
- #define R_CANFDL_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */
- #define R_CANFDL_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */
- #define R_CANFDL_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */
- #define R_CANFDL_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */
- #define R_CANFDL_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */
-/* ======================================================= CFDRFSTS ======================================================== */
- #define R_CANFDL_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */
- #define R_CANFDL_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */
- #define R_CANFDL_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */
- #define R_CANFDL_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */
- #define R_CANFDL_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */
- #define R_CANFDL_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDRFPCTR ======================================================= */
- #define R_CANFDL_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */
- #define R_CANFDL_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */
-/* ======================================================== CFDCFCC ======================================================== */
- #define R_CANFDL_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */
- #define R_CANFDL_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */
- #define R_CANFDL_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */
- #define R_CANFDL_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */
- #define R_CANFDL_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */
- #define R_CANFDL_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */
- #define R_CANFDL_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */
- #define R_CANFDL_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */
- #define R_CANFDL_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */
- #define R_CANFDL_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */
- #define R_CANFDL_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */
- #define R_CANFDL_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */
- #define R_CANFDL_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */
- #define R_CANFDL_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */
- #define R_CANFDL_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDCFSTS ======================================================== */
- #define R_CANFDL_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */
- #define R_CANFDL_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */
- #define R_CANFDL_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */
- #define R_CANFDL_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */
- #define R_CANFDL_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */
- #define R_CANFDL_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */
- #define R_CANFDL_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDCFPCTR ======================================================= */
- #define R_CANFDL_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */
- #define R_CANFDL_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDFESTS ======================================================== */
- #define R_CANFDL_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */
- #define R_CANFDL_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */
- #define R_CANFDL_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDFFSTS ======================================================== */
- #define R_CANFDL_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */
- #define R_CANFDL_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */
- #define R_CANFDL_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDFMSTS ======================================================== */
- #define R_CANFDL_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */
- #define R_CANFDL_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */
- #define R_CANFDL_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDRFISTS ======================================================= */
- #define R_CANFDL_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */
- #define R_CANFDL_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */
-/* ======================================================== CFDTMC ========================================================= */
- #define R_CANFDL_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */
- #define R_CANFDL_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */
- #define R_CANFDL_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */
- #define R_CANFDL_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDTMSTS ======================================================== */
- #define R_CANFDL_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */
- #define R_CANFDL_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */
- #define R_CANFDL_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */
- #define R_CANFDL_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */
- #define R_CANFDL_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */
- #define R_CANFDL_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDTMTRSTS ======================================================= */
- #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */
- #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */
-/* ====================================================== CFDTMTARSTS ====================================================== */
- #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */
- #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */
-/* ====================================================== CFDTMTCSTS ======================================================= */
- #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */
- #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */
-/* ====================================================== CFDTMTASTS ======================================================= */
- #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */
- #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */
-/* ======================================================= CFDTMIEC ======================================================== */
- #define R_CANFDL_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */
- #define R_CANFDL_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */
-/* ======================================================= CFDTXQCC0 ======================================================= */
- #define R_CANFDL_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
- #define R_CANFDL_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
- #define R_CANFDL_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
- #define R_CANFDL_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
- #define R_CANFDL_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */
-/* ====================================================== CFDTXQSTS0 ======================================================= */
- #define R_CANFDL_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
- #define R_CANFDL_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
- #define R_CANFDL_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
- #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
- #define R_CANFDL_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
-/* ====================================================== CFDTXQPCTR0 ====================================================== */
- #define R_CANFDL_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
- #define R_CANFDL_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDTHLCC ======================================================== */
- #define R_CANFDL_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */
- #define R_CANFDL_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */
- #define R_CANFDL_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */
- #define R_CANFDL_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */
- #define R_CANFDL_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDTHLSTS ======================================================= */
- #define R_CANFDL_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */
- #define R_CANFDL_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */
- #define R_CANFDL_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */
- #define R_CANFDL_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */
- #define R_CANFDL_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */
- #define R_CANFDL_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */
-/* ====================================================== CFDTHLPCTR ======================================================= */
- #define R_CANFDL_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */
- #define R_CANFDL_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */
-/* ===================================================== CFDGTINTSTS0 ====================================================== */
- #define R_CANFDL_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */
- #define R_CANFDL_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */
- #define R_CANFDL_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */
- #define R_CANFDL_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */
- #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */
- #define R_CANFDL_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */
-/* ====================================================== CFDGTSTCFG ======================================================= */
- #define R_CANFDL_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */
- #define R_CANFDL_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */
-/* ====================================================== CFDGTSTCTR ======================================================= */
- #define R_CANFDL_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */
- #define R_CANFDL_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGFDCFG ======================================================= */
- #define R_CANFDL_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */
- #define R_CANFDL_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */
- #define R_CANFDL_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */
-/* ======================================================= CFDGLOCKK ======================================================= */
- #define R_CANFDL_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
- #define R_CANFDL_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */
-/* ===================================================== CFDGAFLIGNENT ===================================================== */
- #define R_CANFDL_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */
- #define R_CANFDL_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */
-/* ===================================================== CFDGAFLIGNCTR ===================================================== */
- #define R_CANFDL_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */
- #define R_CANFDL_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_CANFDL_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDCDTCT ======================================================== */
- #define R_CANFDL_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */
- #define R_CANFDL_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */
- #define R_CANFDL_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */
- #define R_CANFDL_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDCDTSTS ======================================================= */
- #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */
- #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */
- #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */
- #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
-/* ======================================================= CFDGRSTC ======================================================== */
- #define R_CANFDL_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */
- #define R_CANFDL_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
- #define R_CANFDL_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_CANFDL_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ======================================================= CFDRPGACC ======================================================= */
- #define R_CANFDL_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
- #define R_CANFDL_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_CRC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CRCCR0 ========================================================= */
- #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */
- #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */
- #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */
- #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */
- #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */
- #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */
-/* ======================================================== CRCCR1 ========================================================= */
- #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */
- #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */
- #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */
- #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */
-/* ======================================================== CRCDIR ========================================================= */
- #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */
- #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= CRCDIR_BY ======================================================= */
- #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */
- #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */
-/* ======================================================== CRCDOR ========================================================= */
- #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */
- #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= CRCDOR_HA ======================================================= */
- #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */
- #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */
-/* ======================================================= CRCDOR_BY ======================================================= */
- #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */
- #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */
-/* ======================================================== CRCSAR ========================================================= */
- #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */
- #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSU ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CTSUCR0 ======================================================== */
- #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */
- #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */
- #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */
- #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */
- #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */
- #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */
- #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */
-/* ======================================================== CTSUCR1 ======================================================== */
- #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */
- #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */
- #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */
- #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */
- #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */
- #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */
- #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUSDPRS ======================================================= */
- #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */
- #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */
- #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */
- #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */
-/* ======================================================== CTSUSST ======================================================== */
- #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */
- #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */
-/* ======================================================= CTSUMCH0 ======================================================== */
- #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */
- #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */
-/* ======================================================= CTSUMCH1 ======================================================== */
- #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */
- #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */
-/* ======================================================= CTSUCHAC ======================================================== */
- #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */
- #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUCHTRC ======================================================= */
- #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */
- #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUDCLKC ======================================================= */
- #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */
- #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */
- #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */
-/* ======================================================== CTSUST ========================================================= */
- #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */
- #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */
- #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */
- #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */
- #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */
- #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */
-/* ======================================================== CTSUSSC ======================================================== */
- #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */
- #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */
-/* ======================================================== CTSUSO0 ======================================================== */
- #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */
- #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */
- #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */
- #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */
-/* ======================================================== CTSUSO1 ======================================================== */
- #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */
- #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */
- #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */
- #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */
- #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */
-/* ======================================================== CTSUSC ========================================================= */
- #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */
- #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */
-/* ======================================================== CTSURC ========================================================= */
- #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */
- #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */
-/* ======================================================= CTSUERRS ======================================================== */
- #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */
- #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */
- #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */
- #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */
- #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */
- #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */
- #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */
- #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */
- #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUTRMR ======================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSU2 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CTSUCRA ======================================================== */
- #define R_CTSU2_CTSUCRA_STRT_Pos (0UL) /*!< STRT (Bit 0) */
- #define R_CTSU2_CTSUCRA_STRT_Msk (0x1UL) /*!< STRT (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_CAP_Pos (1UL) /*!< CAP (Bit 1) */
- #define R_CTSU2_CTSUCRA_CAP_Msk (0x2UL) /*!< CAP (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_SNZ_Pos (2UL) /*!< SNZ (Bit 2) */
- #define R_CTSU2_CTSUCRA_SNZ_Msk (0x4UL) /*!< SNZ (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_CFCON_Pos (3UL) /*!< CFCON (Bit 3) */
- #define R_CTSU2_CTSUCRA_CFCON_Msk (0x8UL) /*!< CFCON (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_INIT_Pos (4UL) /*!< INIT (Bit 4) */
- #define R_CTSU2_CTSUCRA_INIT_Msk (0x10UL) /*!< INIT (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_PUMPON_Pos (5UL) /*!< PUMPON (Bit 5) */
- #define R_CTSU2_CTSUCRA_PUMPON_Msk (0x20UL) /*!< PUMPON (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_TXVSEL_Pos (6UL) /*!< TXVSEL (Bit 6) */
- #define R_CTSU2_CTSUCRA_TXVSEL_Msk (0xc0UL) /*!< TXVSEL (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCRA_PON_Pos (8UL) /*!< PON (Bit 8) */
- #define R_CTSU2_CTSUCRA_PON_Msk (0x100UL) /*!< PON (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_CSW_Pos (9UL) /*!< CSW (Bit 9) */
- #define R_CTSU2_CTSUCRA_CSW_Msk (0x200UL) /*!< CSW (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_ATUNE0_Pos (10UL) /*!< ATUNE0 (Bit 10) */
- #define R_CTSU2_CTSUCRA_ATUNE0_Msk (0x400UL) /*!< ATUNE0 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_ATUNE1_Pos (11UL) /*!< ATUNE1 (Bit 11) */
- #define R_CTSU2_CTSUCRA_ATUNE1_Msk (0x800UL) /*!< ATUNE1 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_CLK_Pos (12UL) /*!< CLK (Bit 12) */
- #define R_CTSU2_CTSUCRA_CLK_Msk (0x3000UL) /*!< CLK (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCRA_MD0_Pos (14UL) /*!< MD0 (Bit 14) */
- #define R_CTSU2_CTSUCRA_MD0_Msk (0x4000UL) /*!< MD0 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_MD1_Pos (15UL) /*!< MD1 (Bit 15) */
- #define R_CTSU2_CTSUCRA_MD1_Msk (0x8000UL) /*!< MD1 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_MD2_Pos (16UL) /*!< MD2 (Bit 16) */
- #define R_CTSU2_CTSUCRA_MD2_Msk (0x10000UL) /*!< MD2 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_ATUNE2_Pos (17UL) /*!< ATUNE2 (Bit 17) */
- #define R_CTSU2_CTSUCRA_ATUNE2_Msk (0x20000UL) /*!< ATUNE2 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_LOAD_Pos (18UL) /*!< LOAD (Bit 18) */
- #define R_CTSU2_CTSUCRA_LOAD_Msk (0xc0000UL) /*!< LOAD (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCRA_POSEL_Pos (20UL) /*!< POSEL (Bit 20) */
- #define R_CTSU2_CTSUCRA_POSEL_Msk (0x300000UL) /*!< POSEL (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCRA_SDPSEL_Pos (22UL) /*!< SDPSEL (Bit 22) */
- #define R_CTSU2_CTSUCRA_SDPSEL_Msk (0x400000UL) /*!< SDPSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_PCSEL_Pos (23UL) /*!< PCSEL (Bit 23) */
- #define R_CTSU2_CTSUCRA_PCSEL_Msk (0x800000UL) /*!< PCSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_STCLK_Pos (24UL) /*!< STCLK (Bit 24) */
- #define R_CTSU2_CTSUCRA_STCLK_Msk (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f) */
- #define R_CTSU2_CTSUCRA_DCMODE_Pos (30UL) /*!< DCMODE (Bit 30) */
- #define R_CTSU2_CTSUCRA_DCMODE_Msk (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRA_DCBACK_Pos (31UL) /*!< DCBACK (Bit 31) */
- #define R_CTSU2_CTSUCRA_DCBACK_Msk (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUCRAL ======================================================== */
-/* ======================================================== CTSUCR0 ======================================================== */
-/* ======================================================== CTSUCR1 ======================================================== */
-/* ======================================================= CTSUCRAH ======================================================== */
-/* ======================================================== CTSUCR2 ======================================================== */
-/* ======================================================== CTSUCR3 ======================================================== */
-/* ======================================================== CTSUCRB ======================================================== */
- #define R_CTSU2_CTSUCRB_PRRATIO_Pos (0UL) /*!< PRRATIO (Bit 0) */
- #define R_CTSU2_CTSUCRB_PRRATIO_Msk (0xfUL) /*!< PRRATIO (Bitfield-Mask: 0x0f) */
- #define R_CTSU2_CTSUCRB_PRMODE_Pos (4UL) /*!< PRMODE (Bit 4) */
- #define R_CTSU2_CTSUCRB_PRMODE_Msk (0x30UL) /*!< PRMODE (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCRB_SOFF_Pos (6UL) /*!< SOFF (Bit 6) */
- #define R_CTSU2_CTSUCRB_SOFF_Msk (0x40UL) /*!< SOFF (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRB_PROFF_Pos (7UL) /*!< PROFF (Bit 7) */
- #define R_CTSU2_CTSUCRB_PROFF_Msk (0x80UL) /*!< PROFF (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCRB_SST_Pos (8UL) /*!< SST (Bit 8) */
- #define R_CTSU2_CTSUCRB_SST_Msk (0xff00UL) /*!< SST (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUCRB_SSMOD_Pos (24UL) /*!< SSMOD (Bit 24) */
- #define R_CTSU2_CTSUCRB_SSMOD_Msk (0x7000000UL) /*!< SSMOD (Bitfield-Mask: 0x07) */
- #define R_CTSU2_CTSUCRB_SSCNT_Pos (28UL) /*!< SSCNT (Bit 28) */
- #define R_CTSU2_CTSUCRB_SSCNT_Msk (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03) */
-/* ======================================================= CTSUCRBL ======================================================== */
-/* ======================================================= CTSUSDPRS ======================================================= */
-/* ======================================================== CTSUSST ======================================================== */
-/* ======================================================= CTSUCRBH ======================================================== */
-/* ======================================================= CTSUDCLKC ======================================================= */
-/* ======================================================== CTSUMCH ======================================================== */
- #define R_CTSU2_CTSUMCH_MCH0_Pos (0UL) /*!< MCH0 (Bit 0) */
- #define R_CTSU2_CTSUMCH_MCH0_Msk (0x3fUL) /*!< MCH0 (Bitfield-Mask: 0x3f) */
- #define R_CTSU2_CTSUMCH_MCH1_Pos (8UL) /*!< MCH1 (Bit 8) */
- #define R_CTSU2_CTSUMCH_MCH1_Msk (0x3f00UL) /*!< MCH1 (Bitfield-Mask: 0x3f) */
- #define R_CTSU2_CTSUMCH_MCA0_Pos (16UL) /*!< MCA0 (Bit 16) */
- #define R_CTSU2_CTSUMCH_MCA0_Msk (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUMCH_MCA1_Pos (17UL) /*!< MCA1 (Bit 17) */
- #define R_CTSU2_CTSUMCH_MCA1_Msk (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUMCH_MCA2_Pos (18UL) /*!< MCA2 (Bit 18) */
- #define R_CTSU2_CTSUMCH_MCA2_Msk (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUMCH_MCA3_Pos (19UL) /*!< MCA3 (Bit 19) */
- #define R_CTSU2_CTSUMCH_MCA3_Msk (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUMCHL ======================================================== */
-/* ======================================================= CTSUMCH0 ======================================================== */
-/* ======================================================= CTSUMCH1 ======================================================== */
-/* ======================================================= CTSUMCHH ======================================================== */
-/* ======================================================= CTSUMFAF ======================================================== */
-/* ======================================================= CTSUCHACA ======================================================= */
- #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */
- #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */
- #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */
- #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */
- #define R_CTSU2_CTSUCHACA_CHAC05_Msk (0x20UL) /*!< CHAC05 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC06_Pos (6UL) /*!< CHAC06 (Bit 6) */
- #define R_CTSU2_CTSUCHACA_CHAC06_Msk (0x40UL) /*!< CHAC06 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC07_Pos (7UL) /*!< CHAC07 (Bit 7) */
- #define R_CTSU2_CTSUCHACA_CHAC07_Msk (0x80UL) /*!< CHAC07 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC08_Pos (8UL) /*!< CHAC08 (Bit 8) */
- #define R_CTSU2_CTSUCHACA_CHAC08_Msk (0x100UL) /*!< CHAC08 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC09_Pos (9UL) /*!< CHAC09 (Bit 9) */
- #define R_CTSU2_CTSUCHACA_CHAC09_Msk (0x200UL) /*!< CHAC09 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC10_Pos (10UL) /*!< CHAC10 (Bit 10) */
- #define R_CTSU2_CTSUCHACA_CHAC10_Msk (0x400UL) /*!< CHAC10 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC11_Pos (11UL) /*!< CHAC11 (Bit 11) */
- #define R_CTSU2_CTSUCHACA_CHAC11_Msk (0x800UL) /*!< CHAC11 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC12_Pos (12UL) /*!< CHAC12 (Bit 12) */
- #define R_CTSU2_CTSUCHACA_CHAC12_Msk (0x1000UL) /*!< CHAC12 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC13_Pos (13UL) /*!< CHAC13 (Bit 13) */
- #define R_CTSU2_CTSUCHACA_CHAC13_Msk (0x2000UL) /*!< CHAC13 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC14_Pos (14UL) /*!< CHAC14 (Bit 14) */
- #define R_CTSU2_CTSUCHACA_CHAC14_Msk (0x4000UL) /*!< CHAC14 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC15_Pos (15UL) /*!< CHAC15 (Bit 15) */
- #define R_CTSU2_CTSUCHACA_CHAC15_Msk (0x8000UL) /*!< CHAC15 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC16_Pos (16UL) /*!< CHAC16 (Bit 16) */
- #define R_CTSU2_CTSUCHACA_CHAC16_Msk (0x10000UL) /*!< CHAC16 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC17_Pos (17UL) /*!< CHAC17 (Bit 17) */
- #define R_CTSU2_CTSUCHACA_CHAC17_Msk (0x20000UL) /*!< CHAC17 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC18_Pos (18UL) /*!< CHAC18 (Bit 18) */
- #define R_CTSU2_CTSUCHACA_CHAC18_Msk (0x40000UL) /*!< CHAC18 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC21_Pos (21UL) /*!< CHAC21 (Bit 21) */
- #define R_CTSU2_CTSUCHACA_CHAC21_Msk (0x200000UL) /*!< CHAC21 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC22_Pos (22UL) /*!< CHAC22 (Bit 22) */
- #define R_CTSU2_CTSUCHACA_CHAC22_Msk (0x400000UL) /*!< CHAC22 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC23_Pos (23UL) /*!< CHAC23 (Bit 23) */
- #define R_CTSU2_CTSUCHACA_CHAC23_Msk (0x800000UL) /*!< CHAC23 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC24_Pos (24UL) /*!< CHAC24 (Bit 24) */
- #define R_CTSU2_CTSUCHACA_CHAC24_Msk (0x1000000UL) /*!< CHAC24 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC25_Pos (25UL) /*!< CHAC25 (Bit 25) */
- #define R_CTSU2_CTSUCHACA_CHAC25_Msk (0x2000000UL) /*!< CHAC25 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC26_Pos (26UL) /*!< CHAC26 (Bit 26) */
- #define R_CTSU2_CTSUCHACA_CHAC26_Msk (0x4000000UL) /*!< CHAC26 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC27_Pos (27UL) /*!< CHAC27 (Bit 27) */
- #define R_CTSU2_CTSUCHACA_CHAC27_Msk (0x8000000UL) /*!< CHAC27 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC28_Pos (28UL) /*!< CHAC28 (Bit 28) */
- #define R_CTSU2_CTSUCHACA_CHAC28_Msk (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC29_Pos (29UL) /*!< CHAC29 (Bit 29) */
- #define R_CTSU2_CTSUCHACA_CHAC29_Msk (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC30_Pos (30UL) /*!< CHAC30 (Bit 30) */
- #define R_CTSU2_CTSUCHACA_CHAC30_Msk (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACA_CHAC31_Pos (31UL) /*!< CHAC31 (Bit 31) */
- #define R_CTSU2_CTSUCHACA_CHAC31_Msk (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01) */
-/* ====================================================== CTSUCHACAL ======================================================= */
-/* ======================================================= CTSUCHAC0 ======================================================= */
-/* ======================================================= CTSUCHAC1 ======================================================= */
-/* ====================================================== CTSUCHACAH ======================================================= */
-/* ======================================================= CTSUCHAC2 ======================================================= */
-/* ======================================================= CTSUCHAC3 ======================================================= */
-/* ======================================================= CTSUCHACB ======================================================= */
- #define R_CTSU2_CTSUCHACB_CHAC32_Pos (0UL) /*!< CHAC32 (Bit 0) */
- #define R_CTSU2_CTSUCHACB_CHAC32_Msk (0x1UL) /*!< CHAC32 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACB_CHAC33_Pos (1UL) /*!< CHAC33 (Bit 1) */
- #define R_CTSU2_CTSUCHACB_CHAC33_Msk (0x2UL) /*!< CHAC33 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACB_CHAC34_Pos (2UL) /*!< CHAC34 (Bit 2) */
- #define R_CTSU2_CTSUCHACB_CHAC34_Msk (0x4UL) /*!< CHAC34 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHACB_CHAC35_Pos (3UL) /*!< CHAC35 (Bit 3) */
- #define R_CTSU2_CTSUCHACB_CHAC35_Msk (0x8UL) /*!< CHAC35 (Bitfield-Mask: 0x01) */
-/* ====================================================== CTSUCHACBL ======================================================= */
-/* ======================================================= CTSUCHAC4 ======================================================= */
-/* ====================================================== CTSUCHTRCA ======================================================= */
- #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk (0x20UL) /*!< CHTRC05 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos (6UL) /*!< CHTRC06 (Bit 6) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk (0x40UL) /*!< CHTRC06 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos (7UL) /*!< CHTRC07 (Bit 7) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk (0x80UL) /*!< CHTRC07 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos (8UL) /*!< CHTRC08 (Bit 8) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk (0x100UL) /*!< CHTRC08 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos (9UL) /*!< CHTRC09 (Bit 9) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk (0x200UL) /*!< CHTRC09 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos (10UL) /*!< CHTRC10 (Bit 10) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk (0x400UL) /*!< CHTRC10 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos (11UL) /*!< CHTRC11 (Bit 11) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk (0x800UL) /*!< CHTRC11 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos (12UL) /*!< CHTRC12 (Bit 12) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk (0x1000UL) /*!< CHTRC12 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos (13UL) /*!< CHTRC13 (Bit 13) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk (0x2000UL) /*!< CHTRC13 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos (14UL) /*!< CHTRC14 (Bit 14) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk (0x4000UL) /*!< CHTRC14 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos (15UL) /*!< CHTRC15 (Bit 15) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk (0x8000UL) /*!< CHTRC15 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos (16UL) /*!< CHTRC16 (Bit 16) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk (0x10000UL) /*!< CHTRC16 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos (17UL) /*!< CHTRC17 (Bit 17) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk (0x20000UL) /*!< CHTRC17 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos (18UL) /*!< CHTRC18 (Bit 18) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk (0x40000UL) /*!< CHTRC18 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos (21UL) /*!< CHTRC21 (Bit 21) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk (0x200000UL) /*!< CHTRC21 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos (22UL) /*!< CHTRC22 (Bit 22) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk (0x400000UL) /*!< CHTRC22 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos (23UL) /*!< CHTRC23 (Bit 23) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk (0x800000UL) /*!< CHTRC23 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos (24UL) /*!< CHTRC24 (Bit 24) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk (0x1000000UL) /*!< CHTRC24 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos (25UL) /*!< CHTRC25 (Bit 25) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk (0x2000000UL) /*!< CHTRC25 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos (26UL) /*!< CHTRC26 (Bit 26) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk (0x4000000UL) /*!< CHTRC26 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos (27UL) /*!< CHTRC27 (Bit 27) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk (0x8000000UL) /*!< CHTRC27 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos (28UL) /*!< CHTRC28 (Bit 28) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos (29UL) /*!< CHTRC29 (Bit 29) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos (30UL) /*!< CHTRC30 (Bit 30) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos (31UL) /*!< CHTRC31 (Bit 31) */
- #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01) */
-/* ====================================================== CTSUCHTRCAL ====================================================== */
-/* ====================================================== CTSUCHTRC0 ======================================================= */
-/* ====================================================== CTSUCHTRC1 ======================================================= */
-/* ====================================================== CTSUCHTRCAH ====================================================== */
-/* ====================================================== CTSUCHTRC2 ======================================================= */
-/* ====================================================== CTSUCHTRC3 ======================================================= */
-/* ====================================================== CTSUCHTRCB ======================================================= */
- #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos (0UL) /*!< CHTRC32 (Bit 0) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk (0x1UL) /*!< CHTRC32 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos (1UL) /*!< CHTRC33 (Bit 1) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk (0x2UL) /*!< CHTRC33 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos (2UL) /*!< CHTRC34 (Bit 2) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk (0x4UL) /*!< CHTRC34 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos (3UL) /*!< CHTRC35 (Bit 3) */
- #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk (0x8UL) /*!< CHTRC35 (Bitfield-Mask: 0x01) */
-/* ====================================================== CTSUCHTRCBL ====================================================== */
-/* ====================================================== CTSUCHTRC4 ======================================================= */
-/* ======================================================== CTSUSR ========================================================= */
- #define R_CTSU2_CTSUSR_MFC_Pos (0UL) /*!< MFC (Bit 0) */
- #define R_CTSU2_CTSUSR_MFC_Msk (0x3UL) /*!< MFC (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUSR_ICOMPRST_Pos (5UL) /*!< ICOMPRST (Bit 5) */
- #define R_CTSU2_CTSUSR_ICOMPRST_Msk (0x20UL) /*!< ICOMPRST (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_ICOMP1_Pos (6UL) /*!< ICOMP1 (Bit 6) */
- #define R_CTSU2_CTSUSR_ICOMP1_Msk (0x40UL) /*!< ICOMP1 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_ICOMP0_Pos (7UL) /*!< ICOMP0 (Bit 7) */
- #define R_CTSU2_CTSUSR_ICOMP0_Msk (0x80UL) /*!< ICOMP0 (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_STC_Pos (8UL) /*!< STC (Bit 8) */
- #define R_CTSU2_CTSUSR_STC_Msk (0x700UL) /*!< STC (Bitfield-Mask: 0x07) */
- #define R_CTSU2_CTSUSR_DTSR_Pos (12UL) /*!< DTSR (Bit 12) */
- #define R_CTSU2_CTSUSR_DTSR_Msk (0x1000UL) /*!< DTSR (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_SENSOVF_Pos (13UL) /*!< SENSOVF (Bit 13) */
- #define R_CTSU2_CTSUSR_SENSOVF_Msk (0x2000UL) /*!< SENSOVF (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_SUOVF_Pos (14UL) /*!< SUOVF (Bit 14) */
- #define R_CTSU2_CTSUSR_SUOVF_Msk (0x4000UL) /*!< SUOVF (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_PS_Pos (15UL) /*!< PS (Bit 15) */
- #define R_CTSU2_CTSUSR_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUSR_CFCRDCH_Pos (16UL) /*!< CFCRDCH (Bit 16) */
- #define R_CTSU2_CTSUSR_CFCRDCH_Msk (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f) */
-/* ======================================================== CTSUSRL ======================================================== */
-/* ======================================================== CTSUSR0 ======================================================== */
-/* ======================================================== CTSUST ========================================================= */
-/* ======================================================== CTSUSRH ======================================================== */
-/* ======================================================== CTSUSR2 ======================================================== */
-/* ======================================================== CTSUSO ========================================================= */
- #define R_CTSU2_CTSUSO_SO_Pos (0UL) /*!< SO (Bit 0) */
- #define R_CTSU2_CTSUSO_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */
- #define R_CTSU2_CTSUSO_SNUM_Pos (10UL) /*!< SNUM (Bit 10) */
- #define R_CTSU2_CTSUSO_SNUM_Msk (0x3fc00UL) /*!< SNUM (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSO_SSDIV_Pos (20UL) /*!< SSDIV (Bit 20) */
- #define R_CTSU2_CTSUSO_SSDIV_Msk (0xf00000UL) /*!< SSDIV (Bitfield-Mask: 0x0f) */
- #define R_CTSU2_CTSUSO_SDPA_Pos (24UL) /*!< SDPA (Bit 24) */
- #define R_CTSU2_CTSUSO_SDPA_Msk (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff) */
-/* ======================================================== CTSUSO0 ======================================================== */
-/* ======================================================== CTSUSO1 ======================================================== */
-/* ======================================================= CTSUSCNT ======================================================== */
- #define R_CTSU2_CTSUSCNT_SENSCNT_Pos (0UL) /*!< SENSCNT (Bit 0) */
- #define R_CTSU2_CTSUSCNT_SENSCNT_Msk (0xffffUL) /*!< SENSCNT (Bitfield-Mask: 0xffff) */
- #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos (16UL) /*!< SUCKCNT (Bit 16) */
- #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff) */
-/* ======================================================== CTSUSC ========================================================= */
-/* ======================================================= CTSUCALIB ======================================================= */
- #define R_CTSU2_CTSUCALIB_TSOD_Pos (2UL) /*!< TSOD (Bit 2) */
- #define R_CTSU2_CTSUCALIB_TSOD_Msk (0x4UL) /*!< TSOD (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_DRV_Pos (3UL) /*!< DRV (Bit 3) */
- #define R_CTSU2_CTSUCALIB_DRV_Msk (0x8UL) /*!< DRV (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
- #define R_CTSU2_CTSUCALIB_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
- #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos (6UL) /*!< SUCLKEN (Bit 6) */
- #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk (0x40UL) /*!< SUCLKEN (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_TSOC_Pos (7UL) /*!< TSOC (Bit 7) */
- #define R_CTSU2_CTSUCALIB_TSOC_Msk (0x80UL) /*!< TSOC (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos (8UL) /*!< CNTRDSEL (Bit 8) */
- #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk (0x100UL) /*!< CNTRDSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_IOC_Pos (9UL) /*!< IOC (Bit 9) */
- #define R_CTSU2_CTSUCALIB_IOC_Msk (0x200UL) /*!< IOC (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos (10UL) /*!< CFCRDMD (Bit 10) */
- #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */
- #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CFCSEL_Pos (16UL) /*!< CFCSEL (Bit 16) */
- #define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */
- #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */
- #define R_CTSU2_CTSUCALIB_CFCMODE_Msk (0x400000UL) /*!< CFCMODE (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_DACMSEL_Pos (24UL) /*!< DACMSEL (Bit 24) */
- #define R_CTSU2_CTSUCALIB_DACMSEL_Msk (0x1000000UL) /*!< DACMSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_DACCARRY_Pos (25UL) /*!< DACCARRY (Bit 25) */
- #define R_CTSU2_CTSUCALIB_DACCARRY_Msk (0x2000000UL) /*!< DACCARRY (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_SUMSEL_Pos (26UL) /*!< SUMSEL (Bit 26) */
- #define R_CTSU2_CTSUCALIB_SUMSEL_Msk (0x4000000UL) /*!< SUMSEL (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_SUCARRY_Pos (27UL) /*!< SUCARRY (Bit 27) */
- #define R_CTSU2_CTSUCALIB_SUCARRY_Msk (0x8000000UL) /*!< SUCARRY (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_DACCLK_Pos (28UL) /*!< DACCLK (Bit 28) */
- #define R_CTSU2_CTSUCALIB_DACCLK_Msk (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CCOCLK_Pos (29UL) /*!< CCOCLK (Bit 29) */
- #define R_CTSU2_CTSUCALIB_CCOCLK_Msk (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos (30UL) /*!< CCOCALIB (Bit 30) */
- #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01) */
- #define R_CTSU2_CTSUCALIB_TXREV_Pos (31UL) /*!< TXREV (Bit 31) */
- #define R_CTSU2_CTSUCALIB_TXREV_Msk (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01) */
-/* ======================================================= CTSUDBGR0 ======================================================= */
-/* ======================================================= CTSUDBGR1 ======================================================= */
-/* ====================================================== CTSUSUCLKA ======================================================= */
- #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos (0UL) /*!< SUADJ0 (Bit 0) */
- #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk (0xffUL) /*!< SUADJ0 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos (8UL) /*!< SUMULTI0 (Bit 8) */
- #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk (0xff00UL) /*!< SUMULTI0 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos (16UL) /*!< SUADJ1 (Bit 16) */
- #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk (0xff0000UL) /*!< SUADJ1 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos (24UL) /*!< SUMULTI1 (Bit 24) */
- #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff) */
-/* ====================================================== CTSUSUCLK0 ======================================================= */
-/* ====================================================== CTSUSUCLK1 ======================================================= */
-/* ====================================================== CTSUSUCLKB ======================================================= */
- #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos (0UL) /*!< SUADJ2 (Bit 0) */
- #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk (0xffUL) /*!< SUADJ2 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos (8UL) /*!< SUMULTI2 (Bit 8) */
- #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk (0xff00UL) /*!< SUMULTI2 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos (16UL) /*!< SUADJ3 (Bit 16) */
- #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk (0xff0000UL) /*!< SUADJ3 (Bitfield-Mask: 0xff) */
- #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos (24UL) /*!< SUMULTI3 (Bit 24) */
- #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff) */
-/* ====================================================== CTSUSUCLK2 ======================================================= */
-/* ====================================================== CTSUSUCLK3 ======================================================= */
-/* ====================================================== CTSUCFCCNT ======================================================= */
- #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */
- #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */
-/* ====================================================== CTSUCFCCNTL ====================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_DAC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DACR ========================================================== */
- #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */
- #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */
- #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */
- #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */
-/* ========================================================= DADR ========================================================== */
- #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */
- #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */
-/* ========================================================= DADPR ========================================================= */
- #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */
- #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */
-/* ======================================================== DAADSCR ======================================================== */
- #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */
- #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */
-/* ======================================================= DAVREFCR ======================================================== */
- #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */
- #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */
-/* ========================================================= DAPC ========================================================== */
- #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */
- #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */
-/* ======================================================== DAAMPCR ======================================================== */
- #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */
- #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */
-/* ======================================================== DAASWCR ======================================================== */
- #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */
- #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */
- #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */
- #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */
-/* ======================================================== DAADUSR ======================================================== */
- #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */
- #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DAC8 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== DAM ========================================================== */
- #define R_DAC8_DAM_DACE1_Pos (5UL) /*!< DACE1 (Bit 5) */
- #define R_DAC8_DAM_DACE1_Msk (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01) */
- #define R_DAC8_DAM_DACE0_Pos (4UL) /*!< DACE0 (Bit 4) */
- #define R_DAC8_DAM_DACE0_Msk (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01) */
- #define R_DAC8_DAM_DAMD1_Pos (1UL) /*!< DAMD1 (Bit 1) */
- #define R_DAC8_DAM_DAMD1_Msk (0x2UL) /*!< DAMD1 (Bitfield-Mask: 0x01) */
- #define R_DAC8_DAM_DAMD0_Pos (0UL) /*!< DAMD0 (Bit 0) */
- #define R_DAC8_DAM_DAMD0_Msk (0x1UL) /*!< DAMD0 (Bitfield-Mask: 0x01) */
-/* ========================================================= DACS ========================================================== */
- #define R_DAC8_DACS_DACS_Pos (0UL) /*!< DACS (Bit 0) */
- #define R_DAC8_DACS_DACS_Msk (0xffUL) /*!< DACS (Bitfield-Mask: 0xff) */
-/* ======================================================= DACADSCR ======================================================== */
- #define R_DAC8_DACADSCR_DACADST_Pos (0UL) /*!< DACADST (Bit 0) */
- #define R_DAC8_DACADSCR_DACADST_Msk (0x1UL) /*!< DACADST (Bitfield-Mask: 0x01) */
-/* ========================================================= DACPC ========================================================= */
- #define R_DAC8_DACPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */
- #define R_DAC8_DACPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DALI0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== BTVTHR1 ======================================================== */
- #define R_DALI0_BTVTHR1_BTV2_Pos (8UL) /*!< BTV2 (Bit 8) */
- #define R_DALI0_BTVTHR1_BTV2_Msk (0xff00UL) /*!< BTV2 (Bitfield-Mask: 0xff) */
- #define R_DALI0_BTVTHR1_BTV1_Pos (0UL) /*!< BTV1 (Bit 0) */
- #define R_DALI0_BTVTHR1_BTV1_Msk (0x7fUL) /*!< BTV1 (Bitfield-Mask: 0x7f) */
-/* ======================================================== BTVTHR2 ======================================================== */
- #define R_DALI0_BTVTHR2_BTV4_Pos (8UL) /*!< BTV4 (Bit 8) */
- #define R_DALI0_BTVTHR2_BTV4_Msk (0xff00UL) /*!< BTV4 (Bitfield-Mask: 0xff) */
- #define R_DALI0_BTVTHR2_BTV3_Pos (0UL) /*!< BTV3 (Bit 0) */
- #define R_DALI0_BTVTHR2_BTV3_Msk (0xffUL) /*!< BTV3 (Bitfield-Mask: 0xff) */
-/* ======================================================== BTVTHR3 ======================================================== */
- #define R_DALI0_BTVTHR3_BTV5_Pos (0UL) /*!< BTV5 (Bit 0) */
- #define R_DALI0_BTVTHR3_BTV5_Msk (0xffUL) /*!< BTV5 (Bitfield-Mask: 0xff) */
-/* ======================================================== BTVTHR4 ======================================================== */
- #define R_DALI0_BTVTHR4_BTV6_Pos (0UL) /*!< BTV6 (Bit 0) */
- #define R_DALI0_BTVTHR4_BTV6_Msk (0x1ffUL) /*!< BTV6 (Bitfield-Mask: 0x1ff) */
-/* ======================================================== COLTHR1 ======================================================== */
- #define R_DALI0_COLTHR1_COL2_Pos (8UL) /*!< COL2 (Bit 8) */
- #define R_DALI0_COLTHR1_COL2_Msk (0x3f00UL) /*!< COL2 (Bitfield-Mask: 0x3f) */
- #define R_DALI0_COLTHR1_COL1_Pos (0UL) /*!< COL1 (Bit 0) */
- #define R_DALI0_COLTHR1_COL1_Msk (0x3fUL) /*!< COL1 (Bitfield-Mask: 0x3f) */
-/* ======================================================== COLTHR2 ======================================================== */
- #define R_DALI0_COLTHR2_COL4_Pos (8UL) /*!< COL4 (Bit 8) */
- #define R_DALI0_COLTHR2_COL4_Msk (0x7f00UL) /*!< COL4 (Bitfield-Mask: 0x7f) */
- #define R_DALI0_COLTHR2_COL3_Pos (0UL) /*!< COL3 (Bit 0) */
- #define R_DALI0_COLTHR2_COL3_Msk (0x7fUL) /*!< COL3 (Bitfield-Mask: 0x7f) */
-/* ======================================================== COLTHR3 ======================================================== */
- #define R_DALI0_COLTHR3_COL6_Pos (8UL) /*!< COL6 (Bit 8) */
- #define R_DALI0_COLTHR3_COL6_Msk (0x7f00UL) /*!< COL6 (Bitfield-Mask: 0x7f) */
- #define R_DALI0_COLTHR3_COL5_Pos (0UL) /*!< COL5 (Bit 0) */
- #define R_DALI0_COLTHR3_COL5_Msk (0x7fUL) /*!< COL5 (Bitfield-Mask: 0x7f) */
-/* ======================================================== COLTHR4 ======================================================== */
- #define R_DALI0_COLTHR4_COL8_Pos (8UL) /*!< COL8 (Bit 8) */
- #define R_DALI0_COLTHR4_COL8_Msk (0xff00UL) /*!< COL8 (Bitfield-Mask: 0xff) */
- #define R_DALI0_COLTHR4_COL7_Pos (0UL) /*!< COL7 (Bit 0) */
- #define R_DALI0_COLTHR4_COL7_Msk (0xffUL) /*!< COL7 (Bitfield-Mask: 0xff) */
-/* ======================================================== COLTHR5 ======================================================== */
- #define R_DALI0_COLTHR5_COL9_Pos (0UL) /*!< COL9 (Bit 0) */
- #define R_DALI0_COLTHR5_COL9_Msk (0xffUL) /*!< COL9 (Bitfield-Mask: 0xff) */
-/* ========================================================= CNFR1 ========================================================= */
- #define R_DALI0_CNFR1_CHL_Pos (12UL) /*!< CHL (Bit 12) */
- #define R_DALI0_CNFR1_CHL_Msk (0x7000UL) /*!< CHL (Bitfield-Mask: 0x07) */
- #define R_DALI0_CNFR1_CKS_Pos (8UL) /*!< CKS (Bit 8) */
- #define R_DALI0_CNFR1_CKS_Msk (0x300UL) /*!< CKS (Bitfield-Mask: 0x03) */
- #define R_DALI0_CNFR1_BR_Pos (0UL) /*!< BR (Bit 0) */
- #define R_DALI0_CNFR1_BR_Msk (0xffUL) /*!< BR (Bitfield-Mask: 0xff) */
-/* ========================================================= CNFR2 ========================================================= */
- #define R_DALI0_CNFR2_CDM0_Pos (5UL) /*!< CDM0 (Bit 5) */
- #define R_DALI0_CNFR2_CDM0_Msk (0x20UL) /*!< CDM0 (Bitfield-Mask: 0x01) */
- #define R_DALI0_CNFR2_CDE_Pos (4UL) /*!< CDE (Bit 4) */
- #define R_DALI0_CNFR2_CDE_Msk (0x10UL) /*!< CDE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CNFR2_TXWE_Pos (3UL) /*!< TXWE (Bit 3) */
- #define R_DALI0_CNFR2_TXWE_Msk (0x8UL) /*!< TXWE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CNFR2_SGA_Pos (2UL) /*!< SGA (Bit 2) */
- #define R_DALI0_CNFR2_SGA_Msk (0x4UL) /*!< SGA (Bitfield-Mask: 0x01) */
- #define R_DALI0_CNFR2_BTVM_Pos (1UL) /*!< BTVM (Bit 1) */
- #define R_DALI0_CNFR2_BTVM_Msk (0x2UL) /*!< BTVM (Bitfield-Mask: 0x01) */
- #define R_DALI0_CNFR2_BTVE_Pos (0UL) /*!< BTVE (Bit 0) */
- #define R_DALI0_CNFR2_BTVE_Msk (0x1UL) /*!< BTVE (Bitfield-Mask: 0x01) */
-/* ========================================================= TXWR1 ========================================================= */
- #define R_DALI0_TXWR1_TXLW_Pos (0UL) /*!< TXLW (Bit 0) */
- #define R_DALI0_TXWR1_TXLW_Msk (0x7fUL) /*!< TXLW (Bitfield-Mask: 0x7f) */
-/* ========================================================= TDR1H ========================================================= */
- #define R_DALI0_TDR1H_DTDR_Pos (0UL) /*!< DTDR (Bit 0) */
- #define R_DALI0_TDR1H_DTDR_Msk (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= TDR1L ========================================================= */
- #define R_DALI0_TDR1L_DTDR_Pos (0UL) /*!< DTDR (Bit 0) */
- #define R_DALI0_TDR1L_DTDR_Msk (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff) */
-/* ======================================================== TRSTR1 ========================================================= */
- #define R_DALI0_TRSTR1_TRST_Pos (0UL) /*!< TRST (Bit 0) */
- #define R_DALI0_TRSTR1_TRST_Msk (0x1UL) /*!< TRST (Bitfield-Mask: 0x01) */
-/* ========================================================= CTR1 ========================================================== */
- #define R_DALI0_CTR1_FEIE_Pos (12UL) /*!< FEIE (Bit 12) */
- #define R_DALI0_CTR1_FEIE_Msk (0x1000UL) /*!< FEIE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_BPIE_Pos (11UL) /*!< BPIE (Bit 11) */
- #define R_DALI0_CTR1_BPIE_Msk (0x800UL) /*!< BPIE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_CLIE_Pos (10UL) /*!< CLIE (Bit 10) */
- #define R_DALI0_CTR1_CLIE_Msk (0x400UL) /*!< CLIE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_DEIE_Pos (9UL) /*!< DEIE (Bit 9) */
- #define R_DALI0_CTR1_DEIE_Msk (0x200UL) /*!< DEIE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_SDIE_Pos (8UL) /*!< SDIE (Bit 8) */
- #define R_DALI0_CTR1_SDIE_Msk (0x100UL) /*!< SDIE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_RE_Pos (1UL) /*!< RE (Bit 1) */
- #define R_DALI0_CTR1_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
- #define R_DALI0_CTR1_TE_Pos (0UL) /*!< TE (Bit 0) */
- #define R_DALI0_CTR1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */
-/* ======================================================== TXDCTR1 ======================================================== */
- #define R_DALI0_TXDCTR1_TXASE_Pos (1UL) /*!< TXASE (Bit 1) */
- #define R_DALI0_TXDCTR1_TXASE_Msk (0x2UL) /*!< TXASE (Bitfield-Mask: 0x01) */
- #define R_DALI0_TXDCTR1_TXAS_Pos (0UL) /*!< TXAS (Bit 0) */
- #define R_DALI0_TXDCTR1_TXAS_Msk (0x1UL) /*!< TXAS (Bitfield-Mask: 0x01) */
-/* ========================================================= RDR1H ========================================================= */
- #define R_DALI0_RDR1H_DRDR_Pos (0UL) /*!< DRDR (Bit 0) */
- #define R_DALI0_RDR1H_DRDR_Msk (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= RDR1L ========================================================= */
- #define R_DALI0_RDR1L_DRDR_Pos (0UL) /*!< DRDR (Bit 0) */
- #define R_DALI0_RDR1L_DRDR_Msk (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= STR1 ========================================================== */
- #define R_DALI0_STR1_RDBL_Pos (10UL) /*!< RDBL (Bit 10) */
- #define R_DALI0_STR1_RDBL_Msk (0xfc00UL) /*!< RDBL (Bitfield-Mask: 0x3f) */
- #define R_DALI0_STR1_DAF_Pos (9UL) /*!< DAF (Bit 9) */
- #define R_DALI0_STR1_DAF_Msk (0x200UL) /*!< DAF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_CDF_Pos (8UL) /*!< CDF (Bit 8) */
- #define R_DALI0_STR1_CDF_Msk (0x100UL) /*!< CDF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_O32F_Pos (7UL) /*!< O32F (Bit 7) */
- #define R_DALI0_STR1_O32F_Msk (0x80UL) /*!< O32F (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_BPDF_Pos (6UL) /*!< BPDF (Bit 6) */
- #define R_DALI0_STR1_BPDF_Msk (0x40UL) /*!< BPDF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_BBF_Pos (5UL) /*!< BBF (Bit 5) */
- #define R_DALI0_STR1_BBF_Msk (0x20UL) /*!< BBF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_TENDF_Pos (4UL) /*!< TENDF (Bit 4) */
- #define R_DALI0_STR1_TENDF_Msk (0x10UL) /*!< TENDF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_RDRF_Pos (3UL) /*!< RDRF (Bit 3) */
- #define R_DALI0_STR1_RDRF_Msk (0x8UL) /*!< RDRF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_BTVF_Pos (2UL) /*!< BTVF (Bit 2) */
- #define R_DALI0_STR1_BTVF_Msk (0x4UL) /*!< BTVF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_OVF_Pos (1UL) /*!< OVF (Bit 1) */
- #define R_DALI0_STR1_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */
- #define R_DALI0_STR1_MFEF_Pos (0UL) /*!< MFEF (Bit 0) */
- #define R_DALI0_STR1_MFEF_Msk (0x1UL) /*!< MFEF (Bitfield-Mask: 0x01) */
-/* ========================================================= COLR1 ========================================================= */
- #define R_DALI0_COLR1_TXDCV_Pos (13UL) /*!< TXDCV (Bit 13) */
- #define R_DALI0_COLR1_TXDCV_Msk (0x2000UL) /*!< TXDCV (Bitfield-Mask: 0x01) */
- #define R_DALI0_COLR1_RXDCEG_Pos (12UL) /*!< RXDCEG (Bit 12) */
- #define R_DALI0_COLR1_RXDCEG_Msk (0x1000UL) /*!< RXDCEG (Bitfield-Mask: 0x01) */
- #define R_DALI0_COLR1_RXDMON_Pos (11UL) /*!< RXDMON (Bit 11) */
- #define R_DALI0_COLR1_RXDMON_Msk (0x800UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
- #define R_DALI0_COLR1_CLDAF_Pos (10UL) /*!< CLDAF (Bit 10) */
- #define R_DALI0_COLR1_CLDAF_Msk (0x400UL) /*!< CLDAF (Bitfield-Mask: 0x01) */
- #define R_DALI0_COLR1_CDTF1_Pos (4UL) /*!< CDTF1 (Bit 4) */
- #define R_DALI0_COLR1_CDTF1_Msk (0x10UL) /*!< CDTF1 (Bitfield-Mask: 0x01) */
- #define R_DALI0_COLR1_CFTF2_Pos (0UL) /*!< CFTF2 (Bit 0) */
- #define R_DALI0_COLR1_CFTF2_Msk (0xfUL) /*!< CFTF2 (Bitfield-Mask: 0x0f) */
-/* ========================================================= FECR1 ========================================================= */
- #define R_DALI0_FECR1_DAFC_Pos (9UL) /*!< DAFC (Bit 9) */
- #define R_DALI0_FECR1_DAFC_Msk (0x200UL) /*!< DAFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_CDFC_Pos (8UL) /*!< CDFC (Bit 8) */
- #define R_DALI0_FECR1_CDFC_Msk (0x100UL) /*!< CDFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_O32FC_Pos (7UL) /*!< O32FC (Bit 7) */
- #define R_DALI0_FECR1_O32FC_Msk (0x80UL) /*!< O32FC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_BPDFC_Pos (6UL) /*!< BPDFC (Bit 6) */
- #define R_DALI0_FECR1_BPDFC_Msk (0x40UL) /*!< BPDFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_BBFC_Pos (5UL) /*!< BBFC (Bit 5) */
- #define R_DALI0_FECR1_BBFC_Msk (0x20UL) /*!< BBFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_TENDFC_Pos (4UL) /*!< TENDFC (Bit 4) */
- #define R_DALI0_FECR1_TENDFC_Msk (0x10UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_RDRFC_Pos (3UL) /*!< RDRFC (Bit 3) */
- #define R_DALI0_FECR1_RDRFC_Msk (0x8UL) /*!< RDRFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_BTVFC_Pos (2UL) /*!< BTVFC (Bit 2) */
- #define R_DALI0_FECR1_BTVFC_Msk (0x4UL) /*!< BTVFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_OVFC_Pos (1UL) /*!< OVFC (Bit 1) */
- #define R_DALI0_FECR1_OVFC_Msk (0x2UL) /*!< OVFC (Bitfield-Mask: 0x01) */
- #define R_DALI0_FECR1_MFEFC_Pos (0UL) /*!< MFEFC (Bit 0) */
- #define R_DALI0_FECR1_MFEFC_Msk (0x1UL) /*!< MFEFC (Bitfield-Mask: 0x01) */
-/* ========================================================= SWRR1 ========================================================= */
- #define R_DALI0_SWRR1_SWR_Pos (0UL) /*!< SWR (Bit 0) */
- #define R_DALI0_SWRR1_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DEBUG ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== DBGSTR ========================================================= */
- #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */
- #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */
- #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */
-/* ======================================================= DBGSTOPCR ======================================================= */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */
- #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DMA ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DMAST ========================================================= */
- #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */
- #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */
-/* ======================================================== DMECHR ========================================================= */
- #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */
- #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */
- #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */
- #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */
- #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */
- #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DMAC0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DMSAR ========================================================= */
- #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */
- #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= DMDAR ========================================================= */
- #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */
- #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= DMCRA ========================================================= */
- #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */
- #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */
- #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */
- #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */
-/* ========================================================= DMCRB ========================================================= */
- #define R_DMAC0_DMCRB_DMCRB_Pos (0UL) /*!< DMCRB (Bit 0) */
- #define R_DMAC0_DMCRB_DMCRB_Msk (0xffffUL) /*!< DMCRB (Bitfield-Mask: 0xffff) */
-/* ========================================================= DMTMD ========================================================= */
- #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */
- #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */
- #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */
- #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */
- #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */
- #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */
-/* ========================================================= DMINT ========================================================= */
- #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */
- #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */
- #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */
- #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */
- #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */
- #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */
-/* ========================================================= DMAMD ========================================================= */
- #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */
- #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */
- #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */
- #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */
- #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */
- #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */
- #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */
- #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */
- #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */
- #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */
-/* ========================================================= DMOFR ========================================================= */
- #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */
- #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= DMCNT ========================================================= */
- #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */
- #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */
-/* ========================================================= DMREQ ========================================================= */
- #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */
- #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */
- #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */
-/* ========================================================= DMSTS ========================================================= */
- #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */
- #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */
- #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */
- #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */
- #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */
-/* ========================================================= DMSRR ========================================================= */
-/* ========================================================= DMDRR ========================================================= */
-/* ========================================================= DMSBS ========================================================= */
- #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */
- #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */
- #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */
- #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */
-/* ========================================================= DMDBS ========================================================= */
- #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */
- #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */
- #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */
- #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */
-/* ========================================================= DMBWR ========================================================= */
- #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */
- #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DOC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DOCR ========================================================== */
- #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */
- #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
- #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */
- #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
- #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */
- #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */
- #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
- #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
-/* ========================================================= DODIR ========================================================= */
- #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */
- #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */
-/* ========================================================= DODSR ========================================================= */
- #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */
- #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_DRW ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CONTROL ======================================================== */
- #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */
- #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */
- #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */
- #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */
- #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */
- #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */
- #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */
- #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */
- #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */
- #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */
- #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */
- #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */
- #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */
- #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */
- #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */
- #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */
- #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */
- #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */
- #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */
- #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */
- #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */
- #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */
- #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */
- #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */
- #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */
-/* ======================================================= CONTROL2 ======================================================== */
- #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */
- #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */
- #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */
- #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */
- #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */
- #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */
- #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */
- #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */
- #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */
- #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */
- #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */
- #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */
- #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */
- #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */
- #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */
- #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */
- #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */
- #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */
- #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */
- #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */
- #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */
- #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */
- #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */
- #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */
- #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */
- #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */
- #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */
- #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */
- #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */
- #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */
- #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */
- #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */
- #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */
- #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */
-/* ======================================================== IRQCTL ========================================================= */
- #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */
- #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */
- #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */
- #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */
- #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */
- #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */
- #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */
- #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */
- #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */
- #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */
- #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */
- #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */
-/* ======================================================= CACHECTL ======================================================== */
- #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */
- #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */
- #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */
- #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */
- #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */
- #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */
- #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */
- #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */
-/* ======================================================== STATUS ========================================================= */
- #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */
- #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */
- #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */
- #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */
- #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */
- #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */
- #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */
- #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */
- #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */
- #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */
- #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */
- #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */
-/* ====================================================== HWREVISION ======================================================= */
- #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */
- #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */
- #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */
- #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */
- #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */
- #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */
- #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */
- #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */
- #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */
- #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */
- #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */
- #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */
-/* ======================================================== COLOR1 ========================================================= */
- #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */
- #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */
- #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */
- #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */
- #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */
-/* ======================================================== COLOR2 ========================================================= */
- #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */
- #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */
- #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */
- #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */
- #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */
- #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */
-/* ======================================================== PATTERN ======================================================== */
- #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */
- #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */
-/* ======================================================== L1START ======================================================== */
- #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L2START ======================================================== */
- #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L3START ======================================================== */
- #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L4START ======================================================== */
- #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L5START ======================================================== */
- #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L6START ======================================================== */
- #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */
- #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L1XADD ========================================================= */
- #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L2XADD ========================================================= */
- #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L3XADD ========================================================= */
- #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L4XADD ========================================================= */
- #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L5XADD ========================================================= */
- #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L6XADD ========================================================= */
- #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */
- #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L1YADD ========================================================= */
- #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L2YADD ========================================================= */
- #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L3YADD ========================================================= */
- #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L4YADD ========================================================= */
- #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L5YADD ========================================================= */
- #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L6YADD ========================================================= */
- #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */
- #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L1BAND ========================================================= */
- #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */
- #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== L2BAND ========================================================= */
- #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */
- #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= TEXORIGIN ======================================================= */
- #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */
- #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= TEXPITCH ======================================================== */
- #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */
- #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== TEXMASK ======================================================== */
- #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */
- #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */
- #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */
- #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */
-/* ======================================================== LUSTART ======================================================== */
- #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */
- #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LUXADD ========================================================= */
- #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */
- #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LUYADD ========================================================= */
- #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */
- #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= LVSTARTI ======================================================== */
- #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */
- #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= LVSTARTF ======================================================== */
- #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */
- #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */
-/* ======================================================== LVXADDI ======================================================== */
- #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */
- #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LVYADDI ======================================================== */
- #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */
- #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= LVYXADDF ======================================================== */
- #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */
- #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */
- #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */
- #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */
-/* ======================================================= TEXCLADDR ======================================================= */
- #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */
- #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */
-/* ======================================================= TEXCLDATA ======================================================= */
- #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */
- #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */
-/* ====================================================== TEXCLOFFSET ====================================================== */
- #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */
- #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */
-/* ======================================================== COLKEY ========================================================= */
- #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */
- #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */
- #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */
- #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */
- #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */
- #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */
-/* ========================================================= SIZE ========================================================== */
- #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */
- #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */
- #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */
- #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */
-/* ========================================================= PITCH ========================================================= */
- #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */
- #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */
- #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */
- #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */
-/* ======================================================== ORIGIN ========================================================= */
- #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */
- #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */
-/* ====================================================== DLISTSTART ======================================================= */
- #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */
- #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */
-/* ====================================================== PERFTRIGGER ====================================================== */
- #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */
- #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */
- #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */
- #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */
-/* ====================================================== PERFCOUNT1 ======================================================= */
- #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */
- #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */
-/* ====================================================== PERFCOUNT2 ======================================================= */
- #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */
- #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_DTC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DTCCR ========================================================= */
- #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */
- #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */
-/* ======================================================== DTCVBR ========================================================= */
- #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */
- #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= DTCST ========================================================= */
- #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */
- #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */
-/* ======================================================== DTCSTS ========================================================= */
- #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */
- #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */
- #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */
- #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */
-/* ======================================================= DTCCR_SEC ======================================================= */
- #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */
- #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */
-/* ====================================================== DTCVBR_SEC ======================================================= */
-/* ========================================================= DTEVR ========================================================= */
- #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */
- #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */
- #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */
- #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */
- #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */
- #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_ELC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ELCR ========================================================== */
- #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */
- #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */
-/* ======================================================== ELCSARA ======================================================== */
- #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */
- #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */
- #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */
- #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
-/* ======================================================== ELCSARB ======================================================== */
- #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */
- #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */
- #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */
- #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */
- #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */
- #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */
- #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */
- #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */
- #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */
- #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */
- #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */
- #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */
- #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */
- #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */
- #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */
- #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */
- #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */
-/* ======================================================== ELCSARC ======================================================== */
- #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */
- #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */
- #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */
- #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ECMR ========================================================== */
- #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */
- #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */
- #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */
- #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */
- #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */
- #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */
- #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */
- #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */
- #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */
- #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */
- #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */
- #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */
- #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */
- #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */
-/* ========================================================= RFLR ========================================================== */
- #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */
- #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */
-/* ========================================================= ECSR ========================================================== */
- #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */
- #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */
- #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */
- #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */
- #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */
- #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */
-/* ======================================================== ECSIPR ========================================================= */
- #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */
- #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */
- #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */
- #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */
- #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */
- #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */
-/* ========================================================== PIR ========================================================== */
- #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */
- #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */
- #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */
- #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */
- #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */
- #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */
-/* ========================================================== PSR ========================================================== */
- #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */
- #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */
-/* ========================================================= RDMLR ========================================================= */
- #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */
- #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */
-/* ========================================================= IPGR ========================================================== */
- #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */
- #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */
-/* ========================================================== APR ========================================================== */
- #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */
- #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */
-/* ========================================================== MPR ========================================================== */
- #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */
- #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */
-/* ========================================================= RFCF ========================================================== */
- #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */
- #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */
-/* ======================================================== TPAUSER ======================================================== */
- #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */
- #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */
-/* ======================================================= TPAUSECR ======================================================== */
-/* ========================================================= BCFRR ========================================================= */
- #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */
- #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */
-/* ========================================================= MAHR ========================================================== */
- #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */
- #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= MALR ========================================================== */
- #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */
- #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */
-/* ========================================================= TROCR ========================================================= */
- #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */
- #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= CDCR ========================================================== */
-/* ========================================================= LCCR ========================================================== */
- #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */
- #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= CNDCR ========================================================= */
- #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */
- #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= CEFCR ========================================================= */
- #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */
- #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= FRECR ========================================================= */
- #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */
- #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== TSFRCR ========================================================= */
- #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */
- #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== TLFRCR ========================================================= */
- #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */
- #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= RFCR ========================================================== */
- #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */
- #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= MAFCR ========================================================= */
- #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */
- #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EDMAC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= EDMR ========================================================== */
- #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */
- #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */
- #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */
- #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */
- #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */
-/* ========================================================= EDTRR ========================================================= */
- #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */
- #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */
-/* ========================================================= EDRRR ========================================================= */
- #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */
- #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */
-/* ========================================================= TDLAR ========================================================= */
- #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */
- #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= RDLAR ========================================================= */
- #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */
- #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= EESR ========================================================== */
- #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */
- #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */
- #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */
- #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */
- #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */
- #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */
- #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */
- #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */
- #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */
- #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */
- #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */
- #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */
- #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */
- #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */
- #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */
- #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */
- #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */
- #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */
- #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */
- #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */
- #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */
- #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */
- #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */
-/* ======================================================== EESIPR ========================================================= */
- #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */
- #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */
- #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */
- #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */
- #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */
- #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */
- #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */
- #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */
- #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */
- #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */
- #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */
- #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */
- #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */
- #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */
- #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */
- #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */
- #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */
- #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */
- #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */
- #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */
- #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */
- #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */
- #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */
-/* ======================================================== TRSCER ========================================================= */
- #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */
- #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */
- #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */
-/* ========================================================= RMFCR ========================================================= */
- #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */
- #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */
-/* ========================================================= TFTR ========================================================== */
- #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */
- #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */
-/* ========================================================== FDR ========================================================== */
- #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */
- #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */
- #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */
- #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */
-/* ========================================================= RMCR ========================================================== */
- #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */
- #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */
-/* ========================================================= TFUCR ========================================================= */
- #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */
- #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */
-/* ========================================================= RFOCR ========================================================= */
- #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */
- #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */
-/* ========================================================= IOSR ========================================================== */
- #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */
- #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */
-/* ========================================================= FCFTR ========================================================= */
- #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */
- #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */
- #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */
- #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */
-/* ======================================================== RPADIR ========================================================= */
- #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */
- #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */
- #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */
- #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */
-/* ========================================================= TRIMD ========================================================= */
- #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */
- #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */
- #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */
-/* ========================================================= RBWAR ========================================================= */
- #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */
- #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= RDFAR ========================================================= */
- #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */
- #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= TBRAR ========================================================= */
- #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */
- #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= TDFAR ========================================================= */
- #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */
- #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SYSR ========================================================== */
- #define R_ETHERC_EPTPC_SYSR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */
- #define R_ETHERC_EPTPC_SYSR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */
- #define R_ETHERC_EPTPC_SYSR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */
- #define R_ETHERC_EPTPC_SYSR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */
- #define R_ETHERC_EPTPC_SYSR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */
- #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */
- #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */
- #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */
- #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */
- #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */
- #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */
-/* ========================================================= SYIPR ========================================================= */
- #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */
- #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */
- #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */
- #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */
- #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */
- #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */
- #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */
- #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */
- #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */
- #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */
- #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */
-/* ======================================================== SYMACRU ======================================================== */
- #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos (0UL) /*!< SYMACRU (Bit 0) */
- #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk (0xffffffUL) /*!< SYMACRU (Bitfield-Mask: 0xffffff) */
-/* ======================================================== SYMACRL ======================================================== */
- #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos (0UL) /*!< SYMACRL (Bit 0) */
- #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk (0xffffffUL) /*!< SYMACRL (Bitfield-Mask: 0xffffff) */
-/* ======================================================= SYLLCCTLR ======================================================= */
- #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos (0UL) /*!< CTL (Bit 0) */
- #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk (0xffUL) /*!< CTL (Bitfield-Mask: 0xff) */
-/* ======================================================= SYIPADDRR ======================================================= */
- #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos (0UL) /*!< SYIPADDRR (Bit 0) */
- #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SYSPVRR ======================================================== */
- #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos (4UL) /*!< TRSP (Bit 4) */
- #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk (0xf0UL) /*!< TRSP (Bitfield-Mask: 0x0f) */
- #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos (0UL) /*!< VER (Bit 0) */
- #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */
-/* ======================================================== SYDOMR ========================================================= */
- #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos (0UL) /*!< DNUM (Bit 0) */
- #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk (0xffUL) /*!< DNUM (Bitfield-Mask: 0xff) */
-/* ========================================================= ANFR ========================================================== */
- #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */
- #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */
- #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */
- #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */
- #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos (5UL) /*!< FLAG5 (Bit 5) */
- #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk (0x20UL) /*!< FLAG5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos (4UL) /*!< FLAG4 (Bit 4) */
- #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk (0x10UL) /*!< FLAG4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos (3UL) /*!< FLAG3 (Bit 3) */
- #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk (0x8UL) /*!< FLAG3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos (2UL) /*!< FLAG2 (Bit 2) */
- #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk (0x4UL) /*!< FLAG2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos (1UL) /*!< FLAG1 (Bit 1) */
- #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk (0x2UL) /*!< FLAG1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos (0UL) /*!< FLAG0 (Bit 0) */
- #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk (0x1UL) /*!< FLAG0 (Bitfield-Mask: 0x01) */
-/* ========================================================= SYNFR ========================================================= */
- #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */
- #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */
-/* ======================================================== DYRQFR ========================================================= */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */
- #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */
-/* ======================================================== DYRPFR ========================================================= */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */
- #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */
-/* ======================================================== SYCIDRU ======================================================== */
- #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos (0UL) /*!< SYCIDRU (Bit 0) */
- #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SYCIDRL ======================================================== */
- #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos (0UL) /*!< SYCIDRL (Bit 0) */
- #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SYPNUMR ======================================================== */
- #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */
- #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */
-/* ======================================================== SYRVLDR ======================================================== */
- #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos (2UL) /*!< ANUP (Bit 2) */
- #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk (0x4UL) /*!< ANUP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos (1UL) /*!< STUP (Bit 1) */
- #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk (0x2UL) /*!< STUP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos (0UL) /*!< BMUP (Bit 0) */
- #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk (0x1UL) /*!< BMUP (Bitfield-Mask: 0x01) */
-/* ======================================================== SYRFL1R ======================================================== */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos (30UL) /*!< PDFUP2 (Bit 30) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos (29UL) /*!< PDFUP1 (Bit 29) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos (28UL) /*!< PDFUP0 (Bit 28) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos (26UL) /*!< PDRP2 (Bit 26) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk (0x4000000UL) /*!< PDRP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos (25UL) /*!< PDRP1 (Bit 25) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk (0x2000000UL) /*!< PDRP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos (24UL) /*!< PDRP0 (Bit 24) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk (0x1000000UL) /*!< PDRP0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos (22UL) /*!< PDRQ2 (Bit 22) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk (0x400000UL) /*!< PDRQ2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos (21UL) /*!< PDRQ1 (Bit 21) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk (0x200000UL) /*!< PDRQ1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos (20UL) /*!< PDRQ0 (Bit 20) */
- #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk (0x100000UL) /*!< PDRQ0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos (18UL) /*!< DRP2 (Bit 18) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk (0x40000UL) /*!< DRP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos (17UL) /*!< DRP1 (Bit 17) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk (0x20000UL) /*!< DRP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos (16UL) /*!< DRP0 (Bit 16) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk (0x10000UL) /*!< DRP0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos (14UL) /*!< DRQ2 (Bit 14) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk (0x4000UL) /*!< DRQ2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos (13UL) /*!< DRQ1 (Bit 13) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk (0x2000UL) /*!< DRQ1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos (12UL) /*!< DRQ0 (Bit 12) */
- #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk (0x1000UL) /*!< DRQ0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos (10UL) /*!< FUP2 (Bit 10) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk (0x400UL) /*!< FUP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos (9UL) /*!< FUP1 (Bit 9) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk (0x200UL) /*!< FUP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos (8UL) /*!< FUP0 (Bit 8) */
- #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk (0x100UL) /*!< FUP0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos (6UL) /*!< SYNC2 (Bit 6) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk (0x40UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos (5UL) /*!< SYNC1 (Bit 5) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk (0x20UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos (4UL) /*!< SYNC0 (Bit 4) */
- #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk (0x10UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos (1UL) /*!< ANCE1 (Bit 1) */
- #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk (0x2UL) /*!< ANCE1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos (0UL) /*!< ANCE0 (Bit 0) */
- #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk (0x1UL) /*!< ANCE0 (Bitfield-Mask: 0x01) */
-/* ======================================================== SYRFL2R ======================================================== */
- #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos (29UL) /*!< ILL1 (Bit 29) */
- #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos (28UL) /*!< ILL0 (Bit 28) */
- #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos (5UL) /*!< SIG1 (Bit 5) */
- #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk (0x20UL) /*!< SIG1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos (4UL) /*!< SIG0 (Bit 4) */
- #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk (0x10UL) /*!< SIG0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos (1UL) /*!< MAN1 (Bit 1) */
- #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk (0x2UL) /*!< MAN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos (0UL) /*!< MAN0 (Bit 0) */
- #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk (0x1UL) /*!< MAN0 (Bitfield-Mask: 0x01) */
-/* ======================================================== SYTRENR ======================================================== */
- #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos (12UL) /*!< PDRQ (Bit 12) */
- #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk (0x1000UL) /*!< PDRQ (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos (8UL) /*!< DRQ (Bit 8) */
- #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk (0x100UL) /*!< DRQ (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos (4UL) /*!< SYNC (Bit 4) */
- #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk (0x10UL) /*!< SYNC (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */
- #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk (0x1UL) /*!< ANCE (Bitfield-Mask: 0x01) */
-/* ======================================================== MTCIDU ========================================================= */
- #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos (0UL) /*!< MTCIDU (Bit 0) */
- #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== MTCIDL ========================================================= */
- #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos (0UL) /*!< MTCIDL (Bit 0) */
- #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= MTPID ========================================================= */
- #define R_ETHERC_EPTPC_MTPID_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */
- #define R_ETHERC_EPTPC_MTPID_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */
-/* ======================================================== SYTLIR ========================================================= */
- #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos (16UL) /*!< DREQ (Bit 16) */
- #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk (0xff0000UL) /*!< DREQ (Bitfield-Mask: 0xff) */
- #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */
- #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */
- #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */
- #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */
-/* ======================================================== SYRLIR ========================================================= */
- #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos (16UL) /*!< DRESP (Bit 16) */
- #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk (0xff0000UL) /*!< DRESP (Bitfield-Mask: 0xff) */
- #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */
- #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */
- #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */
- #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */
-/* ========================================================= OFMRU ========================================================= */
- #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos (0UL) /*!< OFMRU (Bit 0) */
- #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= OFMRL ========================================================= */
- #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos (0UL) /*!< OFMRL (Bit 0) */
- #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= MPDRU ========================================================= */
- #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos (0UL) /*!< MPDRU (Bit 0) */
- #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= MPDRL ========================================================= */
- #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos (0UL) /*!< MPDRL (Bit 0) */
- #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GMPR ========================================================== */
- #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos (16UL) /*!< GMPR1 (Bit 16) */
- #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk (0xff0000UL) /*!< GMPR1 (Bitfield-Mask: 0xff) */
- #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos (0UL) /*!< GMPR2 (Bit 0) */
- #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk (0xffUL) /*!< GMPR2 (Bitfield-Mask: 0xff) */
-/* ========================================================= GMCQR ========================================================= */
- #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos (0UL) /*!< GMCQR (Bit 0) */
- #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GMIDRU ========================================================= */
- #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos (0UL) /*!< GMIDRU (Bit 0) */
- #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GMIDRL ========================================================= */
- #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos (0UL) /*!< GMIDRL (Bit 0) */
- #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== CUOTSR ========================================================= */
- #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos (16UL) /*!< CUTO (Bit 16) */
- #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff) */
- #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos (0UL) /*!< TSRC (Bit 0) */
- #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk (0xffUL) /*!< TSRC (Bitfield-Mask: 0xff) */
-/* ========================================================== SRR ========================================================== */
- #define R_ETHERC_EPTPC_SRR_SRMV_Pos (0UL) /*!< SRMV (Bit 0) */
- #define R_ETHERC_EPTPC_SRR_SRMV_Msk (0xffffUL) /*!< SRMV (Bitfield-Mask: 0xffff) */
-/* ======================================================== PPMACRU ======================================================== */
- #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos (0UL) /*!< PPMACRU (Bit 0) */
- #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk (0xffffffUL) /*!< PPMACRU (Bitfield-Mask: 0xffffff) */
-/* ======================================================== PPMACRL ======================================================== */
- #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos (0UL) /*!< PPMACRL (Bit 0) */
- #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk (0xffffffUL) /*!< PPMACRL (Bitfield-Mask: 0xffffff) */
-/* ======================================================== PDMACRU ======================================================== */
- #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos (0UL) /*!< PDMACRU (Bit 0) */
- #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk (0xffffffUL) /*!< PDMACRU (Bitfield-Mask: 0xffffff) */
-/* ======================================================== PDMACRL ======================================================== */
- #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos (0UL) /*!< PDMACRL (Bit 0) */
- #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk (0xffffffUL) /*!< PDMACRL (Bitfield-Mask: 0xffffff) */
-/* ======================================================== PETYPER ======================================================== */
- #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */
- #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk (0xffffUL) /*!< TYPE (Bitfield-Mask: 0xffff) */
-/* ========================================================= PPIPR ========================================================= */
- #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos (0UL) /*!< PPIPR (Bit 0) */
- #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= PDIPR ========================================================= */
- #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos (0UL) /*!< PDIPR (Bit 0) */
- #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== PETOSR ========================================================= */
- #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos (0UL) /*!< EVTO (Bit 0) */
- #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk (0xffUL) /*!< EVTO (Bitfield-Mask: 0xff) */
-/* ======================================================== PGTOSR ========================================================= */
- #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos (0UL) /*!< GETO (Bit 0) */
- #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk (0xffUL) /*!< GETO (Bitfield-Mask: 0xff) */
-/* ======================================================== PPTTLR ========================================================= */
- #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos (0UL) /*!< PRTL (Bit 0) */
- #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk (0xffUL) /*!< PRTL (Bitfield-Mask: 0xff) */
-/* ======================================================== PDTTLR ========================================================= */
- #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos (0UL) /*!< PDTL (Bit 0) */
- #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk (0xffUL) /*!< PDTL (Bitfield-Mask: 0xff) */
-/* ======================================================== PEUDPR ========================================================= */
- #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos (0UL) /*!< EVUPT (Bit 0) */
- #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk (0xffffUL) /*!< EVUPT (Bitfield-Mask: 0xffff) */
-/* ======================================================== PGUDPR ========================================================= */
- #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos (0UL) /*!< GEUPT (Bit 0) */
- #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk (0xffffUL) /*!< GEUPT (Bitfield-Mask: 0xffff) */
-/* ========================================================= FFLTR ========================================================= */
- #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos (16UL) /*!< EXTPRM (Bit 16) */
- #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk (0x10000UL) /*!< EXTPRM (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_FFLTR_ENB_Pos (2UL) /*!< ENB (Bit 2) */
- #define R_ETHERC_EPTPC_FFLTR_ENB_Msk (0x4UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_FFLTR_PRT_Pos (1UL) /*!< PRT (Bit 1) */
- #define R_ETHERC_EPTPC_FFLTR_PRT_Msk (0x2UL) /*!< PRT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_FFLTR_SEL_Pos (0UL) /*!< SEL (Bit 0) */
- #define R_ETHERC_EPTPC_FFLTR_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */
-/* ======================================================== FMAC0RU ======================================================== */
- #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Pos (0UL) /*!< FMAC0RU (Bit 0) */
- #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Msk (0xffffffUL) /*!< FMAC0RU (Bitfield-Mask: 0xffffff) */
-/* ======================================================== FMAC0RL ======================================================== */
- #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Pos (0UL) /*!< FMAC0RL (Bit 0) */
- #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Msk (0xffffffUL) /*!< FMAC0RL (Bitfield-Mask: 0xffffff) */
-/* ======================================================== FMAC1RU ======================================================== */
- #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Pos (0UL) /*!< FMAC1RU (Bit 0) */
- #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Msk (0xffffffUL) /*!< FMAC1RU (Bitfield-Mask: 0xffffff) */
-/* ======================================================== FMAC1RL ======================================================== */
- #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Pos (0UL) /*!< FMAC1RL (Bit 0) */
- #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Msk (0xffffffUL) /*!< FMAC1RL (Bitfield-Mask: 0xffffff) */
-/* ======================================================== DASYMRU ======================================================== */
- #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos (0UL) /*!< DASYMRU (Bit 0) */
- #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk (0xffffUL) /*!< DASYMRU (Bitfield-Mask: 0xffff) */
-/* ======================================================== DASYMRL ======================================================== */
- #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos (0UL) /*!< DASYMRL (Bit 0) */
- #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== TSLATR ========================================================= */
- #define R_ETHERC_EPTPC_TSLATR_INGP_Pos (16UL) /*!< INGP (Bit 16) */
- #define R_ETHERC_EPTPC_TSLATR_INGP_Msk (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff) */
- #define R_ETHERC_EPTPC_TSLATR_EGP_Pos (0UL) /*!< EGP (Bit 0) */
- #define R_ETHERC_EPTPC_TSLATR_EGP_Msk (0xffffUL) /*!< EGP (Bitfield-Mask: 0xffff) */
-/* ======================================================== SYCONFR ======================================================== */
- #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos (20UL) /*!< TCMOD (Bit 20) */
- #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk (0x100000UL) /*!< TCMOD (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos (16UL) /*!< FILDIS (Bit 16) */
- #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk (0x10000UL) /*!< FILDIS (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos (12UL) /*!< SBDIS (Bit 12) */
- #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk (0x1000UL) /*!< SBDIS (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos (0UL) /*!< TCYC (Bit 0) */
- #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk (0xffUL) /*!< TCYC (Bitfield-Mask: 0xff) */
-/* ======================================================== SYFORMR ======================================================== */
- #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos (1UL) /*!< FORM1 (Bit 1) */
- #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk (0x2UL) /*!< FORM1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos (0UL) /*!< FORM0 (Bit 0) */
- #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk (0x1UL) /*!< FORM0 (Bitfield-Mask: 0x01) */
-/* ======================================================== RSTOUTR ======================================================== */
- #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos (0UL) /*!< RSTOUTR (Bit 0) */
- #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC_CFG ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== PTRSTR ========================================================= */
- #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos (0UL) /*!< RESET (Bit 0) */
- #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk (0x1UL) /*!< RESET (Bitfield-Mask: 0x01) */
-/* ======================================================== STCSELR ======================================================== */
- #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos (8UL) /*!< SCLKSEL (Bit 8) */
- #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk (0x700UL) /*!< SCLKSEL (Bitfield-Mask: 0x07) */
- #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos (0UL) /*!< SCLKDIV (Bit 0) */
- #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk (0x7UL) /*!< SCLKDIV (Bitfield-Mask: 0x07) */
-/* ======================================================== BYPASS ========================================================= */
- #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos (16UL) /*!< BYPASS1 (Bit 16) */
- #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos (0UL) /*!< BYPASS0 (Bit 0) */
- #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk (0x1UL) /*!< BYPASS0 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_ETHERC_EPTPC_COMMON ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= MIESR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos (3UL) /*!< PRC (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos (0UL) /*!< ST (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */
-/* ======================================================== MIEIPR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos (3UL) /*!< PRC (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos (0UL) /*!< ST (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */
-/* ======================================================== ELIPPR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */
-/* ======================================================== ELIPACR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */
-/* ========================================================= STSR ========================================================== */
- #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos (4UL) /*!< W10D (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */
-/* ========================================================= STIPR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos (4UL) /*!< W10D (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */
-/* ========================================================= STCFR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos (0UL) /*!< STCF (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk (0x3UL) /*!< STCF (Bitfield-Mask: 0x03) */
-/* ========================================================= STMR ========================================================== */
- #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos (29UL) /*!< ALEN1 (Bit 29) */
- #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos (28UL) /*!< ALEN0 (Bit 28) */
- #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos (20UL) /*!< DVTH (Bit 20) */
- #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk (0xf00000UL) /*!< DVTH (Bitfield-Mask: 0x0f) */
- #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos (16UL) /*!< SYTH (Bit 16) */
- #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk (0xf0000UL) /*!< SYTH (Bitfield-Mask: 0x0f) */
- #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos (15UL) /*!< W10S (Bit 15) */
- #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk (0x8000UL) /*!< W10S (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos (13UL) /*!< CMOD (Bit 13) */
- #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk (0x2000UL) /*!< CMOD (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos (0UL) /*!< WINT (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk (0xffUL) /*!< WINT (Bitfield-Mask: 0xff) */
-/* ======================================================== SYNTOR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos (0UL) /*!< SYNTOR (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== IPTSELR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos (5UL) /*!< IPTSEL5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk (0x20UL) /*!< IPTSEL5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos (4UL) /*!< IPTSEL4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk (0x10UL) /*!< IPTSEL4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos (3UL) /*!< IPTSEL3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk (0x8UL) /*!< IPTSEL3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos (2UL) /*!< IPTSEL2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk (0x4UL) /*!< IPTSEL2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos (1UL) /*!< IPTSEL1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk (0x2UL) /*!< IPTSEL1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos (0UL) /*!< IPTSEL0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk (0x1UL) /*!< IPTSEL0 (Bitfield-Mask: 0x01) */
-/* ======================================================== MITSELR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos (5UL) /*!< MINTEN5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk (0x20UL) /*!< MINTEN5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos (4UL) /*!< MINTEN4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk (0x10UL) /*!< MINTEN4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos (3UL) /*!< MINTEN3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk (0x8UL) /*!< MINTEN3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos (2UL) /*!< MINTEN2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk (0x4UL) /*!< MINTEN2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos (1UL) /*!< MINTEN1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk (0x2UL) /*!< MINTEN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos (0UL) /*!< MINTEN0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk (0x1UL) /*!< MINTEN0 (Bitfield-Mask: 0x01) */
-/* ======================================================== ELTSELR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos (5UL) /*!< ELTDIS5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk (0x20UL) /*!< ELTDIS5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos (4UL) /*!< ELTDIS4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk (0x10UL) /*!< ELTDIS4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos (3UL) /*!< ELTDIS3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk (0x8UL) /*!< ELTDIS3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos (2UL) /*!< ELTDIS2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk (0x4UL) /*!< ELTDIS2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos (1UL) /*!< ELTDIS1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk (0x2UL) /*!< ELTDIS1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos (0UL) /*!< ELTDIS0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk (0x1UL) /*!< ELTDIS0 (Bitfield-Mask: 0x01) */
-/* ======================================================= STCHSELR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos (0UL) /*!< SYSEL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk (0x1UL) /*!< SYSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= SYNSTARTR ======================================================= */
- #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos (0UL) /*!< STR (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */
-/* ======================================================== LCIVLDR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk (0x1UL) /*!< LOAD (Bitfield-Mask: 0x01) */
-/* ======================================================= SYNTDARU ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos (0UL) /*!< SYNTDARU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SYNTDARL ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos (0UL) /*!< SYNTDARL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SYNTDBRU ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos (0UL) /*!< SYNTDBRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SYNTDBRL ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos (0UL) /*!< SYNTDBRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LCIVRU ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos (0UL) /*!< LCIVRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk (0xffffUL) /*!< LCIVRU (Bitfield-Mask: 0xffff) */
-/* ======================================================== LCIVRM ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos (0UL) /*!< LCIVRM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LCIVRL ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos (0UL) /*!< LCIVRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GETW10R ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos (0UL) /*!< GW10 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk (0x1UL) /*!< GW10 (Bitfield-Mask: 0x01) */
-/* ======================================================= PLIMITRU ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos (0UL) /*!< PLIMITRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff) */
-/* ======================================================= PLIMITRM ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos (0UL) /*!< PLIMITRM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= PLIMITRL ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos (0UL) /*!< PLIMITRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= MLIMITRU ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos (0UL) /*!< MLIMITRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff) */
-/* ======================================================= MLIMITRM ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos (0UL) /*!< MLIMITRM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= MLIMITRL ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos (0UL) /*!< MLIMITRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= GETINFOR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos (0UL) /*!< INFO (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk (0x1UL) /*!< INFO (Bitfield-Mask: 0x01) */
-/* ======================================================== LCCVRU ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos (0UL) /*!< LCCVRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk (0xffffUL) /*!< LCCVRU (Bitfield-Mask: 0xffff) */
-/* ======================================================== LCCVRM ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos (0UL) /*!< LCCVRM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== LCCVRL ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos (0UL) /*!< LCCVRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== PW10VRU ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos (0UL) /*!< PW10VRU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== PW10VRM ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos (0UL) /*!< PW10VRM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== PW10VRL ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos (0UL) /*!< PW10VRL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== MW10RU ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos (0UL) /*!< MW10RU (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== MW10RM ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos (0UL) /*!< MW10RM (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== MW10RL ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos (0UL) /*!< MW10RL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= TMSTARTR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos (5UL) /*!< EN5 (Bit 5) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos (4UL) /*!< EN4 (Bit 4) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos (3UL) /*!< EN3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos (2UL) /*!< EN2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos (1UL) /*!< EN1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos (0UL) /*!< EN0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */
-/* ========================================================= PRSR ========================================================== */
- #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos (8UL) /*!< MACE (Bit 8) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */
-/* ========================================================= PRIPR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos (8UL) /*!< MACE (Bit 8) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */
-/* ======================================================== TRNDISR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos (0UL) /*!< TDIS (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk (0x3UL) /*!< TDIS (Bitfield-Mask: 0x03) */
-/* ========================================================= TRNMR ========================================================= */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos (9UL) /*!< FWD1 (Bit 9) */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk (0x200UL) /*!< FWD1 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos (8UL) /*!< FWD0 (Bit 8) */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk (0x100UL) /*!< FWD0 (Bitfield-Mask: 0x01) */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos (0UL) /*!< MOD (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk (0x1UL) /*!< MOD (Bitfield-Mask: 0x01) */
-/* ======================================================= TRNCTTDR ======================================================== */
- #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos (0UL) /*!< THVAL (Bit 0) */
- #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk (0x7ffUL) /*!< THVAL (Bitfield-Mask: 0x7ff) */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_HP_CMD ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================== FACI_CMD16 ======================================================= */
-/* ======================================================= FACI_CMD8 ======================================================= */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_HP ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== FASTAT ========================================================= */
- #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */
- #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */
- #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */
- #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */
- #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */
-/* ======================================================== FAEINT ========================================================= */
- #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */
- #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */
- #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */
- #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */
- #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */
-/* ======================================================== FRDYIE ========================================================= */
- #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */
- #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */
-/* ======================================================== FSADDR ========================================================= */
- #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */
- #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== FEADDR ========================================================= */
- #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */
- #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== FMEPROT ======================================================== */
- #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */
- #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */
-/* ======================================================== FBPROT0 ======================================================== */
- #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */
- #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */
-/* ======================================================== FBPROT1 ======================================================== */
- #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */
- #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */
-/* ======================================================== FSTATR ========================================================= */
- #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */
- #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */
- #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */
- #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */
- #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */
- #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */
- #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */
- #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */
- #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */
- #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */
- #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */
- #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */
- #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */
- #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */
-/* ======================================================== FENTRYR ======================================================== */
- #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */
- #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */
- #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */
-/* ======================================================= FSUINITR ======================================================== */
- #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */
- #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */
-/* ========================================================= FCMDR ========================================================= */
- #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */
- #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */
- #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */
-/* ======================================================== FPESTAT ======================================================== */
- #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */
- #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */
-/* ======================================================== FBCCNT ========================================================= */
- #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */
- #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */
-/* ======================================================== FBCSTAT ======================================================== */
- #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */
- #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */
-/* ======================================================== FPSADDR ======================================================== */
- #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */
- #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */
-/* ======================================================== FAWMON ========================================================= */
- #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */
- #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */
- #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */
- #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */
- #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */
- #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */
- #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */
-/* ========================================================= FCPSR ========================================================= */
- #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */
- #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */
-/* ======================================================== FPCKAR ========================================================= */
- #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */
- #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */
-/* ======================================================== FSUACR ========================================================= */
- #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */
- #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */
-
-/* =========================================================================================================================== */
-/* ================ R_FACI_LP ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== DFLCTL ========================================================= */
-/* ========================================================= FPMCR ========================================================= */
- #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */
- #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */
- #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */
- #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */
- #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */
- #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */
-/* ========================================================= FASR ========================================================== */
- #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */
- #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */
-/* ========================================================= FSARL ========================================================= */
- #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */
- #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */
-/* ========================================================= FSARH ========================================================= */
- #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */
- #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */
- #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */
- #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */
-/* ========================================================== FCR ========================================================== */
- #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */
- #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */
- #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */
- #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */
- #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */
-/* ========================================================= FEARL ========================================================= */
- #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */
- #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */
-/* ========================================================= FEARH ========================================================= */
- #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */
- #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */
- #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */
- #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */
-/* ======================================================== FRESETR ======================================================== */
- #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */
- #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */
-/* ======================================================= FSTATR00 ======================================================== */
- #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */
- #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */
- #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */
- #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */
- #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */
- #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */
- #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */
-/* ======================================================== FSTATR1 ======================================================== */
- #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */
- #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */
- #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */
- #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */
-/* ========================================================= FWBL0 ========================================================= */
- #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */
- #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */
-/* ========================================================= FWBH0 ========================================================= */
- #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */
- #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */
-/* ======================================================= FSTATR01 ======================================================== */
- #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */
- #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */
- #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */
- #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */
-/* ========================================================= FWBL1 ========================================================= */
- #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */
- #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */
-/* ========================================================= FWBH1 ========================================================= */
- #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */
- #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */
-/* ========================================================= FRBL1 ========================================================= */
- #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */
- #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */
-/* ========================================================= FRBH1 ========================================================= */
- #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */
- #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */
-/* ========================================================== FPR ========================================================== */
- #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */
- #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */
-/* ========================================================= FPSR ========================================================== */
- #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */
- #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */
-/* ========================================================= FRBL0 ========================================================= */
- #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
- #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
-/* ========================================================= FRBH0 ========================================================= */
- #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
- #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
-/* ========================================================= FSCMR ========================================================= */
- #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */
- #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */
- #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */
-/* ======================================================== FAWSMR ========================================================= */
- #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */
- #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */
-/* ======================================================== FAWEMR ========================================================= */
- #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */
- #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */
-/* ========================================================= FISR ========================================================== */
- #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */
- #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */
- #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */
- #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */
-/* ========================================================= FEXCR ========================================================= */
- #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */
- #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */
- #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */
-/* ========================================================= FEAML ========================================================= */
- #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */
- #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */
-/* ========================================================= FEAMH ========================================================= */
- #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */
- #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */
-/* ======================================================== FSTATR2 ======================================================== */
- #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */
- #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */
- #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */
- #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */
- #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */
- #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */
- #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */
- #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */
-/* ====================================================== FENTRYR_MF4 ====================================================== */
-/* ======================================================== FENTRYR ======================================================== */
-/* ======================================================== FLWAITR ======================================================== */
-/* ========================================================= PFBER ========================================================= */
-
-/* =========================================================================================================================== */
-/* ================ R_CTSUTRIM ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================= CTSUTRIMA ======================================================= */
- #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos (24UL) /*!< SUADJTRIM (Bit 24) */
- #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos (16UL) /*!< SUADJD (Bit 16) */
- #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk (0xff0000UL) /*!< SUADJD (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos (8UL) /*!< DACTRIM (Bit 8) */
- #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk (0xff00UL) /*!< DACTRIM (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos (0UL) /*!< RTRIM (Bit 0) */
- #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk (0xffUL) /*!< RTRIM (Bitfield-Mask: 0xff) */
-/* ======================================================= CTSUTRIMB ======================================================= */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos (24UL) /*!< TRESULT3 (Bit 24) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos (16UL) /*!< TRESULT2 (Bit 16) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk (0xff0000UL) /*!< TRESULT2 (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos (8UL) /*!< TRESULT1 (Bit 8) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk (0xff00UL) /*!< TRESULT1 (Bitfield-Mask: 0xff) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos (0UL) /*!< TRESULT0 (Bit 0) */
- #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk (0xffUL) /*!< TRESULT0 (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ R_FCACHE ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== FCACHEE ======================================================== */
- #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */
- #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */
-/* ======================================================= FCACHEIV ======================================================== */
- #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */
- #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */
-/* ========================================================= FLWT ========================================================== */
- #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */
- #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */
-/* ========================================================= FSAR ========================================================== */
- #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */
- #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */
- #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */
- #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_GLCDC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================= GR1_CLUT0 ======================================================= */
- #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */
- #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */
- #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */
- #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */
- #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */
-/* ======================================================= GR1_CLUT1 ======================================================= */
- #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */
- #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */
- #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */
- #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */
- #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */
-/* ======================================================= GR2_CLUT0 ======================================================= */
- #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */
- #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */
- #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */
- #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */
- #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */
-/* ======================================================= GR2_CLUT1 ======================================================= */
- #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */
- #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */
- #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */
- #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */
- #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */
- #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= GTWP ========================================================== */
- #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
- #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
- #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */
- #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */
- #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */
- #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */
- #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */
- #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */
-/* ========================================================= GTSTR ========================================================= */
- #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */
- #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
-/* ========================================================= GTSTP ========================================================= */
- #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */
- #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
-/* ========================================================= GTCLR ========================================================= */
- #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */
- #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */
-/* ========================================================= GTSSR ========================================================= */
- #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */
- #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */
- #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */
- #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */
- #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */
- #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */
- #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */
- #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */
- #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */
- #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */
- #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */
- #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */
- #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */
-/* ========================================================= GTPSR ========================================================= */
- #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */
- #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */
- #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */
- #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */
- #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */
- #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */
- #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */
- #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */
- #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */
- #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */
- #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */
- #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */
- #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */
-/* ========================================================= GTCSR ========================================================= */
- #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */
- #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */
- #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */
- #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */
- #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */
- #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */
- #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */
- #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */
- #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */
- #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */
- #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */
- #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */
- #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */
-/* ======================================================== GTUPSR ========================================================= */
- #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */
- #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */
- #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */
- #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */
- #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */
- #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */
- #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */
- #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */
- #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */
- #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */
- #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */
- #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */
- #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */
- #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */
-/* ======================================================== GTDNSR ========================================================= */
- #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */
- #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */
- #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */
- #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */
- #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */
- #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */
- #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */
- #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */
- #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */
- #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */
- #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */
- #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */
- #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */
- #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */
-/* ======================================================== GTICASR ======================================================== */
- #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */
- #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */
- #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */
- #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */
- #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */
- #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */
- #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */
- #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */
- #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */
- #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */
- #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */
- #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */
-/* ======================================================== GTICBSR ======================================================== */
- #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */
- #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */
- #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */
- #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */
- #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */
- #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */
- #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */
- #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */
- #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */
- #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */
- #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */
- #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */
-/* ========================================================= GTCR ========================================================== */
- #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */
- #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */
- #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */
- #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */
- #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */
- #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */
-/* ======================================================= GTUDDTYC ======================================================== */
- #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */
- #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */
- #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */
- #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */
- #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */
- #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */
- #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */
- #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */
- #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */
-/* ========================================================= GTIOR ========================================================= */
- #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */
- #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */
- #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */
- #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */
- #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */
- #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */
- #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */
- #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */
- #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */
- #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */
- #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */
- #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */
- #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */
- #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */
- #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */
- #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */
-/* ======================================================== GTINTAD ======================================================== */
- #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */
- #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */
- #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */
- #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */
- #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */
- #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */
-/* ========================================================= GTST ========================================================== */
- #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */
- #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */
- #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */
- #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */
- #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */
- #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */
- #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */
- #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */
- #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */
- #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */
- #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */
- #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */
- #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */
- #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */
- #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */
- #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */
- #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */
- #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */
- #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */
- #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */
- #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */
-/* ========================================================= GTBER ========================================================= */
- #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */
- #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */
- #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */
- #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */
- #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */
- #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */
- #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */
- #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */
- #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */
- #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */
- #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */
- #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */
- #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */
-/* ========================================================= GTITC ========================================================= */
- #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */
- #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */
- #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */
- #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */
- #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */
- #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */
- #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */
- #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */
- #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */
- #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */
- #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */
- #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */
- #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */
-/* ========================================================= GTCNT ========================================================= */
- #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */
- #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTCCR ========================================================= */
- #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */
- #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTPR ========================================================== */
- #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */
- #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTPBR ========================================================= */
- #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */
- #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GTPDBR ========================================================= */
- #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */
- #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GTADTRA ======================================================== */
- #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */
- #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GTADTRB ======================================================== */
- #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */
- #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= GTADTBRA ======================================================== */
- #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */
- #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= GTADTBRB ======================================================== */
- #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */
- #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= GTADTDBRA ======================================================= */
- #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */
- #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= GTADTDBRB ======================================================= */
- #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */
- #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== GTDTCR ========================================================= */
- #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */
- #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */
- #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */
- #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */
- #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */
-/* ========================================================= GTDVU ========================================================= */
- #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
- #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTDVD ========================================================= */
- #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */
- #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTDBU ========================================================= */
- #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
- #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTDBD ========================================================= */
- #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */
- #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= GTSOS ========================================================= */
- #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */
- #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */
-/* ======================================================== GTSOTR ========================================================= */
- #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */
- #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */
-/* ======================================================== GTICLF ========================================================= */
- #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */
- #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */
- #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */
- #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */
- #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */
- #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */
- #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */
- #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */
-/* ========================================================= GTPC ========================================================== */
- #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */
- #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */
- #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */
- #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */
-/* ======================================================== GTSECSR ======================================================== */
- #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */
- #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */
- #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */
- #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */
- #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */
- #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */
- #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */
- #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */
- #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */
- #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */
- #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */
-/* ======================================================== GTSECR ========================================================= */
- #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */
- #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */
- #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */
- #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */
- #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */
- #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */
- #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */
- #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_GTCLK ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== GTCLKCR ======================================================== */
- #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */
- #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_ODC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================= GTDLYCR1 ======================================================== */
- #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */
- #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */
- #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */
- #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */
- #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */
- #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */
-/* ======================================================= GTDLYCR2 ======================================================== */
- #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */
- #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */
- #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */
- #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */
- #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */
- #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_OPS ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= OPSCR ========================================================= */
- #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
- #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
- #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
- #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */
- #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */
- #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
- #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */
- #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */
- #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */
- #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */
- #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */
- #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */
- #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */
- #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */
- #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */
- #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */
- #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */
- #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */
- #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */
- #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */
- #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_GPT_POEG0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= POEGG ========================================================= */
- #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
- #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
- #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
- #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */
- #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */
- #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */
- #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */
- #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */
- #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */
- #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */
- #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */
- #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */
- #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */
- #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */
- #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_ICU ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= IRQCR ========================================================= */
- #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */
- #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */
- #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */
- #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */
- #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */
-/* ========================================================= NMISR ========================================================= */
- #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */
- #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */
- #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */
- #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */
- #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */
- #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */
- #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */
- #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */
- #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */
- #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */
- #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */
- #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */
- #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */
- #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */
- #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */
- #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */
-/* ========================================================= NMIER ========================================================= */
- #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */
- #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */
- #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */
- #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */
- #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */
- #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */
- #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */
- #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */
- #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */
- #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */
- #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */
- #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */
- #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */
- #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */
- #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */
-/* ======================================================== NMICLR ========================================================= */
- #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */
- #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */
- #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */
- #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */
- #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */
- #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */
- #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */
- #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */
- #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */
- #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */
- #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */
- #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */
- #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */
- #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */
- #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */
-/* ========================================================= NMICR ========================================================= */
- #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */
- #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */
- #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */
- #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */
- #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */
- #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */
-/* ========================================================= IELSR ========================================================= */
- #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */
- #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */
- #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
- #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
- #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */
- #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */
-/* ========================================================= DELSR ========================================================= */
- #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
- #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
- #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */
- #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */
-/* ======================================================== SELSR0 ========================================================= */
- #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */
- #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */
-/* ========================================================= WUPEN ========================================================= */
- #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */
- #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */
- #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */
- #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */
- #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */
- #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */
- #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */
- #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */
- #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */
- #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */
- #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */
- #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */
- #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */
- #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */
- #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */
- #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */
- #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */
-/* ======================================================== WUPEN1 ========================================================= */
- #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */
- #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */
- #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */
- #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */
- #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */
-/* ========================================================= IELEN ========================================================= */
- #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */
- #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */
- #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */
- #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_IIC0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= ICCR1 ========================================================= */
- #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */
- #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */
- #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */
- #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */
- #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */
- #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */
- #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */
- #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */
- #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */
-/* ========================================================= ICCR2 ========================================================= */
- #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */
- #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */
- #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */
- #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */
- #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */
- #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */
- #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */
-/* ========================================================= ICMR1 ========================================================= */
- #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */
- #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */
- #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */
- #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */
- #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */
- #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */
-/* ========================================================= ICMR2 ========================================================= */
- #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */
- #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */
- #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */
- #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */
- #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */
- #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */
- #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */
-/* ========================================================= ICMR3 ========================================================= */
- #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */
- #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */
- #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */
- #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */
- #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */
- #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */
- #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */
- #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */
-/* ========================================================= ICFER ========================================================= */
- #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */
- #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */
- #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */
- #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */
- #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */
- #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */
- #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */
- #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */
- #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */
-/* ========================================================= ICSER ========================================================= */
- #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */
- #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */
- #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */
- #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */
- #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */
- #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */
- #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */
-/* ========================================================= ICIER ========================================================= */
- #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */
- #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */
- #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */
- #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */
- #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */
- #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */
- #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */
- #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */
- #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */
-/* ========================================================= ICSR1 ========================================================= */
- #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */
- #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */
- #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */
- #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */
- #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */
- #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */
- #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */
-/* ========================================================= ICSR2 ========================================================= */
- #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
- #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */
- #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */
- #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */
- #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */
- #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */
- #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */
- #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */
- #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */
-/* ========================================================= ICBRL ========================================================= */
- #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */
- #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */
-/* ========================================================= ICBRH ========================================================= */
- #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */
- #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */
-/* ========================================================= ICDRT ========================================================= */
- #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */
- #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */
-/* ========================================================= ICDRR ========================================================= */
- #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */
- #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */
-/* ========================================================= ICWUR ========================================================= */
- #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */
- #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */
- #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */
- #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */
- #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */
- #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */
-/* ======================================================== ICWUR2 ========================================================= */
- #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */
- #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */
- #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */
- #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */
- #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_IRDA ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= IRCR ========================================================== */
- #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */
- #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */
- #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */
- #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */
- #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */
- #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_IWDT ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== IWDTRR ========================================================= */
- #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */
- #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */
-/* ======================================================== IWDTSR ========================================================= */
- #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
- #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
- #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
- #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
- #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
- #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
-
-/* =========================================================================================================================== */
-/* ================ R_JPEG ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= JCMOD ========================================================= */
- #define R_JPEG_JCMOD_DSP_Pos (3UL) /*!< DSP (Bit 3) */
- #define R_JPEG_JCMOD_DSP_Msk (0x8UL) /*!< DSP (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCMOD_REDU_Pos (0UL) /*!< REDU (Bit 0) */
- #define R_JPEG_JCMOD_REDU_Msk (0x7UL) /*!< REDU (Bitfield-Mask: 0x07) */
-/* ========================================================= JCCMD ========================================================= */
- #define R_JPEG_JCCMD_BRST_Pos (7UL) /*!< BRST (Bit 7) */
- #define R_JPEG_JCCMD_BRST_Msk (0x80UL) /*!< BRST (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCCMD_JEND_Pos (2UL) /*!< JEND (Bit 2) */
- #define R_JPEG_JCCMD_JEND_Msk (0x4UL) /*!< JEND (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCCMD_JRST_Pos (1UL) /*!< JRST (Bit 1) */
- #define R_JPEG_JCCMD_JRST_Msk (0x2UL) /*!< JRST (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCCMD_JSRT_Pos (0UL) /*!< JSRT (Bit 0) */
- #define R_JPEG_JCCMD_JSRT_Msk (0x1UL) /*!< JSRT (Bitfield-Mask: 0x01) */
-/* ========================================================= JCQTN ========================================================= */
- #define R_JPEG_JCQTN_QT3_Pos (4UL) /*!< QT3 (Bit 4) */
- #define R_JPEG_JCQTN_QT3_Msk (0x30UL) /*!< QT3 (Bitfield-Mask: 0x03) */
- #define R_JPEG_JCQTN_QT2_Pos (2UL) /*!< QT2 (Bit 2) */
- #define R_JPEG_JCQTN_QT2_Msk (0xcUL) /*!< QT2 (Bitfield-Mask: 0x03) */
- #define R_JPEG_JCQTN_QT1_Pos (0UL) /*!< QT1 (Bit 0) */
- #define R_JPEG_JCQTN_QT1_Msk (0x3UL) /*!< QT1 (Bitfield-Mask: 0x03) */
-/* ========================================================= JCHTN ========================================================= */
- #define R_JPEG_JCHTN_HTA3_Pos (5UL) /*!< HTA3 (Bit 5) */
- #define R_JPEG_JCHTN_HTA3_Msk (0x20UL) /*!< HTA3 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCHTN_HTD3_Pos (4UL) /*!< HTD3 (Bit 4) */
- #define R_JPEG_JCHTN_HTD3_Msk (0x10UL) /*!< HTD3 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCHTN_HTA2_Pos (3UL) /*!< HTA2 (Bit 3) */
- #define R_JPEG_JCHTN_HTA2_Msk (0x8UL) /*!< HTA2 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCHTN_HTD2_Pos (2UL) /*!< HTD2 (Bit 2) */
- #define R_JPEG_JCHTN_HTD2_Msk (0x4UL) /*!< HTD2 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCHTN_HTA1_Pos (1UL) /*!< HTA1 (Bit 1) */
- #define R_JPEG_JCHTN_HTA1_Msk (0x2UL) /*!< HTA1 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JCHTN_HTD1_Pos (0UL) /*!< HTD1 (Bit 0) */
- #define R_JPEG_JCHTN_HTD1_Msk (0x1UL) /*!< HTD1 (Bitfield-Mask: 0x01) */
-/* ======================================================== JCDRIU ========================================================= */
- #define R_JPEG_JCDRIU_DRIU_Pos (0UL) /*!< DRIU (Bit 0) */
- #define R_JPEG_JCDRIU_DRIU_Msk (0xffUL) /*!< DRIU (Bitfield-Mask: 0xff) */
-/* ======================================================== JCDRID ========================================================= */
- #define R_JPEG_JCDRID_DRID_Pos (0UL) /*!< DRID (Bit 0) */
- #define R_JPEG_JCDRID_DRID_Msk (0xffUL) /*!< DRID (Bitfield-Mask: 0xff) */
-/* ======================================================== JCVSZU ========================================================= */
- #define R_JPEG_JCVSZU_VSZU_Pos (0UL) /*!< VSZU (Bit 0) */
- #define R_JPEG_JCVSZU_VSZU_Msk (0xffUL) /*!< VSZU (Bitfield-Mask: 0xff) */
-/* ======================================================== JCVSZD ========================================================= */
- #define R_JPEG_JCVSZD_VSZD_Pos (0UL) /*!< VSZD (Bit 0) */
- #define R_JPEG_JCVSZD_VSZD_Msk (0xffUL) /*!< VSZD (Bitfield-Mask: 0xff) */
-/* ======================================================== JCHSZU ========================================================= */
- #define R_JPEG_JCHSZU_HSZU_Pos (0UL) /*!< HSZU (Bit 0) */
- #define R_JPEG_JCHSZU_HSZU_Msk (0xffUL) /*!< HSZU (Bitfield-Mask: 0xff) */
-/* ======================================================== JCHSZD ========================================================= */
- #define R_JPEG_JCHSZD_HSZD_Pos (0UL) /*!< HSZD (Bit 0) */
- #define R_JPEG_JCHSZD_HSZD_Msk (0xffUL) /*!< HSZD (Bitfield-Mask: 0xff) */
-/* ======================================================== JCDTCU ========================================================= */
- #define R_JPEG_JCDTCU_DCU_Pos (0UL) /*!< DCU (Bit 0) */
- #define R_JPEG_JCDTCU_DCU_Msk (0xffUL) /*!< DCU (Bitfield-Mask: 0xff) */
-/* ======================================================== JCDTCM ========================================================= */
- #define R_JPEG_JCDTCM_DCM_Pos (0UL) /*!< DCM (Bit 0) */
- #define R_JPEG_JCDTCM_DCM_Msk (0xffUL) /*!< DCM (Bitfield-Mask: 0xff) */
-/* ======================================================== JCDTCD ========================================================= */
- #define R_JPEG_JCDTCD_DCD_Pos (0UL) /*!< DCD (Bit 0) */
- #define R_JPEG_JCDTCD_DCD_Msk (0xffUL) /*!< DCD (Bitfield-Mask: 0xff) */
-/* ======================================================== JINTE0 ========================================================= */
- #define R_JPEG_JINTE0_INT7_Pos (7UL) /*!< INT7 (Bit 7) */
- #define R_JPEG_JINTE0_INT7_Msk (0x80UL) /*!< INT7 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE0_INT6_Pos (6UL) /*!< INT6 (Bit 6) */
- #define R_JPEG_JINTE0_INT6_Msk (0x40UL) /*!< INT6 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE0_INT5_Pos (5UL) /*!< INT5 (Bit 5) */
- #define R_JPEG_JINTE0_INT5_Msk (0x20UL) /*!< INT5 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE0_INT3_Pos (3UL) /*!< INT3 (Bit 3) */
- #define R_JPEG_JINTE0_INT3_Msk (0x8UL) /*!< INT3 (Bitfield-Mask: 0x01) */
-/* ======================================================== JINTS0 ========================================================= */
- #define R_JPEG_JINTS0_INS6_Pos (6UL) /*!< INS6 (Bit 6) */
- #define R_JPEG_JINTS0_INS6_Msk (0x40UL) /*!< INS6 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS0_INS5_Pos (5UL) /*!< INS5 (Bit 5) */
- #define R_JPEG_JINTS0_INS5_Msk (0x20UL) /*!< INS5 (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS0_INS3_Pos (3UL) /*!< INS3 (Bit 3) */
- #define R_JPEG_JINTS0_INS3_Msk (0x8UL) /*!< INS3 (Bitfield-Mask: 0x01) */
-/* ======================================================== JCDERR ========================================================= */
- #define R_JPEG_JCDERR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
- #define R_JPEG_JCDERR_ERR_Msk (0xfUL) /*!< ERR (Bitfield-Mask: 0x0f) */
-/* ========================================================= JCRST ========================================================= */
- #define R_JPEG_JCRST_RST_Pos (0UL) /*!< RST (Bit 0) */
- #define R_JPEG_JCRST_RST_Msk (0x1UL) /*!< RST (Bitfield-Mask: 0x01) */
-/* ======================================================== JIFECNT ======================================================== */
- #define R_JPEG_JIFECNT_JOUTSWAP_Pos (8UL) /*!< JOUTSWAP (Bit 8) */
- #define R_JPEG_JIFECNT_JOUTSWAP_Msk (0x700UL) /*!< JOUTSWAP (Bitfield-Mask: 0x07) */
- #define R_JPEG_JIFECNT_DINRINI_Pos (6UL) /*!< DINRINI (Bit 6) */
- #define R_JPEG_JIFECNT_DINRINI_Msk (0x40UL) /*!< DINRINI (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFECNT_DINRCMD_Pos (5UL) /*!< DINRCMD (Bit 5) */
- #define R_JPEG_JIFECNT_DINRCMD_Msk (0x20UL) /*!< DINRCMD (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFECNT_DINLC_Pos (4UL) /*!< DINLC (Bit 4) */
- #define R_JPEG_JIFECNT_DINLC_Msk (0x10UL) /*!< DINLC (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFECNT_DINSWAP_Pos (0UL) /*!< DINSWAP (Bit 0) */
- #define R_JPEG_JIFECNT_DINSWAP_Msk (0x7UL) /*!< DINSWAP (Bitfield-Mask: 0x07) */
-/* ======================================================== JIFESA ========================================================= */
- #define R_JPEG_JIFESA_ESA_Pos (0UL) /*!< ESA (Bit 0) */
- #define R_JPEG_JIFESA_ESA_Msk (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= JIFESOFST ======================================================= */
- #define R_JPEG_JIFESOFST_ESMW_Pos (0UL) /*!< ESMW (Bit 0) */
- #define R_JPEG_JIFESOFST_ESMW_Msk (0x7fffUL) /*!< ESMW (Bitfield-Mask: 0x7fff) */
-/* ======================================================== JIFEDA ========================================================= */
- #define R_JPEG_JIFEDA_EDA_Pos (0UL) /*!< EDA (Bit 0) */
- #define R_JPEG_JIFEDA_EDA_Msk (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== JIFESLC ======================================================== */
- #define R_JPEG_JIFESLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */
- #define R_JPEG_JIFESLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */
-/* ======================================================== JIFDCNT ======================================================== */
- #define R_JPEG_JIFDCNT_VINTER_Pos (28UL) /*!< VINTER (Bit 28) */
- #define R_JPEG_JIFDCNT_VINTER_Msk (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03) */
- #define R_JPEG_JIFDCNT_HINTER_Pos (26UL) /*!< HINTER (Bit 26) */
- #define R_JPEG_JIFDCNT_HINTER_Msk (0xc000000UL) /*!< HINTER (Bitfield-Mask: 0x03) */
- #define R_JPEG_JIFDCNT_OPF_Pos (24UL) /*!< OPF (Bit 24) */
- #define R_JPEG_JIFDCNT_OPF_Msk (0x3000000UL) /*!< OPF (Bitfield-Mask: 0x03) */
- #define R_JPEG_JIFDCNT_JINRINI_Pos (14UL) /*!< JINRINI (Bit 14) */
- #define R_JPEG_JIFDCNT_JINRINI_Msk (0x4000UL) /*!< JINRINI (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_JINRCMD_Pos (13UL) /*!< JINRCMD (Bit 13) */
- #define R_JPEG_JIFDCNT_JINRCMD_Msk (0x2000UL) /*!< JINRCMD (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_JINC_Pos (12UL) /*!< JINC (Bit 12) */
- #define R_JPEG_JIFDCNT_JINC_Msk (0x1000UL) /*!< JINC (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_JINSWAP_Pos (8UL) /*!< JINSWAP (Bit 8) */
- #define R_JPEG_JIFDCNT_JINSWAP_Msk (0x700UL) /*!< JINSWAP (Bitfield-Mask: 0x07) */
- #define R_JPEG_JIFDCNT_DOUTRINI_Pos (6UL) /*!< DOUTRINI (Bit 6) */
- #define R_JPEG_JIFDCNT_DOUTRINI_Msk (0x40UL) /*!< DOUTRINI (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_DOUTRCMD_Pos (5UL) /*!< DOUTRCMD (Bit 5) */
- #define R_JPEG_JIFDCNT_DOUTRCMD_Msk (0x20UL) /*!< DOUTRCMD (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_DOUTLC_Pos (4UL) /*!< DOUTLC (Bit 4) */
- #define R_JPEG_JIFDCNT_DOUTLC_Msk (0x10UL) /*!< DOUTLC (Bitfield-Mask: 0x01) */
- #define R_JPEG_JIFDCNT_DOUTSWAP_Pos (0UL) /*!< DOUTSWAP (Bit 0) */
- #define R_JPEG_JIFDCNT_DOUTSWAP_Msk (0x7UL) /*!< DOUTSWAP (Bitfield-Mask: 0x07) */
-/* ======================================================== JIFDSA ========================================================= */
- #define R_JPEG_JIFDSA_DSA_Pos (0UL) /*!< DSA (Bit 0) */
- #define R_JPEG_JIFDSA_DSA_Msk (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= JIFDDOFST ======================================================= */
- #define R_JPEG_JIFDDOFST_DDMW_Pos (0UL) /*!< DDMW (Bit 0) */
- #define R_JPEG_JIFDDOFST_DDMW_Msk (0x7fffUL) /*!< DDMW (Bitfield-Mask: 0x7fff) */
-/* ======================================================== JIFDDA ========================================================= */
- #define R_JPEG_JIFDDA_DDA_Pos (0UL) /*!< DDA (Bit 0) */
- #define R_JPEG_JIFDDA_DDA_Msk (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== JIFDSDC ======================================================== */
- #define R_JPEG_JIFDSDC_JDATAS_Pos (0UL) /*!< JDATAS (Bit 0) */
- #define R_JPEG_JIFDSDC_JDATAS_Msk (0xffffUL) /*!< JDATAS (Bitfield-Mask: 0xffff) */
-/* ======================================================== JIFDDLC ======================================================== */
- #define R_JPEG_JIFDDLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */
- #define R_JPEG_JIFDDLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */
-/* ======================================================== JIFDADT ======================================================== */
- #define R_JPEG_JIFDADT_ALPHA_Pos (0UL) /*!< ALPHA (Bit 0) */
- #define R_JPEG_JIFDADT_ALPHA_Msk (0xffUL) /*!< ALPHA (Bitfield-Mask: 0xff) */
-/* ======================================================== JINTE1 ========================================================= */
- #define R_JPEG_JINTE1_CBTEN_Pos (6UL) /*!< CBTEN (Bit 6) */
- #define R_JPEG_JINTE1_CBTEN_Msk (0x40UL) /*!< CBTEN (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE1_DINLEN_Pos (5UL) /*!< DINLEN (Bit 5) */
- #define R_JPEG_JINTE1_DINLEN_Msk (0x20UL) /*!< DINLEN (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE1_DBTEN_Pos (2UL) /*!< DBTEN (Bit 2) */
- #define R_JPEG_JINTE1_DBTEN_Msk (0x4UL) /*!< DBTEN (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE1_JINEN_Pos (1UL) /*!< JINEN (Bit 1) */
- #define R_JPEG_JINTE1_JINEN_Msk (0x2UL) /*!< JINEN (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTE1_DOUTLEN_Pos (0UL) /*!< DOUTLEN (Bit 0) */
- #define R_JPEG_JINTE1_DOUTLEN_Msk (0x1UL) /*!< DOUTLEN (Bitfield-Mask: 0x01) */
-/* ======================================================== JINTS1 ========================================================= */
- #define R_JPEG_JINTS1_CBTF_Pos (6UL) /*!< CBTF (Bit 6) */
- #define R_JPEG_JINTS1_CBTF_Msk (0x40UL) /*!< CBTF (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS1_DINLF_Pos (5UL) /*!< DINLF (Bit 5) */
- #define R_JPEG_JINTS1_DINLF_Msk (0x20UL) /*!< DINLF (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS1_DBTF_Pos (2UL) /*!< DBTF (Bit 2) */
- #define R_JPEG_JINTS1_DBTF_Msk (0x4UL) /*!< DBTF (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS1_JINF_Pos (1UL) /*!< JINF (Bit 1) */
- #define R_JPEG_JINTS1_JINF_Msk (0x2UL) /*!< JINF (Bitfield-Mask: 0x01) */
- #define R_JPEG_JINTS1_DOUTLF_Pos (0UL) /*!< DOUTLF (Bit 0) */
- #define R_JPEG_JINTS1_DOUTLF_Msk (0x1UL) /*!< DOUTLF (Bitfield-Mask: 0x01) */
-/* ======================================================== JCQTBL0 ======================================================== */
-/* ======================================================== JCQTBL1 ======================================================== */
-/* ======================================================== JCQTBL2 ======================================================== */
-/* ======================================================== JCQTBL3 ======================================================== */
-/* ======================================================== JCHTBD0 ======================================================== */
-/* ======================================================== JCHTBD1 ======================================================== */
-/* ======================================================== JCHTBA0 ======================================================== */
-/* ======================================================== JCHTBA1 ======================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_KINT ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= KRCTL ========================================================= */
- #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */
- #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */
- #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */
- #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */
-/* ========================================================== KRF ========================================================== */
- #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */
- #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */
- #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */
- #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */
- #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */
- #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */
- #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */
- #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */
- #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */
-/* ========================================================== KRM ========================================================== */
- #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */
- #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */
- #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */
- #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */
- #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */
- #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */
- #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */
- #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */
- #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */
- #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_I3C0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= PRTS ========================================================== */
- #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
- #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */
-/* ========================================================= CECTL ========================================================= */
- #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */
- #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */
-/* ========================================================= BCTL ========================================================== */
- #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */
- #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */
- #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */
- #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */
- #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */
- #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */
- #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */
-/* ======================================================== MSDVAD ========================================================= */
- #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */
- #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */
- #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */
-/* ======================================================== RSTCTL ========================================================= */
- #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */
- #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */
- #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */
- #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */
- #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */
- #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */
- #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */
- #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */
- #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */
- #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */
-/* ========================================================= PRSST ========================================================= */
- #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */
- #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */
- #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */
- #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */
- #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */
- #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */
-/* ========================================================= INST ========================================================== */
- #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */
- #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */
-/* ========================================================= INSTE ========================================================= */
- #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */
- #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */
-/* ========================================================= INIE ========================================================== */
- #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */
- #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */
-/* ======================================================== INSTFC ========================================================= */
- #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */
- #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */
-/* ========================================================= DVCT ========================================================== */
- #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */
- #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */
-/* ======================================================== IBINCTL ======================================================== */
- #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */
- #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */
- #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */
- #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */
- #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */
- #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */
-/* ========================================================= BFCTL ========================================================= */
- #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */
- #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */
- #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */
- #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */
- #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */
- #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */
- #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */
- #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */
-/* ========================================================= SVCTL ========================================================= */
- #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */
- #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */
- #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */
- #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */
- #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */
- #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */
-/* ======================================================= REFCKCTL ======================================================== */
- #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */
- #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */
-/* ========================================================= STDBR ========================================================= */
- #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */
- #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */
- #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */
- #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */
- #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */
- #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */
- #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */
- #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */
- #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */
- #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */
-/* ========================================================= EXTBR ========================================================= */
- #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */
- #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */
- #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */
- #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */
- #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */
- #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */
- #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */
- #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */
-/* ======================================================== BFRECDT ======================================================== */
- #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */
- #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */
-/* ======================================================== BAVLCDT ======================================================== */
- #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */
- #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */
-/* ======================================================== BIDLCDT ======================================================== */
- #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */
- #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */
-/* ======================================================== OUTCTL ========================================================= */
- #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */
- #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */
- #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */
- #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */
- #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */
- #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */
- #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */
- #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */
- #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */
- #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */
- #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */
- #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */
-/* ========================================================= INCTL ========================================================= */
- #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */
- #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */
- #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */
- #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */
-/* ======================================================== TMOCTL ========================================================= */
- #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */
- #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */
- #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */
- #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */
- #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */
- #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */
- #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */
- #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */
-/* ======================================================== ACKCTL ========================================================= */
- #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */
- #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */
- #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */
- #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */
- #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */
- #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */
-/* ======================================================= SCSTRCTL ======================================================== */
- #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */
- #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */
- #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */
-/* ======================================================= SCSTLCTL ======================================================== */
- #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */
- #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */
- #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */
- #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */
- #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */
- #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */
- #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */
- #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */
-/* ======================================================== SVTDLG0 ======================================================== */
- #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */
- #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */
-/* ======================================================== CNDCTL ========================================================= */
- #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */
- #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */
- #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */
- #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */
- #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */
- #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */
-/* ======================================================== NCMDQP ========================================================= */
-/* ======================================================== NRSPQP ========================================================= */
-/* ======================================================== NTDTBP0 ======================================================== */
-/* ======================================================== NIBIQP ========================================================= */
-/* ========================================================= NRSQP ========================================================= */
-/* ======================================================== NQTHCTL ======================================================== */
- #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */
- #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */
- #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */
- #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */
- #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */
-/* ======================================================= NTBTHCTL0 ======================================================= */
- #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */
- #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */
- #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */
- #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */
- #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */
- #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */
- #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */
- #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */
-/* ======================================================= NRQTHCTL ======================================================== */
- #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */
- #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */
-/* ========================================================== BST ========================================================== */
- #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */
- #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */
- #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */
- #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */
- #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */
- #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */
- #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */
- #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */
-/* ========================================================= BSTE ========================================================== */
- #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */
- #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */
- #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */
- #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */
- #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */
- #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */
- #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */
- #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */
-/* ========================================================== BIE ========================================================== */
- #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */
- #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */
- #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */
- #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */
- #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */
- #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */
- #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */
- #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */
-/* ========================================================= BSTFC ========================================================= */
- #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */
- #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */
- #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */
- #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */
- #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */
- #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */
- #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */
- #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */
-/* ========================================================= NTST ========================================================== */
- #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */
- #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */
- #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */
- #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */
- #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */
- #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */
- #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */
- #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */
- #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */
-/* ========================================================= NTSTE ========================================================= */
- #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */
- #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */
- #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */
- #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */
- #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */
- #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */
- #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */
- #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */
- #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */
-/* ========================================================= NTIE ========================================================== */
- #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */
- #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */
- #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */
- #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */
- #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */
- #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */
- #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */
- #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */
- #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */
-/* ======================================================== NTSTFC ========================================================= */
- #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */
- #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */
- #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */
- #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */
- #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */
- #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */
- #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */
- #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */
- #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */
- #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */
-/* ========================================================= BCST ========================================================== */
- #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */
- #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */
- #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */
- #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */
- #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */
-/* ========================================================= SVST ========================================================== */
- #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */
- #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */
- #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */
- #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */
- #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */
- #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */
-/* ======================================================== DATBAS0 ======================================================== */
- #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
-/* ======================================================== DATBAS1 ======================================================== */
- #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
-/* ======================================================== DATBAS2 ======================================================== */
- #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
-/* ======================================================== DATBAS3 ======================================================== */
- #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
-/* ======================================================= EXDATBAS ======================================================== */
- #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */
- #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */
- #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */
- #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */
- #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */
- #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */
- #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */
- #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */
-/* ======================================================= SDATBAS0 ======================================================== */
- #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
- #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
- #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
- #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
- #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
- #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
-/* ======================================================= SDATBAS1 ======================================================== */
- #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
- #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
- #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
- #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
- #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
- #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
-/* ======================================================= SDATBAS2 ======================================================== */
- #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
- #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
- #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
- #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
- #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
- #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
- #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
-/* ======================================================== MSDCT0 ========================================================= */
- #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
-/* ======================================================== MSDCT1 ========================================================= */
- #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
-/* ======================================================== MSDCT2 ========================================================= */
- #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
-/* ======================================================== MSDCT3 ========================================================= */
- #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
-/* ========================================================= SVDCT ========================================================= */
- #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
- #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
- #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */
- #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */
- #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */
- #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */
- #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */
- #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */
-/* ======================================================= SDCTPIDL ======================================================== */
-/* ======================================================= SDCTPIDH ======================================================== */
-/* ======================================================== SVDVAD0 ======================================================== */
- #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */
- #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */
- #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */
- #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */
- #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */
- #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */
- #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */
-/* ======================================================== CSECMD ========================================================= */
- #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */
- #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */
- #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */
- #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */
- #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */
- #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */
-/* ======================================================== CEACTST ======================================================== */
- #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */
- #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */
-/* ========================================================= CMWLG ========================================================= */
- #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */
- #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */
-/* ========================================================= CMRLG ========================================================= */
- #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */
- #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */
- #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */
- #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */
-/* ======================================================== CETSTMD ======================================================== */
- #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */
- #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */
-/* ======================================================== CGDVST ========================================================= */
- #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */
- #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */
- #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */
- #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */
- #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */
- #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */
- #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */
- #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */
-/* ======================================================== CMDSPW ========================================================= */
- #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */
- #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */
-/* ======================================================== CMDSPR ========================================================= */
- #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */
- #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */
- #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */
- #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */
-/* ======================================================== CMDSPT ========================================================= */
- #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */
- #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */
- #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */
- #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */
-/* ========================================================= CETSM ========================================================= */
- #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */
- #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */
- #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */
- #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */
-/* ======================================================== BITCNT ========================================================= */
- #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */
- #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */
- #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */
- #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */
-/* ======================================================== NQSTLV ========================================================= */
- #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */
- #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */
- #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */
- #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */
- #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */
- #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */
-/* ======================================================= NDBSTLV0 ======================================================== */
- #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */
- #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */
- #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */
- #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */
-/* ======================================================= NRSQSTLV ======================================================== */
- #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */
- #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */
-/* ======================================================== PRSTDBG ======================================================== */
- #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */
- #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */
- #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */
- #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */
- #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */
- #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */
- #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */
- #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */
-/* ======================================================= MSERRCNT ======================================================== */
- #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */
- #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ R_MMF ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= MMSFR ========================================================= */
- #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */
- #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */
- #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= MMEN ========================================================== */
- #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */
- #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */
- #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_MMPU ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_SMPU ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== SMPUCTL ======================================================== */
- #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
- #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */
- #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
- #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_MPU_SPMON ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_MSTP ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== MSTPCRA ======================================================== */
- #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */
- #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */
- #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */
- #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */
-/* ======================================================== MSTPCRB ======================================================== */
- #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */
- #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */
- #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */
- #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */
- #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */
- #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */
- #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */
- #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */
- #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */
- #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */
- #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */
- #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */
- #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */
- #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */
- #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */
- #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */
- #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */
- #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */
- #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */
- #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */
- #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */
- #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */
- #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */
- #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */
- #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */
- #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */
-/* ======================================================== MSTPCRC ======================================================== */
- #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */
- #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */
- #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */
- #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */
- #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */
- #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */
- #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */
- #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */
- #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */
- #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */
- #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */
- #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */
- #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */
- #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */
- #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */
- #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */
- #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */
- #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */
- #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */
- #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */
-/* ======================================================== MSTPCRD ======================================================== */
- #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */
- #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */
- #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */
- #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */
- #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */
- #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */
- #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */
- #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */
- #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */
- #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */
- #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */
- #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */
- #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */
- #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */
- #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */
- #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */
- #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */
- #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */
- #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */
- #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */
- #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */
- #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */
- #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */
- #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */
- #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */
-/* ======================================================== MSTPCRE ======================================================== */
- #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */
- #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */
- #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */
- #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */
- #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */
- #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */
- #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */
- #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */
- #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */
- #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */
- #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */
- #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */
- #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */
- #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */
- #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_OPAMP ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= AMPMC ========================================================= */
- #define R_OPAMP_AMPMC_AMPSP_Pos (7UL) /*!< AMPSP (Bit 7) */
- #define R_OPAMP_AMPMC_AMPSP_Msk (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01) */
- #define R_OPAMP_AMPMC_AMPPC_Pos (0UL) /*!< AMPPC (Bit 0) */
- #define R_OPAMP_AMPMC_AMPPC_Msk (0x1UL) /*!< AMPPC (Bitfield-Mask: 0x01) */
-/* ======================================================== AMPTRM ========================================================= */
- #define R_OPAMP_AMPTRM_AMPTRM_Pos (0UL) /*!< AMPTRM (Bit 0) */
- #define R_OPAMP_AMPTRM_AMPTRM_Msk (0x3UL) /*!< AMPTRM (Bitfield-Mask: 0x03) */
-/* ======================================================== AMPTRS ========================================================= */
- #define R_OPAMP_AMPTRS_AMPTRS_Pos (0UL) /*!< AMPTRS (Bit 0) */
- #define R_OPAMP_AMPTRS_AMPTRS_Msk (0x3UL) /*!< AMPTRS (Bitfield-Mask: 0x03) */
-/* ========================================================= AMPC ========================================================== */
- #define R_OPAMP_AMPC_IREFE_Pos (7UL) /*!< IREFE (Bit 7) */
- #define R_OPAMP_AMPC_IREFE_Msk (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01) */
- #define R_OPAMP_AMPC_AMPE_Pos (0UL) /*!< AMPE (Bit 0) */
- #define R_OPAMP_AMPC_AMPE_Msk (0x1UL) /*!< AMPE (Bitfield-Mask: 0x01) */
-/* ======================================================== AMPMON ========================================================= */
- #define R_OPAMP_AMPMON_AMPMON_Pos (0UL) /*!< AMPMON (Bit 0) */
- #define R_OPAMP_AMPMON_AMPMON_Msk (0x1UL) /*!< AMPMON (Bitfield-Mask: 0x01) */
-/* ======================================================== AMPCPC ========================================================= */
- #define R_OPAMP_AMPCPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */
- #define R_OPAMP_AMPCPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */
-/* ======================================================== AMPUOTE ======================================================== */
- #define R_OPAMP_AMPUOTE_AMPTE_Pos (0UL) /*!< AMPTE (Bit 0) */
- #define R_OPAMP_AMPUOTE_AMPTE_Msk (0x1UL) /*!< AMPTE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_PDC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= PCCR0 ========================================================= */
- #define R_PDC_PCCR0_EDS_Pos (14UL) /*!< EDS (Bit 14) */
- #define R_PDC_PCCR0_EDS_Msk (0x4000UL) /*!< EDS (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_PCKDIV_Pos (11UL) /*!< PCKDIV (Bit 11) */
- #define R_PDC_PCCR0_PCKDIV_Msk (0x3800UL) /*!< PCKDIV (Bitfield-Mask: 0x07) */
- #define R_PDC_PCCR0_PCKOE_Pos (10UL) /*!< PCKOE (Bit 10) */
- #define R_PDC_PCCR0_PCKOE_Msk (0x400UL) /*!< PCKOE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_HERIE_Pos (9UL) /*!< HERIE (Bit 9) */
- #define R_PDC_PCCR0_HERIE_Msk (0x200UL) /*!< HERIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_VERIE_Pos (8UL) /*!< VERIE (Bit 8) */
- #define R_PDC_PCCR0_VERIE_Msk (0x100UL) /*!< VERIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_UDRIE_Pos (7UL) /*!< UDRIE (Bit 7) */
- #define R_PDC_PCCR0_UDRIE_Msk (0x80UL) /*!< UDRIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_OVIE_Pos (6UL) /*!< OVIE (Bit 6) */
- #define R_PDC_PCCR0_OVIE_Msk (0x40UL) /*!< OVIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_FEIE_Pos (5UL) /*!< FEIE (Bit 5) */
- #define R_PDC_PCCR0_FEIE_Msk (0x20UL) /*!< FEIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_DFIE_Pos (4UL) /*!< DFIE (Bit 4) */
- #define R_PDC_PCCR0_DFIE_Msk (0x10UL) /*!< DFIE (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_PRST_Pos (3UL) /*!< PRST (Bit 3) */
- #define R_PDC_PCCR0_PRST_Msk (0x8UL) /*!< PRST (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_HPS_Pos (2UL) /*!< HPS (Bit 2) */
- #define R_PDC_PCCR0_HPS_Msk (0x4UL) /*!< HPS (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_VPS_Pos (1UL) /*!< VPS (Bit 1) */
- #define R_PDC_PCCR0_VPS_Msk (0x2UL) /*!< VPS (Bitfield-Mask: 0x01) */
- #define R_PDC_PCCR0_PCKE_Pos (0UL) /*!< PCKE (Bit 0) */
- #define R_PDC_PCCR0_PCKE_Msk (0x1UL) /*!< PCKE (Bitfield-Mask: 0x01) */
-/* ========================================================= PCCR1 ========================================================= */
- #define R_PDC_PCCR1_PCE_Pos (0UL) /*!< PCE (Bit 0) */
- #define R_PDC_PCCR1_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
-/* ========================================================= PCSR ========================================================== */
- #define R_PDC_PCSR_HERF_Pos (6UL) /*!< HERF (Bit 6) */
- #define R_PDC_PCSR_HERF_Msk (0x40UL) /*!< HERF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_VERF_Pos (5UL) /*!< VERF (Bit 5) */
- #define R_PDC_PCSR_VERF_Msk (0x20UL) /*!< VERF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */
- #define R_PDC_PCSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_OVRF_Pos (3UL) /*!< OVRF (Bit 3) */
- #define R_PDC_PCSR_OVRF_Msk (0x8UL) /*!< OVRF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_FEF_Pos (2UL) /*!< FEF (Bit 2) */
- #define R_PDC_PCSR_FEF_Msk (0x4UL) /*!< FEF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_FEMPF_Pos (1UL) /*!< FEMPF (Bit 1) */
- #define R_PDC_PCSR_FEMPF_Msk (0x2UL) /*!< FEMPF (Bitfield-Mask: 0x01) */
- #define R_PDC_PCSR_FBSY_Pos (0UL) /*!< FBSY (Bit 0) */
- #define R_PDC_PCSR_FBSY_Msk (0x1UL) /*!< FBSY (Bitfield-Mask: 0x01) */
-/* ======================================================== PCMONR ========================================================= */
- #define R_PDC_PCMONR_HSYNC_Pos (1UL) /*!< HSYNC (Bit 1) */
- #define R_PDC_PCMONR_HSYNC_Msk (0x2UL) /*!< HSYNC (Bitfield-Mask: 0x01) */
- #define R_PDC_PCMONR_VSYNC_Pos (0UL) /*!< VSYNC (Bit 0) */
- #define R_PDC_PCMONR_VSYNC_Msk (0x1UL) /*!< VSYNC (Bitfield-Mask: 0x01) */
-/* ========================================================= PCDR ========================================================== */
- #define R_PDC_PCDR_PCDR_Pos (0UL) /*!< PCDR (Bit 0) */
- #define R_PDC_PCDR_PCDR_Msk (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff) */
-/* ========================================================== VCR ========================================================== */
- #define R_PDC_VCR_VSZ_Pos (16UL) /*!< VSZ (Bit 16) */
- #define R_PDC_VCR_VSZ_Msk (0xfff0000UL) /*!< VSZ (Bitfield-Mask: 0xfff) */
- #define R_PDC_VCR_VST_Pos (0UL) /*!< VST (Bit 0) */
- #define R_PDC_VCR_VST_Msk (0xfffUL) /*!< VST (Bitfield-Mask: 0xfff) */
-/* ========================================================== HCR ========================================================== */
- #define R_PDC_HCR_HSZ_Pos (16UL) /*!< HSZ (Bit 16) */
- #define R_PDC_HCR_HSZ_Msk (0xfff0000UL) /*!< HSZ (Bitfield-Mask: 0xfff) */
- #define R_PDC_HCR_HST_Pos (0UL) /*!< HST (Bit 0) */
- #define R_PDC_HCR_HST_Msk (0xfffUL) /*!< HST (Bitfield-Mask: 0xfff) */
-
-/* =========================================================================================================================== */
-/* ================ R_PORT0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== PCNTR1 ========================================================= */
- #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */
- #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */
- #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */
- #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= PODR ========================================================== */
- #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */
- #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
-/* ========================================================== PDR ========================================================== */
- #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */
- #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */
-/* ======================================================== PCNTR2 ========================================================= */
- #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */
- #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */
- #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
- #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */
-/* ========================================================= EIDR ========================================================== */
- #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */
- #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */
-/* ========================================================= PIDR ========================================================== */
- #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
- #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */
-/* ======================================================== PCNTR3 ========================================================= */
- #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */
- #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */
- #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */
- #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */
-/* ========================================================= PORR ========================================================== */
- #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */
- #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */
-/* ========================================================= POSR ========================================================== */
- #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */
- #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */
-/* ======================================================== PCNTR4 ========================================================= */
- #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */
- #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */
- #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
- #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */
-/* ========================================================= EORR ========================================================== */
- #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */
- #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */
-/* ========================================================= EOSR ========================================================== */
- #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
- #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_PFS ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_PMISC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== PFENET ========================================================= */
- #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */
- #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */
- #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */
- #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */
-/* ========================================================= PWPR ========================================================== */
- #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
- #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
- #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
- #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
-/* ========================================================= PWPRS ========================================================= */
- #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
- #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
- #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
- #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_QSPI ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== SFMSMD ========================================================= */
- #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */
- #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */
- #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */
- #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */
- #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */
- #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */
- #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */
- #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */
- #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */
- #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */
- #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */
-/* ======================================================== SFMSSC ========================================================= */
- #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */
- #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */
- #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */
- #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */
-/* ======================================================== SFMSKC ========================================================= */
- #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */
- #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */
- #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */
-/* ======================================================== SFMSST ========================================================= */
- #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */
- #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */
- #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */
- #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */
-/* ======================================================== SFMCOM ========================================================= */
- #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */
- #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */
-/* ======================================================== SFMCMD ========================================================= */
- #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */
- #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */
-/* ======================================================== SFMCST ========================================================= */
- #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */
- #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */
- #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */
-/* ======================================================== SFMSIC ========================================================= */
- #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */
- #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */
-/* ======================================================== SFMSAC ========================================================= */
- #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */
- #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */
- #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */
-/* ======================================================== SFMSDC ========================================================= */
- #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */
- #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */
- #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */
- #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */
- #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */
- #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */
-/* ======================================================== SFMSPC ========================================================= */
- #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */
- #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */
- #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */
- #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */
-/* ======================================================== SFMPMD ========================================================= */
- #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */
- #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */
-/* ======================================================== SFMCNT1 ======================================================== */
- #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */
- #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */
-
-/* =========================================================================================================================== */
-/* ================ R_RTC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== R64CNT ========================================================= */
- #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */
- #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */
- #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */
- #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */
- #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */
- #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */
- #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */
- #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */
- #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */
-/* ======================================================== RSECCNT ======================================================== */
- #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
- #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
- #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
- #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT0 ========================================================= */
- #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */
- #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */
-/* ======================================================== RMINCNT ======================================================== */
- #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
- #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
- #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
- #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT1 ========================================================= */
- #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */
- #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */
-/* ======================================================== RHRCNT ========================================================= */
- #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */
- #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
- #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
- #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
- #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
-/* ========================================================= BCNT2 ========================================================= */
- #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */
- #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */
-/* ======================================================== RWKCNT ========================================================= */
- #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
- #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
-/* ========================================================= BCNT3 ========================================================= */
- #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */
- #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */
-/* ======================================================== RDAYCNT ======================================================== */
- #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
- #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
- #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
- #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== RMONCNT ======================================================== */
- #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
- #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
- #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
- #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== RYRCNT ========================================================= */
- #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
- #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
- #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
- #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== RSECAR ========================================================= */
- #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
- #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
- #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
- #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== BCNT0AR ======================================================== */
- #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */
- #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */
-/* ======================================================== RMINAR ========================================================= */
- #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
- #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
- #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
- #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== BCNT1AR ======================================================== */
- #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */
- #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */
-/* ========================================================= RHRAR ========================================================= */
- #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */
- #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
- #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
- #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
- #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== BCNT2AR ======================================================== */
- #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */
- #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */
-/* ========================================================= RWKAR ========================================================= */
- #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
- #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
-/* ======================================================== BCNT3AR ======================================================== */
- #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */
- #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */
-/* ======================================================== RDAYAR ========================================================= */
- #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
- #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
- #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
- #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
-/* ======================================================= BCNT0AER ======================================================== */
- #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
- #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
-/* ======================================================== RMONAR ========================================================= */
- #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
- #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
- #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
- #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
- #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
-/* ======================================================= BCNT1AER ======================================================== */
- #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
- #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
-/* ========================================================= RYRAR ========================================================= */
- #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
- #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
- #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
- #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
-/* ======================================================= BCNT2AER ======================================================== */
- #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
- #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
-/* ======================================================== RYRAREN ======================================================== */
- #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */
- #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
-/* ======================================================= BCNT3AER ======================================================== */
- #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
- #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
-/* ========================================================= RCR1 ========================================================== */
- #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */
- #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */
- #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */
- #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */
- #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */
- #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */
- #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */
-/* ========================================================= RCR2 ========================================================== */
- #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */
- #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */
- #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */
- #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */
- #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */
- #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */
- #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */
- #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */
- #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
-/* ========================================================= RCR4 ========================================================== */
- #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */
- #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */
- #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */
- #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */
-/* ========================================================= RFRH ========================================================== */
- #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */
- #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */
-/* ========================================================= RFRL ========================================================== */
- #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */
- #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */
-/* ========================================================= RADJ ========================================================== */
- #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */
- #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */
- #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */
- #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */
-
-/* =========================================================================================================================== */
-/* ================ R_SCI0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== SMR ========================================================== */
- #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */
- #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */
- #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */
- #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */
- #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */
- #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */
- #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */
- #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
-/* ======================================================= SMR_SMCI ======================================================== */
- #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */
- #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */
- #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */
- #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */
- #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */
- #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */
- #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */
- #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
-/* ========================================================== BRR ========================================================== */
- #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */
- #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */
-/* ========================================================== SCR ========================================================== */
- #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */
- #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */
- #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */
- #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */
- #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
- #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
- #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */
- #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
-/* ======================================================= SCR_SMCI ======================================================== */
- #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */
- #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */
- #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */
- #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */
- #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
- #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
- #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */
- #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
-/* ========================================================== TDR ========================================================== */
- #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */
- #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */
-/* ========================================================== SSR ========================================================== */
- #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
- #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
- #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */
- #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */
- #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */
- #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */
- #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */
- #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
- #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
-/* ======================================================= SSR_FIFO ======================================================== */
- #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */
- #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */
- #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */
- #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */
- #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */
- #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */
- #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */
- #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
-/* ======================================================= SSR_SMCI ======================================================== */
- #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
- #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
- #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */
- #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */
- #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */
- #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */
- #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */
- #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
- #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
- #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
-/* ========================================================== RDR ========================================================== */
- #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */
- #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */
-/* ========================================================= SCMR ========================================================== */
- #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */
- #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */
- #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */
- #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */
- #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */
- #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */
- #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */
-/* ========================================================= SEMR ========================================================== */
- #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */
- #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
- #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */
- #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */
- #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */
- #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */
- #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */
- #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */
- #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */
- #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */
- #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */
-/* ========================================================= SNFR ========================================================== */
- #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */
- #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */
-/* ========================================================= SIMR1 ========================================================= */
- #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */
- #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */
- #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */
- #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */
-/* ========================================================= SIMR2 ========================================================= */
- #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */
- #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
- #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */
- #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
- #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */
- #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
-/* ========================================================= SIMR3 ========================================================= */
- #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */
- #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
- #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */
- #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
- #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
- #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
- #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */
- #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
- #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */
- #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
- #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */
- #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
-/* ========================================================= SISR ========================================================== */
- #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
- #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
-/* ========================================================= SPMR ========================================================== */
- #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */
- #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */
- #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */
- #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */
- #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */
- #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */
- #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */
- #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */
-/* ========================================================= TDRHL ========================================================= */
- #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */
- #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */
-/* ======================================================== FTDRHL ========================================================= */
- #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
- #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
- #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
- #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
-/* ========================================================= FTDRH ========================================================= */
- #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */
- #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */
- #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */
- #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */
-/* ========================================================= FTDRL ========================================================= */
- #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */
- #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */
-/* ========================================================= RDRHL ========================================================= */
- #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */
- #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */
-/* ======================================================== FRDRHL ========================================================= */
- #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */
- #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */
- #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */
- #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */
- #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */
- #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */
- #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
- #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
-/* ========================================================= FRDRH ========================================================= */
- #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */
- #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */
- #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */
- #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */
- #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */
- #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */
- #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
- #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */
- #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */
-/* ========================================================= FRDRL ========================================================= */
- #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */
- #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */
-/* ========================================================= MDDR ========================================================== */
- #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */
- #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */
-/* ========================================================= DCCR ========================================================== */
- #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */
- #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */
- #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */
- #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
- #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */
- #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */
- #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */
- #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */
- #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */
- #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */
-/* ========================================================== FCR ========================================================== */
- #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */
- #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */
- #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */
- #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */
- #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */
- #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */
- #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */
- #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */
- #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */
- #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */
- #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */
- #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */
- #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */
- #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */
-/* ========================================================== FDR ========================================================== */
- #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */
- #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */
- #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */
- #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */
-/* ========================================================== LSR ========================================================== */
- #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */
- #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */
- #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */
- #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */
- #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */
- #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */
-/* ========================================================== CDR ========================================================== */
- #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
- #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
-/* ========================================================= SPTR ========================================================== */
- #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */
- #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */
- #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */
- #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */
- #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */
- #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */
- #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */
- #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */
- #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */
-/* ========================================================= ACTR ========================================================== */
- #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */
- #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */
- #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */
- #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */
- #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */
- #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */
- #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */
- #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */
-/* ========================================================= ESMER ========================================================= */
- #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */
- #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */
-/* ========================================================== CR0 ========================================================== */
- #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */
- #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */
- #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */
- #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
- #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */
- #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */
-/* ========================================================== CR1 ========================================================== */
- #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */
- #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */
- #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */
- #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
- #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */
- #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */
- #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */
- #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */
- #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */
- #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */
-/* ========================================================== CR2 ========================================================== */
- #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */
- #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */
- #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */
- #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */
- #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */
- #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */
-/* ========================================================== CR3 ========================================================== */
- #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */
- #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */
-/* ========================================================== PCR ========================================================== */
- #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */
- #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */
- #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */
- #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */
- #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */
- #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
-/* ========================================================== ICR ========================================================== */
- #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */
- #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */
- #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */
- #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */
- #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */
- #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
- #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */
- #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
-/* ========================================================== STR ========================================================== */
- #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */
- #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */
- #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
- #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */
- #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
- #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */
- #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */
- #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */
- #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */
- #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */
-/* ========================================================= STCR ========================================================== */
- #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */
- #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */
- #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */
- #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */
- #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */
- #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */
- #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */
- #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */
- #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */
- #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */
- #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */
- #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */
-/* ========================================================= CF0DR ========================================================= */
-/* ========================================================= CF0CR ========================================================= */
- #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */
- #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */
- #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */
- #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */
- #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */
- #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */
- #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */
- #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */
- #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */
-/* ========================================================= CF0RR ========================================================= */
-/* ======================================================== PCF1DR ========================================================= */
-/* ======================================================== SCF1DR ========================================================= */
-/* ========================================================= CF1CR ========================================================= */
- #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */
- #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */
- #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */
- #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */
- #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */
- #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */
- #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */
- #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */
- #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */
- #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */
-/* ========================================================= CF1RR ========================================================= */
-/* ========================================================== TCR ========================================================== */
- #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */
- #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
-/* ========================================================== TMR ========================================================== */
- #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */
- #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */
- #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */
- #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */
- #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
- #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */
-/* ========================================================= TPRE ========================================================== */
-/* ========================================================= TCNT ========================================================== */
-
-/* =========================================================================================================================== */
-/* ================ R_SDADC0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= STC1 ========================================================== */
- #define R_SDADC0_STC1_VSBIAS_Pos (8UL) /*!< VSBIAS (Bit 8) */
- #define R_SDADC0_STC1_VSBIAS_Msk (0xf00UL) /*!< VSBIAS (Bitfield-Mask: 0x0f) */
- #define R_SDADC0_STC1_CLKDIV_Pos (0UL) /*!< CLKDIV (Bit 0) */
- #define R_SDADC0_STC1_CLKDIV_Msk (0xfUL) /*!< CLKDIV (Bitfield-Mask: 0x0f) */
- #define R_SDADC0_STC1_SDADLPM_Pos (7UL) /*!< SDADLPM (Bit 7) */
- #define R_SDADC0_STC1_SDADLPM_Msk (0x80UL) /*!< SDADLPM (Bitfield-Mask: 0x01) */
- #define R_SDADC0_STC1_VREFSEL_Pos (15UL) /*!< VREFSEL (Bit 15) */
- #define R_SDADC0_STC1_VREFSEL_Msk (0x8000UL) /*!< VREFSEL (Bitfield-Mask: 0x01) */
-/* ========================================================= STC2 ========================================================== */
- #define R_SDADC0_STC2_BGRPON_Pos (0UL) /*!< BGRPON (Bit 0) */
- #define R_SDADC0_STC2_BGRPON_Msk (0x1UL) /*!< BGRPON (Bitfield-Mask: 0x01) */
- #define R_SDADC0_STC2_ADFPWDS_Pos (2UL) /*!< ADFPWDS (Bit 2) */
- #define R_SDADC0_STC2_ADFPWDS_Msk (0x4UL) /*!< ADFPWDS (Bitfield-Mask: 0x01) */
- #define R_SDADC0_STC2_ADCPON_Pos (1UL) /*!< ADCPON (Bit 1) */
- #define R_SDADC0_STC2_ADCPON_Msk (0x2UL) /*!< ADCPON (Bitfield-Mask: 0x01) */
-/* ========================================================= PGAC ========================================================== */
- #define R_SDADC0_PGAC_PGAASN_Pos (31UL) /*!< PGAASN (Bit 31) */
- #define R_SDADC0_PGAC_PGAASN_Msk (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01) */
- #define R_SDADC0_PGAC_PGACVE_Pos (30UL) /*!< PGACVE (Bit 30) */
- #define R_SDADC0_PGAC_PGACVE_Msk (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01) */
- #define R_SDADC0_PGAC_PGAREV_Pos (28UL) /*!< PGAREV (Bit 28) */
- #define R_SDADC0_PGAC_PGAREV_Msk (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01) */
- #define R_SDADC0_PGAC_PGAAVE_Pos (26UL) /*!< PGAAVE (Bit 26) */
- #define R_SDADC0_PGAC_PGAAVE_Msk (0xc000000UL) /*!< PGAAVE (Bitfield-Mask: 0x03) */
- #define R_SDADC0_PGAC_PGAAVN_Pos (24UL) /*!< PGAAVN (Bit 24) */
- #define R_SDADC0_PGAC_PGAAVN_Msk (0x3000000UL) /*!< PGAAVN (Bitfield-Mask: 0x03) */
- #define R_SDADC0_PGAC_PGACTN_Pos (21UL) /*!< PGACTN (Bit 21) */
- #define R_SDADC0_PGAC_PGACTN_Msk (0xe00000UL) /*!< PGACTN (Bitfield-Mask: 0x07) */
- #define R_SDADC0_PGAC_PGACTM_Pos (16UL) /*!< PGACTM (Bit 16) */
- #define R_SDADC0_PGAC_PGACTM_Msk (0x1f0000UL) /*!< PGACTM (Bitfield-Mask: 0x1f) */
- #define R_SDADC0_PGAC_PGASEL_Pos (15UL) /*!< PGASEL (Bit 15) */
- #define R_SDADC0_PGAC_PGASEL_Msk (0x8000UL) /*!< PGASEL (Bitfield-Mask: 0x01) */
- #define R_SDADC0_PGAC_PGAPOL_Pos (14UL) /*!< PGAPOL (Bit 14) */
- #define R_SDADC0_PGAC_PGAPOL_Msk (0x4000UL) /*!< PGAPOL (Bitfield-Mask: 0x01) */
- #define R_SDADC0_PGAC_PGAOFS_Pos (8UL) /*!< PGAOFS (Bit 8) */
- #define R_SDADC0_PGAC_PGAOFS_Msk (0x1f00UL) /*!< PGAOFS (Bitfield-Mask: 0x1f) */
- #define R_SDADC0_PGAC_PGAOSR_Pos (5UL) /*!< PGAOSR (Bit 5) */
- #define R_SDADC0_PGAC_PGAOSR_Msk (0xe0UL) /*!< PGAOSR (Bitfield-Mask: 0x07) */
- #define R_SDADC0_PGAC_PGAGC_Pos (0UL) /*!< PGAGC (Bit 0) */
- #define R_SDADC0_PGAC_PGAGC_Msk (0x1fUL) /*!< PGAGC (Bitfield-Mask: 0x1f) */
-/* ========================================================= ADC1 ========================================================== */
- #define R_SDADC0_ADC1_PGASLFT_Pos (20UL) /*!< PGASLFT (Bit 20) */
- #define R_SDADC0_ADC1_PGASLFT_Msk (0x100000UL) /*!< PGASLFT (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADC1_PGADISC_Pos (17UL) /*!< PGADISC (Bit 17) */
- #define R_SDADC0_ADC1_PGADISC_Msk (0x20000UL) /*!< PGADISC (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADC1_PGADISA_Pos (16UL) /*!< PGADISA (Bit 16) */
- #define R_SDADC0_ADC1_PGADISA_Msk (0x10000UL) /*!< PGADISA (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADC1_SDADBMP_Pos (8UL) /*!< SDADBMP (Bit 8) */
- #define R_SDADC0_ADC1_SDADBMP_Msk (0x1f00UL) /*!< SDADBMP (Bitfield-Mask: 0x1f) */
- #define R_SDADC0_ADC1_SDADTMD_Pos (4UL) /*!< SDADTMD (Bit 4) */
- #define R_SDADC0_ADC1_SDADTMD_Msk (0x10UL) /*!< SDADTMD (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADC1_SDADSCM_Pos (0UL) /*!< SDADSCM (Bit 0) */
- #define R_SDADC0_ADC1_SDADSCM_Msk (0x1UL) /*!< SDADSCM (Bitfield-Mask: 0x01) */
-/* ========================================================= ADC2 ========================================================== */
- #define R_SDADC0_ADC2_SDADST_Pos (0UL) /*!< SDADST (Bit 0) */
- #define R_SDADC0_ADC2_SDADST_Msk (0x1UL) /*!< SDADST (Bitfield-Mask: 0x01) */
-/* ========================================================= ADCR ========================================================== */
- #define R_SDADC0_ADCR_SDADCRC_Pos (25UL) /*!< SDADCRC (Bit 25) */
- #define R_SDADC0_ADCR_SDADCRC_Msk (0xe000000UL) /*!< SDADCRC (Bitfield-Mask: 0x07) */
- #define R_SDADC0_ADCR_SDADCRS_Pos (24UL) /*!< SDADCRS (Bit 24) */
- #define R_SDADC0_ADCR_SDADCRS_Msk (0x1000000UL) /*!< SDADCRS (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADCR_SDADCRD_Pos (0UL) /*!< SDADCRD (Bit 0) */
- #define R_SDADC0_ADCR_SDADCRD_Msk (0xffffffUL) /*!< SDADCRD (Bitfield-Mask: 0xffffff) */
-/* ========================================================= ADAR ========================================================== */
- #define R_SDADC0_ADAR_SDADMVC_Pos (25UL) /*!< SDADMVC (Bit 25) */
- #define R_SDADC0_ADAR_SDADMVC_Msk (0xe000000UL) /*!< SDADMVC (Bitfield-Mask: 0x07) */
- #define R_SDADC0_ADAR_SDADMVS_Pos (24UL) /*!< SDADMVS (Bit 24) */
- #define R_SDADC0_ADAR_SDADMVS_Msk (0x1000000UL) /*!< SDADMVS (Bitfield-Mask: 0x01) */
- #define R_SDADC0_ADAR_SDADMVD_Pos (0UL) /*!< SDADMVD (Bit 0) */
- #define R_SDADC0_ADAR_SDADMVD_Msk (0xffffffUL) /*!< SDADMVD (Bitfield-Mask: 0xffffff) */
-/* ========================================================= CLBC ========================================================== */
- #define R_SDADC0_CLBC_CLBMD_Pos (0UL) /*!< CLBMD (Bit 0) */
- #define R_SDADC0_CLBC_CLBMD_Msk (0x3UL) /*!< CLBMD (Bitfield-Mask: 0x03) */
-/* ======================================================== CLBSTR ========================================================= */
- #define R_SDADC0_CLBSTR_CLBST_Pos (0UL) /*!< CLBST (Bit 0) */
- #define R_SDADC0_CLBSTR_CLBST_Msk (0x1UL) /*!< CLBST (Bitfield-Mask: 0x01) */
-/* ======================================================== CLBSSR ========================================================= */
- #define R_SDADC0_CLBSSR_CLBSS_Pos (0UL) /*!< CLBSS (Bit 0) */
- #define R_SDADC0_CLBSSR_CLBSS_Msk (0x1UL) /*!< CLBSS (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_SDHI0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== SD_CMD ========================================================= */
- #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */
- #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */
- #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */
- #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */
- #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */
- #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */
- #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */
- #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */
- #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */
- #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */
- #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */
-/* ======================================================== SD_ARG ========================================================= */
- #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */
- #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SD_ARG1 ======================================================== */
- #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */
- #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */
-/* ======================================================== SD_STOP ======================================================== */
- #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */
- #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */
- #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */
-/* ======================================================= SD_SECCNT ======================================================= */
- #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */
- #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SD_RSP10 ======================================================== */
- #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */
- #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SD_RSP1 ======================================================== */
- #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */
- #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */
-/* ======================================================= SD_RSP32 ======================================================== */
- #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */
- #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SD_RSP3 ======================================================== */
- #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */
- #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */
-/* ======================================================= SD_RSP54 ======================================================== */
- #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */
- #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== SD_RSP5 ======================================================== */
- #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */
- #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */
-/* ======================================================= SD_RSP76 ======================================================== */
- #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */
- #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */
-/* ======================================================== SD_RSP7 ======================================================== */
- #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */
- #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */
-/* ======================================================= SD_INFO1 ======================================================== */
- #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */
- #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */
- #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */
- #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */
- #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */
- #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */
- #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */
- #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */
- #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */
- #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */
-/* ======================================================= SD_INFO2 ======================================================== */
- #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */
- #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */
- #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */
- #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */
- #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */
- #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */
- #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */
- #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */
- #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */
- #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */
- #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */
- #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */
- #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */
- #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */
-/* ===================================================== SD_INFO1_MASK ===================================================== */
- #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */
- #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */
- #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */
- #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */
- #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */
- #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */
- #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */
-/* ===================================================== SD_INFO2_MASK ===================================================== */
- #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */
- #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */
- #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */
- #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */
- #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */
- #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */
- #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */
- #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */
- #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */
- #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */
- #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */
-/* ====================================================== SD_CLK_CTRL ====================================================== */
- #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */
- #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */
- #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
- #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */
-/* ======================================================== SD_SIZE ======================================================== */
- #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */
- #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */
-/* ======================================================= SD_OPTION ======================================================= */
- #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */
- #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */
- #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */
- #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */
- #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */
- #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
- #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */
-/* ====================================================== SD_ERR_STS1 ====================================================== */
- #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */
- #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */
- #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */
- #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */
- #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */
- #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */
- #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */
- #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */
- #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */
- #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */
- #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */
- #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */
- #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */
-/* ====================================================== SD_ERR_STS2 ====================================================== */
- #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */
- #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */
- #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */
- #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */
- #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */
- #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */
- #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */
- #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */
-/* ======================================================== SD_BUF0 ======================================================== */
- #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */
- #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SDIO_MODE ======================================================= */
- #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */
- #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */
- #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */
- #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */
- #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */
-/* ====================================================== SDIO_INFO1 ======================================================= */
- #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */
- #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */
- #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */
- #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */
-/* ==================================================== SDIO_INFO1_MASK ==================================================== */
- #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */
- #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */
- #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */
- #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */
- #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */
-/* ======================================================= SD_DMAEN ======================================================== */
- #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */
- #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
-/* ======================================================= SOFT_RST ======================================================== */
- #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */
- #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */
-/* ======================================================= SDIF_MODE ======================================================= */
- #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */
- #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */
-/* ======================================================= EXT_SWAP ======================================================== */
- #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */
- #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */
- #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */
- #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_SLCDC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= LCDM0 ========================================================= */
- #define R_SLCDC_LCDM0_MDSET_Pos (6UL) /*!< MDSET (Bit 6) */
- #define R_SLCDC_LCDM0_MDSET_Msk (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03) */
- #define R_SLCDC_LCDM0_LWAVE_Pos (5UL) /*!< LWAVE (Bit 5) */
- #define R_SLCDC_LCDM0_LWAVE_Msk (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM0_LDTY_Pos (2UL) /*!< LDTY (Bit 2) */
- #define R_SLCDC_LCDM0_LDTY_Msk (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07) */
- #define R_SLCDC_LCDM0_LBAS_Pos (0UL) /*!< LBAS (Bit 0) */
- #define R_SLCDC_LCDM0_LBAS_Msk (0x3UL) /*!< LBAS (Bitfield-Mask: 0x03) */
-/* ========================================================= LCDM1 ========================================================= */
- #define R_SLCDC_LCDM1_LCDON_Pos (7UL) /*!< LCDON (Bit 7) */
- #define R_SLCDC_LCDM1_LCDON_Msk (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM1_SCOC_Pos (6UL) /*!< SCOC (Bit 6) */
- #define R_SLCDC_LCDM1_SCOC_Msk (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM1_VLCON_Pos (5UL) /*!< VLCON (Bit 5) */
- #define R_SLCDC_LCDM1_VLCON_Msk (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM1_BLON_Pos (4UL) /*!< BLON (Bit 4) */
- #define R_SLCDC_LCDM1_BLON_Msk (0x10UL) /*!< BLON (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM1_LCDSEL_Pos (3UL) /*!< LCDSEL (Bit 3) */
- #define R_SLCDC_LCDM1_LCDSEL_Msk (0x8UL) /*!< LCDSEL (Bitfield-Mask: 0x01) */
- #define R_SLCDC_LCDM1_LCDVLM_Pos (0UL) /*!< LCDVLM (Bit 0) */
- #define R_SLCDC_LCDM1_LCDVLM_Msk (0x1UL) /*!< LCDVLM (Bitfield-Mask: 0x01) */
-/* ========================================================= LCDC0 ========================================================= */
- #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */
- #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */
-/* ========================================================= VLCD ========================================================== */
- #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */
- #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */
-/* ========================================================== SEG ========================================================== */
- #define R_SLCDC_SEG_A_Pos (0UL) /*!< A (Bit 0) */
- #define R_SLCDC_SEG_A_Msk (0xfUL) /*!< A (Bitfield-Mask: 0x0f) */
- #define R_SLCDC_SEG_B_Pos (4UL) /*!< B (Bit 4) */
- #define R_SLCDC_SEG_B_Msk (0xf0UL) /*!< B (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ R_SPI0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SPCR ========================================================== */
- #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */
- #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */
- #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */
- #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */
- #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */
- #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */
- #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */
- #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */
- #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */
-/* ========================================================= SSLP ========================================================== */
- #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
- #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
- #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
- #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
- #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */
- #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */
- #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */
- #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */
- #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */
- #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */
-/* ========================================================= SPPCR ========================================================= */
- #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */
- #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */
- #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */
- #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */
- #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */
-/* ========================================================= SPSR ========================================================== */
- #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */
- #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */
- #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */
- #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */
- #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */
- #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */
- #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */
- #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */
- #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */
-/* ========================================================= SPDR ========================================================== */
-/* ======================================================== SPDR_HA ======================================================== */
-/* ======================================================== SPDR_BY ======================================================== */
-/* ========================================================= SPSCR ========================================================= */
- #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */
- #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
-/* ========================================================= SPBR ========================================================== */
- #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */
- #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */
-/* ========================================================= SPDCR ========================================================= */
- #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */
- #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */
- #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */
- #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */
- #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */
- #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */
- #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */
-/* ========================================================= SPCKD ========================================================= */
- #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
- #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
-/* ========================================================= SSLND ========================================================= */
- #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */
- #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
-/* ========================================================= SPND ========================================================== */
- #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */
- #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
-/* ========================================================= SPCR2 ========================================================= */
- #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */
- #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */
- #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */
- #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */
- #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */
- #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */
- #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */
-/* ========================================================= SPCMD ========================================================= */
- #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */
- #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */
- #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */
- #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */
- #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
-/* ======================================================== SPDCR2 ========================================================= */
- #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
- #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */
- #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */
-/* ========================================================= SPSSR ========================================================= */
- #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */
- #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */
- #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */
- #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */
-/* ========================================================= SPCR3 ========================================================= */
- #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */
- #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */
- #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */
- #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
-/* ========================================================= SPPR ========================================================== */
- #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */
- #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */
- #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */
- #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */
- #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */
- #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */
-
-/* =========================================================================================================================== */
-/* ================ R_SRAM ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== PARIOAD ======================================================== */
- #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
-/* ======================================================= SRAMPRCR ======================================================== */
- #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
- #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
- #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */
- #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */
-/* ======================================================= SRAMWTSC ======================================================== */
-/* ======================================================== ECCMODE ======================================================== */
- #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */
- #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */
-/* ======================================================== ECC2STS ======================================================== */
- #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */
- #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ECC1STSEN ======================================================= */
- #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */
- #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */
-/* ======================================================== ECC1STS ======================================================== */
- #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */
- #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */
-/* ======================================================== ECCPRCR ======================================================== */
- #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
- #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
- #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */
- #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */
-/* ======================================================= ECCPRCR2 ======================================================== */
- #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */
- #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */
- #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */
- #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */
-/* ======================================================== ECCETST ======================================================== */
- #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */
- #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */
-/* ======================================================== ECCOAD ========================================================= */
- #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
-/* ======================================================= SRAMPRCR2 ======================================================= */
- #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */
- #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */
- #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */
- #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
-
-/* =========================================================================================================================== */
-/* ================ R_BUS_B ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================== BUSSCNTFHBIU ====================================================== */
- #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ===================================================== BUSSCNTFLBIU ====================================================== */
- #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ===================================================== BUSSCNTS0BIU ====================================================== */
- #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ===================================================== BUSSCNTPSBIU ====================================================== */
- #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
-/* ===================================================== BUSSCNTPLBIU ====================================================== */
- #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
-/* ===================================================== BUSSCNTPHBIU ====================================================== */
- #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
-/* ===================================================== BUSSCNTEQBIU ====================================================== */
- #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ===================================================== BUSSCNTEOBIU ====================================================== */
- #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ===================================================== BUSSCNTECBIU ====================================================== */
- #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
- #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
-/* ====================================================== BUS1ERRSTAT ====================================================== */
- #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
- #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
- #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
- #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
- #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS2ERRSTAT ====================================================== */
- #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
- #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
- #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
- #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
- #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS3ERRSTAT ====================================================== */
- #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
- #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
- #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
- #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
- #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS4ERRSTAT ====================================================== */
- #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
- #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
- #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
- #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
- #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS1ERRCLR ======================================================= */
- #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
- #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
- #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
- #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
- #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS2ERRCLR ======================================================= */
- #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
- #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
- #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
- #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
- #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS3ERRCLR ======================================================= */
- #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
- #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
- #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
- #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
- #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
-/* ====================================================== BUS4ERRCLR ======================================================= */
- #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
- #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
- #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
- #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
- #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
- #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
-/* ==================================================== DMACDTCERRSTAT ===================================================== */
- #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */
- #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */
-/* ===================================================== DMACDTCERRCLR ===================================================== */
- #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */
- #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */
-/* ======================================================== CSRECEN ======================================================== */
- #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
- #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
- #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
- #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_SRC ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== SRCFCTR ======================================================== */
- #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */
- #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */
-/* ========================================================= SRCID ========================================================= */
- #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */
- #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= SRCOD ========================================================= */
- #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */
- #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SRCIDCTRL ======================================================= */
- #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */
- #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */
- #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */
- #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */
-/* ======================================================== SRCCTRL ======================================================== */
- #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */
- #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */
- #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */
- #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */
- #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */
- #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */
- #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */
- #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */
- #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */
- #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */
- #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */
-/* ======================================================= SRCODCTRL ======================================================= */
- #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */
- #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */
- #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */
- #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */
- #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */
-/* ======================================================== SRCSTAT ======================================================== */
- #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */
- #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */
- #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */
- #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */
- #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */
- #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */
- #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */
- #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */
- #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */
- #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */
- #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */
- #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_SSI0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SSICR ========================================================= */
- #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */
- #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */
- #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */
- #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */
- #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */
- #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */
- #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */
- #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */
- #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */
- #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */
- #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */
- #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */
- #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */
- #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */
- #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */
- #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */
- #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */
- #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */
- #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */
- #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */
- #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */
- #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */
- #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */
- #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */
- #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */
-/* ========================================================= SSISR ========================================================= */
- #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */
- #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */
- #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */
- #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */
- #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */
- #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */
- #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */
- #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */
- #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */
- #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */
- #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */
- #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */
- #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */
-/* ======================================================== SSIFCR ========================================================= */
- #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */
- #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */
- #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */
- #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */
- #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */
- #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */
- #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */
- #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */
- #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */
- #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */
- #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */
- #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */
-/* ======================================================== SSIFSR ========================================================= */
- #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */
- #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */
- #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */
- #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */
- #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */
- #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */
- #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */
-/* ======================================================== SSIFTDR ======================================================== */
- #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */
- #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SSIFTDR16 ======================================================= */
-/* ======================================================= SSIFTDR8 ======================================================== */
-/* ======================================================== SSIFRDR ======================================================== */
- #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */
- #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */
-/* ======================================================= SSIFRDR16 ======================================================= */
-/* ======================================================= SSIFRDR8 ======================================================== */
-/* ======================================================== SSIOFR ========================================================= */
- #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */
- #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */
- #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */
- #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */
- #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */
-/* ======================================================== SSISCR ========================================================= */
- #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */
- #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */
- #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */
- #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */
-
-/* =========================================================================================================================== */
-/* ================ R_SYSTEM ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SBYCR ========================================================= */
- #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */
- #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */
- #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */
-/* ======================================================== MSTPCRA ======================================================== */
- #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */
- #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */
- #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */
- #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */
- #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */
- #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */
- #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */
-/* ======================================================= SCKDIVCR ======================================================== */
- #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */
- #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */
- #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */
- #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */
- #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */
- #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */
- #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */
- #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */
-/* ======================================================= SCKDIVCR2 ======================================================= */
- #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */
- #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */
-/* ======================================================== SCKSCR ========================================================= */
- #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
- #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */
-/* ======================================================== PLLCCR ========================================================= */
- #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */
- #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */
- #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */
- #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */
- #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */
-/* ========================================================= PLLCR ========================================================= */
- #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */
- #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */
-/* ======================================================== PLLCCR2 ======================================================== */
- #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */
- #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */
- #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */
-/* ========================================================= BCKCR ========================================================= */
- #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */
- #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */
-/* ======================================================== MEMWAIT ======================================================== */
- #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */
- #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */
-/* ======================================================== MOSCCR ========================================================= */
- #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */
- #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */
-/* ======================================================== HOCOCR ========================================================= */
- #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
- #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
-/* ======================================================== MOCOCR ========================================================= */
- #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
- #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
-/* ======================================================== FLLCR1 ========================================================= */
- #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */
- #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */
-/* ======================================================== FLLCR2 ========================================================= */
- #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */
- #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */
-/* ========================================================= OSCSF ========================================================= */
- #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */
- #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */
- #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */
- #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */
- #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */
-/* ========================================================= CKOCR ========================================================= */
- #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */
- #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */
- #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */
- #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */
-/* ======================================================== TRCKCR ========================================================= */
- #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */
- #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */
- #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */
-/* ======================================================== OSTDCR ========================================================= */
- #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */
- #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */
- #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */
-/* ======================================================== OSTDSR ========================================================= */
- #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */
- #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */
-/* ========================================================= LPOPT ========================================================= */
- #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */
- #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */
- #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */
- #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */
- #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */
-/* ======================================================= SLCDSCKCR ======================================================= */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */
-/* ======================================================== EBCKOCR ======================================================== */
- #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */
- #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */
-/* ======================================================== SDCKOCR ======================================================== */
- #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */
- #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */
-/* ======================================================= MOCOUTCR ======================================================== */
- #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */
- #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */
-/* ======================================================= HOCOUTCR ======================================================== */
- #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */
- #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */
-/* ========================================================= SNZCR ========================================================= */
- #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */
- #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */
- #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */
- #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */
-/* ======================================================== SNZEDCR ======================================================== */
- #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */
- #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */
- #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */
- #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */
- #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */
- #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */
- #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */
- #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */
- #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */
-/* ======================================================= SNZREQCR ======================================================== */
- #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
-/* ======================================================== FLSTOP ========================================================= */
- #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */
- #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */
- #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */
-/* ========================================================= PSMCR ========================================================= */
- #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */
- #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */
-/* ========================================================= OPCCR ========================================================= */
- #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */
- #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */
- #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */
-/* ======================================================== SOPCCR ========================================================= */
- #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */
- #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */
- #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */
-/* ======================================================= MOSCWTCR ======================================================== */
- #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */
- #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */
-/* ======================================================= HOCOWTCR ======================================================== */
- #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */
- #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */
-/* ======================================================== RSTSR1 ========================================================= */
- #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */
- #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */
- #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */
- #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */
- #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */
- #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */
- #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */
- #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */
- #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */
- #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */
- #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */
-/* ======================================================== STCONR ========================================================= */
- #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */
- #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */
-/* ======================================================== LVD1CR1 ======================================================== */
- #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
- #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
- #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
-/* ======================================================== LVD2CR1 ======================================================== */
- #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
- #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
- #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
-/* ====================================================== USBCKCR_ALT ====================================================== */
- #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */
- #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= SDADCCKCR ======================================================= */
- #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */
-/* ======================================================== LVD1SR ========================================================= */
- #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */
- #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */
- #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
-/* ======================================================== LVD2SR ========================================================= */
- #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */
- #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */
- #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
-/* ========================================================= PRCR ========================================================== */
- #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
- #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
- #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
- #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
- #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
- #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
- #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIER0 ======================================================== */
- #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
- #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIER1 ======================================================== */
- #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
- #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIER2 ======================================================== */
- #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */
- #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */
- #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */
- #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */
- #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */
- #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIER3 ======================================================== */
- #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */
- #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */
- #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */
- #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */
- #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIFR0 ======================================================== */
- #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
- #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIFR1 ======================================================== */
- #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
- #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIFR2 ======================================================== */
- #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */
- #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */
- #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */
- #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */
- #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */
- #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSIFR3 ======================================================== */
- #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */
- #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */
- #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */
- #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */
- #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */
-/* ======================================================= DPSIEGR0 ======================================================== */
- #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
-/* ======================================================= DPSIEGR1 ======================================================== */
- #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
-/* ======================================================= DPSIEGR2 ======================================================== */
- #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */
- #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */
- #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSBYCR ======================================================== */
- #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */
- #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */
- #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */
- #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */
-/* ======================================================== SYOCDCR ======================================================== */
- #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */
- #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */
- #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */
-/* ========================================================= MOMCR ========================================================= */
- #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */
- #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */
- #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */
- #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */
- #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */
-/* ======================================================== RSTSR0 ========================================================= */
- #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */
- #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */
- #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */
- #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */
- #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */
- #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */
-/* ======================================================== RSTSR2 ========================================================= */
- #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */
- #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */
-/* ======================================================== LVCMPCR ======================================================== */
- #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */
- #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */
- #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
-/* ======================================================= LVD1CMPCR ======================================================= */
- #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
- #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
- #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */
- #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
-/* ======================================================== LVDLVLR ======================================================== */
- #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */
- #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
- #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
-/* ======================================================= LVD2CMPCR ======================================================= */
- #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */
- #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */
- #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
-/* ======================================================== LVD1CR0 ======================================================== */
- #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
- #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
- #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
- #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
- #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
- #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
- #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
-/* ======================================================== LVD2CR0 ======================================================== */
- #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
- #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
- #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
- #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
- #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
- #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
- #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTCR1 ========================================================= */
- #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */
- #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */
-/* ======================================================== DCDCCTL ======================================================== */
- #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */
- #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */
- #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */
- #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */
- #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */
- #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */
- #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */
-/* ======================================================== VCCSEL ========================================================= */
- #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */
- #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */
-/* ======================================================== SOSCCR ========================================================= */
- #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */
- #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */
-/* ========================================================= SOMCR ========================================================= */
- #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */
- #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */
-/* ======================================================== LOCOCR ========================================================= */
- #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */
- #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */
-/* ======================================================= LOCOUTCR ======================================================== */
- #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */
- #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */
-/* ======================================================== VBTCR2 ========================================================= */
- #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */
- #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */
- #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */
-/* ========================================================= VBTSR ========================================================= */
- #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */
- #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */
- #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */
- #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */
-/* ======================================================= VBTCMPCR ======================================================== */
- #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */
- #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */
-/* ======================================================= VBTLVDICR ======================================================= */
- #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */
-/* ======================================================= VBTWCTLR ======================================================== */
- #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */
- #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */
-/* ====================================================== VBTWCH0OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */
-/* ====================================================== VBTWCH1OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */
-/* ====================================================== VBTWCH2OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */
-/* ======================================================= VBTICTLR ======================================================== */
- #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */
- #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */
- #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */
- #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */
-/* ======================================================= VBTOCTLR ======================================================== */
- #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */
- #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */
- #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */
- #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */
- #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */
- #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */
- #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTWTER ======================================================== */
- #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */
- #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */
- #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */
- #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */
- #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */
- #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */
- #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTWEGR ======================================================== */
- #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */
- #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */
- #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */
- #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTWFR ========================================================= */
- #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */
- #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */
- #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */
- #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */
- #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */
- #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */
- #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTBKR ========================================================= */
- #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
- #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
-/* ======================================================== FWEPROR ======================================================== */
- #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */
- #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */
-/* ======================================================== PLL2CCR ======================================================== */
- #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */
- #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */
- #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */
- #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */
-/* ======================================================== PLL2CR ========================================================= */
- #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */
- #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */
-/* ====================================================== USBCKDIVCR ======================================================= */
- #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */
- #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */
-/* ====================================================== OCTACKDIVCR ====================================================== */
- #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */
- #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */
-/* ===================================================== SCISPICKDIVCR ===================================================== */
- #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */
- #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */
-/* ===================================================== CANFDCKDIVCR ====================================================== */
- #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */
- #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */
-/* ====================================================== GPTCKDIVCR ======================================================= */
- #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */
- #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */
-/* ====================================================== IICCKDIVCR ======================================================= */
- #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */
- #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */
-/* ======================================================== USBCKCR ======================================================== */
- #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */
- #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */
- #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */
- #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */
-/* ======================================================= OCTACKCR ======================================================== */
- #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */
- #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */
- #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */
- #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */
-/* ====================================================== SCISPICKCR ======================================================= */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */
- #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */
-/* ======================================================= CANFDCKCR ======================================================= */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */
-/* ======================================================== GPTCKCR ======================================================== */
- #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */
- #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */
- #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */
- #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */
-/* ======================================================== IICCKCR ======================================================== */
- #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */
- #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */
- #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */
- #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */
-/* ======================================================= SNZREQCR1 ======================================================= */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */
-/* ======================================================= SNZEDCR1 ======================================================== */
- #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */
- #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */
-/* ======================================================== CGFSAR ========================================================= */
- #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */
- #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */
- #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */
- #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */
- #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */
- #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */
- #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */
- #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */
- #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */
- #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */
- #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */
- #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
- #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
- #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
-/* ======================================================== LPMSAR ========================================================= */
- #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */
- #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */
- #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */
- #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */
-/* ======================================================== LVDSAR ========================================================= */
- #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
-/* ======================================================== RSTSAR ========================================================= */
- #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
-/* ======================================================== BBFSAR ========================================================= */
- #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
- #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
- #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
- #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
- #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */
- #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
- #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */
- #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */
- #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */
-/* ======================================================== DPFSAR ========================================================= */
- #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */
- #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */
- #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */
- #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */
- #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */
- #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */
- #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */
- #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */
- #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */
- #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */
- #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */
- #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */
- #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */
- #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */
- #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */
- #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */
- #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */
- #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */
- #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */
- #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */
- #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */
- #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */
- #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */
- #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */
- #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */
-/* ======================================================== DPSWCR ========================================================= */
- #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */
- #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */
-/* ====================================================== VBATTMNSELR ====================================================== */
- #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */
- #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= VBATTMONR ======================================================= */
- #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */
- #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */
-/* ======================================================== VBTBER ========================================================= */
- #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */
- #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== TSCDRH ========================================================= */
- #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */
- #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */
-/* ======================================================== TSCDRL ========================================================= */
- #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */
- #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN_CAL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= TSCDR ========================================================= */
- #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */
- #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */
-
-/* =========================================================================================================================== */
-/* ================ R_TSN_CTRL ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= TSCR ========================================================== */
- #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */
- #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */
- #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */
- #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_USB_FS0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== SYSCFG ========================================================= */
- #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */
- #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */
- #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */
- #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */
- #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */
- #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */
- #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */
- #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */
-/* ======================================================== BUSWAIT ======================================================== */
- #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */
- #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */
-/* ======================================================== SYSSTS0 ======================================================== */
- #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */
- #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */
- #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */
- #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */
- #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */
- #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */
-/* ======================================================== PLLSTA ========================================================= */
- #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */
- #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */
-/* ======================================================= DVSTCTR0 ======================================================== */
- #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */
- #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */
- #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */
- #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */
- #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */
- #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */
- #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */
- #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */
- #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */
- #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */
-/* ======================================================= TESTMODE ======================================================== */
- #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */
- #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */
-/* ======================================================== CFIFOL ========================================================= */
-/* ======================================================== CFIFOLL ======================================================== */
-/* ========================================================= CFIFO ========================================================= */
-/* ======================================================== CFIFOH ========================================================= */
-/* ======================================================== CFIFOHH ======================================================== */
-/* ======================================================== D0FIFOL ======================================================== */
-/* ======================================================= D0FIFOLL ======================================================== */
-/* ======================================================== D0FIFO ========================================================= */
-/* ======================================================== D0FIFOH ======================================================== */
-/* ======================================================= D0FIFOHH ======================================================== */
-/* ======================================================== D1FIFOL ======================================================== */
-/* ======================================================= D1FIFOLL ======================================================== */
-/* ======================================================== D1FIFO ========================================================= */
-/* ======================================================== D1FIFOH ======================================================== */
-/* ======================================================= D1FIFOHH ======================================================== */
-/* ======================================================= CFIFOSEL ======================================================== */
- #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
- #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
- #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
- #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
- #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */
- #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
- #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
-/* ======================================================= CFIFOCTR ======================================================== */
- #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
- #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
- #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
- #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
- #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
-/* ======================================================= D0FIFOSEL ======================================================= */
- #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
- #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
- #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
- #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
- #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
- #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
- #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
- #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
-/* ======================================================= D0FIFOCTR ======================================================= */
- #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
- #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
- #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
- #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
- #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
-/* ======================================================= D1FIFOSEL ======================================================= */
- #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
- #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
- #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
- #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
- #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
- #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
- #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
- #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
-/* ======================================================= D1FIFOCTR ======================================================= */
- #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
- #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
- #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
- #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
- #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
-/* ======================================================== INTENB0 ======================================================== */
- #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */
- #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */
- #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */
- #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */
- #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */
- #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */
- #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */
- #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */
- #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */
-/* ======================================================== INTENB1 ======================================================== */
- #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */
- #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */
- #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */
- #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */
- #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */
- #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */
- #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */
- #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */
- #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */
-/* ======================================================== BRDYENB ======================================================== */
- #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */
- #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */
-/* ======================================================== NRDYENB ======================================================== */
- #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */
- #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */
-/* ======================================================== BEMPENB ======================================================== */
- #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */
- #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */
-/* ======================================================== SOFCFG ========================================================= */
- #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */
- #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */
- #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */
- #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */
- #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */
-/* ======================================================== PHYSET ========================================================= */
- #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */
- #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */
- #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */
- #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
- #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */
- #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */
- #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */
- #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */
-/* ======================================================== INTSTS0 ======================================================== */
- #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */
- #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */
- #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */
- #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */
- #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */
- #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */
- #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */
- #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */
- #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */
- #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
- #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */
- #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */
- #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */
- #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */
-/* ======================================================== INTSTS1 ======================================================== */
- #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */
- #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */
- #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */
- #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */
- #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */
- #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */
- #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */
- #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */
- #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */
- #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */
- #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */
-/* ======================================================== BRDYSTS ======================================================== */
- #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */
- #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */
-/* ======================================================== NRDYSTS ======================================================== */
- #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */
- #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */
-/* ======================================================== BEMPSTS ======================================================== */
- #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */
- #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */
-/* ======================================================== FRMNUM ========================================================= */
- #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */
- #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */
- #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */
- #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */
-/* ======================================================== UFRMNUM ======================================================== */
- #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */
- #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */
- #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */
-/* ======================================================== USBADDR ======================================================== */
- #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */
- #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */
- #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */
- #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */
-/* ======================================================== USBREQ ========================================================= */
- #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
- #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
- #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
- #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
-/* ======================================================== USBVAL ========================================================= */
- #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */
- #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
-/* ======================================================== USBINDX ======================================================== */
- #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
- #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
-/* ======================================================== USBLENG ======================================================== */
- #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */
- #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
-/* ======================================================== DCPCFG ========================================================= */
- #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
- #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
- #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
- #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
-/* ======================================================== DCPMAXP ======================================================== */
- #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
- #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
- #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */
-/* ======================================================== DCPCTR ========================================================= */
- #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
- #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */
- #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */
- #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
- #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
- #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
- #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
- #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */
- #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */
- #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
-/* ======================================================== PIPESEL ======================================================== */
- #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */
- #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== PIPECFG ======================================================== */
- #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */
- #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */
- #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */
- #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
- #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
- #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */
- #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */
-/* ======================================================= PIPEMAXP ======================================================== */
- #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
- #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
- #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */
-/* ======================================================= PIPEPERI ======================================================== */
- #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */
- #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */
- #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */
-/* ======================================================= PIPE_CTR ======================================================== */
- #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
- #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */
- #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
- #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
- #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */
- #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */
- #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
- #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
- #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
- #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
- #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */
- #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
-/* ======================================================== DEVADD ========================================================= */
- #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */
- #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */
- #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */
- #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */
- #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */
-/* ====================================================== USBBCCTRL0 ======================================================= */
- #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */
- #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */
- #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */
- #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */
- #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */
- #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */
- #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */
- #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */
- #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */
- #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */
-/* ======================================================== UCKSEL ========================================================= */
- #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */
- #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */
-/* ========================================================= USBMC ========================================================= */
- #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */
- #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */
- #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */
-/* ======================================================== PHYSLEW ======================================================== */
- #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */
- #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */
- #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */
- #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */
- #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */
-/* ======================================================== LPCTRL ========================================================= */
- #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */
- #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */
-/* ========================================================= LPSTS ========================================================= */
- #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */
- #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */
-/* ======================================================== BCCTRL ========================================================= */
- #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */
- #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */
- #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */
- #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */
- #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */
- #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */
- #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */
- #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */
- #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */
-/* ======================================================= PL1CTRL1 ======================================================== */
- #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */
- #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */
- #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
- #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */
- #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */
- #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */
- #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */
-/* ======================================================= PL1CTRL2 ======================================================== */
- #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */
- #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */
- #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */
-/* ======================================================= HL1CTRL1 ======================================================== */
- #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */
- #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */
- #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */
- #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */
-/* ======================================================= HL1CTRL2 ======================================================== */
- #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */
- #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */
- #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */
- #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */
- #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */
- #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */
-/* ======================================================== DPUSR0R ======================================================== */
- #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */
- #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */
- #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */
- #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */
-/* ======================================================== DPUSR1R ======================================================== */
- #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */
- #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */
- #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */
- #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */
- #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */
- #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */
- #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */
-/* ======================================================== DPUSR2R ======================================================== */
- #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */
- #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */
- #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */
- #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */
- #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */
- #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */
- #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */
-/* ======================================================== DPUSRCR ======================================================== */
- #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */
- #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */
- #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */
-/* ====================================================== DPUSR0R_FS ======================================================= */
- #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */
- #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */
- #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */
- #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */
- #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */
- #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */
- #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */
- #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */
- #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */
- #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */
-/* ====================================================== DPUSR1R_FS ======================================================= */
- #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */
- #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */
- #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */
- #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */
- #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */
- #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */
- #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */
- #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */
- #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_WDT ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= WDTRR ========================================================= */
- #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */
- #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */
-/* ========================================================= WDTCR ========================================================= */
- #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */
- #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */
- #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */
- #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */
- #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */
- #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */
- #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */
- #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */
-/* ========================================================= WDTSR ========================================================= */
- #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
- #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
- #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
- #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
- #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
- #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
-/* ======================================================== WDTRCR ========================================================= */
- #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */
- #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */
-/* ======================================================= WDTCSTPR ======================================================== */
- #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */
- #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_TZF ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== TZFOAD ========================================================= */
- #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
- #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ========================================================= TZFPT ========================================================= */
- #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
- #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
- #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
- #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
-/* ======================================================== TZFSAR ========================================================= */
- #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */
- #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_CACHE ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================== CCACTL ========================================================= */
- #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */
- #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */
-/* ======================================================== CCAFCT ========================================================= */
- #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */
- #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */
-/* ======================================================== CCALCF ========================================================= */
- #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */
- #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */
-/* ======================================================== SCACTL ========================================================= */
- #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */
- #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */
-/* ======================================================== SCAFCT ========================================================= */
- #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */
- #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */
-/* ======================================================== SCALCF ========================================================= */
- #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */
- #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */
-/* ======================================================== CAPOAD ========================================================= */
- #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
- #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
-/* ======================================================== CAPRCR ========================================================= */
- #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */
- #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */
- #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */
- #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
-
-/* =========================================================================================================================== */
-/* ================ R_CPSCU ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= CSAR ========================================================== */
- #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */
- #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */
- #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */
- #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */
- #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */
- #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */
-/* ======================================================== SRAMSAR ======================================================== */
- #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */
- #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */
- #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */
- #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */
- #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */
- #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */
-/* ======================================================= STBRAMSAR ======================================================= */
- #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */
- #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */
-/* ======================================================== DTCSAR ========================================================= */
- #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */
- #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */
-/* ======================================================== DMACSAR ======================================================== */
- #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */
- #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */
-/* ======================================================== ICUSARA ======================================================== */
- #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */
- #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */
-/* ======================================================== ICUSARB ======================================================== */
- #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */
- #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */
-/* ======================================================== ICUSARC ======================================================== */
- #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */
- #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */
-/* ======================================================== ICUSARD ======================================================== */
- #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */
- #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */
-/* ======================================================== ICUSARE ======================================================== */
- #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */
- #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */
- #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */
- #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */
- #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */
- #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */
- #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */
- #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */
- #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */
- #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */
- #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */
-/* ======================================================== ICUSARF ======================================================== */
- #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */
- #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */
- #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */
- #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */
- #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */
-/* ======================================================== ICUSARG ======================================================== */
- #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
- #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== ICUSARH ======================================================== */
- #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
- #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== ICUSARI ======================================================== */
- #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
- #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== BUSSARA ======================================================== */
- #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */
- #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */
-/* ======================================================== BUSSARB ======================================================== */
- #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */
- #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */
-/* ======================================================= MMPUSARA ======================================================== */
- #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */
- #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */
-/* ======================================================= MMPUSARB ======================================================== */
- #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */
- #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */
-/* ======================================================== CPUDSAR ======================================================== */
- #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */
- #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_CEC ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= CADR ========================================================== */
- #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */
- #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */
- #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */
- #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */
- #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */
- #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */
- #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */
- #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */
- #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */
- #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */
- #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */
- #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */
- #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */
- #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */
- #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */
- #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */
- #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */
-/* ======================================================== CECCTL1 ======================================================== */
- #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */
- #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */
- #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */
- #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */
- #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */
- #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */
- #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */
- #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */
- #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */
-/* ========================================================= STATB ========================================================= */
- #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */
- #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */
-/* ========================================================= STATL ========================================================= */
- #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */
- #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */
-/* ========================================================= LGC0L ========================================================= */
- #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */
- #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */
-/* ========================================================= LGC1L ========================================================= */
- #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */
- #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */
-/* ========================================================= DATB ========================================================== */
- #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */
- #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */
-/* ========================================================= NOMT ========================================================== */
- #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */
- #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */
-/* ======================================================== STATLL ========================================================= */
- #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */
- #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */
-/* ======================================================== STATLH ========================================================= */
- #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */
- #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */
-/* ======================================================== STATBL ========================================================= */
- #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */
- #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */
-/* ======================================================== STATBH ========================================================= */
- #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */
- #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */
-/* ======================================================== LGC0LL ========================================================= */
- #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */
- #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */
-/* ======================================================== LGC0LH ========================================================= */
- #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */
- #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */
-/* ======================================================== LGC1LL ========================================================= */
- #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */
- #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */
-/* ======================================================== LGC1LH ========================================================= */
- #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */
- #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */
-/* ========================================================= DATBL ========================================================= */
- #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */
- #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */
-/* ========================================================= DATBH ========================================================= */
- #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */
- #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */
-/* ========================================================= NOMP ========================================================== */
- #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */
- #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */
-/* ======================================================== CECEXMD ======================================================== */
- #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */
- #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */
- #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */
- #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */
- #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */
- #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= CECEXMON ======================================================== */
- #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */
- #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */
- #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */
- #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */
-/* ========================================================= CTXD ========================================================== */
-/* ========================================================= CRXD ========================================================== */
-/* ========================================================= CECES ========================================================= */
- #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */
- #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */
- #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */
- #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */
- #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */
- #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */
- #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */
- #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */
- #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */
-/* ========================================================= CECS ========================================================== */
- #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */
- #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */
- #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */
- #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */
- #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */
- #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */
- #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */
- #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */
- #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */
- #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */
- #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */
- #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */
-/* ========================================================= CECFC ========================================================= */
- #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */
- #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */
- #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */
- #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */
- #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */
- #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */
- #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */
- #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */
-/* ======================================================== CECCTL0 ======================================================== */
- #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */
- #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */
- #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */
- #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */
- #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */
- #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */
- #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */
- #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */
- #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_OSPI ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== DCR ========================================================== */
- #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */
- #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */
- #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */
-/* ========================================================== DAR ========================================================== */
- #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */
- #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */
- #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */
- #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */
- #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */
- #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */
- #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */
-/* ========================================================= DCSR ========================================================== */
- #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */
- #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */
- #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */
- #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */
- #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */
- #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */
- #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */
- #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */
- #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */
- #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */
- #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */
- #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */
- #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */
- #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */
- #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */
- #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */
- #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */
- #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */
-/* ========================================================== DSR ========================================================== */
- #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */
- #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */
- #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */
- #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */
-/* ========================================================= MDTR ========================================================== */
- #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */
- #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */
- #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */
- #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */
- #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */
- #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */
- #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */
- #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */
- #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */
- #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */
-/* ========================================================= ACTR ========================================================== */
- #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */
- #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= ACAR ========================================================== */
- #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */
- #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */
-/* ======================================================== DRCSTR ========================================================= */
- #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */
- #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */
- #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */
- #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */
- #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */
- #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */
- #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */
- #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */
- #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */
- #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */
- #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */
- #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */
- #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */
- #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */
- #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */
-/* ======================================================== DWCSTR ========================================================= */
- #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */
- #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */
- #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */
- #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */
- #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */
- #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */
- #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */
- #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */
- #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */
- #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */
- #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */
- #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */
- #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */
- #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */
- #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */
-/* ========================================================= DCSTR ========================================================= */
- #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */
- #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */
- #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */
- #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */
- #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */
- #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */
-/* ========================================================= CDSR ========================================================== */
- #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */
- #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */
- #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */
- #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */
- #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */
- #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */
- #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */
- #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */
- #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */
- #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */
- #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */
- #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */
- #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */
- #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */
- #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */
-/* ========================================================= MDLR ========================================================== */
- #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */
- #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */
- #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */
- #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */
- #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */
- #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */
- #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */
- #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */
-/* ========================================================= MRWCR ========================================================= */
- #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */
- #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */
- #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */
- #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */
- #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */
- #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */
-/* ======================================================== MRWCSR ========================================================= */
- #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */
- #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */
- #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */
- #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */
- #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */
- #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */
- #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */
- #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */
- #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */
- #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */
- #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */
- #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */
- #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */
- #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */
- #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */
- #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */
- #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */
- #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */
- #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */
-/* ========================================================== ESR ========================================================== */
- #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */
- #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */
- #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */
- #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */
-/* ========================================================= CWNDR ========================================================= */
- #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */
- #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= CWDR ========================================================== */
- #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */
- #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */
- #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */
- #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */
- #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */
-/* ========================================================== CRR ========================================================== */
- #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */
- #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */
- #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */
- #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */
- #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */
- #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */
-/* ========================================================= ACSR ========================================================== */
- #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */
- #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */
- #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */
- #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */
-/* ======================================================== DCSMXR ========================================================= */
- #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */
- #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */
- #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */
- #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */
-/* ======================================================== DWSCTSR ======================================================== */
- #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */
- #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */
- #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */
- #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */
-
-/* =========================================================================================================================== */
-/* ================ R_ADC_B0 ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================= ADCLKENR ======================================================== */
- #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */
- #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
-/* ======================================================== ADCLKSR ======================================================== */
- #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */
- #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */
-/* ======================================================== ADCLKCR ======================================================== */
- #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
- #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */
- #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */
-/* ======================================================== ADSYCR ========================================================= */
- #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */
- #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */
- #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */
- #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */
- #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADERINTCR ======================================================= */
- #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */
- #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */
- #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADOVFINTCR ======================================================= */
- #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */
- #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */
- #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADCALINTCR ======================================================= */
- #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */
- #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */
- #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */
-/* ========================================================= ADMDR ========================================================= */
- #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */
- #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */
- #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADGSPCR ======================================================== */
- #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */
- #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */
- #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */
- #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */
- #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */
- #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */
- #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */
- #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */
- #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */
-/* ======================================================== ADSGER ========================================================= */
- #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */
- #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */
-/* ======================================================== ADSGCR0 ======================================================== */
- #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */
- #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */
- #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */
- #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */
- #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */
-/* ======================================================== ADSGCR1 ======================================================== */
- #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */
- #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */
- #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */
- #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */
- #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */
-/* ======================================================== ADSGCR2 ======================================================== */
- #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */
- #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */
-/* ======================================================== ADINTCR ======================================================== */
- #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */
- #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x3ffUL) /*!< ADIEn (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGEXT0 ======================================================= */
- #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT1 ======================================================= */
- #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT2 ======================================================= */
- #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT3 ======================================================= */
- #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT4 ======================================================= */
- #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT5 ======================================================= */
- #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT6 ======================================================= */
- #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT7 ======================================================= */
- #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGEXT8 ======================================================= */
- #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
- #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
- #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADTRGELC0 ======================================================= */
- #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC1 ======================================================= */
- #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC2 ======================================================= */
- #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC3 ======================================================= */
- #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC4 ======================================================= */
- #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC5 ======================================================= */
- #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC6 ======================================================= */
- #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC7 ======================================================= */
- #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGELC8 ======================================================= */
- #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
- #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADTRGGPT0 ======================================================= */
- #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT1 ======================================================= */
- #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT2 ======================================================= */
- #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT3 ======================================================= */
- #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT4 ======================================================= */
- #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT5 ======================================================= */
- #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT6 ======================================================= */
- #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT7 ======================================================= */
- #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGGPT8 ======================================================= */
- #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
- #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
- #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADTRGDLR0 ======================================================= */
- #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */
- #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */
- #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */
-/* ======================================================= ADTRGDLR1 ======================================================= */
- #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */
- #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */
- #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */
-/* ======================================================= ADTRGDLR2 ======================================================= */
- #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */
- #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */
- #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */
-/* ======================================================= ADTRGDLR3 ======================================================= */
- #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */
- #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */
- #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */
-/* ======================================================= ADTRGDLR4 ======================================================= */
- #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */
- #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */
-/* ======================================================= ADSGDCR0 ======================================================== */
- #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR1 ======================================================== */
- #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR2 ======================================================== */
- #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR3 ======================================================== */
- #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR4 ======================================================== */
- #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR5 ======================================================== */
- #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR6 ======================================================== */
- #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR7 ======================================================== */
- #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADSGDCR8 ======================================================== */
- #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
- #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
- #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
- #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
- #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
- #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADSSTR0 ======================================================== */
- #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */
- #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */
- #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR1 ======================================================== */
- #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */
- #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */
- #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR2 ======================================================== */
- #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */
- #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */
- #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR3 ======================================================== */
- #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */
- #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */
- #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR4 ======================================================== */
- #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */
- #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */
- #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR5 ======================================================== */
- #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */
- #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */
- #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR6 ======================================================== */
- #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */
- #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */
- #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */
-/* ======================================================== ADSSTR7 ======================================================== */
- #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */
- #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */
- #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */
-/* ======================================================= ADCNVSTR ======================================================== */
- #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */
- #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */
- #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */
- #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */
-/* ======================================================= ADCALSTCR ======================================================= */
- #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */
- #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */
- #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */
- #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */
-/* ======================================================== ADSHCR0 ======================================================== */
- #define R_ADC_B0_ADSHCR0_SHEN0_Pos (0UL) /*!< SHEN0 (Bit 0) */
- #define R_ADC_B0_ADSHCR0_SHEN0_Msk (0x1UL) /*!< SHEN0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSHCR0_SHEN1_Pos (1UL) /*!< SHEN1 (Bit 1) */
- #define R_ADC_B0_ADSHCR0_SHEN1_Msk (0x2UL) /*!< SHEN1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSHCR0_SHEN2_Pos (2UL) /*!< SHEN2 (Bit 2) */
- #define R_ADC_B0_ADSHCR0_SHEN2_Msk (0x4UL) /*!< SHEN2 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADSHSTR0 ======================================================== */
- #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */
- #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */
- #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */
-/* ======================================================== ADSHCR1 ======================================================== */
- #define R_ADC_B0_ADSHCR1_SHEN4_Pos (0UL) /*!< SHEN4 (Bit 0) */
- #define R_ADC_B0_ADSHCR1_SHEN4_Msk (0x1UL) /*!< SHEN4 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSHCR1_SHEN5_Pos (1UL) /*!< SHEN5 (Bit 1) */
- #define R_ADC_B0_ADSHCR1_SHEN5_Msk (0x2UL) /*!< SHEN5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSHCR1_SHEN6_Pos (2UL) /*!< SHEN6 (Bit 2) */
- #define R_ADC_B0_ADSHCR1_SHEN6_Msk (0x4UL) /*!< SHEN6 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADSHSTR1 ======================================================== */
- #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */
- #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */
- #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */
-/* ======================================================= ADCALSHCR ======================================================= */
- #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */
- #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */
- #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */
- #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */
-/* ======================================================== ADPGACR ======================================================== */
- #define R_ADC_B0_ADPGACR_PGADEN_Pos (1UL) /*!< PGADEN (Bit 1) */
- #define R_ADC_B0_ADPGACR_PGADEN_Msk (0x2UL) /*!< PGADEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGACR_PGASEL1_Pos (2UL) /*!< PGASEL1 (Bit 2) */
- #define R_ADC_B0_ADPGACR_PGASEL1_Msk (0x4UL) /*!< PGASEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGACR_PGAENAMP_Pos (3UL) /*!< PGAENAMP (Bit 3) */
- #define R_ADC_B0_ADPGACR_PGAENAMP_Msk (0x8UL) /*!< PGAENAMP (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGACR_PGAGEN_Pos (16UL) /*!< PGAGEN (Bit 16) */
- #define R_ADC_B0_ADPGACR_PGAGEN_Msk (0x10000UL) /*!< PGAGEN (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGACR_PGADG_Pos (20UL) /*!< PGADG (Bit 20) */
- #define R_ADC_B0_ADPGACR_PGADG_Msk (0x300000UL) /*!< PGADG (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADPGACR_PGAGAIN_Pos (24UL) /*!< PGAGAIN (Bit 24) */
- #define R_ADC_B0_ADPGACR_PGAGAIN_Msk (0xf000000UL) /*!< PGAGAIN (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADPGAMONCR ======================================================= */
- #define R_ADC_B0_ADPGAMONCR_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
- #define R_ADC_B0_ADPGAMONCR_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL0_Pos (16UL) /*!< MONSEL0 (Bit 16) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL0_Msk (0x10000UL) /*!< MONSEL0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL1_Pos (17UL) /*!< MONSEL1 (Bit 17) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL1_Msk (0x20000UL) /*!< MONSEL1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL2_Pos (18UL) /*!< MONSEL2 (Bit 18) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL2_Msk (0x40000UL) /*!< MONSEL2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL3_Pos (19UL) /*!< MONSEL3 (Bit 19) */
- #define R_ADC_B0_ADPGAMONCR_MONSEL3_Msk (0x80000UL) /*!< MONSEL3 (Bitfield-Mask: 0x01) */
-/* ======================================================== ADREFCR ======================================================== */
- #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */
- #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */
-/* ======================================================= ADUOFTR0 ======================================================== */
- #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR1 ======================================================== */
- #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR2 ======================================================== */
- #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR3 ======================================================== */
- #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR4 ======================================================== */
- #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR5 ======================================================== */
- #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR6 ======================================================== */
- #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADUOFTR7 ======================================================== */
- #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
- #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
-/* ======================================================== ADUGTR0 ======================================================== */
- #define R_ADC_B0_ADUGTR0_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR0_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR1 ======================================================== */
- #define R_ADC_B0_ADUGTR1_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR1_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR2 ======================================================== */
- #define R_ADC_B0_ADUGTR2_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR2_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR3 ======================================================== */
- #define R_ADC_B0_ADUGTR3_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR3_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR4 ======================================================== */
- #define R_ADC_B0_ADUGTR4_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR4_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR5 ======================================================== */
- #define R_ADC_B0_ADUGTR5_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR5_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR6 ======================================================== */
- #define R_ADC_B0_ADUGTR6_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR6_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ======================================================== ADUGTR7 ======================================================== */
- #define R_ADC_B0_ADUGTR7_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
- #define R_ADC_B0_ADUGTR7_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
-/* ====================================================== ADLIMINTCR ======================================================= */
- #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */
- #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */
-/* ======================================================= ADLIMTR0 ======================================================== */
- #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR1 ======================================================== */
- #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR2 ======================================================== */
- #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR3 ======================================================== */
- #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR4 ======================================================== */
- #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR5 ======================================================== */
- #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR6 ======================================================== */
- #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADLIMTR7 ======================================================== */
- #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */
- #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
- #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPENR ======================================================== */
- #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */
- #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */
-/* ====================================================== ADCMPINTCR ======================================================= */
- #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */
- #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCCMPCR0 ======================================================= */
- #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */
- #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */
- #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADCCMPCR1 ======================================================= */
- #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */
- #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */
- #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADCMPMDR0 ======================================================= */
- #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */
- #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */
-/* ======================================================= ADCMPMDR1 ======================================================= */
- #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */
- #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */
-/* ======================================================= ADCMPTBR0 ======================================================= */
- #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR1 ======================================================= */
- #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR2 ======================================================= */
- #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR3 ======================================================= */
- #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR4 ======================================================= */
- #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR5 ======================================================= */
- #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR6 ======================================================= */
- #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADCMPTBR7 ======================================================= */
- #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
- #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
- #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
-/* ======================================================= ADFIFOCR ======================================================== */
- #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */
- #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADFIFOINTCR ====================================================== */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */
- #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */
-/* ===================================================== ADFIFOINTLR0 ====================================================== */
- #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */
- #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */
-/* ===================================================== ADFIFOINTLR1 ====================================================== */
- #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */
- #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */
-/* ===================================================== ADFIFOINTLR2 ====================================================== */
- #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */
- #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */
-/* ===================================================== ADFIFOINTLR3 ====================================================== */
- #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */
- #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */
-/* ===================================================== ADFIFOINTLR4 ====================================================== */
- #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */
- #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR0 ======================================================== */
- #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR1 ======================================================== */
- #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR2 ======================================================== */
- #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR3 ======================================================== */
- #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR4 ======================================================== */
- #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR5 ======================================================== */
- #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR6 ======================================================== */
- #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR7 ======================================================== */
- #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR8 ======================================================== */
- #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================== ADCHCR9 ======================================================== */
- #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR10 ======================================================== */
- #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR11 ======================================================== */
- #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR12 ======================================================== */
- #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR13 ======================================================== */
- #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR14 ======================================================== */
- #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR15 ======================================================== */
- #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR16 ======================================================== */
- #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR17 ======================================================== */
- #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR18 ======================================================== */
- #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR19 ======================================================== */
- #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR20 ======================================================== */
- #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR21 ======================================================== */
- #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR22 ======================================================== */
- #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR23 ======================================================== */
- #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR24 ======================================================== */
- #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR25 ======================================================== */
- #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR26 ======================================================== */
- #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR27 ======================================================== */
- #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR28 ======================================================== */
- #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR29 ======================================================== */
- #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR30 ======================================================== */
- #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR31 ======================================================== */
- #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR32 ======================================================== */
- #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR33 ======================================================== */
- #define R_ADC_B0_ADCHCR33_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR33_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR33_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR33_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR33_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR33_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR33_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR33_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR34 ======================================================== */
- #define R_ADC_B0_ADCHCR34_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR34_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR34_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR34_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR34_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR34_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR34_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR34_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR35 ======================================================== */
- #define R_ADC_B0_ADCHCR35_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR35_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR35_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR35_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR35_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR35_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR35_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR35_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADCHCR36 ======================================================== */
- #define R_ADC_B0_ADCHCR36_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
- #define R_ADC_B0_ADCHCR36_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
- #define R_ADC_B0_ADCHCR36_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
- #define R_ADC_B0_ADCHCR36_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADCHCR36_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
- #define R_ADC_B0_ADCHCR36_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCHCR36_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
- #define R_ADC_B0_ADCHCR36_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA0 ======================================================= */
- #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA1 ======================================================= */
- #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA2 ======================================================= */
- #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA3 ======================================================= */
- #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA4 ======================================================= */
- #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA5 ======================================================= */
- #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA6 ======================================================= */
- #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA7 ======================================================= */
- #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA8 ======================================================= */
- #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRA9 ======================================================= */
- #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA10 ======================================================= */
- #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA11 ======================================================= */
- #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA12 ======================================================= */
- #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA13 ======================================================= */
- #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA14 ======================================================= */
- #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA15 ======================================================= */
- #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA16 ======================================================= */
- #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA17 ======================================================= */
- #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA18 ======================================================= */
- #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA19 ======================================================= */
- #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA20 ======================================================= */
- #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA21 ======================================================= */
- #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA22 ======================================================= */
- #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA23 ======================================================= */
- #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA24 ======================================================= */
- #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA25 ======================================================= */
- #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA26 ======================================================= */
- #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA27 ======================================================= */
- #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA28 ======================================================= */
- #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA29 ======================================================= */
- #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA30 ======================================================= */
- #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA31 ======================================================= */
- #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA32 ======================================================= */
- #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA33 ======================================================= */
- #define R_ADC_B0_ADDOPCRA33_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA33_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA34 ======================================================= */
- #define R_ADC_B0_ADDOPCRA34_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA34_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA35 ======================================================= */
- #define R_ADC_B0_ADDOPCRA35_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA35_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ====================================================== ADDOPCRA36 ======================================================= */
- #define R_ADC_B0_ADDOPCRA36_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
- #define R_ADC_B0_ADDOPCRA36_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
- #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADDOPCRB0 ======================================================= */
- #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB1 ======================================================= */
- #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB2 ======================================================= */
- #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB3 ======================================================= */
- #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB4 ======================================================= */
- #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB5 ======================================================= */
- #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB6 ======================================================= */
- #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB7 ======================================================= */
- #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB8 ======================================================= */
- #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRB9 ======================================================= */
- #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB10 ======================================================= */
- #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB11 ======================================================= */
- #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB12 ======================================================= */
- #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB13 ======================================================= */
- #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB14 ======================================================= */
- #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB15 ======================================================= */
- #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB16 ======================================================= */
- #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB17 ======================================================= */
- #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB18 ======================================================= */
- #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB19 ======================================================= */
- #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB20 ======================================================= */
- #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB21 ======================================================= */
- #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB22 ======================================================= */
- #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB23 ======================================================= */
- #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB24 ======================================================= */
- #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB25 ======================================================= */
- #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB26 ======================================================= */
- #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB27 ======================================================= */
- #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB28 ======================================================= */
- #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB29 ======================================================= */
- #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB30 ======================================================= */
- #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB31 ======================================================= */
- #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB32 ======================================================= */
- #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB33 ======================================================= */
- #define R_ADC_B0_ADDOPCRB33_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB33_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB33_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB33_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB34 ======================================================= */
- #define R_ADC_B0_ADDOPCRB34_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB34_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB34_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB34_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB35 ======================================================= */
- #define R_ADC_B0_ADDOPCRB35_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB35_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB35_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB35_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ====================================================== ADDOPCRB36 ======================================================= */
- #define R_ADC_B0_ADDOPCRB36_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
- #define R_ADC_B0_ADDOPCRB36_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRB36_ADC_Pos (8UL) /*!< ADC (Bit 8) */
- #define R_ADC_B0_ADDOPCRB36_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
- #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
-/* ======================================================= ADDOPCRC0 ======================================================= */
- #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC1 ======================================================= */
- #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC2 ======================================================= */
- #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC3 ======================================================= */
- #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC4 ======================================================= */
- #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC5 ======================================================= */
- #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC6 ======================================================= */
- #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC7 ======================================================= */
- #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC8 ======================================================= */
- #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADDOPCRC9 ======================================================= */
- #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC10 ======================================================= */
- #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC11 ======================================================= */
- #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC12 ======================================================= */
- #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC13 ======================================================= */
- #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC14 ======================================================= */
- #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC15 ======================================================= */
- #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC16 ======================================================= */
- #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC17 ======================================================= */
- #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC18 ======================================================= */
- #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC19 ======================================================= */
- #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC20 ======================================================= */
- #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC21 ======================================================= */
- #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC22 ======================================================= */
- #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC23 ======================================================= */
- #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC24 ======================================================= */
- #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC25 ======================================================= */
- #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC26 ======================================================= */
- #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC27 ======================================================= */
- #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC28 ======================================================= */
- #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC29 ======================================================= */
- #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC30 ======================================================= */
- #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC31 ======================================================= */
- #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC32 ======================================================= */
- #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC33 ======================================================= */
- #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC33_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC33_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC34 ======================================================= */
- #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC34_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC34_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC35 ======================================================= */
- #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC35_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC35_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ====================================================== ADDOPCRC36 ======================================================= */
- #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
- #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADDOPCRC36_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
- #define R_ADC_B0_ADDOPCRC36_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
- #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
- #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
-/* ======================================================= ADCALSTR ======================================================== */
- #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */
- #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */
- #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */
-/* ======================================================= ADTRGENR ======================================================== */
- #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */
- #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */
-/* ======================================================== ADSYSTR ======================================================== */
- #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */
- #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */
-/* ========================================================= ADSTR ========================================================= */
- #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */
- #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */
-/* ======================================================== ADSTOPR ======================================================== */
- #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */
- #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */
- #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */
-/* ========================================================= ADSR ========================================================== */
- #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */
- #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */
- #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */
- #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */
- #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */
-/* ======================================================== ADGRSR ========================================================= */
- #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */
- #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */
-/* ======================================================== ADERSR ========================================================= */
- #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */
- #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */
- #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */
-/* ======================================================== ADERSCR ======================================================== */
- #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */
- #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */
- #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADCALENDSR ======================================================= */
- #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */
- #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */
- #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADCALENDSCR ====================================================== */
- #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */
- #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */
- #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADOVFERSR ======================================================= */
- #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */
- #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */
- #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADOVFCHSR0 ======================================================= */
- #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Pos (0UL) /*!< OFVCHFn (Bit 0) */
- #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Msk (0x1fffffffUL) /*!< OFVCHFn (Bitfield-Mask: 0x1fffffff) */
-/* ======================================================= ADOVFEXSR ======================================================= */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Pos (2UL) /*!< OVFEXF2 (Bit 2) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Msk (0x4UL) /*!< OVFEXF2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Pos (7UL) /*!< OVFEXF7 (Bit 7) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Msk (0x80UL) /*!< OVFEXF7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */
- #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADOVFERSCR ======================================================= */
- #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */
- #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */
- #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADOVFCHSCR0 ====================================================== */
- #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */
- #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x1fffffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x1fffffff) */
-/* ====================================================== ADOVFEXSCR ======================================================= */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Pos (2UL) /*!< OVFEXC2 (Bit 2) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Msk (0x4UL) /*!< OVFEXC2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Pos (7UL) /*!< OVFEXC7 (Bit 7) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Msk (0x80UL) /*!< OVFEXC7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */
- #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFOSR0 ======================================================= */
- #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */
- #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */
- #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADFIFOSR1 ======================================================= */
- #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */
- #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */
- #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADFIFOSR2 ======================================================= */
- #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */
- #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */
- #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADFIFOSR3 ======================================================= */
- #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */
- #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */
- #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */
- #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADFIFOSR4 ======================================================= */
- #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */
- #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */
-/* ======================================================= ADFIFODCR ======================================================= */
- #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */
- #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */
-/* ====================================================== ADFIFOERSR ======================================================= */
- #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */
- #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */
- #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */
- #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */
-/* ====================================================== ADFIFOERSCR ====================================================== */
- #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */
- #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */
- #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */
- #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */
-/* ======================================================= ADCMPTBSR ======================================================= */
- #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */
- #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */
-/* ====================================================== ADCMPTBSCR ======================================================= */
- #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */
- #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */
-/* ====================================================== ADCMPCHSR0 ======================================================= */
- #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */
- #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x1fffffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x1fffffff) */
-/* ======================================================= ADCMPEXSR ======================================================= */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Pos (2UL) /*!< CMPEXF2 (Bit 2) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Msk (0x4UL) /*!< CMPEXF2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Pos (7UL) /*!< CMPEXF7 (Bit 7) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Msk (0x80UL) /*!< CMPEXF7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */
- #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADCMPCHSCR0 ====================================================== */
- #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */
- #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x1fffffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x1fffffff) */
-/* ====================================================== ADCMPEXSCR ======================================================= */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Pos (2UL) /*!< CMPEXC2 (Bit 2) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Msk (0x4UL) /*!< CMPEXC2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Pos (7UL) /*!< CMPEXC7 (Bit 7) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Msk (0x80UL) /*!< CMPEXC7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */
- #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */
-/* ======================================================= ADLIMGRSR ======================================================= */
- #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */
- #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */
-/* ====================================================== ADLIMCHSR0 ======================================================= */
- #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */
- #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x1fffffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x1fffffff) */
-/* ======================================================= ADLIMEXSR ======================================================= */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */
- #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADLIMGRSCR ======================================================= */
- #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */
- #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */
-/* ====================================================== ADLIMCHSCR0 ====================================================== */
- #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */
- #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x1fffffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x1fffffff) */
-/* ====================================================== ADLIMEXSCR ======================================================= */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */
- #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */
-/* ====================================================== ADSCANENDSR ====================================================== */
- #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */
- #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */
-/* ===================================================== ADSCANENDSCR ====================================================== */
- #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */
- #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */
-/* ========================================================= ADDR ========================================================== */
- #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================== ADEXDR ========================================================= */
- #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */
- #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */
- #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR0 ======================================================= */
- #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR1 ======================================================= */
- #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR2 ======================================================= */
- #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR3 ======================================================= */
- #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR4 ======================================================= */
- #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR5 ======================================================= */
- #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR6 ======================================================= */
- #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR7 ======================================================= */
- #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-/* ======================================================= ADFIFODR8 ======================================================= */
- #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */
- #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
- #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */
- #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
- #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */
- #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_DOC_B ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= DOCR ========================================================== */
- #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
- #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
- #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */
- #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */
- #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */
- #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */
- #define R_DOC_B_DOCR_DOPCIE_Pos (7UL) /*!< DOPCIE (Bit 7) */
- #define R_DOC_B_DOCR_DOPCIE_Msk (0x80UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */
-/* ========================================================= DOSR ========================================================== */
- #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */
- #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
-/* ========================================================= DOSCR ========================================================= */
- #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */
- #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
-/* ========================================================= DODIR ========================================================= */
-/* ======================================================== DODSR0 ========================================================= */
-/* ======================================================== DODSR1 ========================================================= */
-
-/* =========================================================================================================================== */
-/* ================ R_SCI_B0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================== RDR ========================================================== */
- #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
- #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
- #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */
- #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */
- #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */
- #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */
- #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
- #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */
- #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */
- #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
-/* ========================================================== TDR ========================================================== */
- #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
- #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
- #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
- #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */
- #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */
-/* ========================================================= CCR0 ========================================================== */
- #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */
- #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */
- #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */
- #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */
- #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */
- #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */
- #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */
- #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */
- #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */
- #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */
-/* ========================================================= CCR1 ========================================================== */
- #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */
- #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */
- #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */
- #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */
- #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */
- #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */
- #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */
- #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */
- #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
- #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */
- #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */
- #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */
- #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
-/* ========================================================= CCR2 ========================================================== */
- #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */
- #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */
- #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */
- #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */
- #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */
- #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */
- #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */
- #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */
- #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */
-/* ========================================================= CCR3 ========================================================== */
- #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */
- #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */
- #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */
- #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */
- #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */
- #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */
- #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */
- #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */
- #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */
- #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */
- #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */
- #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */
- #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */
-/* ========================================================= CCR4 ========================================================== */
- #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
- #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
- #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */
- #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */
- #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */
- #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */
- #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */
- #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */
- #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */
-/* ========================================================= CESR ========================================================== */
- #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */
- #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */
- #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */
-/* ========================================================== ICR ========================================================== */
- #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */
- #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */
- #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */
- #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */
- #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */
- #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */
- #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */
- #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */
- #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */
- #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */
- #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
-/* ========================================================== FCR ========================================================== */
- #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */
- #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
- #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */
- #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */
- #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */
- #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */
- #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */
- #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */
- #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */
-/* ========================================================== MCR ========================================================== */
- #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */
- #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */
- #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */
- #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */
- #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */
- #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */
- #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */
- #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */
- #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */
- #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */
- #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */
- #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */
- #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */
- #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */
- #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */
- #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */
-/* ========================================================== DCR ========================================================== */
- #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */
- #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */
- #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */
- #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */
- #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */
-/* ========================================================= XCR0 ========================================================== */
- #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */
- #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */
- #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */
- #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */
- #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */
- #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */
- #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */
- #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */
- #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */
- #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */
- #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */
- #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */
- #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */
- #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */
- #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */
-/* ========================================================= XCR1 ========================================================== */
- #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */
- #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */
- #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */
- #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */
- #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */
- #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */
- #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */
-/* ========================================================= XCR2 ========================================================== */
- #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */
- #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */
- #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */
- #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */
-/* ========================================================== CSR ========================================================== */
- #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */
- #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */
- #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */
- #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */
- #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */
- #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
- #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */
- #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */
- #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */
- #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */
- #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */
- #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */
- #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */
-/* ========================================================== ISR ========================================================== */
- #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
- #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
- #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
-/* ========================================================= FRSR ========================================================== */
- #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */
- #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */
- #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */
- #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */
- #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */
- #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */
- #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */
-/* ========================================================= FTSR ========================================================== */
- #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */
- #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */
-/* ========================================================== MSR ========================================================== */
- #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */
- #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */
- #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */
- #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */
- #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */
- #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */
-/* ========================================================= XSR0 ========================================================== */
- #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */
- #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */
- #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */
- #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */
- #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */
- #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */
- #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */
- #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */
- #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */
- #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */
- #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */
- #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */
- #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */
- #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */
-/* ========================================================= XSR1 ========================================================== */
- #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */
- #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */
-/* ========================================================= CFCLR ========================================================= */
- #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */
- #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */
- #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */
- #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */
- #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */
- #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */
- #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */
- #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */
- #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */
- #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */
- #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */
-/* ======================================================== ICFCLR ========================================================= */
- #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */
- #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */
-/* ========================================================= FFCLR ========================================================= */
- #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */
- #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */
-/* ========================================================= MFCLR ========================================================= */
- #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */
- #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */
- #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */
- #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */
- #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */
-/* ========================================================= XFCLR ========================================================= */
- #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */
- #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */
- #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */
- #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */
- #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */
- #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */
- #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */
- #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */
- #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */
- #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_SPI_B0 ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SPDR ========================================================== */
-/* ======================================================== SPDECR ========================================================= */
- #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
- #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
- #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */
- #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
- #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */
- #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
- #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */
- #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */
-/* ========================================================= SPCR ========================================================== */
- #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */
- #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */
- #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */
- #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */
- #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */
- #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */
- #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */
- #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */
- #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */
- #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */
- #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */
- #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */
- #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */
- #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */
- #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */
- #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */
- #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */
- #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */
- #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */
- #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */
-/* ========================================================= SPCR2 ========================================================= */
- #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */
- #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */
- #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */
- #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */
- #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */
- #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
- #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */
- #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */
- #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */
- #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
-/* ========================================================= SPCR3 ========================================================= */
- #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
- #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
- #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
- #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
- #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */
- #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */
- #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */
- #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD0 ========================================================= */
- #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD1 ========================================================= */
- #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD2 ========================================================= */
- #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD3 ========================================================= */
- #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD4 ========================================================= */
- #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD5 ========================================================= */
- #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD6 ========================================================= */
- #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ======================================================== SPCMD7 ========================================================= */
- #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
- #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
- #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
- #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
- #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
- #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
- #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
- #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
- #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */
- #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
- #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
- #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
-/* ========================================================= SPDCR ========================================================= */
- #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
- #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */
- #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */
- #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */
- #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */
-/* ======================================================== SPDCR2 ========================================================= */
- #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */
- #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */
- #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
- #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */
-/* ========================================================= SPSR ========================================================== */
- #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */
- #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */
- #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */
- #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */
- #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */
- #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */
- #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */
- #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */
- #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */
- #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */
- #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */
- #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */
- #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */
- #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */
-/* ======================================================== SPTFSR ========================================================= */
- #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */
- #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */
-/* ======================================================== SPRFSR ========================================================= */
- #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */
- #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */
-/* ========================================================= SPPSR ========================================================= */
- #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */
- #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */
-/* ========================================================= SPSRC ========================================================= */
- #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */
- #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */
- #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */
- #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */
- #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */
- #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */
- #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */
- #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */
- #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */
- #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */
-/* ========================================================= SPFCR ========================================================= */
- #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */
- #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */
-
-/* =========================================================================================================================== */
-/* ================ R_TFU ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================= SCDT0 ========================================================= */
- #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */
- #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= SCDT1 ========================================================= */
- #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */
- #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= ATDT0 ========================================================= */
- #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */
- #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */
-/* ========================================================= ATDT1 ========================================================= */
- #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */
- #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */
-
-/** @} */ /* End of group PosMask_peripherals */
-
#ifdef __cplusplus
}
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
index 363e7b7e05..b61fe0f003 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
index a2e07b2f03..d135ed0762 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -64,12 +64,7 @@ void Reset_Handler (void)
SystemInit();
/* Call user application. */
-#ifdef __ARMCC_VERSION
main();
-#elif defined(__GNUC__)
- extern int entry(void);
- entry();
-#endif
while (1)
{
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
index 2e0f1e1c77..13d37745c0 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -36,6 +36,9 @@
/* Mask to select CP bits( 0xF00000 ) */
#define CP_MASK (0xFU << 20)
+/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */
+#define CCR_CACHE_ENABLE (0x000E0201)
+
/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U)
@@ -43,19 +46,8 @@
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
-
-#if defined(__ICCARM__)
- #define BSP_PRV_STACK_LIMIT ((uint32_t) __section_begin(".stack"))
- #define BSP_PRV_STACK_TOP ((uint32_t) __section_end(".stack"))
-#elif defined(__ARMCC_VERSION)
- #define BSP_PRV_STACK_LIMIT ((uint32_t) &Image$$STACK$$ZI$$Base)
- #define BSP_PRV_STACK_TOP ((uint32_t) &Image$$STACK$$ZI$$Base + \
- (uint32_t) &Image$$STACK$$ZI$$Length)
-#elif defined(__GNUC__)
- #define BSP_PRV_STACK_LIMIT ((uint32_t) &__StackLimit)
- #define BSP_PRV_STACK_TOP ((uint32_t) &__StackTop)
-#endif
-
+#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES)
+#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0])
#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5)
/***********************************************************************************************************************
@@ -77,6 +69,11 @@ extern uint32_t Image$$DATA$$Base;
extern uint32_t Image$$DATA$$Length;
extern uint32_t Image$$STACK$$ZI$$Base;
extern uint32_t Image$$STACK$$ZI$$Length;
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+extern uint32_t Load$$DTCM_DATA_INIT$$Base;
+extern uint32_t Image$$DTCM_DATA_INIT$$Base;
+extern uint32_t Image$$DTCM_DATA_INIT$$Length;
+ #endif
#elif defined(__GNUC__)
/* Generated by linker. */
@@ -87,11 +84,20 @@ extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackLimit;
extern uint32_t __StackTop;
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+extern uint32_t __dtcm_data_init_start;
+extern uint32_t __dtcm_data_start__;
+extern uint32_t __dtcm_data_end__;
+ #endif
#elif defined(__ICCARM__)
#pragma section=".bss"
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".stack"
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+ #pragma section=".dtcm_data"
+ #pragma section=".dtcm_data_init"
+ #endif
#endif
/* Initialize static constructors */
@@ -145,6 +151,15 @@ static void bsp_init_uninitialized_vars(void);
**********************************************************************************************************************/
void SystemInit (void)
{
+#if defined(RENESAS_CORTEX_M85)
+
+ /* Enable the ARM core instruction cache, branch prediction and low-overhead-branch extension.
+ * See Section 5.5 of the Cortex-M55 TRM and Section D1.2.9 in the ARMv8-M Architecture Reference Manual */
+ SCB->CCR = (uint32_t) CCR_CACHE_ENABLE;
+ __DSB();
+ __ISB();
+#endif
+
#if __FPU_USED
/* Enable the FPU only when it is used.
@@ -221,6 +236,16 @@ void SystemInit (void)
#endif
#endif
+#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN
+
+ /* Turn on graphics power domain.
+ * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+ R_SYSTEM->PDCTRGD = 0;
+ (void) R_SYSTEM->PDCTRGD;
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+#endif
+
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
@@ -247,9 +272,14 @@ void SystemInit (void)
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
+ #if 33U == __CORTEX_M
/* Use CM33 stack monitor. */
__set_MSPLIM(BSP_PRV_STACK_LIMIT);
+ #else
+
+ /* CM85 stack monitor not yet supported. */
+ #endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
@@ -267,10 +297,21 @@ void SystemInit (void)
/* Copy initialized RAM data from ROM to RAM. */
#if defined(__ARMCC_VERSION)
memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+ memcpy((uint8_t *) &Image$$DTCM_DATA_INIT$$Base,
+ (uint8_t *) &Load$$DTCM_DATA_INIT$$Base,
+ (uint32_t) &Image$$DTCM_DATA_INIT$$Length);
+ #endif
#elif defined(__GNUC__)
memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+ memcpy(&__dtcm_data_start__,
+ &__dtcm_data_init_start,
+ ((uint32_t) &__dtcm_data_end__ - (uint32_t) &__dtcm_data_start__));
+ #endif
#elif defined(__ICCARM__)
- memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
+ memcpy((uint32_t *) __section_begin(".data"),
+ (uint32_t *) __section_begin(".data_init"),
(uint32_t) __section_size(".data"));
/* Copy functions to be executed from RAM. */
@@ -283,8 +324,14 @@ void SystemInit (void)
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
- memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
+ memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"),
+ (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
(uint32_t) __section_size("__DLIB_PERTHREAD_init"));
+ #if BSP_FEATURE_BSP_HAS_DTCM == 1
+ memcpy((uint32_t *) __section_begin(".dtcm_data"),
+ (uint32_t *) __section_begin(".dtcm_data_init"),
+ (uint32_t) __section_size(".dtcm_data"));
+ #endif
#endif
/* Initialize static constructors */
@@ -296,14 +343,12 @@ void SystemInit (void)
(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
p_init_func();
}
-
#elif defined(__GNUC__)
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = 0; i < count; i++)
{
__init_array_start[i]();
}
-
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
@@ -314,8 +359,18 @@ void SystemInit (void)
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
+#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+ /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */
+ #if !BSP_TZ_NONSECURE_BUILD
+
+ /* Perform RTC reset sequence to avoid unintended operation. */
+ R_BSP_Init_RTC();
+ #endif
+#endif
+
#if !BSP_CFG_PFS_PROTECT
- #if BSP_TZ_SECURE_BUILD
+ #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
index a8f399026d..14ce8f0a4b 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -21,7 +21,11 @@
/** @} (end addtogroup BSP_MCU) */
#ifndef BSP_ARM_EXCEPTIONS_H
-#define BSP_ARM_EXCEPTIONS_H
+ #define BSP_ARM_EXCEPTIONS_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
/***********************************************************************************************************************
* Macro definitions
@@ -47,4 +51,8 @@ typedef enum IRQn
SysTick_IRQn = -1, /* 15 System Tick Timer */
} IRQn_Type;
+ #ifdef __cplusplus
+}
+ #endif
+
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
index 2f2374b41b..3ef0bce475 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -36,8 +36,6 @@
#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
-#define BSP_PRV_MAXIMUM_HOCOWTR_HSTS ((uint8_t) 0x6U)
-
/* Wait state definitions for MEMWAIT. */
#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U)
#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (1U)
@@ -57,9 +55,12 @@
#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U)
#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U)
#define BSP_PRV_ROM_THREE_WAIT_CYCLES (3U)
-#define BSP_PRV_SRAM_PRCR_KEY (0x78U)
-#define BSP_PRV_SRAM_UNLOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U)
-#define BSP_PRV_SRAM_LOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U)
+#define BSP_PRV_ROM_FOUR_WAIT_CYCLES (4U)
+#define BSP_PRV_ROM_FIVE_WAIT_CYCLES (5U)
+#define BSP_PRV_SRAM_UNLOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \
+ BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x1U)
+#define BSP_PRV_SRAM_LOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \
+ BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x0U)
/* Calculate value to write to MOMCR (MODRV controls main clock drive strength and MOSEL determines the source of the
* main oscillator). */
@@ -73,9 +74,19 @@
#define BSP_PRV_CKOCR_CKODIV_BIT (4U)
#define BSP_PRV_CKOCR_CKOEN_BIT (7U)
+/* Stop interval of at least 5 SOSC clock cycles between stop and restart of SOSC.
+ * Calculated based on 8Mhz of MOCO clock. */
+#define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (1220U)
+
+/* Locations of bitfields used to configure Peripheral Clocks. */
+#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS (6U)
+#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS)
+#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS (7U)
+#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS)
+
#ifdef BSP_CFG_UCK_DIV
-/* If the MCU has SCKDIVCR2. */
+/* If the MCU has SCKDIVCR2 for USBCK configuration. */
#if !BSP_FEATURE_BSP_HAS_USBCKDIVCR
/* Location of bitfield used to configure USB clock divider. */
@@ -84,13 +95,20 @@
/* If the MCU has USBCKDIVCR. */
#elif BSP_FEATURE_BSP_HAS_USBCKDIVCR
-
- #if BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCK_DIV
- #define BSP_PRV_UCK_DIV (5U)
+ #if BSP_CLOCKS_USB_CLOCK_DIV_1 == BSP_CFG_UCK_DIV
+ #define BSP_PRV_UCK_DIV (0U)
+ #elif BSP_CLOCKS_USB_CLOCK_DIV_2 == BSP_CFG_UCK_DIV
+ #define BSP_PRV_UCK_DIV (1U)
+ #elif BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCK_DIV
+ #define BSP_PRV_UCK_DIV (5U)
#elif BSP_CLOCKS_USB_CLOCK_DIV_4 == BSP_CFG_UCK_DIV
- #define BSP_PRV_UCK_DIV (2U)
+ #define BSP_PRV_UCK_DIV (2U)
#elif BSP_CLOCKS_USB_CLOCK_DIV_5 == BSP_CFG_UCK_DIV
- #define BSP_PRV_UCK_DIV (6U)
+ #define BSP_PRV_UCK_DIV (6U)
+ #elif BSP_CLOCKS_USB_CLOCK_DIV_6 == BSP_CFG_UCK_DIV
+ #define BSP_PRV_UCK_DIV (3U)
+ #elif BSP_CLOCKS_USB_CLOCK_DIV_8 == BSP_CFG_UCK_DIV
+ #define BSP_PRV_UCK_DIV (4U)
#else
#error "BSP_CFG_UCK_DIV not supported."
@@ -98,257 +116,403 @@
#endif
#endif
#endif
-
+#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB source clock by 1
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB source clock by 2
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB source clock by 3
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB source clock by 4
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB source clock by 5
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB source clock by 6
+ #define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB source clock by 8
+#endif /* BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ*/
/* Choose the value to write to FLLCR2 (if applicable). */
#if BSP_PRV_HOCO_USE_FLL
- #if 0U == BSP_CFG_HOCO_FREQUENCY
- #define BSP_PRV_FLL_FLLCR2 (0x1E9U)
- #elif 1U == BSP_CFG_HOCO_FREQUENCY
- #define BSP_PRV_FLL_FLLCR2 (0x226U)
+ #if 1U == BSP_CFG_HOCO_FREQUENCY
+ #define BSP_PRV_FLL_FLLCR2 (0x226U)
#elif 2U == BSP_CFG_HOCO_FREQUENCY
- #define BSP_PRV_FLL_FLLCR2 (0x263U)
+ #define BSP_PRV_FLL_FLLCR2 (0x263U)
+ #elif 4U == BSP_CFG_HOCO_FREQUENCY
+ #define BSP_PRV_FLL_FLLCR2 (0x263U)
+ #else
+
+/* When BSP_CFG_HOCO_FREQUENCY is 0, 4, 7 */
+ #define BSP_PRV_FLL_FLLCR2 (0x1E9U)
#endif
#endif
/* Calculate the value to write to SCKDIVCR. */
-#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 7U) << 24U)
-#if BSP_FEATURE_CGC_HAS_PCLKD
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
+#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U)
+#if BSP_FEATURE_CGC_HAS_PCLKE
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKD
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKC
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0x7U) << 4U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKB
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKA
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U)
#endif
#if BSP_FEATURE_CGC_HAS_BCLK
- #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0x7U) << 16U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U)
#elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
/* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */
- #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U)
#endif
#if BSP_FEATURE_CGC_HAS_FCLK
- #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0x7U) << 28U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U)
#else
- #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U)
+ #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U)
+#endif
+#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \
+ BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS)
+#if BSP_FEATURE_CGC_HAS_CPUCLK
+ #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
+ #define BSP_PRV_STARTUP_SCKDIVCR2 (BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS)
#endif
-#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \
- BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS)
/* The number of clocks is used to size the g_clock_freq array. */
#if BSP_PRV_PLL2_SUPPORTED
- #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + 1U)
+ #if 0 != BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + (BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS - 1) + \
+ BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS)
+ #else
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + 1U)
+ #endif
#elif BSP_PRV_PLL_SUPPORTED
- #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U)
+ #if 0 != BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS
+
+/* Removed offset of 1 since the BSP_CLOCKS_SOURCE_CLOCK_PLL will be reused for BSP_CLOCKS_SOURCE_CLOCK_PLL1P which is included in BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS count. */
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS)
+ #else
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U)
+ #endif
#else
- #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U)
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U)
#endif
/* Calculate PLLCCR value. */
#if BSP_PRV_PLL_SUPPORTED
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
#if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
- #define BSP_PRV_PLSRCSEL (0)
+ #define BSP_PRV_PLSRCSEL (0)
+ #define BSP_PRV_PLL_USED (1)
#elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
- #define BSP_PRV_PLSRCSEL (1)
+ #define BSP_PRV_PLSRCSEL (1)
+ #define BSP_PRV_PLL_USED (1)
+ #else
+ #define BSP_PRV_PLL_USED (0)
#endif
- #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide
- #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8
- #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4
- #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
- BSP_PRV_PLLCCR_PLLMUL_BIT) | \
- (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \
- BSP_CFG_PLL_DIV)
+ #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide
+ #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8
+ #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4
+ #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
+ BSP_PRV_PLLCCR_PLLMUL_BIT) | \
+ (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \
+ BSP_CFG_PLL_DIV)
#endif
#if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
- #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide
- #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6
+ #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
+ #define BSP_PRV_PLSRCSEL (0)
+ #define BSP_PRV_PLL_USED (1)
+ #else
+ #define BSP_PRV_PLL_USED (0)
+ #endif
+ #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide
+ #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6
- #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
- #define BSP_PRV_PLLCCR (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \
+ #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
+ #define BSP_PRV_PLLCCR (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \
(BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)
#endif
+ #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
+ #define BSP_PRV_PLSRCSEL (0)
+ #define BSP_PRV_PLL_USED (1)
+ #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+ #define BSP_PRV_PLSRCSEL (1)
+ #define BSP_PRV_PLL_USED (1)
+ #else
+ #define BSP_PRV_PLL_USED (0)
+ #endif
+
+ #define BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK (0x3FFU)
+ #define BSP_PRV_PLLCCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6
+ #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4
+ #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK) << \
+ BSP_PRV_PLLCCR_PLLMULNF_BIT) | \
+ (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \
+ BSP_CFG_PLL_DIV)
+ #define BSP_PRV_PLLCCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLLCCR2/PLL2CCR2 is 4 bits wide
+ #define BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLLCCR2/PLL2CCR2 starts at bit 4
+ #define BSP_PRV_PLLCCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLLCCR2/PLL2CCR2 starts at bit 8
+ #define BSP_PRV_PLLCCR2 (((BSP_CFG_PLODIVR & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
+ BSP_PRV_PLLCCR2_PLL_DIV_R_BIT) | \
+ ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
+ BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) | \
+ (BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK))
+ #endif
+ #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE
+ #define BSP_PRV_PLL_USED (1)
+ #else
+ #define BSP_PRV_PLL_USED (0)
+ #endif
+
+ #define BSP_PRV_PLLCCR_PLLMUL_MASK (0xFFU) // PLLMUL is 8 bits wide
+ #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL starts at bit 8
+ #define BSP_PRV_PLLCCR_RESET (0x0004U) // Bit 2 must be written as 1
+ #define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
+ BSP_PRV_PLLCCR_PLLMUL_BIT) | \
+ BSP_PRV_PLLCCR_RESET)
+ #endif
#endif
#if BSP_FEATURE_CGC_HAS_PLL2
#if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE
- #define BSP_PRV_PL2SRCSEL (0)
+ #define BSP_PRV_PL2SRCSEL (0)
+ #define BSP_PRV_PLL2_USED (1)
#elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE
- #define BSP_PRV_PL2SRCSEL (1)
+ #define BSP_PRV_PL2SRCSEL (1)
+ #define BSP_PRV_PLL2_USED (1)
+ #else
+ #define BSP_PRV_PLL2_USED (0)
+ #endif
+
+ #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x3FF)
+ #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMULNF_MASK (0x003U)
+ #define BSP_PRV_PLL2CCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6
+ #define BSP_PRV_PLL2CCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4
+ #define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK) << \
+ BSP_PRV_PLL2CCR_PLLMULNF_BIT) | \
+ (BSP_PRV_PL2SRCSEL << BSP_PRV_PLL2CCR_PLSRCSEL_BIT)) | \
+ BSP_CFG_PLL2_DIV)
+ #define BSP_PRV_PLL2CCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLL2CCR2 is 4 bits wide
+ #define BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLL2CCR2 starts at bit 4
+ #define BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLL2CCR2 starts at bit 8
+ #define BSP_PRV_PLL2CCR2 (((BSP_CFG_PL2ODIVR & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \
+ BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT) | \
+ ((BSP_CFG_PL2ODIVQ & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \
+ BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT) | \
+ (BSP_CFG_PL2ODIVP & BSP_PRV_PLL2CCR2_PLL_DIV_MASK))
+ #else
+ #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
+ (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
+ (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos))
#endif
- #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
- (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
- (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos))
#endif
/* All clocks with configurable source except PLL and CLKOUT can use PLL. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
- #define BSP_PRV_STABILIZE_PLL (1)
-#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
- (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
- #define BSP_PRV_PLL_USED (1)
-#else
- #define BSP_PRV_PLL_USED (0)
+ #define BSP_PRV_STABILIZE_PLL (1)
#endif
-/* All clocks with configurable source except the main clock, PLL, and CLKOUT can use PLL2. */
-#if defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
- (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
- #define BSP_PRV_PLL2_USED (1)
-#else
- #define BSP_PRV_PLL2_USED (0)
-#endif
-
-/* All clocks with configurable source except UCK, CANFD can use the main oscillator. */
+/* All clocks with configurable source can use the main oscillator. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
- #define BSP_PRV_STABILIZE_MAIN_OSC (1)
-#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED
- #define BSP_PRV_MAIN_OSC_USED (1)
- #define BSP_PRV_STABILIZE_MAIN_OSC (1)
-#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED
- #define BSP_PRV_MAIN_OSC_USED (1)
- #define BSP_PRV_STABILIZE_MAIN_OSC (1)
-#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
-#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
+ (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
#else
- #define BSP_PRV_MAIN_OSC_USED (0)
+ #define BSP_PRV_MAIN_OSC_USED (0)
#endif
-/* All clocks with configurable source can use HOCO. */
+/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
- #define BSP_PRV_STABILIZE_HOCO (1)
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL_USED
- #define BSP_PRV_HOCO_USED (1)
- #define BSP_PRV_STABILIZE_HOCO (1)
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL2_USED
- #define BSP_PRV_HOCO_USED (1)
- #define BSP_PRV_STABILIZE_HOCO (1)
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
(BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
- #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
#else
- #define BSP_PRV_HOCO_USED (0)
+ #define BSP_PRV_HOCO_USED (0)
#endif
-/* All clocks with configurable source except UCK, CANFD, and PLL can use MOCO. */
+/* All clocks with configurable source except PLL can use MOCO. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
- #define BSP_PRV_STABILIZE_MOCO (1)
+ #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_STABILIZE_MOCO (1)
#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
+ (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
- #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_MOCO_USED (1)
#else
- #define BSP_PRV_MOCO_USED (0)
+ #define BSP_PRV_MOCO_USED (0)
#endif
-/* All clocks with configurable source except UCK, CANFD, and PLL can use LOCO. */
+/* All clocks with configurable source except UCK, CANFD, LCDCLK, USBHSCLK, I3CCLK and PLL can use LOCO. */
#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
- #define BSP_PRV_STABILIZE_LOCO (1)
+ #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_STABILIZE_LOCO (1)
#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
- #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_LOCO_USED (1)
#else
- #define BSP_PRV_LOCO_USED (0)
+ #define BSP_PRV_LOCO_USED (0)
#endif
/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock
* frequency. */
#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \
!BSP_PRV_PLL_USED && !BSP_PRV_PLL2_USED
- #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED)
+ #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED)
#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ
- #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
+ #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
#else
- #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED)
+ #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED)
#endif
#if BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB
- #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0 == BSP_CFG_ROM_REG_OFS1_ICSATS)
+ #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0 == BSP_CFG_ROM_REG_OFS1_ICSATS)
#else
- #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0)
+ #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0)
+#endif
+
+#if (BSP_FEATURE_BSP_HAS_CANFD_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \
+ (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)) || \
+ (BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_SCI_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \
+ (BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED))
+
+ #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U)
+#else
+ #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (0U)
#endif
/***********************************************************************************************************************
@@ -365,16 +529,40 @@
static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz);
static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state);
+#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #if defined(__ICCARM__)
+
+void R_BSP_SubClockStabilizeWait(uint32_t delay_ms);
+
+ #pragma weak R_BSP_SubClockStabilizeWait
+
+ #elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+
+void R_BSP_SubClockStabilizeWait(uint32_t delay_ms) __attribute__((weak));
+
+ #endif
+#endif
+
+#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U)
+static void bsp_peripheral_clock_set(volatile uint8_t * p_clk_ctrl_reg,
+ volatile uint8_t * p_clk_div_reg,
+ uint8_t peripheral_clk_div,
+ uint8_t peripheral_clk_source);
+
+#endif
+
#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode);
#endif
-#if !BSP_CFG_SOFT_RESET_SUPPORTED
+#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
static void bsp_prv_clock_set_hard_reset(void);
#endif
+void prv_clock_dividers_set(uint32_t sckdivcr, uint8_t sckdivcr2);
+
/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C
* runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime
* environment is initialized. */
@@ -528,6 +716,7 @@ void bsp_prv_operating_mode_set (uint8_t operating_mode)
}
#endif
+ #if BSP_FEATURE_CGC_HAS_SOPCCR
if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode)
{
/* Wait for transition to complete. */
@@ -540,7 +729,10 @@ void bsp_prv_operating_mode_set (uint8_t operating_mode)
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
}
else
+ #endif
{
+ #if BSP_FEATURE_CGC_HAS_SOPCCR
+
/* Wait for transition to complete. */
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
@@ -551,6 +743,7 @@ void bsp_prv_operating_mode_set (uint8_t operating_mode)
* Checking the entire register is slightly more efficient. This will also hang the program if the LPM
* registers are not unlocked, which can help catch programming errors. */
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U);
+ #endif
bsp_prv_operating_mode_opccr_set(operating_mode);
}
@@ -589,7 +782,27 @@ void bsp_prv_prepare_pll (uint32_t pll_freq_hz)
void SystemCoreClockUpdate (void)
{
uint32_t clock_index = R_SYSTEM->SCKSCR;
+#if !BSP_FEATURE_CGC_HAS_CPUCLK
SystemCoreClock = g_clock_freq[clock_index] >> R_SYSTEM->SCKDIVCR_b.ICK;
+#else
+ uint8_t cpuclk_div = R_SYSTEM->SCKDIVCR2_b.CPUCK;
+ if (8U == cpuclk_div)
+ {
+ SystemCoreClock = g_clock_freq[clock_index] / 3U;
+ }
+ else if (9U == cpuclk_div)
+ {
+ SystemCoreClock = g_clock_freq[clock_index] / 6U;
+ }
+ else if (10U == cpuclk_div)
+ {
+ SystemCoreClock = g_clock_freq[clock_index] / 12U;
+ }
+ else
+ {
+ SystemCoreClock = g_clock_freq[clock_index] >> cpuclk_div;
+ }
+#endif
}
#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
@@ -667,14 +880,50 @@ void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask)
#endif
+/*******************************************************************************************************************//**
+ * Write SCKDIVCR and SCKDIVCR2 in the correct order to ensure that CPUCLK frequency is greater than ICLK frequency.
+ *
+ * @param[in] sckdivcr The new SCKDIVCR setting.
+ * @param[in] sckdivcr2 The new SCKDIVCR2 setting.
+ **********************************************************************************************************************/
+void prv_clock_dividers_set (uint32_t sckdivcr, uint8_t sckdivcr2)
+{
+#if BSP_FEATURE_CGC_HAS_CPUCLK
+ uint32_t requested_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(
+ (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK);
+ uint32_t current_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(R_SYSTEM->SCKDIVCR_b.ICK);
+
+ if (requested_iclk_div >= current_iclk_div)
+ {
+ /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to
+ * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR = sckdivcr;
+ R_SYSTEM->SCKDIVCR2 = sckdivcr2;
+ }
+ else
+ {
+ /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first
+ * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR2 = sckdivcr2;
+ R_SYSTEM->SCKDIVCR = sckdivcr;
+ }
+
+#else
+ FSP_PARAMETER_NOT_USED(sckdivcr2);
+
+ R_SYSTEM->SCKDIVCR = sckdivcr;
+#endif
+}
+
/*******************************************************************************************************************//**
* Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this
* configuration and the CGC registers are expected to be unlocked in PRCR.
*
* @param[in] clock Desired system clock
* @param[in] sckdivcr Value to set in SCKDIVCR register
+ * @param[in] sckdivcr2 Value to set in SCKDIVCR2 register
**********************************************************************************************************************/
-void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr)
+void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2)
{
#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
@@ -683,36 +932,29 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr)
uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set();
#endif
- uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
+ uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
/* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be
* set is higher than before. */
- uint32_t clock_freq_hz_post_change = g_clock_freq[clock] >> iclk_div;
+ uint32_t clock_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(iclk_div);
uint8_t new_rom_wait_state = bsp_clock_set_prechange(clock_freq_hz_post_change);
- /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
- * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
-
- /* If the current ICLK divider is less (higher frequency) than the requested ICLK divider, set the divider
- * first. */
- sckdivcr = sckdivcr & BSP_PRV_SCKDIVCR_MASK;
- if (R_SYSTEM->SCKDIVCR_b.ICK < iclk_div)
+ /* Switching to a faster source clock. */
+ if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR])
{
- /* Set the system dividers */
- R_SYSTEM->SCKDIVCR = sckdivcr;
+ /* Set the clock dividers before switching to the new clock source. */
+ prv_clock_dividers_set(sckdivcr, sckdivcr2);
- /* Set the system source clock */
+ /* Switch to the new clock source. */
R_SYSTEM->SCKSCR = (uint8_t) clock;
}
- /* If the current ICLK divider is greater (lower frequency) than the requested ICLK divider, set the clock
- * source first. If the ICLK divider is the same, order does not matter. */
+ /* Switching to a slower source clock. */
else
{
- /* Set the system source clock */
R_SYSTEM->SCKSCR = (uint8_t) clock;
- /* Set the system dividers */
- R_SYSTEM->SCKDIVCR = sckdivcr;
+ /* Set the clock dividers after switching to the new clock source. */
+ prv_clock_dividers_set(sckdivcr, sckdivcr2);
}
/* Clock is now at requested frequency. */
@@ -746,7 +988,7 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr)
#endif
}
-#if !BSP_CFG_SOFT_RESET_SUPPORTED
+#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
static void bsp_prv_clock_set_hard_reset (void)
{
@@ -763,8 +1005,14 @@ static void bsp_prv_clock_set_hard_reset (void)
#elif 0 == BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS || \
(BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS)
R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES;
- #else
+ #elif 0 == BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS || \
+ (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS)
R_FCACHE->FLWT = BSP_PRV_ROM_THREE_WAIT_CYCLES;
+ #elif 0 == BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS || \
+ (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS)
+ R_FCACHE->FLWT = BSP_PRV_ROM_FOUR_WAIT_CYCLES;
+ #else
+ R_FCACHE->FLWT = BSP_PRV_ROM_FIVE_WAIT_CYCLES;
#endif
#endif
@@ -787,26 +1035,58 @@ static void bsp_prv_clock_set_hard_reset (void)
/* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
* dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
- /* ICLK divider at reset is lowest possible, so set dividers first. */
+ /* MOCO is the source clock after reset. If the new source clock is faster than the current source clock,
+ * then set the clock dividers before switching to the new source clock. */
+ #if BSP_MOCO_FREQ_HZ <= BSP_STARTUP_SOURCE_CLOCK_HZ
+ #if BSP_FEATURE_CGC_HAS_CPUCLK
+ #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET)
- /* Set the system dividers first if ICLK divisor is larger than reset value. */
- #if BSP_CFG_ICLK_DIV >= BSP_FEATURE_CGC_ICLK_DIV_RESET
+ /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to
+ * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2;
+ #else
+
+ /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first
+ * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2;
+ R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
+ #else
R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
#endif
/* Set the system source clock */
R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE;
- /* Set the system dividers after setting the system clock source if ICLK divisor is smaller than reset value. */
- #if BSP_CFG_ICLK_DIV < BSP_FEATURE_CGC_ICLK_DIV_RESET
- R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
- #endif
+ /* MOCO is the source clock after reset. If the new source clock is slower than the current source clock,
+ * then set the clock dividers after switching to the new source clock. */
+ #if BSP_MOCO_FREQ_HZ > BSP_STARTUP_SOURCE_CLOCK_HZ
+ #if BSP_FEATURE_CGC_HAS_CPUCLK
+ #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET)
- /* Clock is now at requested frequency. */
+ /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to
+ * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2;
+ #else
+
+ /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first
+ * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */
+ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2;
+ R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
+ #else
+ R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
+ #endif
/* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
SystemCoreClockUpdate();
+ /* Clocks are now at requested frequencies. */
+
/* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be
* set is lower than previous. */
#if BSP_FEATURE_CGC_HAS_SRAMWTSC
@@ -817,7 +1097,12 @@ static void bsp_prv_clock_set_hard_reset (void)
R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
#else
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+
+ /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */
+ __DMB();
R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
+ __DMB();
+
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
#endif
#endif
@@ -852,9 +1137,15 @@ static void bsp_clock_freq_var_init (void)
#endif
#if BSP_PRV_PLL_SUPPORTED
#if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
+ #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE)
/* The PLL Is the startup clock. */
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ;
+ #else
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ;
+ #endif
#else
/* The PLL value will be calculated at initialization. */
@@ -873,6 +1164,12 @@ static void bsp_clock_freq_var_init (void)
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) /
(BSP_CFG_PLL_DIV + 1U);
+ #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ;
+ #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U;
#else
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >>
BSP_CFG_PLL_DIV;
@@ -884,6 +1181,10 @@ static void bsp_clock_freq_var_init (void)
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) /
(BSP_CFG_PLL2_DIV + 1U);
+ #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = BSP_CFG_PLL2P_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = BSP_CFG_PLL2Q_FREQUENCY_HZ;
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = BSP_CFG_PLL2R_FREQUENCY_HZ;
#else
g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] =
((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV;
@@ -924,7 +1225,7 @@ void bsp_clock_init (void)
bsp_clock_freq_var_init();
#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
/* Update the main oscillator drive, source, and wait states if the main oscillator is stopped. If the main
* oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */
@@ -953,20 +1254,27 @@ void bsp_clock_init (void)
#if BSP_FEATURE_CGC_HAS_SOSC
#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
- /* If the board has a subclock, set the subclock drive and start the subclock if the subclock is stopped. If the
- * subclock is running, the subclock drive is assumed to be set appropriately. */
- if (R_SYSTEM->SOSCCR)
+ /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */
+ if (0U == R_SYSTEM->SOSCCR)
{
- /* Configure the subclock drive if the subclock is not already running. */
- R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK);
- R_SYSTEM->SOSCCR = 0U;
- #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)
+ /* Stop the Sub-Clock Oscillator to update the SOMCR register. */
+ R_SYSTEM->SOSCCR = 1U;
- /* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */
- R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS);
- #endif
+ /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity
+ * and restarting Sub-Clock Oscillator. */
+ R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS);
}
+ /* Configure the subclock drive as subclock is not running. */
+ R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK);
+
+ /* Restart the Sub-Clock Oscillator. */
+ R_SYSTEM->SOSCCR = 0U;
+ #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)
+
+ /* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */
+ R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS);
+ #endif
#else
R_SYSTEM->SOSCCR = 1U;
#endif
@@ -986,18 +1294,18 @@ void bsp_clock_init (void)
/* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating
* power control mode. */
#endif
- R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
+ R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE;
#endif
#else
/* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode. There is no restriction to
* writing this register. */
- R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
+ R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE;
#endif
#endif
#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
/* Switch to high-speed to prevent any issues with the subsequent clock configurations. */
bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
@@ -1044,7 +1352,7 @@ void bsp_clock_init (void)
#endif
#endif
#if BSP_PRV_MOCO_USED
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
/* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */
if (0U != R_SYSTEM->MOCOCR)
@@ -1057,7 +1365,7 @@ void bsp_clock_init (void)
#endif
#endif
#if BSP_PRV_LOCO_USED
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
/* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */
if (0U != R_SYSTEM->LOCOCR)
@@ -1090,6 +1398,9 @@ void bsp_clock_init (void)
#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED
#if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR;
+ #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2;
+ #endif
/* Start PLL2. */
R_SYSTEM->PLL2CR = 0U;
@@ -1097,16 +1408,18 @@ void bsp_clock_init (void)
#endif
#if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED
- #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
/* Configure the PLL registers. */
- #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR;
- #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE
+ #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE
R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR;
- #endif
+ #elif 3U == BSP_FEATURE_CGC_PLLCCR_TYPE
+ R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR;
+ R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2;
+ #endif
- #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0
+ #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0
/* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some
* MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100).
@@ -1114,9 +1427,9 @@ void bsp_clock_init (void)
* PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running
* while setting PLLCCR. */
bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US));
- #endif
#endif
+ /* Start the PLL. */
R_SYSTEM->PLLCR = 0U;
#if BSP_PRV_STABILIZE_PLL
@@ -1127,8 +1440,18 @@ void bsp_clock_init (void)
#endif
/* Set source clock and dividers. */
-#if BSP_CFG_SOFT_RESET_SUPPORTED
- bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR);
+#if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
+ #if BSP_TZ_SECURE_BUILD
+
+ /* In case of soft reset, make sure callback pointer is NULL initially. */
+ g_bsp_clock_update_callback = NULL;
+ #endif
+
+ #if BSP_FEATURE_CGC_HAS_CPUCLK
+ bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, BSP_PRV_STARTUP_SCKDIVCR2);
+ #else
+ bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, 0);
+ #endif
#else
bsp_prv_clock_set_hard_reset();
#endif
@@ -1137,7 +1460,7 @@ void bsp_clock_init (void)
#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED
#if BSP_PRV_PLL_SUPPORTED
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
if (BSP_PRV_OPERATING_MODE_LOW_SPEED == BSP_PRV_STARTUP_OPERATING_MODE)
{
/* If the MCU has a PLL, ensure PLL is stopped and stable before entering low speed mode. */
@@ -1174,7 +1497,7 @@ void bsp_clock_init (void)
R_SYSTEM->BCKCR = BSP_CFG_BCLK_OUTPUT - 1U;
R_SYSTEM->EBCKOCR = 1U;
#else
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
R_SYSTEM->EBCKOCR = 0U;
#endif
#endif
@@ -1187,7 +1510,7 @@ void bsp_clock_init (void)
/* Configure CLKOUT. */
#if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED
- #if BSP_CFG_SOFT_RESET_SUPPORTED
+ #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
R_SYSTEM->CKOCR = 0U;
#endif
#else
@@ -1263,85 +1586,70 @@ void bsp_clock_init (void)
#if BSP_FEATURE_BSP_HAS_CANFD_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \
(BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
- /* Request to stop the CANFD clock. */
- R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 1;
-
- /* Wait for the CANFD clock to stop. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 1U);
-
- /* Select the CANFD clock divisor and source. */
- R_SYSTEM->CANFDCKDIVCR = BSP_CFG_CANFDCLK_DIV;
- R_SYSTEM->CANFDCKCR = BSP_CFG_CANFDCLK_SOURCE | R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk |
- R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk;
-
- /* Request to start the CANFD clock. */
- R_SYSTEM->CANFDCKCR_b.CANFDCKSREQ = 0;
-
- /* Wait for the CANFD clock to start. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 0U);
+ bsp_peripheral_clock_set(&R_SYSTEM->CANFDCKCR,
+ &R_SYSTEM->CANFDCKDIVCR,
+ BSP_CFG_CANFDCLK_DIV,
+ BSP_CFG_CANFDCLK_SOURCE);
#endif
/* Set the SCISPI clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->SCISPICKCR,
+ &R_SYSTEM->SCISPICKDIVCR,
+ BSP_CFG_SCISPICLK_DIV,
+ BSP_CFG_SCISPICLK_SOURCE);
+#endif
- /* Request to stop the SCISPI clock. */
- R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 1;
+ /* Set the SCI clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_SCI_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->SCICKCR, &R_SYSTEM->SCICKDIVCR, BSP_CFG_SCICLK_DIV, BSP_CFG_SCICLK_SOURCE);
+#endif
- /* Wait for the SCISPI clock to stop. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 1U);
-
- /* Select the SCISPI clock divisor and source. */
- R_SYSTEM->SCISPICKDIVCR = BSP_CFG_SCISPICLK_DIV;
- R_SYSTEM->SCISPICKCR = BSP_CFG_SCISPICLK_SOURCE | R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk |
- R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk;
-
- /* Request to start the SCISPI clock. */
- R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 0;
-
- /* Wait for the SCISPI clock to start. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 0U);
+ /* Set the SPI clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->SPICKCR, &R_SYSTEM->SPICKDIVCR, BSP_CFG_SPICLK_DIV, BSP_CFG_SPICLK_SOURCE);
#endif
/* Set the GPT clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
-
- /* Request to stop the GPT clock. */
- R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 1;
-
- /* Wait for the GPT clock to stop. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 1U);
-
- /* Select the GPT clock divisor and source. */
- R_SYSTEM->GPTCKDIVCR = BSP_CFG_GPTCLK_DIV;
- R_SYSTEM->GPTCKCR = BSP_CFG_GPTCLK_SOURCE | R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk |
- R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk;
-
- /* Request to start the GPT clock. */
- R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 0;
-
- /* Wait for the GPT clock to start. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 0U);
+ bsp_peripheral_clock_set(&R_SYSTEM->GPTCKCR, &R_SYSTEM->GPTCKDIVCR, BSP_CFG_GPTCLK_DIV, BSP_CFG_GPTCLK_SOURCE);
#endif
/* Set the IIC clock if it exists on the MCU */
#if BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE);
+#endif
- /* Request to stop the IIC clock. */
- R_SYSTEM->IICCKCR_b.IICCKSREQ = 1;
+ /* Set the CEC clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE);
+#endif
- /* Wait for the IIC clock to stop. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 1U);
+ /* Set the I3C clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE);
+#endif
- /* Select the IIC clock divisor and source. */
- R_SYSTEM->IICCKDIVCR = BSP_CFG_IICCLK_DIV;
- R_SYSTEM->IICCKCR = BSP_CFG_IICCLK_SOURCE | R_SYSTEM_IICCKCR_IICCKSREQ_Msk |
- R_SYSTEM_IICCKCR_IICCKSRDY_Msk;
+ /* Set the ADC clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->ADCCKCR, &R_SYSTEM->ADCCKDIVCR, BSP_CFG_ADCCLK_DIV, BSP_CFG_ADCCLK_SOURCE);
+#endif
- /* Request to start the IIC clock. */
- R_SYSTEM->IICCKCR_b.IICCKSREQ = 0;
+ /* Set the LCD clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->LCDCKCR, &R_SYSTEM->LCDCKDIVCR, BSP_CFG_LCDCLK_DIV, BSP_CFG_LCDCLK_SOURCE);
+#endif
- /* Wait for the IIC clock to start. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 0U);
+ /* Set the USB-HS clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+ bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, &R_SYSTEM->USB60CKDIVCR, BSP_CFG_U60CK_DIV, BSP_CFG_U60CK_SOURCE);
+#endif
+
+ /* Set the SDADC clock if it exists on the MCU. */
+#if BSP_FEATURE_BSP_HAS_SDADC_CLOCK && (BSP_CFG_SDADC_CLOCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+
+ /* SDADC isn't controlled like the other peripheral clocks so we cannot use the generic setter. */
+ R_SYSTEM->SDADCCKCR = BSP_CFG_SDADC_CLOCK_SOURCE & R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk;
#endif
/* Lock CGC and LPM protection registers. */
@@ -1356,6 +1664,66 @@ void bsp_clock_init (void)
#endif
}
+#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+
+/*******************************************************************************************************************//**
+ * This function is called during SOSC stabilization when Sub-Clock oscillator is populated.
+ * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
+ * implemented version. One of the main uses for this function is to update the IWDT/WDT Refresh Register if an
+ * application starts IWDT/WDT automatically after reset. To use this function just copy this function into your own
+ * code and modify it to meet your needs.
+ *
+ * @param[in] delay_ms Stabilization Time for the clock.
+ **********************************************************************************************************************/
+void R_BSP_SubClockStabilizeWait (uint32_t delay_ms)
+{
+ /* Wait for clock to stabilize. */
+ R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS);
+}
+
+#endif
+
+#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U)
+
+/*******************************************************************************************************************//**
+ * Set the peripheral clock on the MCU
+ *
+ * @param[in] p_clk_ctrl_reg Pointer to peripheral clock control register
+ * @param[in] p_clk_div_reg Pointer to peripheral clock division control register
+ * @param[in] peripheral_clk_div Peripheral clock division
+ * @param[in] peripheral_clk_source Peripheral clock source
+ *
+ * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist).
+ **********************************************************************************************************************/
+static void bsp_peripheral_clock_set (volatile uint8_t * p_clk_ctrl_reg,
+ volatile uint8_t * p_clk_div_reg,
+ uint8_t peripheral_clk_div,
+ uint8_t peripheral_clk_source)
+{
+ /* Request to stop the peripheral clock. */
+ *p_clk_ctrl_reg |= (uint8_t) BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK;
+
+ /* Wait for the peripheral clock to stop. */
+ FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >>
+ BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS),
+ 1U);
+
+ /* Select the peripheral clock divisor and source. */
+ *p_clk_div_reg = peripheral_clk_div;
+ *p_clk_ctrl_reg = peripheral_clk_source | BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK |
+ BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK;
+
+ /* Request to start the peripheral clock. */
+ *p_clk_ctrl_reg &= (uint8_t) ~BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK;
+
+ /* Wait for the peripheral clock to start. */
+ FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >>
+ BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS),
+ 0U);
+}
+
+#endif
+
/*******************************************************************************************************************//**
* Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change.
*
@@ -1374,13 +1742,18 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz)
/* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */
if (requested_freq_hz > BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS)
{
- #ifdef BSP_FEATURE_CGC_HAS_SRAMPRCR2
+ #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1
R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK;
R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE;
R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
#else
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+
+ /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */
+ __DMB();
R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE;
+ __DMB();
+
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
#endif
}
@@ -1413,7 +1786,7 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz)
new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
}
- #else
+ #elif BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS == 0
if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
{
new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
@@ -1430,6 +1803,54 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz)
{
new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES;
}
+
+ #elif BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS == 0
+ if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES;
+ }
+ else
+ {
+ new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES;
+ }
+
+ #else
+ if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES;
+ }
+ else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS)
+ {
+ new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES;
+ }
+ else
+ {
+ new_rom_wait_state = BSP_PRV_ROM_FIVE_WAIT_CYCLES;
+ }
#endif
/* If more wait states are required after the change, then set the wait states before changing the clock. */
@@ -1483,7 +1904,12 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_
R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK;
#else
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+
+ /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */
+ __DMB();
R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE;
+ __DMB();
+
R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
#endif
}
@@ -1563,4 +1989,65 @@ uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
return source_clock;
}
+#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+/*******************************************************************************************************************//**
+ * RTC Initialization
+ *
+ * Some RTC registers must be initialized after reset to ensure correct operation.
+ * This reset is not performed automatically if the RTC is used in a project as it will
+ * be handled by the RTC driver if needed.
+ **********************************************************************************************************************/
+void R_BSP_Init_RTC (void)
+{
+ /* RA4M3 UM r01uh0893ej0120: Figure 23.14 Initialization procedure */
+
+ /* RCKSEL bit is not initialized after reset. Use LOCO as the default
+ * clock source if it is available. Note RCR4.ROPSEL is also cleared.
+ */
+ #if BSP_PRV_LOCO_USED
+ R_RTC->RCR4 = 1 << R_RTC_RCR4_RCKSEL_Pos;
+ #else
+
+ /* Sses SOSC as clock source, or there is no clock source. */
+ R_RTC->RCR4 = 0;
+ #endif
+
+ #if !BSP_CFG_RTC_USED
+ #if BSP_PRV_LOCO_USED || (BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED)
+
+ /*Wait for 6 clocks: 200 > (6*1000000) / 32K */
+ R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+
+ R_RTC->RCR2 = 0;
+ FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2, 0);
+
+ R_RTC->RCR2_b.RESET = 1;
+ FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.RESET, 0);
+
+ /* Disable RTC interrupts */
+ R_RTC->RCR1 = 0;
+
+ #if BSP_FEATURE_RTC_HAS_TCEN
+ for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++)
+ {
+ /* RTCCRn.TCEN must be cleared after reset. */
+ R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U;
+ FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0);
+ }
+ #endif
+ #endif
+ #endif
+
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+ /* VBTICTLR.VCHnINEN must be cleared after reset. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+ R_SYSTEM->VBTICTLR = 0U;
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+ #endif
+}
+
+#endif
+
/** @} (end addtogroup BSP_MCU_PRV) */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
index 68e4a77570..b4d4868be1 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -36,13 +36,24 @@ FSP_HEADER
/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */
/* Must match SCKCR.CKSEL values. */
-#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator.
-#define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator.
+#if 0 == BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS && 0 == BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator.
+#elif (0 != BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS && 0 != BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS)
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. Treated as PLL1P.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. Treated as PLL2P.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator.
+ #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator.
+#endif
/* PLLs are not supported in the following scenarios:
* - When using low voltage mode
@@ -50,7 +61,10 @@ FSP_HEADER
* - When the PLL only accepts the main oscillator as a source and XTAL is not used
*/
#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
- !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
+ !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
+ (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
+ (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \
+ !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
#define BSP_PRV_PLL_SUPPORTED (1)
#if BSP_FEATURE_CGC_HAS_PLL2
#define BSP_PRV_PLL2_SUPPORTED (1)
@@ -66,161 +80,239 @@ FSP_HEADER
* calculated here is also used to initialize the g_clock_freq array. */
#if BSP_PRV_PLL_SUPPORTED
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE)
- #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
+ #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#else
- #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
+ #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#endif
#endif
#if BSP_PRV_PLL2_SUPPORTED
#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE
- #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
+ #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#else
- #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
+ #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#endif
#endif
/* Frequencies of clocks with fixed freqencies. */
-#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz
-#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz
-#define BSP_MOCO_FREQ_HZ (8000000U) // MOCO frequency is fixed at 8 MHz
+#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz
+#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz
+#define BSP_MOCO_FREQ_HZ (8000000U) // MOCO frequency is fixed at 8 MHz
#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
#if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
- #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
+ #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
- #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
+ #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#endif
- #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \
- (BSP_CFG_PLL_DIV + 1U))
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \
+ (BSP_CFG_PLL_DIV + 1U))
#elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
- #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
- #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \
- (BSP_CFG_PLL_DIV))
+ #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \
+ (BSP_CFG_PLL_DIV))
+ #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ)
#endif
#endif
+/* Convert divisor bitfield settings into divisor values to calculate startup clocks */
+#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div)))
+#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
+#define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV)
+#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
+#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV)
+#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV)
+#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
+#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)
+#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV)
+#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV)
+
/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
* not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
-#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV)
-#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
-#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
-#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV)
-#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
-#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV)
-#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV)
+#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE)
+#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE)
+#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE)
+#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE)
+#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE)
+#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE)
+#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE)
+#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE)
+#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE)
/* System clock divider options. */
-#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64.
-#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only).
+#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only).
+#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12.
/* USB clock divider options. */
-#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3
-#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4
-#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5
+#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1
+#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2
+#define BSP_CLOCKS_USB_CLOCK_DIV_3 (5) // Divide USB source clock by 3
+#define BSP_CLOCKS_USB_CLOCK_DIV_4 (2) // Divide USB source clock by 4
+#define BSP_CLOCKS_USB_CLOCK_DIV_5 (6) // Divide USB source clock by 5
+#define BSP_CLOCKS_USB_CLOCK_DIV_6 (3) // Divide USB source clock by 6
+#define BSP_CLOCKS_USB_CLOCK_DIV_8 (4) // Divide USB source clock by 8
+
+/* USB60 clock divider options. */
+#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1
+#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2
+#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3
+#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4
+#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5
+#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6
+#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8
+
+/* GLCD clock divider options. */
+#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1
+#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2
+#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3
+#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4
+#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5
+#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6
+#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8
/* OCTA clock divider options. */
-#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1
-#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2
-#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4
-#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6
-#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8
+#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1
+#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2
+#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4
+#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6
+#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8
/* CANFD clock divider options. */
-#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1
-#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2
-#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4
-#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6
-#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8
+
+/* SCI clock divider options. */
+#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1
+#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2
+#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3
+#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4
+#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5
+#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6
+#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8
+
+/* SPI clock divider options. */
+#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1
+#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2
+#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3
+#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4
+#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5
+#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6
+#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8
/* SCISPI clock divider options. */
-#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1
-#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2
-#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4
-#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6
-#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8
/* GPT clock divider options. */
-#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1
-#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2
-#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4
-#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6
-#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8
+#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1
+#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2
+#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3
+#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4
+#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5
+#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6
+#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8
/* IIC clock divider options. */
-#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1
-#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2
-#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4
-#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6
-#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8
+#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1
+#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2
+#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4
+#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6
+#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8
+
+/* CEC clock divider options. */
+#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1
+#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2
+
+/* I3C clock divider options. */
+#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1
+#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2
+#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3
+#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4
+#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5
+#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6
+#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8
+
+/* ADC clock divider options. */
+#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1
+#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2
+#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3
+#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4
+#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5
+#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6
+#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8
/* PLL divider options. */
-#define BSP_CLOCKS_PLL_DIV_1 (0)
-#define BSP_CLOCKS_PLL_DIV_2 (1)
-#define BSP_CLOCKS_PLL_DIV_3 (2)
-#define BSP_CLOCKS_PLL_DIV_4 (2)
+#define BSP_CLOCKS_PLL_DIV_1 (0)
+#define BSP_CLOCKS_PLL_DIV_2 (1)
+#define BSP_CLOCKS_PLL_DIV_3 (2)
+#define BSP_CLOCKS_PLL_DIV_4 (3)
+#define BSP_CLOCKS_PLL_DIV_5 (4)
+#define BSP_CLOCKS_PLL_DIV_6 (5)
+#define BSP_CLOCKS_PLL_DIV_8 (7)
+#define BSP_CLOCKS_PLL_DIV_9 (8)
+#define BSP_CLOCKS_PLL_DIV_16 (15)
/* PLL multiplier options. */
-#define BSP_CLOCKS_PLL_MUL_8_0 (0xF)
-#define BSP_CLOCKS_PLL_MUL_9_0 (0x11)
-#define BSP_CLOCKS_PLL_MUL_10_0 (0x13)
-#define BSP_CLOCKS_PLL_MUL_10_5 (0x14)
-#define BSP_CLOCKS_PLL_MUL_11_0 (0x15)
-#define BSP_CLOCKS_PLL_MUL_11_5 (0x16)
-#define BSP_CLOCKS_PLL_MUL_12_0 (0x17)
-#define BSP_CLOCKS_PLL_MUL_12_5 (0x18)
-#define BSP_CLOCKS_PLL_MUL_13_0 (0x19)
-#define BSP_CLOCKS_PLL_MUL_13_5 (0x1A)
-#define BSP_CLOCKS_PLL_MUL_14_0 (0x1B)
-#define BSP_CLOCKS_PLL_MUL_14_5 (0x1c)
-#define BSP_CLOCKS_PLL_MUL_15_0 (0x1d)
-#define BSP_CLOCKS_PLL_MUL_15_5 (0x1e)
-#define BSP_CLOCKS_PLL_MUL_16_0 (0x1f)
-#define BSP_CLOCKS_PLL_MUL_16_5 (0x20)
-#define BSP_CLOCKS_PLL_MUL_17_0 (0x21)
-#define BSP_CLOCKS_PLL_MUL_17_5 (0x22)
-#define BSP_CLOCKS_PLL_MUL_18_0 (0x23)
-#define BSP_CLOCKS_PLL_MUL_18_5 (0x24)
-#define BSP_CLOCKS_PLL_MUL_19_0 (0x25)
-#define BSP_CLOCKS_PLL_MUL_19_5 (0x26)
-#define BSP_CLOCKS_PLL_MUL_20_0 (0x27)
-#define BSP_CLOCKS_PLL_MUL_20_5 (0x28)
-#define BSP_CLOCKS_PLL_MUL_21_0 (0x29)
-#define BSP_CLOCKS_PLL_MUL_21_5 (0x2A)
-#define BSP_CLOCKS_PLL_MUL_22_0 (0x2B)
-#define BSP_CLOCKS_PLL_MUL_22_5 (0x2c)
-#define BSP_CLOCKS_PLL_MUL_23_0 (0x2d)
-#define BSP_CLOCKS_PLL_MUL_23_5 (0x2e)
-#define BSP_CLOCKS_PLL_MUL_24_0 (0x2f)
-#define BSP_CLOCKS_PLL_MUL_24_5 (0x30)
-#define BSP_CLOCKS_PLL_MUL_25_0 (0x31)
-#define BSP_CLOCKS_PLL_MUL_25_5 (0x32)
-#define BSP_CLOCKS_PLL_MUL_26_0 (0x33)
-#define BSP_CLOCKS_PLL_MUL_26_5 (0x34)
-#define BSP_CLOCKS_PLL_MUL_27_0 (0x35)
-#define BSP_CLOCKS_PLL_MUL_27_5 (0x36)
-#define BSP_CLOCKS_PLL_MUL_28_0 (0x37)
-#define BSP_CLOCKS_PLL_MUL_28_5 (0x38)
-#define BSP_CLOCKS_PLL_MUL_29_0 (0x39)
-#define BSP_CLOCKS_PLL_MUL_29_5 (0x3A)
-#define BSP_CLOCKS_PLL_MUL_30_0 (0x3B)
-#define BSP_CLOCKS_PLL_MUL_31_0 (0x3D)
+#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+
+/* Offset from decimal multiplier to register value for PLLCCR type 4. */
+ #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574)
+
+/**
+ * X=Integer portion of the multiplier.
+ * Y=Fractional portion of the multiplier. (not used for this PLLCCR type)
+ */
+ #define BSP_CLOCKS_PLL_MUL(X, Y) ((X) -BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET)
+
+#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE)
+
+/**
+ * X=Integer portion of the multiplier.
+ * Y=Fractional portion of the multiplier.
+ */
+ #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U)
+
+#else
+
+ #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U)
+ #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U)
+ #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U)
+
+/**
+ * X=Integer portion of the multiplier.
+ * Y=Fractional portion of the multiplier.
+ */
+ #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U)))
+
+#endif
/* Configuration option used to disable clock output. */
#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU)
@@ -236,41 +328,46 @@ FSP_HEADER
#endif
/* Create a mask of valid bits in SCKDIVCR. */
-#define BSP_PRV_SCKDIVCR_ICLK_MASK (7U << 24)
+#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
#if BSP_FEATURE_CGC_HAS_PCLKD
- #define BSP_PRV_SCKDIVCR_PCLKD_MASK (7U << 0)
+ #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0)
#else
#define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKC
- #define BSP_PRV_SCKDIVCR_PCLKC_MASK (7U << 4)
+ #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4)
#else
#define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKB
- #define BSP_PRV_SCKDIVCR_PCLKB_MASK (7U << 8)
+ #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8)
#else
#define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKA
- #define BSP_PRV_SCKDIVCR_PCLKA_MASK (7U << 12)
+ #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12)
#else
#define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
- #define BSP_PRV_SCKDIVCR_BCLK_MASK (7U << 16)
+ #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16)
#else
#define BSP_PRV_SCKDIVCR_BCLK_MASK (0U)
#endif
+#if BSP_FEATURE_CGC_HAS_PCLKE
+ #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
+#else
+ #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U)
+#endif
#if BSP_FEATURE_CGC_HAS_FCLK
- #define BSP_PRV_SCKDIVCR_FCLK_MASK (7U << 28)
+ #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28)
#else
#define BSP_PRV_SCKDIVCR_FCLK_MASK (0U)
#endif
-#define BSP_PRV_SCKDIVCR_MASK ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) | \
- BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \
- BSP_PRV_SCKDIVCR_PCLKA_MASK) | \
- BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK)
+#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \
+ BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \
+ BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \
+ BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK)
/* FLL is only used when enabled, present and the subclock is populated. */
#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED
@@ -283,6 +380,10 @@ FSP_HEADER
#define BSP_PRV_FLL_STABILIZATION_TIME_US (0)
#endif
+#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+ #define BSP_PRV_RTC_RESET_DELAY_US (200)
+#endif
+
/* Operating power control modes. */
#define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed
#define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed
@@ -310,6 +411,667 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp
#endif
+/** PLL multiplier values */
+typedef enum e_cgc_pll_mul
+{
+ CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.0
+ CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.0
+ CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00
+ CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50
+ CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00
+ CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50
+ CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00
+ CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50
+ CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00
+ CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50
+ CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00
+ CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50
+ CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00
+ CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50
+ CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00
+ CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50
+ CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00
+ CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50
+ CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00
+ CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50
+ CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00
+ CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50
+ CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00
+ CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50
+ CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00
+ CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50
+ CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00
+ CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50
+ CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00
+ CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50
+ CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00
+ CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50
+ CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00
+ CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50
+ CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00
+ CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33
+ CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50
+ CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66
+ CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00
+ CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33
+ CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50
+ CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66
+ CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00
+ CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33
+ CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50
+ CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66
+ CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00
+ CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33
+ CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50
+ CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66
+ CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00
+ CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33
+ CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50
+ CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66
+ CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00
+ CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33
+ CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50
+ CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66
+ CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00
+ CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33
+ CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50
+ CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66
+ CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00
+ CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33
+ CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50
+ CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66
+ CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00
+ CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33
+ CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50
+ CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66
+ CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00
+ CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33
+ CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50
+ CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66
+ CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00
+ CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33
+ CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50
+ CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66
+ CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00
+ CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33
+ CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50
+ CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66
+ CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00
+ CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33
+ CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50
+ CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66
+ CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00
+ CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33
+ CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50
+ CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66
+ CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00
+ CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33
+ CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50
+ CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66
+ CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00
+ CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33
+ CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50
+ CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66
+ CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00
+ CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33
+ CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50
+ CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66
+ CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00
+ CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33
+ CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50
+ CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66
+ CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00
+ CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33
+ CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50
+ CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66
+ CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00
+ CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33
+ CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50
+ CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66
+ CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00
+ CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33
+ CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50
+ CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66
+ CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00
+ CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33
+ CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50
+ CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66
+ CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00
+ CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33
+ CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50
+ CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66
+ CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00
+ CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33
+ CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50
+ CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66
+ CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00
+ CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33
+ CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50
+ CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66
+ CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00
+ CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33
+ CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50
+ CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66
+ CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00
+ CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33
+ CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50
+ CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66
+ CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00
+ CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33
+ CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50
+ CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66
+ CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00
+ CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33
+ CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50
+ CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66
+ CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00
+ CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33
+ CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50
+ CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66
+ CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00
+ CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33
+ CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50
+ CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66
+ CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00
+ CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33
+ CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50
+ CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66
+ CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00
+ CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33
+ CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50
+ CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66
+ CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00
+ CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33
+ CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50
+ CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66
+ CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00
+ CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33
+ CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50
+ CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66
+ CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00
+ CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33
+ CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50
+ CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66
+ CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00
+ CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33
+ CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50
+ CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66
+ CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00
+ CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33
+ CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50
+ CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66
+ CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00
+ CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33
+ CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50
+ CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66
+ CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00
+ CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33
+ CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50
+ CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66
+ CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00
+ CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33
+ CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50
+ CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66
+ CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00
+ CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33
+ CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50
+ CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66
+ CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00
+ CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33
+ CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50
+ CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66
+ CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00
+ CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33
+ CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50
+ CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66
+ CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00
+ CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33
+ CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50
+ CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66
+ CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00
+ CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33
+ CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50
+ CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66
+ CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00
+ CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33
+ CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50
+ CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66
+ CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00
+ CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33
+ CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50
+ CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66
+ CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00
+ CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33
+ CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50
+ CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66
+ CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00
+ CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33
+ CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50
+ CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66
+ CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00
+ CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33
+ CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50
+ CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66
+ CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00
+ CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33
+ CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50
+ CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66
+ CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00
+ CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33
+ CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50
+ CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66
+ CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00
+ CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33
+ CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50
+ CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66
+ CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00
+ CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33
+ CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50
+ CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66
+ CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00
+ CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33
+ CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50
+ CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66
+ CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00
+ CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33
+ CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50
+ CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66
+ CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00
+ CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33
+ CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50
+ CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66
+ CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00
+ CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33
+ CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50
+ CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66
+ CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00
+ CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33
+ CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50
+ CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66
+ CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00
+ CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33
+ CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50
+ CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66
+ CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00
+ CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33
+ CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50
+ CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66
+ CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00
+ CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33
+ CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50
+ CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66
+ CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00
+ CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33
+ CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50
+ CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66
+ CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00
+ CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33
+ CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50
+ CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66
+ CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00
+ CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33
+ CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50
+ CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66
+ CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00
+ CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33
+ CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50
+ CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66
+ CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00
+ CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33
+ CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50
+ CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66
+ CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00
+ CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33
+ CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50
+ CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66
+ CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00
+ CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33
+ CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50
+ CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66
+ CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00
+ CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33
+ CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50
+ CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66
+ CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00
+ CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33
+ CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50
+ CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66
+ CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00
+ CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33
+ CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50
+ CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66
+ CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00
+ CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33
+ CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50
+ CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66
+ CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00
+ CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33
+ CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50
+ CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66
+ CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00
+ CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33
+ CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50
+ CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66
+ CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00
+ CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33
+ CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50
+ CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66
+ CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00
+ CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33
+ CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50
+ CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66
+ CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00
+ CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33
+ CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50
+ CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66
+ CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00
+ CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33
+ CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50
+ CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66
+ CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00
+ CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33
+ CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50
+ CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66
+ CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00
+ CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33
+ CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50
+ CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66
+ CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00
+ CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33
+ CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50
+ CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66
+ CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00
+ CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33
+ CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50
+ CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66
+ CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00
+ CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33
+ CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50
+ CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66
+ CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00
+ CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33
+ CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50
+ CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66
+ CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00
+ CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33
+ CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50
+ CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66
+ CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00
+ CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33
+ CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50
+ CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66
+ CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00
+ CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33
+ CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50
+ CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66
+ CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00
+ CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33
+ CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50
+ CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66
+ CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00
+ CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33
+ CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50
+ CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66
+ CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00
+ CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33
+ CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50
+ CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66
+ CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00
+ CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33
+ CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50
+ CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66
+ CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00
+ CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33
+ CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50
+ CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66
+ CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00
+ CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33
+ CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50
+ CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66
+ CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00
+ CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33
+ CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50
+ CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66
+ CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00
+ CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33
+ CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50
+ CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66
+ CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00
+ CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33
+ CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50
+ CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66
+ CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00
+ CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33
+ CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50
+ CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66
+ CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00
+ CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33
+ CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50
+ CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66
+ CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00
+ CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33
+ CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50
+ CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66
+ CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00
+ CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33
+ CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50
+ CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66
+ CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00
+ CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33
+ CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50
+ CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66
+ CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00
+ CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33
+ CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50
+ CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66
+ CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00
+ CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33
+ CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50
+ CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66
+ CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00
+ CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33
+ CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50
+ CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66
+ CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00
+ CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33
+ CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50
+ CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66
+ CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00
+ CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33
+ CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50
+ CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66
+ CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00
+ CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33
+ CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50
+ CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66
+ CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00
+ CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33
+ CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50
+ CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66
+ CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00
+ CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33
+ CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50
+ CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66
+ CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00
+ CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33
+ CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50
+ CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66
+ CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00
+ CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33
+ CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50
+ CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66
+ CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00
+ CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33
+ CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50
+ CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66
+ CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00
+ CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33
+ CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50
+ CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66
+ CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00
+ CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33
+ CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50
+ CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66
+ CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00
+ CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33
+ CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50
+ CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66
+ CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00
+ CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33
+ CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50
+ CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66
+ CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00
+ CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33
+ CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50
+ CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66
+ CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00
+ CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33
+ CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50
+ CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66
+ CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00
+ CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33
+ CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50
+ CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66
+ CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00
+ CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33
+ CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50
+ CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66
+ CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00
+ CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33
+ CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50
+ CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66
+ CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00
+ CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33
+ CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50
+ CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66
+ CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00
+ CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33
+ CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50
+ CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66
+ CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00
+ CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33
+ CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50
+ CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66
+ CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00
+ CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33
+ CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50
+ CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66
+ CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00
+ CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33
+ CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50
+ CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66
+ CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00
+ CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33
+ CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50
+ CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66
+ CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00
+ CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33
+ CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50
+ CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66
+ CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00
+ CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33
+ CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50
+ CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66
+ CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00
+ CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33
+ CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50
+ CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66
+ CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00
+ CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33
+ CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50
+ CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66
+ CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00
+ CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33
+ CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50
+ CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66
+ CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00
+ CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33
+ CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50
+ CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66
+ CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00
+ CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33
+ CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50
+ CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66
+ CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00
+ CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33
+ CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50
+ CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66
+ CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00
+ CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33
+ CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50
+ CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66
+ CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00
+ CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33
+ CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50
+ CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66
+ CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00
+ CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33
+ CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50
+ CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66
+ CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00
+ CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33
+ CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50
+ CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66
+ CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00
+ CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33
+ CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50
+ CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66
+ CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00
+ CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33
+ CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50
+ CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66
+ CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00
+ CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33
+ CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50
+ CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66
+ CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00
+ CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33
+ CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50
+ CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66
+ CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00
+ CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33
+ CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50
+ CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66
+ CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00
+ CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33
+ CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50
+ CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66
+ CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00
+ CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33
+ CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50
+ CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66
+ CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00
+ CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33
+ CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50
+ CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66
+ CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00
+ CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33
+ CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50
+ CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66
+ CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00
+ CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33
+ CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50
+ CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66
+ CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00
+ CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33
+ CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50
+ CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66
+ CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00
+ CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33
+ CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50
+ CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66
+ CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00
+ CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33
+ CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50
+ CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66
+ CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00
+ CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33
+ CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50
+ CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66
+ CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00
+ CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00
+} cgc_pll_mul_t;
+
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
@@ -346,7 +1108,13 @@ void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask);
#endif
void bsp_prv_prepare_pll(uint32_t pll_freq_hz);
-void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr);
+void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2);
+
+/* RTC Initialization */
+#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+void R_BSP_Init_RTC(void);
+
+#endif
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.c
index 6613c10fd3..a7121a54ef 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -75,10 +75,13 @@ void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); ///
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
- .minor = FSP_VERSION_MINOR,
- .major = FSP_VERSION_MAJOR,
- .build = FSP_VERSION_BUILD,
- .patch = FSP_VERSION_PATCH
+ .version_id_b =
+ {
+ .minor = FSP_VERSION_MINOR,
+ .major = FSP_VERSION_MAJOR,
+ .build = FSP_VERSION_BUILD,
+ .patch = FSP_VERSION_PATCH
+ }
};
/* Public FSP version name. */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.h
index 8f25cb6560..a800ecbf9d 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -125,6 +125,12 @@ FSP_HEADER
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
+#ifndef FSP_REGISTER_READ
+
+/* Read a register and discard the result. */
+ #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
+#endif
+
/****************************************************************
*
* This check is performed to select suitable ASM API with respect to core
@@ -180,11 +186,15 @@ FSP_HEADER
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
-/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */
-#define FSP_PRIV_SCKDIVCR_DIV_MASK (7)
+/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
+#if (BSP_CFG_MCU_PART_SERIES == 8)
+ #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
+#else
+ #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
+#endif
/* Use the secure registers for secure projects and flat projects. */
-#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
+#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE && !(BSP_CFG_MCU_PART_SERIES == 8)
#define FSP_PRIV_TZ_USE_SECURE_REGS (1)
#else
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
@@ -246,7 +256,6 @@ typedef struct st_bsp_unique_id
* Exported global variables
**********************************************************************************************************************/
uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
-
/***********************************************************************************************************************
* Global variables (defined in other files)
**********************************************************************************************************************/
@@ -276,10 +285,68 @@ __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
uint32_t sckdivcr = R_SYSTEM->SCKDIVCR;
- uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
- uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK;
+ uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
+
+#if BSP_FEATURE_CGC_HAS_CPUCLK
+
+ /* Get CPUCLK divisor */
+ uint32_t cpuclk_div = R_SYSTEM->SCKDIVCR2 & FSP_PRV_SCKDIVCR_DIV_MASK;
+
+ /* Determine if either divisor is a multiple of 3 */
+ if ((cpuclk_div | clock_div) & 8U)
+ {
+ /* Convert divisor settings to their actual values */
+ cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
+ clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
+
+ /* Calculate clock with multiplication and division instead of shifting */
+ return (SystemCoreClock * cpuclk_div) / clock_div;
+ }
+ else
+ {
+ return (SystemCoreClock << cpuclk_div) >> clock_div;
+ }
+#else
+ uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
return (SystemCoreClock << iclk_div) >> clock_div;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
+ *
+ * @return Clock Divider
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
+{
+ if (2U >= ckdivcr)
+ {
+ /* clock_div:
+ * - Clock Divided by 1: 0
+ * - Clock Divided by 2: 1
+ * - Clock Divided by 4: 2
+ */
+ return 1 << ckdivcr;
+ }
+ else if (3U == ckdivcr)
+ {
+ /* Clock Divided by 6 */
+ return 6U;
+ }
+ else if (4U == ckdivcr)
+ {
+ /* Clock Divided by 8 */
+ return 8U;
+ }
+ else if (5U == ckdivcr)
+ {
+ /* Clock Divided by 3 */
+ return 3U;
+ }
+
+ /* Clock Divided by 5 */
+ return 5U;
}
#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
@@ -292,10 +359,44 @@ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
{
uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
- uint32_t clock_div = (scispidivcr & FSP_PRIV_SCKDIVCR_DIV_MASK);
+ uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
- return R_BSP_SourceClockHzGet(scispicksel) >> clock_div;
+ return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
+}
+
+#endif
+#if BSP_FEATURE_BSP_HAS_SPI_CLOCK
+
+/*******************************************************************************************************************//**
+ * Gets the frequency of a SPI clock.
+ *
+ * @return Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
+{
+ uint32_t spidivcr = R_SYSTEM->SPICKDIVCR;
+ uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
+ fsp_priv_source_clock_t spicksel = (fsp_priv_source_clock_t) R_SYSTEM->SPICKCR_b.CKSEL;
+
+ return R_BSP_SourceClockHzGet(spicksel) / clock_div;
+}
+
+#endif
+#if BSP_FEATURE_BSP_HAS_SCI_CLOCK
+
+/*******************************************************************************************************************//**
+ * Gets the frequency of a SCI clock.
+ *
+ * @return Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
+{
+ uint32_t scidivcr = R_SYSTEM->SCICKDIVCR;
+ uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
+ fsp_priv_source_clock_t scicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCICKCR_b.SCICKSEL;
+
+ return R_BSP_SourceClockHzGet(scicksel) / clock_div;
}
#endif
@@ -305,7 +406,7 @@ __STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
*
* @return A pointer to the unique identifier structure
**********************************************************************************************************************/
-__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
+__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
{
return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
}
@@ -313,7 +414,7 @@ __STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
/*******************************************************************************************************************//**
* Disables the flash cache.
**********************************************************************************************************************/
-__STATIC_INLINE void R_BSP_FlashCacheDisable ()
+__STATIC_INLINE void R_BSP_FlashCacheDisable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
R_FCACHE->FCACHEE = 0U;
@@ -329,7 +430,7 @@ __STATIC_INLINE void R_BSP_FlashCacheDisable ()
/*******************************************************************************************************************//**
* Enables the flash cache.
**********************************************************************************************************************/
-__STATIC_INLINE void R_BSP_FlashCacheEnable ()
+__STATIC_INLINE void R_BSP_FlashCacheEnable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
index b07ca8ffcb..a5159d0a3b 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -24,72 +24,84 @@
**********************************************************************************************************************/
#ifndef BSP_COMPILER_SUPPORT_H
-#define BSP_COMPILER_SUPPORT_H
+ #define BSP_COMPILER_SUPPORT_H
-#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
- #include "arm_cmse.h"
-#endif
+ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ #include "arm_cmse.h"
+ #endif
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
-#if defined(__ARMCC_VERSION) /* AC6 compiler */
+ #if defined(__ARMCC_VERSION) /* AC6 compiler */
/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
* memory (ROM) is reserved unnecessarily. */
- #define BSP_UNINIT_SECTION_PREFIX ".bss"
- #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
- #define BSP_DONT_REMOVE
- #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
- #define BSP_FORCE_INLINE __attribute__((always_inline))
-#elif defined(__GNUC__) /* GCC compiler */
- #define BSP_UNINIT_SECTION_PREFIX
- #define BSP_SECTION_HEAP ".heap"
- #define BSP_DONT_REMOVE
- #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
- #define BSP_FORCE_INLINE __attribute__((always_inline))
-#elif defined(__ICCARM__) /* IAR compiler */
- #define BSP_UNINIT_SECTION_PREFIX
- #define BSP_SECTION_HEAP "HEAP"
- #define BSP_DONT_REMOVE __root
- #define BSP_ATTRIBUTE_STACKLESS __stackless
- #define BSP_FORCE_INLINE _Pragma("inline=forced")
-#endif
+ #define BSP_UNINIT_SECTION_PREFIX ".bss"
+ #ifndef BSP_SECTION_HEAP
+ #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
+ #endif
+ #define BSP_DONT_REMOVE
+ #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
+ #define BSP_FORCE_INLINE __attribute__((always_inline))
+ #elif defined(__GNUC__) /* GCC compiler */
+ #define BSP_UNINIT_SECTION_PREFIX
+ #ifndef BSP_SECTION_HEAP
+ #define BSP_SECTION_HEAP ".heap"
+ #endif
+ #define BSP_DONT_REMOVE
+ #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
+ #define BSP_FORCE_INLINE __attribute__((always_inline))
+ #elif defined(__ICCARM__) /* IAR compiler */
+ #define BSP_UNINIT_SECTION_PREFIX
+ #ifndef BSP_SECTION_HEAP
+ #define BSP_SECTION_HEAP "HEAP"
+ #endif
+ #define BSP_DONT_REMOVE __root
+ #define BSP_ATTRIBUTE_STACKLESS __stackless
+ #define BSP_FORCE_INLINE _Pragma("inline=forced")
+ #endif
-#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
-#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
-#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
-#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
-#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
-#define BSP_SECTION_ID_CODE ".id_code"
+ #ifndef BSP_SECTION_STACK
+ #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
+ #endif
+ #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
+ #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
+ #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
+ #define BSP_SECTION_ROM_REGISTERS ".rom_registers"
+ #define BSP_SECTION_ID_CODE ".id_code"
/* Compiler neutral macros. */
-#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
+ #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
-#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
+ #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
-#define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED
+ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED
-#define BSP_WEAK_REFERENCE __attribute__((weak))
+ #define BSP_WEAK_REFERENCE __attribute__((weak))
/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
-#define BSP_STACK_ALIGNMENT (8)
+ #define BSP_STACK_ALIGNMENT (8)
/***********************************************************************************************************************
* TrustZone definitions
**********************************************************************************************************************/
-#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
- #if defined(__ICCARM__) /* IAR compiler */
- #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
- #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
+ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
+ #if defined(__ICCARM__) /* IAR compiler */
+ #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
+ #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
+ #else
+ #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
+ #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
+ #endif
#else
- #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
- #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
+ #define BSP_CMSE_NONSECURE_CALL
+ #define BSP_CMSE_NONSECURE_ENTRY
#endif
-#else
- #define BSP_CMSE_NONSECURE_CALL
- #define BSP_CMSE_NONSECURE_ENTRY
-#endif
/***********************************************************************************************************************
* Exported global variables
@@ -101,4 +113,8 @@
/** @} (end of addtogroup BSP_MCU) */
+ #ifdef __cplusplus
+}
+ #endif
+
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.c
index 4dd223547e..e51a062169 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -160,23 +160,29 @@ void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
-BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
+BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__(
+ (unused)) uint32_t loop_cnt)
{
- __asm volatile ("sw_delay_loop: \n"
+ __asm volatile (
+#if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__))
+ /* Optimize inner loop execution time on CM85 cores (Alignment allows for instruction fusion). */
+ ".align 8\n"
+#endif
+ "sw_delay_loop: \n"
#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
- " subs r0, #1 \n" ///< 1 cycle
+ " subs r0, #1 \n" ///< 1 cycle
#elif defined(__GNUC__)
- " sub r0, r0, #1 \n" ///< 1 cycle
+ " sub r0, r0, #1 \n" ///< 1 cycle
#endif
- " cmp r0, #0 \n" ///< 1 cycle
+ " cmp r0, #0 \n" ///< 1 cycle
/* CM0 and CM23 have a different instruction set */
#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
- " bne sw_delay_loop \n" ///< 2 cycles
+ " bne sw_delay_loop \n" ///< 2 cycles
#else
- " bne.n sw_delay_loop \n" ///< 2 cycles
+ " bne.n sw_delay_loop \n" ///< 2 cycles
#endif
- " bx lr \n"); ///< 2 cycles
+ " bx lr \n"); ///< 2 cycles
}
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.h
index e759e74fa2..8a2c20c0b2 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -41,7 +41,19 @@ FSP_HEADER
/* The number of cycles required per software delay loop. */
#ifndef BSP_DELAY_LOOP_CYCLES
- #define BSP_DELAY_LOOP_CYCLES (4)
+ #if defined(RENESAS_CORTEX_M85)
+
+/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for
+ * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in
+ * this case. */
+ #if defined(__ICCARM__)
+ #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1)
+ #else
+ #define BSP_DELAY_LOOP_CYCLES (1)
+ #endif
+ #else
+ #define BSP_DELAY_LOOP_CYCLES (4)
+ #endif
#endif
/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
index fd1d74e944..797f5c6014 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -105,7 +105,7 @@ void NMI_Handler (void)
uint16_t nmisr = R_ICU->NMISR;
/* Loop over all NMI status flags */
- for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_CACHE_PARITY; irq++)
+ for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_GRP_IRQ_TOTAL_ITEMS - 1); irq++)
{
/* If the current irq status register is set call the irq callback. */
if (0U != (nmisr & (1U << irq)))
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
index 3a62f1c7d1..001fa8e527 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -38,6 +38,8 @@ FSP_HEADER
* Typedef definitions
**********************************************************************************************************************/
+#ifndef BSP_OVERRIDE_GROUP_IRQ_T
+
/** Which interrupts can have callbacks registered. */
typedef enum e_bsp_grp_irq
{
@@ -57,6 +59,8 @@ typedef enum e_bsp_grp_irq
BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error
} bsp_grp_irq_t;
+#endif
+
/* Callback type. */
typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq);
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.c
index 07a0674e27..d9b4df141d 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.h
index 40d7c77ff0..ae5bb696e0 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.c
index ad0cbb7ac8..130761000a 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.h
index 22b7f692b2..bbd20a481e 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -409,7 +409,7 @@ __STATIC_INLINE void R_BSP_PinAccessEnable (void)
/** If this is first entry then allow writing of PFS. */
if (0 == g_protect_pfswe_counter)
{
- #if BSP_TZ_SECURE_BUILD
+ #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
@@ -448,7 +448,7 @@ __STATIC_INLINE void R_BSP_PinAccessDisable (void)
/** Is it safe to disable writing of PFS? */
if (0 == g_protect_pfswe_counter)
{
- #if BSP_TZ_SECURE_BUILD
+ #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled
#else
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.c
index 212ab48507..5a9faf2579 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -74,7 +74,12 @@ void bsp_irq_cfg (void)
#if !BSP_TZ_SECURE_BUILD
/* Set the DMAC channels to secure access. */
+ #ifdef BSP_TZ_CFG_ICUSARC
R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk;
+ #endif
+ #ifdef BSP_TZ_CFG_DMASARA
+ R_CPSCU->DMASARA = ~R_CPSCU_DMASARA_DMASARAn_Msk;
+ #endif
#endif
/* Place all vectors in non-secure state unless they are used in the secure project. */
@@ -105,7 +110,7 @@ void bsp_irq_cfg (void)
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
- for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
+ for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++)
{
R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i];
}
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.h
index 7fe448a7dd..baca33c74a 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -71,6 +71,10 @@ __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
{
/* Clear the IR bit in the selected IELSR register. */
R_ICU->IELSR_b[irq].IR = 0U;
+
+ /* Read back the IELSR register to ensure that the IR bit is cleared.
+ * MREF_INTERNAL_001 */
+ FSP_REGISTER_READ(R_ICU->IELSR[irq]);
}
/*******************************************************************************************************************//**
@@ -86,6 +90,9 @@ __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
/* Clear the IR bit in the selected IELSR register. */
R_BSP_IrqStatusClear(irq);
+ /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */
+ __DMB();
+
/* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
* exceptions every time an interrupt is cleared in the NVIC. */
uint32_t _irq = (uint32_t) irq;
@@ -133,7 +140,10 @@ __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
/* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
* every time an interrupt is enabled in the NVIC. */
uint32_t _irq = (uint32_t) irq;
- NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
+
+ __COMPILER_BARRIER();
+ NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
+ __COMPILER_BARRIER();
}
/*******************************************************************************************************************//**
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
index 594796c0b1..26a63083da 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
index 10b26dfcba..296340106e 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -24,6 +24,10 @@
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
+#if __has_include("internal/bsp_module_stop_internal.h")
+ #include "internal/bsp_module_stop_internal.h"
+#endif
+
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
@@ -48,7 +52,7 @@ FSP_HEADER
#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \
- BSP_MSTP_REG_ ## ip(channel); \
+ FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \
FSP_CRITICAL_SECTION_EXIT;}
/*******************************************************************************************************************//**
@@ -60,7 +64,7 @@ FSP_HEADER
#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \
- BSP_MSTP_REG_ ## ip(channel); \
+ FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \
FSP_CRITICAL_SECTION_EXIT;}
/** @} (end addtogroup BSP_MCU) */
@@ -69,20 +73,35 @@ FSP_HEADER
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \
channel) ? (1U << 5U) : (1U << 6U));
- #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
- #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
+
+ #ifndef BSP_MSTP_REG_FSP_IP_AGT
+ #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
+ #endif
+ #ifndef BSP_MSTP_BIT_FSP_IP_AGT
+ #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
+ #endif
+
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U));
#else
#if (2U == BSP_FEATURE_ELC_VERSION)
- #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
- #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31);
- #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
- #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
+ #if BSP_MCU_GROUP_RA6T2
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31);
+ #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
+ #else
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
+ #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
+ #endif
#define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U);
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
+ #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel));
#else
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
@@ -104,6 +123,8 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel));
#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U));
+#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel));
#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel));
#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB
@@ -150,12 +171,14 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel));
#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel));
+#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel));
#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel));
#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel));
#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC
-#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U));
+#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel));
#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel));
#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
index efab908a77..03f621cb64 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
index 6c9c89c6aa..c7be654681 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
index 1df5ccbec0..1e0ff6d48b 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -62,7 +62,28 @@
#if !BSP_CFG_BOOT_IMAGE
- #if 33U != __CORTEX_M // NOLINT(readability-magic-numbers)
+ #if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
+
+/** ID code definitions defined here. */
+BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
+{
+ BSP_CFG_ID_CODE_LONG_1,
+ #if BSP_FEATURE_BSP_OSIS_PADDING
+ 0xFFFFFFFFU,
+ #endif
+ BSP_CFG_ID_CODE_LONG_2,
+ #if BSP_FEATURE_BSP_OSIS_PADDING
+ 0xFFFFFFFFU,
+ #endif
+ BSP_CFG_ID_CODE_LONG_3,
+ #if BSP_FEATURE_BSP_OSIS_PADDING
+ 0xFFFFFFFFU,
+ #endif
+ BSP_CFG_ID_CODE_LONG_4
+};
+ #endif
+
+ #if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers)
/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) =
@@ -84,23 +105,25 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION
(uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
};
-/** ID code definitions defined here. */
-BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
-{
- BSP_CFG_ID_CODE_LONG_1,
- #if BSP_FEATURE_BSP_OSIS_PADDING
- 0xFFFFFFFFU,
+ #elif BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
+
+ #if !BSP_TZ_NONSECURE_BUILD
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
+ BSP_CFG_ROM_REG_OFS0;
+
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
+ 0xFFFFFFFF;
+
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
+ BSP_ROM_REG_OFS1_SETTING;
+
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
+ BSP_CFG_ROM_REG_BPS0;
+
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
+ BSP_CFG_ROM_REG_PBPS0;
+
#endif
- BSP_CFG_ID_CODE_LONG_2,
- #if BSP_FEATURE_BSP_OSIS_PADDING
- 0xFFFFFFFFU,
- #endif
- BSP_CFG_ID_CODE_LONG_3,
- #if BSP_FEATURE_BSP_OSIS_PADDING
- 0xFFFFFFFFU,
- #endif
- BSP_CFG_ID_CODE_LONG_4
-};
#else /* CM33 parts */
@@ -109,6 +132,11 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
+ #if BSP_FEATURE_BSP_HAS_OFS2
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_rom_ofs2 =
+ BSP_CFG_ROM_REG_OFS2;
+
+ #endif
#if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel =
BSP_CFG_ROM_REG_DUALSEL;
@@ -121,6 +149,12 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas"
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_rom_ofs1 =
BSP_ROM_REG_OFS1_SETTING;
+
+ #if BSP_FEATURE_BSP_HAS_OFS3
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3") g_bsp_rom_ofs3 =
+ BSP_CFG_ROM_REG_OFS3;
+
+ #endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_rom_banksel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps0") g_bsp_rom_bps0 =
@@ -129,12 +163,16 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps1
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps2") g_bsp_rom_bps2 =
BSP_CFG_ROM_REG_BPS2;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps3") g_bsp_rom_bps3 =
+ BSP_CFG_ROM_REG_BPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps0") g_bsp_rom_pbps0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps1") g_bsp_rom_pbps1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps2") g_bsp_rom_pbps2 =
BSP_CFG_ROM_REG_PBPS2;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps3") g_bsp_rom_pbps3 =
+ BSP_CFG_ROM_REG_PBPS3;
#endif
@@ -142,6 +180,12 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1_sec =
BSP_ROM_REG_OFS1_SETTING;
+
+ #if BSP_FEATURE_BSP_HAS_OFS3
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sec") g_bsp_rom_ofs3_sec =
+ BSP_CFG_ROM_REG_OFS3;
+
+ #endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_rom_banksel_sec =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps_sec0 =
@@ -150,14 +194,24 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec2") g_bsp_rom_bps_sec2 =
BSP_CFG_ROM_REG_BPS2;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec3") g_bsp_rom_bps_sec3 =
+ BSP_CFG_ROM_REG_BPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps_sec0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec1") g_bsp_rom_pbps_sec1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec2") g_bsp_rom_pbps_sec2 =
BSP_CFG_ROM_REG_PBPS2;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec3") g_bsp_rom_pbps_sec3 =
+ BSP_CFG_ROM_REG_PBPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_rom_ofs1_sel =
BSP_CFG_ROM_REG_OFS1_SEL;
+
+ #if BSP_FEATURE_BSP_HAS_OFS3
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sel") g_bsp_rom_ofs3_sel =
+ BSP_CFG_ROM_REG_OFS3_SEL;
+
+ #endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 =
@@ -166,6 +220,8 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_
BSP_CFG_ROM_REG_BPS_SEL1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel2") g_bsp_rom_bps_sel2 =
BSP_CFG_ROM_REG_BPS_SEL2;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel3") g_bsp_rom_bps_sel3 =
+ BSP_CFG_ROM_REG_BPS_SEL3;
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
index fa4e782503..2bf2cbbe7c 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.c
index 62d9fe81f6..6a4aef5429 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -32,6 +32,9 @@
#define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U)
#define RA_NOT_DEFINED (0)
+/* Branch T3 Instruction (IMM11=-2) */
+ #define BSP_PRV_INFINITE_LOOP (0xE7FE)
+
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
@@ -55,39 +58,34 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
#endif
#if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
- #pragma section=".tz_flash_nsc_start"
+
#pragma section=".tz_flash_ns_start"
- #pragma section=".tz_ram_nsc_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start");
+ #pragma section="Veneer$$CMSE"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) __section_begin(
+ "Veneer$$CMSE");
#pragma section=".tz_ram_ns_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) __section_begin(".tz_ram_ns_start");
+ #pragma section=".tz_ram_nsc_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) __section_begin(
+ ".tz_ram_nsc_start");
#pragma section=".tz_data_flash_ns_start"
- #pragma section=".tz_sdram_ns_start"
- #pragma section=".tz_qspi_flash_ns_start"
- #pragma section=".tz_ospi_device_0_ns_start"
- #pragma section=".tz_ospi_device_1_ns_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) __section_begin(
+ ".tz_data_flash_ns_start");
-/* &__tz__C is the address of the non-secure callable section. Must assign value to this variable or
- * linker will give error. */
-
-/* &__tz__N is the start address of the non-secure region. */
-BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
-BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
-BSP_DONT_REMOVE void * __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
-BSP_DONT_REMOVE void * __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
-BSP_DONT_REMOVE void * __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
-
- #if BSP_FEATURE_SDRAM_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start";
- #endif
-BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
- #if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
- #endif
- #if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
-BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
- #endif
-
-BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
#elif defined(__ARMCC_VERSION)
+ #if BSP_FEATURE_BSP_HAS_ITCM
+extern const uint32_t Image$$__tz_ITCM_N$$Base;
+extern const uint32_t Image$$__tz_ITCM_S$$Base;
+ #endif
+ #if BSP_FEATURE_BSP_HAS_DTCM
+extern const uint32_t Image$$__tz_DTCM_N$$Base;
+extern const uint32_t Image$$__tz_DTCM_S$$Base;
+ #endif
+ #if BSP_FEATURE_BSP_HAS_STBRAMSABAR
+extern const uint32_t Image$$__tz_STANDBY_SRAM_N$$Base;
+extern const uint32_t Image$$__tz_STANDBY_SRAM_S$$Base;
+ #endif
extern const uint32_t Image$$__tz_FLASH_N$$Base;
extern const uint32_t Image$$__tz_FLASH_C$$Base;
extern const uint32_t Image$$__tz_FLASH_S$$Base;
@@ -111,6 +109,18 @@ extern const uint32_t Image$$__tz_OPTION_SETTING_S_S$$Base;
extern const uint32_t Image$$__tz_ID_CODE_N$$Base;
extern const uint32_t Image$$__tz_ID_CODE_S$$Base;
+ #if BSP_FEATURE_BSP_HAS_ITCM
+ #define __tz_ITCM_N Image$$__tz_ITCM_N$$Base
+ #define __tz_ITCM_S Image$$__tz_ITCM_S$$Base
+ #endif
+ #if BSP_FEATURE_BSP_HAS_DTCM
+ #define __tz_DTCM_N Image$$__tz_DTCM_N$$Base
+ #define __tz_DTCM_S Image$$__tz_DTCM_S$$Base
+ #endif
+ #if BSP_FEATURE_BSP_HAS_STBRAMSABAR
+ #define __tz_STANDBY_SRAM_N Image$$__tz_STANDBY_SRAM_N$$Base
+ #define __tz_STANDBY_SRAM_S Image$$__tz_STANDBY_SRAM_S$$Base
+ #endif
#define __tz_FLASH_N Image$$__tz_FLASH_N$$Base
#define __tz_FLASH_C Image$$__tz_FLASH_C$$Base
#define __tz_FLASH_S Image$$__tz_FLASH_S$$Base
@@ -136,6 +146,18 @@ extern const uint32_t Image$$__tz_ID_CODE_S$$Base;
/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the
* start addresses of Secure, Non-secure and Non-secure Callable regions. */
+ #if BSP_FEATURE_BSP_HAS_ITCM
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_itcm = &__tz_ITCM_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_itcm = &__tz_ITCM_S;
+ #endif
+ #if BSP_FEATURE_BSP_HAS_DTCM
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_dtcm = &__tz_DTCM_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_dtcm = &__tz_DTCM_S;
+ #endif
+ #if BSP_FEATURE_BSP_HAS_STBRAMSABAR
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_standby_sram = &__tz_STANDBY_SRAM_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_standby_sram = &__tz_STANDBY_SRAM_S;
+ #endif
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S;
@@ -165,8 +187,19 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code =
#endif
#elif defined(__GNUC__)
+
extern const uint32_t FLASH_NS_IMAGE_START;
-BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START;
+extern const uint32_t __tz_FLASH_C;
+extern const uint32_t __tz_DATA_FLASH_N;
+extern const uint32_t __tz_RAM_N;
+extern const uint32_t __tz_RAM_C;
+
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) &__tz_FLASH_C;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) &__tz_DATA_FLASH_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) &__tz_RAM_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) &__tz_RAM_C;
+
#endif
#if BSP_TZ_SECURE_BUILD
@@ -192,6 +225,31 @@ void R_BSP_NonSecureEnter (void)
uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t));
bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address);
+ #if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+
+ /* Check if the NS application exists. If the address of the Reset_Handler is all '1's, then assume that
+ * the NS application has not been programmed.
+ *
+ * If the secure application attempts to jump to an invalid instruction, a HardFault will occur. If the
+ * MCU is in NSECSD state, then the debugger will be unable to connect and program the NS Application. Jumping to
+ * a valid instruction ensures that the debugger will be able to connect.
+ */
+ if (UINT32_MAX == *p_ns_reset_address)
+ {
+ p_ns_reset = (bsp_nonsecure_func_t) gp_start_of_nonsecure_ram;
+
+ /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n )). */
+ uint16_t * infinite_loop = (uint16_t *) gp_start_of_nonsecure_ram;
+ *infinite_loop = BSP_PRV_INFINITE_LOOP;
+
+ /* Set the NS stack pointer to a valid location in NS RAM. */
+ __TZ_set_MSP_NS((uint32_t) gp_start_of_nonsecure_ram + 0x20U);
+
+ /* Jump to the infinite loop. */
+ p_ns_reset();
+ }
+ #endif
+
/* Set the NS vector table address */
SCB_NS->VTOR = (uint32_t) p_ns_vector_table;
@@ -213,6 +271,19 @@ void R_BSP_NonSecureEnter (void)
**********************************************************************************************************************/
void R_BSP_SecurityInit (void)
{
+ /* Disable PRCR for SARs. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+ #if 0 == BSP_FEATURE_TZ_HAS_DLM
+
+ /* If DLM is not implemented, then the TrustZone partitions must be set at run-time. */
+ R_PSCU->CFSAMONA = (uint32_t) gp_start_of_nonsecure_flash & R_PSCU_CFSAMONA_CFS2_Msk;
+ R_PSCU->CFSAMONB = (uint32_t) gp_start_of_nonsecure_callable_flash & R_PSCU_CFSAMONB_CFS1_Msk;
+ R_PSCU->DFSAMON = (uint32_t) gp_start_of_nonsecure_data_flash & R_PSCU_DFSAMON_DFS_Msk;
+ R_PSCU->SSAMONA = (uint32_t) gp_start_of_nonsecure_ram & R_PSCU_SSAMONA_SS2_Msk;
+ R_PSCU->SSAMONB = (uint32_t) gp_start_of_nonsecure_callable_ram & R_PSCU_SSAMONB_SS1_Msk;
+ #endif
+
/* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the
* system. */
SAU->CTRL = SAU_CTRL_ALLNS_Msk;
@@ -247,11 +318,11 @@ void R_BSP_SecurityInit (void)
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
#endif
- /* Disable PRCR for SARs. */
- R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+ #if BSP_FEATURE_BSP_HAS_TZFSAR
/* Set TrustZone filter to Secure. */
R_TZF->TZFSAR = ~R_TZF_TZFSAR_TZFSA0_Msk;
+ #endif
/* Set TrustZone filter exception response. */
R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 1U;
@@ -266,7 +337,9 @@ void R_BSP_SecurityInit (void)
R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR;
/* Initialize Type 2 SARs. */
- R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
+ #ifdef BSP_TZ_CFG_CSAR
+ R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
+ #endif
R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */
R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */
R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */
@@ -277,11 +350,21 @@ void R_BSP_SecurityInit (void)
#endif
R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */
R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */
+ #ifdef BSP_TZ_CFG_ICUSARC
R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */
+ #endif
+ #ifdef BSP_TZ_CFG_DMASARA
+ R_CPSCU->DMASARA = BSP_TZ_CFG_DMASARA; /* DMAC Channel Security Attribution. */
+ #endif
+ #ifdef BSP_TZ_CFG_ICUSARD
R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */
+ #endif
R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */
#ifdef BSP_TZ_CFG_ICUSARF
R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */
+ #endif
+ #ifdef BSP_TZ_CFG_TEVTRCR
+ R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */
#endif
R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */
R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */
@@ -290,7 +373,9 @@ void R_BSP_SecurityInit (void)
R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */
R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */
- #if BSP_TZ_CFG_ICUSARC != UINT32_MAX
+ #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \
+ (defined(BSP_TZ_CFG_DMASARA) && (BSP_TZ_CFG_DMASARA != UINT32_MAX))
+
R_BSP_MODULE_START(FSP_IP_DMAC, 0);
/* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.h
index 0bd1a0eee5..fa938cb526 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
index 2f3e203352..c4367add6c 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
index d407d7092e..c475d661d2 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
index 0655d6be80..f43b503ddd 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -52,289 +52,366 @@
* Private global variables and functions
**********************************************************************************************************************/
-#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU
-#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU
-#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
-#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
-#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC)
-#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
-#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
-#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
-#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
-#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
-#define BSP_FEATURE_ADC_HAS_PGA (0U)
-#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
-#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
-#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
-#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
-#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
-#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
-#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU)
-#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU
-#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
-#define BSP_FEATURE_ADC_TSN_SLOPE (4000)
-#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13
-#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28
-#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
-#define BSP_FEATURE_ADC_HAS_ADBUF (1U)
+#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
+#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
+#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
+#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
+#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
+#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
+#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC)
+#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
+#define BSP_FEATURE_ADC_HAS_ADBUF (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
+#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
+#define BSP_FEATURE_ADC_HAS_PGA (0U)
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
+#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
+#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
+#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
+#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU
+#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
+#define BSP_FEATURE_ADC_TSN_SLOPE (4000)
+#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13
+#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28
+#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
-#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
-#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
+#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
-#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
-#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
-#define BSP_FEATURE_AGT_HAS_AGTW (0U)
+#define BSP_FEATURE_BSP_FLASH_CACHE (1)
+#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
+#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
+#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1)
+#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1)
+#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
+#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
+#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U)
+#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock
+#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0)
+#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U)
+#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
+#define BSP_FEATURE_BSP_HAS_OFS2 (0)
+#define BSP_FEATURE_BSP_HAS_OFS3 (0)
+#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U)
+#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0)
+#define BSP_FEATURE_BSP_HAS_SP_MON (0U)
+#define BSP_FEATURE_BSP_HAS_SYRACCR (0U)
+#define BSP_FEATURE_BSP_HAS_TZFSAR (1)
+#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU
+#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock.
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U)
+#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U)
+#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid.
+#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U)
+#define BSP_FEATURE_BSP_NUM_PMSAR (12U)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U)
+#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U)
+#define BSP_FEATURE_BSP_OSIS_PADDING (0U)
+#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U)
+#define BSP_FEATURE_BSP_RESET_TRNG (0U)
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
+#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U)
+#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U)
+#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U)
-#define BSP_FEATURE_BSP_FLASH_CACHE (1)
-#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
-#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
-#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0)
-#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
-#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1)
-#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
-#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU
-#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU
-#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U)
-#define BSP_FEATURE_BSP_HAS_SP_MON (0U)
-#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock.
-#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U)
-#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U)
-#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U)
-#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U)
-#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U)
-#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU
-#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid.
-#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U)
-#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU)
-#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U)
-#define BSP_FEATURE_BSP_OSIS_PADDING (0U)
-#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U)
-#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U)
-#define BSP_FEATURE_BSP_RESET_TRNG (0U)
-#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
-#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle.
-#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
-#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
-#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U)
-#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U)
-#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U)
+#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B')
+#define BSP_FEATURE_CANFD_LITE (0U)
+#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U)
+#define BSP_FEATURE_CANFD_NUM_INSTANCES (1U)
-#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
-#define BSP_FEATURE_CAN_CLOCK (0U)
-#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
-#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD
+#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
+#define BSP_FEATURE_CAN_CLOCK (0U)
+#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
+#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD
-#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U)
-#define BSP_FEATURE_CANFD_LITE (0U)
+#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1)
+#define BSP_FEATURE_CGC_HAS_BCLK (1U)
+#define BSP_FEATURE_CGC_HAS_CPUCLK (0U)
+#define BSP_FEATURE_CGC_HAS_FCLK (1U)
+#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
+#define BSP_FEATURE_CGC_HAS_FLL (1U)
+#define BSP_FEATURE_CGC_HAS_FLWT (1U)
+#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U)
+#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
+#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKE (0U)
+#define BSP_FEATURE_CGC_HAS_PLL (1U)
+#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI.
+#define BSP_FEATURE_CGC_HAS_SOPCCR (1U)
+#define BSP_FEATURE_CGC_HAS_SOSC (1U)
+#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC.
+#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
+#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0)
+#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U)
+#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
+#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
+#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
+#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
+#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
+#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
+#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
+#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
+#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U)
+#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
+#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U)
+#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
+#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0)
+#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
+#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78)
+#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0)
-#define BSP_FEATURE_CGC_HAS_BCLK (1U)
-#define BSP_FEATURE_CGC_HAS_FCLK (1U)
-#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
-#define BSP_FEATURE_CGC_HAS_FLWT (1U)
-#define BSP_FEATURE_CGC_HAS_FLL (1U)
-#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U)
-#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
-#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
-#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
-#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
-#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
-#define BSP_FEATURE_CGC_HAS_PLL (1U)
-#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI.
-#define BSP_FEATURE_CGC_HAS_SOSC (1U)
-#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC.
-#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
-#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
-#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
-#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
-#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
-#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
-#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
-#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
-#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
-#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
-#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
-#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
-#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
-#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U)
-#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0)
-#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
-#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U)
-#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0)
+#define BSP_FEATURE_CRYPTO_HAS_AES (1)
+#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1)
+#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1)
+#define BSP_FEATURE_CRYPTO_HAS_ECC (1)
+#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1)
+#define BSP_FEATURE_CRYPTO_HAS_HASH (1)
+#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_CRYPTO_HAS_RSA (1)
+#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5 (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5B (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE7 (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1)
-#define BSP_FEATURE_CRYPTO_HAS_AES (1)
-#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1)
-#define BSP_FEATURE_CRYPTO_HAS_ECC (1)
-#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1)
-#define BSP_FEATURE_CRYPTO_HAS_HASH (1)
-#define BSP_FEATURE_CRYPTO_HAS_RSA (1)
-#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1)
-#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1)
-#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1)
+#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U)
+#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U)
+#define BSP_FEATURE_CTSU_HAS_TXVSEL (1)
+#define BSP_FEATURE_CTSU_VERSION (1)
-#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U)
-#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U)
-#define BSP_FEATURE_CTSU_HAS_TXVSEL (1)
-#define BSP_FEATURE_CTSU_VERSION (1)
+#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU
-#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU
-#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU
-#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU
-#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU
+#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U)
+#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
+#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
+#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U)
+#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U)
+#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
+#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
-#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
-#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
-#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U)
-#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
-#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U)
-#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
+#define BSP_FEATURE_DMAC_HAS_DELSR (0U)
+#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U)
+#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
-#define BSP_FEATURE_DOC_VERSION (1U)
+#define BSP_FEATURE_DOC_VERSION (1U)
-#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
-#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U)
+#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register
-#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register
+#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
+#define BSP_FEATURE_ELC_VERSION (1U)
-#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
-#define BSP_FEATURE_ELC_VERSION (1U)
+#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
+#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
+#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0U) // Feature not available on this MCU
-#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
-#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
+#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U)
+#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U)
+#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U)
+#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U)
+#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
+#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
+#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
+#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1)
+#define BSP_FEATURE_FLASH_HP_VERSION (40U)
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U)
-#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U)
-#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U)
-#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U)
-#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U)
-#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
-#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
-#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
-#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1)
-#define BSP_FEATURE_FLASH_HP_VERSION (40U)
-#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU
-#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU
+#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0)
-#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0)
+#define BSP_FEATURE_GPTE_CHANNEL_MASK (0)
-#define BSP_FEATURE_GPTE_CHANNEL_MASK (0)
+#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U)
+#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
+#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_TPCS_SHIFT (0U)
+#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU)
-#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
-#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU)
-#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
-#define BSP_FEATURE_GPT_HAS_GTCLKCR (0U)
-#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU
-#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU
-#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU
-#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU
-#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U)
-#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U)
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU
-#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
-#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
-#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register
-#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U)
+#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U)
+#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
+#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
+#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register
+#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U)
-#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U)
-#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07)
-#define BSP_FEATURE_IIC_VERSION (1U)
-#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U)
-#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U)
+#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U)
+#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U)
+#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07)
+#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU TODO_CHECK_FEATURE
-#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU
-#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU
-#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU
+#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU)
+#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
+#define BSP_FEATURE_IOPORT_VERSION (1U)
-#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU)
-#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
+#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL)
+#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0U) // Feature not available on this MCU
-#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
-#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U)
-#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
-#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU)
-#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
-#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
-#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
-#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
-#define BSP_FEATURE_LPM_HAS_STCONR (0U)
-#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0)
-#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register
-#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register
+#define BSP_FEATURE_KINT_HAS_MSTP (0U)
-#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U)
-#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U)
-#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
-#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
-#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
-#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
-#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
+#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
+#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U)
+#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
+#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU)
+#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U)
+#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U)
+#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U)
+#define BSP_FEATURE_LPM_HAS_LPSCR (0U)
+#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U)
+#define BSP_FEATURE_LPM_HAS_SNOOZE (1U)
+#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
+#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
+#define BSP_FEATURE_LPM_HAS_STCONR (0U)
+#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0)
+#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register
+#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register
+#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U)
-#define BSP_FEATURE_IOPORT_VERSION (1U)
+#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U)
+#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U)
+#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
-#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
-#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
-#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
-#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
+#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U)
+#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U)
-#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U)
-#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U)
+#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
+#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
+#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
+#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
-#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
+#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U)
+#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U)
-#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U)
+#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
-#define BSP_FEATURE_SCI_VERSION (1U)
-#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
-#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
-#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
-#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
-#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
-#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature
+#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U)
-#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
-#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
-#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U)
-#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB)
-#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported
+#define BSP_FEATURE_RTC_IS_AVAILABLE (1U)
+#define BSP_FEATURE_RTC_IS_IRTC (0U)
+#define BSP_FEATURE_RTC_HAS_ROPSEL (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U)
-#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U)
+#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
+#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
+#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature
+#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
+#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
+#define BSP_FEATURE_SCI_VERSION (1U)
-#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB)
+#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
+#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
+#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U)
-#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA)
-#define BSP_FEATURE_SPI_HAS_SPCR3 (1U)
-#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
-#define BSP_FEATURE_SPI_MAX_CHANNEL (2U)
+#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U)
-#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U)
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0)
-#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
-#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
+#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SPI_HAS_SPCR3 (1U)
+#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
+#define BSP_FEATURE_SPI_MAX_CHANNEL (2U)
+#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U)
-#define BSP_FEATURE_TFU_SPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU
+#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U)
-#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
+#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
+#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
-#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
+#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU
-#define BSP_FEATURE_BSP_NUM_PMSAR (12U)
+#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
+#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
+#define BSP_FEATURE_TZ_HAS_DLM (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U)
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
index 8b73d26c4c..3a63bb9612 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_ioport/r_ioport.c
index f45ae0b2e9..3b9717239b 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_ioport/r_ioport.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_ioport/r_ioport.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -46,10 +46,6 @@
/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
#define IOPORT_PRV_PORT_OFFSET (8U)
-#ifndef BSP_MCU_VBATT_SUPPORT
- #define BSP_MCU_VBATT_SUPPORT (0U)
-#endif
-
#define IOPORT_PRV_PORT_BITS (0xFF00U)
#define IOPORT_PRV_PIN_BITS (0x00FFU)
@@ -84,7 +80,7 @@ static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port,
static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value);
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP
#endif
@@ -106,7 +102,6 @@ const ioport_api_t g_ioport_on_ioport =
.pinCfg = R_IOPORT_PinCfg,
.pinEventInputRead = R_IOPORT_PinEventInputRead,
.pinEventOutputWrite = R_IOPORT_PinEventOutputWrite,
- .pinEthernetModeCfg = R_IOPORT_EthernetModeCfg,
.pinRead = R_IOPORT_PinRead,
.pinWrite = R_IOPORT_PinWrite,
.portDirectionSet = R_IOPORT_PortDirectionSet,
@@ -116,7 +111,7 @@ const ioport_api_t g_ioport_on_ioport =
.portWrite = R_IOPORT_PortWrite,
};
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
static const bsp_io_port_pin_t g_vbatt_pins_input[] =
{
BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN
@@ -238,7 +233,7 @@ fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin,
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/* Create temporary structure for handling VBATT pins. */
ioport_cfg_t temp_cfg;
@@ -673,39 +668,6 @@ fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_por
return FSP_SUCCESS;
}
-/***********************************************************************************************************************
- * DEPRECATED Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
- *
- * @retval FSP_SUCCESS Ethernet PHY mode set
- * @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid
- * @retval FSP_ERR_UNSUPPORTED Ethernet configuration not supported on this device.
- * @retval FSP_ERR_NOT_OPEN The module has not been opened
- * @retval FSP_ERR_ASSERTION NULL pointer
- *
- * @note This function is not re-entrant.
- **********************************************************************************************************************/
-fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl,
- ioport_ethernet_channel_t channel,
- ioport_ethernet_mode_t mode)
-{
- FSP_ERROR_RETURN(1U == BSP_FEATURE_IOPORT_HAS_ETHERNET, FSP_ERR_UNSUPPORTED);
-
-#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
- ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(channel < IOPORT_ETHERNET_CHANNEL_END, FSP_ERR_INVALID_ARGUMENT);
- FSP_ERROR_RETURN(mode < IOPORT_ETHERNET_MODE_END, FSP_ERR_INVALID_ARGUMENT);
-#else
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_PARAMETER_NOT_USED(channel);
-#endif
-
- R_PMISC->PFENET = (uint8_t) mode;
-
- return FSP_SUCCESS;
-}
-
/*******************************************************************************************************************//**
* @} (end addtogroup IOPORT)
**********************************************************************************************************************/
@@ -721,7 +683,7 @@ fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl,
**********************************************************************************************************************/
void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
{
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/* Handle any VBATT domain pin configuration. */
bsp_vbatt_init(p_cfg);
@@ -812,7 +774,7 @@ static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value)
R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value;
}
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/*******************************************************************************************************************//**
* @brief Initializes VBTICTLR register based on pin configuration.
@@ -826,12 +788,6 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
{
uint32_t pin_index;
uint32_t vbatt_index;
- uint8_t local_vbtictlr_set; ///< Will hold bits to set in VBTICTLR
- uint8_t local_vbtictlr_clear; ///< Will hold bits to clear in VBTICTLR
-
- /* Make no changes unless required. */
- local_vbtictlr_set = 0U;
- local_vbtictlr_clear = 0U;
/* Must loop over all pins as pin configuration table is unordered. */
for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++)
@@ -850,29 +806,78 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value))
{
/* Bit should be set to 1. */
- local_vbtictlr_set |= (uint8_t) (1U << vbatt_index);
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+ if (0 == (R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)))
+ {
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+ R_SYSTEM->VBTICTLR |= (uint8_t) (1U << vbatt_index);
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+ }
+ else
+ {
+ /* Do nothing: it is already enabled. */
+ }
+ #endif
+ #if BSP_FEATURE_RTC_HAS_TCEN
+ #if BSP_TZ_NONSECURE_BUILD
+ if (0 == R_PSCU->PSARE_b.PSARE2)
+ {
+ /* Do nothing: non secure build can't configure secure RTC registers. */
+ }
+ else
+ #endif
+ {
+ if (0 == R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN)
+ {
+ R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 1;
+ R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+ }
+ else
+ {
+ /* Do nothing: it is already enabled. */
+ }
+ }
+ #endif
}
else
{
/* Bit should be cleared to 0. */
- local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index);
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+ if ((R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)) > 0)
+ {
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+ R_SYSTEM->VBTICTLR &= (uint8_t) ~(1U << vbatt_index);
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+ }
+ else
+ {
+ /* Do nothing: it is already disabled. */
+ }
+ #endif
+ #if BSP_FEATURE_RTC_HAS_TCEN
+ #if BSP_TZ_NONSECURE_BUILD
+ if (0 == R_PSCU->PSARE_b.PSARE2)
+ {
+ /* Do nothing: non secure build can't configure secure RTC registers. */
+ }
+ else
+ #endif
+ {
+ if (R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN > 0)
+ {
+ R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 0;
+ R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+ }
+ else
+ {
+ /* Do nothing: it is already disabled. */
+ }
+ }
+ #endif
}
}
}
}
-
- /* Disable write protection on VBTICTLR. */
- R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
-
- /* Read value, set and clear bits as needed and write back. */
- uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR;
- local_vbtictlr |= local_vbtictlr_set; ///< Set appropriate bits
- local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits
-
- R_SYSTEM->VBTICTLR = local_vbtictlr;
-
- /* Enable write protection on VBTICTLR. */
- R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_sci_uart/r_sci_uart.c b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_sci_uart/r_sci_uart.c
index 7f33e83dff..1d2c092b17 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_sci_uart/r_sci_uart.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_sci_uart/r_sci_uart.c
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@@ -93,6 +93,7 @@
#define SCI_SSR_ORER_MASK (0x20U) ///< overflow error
#define SCI_SSR_FER_MASK (0x10U) ///< framing error
#define SCI_SSR_PER_MASK (0x08U) ///< parity err
+#define SCI_SSR_FIFO_RESERVED_MASK (0x02U) ///< Reserved bit mask for SSR_FIFO register
#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK)
#define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE)
@@ -168,6 +169,9 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_uart_prv_ns_callback)(uart_c
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
+
+static void r_sci_negate_de_pin(sci_uart_instance_ctrl_t const * const p_ctrl);
+
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_ctrl,
@@ -316,7 +320,7 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
/* Check parameters. */
FSP_ASSERT(p_ctrl);
FSP_ASSERT(p_cfg);
- FSP_ASSERT(p_cfg->p_callback);
+
FSP_ASSERT(p_cfg->p_extend);
FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting);
FSP_ERROR_RETURN(SCI_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
@@ -337,6 +341,15 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
FSP_ERR_INVALID_ARGUMENT);
}
+ #if (SCI_UART_CFG_RS485_SUPPORT)
+ if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.enable == SCI_UART_RS485_ENABLE)
+ {
+ FSP_ERROR_RETURN(
+ ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.de_control_pin != SCI_UART_INVALID_16BIT_PARAM,
+ FSP_ERR_INVALID_ARGUMENT);
+ }
+ #endif
+
FSP_ASSERT(p_cfg->rxi_irq >= 0);
FSP_ASSERT(p_cfg->txi_irq >= 0);
FSP_ASSERT(p_cfg->tei_irq >= 0);
@@ -378,6 +391,9 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
#endif
+ /* Negate driver enable if RS-485 mode is enabled. */
+ r_sci_negate_de_pin(p_ctrl);
+
/* Enable the SCI channel and reset the registers to their initial state. */
R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel);
@@ -488,6 +504,9 @@ fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_api_ctrl)
/* Remove power to the channel. */
R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel);
+ /* Negate driver enable if RS-485 mode is enabled. */
+ r_sci_negate_de_pin(p_ctrl);
+
return FSP_SUCCESS;
}
@@ -583,6 +602,22 @@ fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons
FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE);
#endif
+ #if (SCI_UART_CFG_RS485_SUPPORT)
+ sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+ /* If RS-485 is enabled, then assert the driver enable pin at the start of a write transfer. */
+ if (p_extend->rs485_setting.enable)
+ {
+ R_BSP_PinAccessEnable();
+
+ bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH ==
+ p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW;
+ R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level);
+
+ R_BSP_PinAccessDisable();
+ }
+ #endif
+
/* Transmit interrupts must be disabled to start with. */
p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
@@ -844,6 +879,9 @@ fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communica
#endif
p_ctrl->tx_src_bytes = 0U;
+ /* Negate driver enable if RS-485 mode is enabled. */
+ r_sci_negate_de_pin(p_ctrl);
+
FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
}
#endif
@@ -915,17 +953,6 @@ fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain
*remaining_bytes = transfer_info.transfer_length_remaining;
}
#endif
- #if SCI_UART_CFG_FIFO_SUPPORT
- if (0U != p_ctrl->fifo_depth)
- {
- /* Reset the receive fifo */
- p_ctrl->p_reg->FCR_b.RFRST = 1U;
-
- /* Wait until RFRST cleared after 1 PCLK according to section 34.2.26 "FIFO Control Register (FCR) in the
- * RA6M3 manual R01UH0886EJ0100 or the relevant section for the MCU being used.*/
- FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 0U);
- }
- #endif
#else
return FSP_ERR_UNSUPPORTED;
@@ -940,14 +967,14 @@ fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain
*
* @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc.
* @param[in] bitrate_modulation Enable bitrate modulation
- * @param[in] baud_rate_error_x_1000 <baud_rate_percent_error> x 1000 required for module to function.
- * Absolute max baud_rate_error is 15000 (15%).
+ * @param[in] baud_rate_error_x_1000 Max baud rate error. At most <baud_rate_percent_error> x 1000 required
+ * for module to function. Absolute max baud_rate_error is 15000 (15%).
* @param[out] p_baud_setting Baud setting information stored here if successful
*
* @retval FSP_SUCCESS Baud rate is set successfully
* @retval FSP_ERR_ASSERTION Null pointer
- * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', source clock frequency could not be read, or error in
- * calculated baud rate is larger than 10%.
+ * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested
+ * max error, or requested max error in baud rate is larger than 15%.
**********************************************************************************************************************/
fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
bool bitrate_modulation,
@@ -956,12 +983,12 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
{
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(p_baud_setting);
- FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 > baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT);
+ FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT);
#endif
- p_baud_setting->brr = SCI_UART_BRR_MAX;
- p_baud_setting->brme = 0U;
+ p_baud_setting->brr = SCI_UART_BRR_MAX;
+ p_baud_setting->semr_baudrate_bits_b.brme = 0U;
p_baud_setting->mddr = SCI_UART_MDDR_MIN;
/* Find the best BRR (bit rate register) value.
@@ -1059,18 +1086,18 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
*/
if (bit_err < hit_bit_err)
{
- p_baud_setting->bgdm = g_async_baud[i].bgdm;
- p_baud_setting->abcs = g_async_baud[i].abcs;
- p_baud_setting->abcse = g_async_baud[i].abcse;
- p_baud_setting->cks = g_async_baud[i].cks;
- p_baud_setting->brr = (uint8_t) temp_brr;
- hit_bit_err = bit_err;
- hit_mddr = mddr;
+ p_baud_setting->semr_baudrate_bits_b.bgdm = g_async_baud[i].bgdm;
+ p_baud_setting->semr_baudrate_bits_b.abcs = g_async_baud[i].abcs;
+ p_baud_setting->semr_baudrate_bits_b.abcse = g_async_baud[i].abcse;
+ p_baud_setting->cks = g_async_baud[i].cks;
+ p_baud_setting->brr = (uint8_t) temp_brr;
+ hit_bit_err = bit_err;
+ hit_mddr = mddr;
}
if (bitrate_modulation)
{
- p_baud_setting->brme = 1U;
+ p_baud_setting->semr_baudrate_bits_b.brme = 1U;
p_baud_setting->mddr = (uint8_t) hit_mddr;
}
else
@@ -1096,6 +1123,33 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
* Private Functions
**********************************************************************************************************************/
+/*******************************************************************************************************************//**
+ * Negate the DE pin if it is enabled.
+ *
+ * @param[in] p_ctrl Pointer to the control block for the channel.
+ **********************************************************************************************************************/
+static void r_sci_negate_de_pin (sci_uart_instance_ctrl_t const * const p_ctrl)
+{
+#if (SCI_UART_CFG_RS485_SUPPORT)
+ sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+ /* If RS-485 is enabled, then negate the driver enable pin at the end of a write transfer. */
+ if (p_extend->rs485_setting.enable)
+ {
+ R_BSP_PinAccessEnable();
+
+ bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH ==
+ p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH;
+ R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level);
+
+ R_BSP_PinAccessDisable();
+ }
+
+#else
+ FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+}
+
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
/*******************************************************************************************************************//**
@@ -1172,7 +1226,7 @@ static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const
if (UART_DATA_BITS_9 == p_ctrl->p_cfg->data_bits)
{
- p_info->size = TRANSFER_SIZE_2_BYTE;
+ p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE;
/* Casting for compatibility with 7 or 8 bit mode. */
*p_transfer_reg = sci_buffer_address + SCI_UART_9BIT_TRANSFER_BUFFER_OFFSET;
@@ -1554,7 +1608,7 @@ static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_ctrl, uint32_
void sci_uart_txi_isr (void)
{
/* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
+ FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@@ -1589,7 +1643,12 @@ void sci_uart_txi_isr (void)
}
/* Clear TDFE flag */
- p_ctrl->p_reg->SSR_FIFO_b.TDFE = 0U;
+ /* Don't acess the flag via bit fields because bit 1 is reserved. It must be written as '1' and has an */
+ /* undefined read value. Bit fields will attempt to do a read-modify-write which could have unintended */
+ /* side effects provided the undefined read behavior. */
+ uint8_t ssr_fifo =
+ (uint8_t) ((p_ctrl->p_reg->SSR_FIFO | SCI_SSR_FIFO_RESERVED_MASK) & ~R_SCI0_SSR_FIFO_TDFE_Msk);
+ p_ctrl->p_reg->SSR_FIFO = ssr_fifo;
}
else
#endif
@@ -1620,11 +1679,16 @@ void sci_uart_txi_isr (void)
p_ctrl->p_reg->SCR = scr_temp;
p_ctrl->p_tx_src = NULL;
- r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY);
+
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY);
+ }
}
/* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
+ FSP_CONTEXT_RESTORE
}
#endif
@@ -1647,7 +1711,7 @@ void sci_uart_txi_isr (void)
void sci_uart_rxi_isr (void)
{
/* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
+ FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@@ -1701,8 +1765,12 @@ void sci_uart_rxi_isr (void)
if (0 == p_ctrl->rx_dest_bytes)
{
- /* Call user callback with the data. */
- r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR);
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ /* Call user callback with the data. */
+ r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR);
+ }
}
else
{
@@ -1712,7 +1780,11 @@ void sci_uart_rxi_isr (void)
if (0 == p_ctrl->rx_dest_bytes)
{
- r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+ }
}
}
@@ -1744,13 +1816,17 @@ void sci_uart_rxi_isr (void)
p_ctrl->p_rx_dest = NULL;
- /* Call callback */
- r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ /* Call callback */
+ r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+ }
}
#endif
/* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
+ FSP_CONTEXT_RESTORE
}
#endif
@@ -1765,7 +1841,7 @@ void sci_uart_rxi_isr (void)
void sci_uart_tei_isr (void)
{
/* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
+ FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@@ -1775,13 +1851,20 @@ void sci_uart_tei_isr (void)
/* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */
p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
- r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE);
+ /* Negate driver enable if RS-485 mode is enabled. */
+ r_sci_negate_de_pin(p_ctrl);
+
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE);
+ }
/* Clear pending IRQ to make sure it doesn't fire again after exiting */
R_BSP_IrqStatusClear(irq);
/* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
+ FSP_CONTEXT_RESTORE
}
#endif
@@ -1833,8 +1916,15 @@ void sci_uart_eri_isr (void)
/* Clear error condition. */
p_ctrl->p_reg->SSR &= (uint8_t) (~SCI_RCVR_ERR_MASK);
- /* Call callback. */
- r_sci_uart_call_callback(p_ctrl, data, event);
+ /* Negate driver enable if RS-485 mode is enabled. */
+ r_sci_negate_de_pin(p_ctrl);
+
+ /* If a callback was provided, call it with the argument */
+ if (NULL != p_ctrl->p_callback)
+ {
+ /* Call callback. */
+ r_sci_uart_call_callback(p_ctrl, data, event);
+ }
/* Clear pending IRQ to make sure it doesn't fire again after exiting */
R_BSP_IrqStatusClear(irq);
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/board_cfg.h
index 274684eab5..825f8cd329 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/board_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/board_cfg.h
@@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
-void bsp_init(void * p_args);
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ void bsp_init(void * p_args);
+
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* BOARD_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
index 4aeb31490d..9cbb0ed383 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -1,7 +1,11 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
-#include "bsp_clock_cfg.h"
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
@@ -14,6 +18,9 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
@@ -30,7 +37,6 @@
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
- #define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) // DEPRECATED, replace with BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
@@ -49,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
+
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* BSP_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
index f19518a62d..e532478f8f 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA6M5BH3CFC
+ #define BSP_MCU_FEATURE_SET ('B')
#define BSP_ROM_SIZE_BYTES (2097152)
#define BSP_RAM_SIZE_BYTES (524288)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 7922272357..050c0e9b4f 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -1,7 +1,11 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
-#include "bsp_mcu_device_pn_cfg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ #include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
@@ -23,7 +27,6 @@
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
- #define BSP_MCU_VBATT_SUPPORT (1)
#if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
@@ -294,6 +297,11 @@
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
+ /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+ #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@@ -332,6 +340,10 @@
/* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+ /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+ #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
#endif
/* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
@@ -344,6 +356,10 @@
/* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+ /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+ #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
#endif
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
@@ -356,8 +372,16 @@
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+ /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+ #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
+
+#ifdef __cplusplus
+}
+#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
index 8db04e4b29..1d94dcb7a7 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -2,7 +2,15 @@
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
#endif /* BSP_PIN_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_ioport_cfg.h
index 6b4353d238..d2688bf5ba 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_ioport_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
#endif /* R_IOPORT_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
index c785418bcf..073c426579 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
@@ -1,8 +1,17 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
-#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
+ #define SCI_UART_CFG_RS485_SUPPORT (0)
+
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* R_SCI_UART_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_gen/bsp_clock_cfg.h b/bsp/renesas/ebf_qi_min_6m5/ra_gen/bsp_clock_cfg.h
index b5743508fc..ded1dbee7f 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_gen/bsp_clock_cfg.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_gen/bsp_clock_cfg.h
@@ -7,25 +7,29 @@
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
-#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
-#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
-#define BSP_CFG_BCLK_OUTPUT (2) /* BCLK/2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_gen/hal_data.c b/bsp/renesas/ebf_qi_min_6m5/ra_gen/hal_data.c
index a64e73f484..ba42e503a3 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_gen/hal_data.c
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_gen/hal_data.c
@@ -4,7 +4,7 @@ sci_uart_instance_ctrl_t g_uart4_ctrl;
baud_setting_t g_uart4_baud_setting =
{
- /* Baud rate calculated with 0.469% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .brme = false
+ /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
@@ -21,6 +21,15 @@ sci_uart_instance_ctrl_t g_uart4_ctrl;
#else
.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
#endif
+ .rs485_setting = {
+ .enable = SCI_UART_RS485_DISABLE,
+ .polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
+ #if 0xFF != 0xFF
+ .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
+ #else
+ .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
+ #endif
+ },
};
/** UART interface configuration */
diff --git a/bsp/renesas/ebf_qi_min_6m5/ra_gen/vector_data.h b/bsp/renesas/ebf_qi_min_6m5/ra_gen/vector_data.h
index 24386909cf..d1eac4f703 100644
--- a/bsp/renesas/ebf_qi_min_6m5/ra_gen/vector_data.h
+++ b/bsp/renesas/ebf_qi_min_6m5/ra_gen/vector_data.h
@@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (4)
@@ -20,4 +23,7 @@
#define SCI4_TEI_IRQn ((IRQn_Type) 2) /* SCI4 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 3) /* SCI4 ERI (Receive error) */
#define SCI4_ERI_IRQn ((IRQn_Type) 3) /* SCI4 ERI (Receive error) */
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* VECTOR_DATA_H */
\ No newline at end of file
diff --git a/bsp/renesas/ebf_qi_min_6m5/template.uvoptx b/bsp/renesas/ebf_qi_min_6m5/template.uvoptx
index 8a46158837..49334c73be 100644
--- a/bsp/renesas/ebf_qi_min_6m5/template.uvoptx
+++ b/bsp/renesas/ebf_qi_min_6m5/template.uvoptx
@@ -1,180 +1,213 @@
-
+
- 1.0
- ### uVision Project, (C) Keil Software
-
- *.c
- *.s*; *.src; *.a*
- *.obj; *.o
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- *.txt; *.h; *.inc
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+ ### uVision Project, (C) Keil Software
+
+
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diff --git a/bsp/renesas/ebf_qi_min_6m5/template.uvprojx b/bsp/renesas/ebf_qi_min_6m5/template.uvprojx
index a82a75867f..d17e01fd09 100644
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+++ b/bsp/renesas/ebf_qi_min_6m5/template.uvprojx
@@ -1,407 +1,422 @@
-
+
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-
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- Target 1
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+ ### uVision Project, (C) Keil Software
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+
+
+ Target 1
+ 0x4
+ ARM-ADS
+ 1
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+
+ R7FA6M5BH
+ Renesas
+ Renesas.RA_DFP.4.4.0
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+
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+
+
+
+
+
+
+
diff --git a/bsp/renesas/libraries/HAL_Drivers/SConscript b/bsp/renesas/libraries/HAL_Drivers/SConscript
index 2dc375b527..16a76beb58 100644
--- a/bsp/renesas/libraries/HAL_Drivers/SConscript
+++ b/bsp/renesas/libraries/HAL_Drivers/SConscript
@@ -32,6 +32,9 @@ if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend(['BSP_USING_I2C', 'BSP_USING_HW_I2C']):
src += ['drv_i2c.c']
+if GetDepend(['BSP_USING_I2C', 'BSP_USING_SCI_I2C']):
+ src += ['drv_sci_i2c.c']
+
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c b/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c
new file mode 100644
index 0000000000..9e7763e874
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2023-06-04 vandoul first version
+ */
+
+#include
+#include
+#include "board.h"
+
+#include
+
+#ifdef BSP_USING_SCI_I2C
+
+#define DBG_TAG "drv.sci2c"
+#ifdef DRV_DEBUG
+ #define DBG_LVL DBG_LOG
+#else
+ #define DBG_LVL DBG_INFO
+#endif /* DRV_DEBUG */
+#include
+
+#include
+
+struct ra_sci_i2c_handle
+{
+ struct rt_i2c_bus_device bus;
+ char bus_name[RT_NAME_MAX];
+ const i2c_master_cfg_t *i2c_cfg;
+ void *i2c_ctrl;
+ struct rt_event event;
+};
+
+enum
+{
+ I2C_EVENT_ABORTED = 1UL<p_context;
+ rt_event_send(&ra_sci_i2c->event, 1UL << p_args->event);
+ LOG_D("event:%x", p_args->event);
+ }
+ LOG_D("p_args:%p", p_args);
+}
+
+static rt_err_t validate_i2c_event(struct ra_sci_i2c_handle *handle)
+{
+ rt_uint32_t event = 0;
+ if(RT_EOK != rt_event_recv(&handle->event, I2C_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(10), &event))
+ {
+ return -RT_ETIMEOUT;
+ }
+ if(event != I2C_EVENT_ABORTED)
+ {
+ return RT_EOK;
+ }
+
+ return -RT_ERROR;
+}
+
+static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+ struct rt_i2c_msg msgs[],
+ rt_uint32_t num)
+{
+ rt_size_t i;
+ struct rt_i2c_msg *msg = msgs;
+ RT_ASSERT(bus != RT_NULL);
+ struct ra_sci_i2c_handle *ra_sci_i2c = rt_container_of(bus, struct ra_sci_i2c_handle, bus);
+ i2c_master_ctrl_t *master_ctrl = ra_sci_i2c->i2c_ctrl;
+ fsp_err_t err = FSP_SUCCESS;
+ bool restart = false;
+
+ for (i = 0; i < num; i++)
+ {
+ if (msg[i].flags & RT_I2C_NO_START)
+ {
+ restart = true;
+ }
+ if (msg[i].flags & RT_I2C_ADDR_10BIT)
+ {
+ //LOG_E("10Bit not support");
+ //break;
+ R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT);
+ }
+ else
+ {
+ //master_ctrl->slave = msg[i].addr;
+ R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT);
+ }
+
+ if (msg[i].flags & RT_I2C_RD)
+ {
+ err = R_SCI_I2C_Read(master_ctrl, msg[i].buf, msg[i].len, restart);
+ if (FSP_SUCCESS == err)
+ {
+ /* handle error */
+ if(RT_EOK != validate_i2c_event(ra_sci_i2c))
+ {
+ //LOG_E("POWER_CTL reg I2C read failed,%d", ra_sci_i2c->event);
+ break;
+ }
+ }
+ /* handle error */
+ else
+ {
+ /* Write API returns itself is not successful */
+ //LOG_E("R_IIC_MASTER_Write API failed");
+ break;
+ }
+ }
+ else
+ {
+ err = R_SCI_I2C_Write(master_ctrl, msg[i].buf, msg[i].len, restart);
+ if (FSP_SUCCESS == err)
+ {
+ if(RT_EOK != validate_i2c_event(ra_sci_i2c))
+ {
+ //LOG_E("POWER_CTL reg I2C write failed,%d", ra_sci_i2c->event);
+ break;
+ }
+ }
+ /* handle error */
+ else
+ {
+ /* Write API returns itself is not successful */
+ //LOG_E("R_IIC_MASTER_Write API failed");
+ break;
+ }
+ }
+ }
+ return (rt_ssize_t)i;
+}
+
+static const struct rt_i2c_bus_device_ops ra_i2c_ops =
+{
+ .master_xfer = ra_i2c_mst_xfer,
+ .slave_xfer = RT_NULL,
+ .i2c_bus_control = RT_NULL
+};
+
+int ra_hw_i2c_init(void)
+{
+ fsp_err_t err = FSP_SUCCESS;
+ for(rt_uint32_t i=0; i