diff --git a/bsp/ra6m4-cpk/.settings/standalone.prefs b/bsp/ra6m4-cpk/.settings/standalone.prefs
deleted file mode 100644
index 62c16e929f..0000000000
--- a/bsp/ra6m4-cpk/.settings/standalone.prefs
+++ /dev/null
@@ -1,21 +0,0 @@
-#Tue Dec 14 18:35:25 CST 2021
-com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/all=1957950123,ra/fsp/inc/api/r_ioport_api.h|1390983687,ra/fsp/inc/instances/r_ioport.h|3204787724,ra/fsp/src/r_ioport/r_ioport.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/all=2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2247478812,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2966752275,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1982083345,ra/fsp/src/bsp/mcu/all/bsp_security.c|1390983687,ra/fsp/inc/instances/r_ioport.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|4191472725,ra/fsp/inc/fsp_version.h|496115995,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|905231975,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1868795951,ra/fsp/inc/fsp_features.h|3366593968,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3098075304,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|1957950123,ra/fsp/inc/api/r_ioport_api.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1222394411,ra/fsp/src/bsp/mcu/all/bsp_io.c|3520119047,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2556589544,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3590501432,ra/fsp/src/bsp/mcu/all/bsp_io.h|3581546608,ra/fsp/inc/fsp_common_api.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2006974055,ra/fsp/inc/api/bsp_api.h|3819230577,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2812024316,ra/fsp/src/bsp/mcu/all/bsp_common.h|3131094294,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/libraries=
-com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#R7FA6M4AF3CFB\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/all=2491522803,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|637879414,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|377628369,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2686445441,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|546157604,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|4005730526,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1562896660,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|4231934849,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3589068132,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1078551279,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3021372151,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3602366610,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2748964184,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3779323067,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1536854638,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|206980015,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3442821435,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2024281644,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/all=2349328507,ra/fsp/src/r_sci_uart/r_sci_uart.c|853178775,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|1672784957,ra/fsp/inc/instances/r_sci_uart.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/all=3852442662,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3571093944,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/libraries=
-com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.813326093=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/all=3559227370,ra/board/ra6m4_cpk/board_init.c|3843040667,ra/board/ra6m4_cpk/board_leds.h|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|2967196421,ra/board/ra6m4_cpk/board_init.h|3938710240,ra/board/ra6m4_cpk/board_leds.c|3343992478,ra/board/ra6m4_cpk/board.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/libraries=
diff --git a/bsp/ra6m4-cpk/docs/picture/fsp_version.png b/bsp/ra6m4-cpk/docs/picture/fsp_version.png
deleted file mode 100644
index 4dbaca0122..0000000000
Binary files a/bsp/ra6m4-cpk/docs/picture/fsp_version.png and /dev/null differ
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
deleted file mode 100644
index 4b27870753..0000000000
--- a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_PIN_CFG_H_
-#define BSP_PIN_CFG_H_
-#include "r_ioport.h"
-#define ARDUINO_AN00 (IOPORT_PORT_00_PIN_00)
-#define ARDUINO_AN01 (IOPORT_PORT_00_PIN_01)
-#define ARDUINO_AN02 (IOPORT_PORT_00_PIN_02)
-#define ARDUINO_AN03 (IOPORT_PORT_00_PIN_03)
-#define ARDUINO_AN04 (IOPORT_PORT_00_PIN_04)
-#define ARDUINO_AN05 (IOPORT_PORT_00_PIN_05)
-#define PMODA_IRQ11 (IOPORT_PORT_00_PIN_06)
-#define J4_PIN23 (IOPORT_PORT_00_PIN_07)
-#define PMODA_IO1 (IOPORT_PORT_00_PIN_08)
-#define J4_PIN26 (IOPORT_PORT_00_PIN_09)
-#define PMODA_IO2 (IOPORT_PORT_00_PIN_14)
-#define PMODA_IO3 (IOPORT_PORT_00_PIN_15)
-#define J1_PIN1 (IOPORT_PORT_01_PIN_00)
-#define J2_PIN4 (IOPORT_PORT_01_PIN_01)
-#define J2_PIN6 (IOPORT_PORT_01_PIN_02)
-#define J1_PIN29 (IOPORT_PORT_01_PIN_03)
-#define J3_PIN39 (IOPORT_PORT_01_PIN_04)
-#define SW1 (IOPORT_PORT_01_PIN_05)
-#define LED3 (IOPORT_PORT_01_PIN_06)
-#define J3_PIN37 (IOPORT_PORT_01_PIN_07)
-#define DEBUG_SWDIO_TMS (IOPORT_PORT_01_PIN_08)
-#define DEBUG_TDO (IOPORT_PORT_01_PIN_09)
-#define DEBUG_TDI (IOPORT_PORT_01_PIN_10)
-#define J1_PIN33 (IOPORT_PORT_01_PIN_11)
-#define J3_PIN15 (IOPORT_PORT_01_PIN_12)
-#define J3_PIN16 (IOPORT_PORT_01_PIN_13)
-#define J3_PIN17 (IOPORT_PORT_01_PIN_14)
-#define J3_PIN18 (IOPORT_PORT_01_PIN_15)
-#define NMI (IOPORT_PORT_02_PIN_00)
-#define MD (IOPORT_PORT_02_PIN_01)
-#define PMODA_MISO_RXD9 (IOPORT_PORT_02_PIN_02)
-#define PMODA_MOSI_TXD9 (IOPORT_PORT_02_PIN_03)
-#define PMODA_RSPCK (IOPORT_PORT_02_PIN_04)
-#define PMODA_SSL_CTS9 (IOPORT_PORT_02_PIN_05)
-#define J1_PIN3 (IOPORT_PORT_02_PIN_06)
-#define J1_PIN8 (IOPORT_PORT_02_PIN_07)
-#define J1_PIN32 (IOPORT_PORT_02_PIN_08)
-#define J1_PIN30 (IOPORT_PORT_02_PIN_09)
-#define J1_PIN28 (IOPORT_PORT_02_PIN_10)
-#define J1_PIN22 (IOPORT_PORT_02_PIN_11)
-#define EXTAL (IOPORT_PORT_02_PIN_12)
-#define XTAL (IOPORT_PORT_02_PIN_13)
-#define J1_PIN20 (IOPORT_PORT_02_PIN_14)
-#define DEBUG_SWDCLK_TCK (IOPORT_PORT_03_PIN_00)
-#define J1_PIN11 (IOPORT_PORT_03_PIN_01)
-#define J3_PIN14 (IOPORT_PORT_03_PIN_02)
-#define J3_PIN13 (IOPORT_PORT_03_PIN_03)
-#define J3_PIN12 (IOPORT_PORT_03_PIN_04)
-#define J3_PIN11 (IOPORT_PORT_03_PIN_05)
-#define J3_PIN10 (IOPORT_PORT_03_PIN_06)
-#define J3_PIN9 (IOPORT_PORT_03_PIN_07)
-#define J3_PIN8 (IOPORT_PORT_03_PIN_08)
-#define J3_PIN7 (IOPORT_PORT_03_PIN_09)
-#define J3_PIN6 (IOPORT_PORT_03_PIN_10)
-#define J3_PIN5 (IOPORT_PORT_03_PIN_11)
-#define J3_PIN4 (IOPORT_PORT_03_PIN_12)
-#define J1_PIN14 (IOPORT_PORT_03_PIN_13)
-#define J4_PIN13 (IOPORT_PORT_04_PIN_00)
-#define J4_PIN11 (IOPORT_PORT_04_PIN_01)
-#define J1_PIN27 (IOPORT_PORT_04_PIN_02)
-#define J4_PIN2 (IOPORT_PORT_04_PIN_03)
-#define J4_PIN4 (IOPORT_PORT_04_PIN_04)
-#define J4_PIN6 (IOPORT_PORT_04_PIN_05)
-#define J4_PIN8 (IOPORT_PORT_04_PIN_06)
-#define USB_VBUS_DETECT (IOPORT_PORT_04_PIN_07)
-#define J2_PIN16 (IOPORT_PORT_04_PIN_08)
-#define J2_PIN18 (IOPORT_PORT_04_PIN_09)
-#define PMODB_MISO_RXD0 (IOPORT_PORT_04_PIN_10)
-#define PMODB_MOSI_TXD0 (IOPORT_PORT_04_PIN_11)
-#define PMODB_RSPCK (IOPORT_PORT_04_PIN_12)
-#define PMODB_SSL_CTS0 (IOPORT_PORT_04_PIN_13)
-#define ARDUINO_RST (IOPORT_PORT_04_PIN_14)
-#define PMODB_IO1 (IOPORT_PORT_04_PIN_15)
-#define USB_VBUS_EN (IOPORT_PORT_05_PIN_00)
-#define USB_OC (IOPORT_PORT_05_PIN_01)
-#define J4_PIN16 (IOPORT_PORT_05_PIN_02)
-#define PMODB_IO2 (IOPORT_PORT_05_PIN_03)
-#define PMODB_IO3 (IOPORT_PORT_05_PIN_04)
-#define DLS_IRQ14 (IOPORT_PORT_05_PIN_05)
-#define PMODB_IRQ15 (IOPORT_PORT_05_PIN_06)
-#define J4_PIN24 (IOPORT_PORT_05_PIN_07)
-#define DLS_SDA (IOPORT_PORT_05_PIN_11)
-#define DLS_SCL (IOPORT_PORT_05_PIN_12)
-#define J1_PIN23 (IOPORT_PORT_06_PIN_00)
-#define J1_PIN19 (IOPORT_PORT_06_PIN_01)
-#define J1_PIN21 (IOPORT_PORT_06_PIN_02)
-#define J1_PIN25 (IOPORT_PORT_06_PIN_03)
-#define J3_PIN36 (IOPORT_PORT_06_PIN_04)
-#define J3_PIN35 (IOPORT_PORT_06_PIN_05)
-#define J3_PIN19 (IOPORT_PORT_06_PIN_08)
-#define J3_PIN20 (IOPORT_PORT_06_PIN_09)
-#define J3_PIN21 (IOPORT_PORT_06_PIN_10)
-#define ARDUINO_GPIO_CLK (IOPORT_PORT_06_PIN_11)
-#define J3_PIN23 (IOPORT_PORT_06_PIN_12)
-#define ARDUINO_TXD (IOPORT_PORT_06_PIN_13)
-#define ARDUINO_RXD (IOPORT_PORT_06_PIN_14)
-#define J4_PIN9 (IOPORT_PORT_07_PIN_00)
-#define J4_PIN7 (IOPORT_PORT_07_PIN_01)
-#define J4_PIN5 (IOPORT_PORT_07_PIN_02)
-#define J4_PIN3 (IOPORT_PORT_07_PIN_03)
-#define J4_PIN1 (IOPORT_PORT_07_PIN_04)
-#define J2_PIN39 (IOPORT_PORT_07_PIN_05)
-#define J2_PIN7 (IOPORT_PORT_07_PIN_08)
-#define J2_PIN11 (IOPORT_PORT_07_PIN_09)
-#define J2_PIN13 (IOPORT_PORT_07_PIN_10)
-#define J2_PIN15 (IOPORT_PORT_07_PIN_11)
-#define ARDUINO_GPIO_PWM (IOPORT_PORT_07_PIN_12)
-#define ARDUINO_GPIO (IOPORT_PORT_07_PIN_13)
-extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M4 CPK */
-
-void BSP_PinConfigSecurityInit();
-#endif /* BSP_PIN_CFG_H_ */
diff --git a/bsp/ra6m4-cpk/.config b/bsp/renesas/ra6m4-cpk/.config
similarity index 100%
rename from bsp/ra6m4-cpk/.config
rename to bsp/renesas/ra6m4-cpk/.config
diff --git a/bsp/ra6m4-cpk/.gitignore b/bsp/renesas/ra6m4-cpk/.gitignore
similarity index 100%
rename from bsp/ra6m4-cpk/.gitignore
rename to bsp/renesas/ra6m4-cpk/.gitignore
diff --git a/bsp/ra6m4-cpk/.ignore_format.yml b/bsp/renesas/ra6m4-cpk/.ignore_format.yml
similarity index 100%
rename from bsp/ra6m4-cpk/.ignore_format.yml
rename to bsp/renesas/ra6m4-cpk/.ignore_format.yml
diff --git a/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs b/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs
new file mode 100644
index 0000000000..e857c7f65b
--- /dev/null
+++ b/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs
@@ -0,0 +1,21 @@
+#Thu Jan 13 17:43:26 CST 2022
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|546480625,ra/fsp/inc/fsp_common_api.h|3297195641,ra/fsp/inc/fsp_version.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1728953905,ra/fsp/inc/fsp_features.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2425160085,ra/fsp/inc/api/bsp_api.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.201575186=false
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/all=3938710240,ra/board/ra6m4_cpk/board_leds.c|2967196421,ra/board/ra6m4_cpk/board_init.h|3343992478,ra/board/ra6m4_cpk/board.h|3559227370,ra/board/ra6m4_cpk/board_init.c|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|1768800601,ra/board/ra6m4_cpk/board_leds.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=1906465970,ra/fsp/inc/api/r_external_irq_api.h|2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#R7FA6M4AF3CFB\#\#3.5.0/libraries=
diff --git a/bsp/ra6m4-cpk/Kconfig b/bsp/renesas/ra6m4-cpk/Kconfig
similarity index 100%
rename from bsp/ra6m4-cpk/Kconfig
rename to bsp/renesas/ra6m4-cpk/Kconfig
diff --git a/bsp/ra6m4-cpk/R7FA6M4AF3CFB.pincfg b/bsp/renesas/ra6m4-cpk/R7FA6M4AF3CFB.pincfg
similarity index 100%
rename from bsp/ra6m4-cpk/R7FA6M4AF3CFB.pincfg
rename to bsp/renesas/ra6m4-cpk/R7FA6M4AF3CFB.pincfg
diff --git a/bsp/ra6m4-cpk/README.md b/bsp/renesas/ra6m4-cpk/README.md
similarity index 85%
rename from bsp/ra6m4-cpk/README.md
rename to bsp/renesas/ra6m4-cpk/README.md
index a072f8667a..f81f105be6 100644
--- a/bsp/ra6m4-cpk/README.md
+++ b/bsp/renesas/ra6m4-cpk/README.md
@@ -44,8 +44,10 @@
| CAN | 支持 | |
| 持续更新中... | | |
| **外接外设** | **支持情况** | **备注** |
-| WiFi | 支持 | [RW007 WiFi 网络模块](https://github.com/RT-Thread-packages/rw007) |
+| WiFi 模块 | 支持 | [RW007 WiFi 网络模块](https://github.com/RT-Thread-packages/rw007) |
| 温湿度传感器 | 支持 | [HS300x 温湿度模块](https://github.com/Guozhanxin/hs300x) |
+| 室内空气质量传感器 | 支持 | [zmod4410 室内空气质量模块](https://github.com/ShermanShao/zmod4410) |
+| 光线传感器 | 支持 | [isl29035光线传感器模块](https://github.com/ShermanShao/isl29035) |
## 使用说明
@@ -65,7 +67,7 @@
**硬件连接**
-使用 USB 数据线连接开发板到 PC。使用 USB 转串口工具连接 P613(TXD)、P614(RXD)。
+使用 USB 数据线连接开发板到 PC,使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART7:P613(TXD)、P614(RXD)。
**编译下载**
@@ -153,16 +155,17 @@ void hal_entry(void)
需要修改瑞萨的 BSP 外设配置或添加新的外设端口,需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
-1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp),建议使用 FSP 3.1.0
-2. 下载安装完成后,需要添加 CPK-RA6M4 开发板的[官方板级支持包](https://www2.renesas.cn/document/sws/1527176?language=zh&r=1527191)
-3. 如何将 BSP 配置包添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
+1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp),请使用 FSP 3.5.0 版本
+2. 下载安装完成后,需要添加 CPK-RA6M4 开发板的官方板级支持包
+> 打开[ CPK-RA6M4 开发板详情页](https://www2.renesas.cn/jp/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra6m4-evaluation-board),在**“下载”**列表中找到 **”CPK-RA6M4板级支持包“**,点击链接即可下载
+3. 如何将 **”CPK-RA6M4板级支持包“**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
4. 请查看文档:[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
-此 BSP 默认只开启了 串口7 的功能,如果需使用更多高级功能例如组件、软件包等,需要利用 ENV 工具进行配置。
+此 BSP 默认只开启了 UART7 的功能,如果需使用更多高级功能例如组件、软件包等,需要利用 ENV 工具进行配置。
步骤如下:
1. 在 bsp 下打开 env 工具。
diff --git a/bsp/renesas/ra6m4-cpk/RTE/_Target_1/RTE_Components.h b/bsp/renesas/ra6m4-cpk/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 0000000000..d5d79fdd80
--- /dev/null
+++ b/bsp/renesas/ra6m4-cpk/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,15 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'project'
+ * Target: 'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/bsp/ra6m4-cpk/SConscript b/bsp/renesas/ra6m4-cpk/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/SConscript
rename to bsp/renesas/ra6m4-cpk/SConscript
diff --git a/bsp/ra6m4-cpk/SConstruct b/bsp/renesas/ra6m4-cpk/SConstruct
similarity index 94%
rename from bsp/ra6m4-cpk/SConstruct
rename to bsp/renesas/ra6m4-cpk/SConstruct
index ac79195833..e75d75371b 100644
--- a/bsp/ra6m4-cpk/SConstruct
+++ b/bsp/renesas/ra6m4-cpk/SConstruct
@@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
- RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
diff --git a/bsp/ra6m4-cpk/buildinfo.gpdsc b/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc
similarity index 98%
rename from bsp/ra6m4-cpk/buildinfo.gpdsc
rename to bsp/renesas/ra6m4-cpk/buildinfo.gpdsc
index ee8476ee88..90f1f75496 100644
--- a/bsp/ra6m4-cpk/buildinfo.gpdsc
+++ b/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc
@@ -74,6 +74,7 @@
+
@@ -108,11 +109,11 @@
+
-
diff --git a/bsp/ra6m4-cpk/configuration.xml b/bsp/renesas/ra6m4-cpk/configuration.xml
similarity index 93%
rename from bsp/ra6m4-cpk/configuration.xml
rename to bsp/renesas/ra6m4-cpk/configuration.xml
index a20ca08969..c239e5f470 100644
--- a/bsp/ra6m4-cpk/configuration.xml
+++ b/bsp/renesas/ra6m4-cpk/configuration.xml
@@ -1,5 +1,5 @@
-
+
@@ -8,7 +8,7 @@
-
+
@@ -71,6 +71,8 @@
+
+
@@ -83,6 +85,7 @@
+
@@ -131,41 +134,41 @@
-
+
Board Support Package Common Files
- Renesas.RA.3.1.0.pack
+ Renesas.RA.3.5.0.pack
-
+
I/O Port
- Renesas.RA.3.1.0.pack
+ Renesas.RA.3.5.0.pack
-
+
Arm CMSIS Version 5 - Core (M)
- Arm.CMSIS5.5.7.0+fsp.3.1.0.pack
+ Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack
-
+
RA6M4-CPK Board Support Files
- Renesas.RA_board_ra6m4_cpk.3.1.0.pack
+ Renesas.RA_board_ra6m4_cpk.3.5.0.pack
-
+
Board support package for R7FA6M4AF3CFB
- Renesas.RA_mcu_ra6m4.3.1.0.pack
+ Renesas.RA_mcu_ra6m4.3.5.0.pack
-
+
Board support package for RA6M4
- Renesas.RA_mcu_ra6m4.3.1.0.pack
+ Renesas.RA_mcu_ra6m4.3.5.0.pack
-
+
Board support package for RA6M4 - FSP Data
- Renesas.RA_mcu_ra6m4.3.1.0.pack
+ Renesas.RA_mcu_ra6m4.3.5.0.pack
-
+
SCI UART
- Renesas.RA.3.1.0.pack
+ Renesas.RA.3.5.0.pack
-
+
External Interrupt
- Renesas.RA.3.1.0.pack
+ Renesas.RA.3.5.0.pack
@@ -177,8 +180,13 @@
+
+
+
+
+
-
+
@@ -200,7 +208,7 @@
-
+
@@ -211,8 +219,8 @@
-
-
+
+
@@ -337,19 +345,16 @@
+
+
+
-
-
-
-
-
-
@@ -363,17 +368,17 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -381,8 +386,8 @@
-
-
+
+
diff --git a/bsp/ra6m4-cpk/docs/picture/1635909864954.png b/bsp/renesas/ra6m4-cpk/docs/picture/1635909864954.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/1635909864954.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/1635909864954.png
diff --git a/bsp/ra6m4-cpk/docs/picture/1635929089445.png b/bsp/renesas/ra6m4-cpk/docs/picture/1635929089445.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/1635929089445.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/1635929089445.png
diff --git a/bsp/ra6m4-cpk/docs/picture/adc_config.png b/bsp/renesas/ra6m4-cpk/docs/picture/adc_config.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/adc_config.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/adc_config.png
diff --git a/bsp/ra6m4-cpk/docs/picture/adc_config1.png b/bsp/renesas/ra6m4-cpk/docs/picture/adc_config1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/adc_config1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/adc_config1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/adc_dac.png b/bsp/renesas/ra6m4-cpk/docs/picture/adc_dac.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/adc_dac.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/adc_dac.png
diff --git a/bsp/ra6m4-cpk/docs/picture/add_flash.png b/bsp/renesas/ra6m4-cpk/docs/picture/add_flash.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/add_flash.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/add_flash.png
diff --git a/bsp/ra6m4-cpk/docs/picture/add_gpt1.png b/bsp/renesas/ra6m4-cpk/docs/picture/add_gpt1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/add_gpt1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/add_gpt1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/add_gpt2.png b/bsp/renesas/ra6m4-cpk/docs/picture/add_gpt2.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/add_gpt2.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/add_gpt2.png
diff --git a/bsp/ra6m4-cpk/docs/picture/add_gpt3.png b/bsp/renesas/ra6m4-cpk/docs/picture/add_gpt3.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/add_gpt3.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/add_gpt3.png
diff --git a/bsp/ra6m4-cpk/docs/picture/can.png b/bsp/renesas/ra6m4-cpk/docs/picture/can.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/can.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/can.png
diff --git a/bsp/ra6m4-cpk/docs/picture/can_callback.png b/bsp/renesas/ra6m4-cpk/docs/picture/can_callback.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/can_callback.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/can_callback.png
diff --git a/bsp/ra6m4-cpk/docs/picture/can_menuconfig.png b/bsp/renesas/ra6m4-cpk/docs/picture/can_menuconfig.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/can_menuconfig.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/can_menuconfig.png
diff --git a/bsp/ra6m4-cpk/docs/picture/config_flash.png b/bsp/renesas/ra6m4-cpk/docs/picture/config_flash.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/config_flash.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/config_flash.png
diff --git a/bsp/ra6m4-cpk/docs/picture/config_irq4.png b/bsp/renesas/ra6m4-cpk/docs/picture/config_irq4.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/config_irq4.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/config_irq4.png
diff --git a/bsp/ra6m4-cpk/docs/picture/cpk-ra6m4.png b/bsp/renesas/ra6m4-cpk/docs/picture/cpk-ra6m4.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/cpk-ra6m4.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/cpk-ra6m4.png
diff --git a/bsp/ra6m4-cpk/docs/picture/customize.png b/bsp/renesas/ra6m4-cpk/docs/picture/customize.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/customize.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/customize.png
diff --git a/bsp/ra6m4-cpk/docs/picture/dac_config0.png b/bsp/renesas/ra6m4-cpk/docs/picture/dac_config0.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/dac_config0.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/dac_config0.png
diff --git a/bsp/ra6m4-cpk/docs/picture/dac_config1.png b/bsp/renesas/ra6m4-cpk/docs/picture/dac_config1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/dac_config1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/dac_config1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/dac_config2.png b/bsp/renesas/ra6m4-cpk/docs/picture/dac_config2.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/dac_config2.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/dac_config2.png
diff --git a/bsp/ra6m4-cpk/docs/picture/dmac_config.png b/bsp/renesas/ra6m4-cpk/docs/picture/dmac_config.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/dmac_config.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/dmac_config.png
diff --git a/bsp/ra6m4-cpk/docs/picture/dmac_int.png b/bsp/renesas/ra6m4-cpk/docs/picture/dmac_int.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/dmac_int.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/dmac_int.png
diff --git a/bsp/ra6m4-cpk/docs/picture/drv_rw007.png b/bsp/renesas/ra6m4-cpk/docs/picture/drv_rw007.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/drv_rw007.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/drv_rw007.png
diff --git a/bsp/ra6m4-cpk/docs/picture/flash_menuconfig.png b/bsp/renesas/ra6m4-cpk/docs/picture/flash_menuconfig.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/flash_menuconfig.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/flash_menuconfig.png
diff --git a/bsp/renesas/ra6m4-cpk/docs/picture/fsp_version.png b/bsp/renesas/ra6m4-cpk/docs/picture/fsp_version.png
new file mode 100644
index 0000000000..4bcdffff4f
Binary files /dev/null and b/bsp/renesas/ra6m4-cpk/docs/picture/fsp_version.png differ
diff --git a/bsp/ra6m4-cpk/docs/picture/gpio.png b/bsp/renesas/ra6m4-cpk/docs/picture/gpio.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/gpio.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/gpio.png
diff --git a/bsp/ra6m4-cpk/docs/picture/gpio_irq.png b/bsp/renesas/ra6m4-cpk/docs/picture/gpio_irq.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/gpio_irq.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/gpio_irq.png
diff --git a/bsp/ra6m4-cpk/docs/picture/icu_stack.png b/bsp/renesas/ra6m4-cpk/docs/picture/icu_stack.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/icu_stack.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/icu_stack.png
diff --git a/bsp/ra6m4-cpk/docs/picture/import_changes.png b/bsp/renesas/ra6m4-cpk/docs/picture/import_changes.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/import_changes.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/import_changes.png
diff --git a/bsp/ra6m4-cpk/docs/picture/irq0.png b/bsp/renesas/ra6m4-cpk/docs/picture/irq0.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/irq0.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/irq0.png
diff --git a/bsp/ra6m4-cpk/docs/picture/irq1.png b/bsp/renesas/ra6m4-cpk/docs/picture/irq1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/irq1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/irq1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/jflash.png b/bsp/renesas/ra6m4-cpk/docs/picture/jflash.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/jflash.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/jflash.png
diff --git a/bsp/ra6m4-cpk/docs/picture/jflash1.png b/bsp/renesas/ra6m4-cpk/docs/picture/jflash1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/jflash1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/jflash1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/jflash2.png b/bsp/renesas/ra6m4-cpk/docs/picture/jflash2.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/jflash2.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/jflash2.png
diff --git a/bsp/ra6m4-cpk/docs/picture/jflash3.png b/bsp/renesas/ra6m4-cpk/docs/picture/jflash3.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/jflash3.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/jflash3.png
diff --git a/bsp/ra6m4-cpk/docs/picture/openrasc.png b/bsp/renesas/ra6m4-cpk/docs/picture/openrasc.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/openrasc.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/openrasc.png
diff --git a/bsp/ra6m4-cpk/docs/picture/p105.png b/bsp/renesas/ra6m4-cpk/docs/picture/p105.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/p105.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/p105.png
diff --git a/bsp/ra6m4-cpk/docs/picture/pwm_env.png b/bsp/renesas/ra6m4-cpk/docs/picture/pwm_env.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/pwm_env.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/pwm_env.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rascuart.png b/bsp/renesas/ra6m4-cpk/docs/picture/rascuart.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rascuart.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rascuart.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rascuart1.png b/bsp/renesas/ra6m4-cpk/docs/picture/rascuart1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rascuart1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rascuart1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/readme_faq1.png b/bsp/renesas/ra6m4-cpk/docs/picture/readme_faq1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/readme_faq1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/readme_faq1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rtc.png b/bsp/renesas/ra6m4-cpk/docs/picture/rtc.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rtc.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rtc.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rtc_config.png b/bsp/renesas/ra6m4-cpk/docs/picture/rtc_config.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rtc_config.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rtc_config.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rtc_env.png b/bsp/renesas/ra6m4-cpk/docs/picture/rtc_env.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rtc_env.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rtc_env.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_int.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_int.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_int.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_int.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_mdk.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_mdk.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_mdk.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_mdk.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_mempool.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_mempool.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_mempool.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_mempool.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_netdev.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_netdev.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_netdev.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_netdev.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_ping.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_ping.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_ping.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_ping.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_pkg.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_pkg.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_pkg.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_pkg.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_reset.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_reset.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_reset.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_reset.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_spi.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_spi.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_spi.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_spi.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_spicfg.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_spicfg.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_spicfg.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_spicfg.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_test.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_test.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_test.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_test.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_wifijoin.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_wifijoin.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_wifijoin.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_wifijoin.png
diff --git a/bsp/ra6m4-cpk/docs/picture/rw007_wlan.png b/bsp/renesas/ra6m4-cpk/docs/picture/rw007_wlan.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/rw007_wlan.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/rw007_wlan.png
diff --git a/bsp/ra6m4-cpk/docs/picture/sdhi_config.png b/bsp/renesas/ra6m4-cpk/docs/picture/sdhi_config.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/sdhi_config.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/sdhi_config.png
diff --git a/bsp/ra6m4-cpk/docs/picture/sdhi_config1.png b/bsp/renesas/ra6m4-cpk/docs/picture/sdhi_config1.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/sdhi_config1.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/sdhi_config1.png
diff --git a/bsp/ra6m4-cpk/docs/picture/sdhi_env.png b/bsp/renesas/ra6m4-cpk/docs/picture/sdhi_env.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/sdhi_env.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/sdhi_env.png
diff --git a/bsp/ra6m4-cpk/docs/picture/spi.png b/bsp/renesas/ra6m4-cpk/docs/picture/spi.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/spi.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/spi.png
diff --git a/bsp/ra6m4-cpk/docs/picture/spi_add.png b/bsp/renesas/ra6m4-cpk/docs/picture/spi_add.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/spi_add.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/spi_add.png
diff --git a/bsp/ra6m4-cpk/docs/picture/spi_env.png b/bsp/renesas/ra6m4-cpk/docs/picture/spi_env.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/spi_env.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/spi_env.png
diff --git a/bsp/ra6m4-cpk/docs/picture/spi_pin.png b/bsp/renesas/ra6m4-cpk/docs/picture/spi_pin.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/spi_pin.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/spi_pin.png
diff --git a/bsp/ra6m4-cpk/docs/picture/wdt.png b/bsp/renesas/ra6m4-cpk/docs/picture/wdt.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/wdt.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/wdt.png
diff --git a/bsp/ra6m4-cpk/docs/picture/wdt_config.png b/bsp/renesas/ra6m4-cpk/docs/picture/wdt_config.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/wdt_config.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/wdt_config.png
diff --git a/bsp/ra6m4-cpk/docs/picture/wdt_env.png b/bsp/renesas/ra6m4-cpk/docs/picture/wdt_env.png
similarity index 100%
rename from bsp/ra6m4-cpk/docs/picture/wdt_env.png
rename to bsp/renesas/ra6m4-cpk/docs/picture/wdt_env.png
diff --git a/bsp/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md b/bsp/renesas/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
similarity index 95%
rename from bsp/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
rename to bsp/renesas/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
index 7ca6129444..41c91fae80 100644
--- a/bsp/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
+++ b/bsp/renesas/ra6m4-cpk/docs/使用瑞萨FSP配置工具.md
@@ -4,14 +4,14 @@
1. 打开 MDK,选择 “Tools -> Customize Tools Menu…”
2. 点击 “new” 图标,添加一条自定义命令: RA Smart Configurator
-3. Command 输入工具的安装路径, 点击“…”找到安装路径下的“rasc.exe”文件并选中 (setup_fsp_v3_1_0_rasc_ 安装目录下)
+3. Command 输入工具的安装路径, 点击“**…**”找到安装路径下的“rasc.exe”文件并选中 (rasc 安装目录下)
4. Initial Folder 输入参数: $P
5. Arguments 输入参数: --device $D --compiler ARMv6 configuration.xml
-6. 点击 OK 保存命令“Tools -> RA smart Configurator”
+6. 点击 OK 保存命令
![img](picture/customize.png)
-7. 点击添加的命令打开配置工具:RA Smart Config
+7. 点击添加的命令 “Tools -> RA smart Configurator”,**打开配置工具**:RA Smart Config
![image.png](picture/openrasc.png)
@@ -24,13 +24,13 @@
> PS:以上相关操作也可以在 FSP 的说明文档中找到。
>
-> 文档路径(本地):在 FSP 的安装目录下 .\fsp_documentation\v3.1.0\fsp_user_manual_v3.1.0\index.html
+> 文档路径(本地):在 FSP 的安装目录下 .\fsp_documentation\v3.5.0\fsp_user_manual_v3.5.0\index.html
>
> 文档路径(官网):https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document
### FSP 版本选择
-此 BSP 使用 **FSP 3.1.0** 版本为基础制作,优先推荐使用 FSP 3.1.0 版本进行配置修改。
+此 BSP 已更新 **FSP 3.5.0** 版本的支持,请使用 **FSP 3.5.0** 版本进行配置修改。下文中部分操作截图使用的是 FSP 3.1.0 版本,仅供参考。
**使用 RASC 前请务必检查 FSP version 、Board、Device 配置项是否正确。**
diff --git a/bsp/ra6m4-cpk/drivers/Kconfig b/bsp/renesas/ra6m4-cpk/drivers/Kconfig
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/Kconfig
rename to bsp/renesas/ra6m4-cpk/drivers/Kconfig
diff --git a/bsp/ra6m4-cpk/drivers/SConscript b/bsp/renesas/ra6m4-cpk/drivers/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/SConscript
rename to bsp/renesas/ra6m4-cpk/drivers/SConscript
diff --git a/bsp/ra6m4-cpk/drivers/board.h b/bsp/renesas/ra6m4-cpk/drivers/board.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/board.h
rename to bsp/renesas/ra6m4-cpk/drivers/board.h
diff --git a/bsp/ra6m4-cpk/drivers/config/drv_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/drv_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/drv_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/drv_config.h
diff --git a/bsp/ra6m4-cpk/drivers/config/ra6m4/adc_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/adc_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/ra6m4/adc_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/adc_config.h
diff --git a/bsp/ra6m4-cpk/drivers/config/ra6m4/can_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/can_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/ra6m4/can_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/can_config.h
diff --git a/bsp/ra6m4-cpk/drivers/config/ra6m4/dac_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/dac_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/ra6m4/dac_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/dac_config.h
diff --git a/bsp/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h
diff --git a/bsp/ra6m4-cpk/drivers/config/ra6m4/uart_config.h b/bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/uart_config.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/config/ra6m4/uart_config.h
rename to bsp/renesas/ra6m4-cpk/drivers/config/ra6m4/uart_config.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_adc.c b/bsp/renesas/ra6m4-cpk/drivers/drv_adc.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_adc.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_adc.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_can.c b/bsp/renesas/ra6m4-cpk/drivers/drv_can.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_can.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_can.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_can.h b/bsp/renesas/ra6m4-cpk/drivers/drv_can.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_can.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_can.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_common.c b/bsp/renesas/ra6m4-cpk/drivers/drv_common.c
similarity index 64%
rename from bsp/ra6m4-cpk/drivers/drv_common.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_common.c
index aeb5017485..4dadc8d4cb 100644
--- a/bsp/ra6m4-cpk/drivers/drv_common.c
+++ b/bsp/renesas/ra6m4-cpk/drivers/drv_common.c
@@ -140,3 +140,46 @@ RT_WEAK void rt_hw_board_init()
#endif
}
+FSP_CPP_HEADER
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+FSP_CPP_FOOTER
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process. This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in] event Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+ if (BSP_WARM_START_RESET == event)
+ {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+ /* Enable reading from data flash. */
+ R_FACI_LP->DFLCTL = 1U;
+
+ /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+ * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+ }
+
+ if (BSP_WARM_START_POST_C == event)
+ {
+ /* C runtime environment and system clocks are setup. */
+
+ /* Configure pins. */
+ R_IOPORT_Open(&g_ioport_ctrl, g_ioport.p_cfg);
+ }
+}
+
+#if BSP_TZ_SECURE_BUILD
+
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ();
+
+/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ()
+{
+
+}
+#endif
\ No newline at end of file
diff --git a/bsp/ra6m4-cpk/drivers/drv_common.h b/bsp/renesas/ra6m4-cpk/drivers/drv_common.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_common.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_common.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_dac.c b/bsp/renesas/ra6m4-cpk/drivers/drv_dac.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_dac.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_dac.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_flash.c b/bsp/renesas/ra6m4-cpk/drivers/drv_flash.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_flash.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_flash.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_flash.h b/bsp/renesas/ra6m4-cpk/drivers/drv_flash.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_flash.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_flash.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_gpio.c b/bsp/renesas/ra6m4-cpk/drivers/drv_gpio.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_gpio.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_gpio.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_gpio.h b/bsp/renesas/ra6m4-cpk/drivers/drv_gpio.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_gpio.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_gpio.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_pwm.c b/bsp/renesas/ra6m4-cpk/drivers/drv_pwm.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_pwm.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_pwm.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_pwm.h b/bsp/renesas/ra6m4-cpk/drivers/drv_pwm.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_pwm.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_pwm.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_rtc.c b/bsp/renesas/ra6m4-cpk/drivers/drv_rtc.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_rtc.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_rtc.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_soft_i2c.c b/bsp/renesas/ra6m4-cpk/drivers/drv_soft_i2c.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_soft_i2c.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_soft_i2c.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_soft_i2c.h b/bsp/renesas/ra6m4-cpk/drivers/drv_soft_i2c.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_soft_i2c.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_soft_i2c.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_spi.c b/bsp/renesas/ra6m4-cpk/drivers/drv_spi.c
similarity index 92%
rename from bsp/ra6m4-cpk/drivers/drv_spi.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_spi.c
index 104134f7a6..c57b7048f6 100644
--- a/bsp/ra6m4-cpk/drivers/drv_spi.c
+++ b/bsp/renesas/ra6m4-cpk/drivers/drv_spi.c
@@ -83,6 +83,19 @@ static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_M
return -RT_EINVAL;
}
+static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
+{
+ spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
+ if(data_width == 1)
+ bit_width = SPI_BIT_WIDTH_8_BITS;
+ else if(data_width == 2)
+ bit_width = SPI_BIT_WIDTH_16_BITS;
+ else if(data_width == 4)
+ bit_width = SPI_BIT_WIDTH_32_BITS;
+
+ return bit_width;
+}
+
static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
@@ -92,8 +105,9 @@ static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
+ spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< send msessage */
- err = R_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, spi_dev->rt_spi_cfg_t->data_width);
+ err = R_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write failed.", spi_dev->ra_spi_handle_t->bus_name);
@@ -113,8 +127,9 @@ static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, co
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
+ spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< receive message */
- err = R_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, spi_dev->rt_spi_cfg_t->data_width);
+ err = R_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("\n%s write failed.\n", spi_dev->ra_spi_handle_t->bus_name);
@@ -133,8 +148,9 @@ static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_sp
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
+ spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< write and receive message */
- err = R_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, spi_dev->rt_spi_cfg_t->data_width);
+ err = R_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write and read failed.", spi_dev->ra_spi_handle_t->bus_name);
diff --git a/bsp/ra6m4-cpk/drivers/drv_spi.h b/bsp/renesas/ra6m4-cpk/drivers/drv_spi.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_spi.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_spi.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_usart_v2.c b/bsp/renesas/ra6m4-cpk/drivers/drv_usart_v2.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_usart_v2.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_usart_v2.c
diff --git a/bsp/ra6m4-cpk/drivers/drv_usart_v2.h b/bsp/renesas/ra6m4-cpk/drivers/drv_usart_v2.h
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_usart_v2.h
rename to bsp/renesas/ra6m4-cpk/drivers/drv_usart_v2.h
diff --git a/bsp/ra6m4-cpk/drivers/drv_wdt.c b/bsp/renesas/ra6m4-cpk/drivers/drv_wdt.c
similarity index 100%
rename from bsp/ra6m4-cpk/drivers/drv_wdt.c
rename to bsp/renesas/ra6m4-cpk/drivers/drv_wdt.c
diff --git a/bsp/ra6m4-cpk/ports/SConscript b/bsp/renesas/ra6m4-cpk/ports/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ports/SConscript
rename to bsp/renesas/ra6m4-cpk/ports/SConscript
diff --git a/bsp/ra6m4-cpk/ports/fal/SConscript b/bsp/renesas/ra6m4-cpk/ports/fal/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ports/fal/SConscript
rename to bsp/renesas/ra6m4-cpk/ports/fal/SConscript
diff --git a/bsp/ra6m4-cpk/ports/fal/fal_cfg.h b/bsp/renesas/ra6m4-cpk/ports/fal/fal_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ports/fal/fal_cfg.h
rename to bsp/renesas/ra6m4-cpk/ports/fal/fal_cfg.h
diff --git a/bsp/ra6m4-cpk/ports/rw007/SConscript b/bsp/renesas/ra6m4-cpk/ports/rw007/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ports/rw007/SConscript
rename to bsp/renesas/ra6m4-cpk/ports/rw007/SConscript
diff --git a/bsp/ra6m4-cpk/ports/rw007/drv_rw007.c b/bsp/renesas/ra6m4-cpk/ports/rw007/drv_rw007.c
similarity index 100%
rename from bsp/ra6m4-cpk/ports/rw007/drv_rw007.c
rename to bsp/renesas/ra6m4-cpk/ports/rw007/drv_rw007.c
diff --git a/bsp/ra6m4-cpk/project.uvoptx b/bsp/renesas/ra6m4-cpk/project.uvoptx
similarity index 84%
rename from bsp/ra6m4-cpk/project.uvoptx
rename to bsp/renesas/ra6m4-cpk/project.uvoptx
index 5454093561..9d8de1e521 100644
--- a/bsp/ra6m4-cpk/project.uvoptx
+++ b/bsp/renesas/ra6m4-cpk/project.uvoptx
@@ -117,10 +117,25 @@
Segger\JL2CM3.dll
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+ d
+
0
JL2CM3
- -U-O78 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0
+ -U-O78 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0
@@ -130,12 +145,12 @@
0
1
- 0
+ 1
0
0
0
0
- 0
+ 1
0
0
0
@@ -182,7 +197,7 @@
0
0
0
- ..\..\libcpu\arm\common\backtrace.c
+ ..\..\..\libcpu\arm\common\backtrace.c
backtrace.c
0
0
@@ -194,8 +209,8 @@
0
0
0
- ..\..\libcpu\arm\common\div0.c
- div0.c
+ ..\..\..\libcpu\arm\common\showmem.c
+ showmem.c
0
0
@@ -206,8 +221,8 @@
0
0
0
- ..\..\libcpu\arm\common\showmem.c
- showmem.c
+ ..\..\..\libcpu\arm\common\div0.c
+ div0.c
0
0
@@ -218,7 +233,7 @@
0
0
0
- ..\..\libcpu\arm\cortex-m4\cpuport.c
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
cpuport.c
0
0
@@ -230,7 +245,7 @@
0
0
0
- ..\..\libcpu\arm\cortex-m4\context_rvds.S
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
context_rvds.S
0
0
@@ -250,7 +265,7 @@
0
0
0
- ..\..\components\drivers\misc\pin.c
+ ..\..\..\components\drivers\misc\pin.c
pin.c
0
0
@@ -262,7 +277,7 @@
0
0
0
- ..\..\components\drivers\serial\serial_v2.c
+ ..\..\..\components\drivers\serial\serial_v2.c
serial_v2.c
0
0
@@ -274,8 +289,8 @@
0
0
0
- ..\..\components\drivers\src\waitqueue.c
- waitqueue.c
+ ..\..\..\components\drivers\src\ringbuffer.c
+ ringbuffer.c
0
0
@@ -286,8 +301,8 @@
0
0
0
- ..\..\components\drivers\src\dataqueue.c
- dataqueue.c
+ ..\..\..\components\drivers\src\pipe.c
+ pipe.c
0
0
@@ -298,8 +313,8 @@
0
0
0
- ..\..\components\drivers\src\ringblk_buf.c
- ringblk_buf.c
+ ..\..\..\components\drivers\src\waitqueue.c
+ waitqueue.c
0
0
@@ -310,8 +325,8 @@
0
0
0
- ..\..\components\drivers\src\pipe.c
- pipe.c
+ ..\..\..\components\drivers\src\completion.c
+ completion.c
0
0
@@ -322,8 +337,8 @@
0
0
0
- ..\..\components\drivers\src\ringbuffer.c
- ringbuffer.c
+ ..\..\..\components\drivers\src\workqueue.c
+ workqueue.c
0
0
@@ -334,8 +349,8 @@
0
0
0
- ..\..\components\drivers\src\workqueue.c
- workqueue.c
+ ..\..\..\components\drivers\src\dataqueue.c
+ dataqueue.c
0
0
@@ -346,8 +361,8 @@
0
0
0
- ..\..\components\drivers\src\completion.c
- completion.c
+ ..\..\..\components\drivers\src\ringblk_buf.c
+ ringblk_buf.c
0
0
@@ -410,7 +425,7 @@
0
0
0
- ..\..\components\finsh\shell.c
+ ..\..\..\components\finsh\shell.c
shell.c
0
0
@@ -422,7 +437,7 @@
0
0
0
- ..\..\components\finsh\msh.c
+ ..\..\..\components\finsh\msh.c
msh.c
0
0
@@ -434,7 +449,7 @@
0
0
0
- ..\..\components\finsh\cmd.c
+ ..\..\..\components\finsh\cmd.c
cmd.c
0
0
@@ -454,8 +469,8 @@
0
0
0
- ..\..\src\components.c
- components.c
+ ..\..\..\src\idle.c
+ idle.c
0
0
@@ -466,8 +481,8 @@
0
0
0
- ..\..\src\irq.c
- irq.c
+ ..\..\..\src\components.c
+ components.c
0
0
@@ -478,7 +493,7 @@
0
0
0
- ..\..\src\object.c
+ ..\..\..\src\object.c
object.c
0
0
@@ -490,8 +505,8 @@
0
0
0
- ..\..\src\idle.c
- idle.c
+ ..\..\..\src\timer.c
+ timer.c
0
0
@@ -502,8 +517,8 @@
0
0
0
- ..\..\src\kservice.c
- kservice.c
+ ..\..\..\src\ipc.c
+ ipc.c
0
0
@@ -514,8 +529,8 @@
0
0
0
- ..\..\src\clock.c
- clock.c
+ ..\..\..\src\device.c
+ device.c
0
0
@@ -526,8 +541,8 @@
0
0
0
- ..\..\src\device.c
- device.c
+ ..\..\..\src\thread.c
+ thread.c
0
0
@@ -538,8 +553,8 @@
0
0
0
- ..\..\src\scheduler.c
- scheduler.c
+ ..\..\..\src\kservice.c
+ kservice.c
0
0
@@ -550,8 +565,8 @@
0
0
0
- ..\..\src\thread.c
- thread.c
+ ..\..\..\src\mem.c
+ mem.c
0
0
@@ -562,8 +577,8 @@
0
0
0
- ..\..\src\mem.c
- mem.c
+ ..\..\..\src\irq.c
+ irq.c
0
0
@@ -574,8 +589,8 @@
0
0
0
- ..\..\src\ipc.c
- ipc.c
+ ..\..\..\src\scheduler.c
+ scheduler.c
0
0
@@ -586,8 +601,8 @@
0
0
0
- ..\..\src\timer.c
- timer.c
+ ..\..\..\src\clock.c
+ clock.c
0
0
@@ -606,7 +621,7 @@
0
0
0
- ..\..\components\libc\compilers\common\time.c
+ ..\..\..\components\libc\compilers\common\time.c
time.c
0
0
@@ -615,7 +630,7 @@
:Renesas RA Smart Configurator:Common Sources
- 1
+ 0
0
0
0
diff --git a/bsp/ra6m4-cpk/project.uvprojx b/bsp/renesas/ra6m4-cpk/project.uvprojx
similarity index 85%
rename from bsp/ra6m4-cpk/project.uvprojx
rename to bsp/renesas/ra6m4-cpk/project.uvprojx
index 9c8734f244..8029e0d36a 100644
--- a/bsp/ra6m4-cpk/project.uvprojx
+++ b/bsp/renesas/ra6m4-cpk/project.uvprojx
@@ -14,11 +14,11 @@
1
- R7FA6M4AF
+ R7FA6M4AF3CFB
Renesas
Renesas.RA_DFP.3.1.0
https://www2.renesas.eu/Keil_MDK_Packs/
- CPUTYPE("Cortex-M33") FPU2 CLOCK(12000000) ELITTLE
+ CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE
@@ -33,7 +33,7 @@
- $$Device:R7FA6M4AF$SVD\R7FA6M4AF.svd
+ $$Device:R7FA6M4AF3CFB$SVD\R7FA6M4AF.svd
0
0
@@ -49,7 +49,7 @@
1
.\Objects\
- ra6m4
+ ra6m4_cpk
1
0
1
@@ -82,11 +82,11 @@
0
0
-
+ cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out"""
0
0
- 0
+ 2
0
0
@@ -109,10 +109,10 @@
1
- SARMCM3.DLL
- -MPU
- DCM.DLL
- -pCM4
+
+
+
+
SARMCM3.DLL
-MPU
TCM.DLL
@@ -130,7 +130,7 @@
0
- 0
+ 1
0
0
1
@@ -339,7 +339,7 @@
-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal
SOC_R7FA6M4AF, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
- ..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;drivers\config;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;..\..\examples\utest\testcases\kernel
+ ..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\components\libc\posix\io\poll;..\..\..\examples\utest\testcases\kernel
@@ -386,27 +386,27 @@
backtrace.c
1
- ..\..\libcpu\arm\common\backtrace.c
-
-
- div0.c
- 1
- ..\..\libcpu\arm\common\div0.c
+ ..\..\..\libcpu\arm\common\backtrace.c
showmem.c
1
- ..\..\libcpu\arm\common\showmem.c
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
cpuport.c
1
- ..\..\libcpu\arm\cortex-m4\cpuport.c
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
context_rvds.S
2
- ..\..\libcpu\arm\cortex-m4\context_rvds.S
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
@@ -416,47 +416,47 @@
pin.c
1
- ..\..\components\drivers\misc\pin.c
+ ..\..\..\components\drivers\misc\pin.c
serial_v2.c
1
- ..\..\components\drivers\serial\serial_v2.c
-
-
- waitqueue.c
- 1
- ..\..\components\drivers\src\waitqueue.c
-
-
- dataqueue.c
- 1
- ..\..\components\drivers\src\dataqueue.c
-
-
- ringblk_buf.c
- 1
- ..\..\components\drivers\src\ringblk_buf.c
-
-
- pipe.c
- 1
- ..\..\components\drivers\src\pipe.c
+ ..\..\..\components\drivers\serial\serial_v2.c
ringbuffer.c
1
- ..\..\components\drivers\src\ringbuffer.c
+ ..\..\..\components\drivers\src\ringbuffer.c
- workqueue.c
+ pipe.c
1
- ..\..\components\drivers\src\workqueue.c
+ ..\..\..\components\drivers\src\pipe.c
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
completion.c
1
- ..\..\components\drivers\src\completion.c
+ ..\..\..\components\drivers\src\completion.c
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
@@ -486,17 +486,17 @@
shell.c
1
- ..\..\components\finsh\shell.c
+ ..\..\..\components\finsh\shell.c
msh.c
1
- ..\..\components\finsh\msh.c
+ ..\..\..\components\finsh\msh.c
cmd.c
1
- ..\..\components\finsh\cmd.c
+ ..\..\..\components\finsh\cmd.c
@@ -504,64 +504,64 @@
Kernel
- components.c
+ idle.c
1
- ..\..\src\components.c
+ ..\..\..\src\idle.c
- irq.c
+ components.c
1
- ..\..\src\irq.c
+ ..\..\..\src\components.c
object.c
1
- ..\..\src\object.c
-
-
- idle.c
- 1
- ..\..\src\idle.c
-
-
- kservice.c
- 1
- ..\..\src\kservice.c
-
-
- clock.c
- 1
- ..\..\src\clock.c
-
-
- device.c
- 1
- ..\..\src\device.c
-
-
- scheduler.c
- 1
- ..\..\src\scheduler.c
-
-
- thread.c
- 1
- ..\..\src\thread.c
-
-
- mem.c
- 1
- ..\..\src\mem.c
-
-
- ipc.c
- 1
- ..\..\src\ipc.c
+ ..\..\..\src\object.c
timer.c
1
- ..\..\src\timer.c
+ ..\..\..\src\timer.c
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
@@ -571,7 +571,7 @@
time.c
1
- ..\..\components\libc\compilers\common\time.c
+ ..\..\..\components\libc\compilers\common\time.c
diff --git a/bsp/ra6m4-cpk/ra/SConscript b/bsp/renesas/ra6m4-cpk/ra/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ra/SConscript
rename to bsp/renesas/ra6m4-cpk/ra/SConscript
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
similarity index 95%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
index d2c3e2291f..abebc95f94 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
@@ -1,11 +1,11 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
- * @version V1.0.0
- * @date 03. March 2020
+ * @version V1.0.1
+ * @date 19. April 2021
******************************************************************************/
/*
- * Copyright (c) 2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -48,7 +48,7 @@
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
-#endif
+#endif
/**
\brief Enable I-Cache
@@ -112,7 +112,7 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
-__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
@@ -325,13 +325,13 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
-__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- if ( dsize > 0 ) {
+ if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
-
+
__DSB();
do {
@@ -355,13 +355,13 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
-__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- if ( dsize > 0 ) {
+ if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
-
+
__DSB();
do {
@@ -385,13 +385,13 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
-__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- if ( dsize > 0 ) {
+ if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
-
+
__DSB();
do {
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
index 237ff6ec3e..a955d47139 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version V5.2.1
- * @date 26. March 2020
+ * @version V5.3.2
+ * @date 27. May 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -63,9 +63,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
-#ifndef __STATIC_FORCEINLINE
+#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
-#endif
+#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
@@ -131,279 +131,6 @@
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); */
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#else
- (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@@ -461,7 +188,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
#define __DMB() __dmb(0xF)
-
+
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
@@ -799,6 +526,280 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+ __ISB();
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@@ -878,6 +879,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
index 90de9dbf8f..6911417747 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
- * @version V5.3.1
- * @date 26. March 2020
+ * @version V5.4.3
+ * @date 27. May 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,10 +29,6 @@
#pragma clang system_header /* treat file as system include file */
-#ifndef __ARM_COMPAT_H
-#include /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
@@ -136,676 +132,26 @@
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
+#endif
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); see arm_compat.h */
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); see arm_compat.h */
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
- (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR() ((uint32_t)0U)
-#endif
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __set_FPSCR __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x) ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@@ -1228,7 +574,7 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
-
+
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
@@ -1376,6 +722,694 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@@ -1452,6 +1486,8 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
index 0e5c7349d3..1e255d5907 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang_ltm.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
- * @version V1.3.0
- * @date 26. March 2020
+ * @version V1.5.3
+ * @date 27. May 2021
******************************************************************************/
/*
- * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,10 +29,6 @@
#pragma clang system_header /* treat file as system include file */
-#ifndef __ARM_COMPAT_H
-#include /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
@@ -136,665 +132,26 @@
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
+#endif
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); see arm_compat.h */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); see arm_compat.h */
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR() ((uint32_t)0U)
-#endif
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __set_FPSCR __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x) ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@@ -1354,6 +711,682 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@@ -1878,6 +1911,8 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
index a2778f58e8..67bda4ef3c 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler GCC header file
- * @version V5.3.0
- * @date 26. March 2020
+ * @version V5.4.1
+ * @date 27. May 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -46,9 +46,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
-#ifndef __STATIC_FORCEINLINE
+#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
-#endif
+#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
@@ -126,23 +126,23 @@
\details This default implementations initialized all data and additional bss
sections relying on .copy.table and .zero.table specified properly
in the used linker script.
-
+
*/
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
{
extern void _start(void) __NO_RETURN;
-
+
typedef struct {
uint32_t const* src;
uint32_t* dest;
uint32_t wlen;
} __copy_table_t;
-
+
typedef struct {
uint32_t* dest;
uint32_t wlen;
} __zero_table_t;
-
+
extern const __copy_table_t __copy_table_start__;
extern const __copy_table_t __copy_table_end__;
extern const __zero_table_t __zero_table_start__;
@@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
pTable->dest[i] = pTable->src[i];
}
}
-
+
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
for(uint32_t i=0u; iwlen; ++i) {
pTable->dest[i] = 0u;
}
}
-
+
_start();
}
-
+
#define __PROGRAM_START __cmsis_start
#endif
@@ -182,701 +182,26 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
#endif
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL __StackSeal
+#endif
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_get_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- return __builtin_arm_get_fpscr();
-#else
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#endif
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- __builtin_arm_set_fpscr(fpscr);
-#else
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
- (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@@ -1250,7 +575,7 @@ __extension__ \
\return Saturated value
*/
#define __USAT(ARG1, ARG2) \
- __extension__ \
+__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
@@ -1610,6 +935,703 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@@ -1925,6 +1947,7 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
}
#define __SSAT16(ARG1, ARG2) \
+__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
@@ -1932,6 +1955,7 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
})
#define __USAT16(ARG1, ARG2) \
+__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
@@ -1965,9 +1989,11 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{
uint32_t result;
-
- __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
-
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+ __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+ } else {
+ result = __SXTB16(__ROR(op1, rotate)) ;
+ }
return result;
}
@@ -1979,6 +2005,18 @@ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
return(result);
}
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+ uint32_t result;
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+ __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
+ } else {
+ result = __SXTAB16(op1, __ROR(op2, rotate));
+ }
+ return result;
+}
+
+
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
@@ -2135,8 +2173,9 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
return(result);
}
-#if 0
+
#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
@@ -2144,6 +2183,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
})
#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
@@ -2152,13 +2192,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
-#endif
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
similarity index 96%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
index 7eeffca5c7..65b824b009 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h
@@ -1,14 +1,14 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version V5.2.0
- * @date 28. January 2020
+ * @version V5.3.0
+ * @date 14. April 2021
******************************************************************************/
//------------------------------------------------------------------------------
//
-// Copyright (c) 2017-2019 IAR Systems
-// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+// Copyright (c) 2017-2021 IAR Systems
+// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
@@ -238,6 +238,7 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#endif
+#undef __WEAK /* undo the definition from DLib_Defaults.h */
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
@@ -266,6 +267,24 @@ __packed struct __iar_u32 { uint32_t v; };
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL STACKSEAL$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
@@ -336,7 +355,13 @@ __packed struct __iar_u32 { uint32_t v; };
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
- #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __arm_wsr("CONTROL", control);
+ __iar_builtin_ISB();
+}
+
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
@@ -358,7 +383,13 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
- #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __arm_wsr("CONTROL_NS", control);
+ __iar_builtin_ISB();
+}
+
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
@@ -680,6 +711,7 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ __iar_builtin_ISB();
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
@@ -965,4 +997,6 @@ __packed struct __iar_u32 { uint32_t v; };
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
index 1ad19e215a..33df455436 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
- * @version V1.3.1
- * @date 27. March 2020
+ * @version V1.4.1
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -210,14 +210,14 @@
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
-
+
#if __FPU_PRESENT != 0U
#ifndef __FPU_DP
#define __FPU_DP 0U
#warning "__FPU_DP not defined in device header file; using default!"
#endif
#endif
-
+
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
@@ -232,7 +232,7 @@
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
@@ -261,7 +261,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -766,22 +766,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -1508,12 +1508,12 @@ typedef struct
/** \brief PMU Event Counter Registers (0-30) Definitions */
#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
-#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
-#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
/** \brief PMU Count Enable Set Register Definitions */
@@ -2221,10 +2221,10 @@ typedef struct
/** \brief PMU Type Register Definitions */
#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
-#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
-#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
@@ -2235,6 +2235,32 @@ typedef struct
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+/** \brief PMU Authentication Status Register Definitions */
+
+#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
+
/*@} end of group CMSIS_PMU */
#endif
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
index 71f000bcad..2bd9e76064 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version V5.2.0
- * @date 27. March 2020
+ * @version V5.2.2
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -254,7 +254,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -545,6 +545,7 @@ typedef struct
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
@@ -745,22 +746,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -2939,7 +2940,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
@{
*/
-
+
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
@@ -3006,7 +3007,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
@{
*/
-
+
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
index 24453a8863..74fb87e5c5 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V5.1.1
- * @date 27. March 2020
+ * @version V5.1.2
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -146,7 +146,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -565,19 +565,19 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
index 13359be3ed..f9cf6ab183 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version V5.2.0
- * @date 27. March 2020
+ * @version V5.2.2
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -254,7 +254,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -545,6 +545,7 @@ typedef struct
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
@@ -745,22 +746,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -3007,7 +3008,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
@{
*/
-
+
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
@@ -3074,7 +3075,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
@{
*/
-
+
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
index 6a5f6ad147..552c29464d 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
- * @version V1.1.0
- * @date 27. March 2020
+ * @version V1.1.2
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -249,12 +249,12 @@
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -545,6 +545,7 @@ typedef struct
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
@@ -745,22 +746,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -3007,7 +3008,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
@{
*/
-
+
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
@@ -3074,7 +3075,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
@{
*/
-
+
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
index 4e0e886697..e21cd14925 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V5.1.1
- * @date 27. March 2020
+ * @version V5.1.2
+ * @date 04. June 2021
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -198,7 +198,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -623,22 +623,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
index 6efaa3f842..ecee4e0afb 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm55.h
* @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
- * @version V1.0.0
- * @date 27. March 2020
+ * @version V1.2.1
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -210,7 +210,7 @@
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
-
+
#if __FPU_PRESENT != 0U
#ifndef __FPU_DP
#define __FPU_DP 0U
@@ -232,12 +232,12 @@
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
@@ -766,22 +766,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -1349,6 +1349,40 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup PwrModCtl_Type Power Mode Control Registers
+ \brief Type definitions for the Power Mode Control Registers (PWRMODCTL)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Power Mode Control Registers (PWRMODCTL).
+ */
+typedef struct
+{
+ __IOM uint32_t CPDLPSTATE;
+ __IOM uint32_t DPDLPSTATE;
+} PwrModCtl_Type;
+
+
+/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE CLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE CLPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE ELPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE ELPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE RLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE RLPSTATE Mask */
+
+/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE DLPSTATE Position */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk 3UL /*!< PWRMODCTL DPDLPSTATE DLPSTATE Mask */
+
+/*@}*/ /* end of group CMSIS_PWRMODCTL */
+
+
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -1508,12 +1542,12 @@ typedef struct
/** \brief PMU Event Counter Registers (0-30) Definitions */
#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
-#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
-#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
/** \brief PMU Count Enable Set Register Definitions */
@@ -2221,10 +2255,10 @@ typedef struct
/** \brief PMU Type Register Definitions */
#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
-#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
-#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
@@ -2235,6 +2269,33 @@ typedef struct
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+/** \brief PMU Authentication Status Register Definitions */
+
+#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
+
+
/*@} end of group CMSIS_PMU */
#endif
@@ -3066,6 +3127,7 @@ typedef struct
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
@@ -3081,6 +3143,7 @@ typedef struct
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
index e1c31c275d..010506e9fa 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm7.h
* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V5.1.2
- * @date 27. March 2020
+ * @version V5.1.6
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -213,7 +213,7 @@
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
-
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -501,7 +501,8 @@ typedef struct
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+ uint32_t RESERVED7[5U];
__IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
__IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
__IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
@@ -676,22 +677,22 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
@@ -875,21 +876,24 @@ typedef struct
#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */
+#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */
#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
/* AHBS Control Register Definitions */
#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
/* Auxiliary Bus Fault Status Register Definitions */
#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
index e8914ba601..d66621031e 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V5.0.9
- * @date 27. March 2020
+ * @version V5.0.10
+ * @date 04. June 2021
******************************************************************************/
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -562,19 +562,19 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h
index 791a8dae65..d9eedf81a6 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h
@@ -1,8 +1,8 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
- * @version V5.1.1
- * @date 10. February 2020
+ * @version V5.1.2
+ * @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
@@ -223,7 +223,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Configure an MPU region.
* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
+* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
@@ -234,7 +234,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
+* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
@@ -243,7 +243,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
MPU->RASR = rasr;
}
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h
index ef44ad01df..3de16efc86 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h
@@ -1,11 +1,11 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
- * @version V5.1.2
- * @date 10. February 2020
+ * @version V5.1.3
+ * @date 03. February 2021
******************************************************************************/
/*
- * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -281,7 +281,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
}
#endif
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h
index dbd39d20c7..f8f3d8935b 100644
--- a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h
+++ b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h
@@ -1,8 +1,8 @@
/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
- * @version V1.0.0
- * @date 24. March 2020
+ * @version V1.0.1
+ * @date 15. April 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
@@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
- return PMU->EVCNTR[num];
+ return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
}
/**
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h
diff --git a/bsp/ra6m4-cpk/ra/arm/CMSIS_5/LICENSE.txt b/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/LICENSE.txt
similarity index 100%
rename from bsp/ra6m4-cpk/ra/arm/CMSIS_5/LICENSE.txt
rename to bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/LICENSE.txt
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board.h b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board.h
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board.h
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h
similarity index 99%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h
index e0e57f9919..52efc903c9 100644
--- a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h
+++ b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_ethernet_phy.h
@@ -30,7 +30,7 @@
#ifndef BSP_ETHERNET_PHY_H
#define BSP_ETHERNET_PHY_H
-#include
+
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.c b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.c
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.c
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.h b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.h
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_init.h
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.c b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.c
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.c
diff --git a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h
similarity index 98%
rename from bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h
rename to bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h
index f050cdf675..10a644f212 100644
--- a/bsp/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h
+++ b/bsp/renesas/ra6m4-cpk/ra/board/ra6m4_cpk/board_leds.h
@@ -57,7 +57,7 @@ typedef struct st_bsp_leds
* found in the bsp_leds_t structure. */
typedef enum e_bsp_led
{
- BSP_LED_LED1 = 0, ///< TB LED - Red
+ BSP_LED_LED3 = 0, ///< TB LED - Red
} bsp_led_t;
/***********************************************************************************************************************
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h
index 88786d5620..c3fd642f1e 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/bsp_api.h
@@ -40,6 +40,7 @@
#endif
/* Vector information for this project. This is generated by the tooling. */
+#include "../../src/bsp/mcu/all/bsp_arm_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
@@ -71,6 +72,11 @@
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
+/* BSP TFU Includes. */
+#if BSP_FEATURE_TFU_SUPPORTED
+ #include "../../src/bsp/mcu/all/bsp_tfu.h"
+#endif
+
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_external_irq_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_external_irq_api.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/inc/api/r_external_irq_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_external_irq_api.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h
similarity index 93%
rename from bsp/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h
index 85a2a7dade..5983dcba0f 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_ioport_api.h
@@ -104,12 +104,21 @@ typedef enum e_ioport_peripheral
/** Pin will function as a CTSU peripheral pin */
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a CMPHS peripheral pin */
+ IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as a segment LCD peripheral pin */
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as an SCI peripheral DEn pin */
+ IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as a DALI peripheral pin */
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as an SCI DEn peripheral pin */
+ IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@@ -125,12 +134,21 @@ typedef enum e_ioport_peripheral
/** Pin will function as a USB high speed peripheral pin */
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a GPT peripheral pin */
+ IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as an SD/MMC peripheral pin */
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a GPT peripheral pin */
+ IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as an Ethernet MMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a GPT peripheral pin */
+ IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as an Ethernet RMMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@@ -140,6 +158,9 @@ typedef enum e_ioport_peripheral
/** Pin will function as a graphics LCD peripheral pin */
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+ /** Pin will function as a CAC peripheral pin */
+ IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
/** Pin will function as a debug trace peripheral pin */
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
@@ -148,9 +169,15 @@ typedef enum e_ioport_peripheral
/** Pin will function as a CEC peripheral pin */
IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as a PGAOUT peripheral pin */
+ IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as a PGAOUT peripheral pin */
+ IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
} ioport_peripheral_t;
-/** Superset of Ethernet channels. */
+/* DEPRECATED Superset of Ethernet channels. */
typedef enum e_ioport_eth_ch
{
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
@@ -158,7 +185,7 @@ typedef enum e_ioport_eth_ch
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
} ioport_ethernet_channel_t;
-/** Superset of Ethernet PHY modes. */
+/* DEPRECATED Superset of Ethernet PHY modes. */
typedef enum e_ioport_eth_mode
{
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
@@ -267,7 +294,7 @@ typedef struct st_ioport_api
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
- /** Configure the PHY mode of the Ethernet channels.
+ /* DEPRECATED Configure the PHY mode of the Ethernet channels.
* @par Implemented as
* - @ref R_IOPORT_EthernetModeCfg()
* @param[in] channel Channel configuration will be set for.
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_transfer_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_transfer_api.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/inc/api/r_transfer_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_transfer_api.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h
similarity index 93%
rename from bsp/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h
index dd56a1fb7c..14e7ee445c 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_uart_api.h
@@ -34,6 +34,7 @@
*
* Implemented by:
* - @ref SCI_UART
+ * - @ref SCI_B_UART
*
* @{
**********************************************************************************************************************/
@@ -76,9 +77,9 @@ typedef enum e_sf_event
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
- UART_DATA_BITS_8, ///< Data bits 8-bit
- UART_DATA_BITS_7, ///< Data bits 7-bit
- UART_DATA_BITS_9 ///< Data bits 9-bit
+ UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
+ UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
+ UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
} uart_data_bits_t;
/** UART Parity definition */
@@ -171,6 +172,7 @@ typedef struct st_uart_api
/** Open UART device.
* @par Implemented as
* - @ref R_SCI_UART_Open()
+ * - @ref R_SCI_B_UART_Open()
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
@@ -184,6 +186,7 @@ typedef struct st_uart_api
* The maximum transfer size is reported by infoGet().
* @par Implemented as
* - @ref R_SCI_UART_Read()
+ * - @ref R_SCI_B_UART_Read()
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
@@ -197,6 +200,7 @@ typedef struct st_uart_api
* The maximum transfer size is reported by infoGet().
* @par Implemented as
* - @ref R_SCI_UART_Write()
+ * - @ref R_SCI_B_UART_Write()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
@@ -210,6 +214,7 @@ typedef struct st_uart_api
*
* @par Implemented as
* - @ref R_SCI_UART_BaudSet()
+ * - @ref R_SCI_B_UART_BaudSet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
@@ -219,6 +224,7 @@ typedef struct st_uart_api
/** Get the driver specific information.
* @par Implemented as
* - @ref R_SCI_UART_InfoGet()
+ * - @ref R_SCI_B_UART_InfoGet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] baudrate Baud rate in bps.
@@ -229,6 +235,7 @@ typedef struct st_uart_api
* Abort ongoing transfer.
* @par Implemented as
* - @ref R_SCI_UART_Abort()
+ * - @ref R_SCI_B_UART_Abort()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
@@ -239,6 +246,7 @@ typedef struct st_uart_api
* Specify callback function and optional context pointer and working memory pointer.
* @par Implemented as
* - R_SCI_Uart_CallbackSet()
+ * - R_SCI_B_Uart_CallbackSet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
@@ -252,10 +260,21 @@ typedef struct st_uart_api
/** Close UART device.
* @par Implemented as
* - @ref R_SCI_UART_Close()
+ * - @ref R_SCI_B_UART_Close()
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
+
+ /** Stop ongoing read and return the number of bytes remaining in the read.
+ * @par Implemented as
+ * - @ref R_SCI_UART_ReadStop()
+ * - @ref R_SCI_B_UART_ReadStop()
+ *
+ * @param[in] p_ctrl Pointer to the UART control block.
+ * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
+ */
+ fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h
index 79ae8e5ba9..478b41a5f3 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_common_api.h
@@ -108,6 +108,7 @@ typedef enum e_fsp_err
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
+ FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, ///< Internal error
@@ -276,14 +277,16 @@ typedef enum e_fsp_err
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
+ FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
/* Start of SF_WIFI Specific */
- FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
- FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
- FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
- FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
- FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
- FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
+ FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
+ FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
+ FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
+ FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
+ FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
+ FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
+ FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_features.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_features.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/inc/fsp_features.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_features.h
index 9687250b89..09bd6b7f3e 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_features.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_features.h
@@ -115,6 +115,9 @@ typedef enum e_fsp_ip
FSP_IP_USBHS = 71, ///< USB High Speed
FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
FSP_IP_CEC = 73, ///< HDMI CEC
+ FSP_IP_TFU = 74, ///< Trigonometric Function Unit
+ FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
+ FSP_IP_CANFD = 76, ///< CAN-FD
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
@@ -221,6 +224,10 @@ typedef enum e_fsp_signal
FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
+ FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B
+ FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C
+ FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D
+ FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E
FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_version.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_version.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/inc/fsp_version.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_version.h
index d7bce2829b..e8b2bfc502 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/fsp_version.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/fsp_version.h
@@ -41,7 +41,7 @@
#define FSP_VERSION_MAJOR (3U)
/** FSP pack minor version. */
-#define FSP_VERSION_MINOR (1U)
+#define FSP_VERSION_MINOR (5U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
@@ -50,10 +50,10 @@
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
-#define FSP_VERSION_STRING ("3.1.0")
+#define FSP_VERSION_STRING ("3.5.0")
/** Unique FSP version ID. */
-#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.1.0")
+#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.5.0")
/**********************************************************************************************************************
* Typedef definitions
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/instances/r_icu.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_icu.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/inc/instances/r_icu.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_icu.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h
similarity index 86%
rename from bsp/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h
index 26e1aede25..9e1861cde8 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_ioport.h
@@ -259,6 +259,57 @@ typedef enum e_ioport_port_pin_t
IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
+
+ IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
+ IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
+ IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2
+ IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3
+ IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4
+ IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5
+ IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6
+ IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7
+ IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8
+ IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9
+ IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10
+ IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11
+ IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12
+ IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13
+ IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14
+ IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15
+
+ IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
+ IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
+ IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
+ IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3
+ IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4
+ IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5
+ IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6
+ IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7
+ IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8
+ IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9
+ IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10
+ IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11
+ IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12
+ IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13
+ IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14
+ IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15
+
+ IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
+ IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
+ IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2
+ IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3
+ IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4
+ IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5
+ IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6
+ IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7
+ IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8
+ IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9
+ IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10
+ IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11
+ IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12
+ IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13
+ IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14
+ IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15
} ioport_port_pin_t;
/**********************************************************************************************************************
diff --git a/bsp/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h
similarity index 94%
rename from bsp/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h
index b9abdbbfc7..520240450a 100644
--- a/bsp/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_sci_uart.h
@@ -54,11 +54,12 @@ typedef enum e_sci_clk_src
} sci_clk_src_t;
/** UART flow control mode definition */
-typedef enum e_flow_control
+typedef enum e_sci_uart_flow_control
{
- SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS
- SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS
- SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS
+ SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS
+ SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS
+ SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS
+ SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, ///< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options
} sci_uart_flow_control_t;
/** UART instance control block. */
@@ -179,6 +180,7 @@ fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
+fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_UART)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
similarity index 65%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
index 8ef6175970..8542eaa843 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
@@ -11,6 +11,10 @@
* @{
*/
+ #define R_ACMPHS0_BASE 0x400F4000
+ #define R_ACMPHS1_BASE 0x400F4100
+ #define R_ACMPHS2_BASE 0x400F4200
+ #define R_ACMPHS3_BASE 0x400F4300
#define R_MPU_BASE 0x40000000
#define R_TZF_BASE 0x40000E00
#define R_SRAM_BASE 0x40002000
@@ -33,15 +37,13 @@
#define R_SYSC_BASE 0x4001E000
#define R_TSN_CAL_BASE 0x407FB17C
#define R_TSN_CTRL_BASE 0x400F3000
- #define R_PFS_BASE 0x40080800
#define R_ELC_BASE 0x40082000
#define R_TC_BASE 0x40083000
#define R_IWDT_BASE 0x40083200
#define R_WDT_BASE 0x40083400
#define R_CAC_BASE 0x40083600
- #define R_MSTP_BASE 0x40084004
-
-// #define R_MSTP_BASE 0x40084000
+ #define R_MSTP_BASE 0x40084000
+ #define R_KINT_BASE 0x40085000
#define R_POEG_BASE 0x4008A000
#define R_USB_FS0_BASE 0x40090000
#define R_USB_HS0_BASE 0x40111000
@@ -63,6 +65,8 @@
#define R_AGT3_BASE 0x400E8300
#define R_AGT4_BASE 0x400E8400
#define R_AGT5_BASE 0x400E8500
+ #define R_AGTW0_BASE 0x400E8000
+ #define R_AGTW1_BASE 0x400E8100
#define R_TSN_CTRL_BASE 0x400F3000
#define R_CRC_BASE 0x40108000
#define R_DOC_BASE 0x40109000
@@ -80,6 +84,8 @@
#define R_SCI9_BASE 0x40118900
#define R_SPI0_BASE 0x4011A000
#define R_SPI1_BASE 0x4011A100
+ #define R_SPI_B0_BASE 0x4011A000
+ #define R_SPI_B1_BASE 0x4011A100
#define R_GPT320_BASE 0x40169000
#define R_GPT321_BASE 0x40169100
#define R_GPT322_BASE 0x40169200
@@ -91,30 +97,52 @@
#define R_GPT168_BASE 0x40169800
#define R_GPT169_BASE 0x40169900
#define R_GPT_OPS_BASE 0x40169A00
+ #define R_GPT_ODC_BASE 0x4016A000
+ #define R_GPT_GTCLK_BASE 0x40169B00
#define R_ADC120_BASE 0x40170000
#define R_ADC121_BASE 0x40170200
- #define R_DAC12_BASE 0x40171000
+
+/* Not included in SVD */
+ #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
+ #define R_DAC120_BASE 0x40172000
+ #define R_DAC121_BASE 0x40172100
+ #else
+ #define R_DAC12_BASE 0x40171000
+ #endif
#define R_FLAD_BASE 0x407FC000
#define R_FACI_HP_CMD_BASE 0x407E0000
#define R_FACI_HP_BASE 0x407FE000
#define R_QSPI_BASE 0x64000000
+ #define R_TFU_BASE 0x40021000
/* Not included in SVD */
- #define R_PORT0_BASE 0x40080000
- #define R_PORT1_BASE 0x40080020
- #define R_PORT2_BASE 0x40080040
- #define R_PORT3_BASE 0x40080060
- #define R_PORT4_BASE 0x40080080
- #define R_PORT5_BASE 0x400800A0
- #define R_PORT6_BASE 0x400800C0
- #define R_PORT7_BASE 0x400800E0
- #define R_PORT8_BASE 0x40080100
- #define R_PORT9_BASE 0x40080120
- #define R_PORT10_BASE 0x40080140
- #define R_PORT11_BASE 0x40080160
- #define R_PFS_BASE 0x40080800
- #define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
-
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ #define R_PORT0_BASE 0x4001F000
+ #define R_PORT1_BASE 0x4001F020
+ #define R_PORT2_BASE 0x4001F040
+ #define R_PORT10_BASE 0x4001F140
+ #define R_PORT11_BASE 0x4001F160
+ #define R_PORT12_BASE 0x4001F180
+ #define R_PORT13_BASE 0x4001F1A0
+ #define R_PORT14_BASE 0x4001F1C0
+ #define R_PFS_BASE 0x4001F800
+ #define R_PMISC_BASE 0x4001FD00
+ #else
+ #define R_PORT0_BASE 0x40080000
+ #define R_PORT1_BASE 0x40080020
+ #define R_PORT2_BASE 0x40080040
+ #define R_PORT3_BASE 0x40080060
+ #define R_PORT4_BASE 0x40080080
+ #define R_PORT5_BASE 0x400800A0
+ #define R_PORT6_BASE 0x400800C0
+ #define R_PORT7_BASE 0x400800E0
+ #define R_PORT8_BASE 0x40080100
+ #define R_PORT9_BASE 0x40080120
+ #define R_PORT10_BASE 0x40080140
+ #define R_PORT11_BASE 0x40080160
+ #define R_PFS_BASE 0x40080800
+ #define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
+ #endif
#define R_GPT_POEG0_BASE 0x4008A000
#define R_GPT_POEG1_BASE 0x4008A100
#define R_GPT_POEG2_BASE 0x4008A200
@@ -122,6 +150,9 @@
#define R_RTC_BASE 0x40083000
+ #define R_I3C0_BASE 0x4011F000
+ #define R_I3C1_BASE 0x4011F400
+
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
@@ -133,114 +164,167 @@
*/
// #define R_MPU ((R_MPU_Type *) R_MPU_BASE)
- #define R_TZF ((R_TZF_Type *) R_TZF_BASE)
- #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
- #define R_BUS ((R_BUS_Type *) R_BUS_BASE)
- #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
- #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
- #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
- #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
- #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
- #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
- #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
- #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
- #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
- #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
- #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
- #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
- #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
- #define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
- #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
- #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
- #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
- #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
- #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
- #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
- #define R_TC ((R_TC_Type *) R_TC_BASE)
- #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
- #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
- #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
- #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
- #define R_POEG ((R_POEG_Type *) R_POEG_BASE)
- #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
- #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
- #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
- #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
- #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
- #define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
- #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
- #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
- #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
- #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
- #define R_CEC ((R_CEC_Type *) R_CEC_BASE)
- #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
- #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
- #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
- #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
- #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
- #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
- #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
- #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
- #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
- #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
- #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
- #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
- #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
- #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
- #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
- #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
- #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
- #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
- #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
- #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
- #define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
- #define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
- #define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
- #define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
- #define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
- #define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
- #define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
- #define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
- #define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
- #define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
- #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
- #define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
- #define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
- #define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
- #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
- #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
- #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
- #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
+ #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
+ #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
+ #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
+ #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
+ #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
+ #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
+ #define R_TZF ((R_TZF_Type *) R_TZF_BASE)
+ #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
+ #define R_BUS ((R_BUS_B_Type *) R_BUS_BASE)
+ #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
+ #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
+ #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
+ #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
+ #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
+ #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
+ #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
+ #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
+ #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
+ #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
+ #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
+ #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
+ #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
+ #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
+ #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
+ #define R_TC ((R_TC_Type *) R_TC_BASE)
+ #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
+ #define R_KINT ((R_KINT_Type *) R_KINT_BASE)
+ #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
+ #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
+ #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
+ #define R_POEG ((R_POEG_Type *) R_POEG_BASE)
+ #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
+ #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
+ #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
+ #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
+ #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
+ #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
+ #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
+ #define R_CEC ((R_CEC_Type *) R_CEC_BASE)
+ #if BSP_FEATURE_CANFD_LITE
+ #define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE)
+ #else
+ #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
+ #endif
+ #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
+ #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
+ #if BSP_FEATURE_AGT_HAS_AGTW
+ #define R_AGT0 ((R_AGTW0_Type *) R_AGT0_BASE)
+ #define R_AGT1 ((R_AGTW0_Type *) R_AGT1_BASE)
+ #define R_AGT2 ((R_AGTW0_Type *) R_AGT2_BASE)
+ #define R_AGT3 ((R_AGTW0_Type *) R_AGT3_BASE)
+ #define R_AGT4 ((R_AGTW0_Type *) R_AGT4_BASE)
+ #define R_AGT5 ((R_AGTW0_Type *) R_AGT5_BASE)
+ #else
+ #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
+ #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
+ #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
+ #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
+ #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
+ #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
+ #endif
+ #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
+ #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
+ #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
+ #if (2U == BSP_FEATURE_DOC_VERSION)
+ #define R_DOC_B ((R_DOC_B_Type *) R_DOC_BASE)
+ #else
+ #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
+ #endif
+ #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
+ #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
+ #if (2U == BSP_FEATURE_SCI_VERSION)
+ #define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE)
+ #define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE)
+ #define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE)
+ #define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE)
+ #define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE)
+ #define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE)
+ #else
+ #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
+ #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
+ #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
+ #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
+ #endif
+ #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE)
+ #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE)
+ #define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
+ #define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
+ #define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
+ #define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
+ #define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
+ #define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
+ #define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
+ #define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
+ #define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
+ #define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
+ #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
+ #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
+ #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE)
+ #define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
+ #define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
+ #define R_ADC_B ((R_ADC_B0_Type *) R_ADC120_BASE)
+ #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
+ #define R_DAC0 ((R_DAC_Type *) R_DAC120_BASE)
+ #define R_DAC1 ((R_DAC_Type *) R_DAC121_BASE)
+ #else
+ #define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
+ #endif
+ #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
+ #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
+ #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
+ #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
+ #define R_TFU ((R_TFU_Type *) R_TFU_BASE)
+ #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
+ #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
/* Not in SVD. */
- #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
- #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
- #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
- #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
- #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
- #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
- #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
- #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
- #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
- #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
- #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
- #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
- #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
- #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
+ #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
+ #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
+ #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
+ #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
+ #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
+ #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
+ #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
+ #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
+ #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
+ #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
+ #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
+ #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
+ #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
+ #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
+ #endif
+ #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
+ #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
- #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
- #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
- #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
- #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
+ #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
+ #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
+ #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
+ #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
- #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
+ #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -265,6 +349,8 @@
#define R_ADC1_BASE 0x4005C200
#define R_AGT0_BASE 0x40084000
#define R_AGT1_BASE 0x40084100
+ #define R_AGTW0_BASE 0x40084000
+ #define R_AGTW1_BASE 0x40084100
#define R_BUS_BASE 0x40003000
#define R_CAC_BASE 0x40044600
#define R_CAN0_BASE 0x40050000
@@ -322,7 +408,7 @@
#define R_GPT_POEG1_BASE 0x40042100
#define R_GPT_POEG2_BASE 0x40042200
#define R_GPT_POEG3_BASE 0x40042300
- #define R_I3C_BASE 0x40083000
+ #define R_I3C0_BASE 0x40083000
#define R_ICU_BASE 0x40006000
#define R_IIC0_BASE 0x40053000
#define R_IIC1_BASE 0x40053100
@@ -335,7 +421,7 @@
#define R_MPU_MMPU_BASE 0x40000000
#define R_MPU_SMPU_BASE 0x40000C00
#define R_MPU_SPMON_BASE 0x40000D00
- #define R_MSTP_BASE 0x40047000
+ #define R_MSTP_BASE (0x40047000 - 4U) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
#define R_OPAMP_BASE 0x40086000
#define R_OPAMP2_BASE 0x400867F8
#define R_PDC_BASE 0x40094000
@@ -404,12 +490,14 @@
#define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
+ #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
+ #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
#define R_BUS ((R_BUS_Type *) R_BUS_BASE)
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
- #if (BSP_FEATURE_CTSU_VERSION == 2)
+ #if (2U == BSP_FEATURE_CTSU_VERSION)
#define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE)
#else
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
@@ -464,7 +552,7 @@
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
- #define R_I3C ((R_I3C_Type *) R_I3C_BASE)
+ #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
@@ -478,7 +566,7 @@
#define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
#define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
- #if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U)
+ #if (2U == BSP_FEATURE_OPAMP_BASE_ADDRESS)
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE)
#else
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
similarity index 71%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
index b969e3676d..a48f6d2926 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
@@ -48,7 +48,7 @@ extern "C" {
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
-/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */
+/* IRQn_Type is provided in bsp_arm_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -1098,6 +1098,520 @@ typedef struct
__IM uint32_t RESERVED[13];
} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */
+/**
+ * @brief R_CANFDL_CFDC [CFDC] (Channel Control/Status)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */
+ __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */
+ __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */
+ __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */
+ } NCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */
+
+ struct
+ {
+ __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */
+ __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */
+ __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */
+ uint32_t : 4;
+ __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */
+ __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */
+ __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */
+ __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */
+ __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */
+ __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */
+ __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */
+ __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */
+ __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */
+ __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */
+ __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */
+ __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+ * enable */
+ uint32_t : 1;
+ __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */
+ __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */
+ __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */
+ __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */
+ uint32_t : 3;
+ __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */
+ __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */
+ } CTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */
+
+ struct
+ {
+ __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */
+ __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */
+ __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */
+ __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */
+ __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */
+ __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */
+ __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */
+ __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */
+ __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */
+ uint32_t : 7;
+ __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */
+ __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */
+ } STS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */
+
+ struct
+ {
+ __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */
+ __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */
+ __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */
+ __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */
+ __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */
+ __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */
+ __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */
+ __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */
+ __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */
+ __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */
+ __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */
+ __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */
+ __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */
+ __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */
+ __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */
+ uint32_t : 1;
+ __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */
+ uint32_t : 1;
+ } ERFL_b;
+ };
+} R_CANFDL_CFDC_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_CANFDL_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */
+ __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */
+ uint32_t : 3;
+ __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */
+ uint32_t : 4;
+ __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */
+ uint32_t : 4;
+ } DCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */
+ uint32_t : 5;
+ __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */
+ __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */
+ __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */
+ uint32_t : 5;
+ __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */
+ uint32_t : 4;
+ __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */
+ __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */
+ __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */
+ uint32_t : 1;
+ } FDCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */
+
+ struct
+ {
+ __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */
+ __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */
+ uint32_t : 30;
+ } FDCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */
+ __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */
+ __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */
+ uint32_t : 5;
+ __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */
+ __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */
+ __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */
+
+ struct
+ {
+ __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */
+ uint32_t : 3;
+ __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */
+ uint32_t : 4;
+ } FDCRC_b;
+ };
+ __IM uint32_t RESERVED[3];
+} R_CANFDL_CFDC2_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief R_CANFDL_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */
+ __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */
+ __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */
+ __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */
+ __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */
+ __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */
+ __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */
+ } M_b;
+ };
+
+ union
+ {
+ __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */
+ uint32_t : 3;
+ __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */
+ __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+ * Pointer */
+ uint32_t : 2;
+ __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */
+ __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */
+ } P0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */
+
+ struct
+ {
+ __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */
+ uint32_t : 23;
+ } P1_b;
+ };
+} R_CANFDL_CFDGAFL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_CANFDL_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */
+
+ struct
+ {
+ __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */
+ __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */
+ uint32_t : 6;
+ __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */
+ } ACC0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */
+
+ struct
+ {
+ __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */
+ __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */
+ uint32_t : 14;
+ } ACC1_b;
+ };
+} R_CANFDL_CFDTHL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief R_CANFDL_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */
+
+ struct
+ {
+ __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */
+ uint32_t : 1;
+ __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */
+ __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */
+
+ struct
+ {
+ __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */
+ uint32_t : 12;
+ __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */
+ uint32_t : 6;
+ __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */
+
+ struct
+ {
+ __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */
+ } DF_b[64];
+ };
+} R_CANFDL_CFDRF_Type; /*!< Size = 76 (0x4c) */
+
+/**
+ * @brief R_CANFDL_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
+
+ struct
+ {
+ __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
+ uint32_t : 1;
+ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
+ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
+
+ struct
+ {
+ __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
+ uint32_t : 12;
+ __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
+
+ struct
+ {
+ __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
+ uint32_t : 6;
+ __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
+
+ struct
+ {
+ __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
+ } DF_b[64];
+ };
+} R_CANFDL_CFDCF_Type; /*!< Size = 76 (0x4c) */
+
+/**
+ * @brief R_CANFDL_CFDTM [CFDTM] (TX Message Buffer Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */
+
+ struct
+ {
+ __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */
+ uint32_t : 1;
+ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */
+ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */
+
+ struct
+ {
+ __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */
+ uint32_t : 12;
+ __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */
+
+ struct
+ {
+ __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */
+ uint32_t : 6;
+ __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */
+ } FDCTR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */
+
+ struct
+ {
+ __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */
+ } DF_b[64];
+ };
+} R_CANFDL_CFDTM_Type; /*!< Size = 76 (0x4c) */
+
+/**
+ * @brief R_CANFDL_CFDRMC_RM [RM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */
+
+ struct
+ {
+ __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */
+ uint32_t : 1;
+ __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */
+ __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */
+ } ID_b;
+ };
+
+ union
+ {
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */
+
+ struct
+ {
+ __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */
+ uint32_t : 12;
+ __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */
+ } PTR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */
+
+ struct
+ {
+ __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */
+ __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
+ __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */
+ uint32_t : 5;
+ __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */
+ uint32_t : 6;
+ __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */
+ } FDSTS_b;
+ };
+
+ union
+ {
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */
+
+ struct
+ {
+ __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */
+ } DF_b[64];
+ };
+} R_CANFDL_CFDRMC_RM_Type; /*!< Size = 76 (0x4c) */
+
+/**
+ * @brief R_CANFDL_CFDRMC [CFDRMC] (RX Message Buffer Access Clusters)
+ */
+typedef struct
+{
+ __IOM R_CANFDL_CFDRMC_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */
+ __IM uint32_t RESERVED[104];
+} R_CANFDL_CFDRMC_Type; /*!< Size = 1024 (0x400) */
+
/**
* @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
*/
@@ -1115,7 +1629,11 @@ typedef struct
__OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */
} BY_b;
};
+ #if (2U == BSP_FEATURE_ELC_VERSION)
+ __IM uint8_t RESERVED[3];
+ #else
__IM uint8_t RESERVED;
+ #endif
} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */
/**
@@ -2415,7 +2933,7 @@ typedef struct
} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */
/**
- * @brief R_PFS_PORT [PORT] (Port [0..11])
+ * @brief R_PFS_PORT [PORT] (Port [0..14])
*/
typedef struct
{
@@ -2428,6 +2946,10 @@ typedef struct
typedef struct
{
__IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */
+
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ __IM uint16_t RESERVED;
+ #endif
} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */
/**
@@ -2588,6 +3110,179 @@ typedef struct
__IM uint8_t RESERVED5[3];
} R_RTC_CP_Type; /*!< Size = 16 (0x10) */
+/**
+ * @brief R_BUS_B_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
+
+ struct
+ {
+ __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
+ uint16_t : 2;
+ __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
+ uint16_t : 4;
+ __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
+ __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
+ uint16_t : 5;
+ __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
+ } MOD_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+ * is valid only when the PWENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+ * is valid only when the PRENB bit in CSnMOD is set to 1. */
+ uint32_t : 5;
+ __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
+ uint32_t : 3;
+ __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
+ uint32_t : 3;
+ } WCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
+ uint32_t : 1;
+ __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
+ uint32_t : 2;
+ __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
+ uint32_t : 1;
+ __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
+ uint32_t : 1;
+ } WCR2_b;
+ };
+ __IM uint32_t RESERVED1;
+} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+ __IM uint16_t RESERVED;
+
+ union
+ {
+ __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
+
+ struct
+ {
+ __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
+ uint16_t : 3;
+ __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
+ uint16_t : 2;
+ __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
+ uint16_t : 3;
+ __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
+ uint16_t : 3;
+ } CR_b;
+ };
+ __IM uint16_t RESERVED1[3];
+
+ union
+ {
+ __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
+
+ struct
+ {
+ __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
+ uint16_t : 4;
+ __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
+ uint16_t : 4;
+ } REC_b;
+ };
+ __IM uint16_t RESERVED2[2];
+} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
+
+ struct
+ {
+ __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+ * an error address. */
+ } ADD_b;
+ };
+
+ union
+ {
+ __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */
+
+ struct
+ {
+ __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */
+ uint8_t : 7;
+ } ERRRW_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[2];
+} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers)
+ */
+typedef struct
+{
+ union
+ {
+ __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */
+
+ struct
+ {
+ __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs,
+ * It stores an error address. */
+ } TZFADD_b;
+ };
+
+ union
+ {
+ __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */
+
+ struct
+ {
+ __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the
+ * time of the error */
+ uint8_t : 7;
+ } TZFERRRW_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[2];
+} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */
+
/**
* @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
*/
@@ -3349,7 +4044,19 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure
uint8_t : 6;
} ADICR_b;
};
- __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */
+
+ struct
+ {
+ uint8_t : 1;
+ __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */
+ uint8_t : 6;
+ } ADACSR_b;
+ };
+ __IM uint8_t RESERVED3;
union
{
@@ -4136,8 +4843,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure
struct
{
__IOM uint8_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */
- uint8_t : 1;
- __IOM uint8_t MONSEL : 4; /*!< [7..4] Monitor output selection bit. */
+ uint8_t : 5;
} ADREFMON_b;
};
__IM uint8_t RESERVED24;
@@ -4210,7 +4916,9 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure
uint32_t : 3;
__IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */
__IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */
- uint32_t : 13;
+ uint32_t : 6;
+ __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */
+ uint32_t : 6;
__IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */
uint32_t : 3;
__IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */
@@ -4234,11 +4942,17 @@ typedef struct /*!< (@ 0x400E0000) R_PSCU Structure
__IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */
__IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */
__IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */
- uint32_t : 3;
- __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC12 and the MSTPCRD.MSTPD20 bit security attribution */
+ uint32_t : 2;
+ __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */
+ __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */
uint32_t : 1;
__IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */
- uint32_t : 9;
+ uint32_t : 2;
+ __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */
+ __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */
+ __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */
+ __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */
+ uint32_t : 3;
} PSARD_b;
};
@@ -4506,6 +5220,158 @@ typedef struct /*!< (@ 0x40084000) R_AGT0 Structure
};
} R_AGT0_Type; /*!< Size = 16 (0x10) */
+/* =========================================================================================================================== */
+/* ================ R_AGTW0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTW0)
+ */
+
+ #ifndef BSP_OVERRIDE_REG_R_AGTW0_TYPE
+
+typedef struct /*!< (@ 0x40084000) R_AGTW0 Structure */
+{
+ union
+ {
+ __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */
+
+ struct
+ {
+ __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
+ * to the TSTOP bit in the AGTCRn register, the 16-bit counter
+ * is forcibly stopped and set to FFFFH. */
+ } AGT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */
+
+ struct
+ {
+ __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCRn register, set to
+ * FFFFH */
+ } AGTCMA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */
+
+ struct
+ {
+ __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+ * written to the TSTOP bit in the AGTCR register, set to
+ * FFFFH */
+ } AGTCMB_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */
+
+ struct
+ {
+ __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */
+ __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */
+ __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */
+ uint8_t : 1;
+ __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */
+ __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */
+ __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */
+ __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */
+ } AGTCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */
+
+ struct
+ {
+ __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */
+ __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */
+ __IOM uint8_t TCK : 3; /*!< [6..4] Count source */
+ uint8_t : 1;
+ } AGTMR1_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */
+
+ struct
+ {
+ __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+ * ratio */
+ uint8_t : 4;
+ __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */
+ } AGTMR2_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */
+
+ struct
+ {
+ uint8_t : 4;
+ __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
+ uint8_t : 3;
+ } AGTIOSEL_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */
+
+ struct
+ {
+ __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+ * mode. */
+ uint8_t : 1;
+ __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */
+ uint8_t : 1;
+ __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */
+ __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */
+ } AGTIOC_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */
+
+ struct
+ {
+ uint8_t : 2;
+ __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */
+ uint8_t : 5;
+ } AGTISR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */
+
+ struct
+ {
+ __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
+ __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */
+ __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */
+ uint8_t : 1;
+ __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
+ __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */
+ __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */
+ uint8_t : 1;
+ } AGTCMSR_b;
+ };
+ __IM uint8_t RESERVED;
+} R_AGTW0_Type; /*!< Size = 20 (0x14) */
+
+ #endif
+
/* =========================================================================================================================== */
/* ================ R_BUS ================ */
/* =========================================================================================================================== */
@@ -6253,6 +7119,631 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure
__IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */
} R_CANFD_Type; /*!< Size = 81920 (0x14000) */
+/* =========================================================================================================================== */
+/* ================ R_CANFDL ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFDL)
+ */
+
+typedef struct /*!< (@ 0x400B0000) R_CANFDL Structure */
+{
+ __IOM R_CANFDL_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */
+ __IM uint32_t RESERVED;
+
+ union
+ {
+ __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */
+
+ struct
+ {
+ __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */
+ __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */
+ __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */
+ __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */
+ __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */
+ __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */
+ uint32_t : 2;
+ __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */
+ __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */
+ uint32_t : 3;
+ __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */
+ } CFDGCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */
+
+ struct
+ {
+ __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */
+ __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */
+ uint32_t : 5;
+ __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */
+ __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */
+ __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */
+ __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */
+ uint32_t : 4;
+ __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */
+ uint32_t : 15;
+ } CFDGCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */
+
+ struct
+ {
+ __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */
+ __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */
+ __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */
+ __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */
+ uint32_t : 28;
+ } CFDGSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */
+
+ struct
+ {
+ __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */
+ __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */
+ __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */
+ __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */
+ uint32_t : 12;
+ __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */
+ uint32_t : 15;
+ } CFDGERFL_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */
+
+ struct
+ {
+ __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */
+ uint32_t : 16;
+ } CFDGTSC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */
+
+ struct
+ {
+ __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */
+ uint32_t : 4;
+ __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */
+ uint32_t : 23;
+ } CFDGAFLECTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */
+ uint32_t : 7;
+ __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */
+ uint32_t : 7;
+ } CFDGAFLCFG0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */
+
+ struct
+ {
+ __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */
+ __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */
+ uint32_t : 21;
+ } CFDRMNB_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */
+
+ struct
+ {
+ __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */
+ } CFDRMND0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */
+ } CFDRMIEC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */
+
+ struct
+ {
+ __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */
+ __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */
+ uint32_t : 2;
+ __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */
+ uint32_t : 1;
+ __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */
+ uint32_t : 1;
+ __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */
+ __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */
+ uint32_t : 16;
+ } CFDRFCC_b[2];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */
+
+ struct
+ {
+ __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */
+ __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */
+ __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */
+ __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */
+ uint32_t : 4;
+ __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */
+ uint32_t : 16;
+ } CFDRFSTS_b[2];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */
+ uint32_t : 24;
+ } CFDRFPCTR_b[2];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */
+
+ struct
+ {
+ __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */
+ __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */
+ __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */
+ uint32_t : 1;
+ __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */
+ __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */
+ __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */
+ __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */
+ __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */
+ __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */
+ __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */
+ __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */
+ } CFDCFCC_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */
+
+ struct
+ {
+ __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */
+ __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */
+ __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */
+ __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */
+ __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */
+ uint32_t : 3;
+ __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */
+ uint32_t : 16;
+ } CFDCFSTS_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */
+ uint32_t : 24;
+ } CFDCFPCTR_b[1];
+ };
+
+ union
+ {
+ __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */
+ uint32_t : 6;
+ __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */
+ uint32_t : 23;
+ } CFDFESTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */
+ uint32_t : 6;
+ __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */
+ uint32_t : 23;
+ } CFDFFSTS_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */
+ uint32_t : 6;
+ __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */
+ uint32_t : 23;
+ } CFDFMSTS_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */
+
+ struct
+ {
+ __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */
+ uint32_t : 31;
+ } CFDRFISTS_b;
+ };
+
+ union
+ {
+ __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */
+
+ struct
+ {
+ __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */
+ __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */
+ __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */
+ uint8_t : 5;
+ } CFDTMC_b[4];
+ };
+
+ union
+ {
+ __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */
+
+ struct
+ {
+ __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */
+ __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */
+ __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */
+ __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */
+ uint8_t : 3;
+ } CFDTMSTS_b[4];
+ };
+
+ union
+ {
+ __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */
+ uint32_t : 28;
+ } CFDTMTRSTS_b[1];
+ };
+
+ union
+ {
+ __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
+ * Status Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */
+ uint32_t : 28;
+ } CFDTMTARSTS_b[1];
+ };
+
+ union
+ {
+ __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */
+ uint32_t : 28;
+ } CFDTMTCSTS_b[1];
+ };
+
+ union
+ {
+ __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */
+
+ struct
+ {
+ __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */
+ uint32_t : 28;
+ } CFDTMTASTS_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
+ * Register */
+
+ struct
+ {
+ __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */
+ uint32_t : 28;
+ } CFDTMIEC_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */
+
+ struct
+ {
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
+ uint32_t : 4;
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
+ uint32_t : 1;
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
+ __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */
+ uint32_t : 22;
+ } CFDTXQCC0_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */
+
+ struct
+ {
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
+ uint32_t : 5;
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
+ uint32_t : 18;
+ } CFDTXQSTS0_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */
+
+ struct
+ {
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
+ uint32_t : 24;
+ } CFDTXQPCTR0_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */
+
+ struct
+ {
+ __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */
+ uint32_t : 7;
+ __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */
+ __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */
+ __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */
+ uint32_t : 21;
+ } CFDTHLCC_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */
+
+ struct
+ {
+ __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */
+ __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */
+ __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */
+ __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */
+ uint32_t : 4;
+ __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */
+ uint32_t : 18;
+ } CFDTHLSTS_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */
+
+ struct
+ {
+ __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */
+ uint32_t : 24;
+ } CFDTHLPCTR_b[1];
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */
+ __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */
+ __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */
+ __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */
+ __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */
+ uint32_t : 27;
+ } CFDGTINTSTS0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */
+ uint32_t : 6;
+ } CFDGTSTCFG_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */
+
+ struct
+ {
+ uint32_t : 2;
+ __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */
+ uint32_t : 29;
+ } CFDGTSTCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */
+
+ struct
+ {
+ __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */
+ uint32_t : 7;
+ __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */
+ uint32_t : 22;
+ } CFDGFDCFG_b;
+ };
+ __IM uint32_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */
+
+ struct
+ {
+ __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */
+ uint32_t : 16;
+ } CFDGLOCKK_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */
+
+ struct
+ {
+ __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */
+ uint32_t : 27;
+ } CFDGAFLIGNENT_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */
+
+ struct
+ {
+ __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */
+ uint32_t : 7;
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
+ uint32_t : 16;
+ } CFDGAFLIGNCTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */
+
+ struct
+ {
+ __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */
+ __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */
+ uint32_t : 6;
+ __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */
+ uint32_t : 23;
+ } CFDCDTCT_b;
+ };
+
+ union
+ {
+ __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */
+
+ struct
+ {
+ __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */
+ __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */
+ uint32_t : 6;
+ __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
+ * 0 */
+ uint32_t : 23;
+ } CFDCDTSTS_b;
+ };
+ __IM uint32_t RESERVED3[2];
+
+ union
+ {
+ __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */
+
+ struct
+ {
+ __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */
+ uint32_t : 7;
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
+ uint32_t : 16;
+ } CFDGRSTC_b;
+ };
+ __IM uint32_t RESERVED4[9];
+ __IOM R_CANFDL_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */
+ __IOM R_CANFDL_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */
+ __IM uint32_t RESERVED5[24];
+
+ union
+ {
+ __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */
+
+ struct
+ {
+ __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
+ } CFDRPGACC_b[64];
+ };
+ __IM uint32_t RESERVED6[104];
+ __IOM R_CANFDL_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */
+ __IOM R_CANFDL_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */
+ __IOM R_CANFDL_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */
+ __IM uint32_t RESERVED7[3];
+ __IOM R_CANFDL_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */
+ __IM uint32_t RESERVED8[118];
+ __IOM R_CANFDL_CFDRMC_Type CFDRMC[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */
+} R_CANFDL_Type; /*!< Size = 6432 (0x1920) */
+
/* =========================================================================================================================== */
/* ================ R_CRC ================ */
/* =========================================================================================================================== */
@@ -6583,24 +8074,25 @@ typedef struct /*!< (@ 0x40081000) R_CTSU Structure
union
{
- __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */
+ __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */
struct
{
- __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */
- __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */
- __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */
- uint16_t : 3;
- __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */
- uint16_t : 7;
- __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */
+ __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */
+ __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */
+ __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */
+ uint16_t : 2;
+ __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */
+ __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */
+ uint16_t : 7;
+ __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */
} CTSUERRS_b;
};
__IM uint16_t RESERVED;
- __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */
+ __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */
__IM uint8_t RESERVED1;
__IM uint16_t RESERVED2;
-} R_CTSU_Type; /*!< Size = 36 (0x24) */
+} R_CTSU_Type; /*!< Size = 36 (0x24) */
/* =========================================================================================================================== */
/* ================ R_CTSU2 ================ */
@@ -6627,8 +8119,8 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
__OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */
__IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */
__IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */
- __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */
- __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */
+ __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power On Control */
+ __IOM uint32_t CSW : 1; /*!< [9..9] TSCAP Pin Enable */
__IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */
__IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */
__IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */
@@ -6636,7 +8128,7 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
__IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */
__IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */
__IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */
- __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */
+ __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Load Control During Measurement */
__IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */
__IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */
__IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */
@@ -6680,15 +8172,15 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
struct
{
- __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */
- __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */
- __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */
- __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */
- __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */
+ __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control */
+ __IOM uint32_t PRMODE : 2; /*!< [5..4] Phase Control Period */
+ __IOM uint32_t SOFF : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable */
+ __IOM uint32_t PROFF : 1; /*!< [7..7] Drive Pulse Phase Control */
+ __IOM uint32_t SST : 8; /*!< [15..8] Wait Time Sensor Stabilization */
uint32_t : 8;
- __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */
+ __IOM uint32_t SSMOD : 3; /*!< [26..24] Spread Spectrum Modulation Frequency */
uint32_t : 1;
- __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */
+ __IOM uint32_t SSCNT : 2; /*!< [29..28] Adjusting the SUCLK frequency */
uint32_t : 2;
} CTSUCRB_b;
};
@@ -6961,7 +8453,7 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
uint32_t : 1;
__IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */
__IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */
- uint32_t : 1;
+ __IOM uint32_t SUOVF : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag */
__IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */
__IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */
uint32_t : 10;
@@ -7000,7 +8492,7 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
__IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */
__IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */
uint32_t : 2;
- __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */
+ __IOM uint32_t SSDIV : 4; /*!< [23..20] Spread Spectrum Frequency */
__IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */
} CTSUSO_b;
};
@@ -7036,26 +8528,31 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure
struct
{
uint32_t : 2;
- __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */
- __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Power Supply Forced Start */
- __IOM uint32_t CLKSEL : 2; /*!< [5..4] CTSU Observation Clock Select */
- __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */
- __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Switched Capacitor Operation Stop */
- __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] CTSU Read Count Select of Sensor Counter */
- __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */
- __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */
- __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */
+ __IOM uint32_t TSOD : 1; /*!< [2..2] TS Pins Fixed Output */
+ __IOM uint32_t DRV : 1; /*!< [3..3] Power Supply Calibration Select */
+ __IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select */
+ __IOM uint32_t SUCLKEN : 1; /*!< [6..6] SUCLK Forced Oscillation Control */
+ __IOM uint32_t TSOC : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit */
+ __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter */
+ __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */
+ __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */
+ __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */
uint32_t : 4;
- __IOM uint32_t CFCSEL : 6; /*!< [21..16] CTSU Observation CFC Clock Select */
- __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */
- uint32_t : 2;
- __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */
+ __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */
+ __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */
uint32_t : 1;
- __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */
- __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */
- __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */
- __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */
- __IOM uint32_t TXREV : 1; /*!< [31..31] CTSU Transmit Pin Inverted Output */
+ __IOM uint32_t DACMSEL : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select */
+ __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration */
+ __IOM uint32_t SUMSEL : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration
+ * Select */
+ __IOM uint32_t SUCARRY : 1; /*!< [27..27] Current Control Oscillator Input Current Adjustment
+ * for SUCLK */
+ __IOM uint32_t DACCLK : 1; /*!< [28..28] Modulation Clock Select for Offset Current Circuits */
+ __IOM uint32_t CCOCLK : 1; /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator
+ * Input Current of SUCLK */
+ __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator
+ * for Measurement */
+ __IOM uint32_t TXREV : 1; /*!< [31..31] Transmit Pin Inverted Output */
} CTSUCALIB_b;
};
@@ -8815,6 +10312,8 @@ typedef struct /*!< (@ 0x40005400) R_DTC Structure
* @brief Event Link Controller (R_ELC)
*/
+ #ifndef BSP_OVERRIDE_REG_R_ELC_TYPE
+
typedef struct /*!< (@ 0x40041000) R_ELC Structure */
{
union
@@ -8840,12 +10339,12 @@ typedef struct /*!< (@ 0x40041000) R_ELC Structure
struct
{
- __IOM uint16_t ELSEGR0 : 1; /*!< [0..0] Event Link Software Event Generation Register 0 Security
+ __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */
+ __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
* Attribution */
- __IOM uint16_t ELSEGR1 : 1; /*!< [1..1] Event Link Software Event Generation Register 1Security
+ __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
* Attribution */
- __IOM uint16_t ELCR : 1; /*!< [2..2] Event Link Controller RegisterSecurity Attribution */
- uint16_t : 13;
+ uint16_t : 13;
} ELCSARA_b;
};
__IM uint16_t RESERVED3;
@@ -8892,6 +10391,8 @@ typedef struct /*!< (@ 0x40041000) R_ELC Structure
};
} R_ELC_Type; /*!< Size = 126 (0x7e) */
+ #endif
+
/* =========================================================================================================================== */
/* ================ R_ETHERC0 ================ */
/* =========================================================================================================================== */
@@ -12489,7 +13990,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure
__IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */
__IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */
__IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */
- uint32_t : 8;
+ __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */
+ uint32_t : 4;
} GTUPSR_b;
};
@@ -12531,7 +14033,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure
__IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */
__IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */
__IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */
- uint32_t : 8;
+ __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */
+ uint32_t : 4;
} GTDNSR_b;
};
@@ -13086,6 +14589,28 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure
};
} R_GPT0_Type; /*!< Size = 216 (0xd8) */
+/* =========================================================================================================================== */
+/* ================ R_GPT_GTCLK ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GTCLK (R_GPT_GTCLK)
+ */
+
+typedef struct /*!< (@ 0x40169B00) R_GPT_GTCLK Structure */
+{
+ union
+ {
+ __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */
+
+ struct
+ {
+ __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */
+ uint32_t : 31;
+ } GTCLKCR_b;
+ };
+} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */
+
/* =========================================================================================================================== */
/* ================ R_GPT_ODC ================ */
/* =========================================================================================================================== */
@@ -13105,7 +14630,7 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure
__IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */
__IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */
uint16_t : 6;
- __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */
+ __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */
uint16_t : 7;
} GTDLYCR1_b;
};
@@ -13122,7 +14647,9 @@ typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure
__IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */
uint16_t : 4;
__IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */
- uint16_t : 3;
+ __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */
+ __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */
+ __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */
__IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */
uint16_t : 3;
} GTDLYCR2_b;
@@ -13417,7 +14944,24 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure
uint32_t : 29;
} WUPEN1_b;
};
- __IM uint32_t RESERVED10[22];
+ __IM uint32_t RESERVED10[6];
+
+ union
+ {
+ __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */
+
+ struct
+ {
+ __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
+ * = 1) */
+ __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
+ * LPOPTEN bit = 1) */
+ uint8_t : 6;
+ } IELEN_b;
+ };
+ __IM uint8_t RESERVED11;
+ __IM uint16_t RESERVED12;
+ __IM uint32_t RESERVED13[15];
union
{
@@ -13429,8 +14973,8 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure
uint16_t : 7;
} SELSR0_b;
};
- __IM uint16_t RESERVED11;
- __IM uint32_t RESERVED12[31];
+ __IM uint16_t RESERVED14;
+ __IM uint32_t RESERVED15[31];
union
{
@@ -13445,7 +14989,7 @@ typedef struct /*!< (@ 0x40006000) R_ICU Structure
uint32_t : 15;
} DELSR_b[8];
};
- __IM uint32_t RESERVED13[24];
+ __IM uint32_t RESERVED16[24];
union
{
@@ -14366,14 +15910,14 @@ typedef struct /*!< (@ 0x40080000) R_KINT Structure
} R_KINT_Type; /*!< Size = 9 (0x9) */
/* =========================================================================================================================== */
-/* ================ I3C ================ */
+/* ================ R_I3C0 ================ */
/* =========================================================================================================================== */
/**
- * @brief I3C Bus Interface (I3C)
+ * @brief I3C Bus Interface (R_I3C0)
*/
-typedef struct /*!< (@ 0x40083000) I3C Structure */
+typedef struct /*!< (@ 0x40083000) R_I3C0 Structure */
{
union
{
@@ -14385,7 +15929,18 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
uint32_t : 31;
} PRTS_b;
};
- __IM uint32_t RESERVED[4];
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */
+
+ struct
+ {
+ __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */
+ uint32_t : 31;
+ } CECTL_b;
+ };
union
{
@@ -14974,7 +16529,20 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
uint32_t : 11;
} NTSTFC_b;
};
- __IM uint32_t RESERVED16[9];
+ __IM uint32_t RESERVED16[8];
+
+ union
+ {
+ __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */
+
+ struct
+ {
+ __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */
+ __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */
+ __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */
+ uint32_t : 29;
+ } BCST_b;
+ };
union
{
@@ -15092,8 +16660,7 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
union
{
- __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 (n
- * = 0) */
+ __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */
struct
{
@@ -15106,7 +16673,39 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
uint32_t : 9;
} SDATBAS0_b;
};
- __IM uint32_t RESERVED23[7];
+
+ union
+ {
+ __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
+ uint32_t : 1;
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
+ uint32_t : 3;
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
+ uint32_t : 9;
+ } SDATBAS1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */
+
+ struct
+ {
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
+ uint32_t : 1;
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
+ uint32_t : 3;
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
+ uint32_t : 9;
+ } SDATBAS2_b;
+ };
+ __IM uint32_t RESERVED23[5];
union
{
@@ -15307,8 +16906,9 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
struct
{
- __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */
- uint32_t : 29;
+ __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */
+ __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */
+ uint32_t : 26;
} CMDSPR_b;
};
@@ -15416,7 +17016,7 @@ typedef struct /*!< (@ 0x40083000) I3C Structure
uint32_t : 24;
} MSERRCNT_b;
};
-} I3C_Type; /*!< Size = 980 (0x3d4) */
+} R_I3C0_Type; /*!< Size = 980 (0x3d4) */
/* =========================================================================================================================== */
/* ================ R_MMF ================ */
@@ -15517,11 +17117,26 @@ typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure
* @brief System-Module Stop (R_MSTP)
*/
-typedef struct /*!< (@ 0x40047000) R_MSTP Structure */
+typedef struct /*!< (@ 0x40047000) R_MSTP Structure */
{
union
{
- __IOM uint32_t MSTPCRB; /*!< (@ 0x00000000) Module Stop Control Register B */
+ __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */
+
+ struct
+ {
+ __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */
+ uint32_t : 6;
+ __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */
+ uint32_t : 14;
+ __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */
+ uint32_t : 9;
+ } MSTPCRA_b;
+ };
+
+ union
+ {
+ __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */
struct
{
@@ -15560,7 +17175,7 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure
union
{
- __IOM uint32_t MSTPCRC; /*!< (@ 0x00000004) Module Stop Control Register C */
+ __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */
struct
{
@@ -15579,7 +17194,10 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure
__IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */
__IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */
__IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */
- uint32_t : 12;
+ uint32_t : 5;
+ __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */
+ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */
+ uint32_t : 5;
__IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */
__IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */
uint32_t : 2;
@@ -15589,7 +17207,7 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure
union
{
- __IOM uint32_t MSTPCRD; /*!< (@ 0x00000008) Module Stop Control Register D */
+ __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */
struct
{
@@ -15637,11 +17255,13 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure
union
{
- __IOM uint32_t MSTPCRE; /*!< (@ 0x0000000C) Module Stop Control Register E */
+ __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */
struct
{
- uint32_t : 14;
+ uint32_t : 4;
+ __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */
+ uint32_t : 9;
__IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module
* Stop */
__IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module
@@ -15659,7 +17279,7 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure
__IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */
} MSTPCRE_b;
};
-} R_MSTP_Type; /*!< Size = 16 (0x10) */
+} R_MSTP_Type; /*!< Size = 20 (0x14) */
/* =========================================================================================================================== */
/* ================ R_OPAMP ================ */
@@ -16186,8 +17806,8 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure
typedef struct /*!< (@ 0x40040800) R_PFS Structure */
{
- __IOM R_PFS_PORT_Type PORT[12]; /*!< (@ 0x00000000) Port [0..11] */
-} R_PFS_Type; /*!< Size = 768 (0x300) */
+ __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */
+} R_PFS_Type; /*!< Size = 960 (0x3c0) */
/* =========================================================================================================================== */
/* ================ R_PMISC ================ */
@@ -16197,6 +17817,8 @@ typedef struct /*!< (@ 0x40040800) R_PFS Structure
* @brief I/O Ports-MISC (R_PMISC)
*/
+ #ifndef BSP_OVERRIDE_REG_R_PMISC_TYPE
+
typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */
{
union
@@ -16241,6 +17863,8 @@ typedef struct /*!< (@ 0x40040D00) R_PMISC Structure
__IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */
} R_PMISC_Type; /*!< Size = 40 (0x28) */
+ #endif
+
/* =========================================================================================================================== */
/* ================ R_QSPI ================ */
/* =========================================================================================================================== */
@@ -17227,14 +18851,14 @@ typedef struct /*!< (@ 0x40070000) R_SCI0 Structure
struct
{
- __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */
- __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */
- __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */
- uint8_t : 1;
- __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */
- uint8_t : 1;
- __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */
- __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */
+ __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */
+ __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */
+ __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */
+ __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */
+ __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */
+ uint8_t : 1;
+ __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */
+ __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */
} SPMR_b;
};
@@ -18814,6 +20438,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure
};
} R_SRAM_Type; /*!< Size = 217 (0xd9) */
+/* =========================================================================================================================== */
+/* ================ R_BUS_B ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS_B)
+ */
+
+typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */
+{
+ __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
+ __IM uint32_t RESERVED[480];
+ __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
+
+ union
+ {
+ __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
+
+ struct
+ {
+ __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
+ __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
+ } CSRECEN_b;
+ };
+ __IM uint16_t RESERVED1;
+ __IM uint32_t RESERVED2[543];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTFHBIU_b;
+ };
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTFLBIU_b;
+ };
+ __IM uint16_t RESERVED4;
+ __IM uint32_t RESERVED5[2];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTS0BIU_b;
+ };
+ __IM uint16_t RESERVED6;
+ __IM uint32_t RESERVED7[3];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPSBIU_b;
+ };
+ __IM uint16_t RESERVED8;
+ __IM uint32_t RESERVED9[3];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPLBIU_b;
+ };
+ __IM uint16_t RESERVED10;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */
+ uint16_t : 15;
+ } BUSSCNTPHBIU_b;
+ };
+ __IM uint16_t RESERVED11;
+ __IM uint32_t RESERVED12[2];
+
+ union
+ {
+ __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTEQBIU_b;
+ };
+ __IM uint16_t RESERVED13;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTEOBIU_b;
+ };
+ __IM uint16_t RESERVED14;
+
+ union
+ {
+ __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */
+
+ struct
+ {
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */
+ uint16_t : 14;
+ } BUSSCNTECBIU_b;
+ };
+ __IM uint16_t RESERVED15;
+ __IM uint32_t RESERVED16[429];
+ __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */
+ __IM uint32_t RESERVED17[48];
+ __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */
+ __IM uint32_t RESERVED18[48];
+
+ union
+ {
+ __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS1ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED19;
+ __IM uint16_t RESERVED20;
+ __IM uint32_t RESERVED21;
+
+ union
+ {
+ __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS1ERRCLR_b;
+ };
+ __IM uint8_t RESERVED22;
+ __IM uint16_t RESERVED23;
+ __IM uint32_t RESERVED24;
+
+ union
+ {
+ __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS2ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED25;
+ __IM uint16_t RESERVED26;
+ __IM uint32_t RESERVED27;
+
+ union
+ {
+ __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS2ERRCLR_b;
+ };
+ __IM uint8_t RESERVED28;
+ __IM uint16_t RESERVED29;
+ __IM uint32_t RESERVED30;
+
+ union
+ {
+ __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS3ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED31;
+ __IM uint16_t RESERVED32;
+
+ union
+ {
+ __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */
+
+ struct
+ {
+ __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */
+ uint8_t : 7;
+ } DMACDTCERRSTAT_b;
+ };
+ __IM uint8_t RESERVED33;
+ __IM uint16_t RESERVED34;
+
+ union
+ {
+ __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS3ERRCLR_b;
+ };
+ __IM uint8_t RESERVED35;
+ __IM uint16_t RESERVED36;
+
+ union
+ {
+ __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */
+
+ struct
+ {
+ __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */
+ uint8_t : 7;
+ } DMACDTCERRCLR_b;
+ };
+ __IM uint8_t RESERVED37;
+ __IM uint16_t RESERVED38;
+
+ union
+ {
+ __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */
+
+ struct
+ {
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */
+ uint8_t : 1;
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */
+ uint8_t : 3;
+ } BUS4ERRSTAT_b;
+ };
+ __IM uint8_t RESERVED39;
+ __IM uint16_t RESERVED40;
+ __IM uint32_t RESERVED41;
+
+ union
+ {
+ __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */
+
+ struct
+ {
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */
+ uint8_t : 1;
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */
+ uint8_t : 3;
+ } BUS4ERRCLR_b;
+ };
+ __IM uint8_t RESERVED42;
+ __IM uint16_t RESERVED43;
+} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */
+
/* =========================================================================================================================== */
/* ================ R_SRC ================ */
/* =========================================================================================================================== */
@@ -19448,8 +21398,25 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} PLL2CR_b;
};
- __IM uint8_t RESERVED12;
- __IM uint32_t RESERVED13;
+ __IM uint8_t RESERVED12;
+
+ union
+ {
+ __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */
+
+ struct
+ {
+ __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
+ * (valid only when LPOPTEN = 1) */
+ __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */
+ __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
+ * clock (valid only when LPOPT.LPOPTEN = 1) */
+ uint8_t : 3;
+ __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */
+ } LPOPT_b;
+ };
+ __IM uint8_t RESERVED13;
+ __IM uint16_t RESERVED14;
union
{
@@ -19462,7 +21429,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */
} SLCDSCKCR_b;
};
- __IM uint8_t RESERVED14;
+ __IM uint8_t RESERVED15;
union
{
@@ -19485,8 +21452,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} SDCKOCR_b;
};
- __IM uint32_t RESERVED15[3];
- __IM uint8_t RESERVED16;
+ __IM uint32_t RESERVED16[3];
+ __IM uint8_t RESERVED17;
union
{
@@ -19515,8 +21482,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
* trimming bits */
} HOCOUTCR_b;
};
- __IM uint8_t RESERVED17;
- __IM uint32_t RESERVED18[2];
+ __IM uint8_t RESERVED18;
+ __IM uint32_t RESERVED19[2];
union
{
@@ -19531,13 +21498,27 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
union
{
- __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */
-
- struct
+ union
{
- __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */
- uint8_t : 5;
- } OCTACKDIVCR_b;
+ __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */
+ uint8_t : 5;
+ } OCTACKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */
+ uint8_t : 5;
+ } SCISPICKDIVCR_b;
+ };
};
union
@@ -19550,8 +21531,30 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 5;
} CANFDCKDIVCR_b;
};
- __IM uint8_t RESERVED19;
- __IM uint32_t RESERVED20;
+
+ union
+ {
+ __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */
+ uint8_t : 5;
+ } GPTCKDIVCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */
+
+ struct
+ {
+ __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */
+ uint8_t : 5;
+ } IICCKDIVCR_b;
+ };
+ __IM uint8_t RESERVED20;
+ __IM uint16_t RESERVED21;
union
{
@@ -19568,15 +21571,31 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
union
{
- __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */
-
- struct
+ union
{
- __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */
- uint8_t : 3;
- __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */
- __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */
- } OCTACKCR_b;
+ __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */
+ __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */
+ } OCTACKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */
+ __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */
+ } SCISPICKCR_b;
+ };
};
union
@@ -19591,8 +21610,35 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */
} CANFDCKCR_b;
};
- __IM uint8_t RESERVED21;
- __IM uint32_t RESERVED22[4];
+
+ union
+ {
+ __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */
+ __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */
+ } GPTCKCR_b;
+ };
+
+ union
+ {
+ __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */
+
+ struct
+ {
+ __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */
+ uint8_t : 3;
+ __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */
+ __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */
+ } IICCKCR_b;
+ };
+ __IM uint8_t RESERVED22;
+ __IM uint16_t RESERVED23;
+ __IM uint32_t RESERVED24[3];
union
{
@@ -19606,8 +21652,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint32_t : 29;
} SNZREQCR1_b;
};
- __IM uint32_t RESERVED23;
- __IM uint16_t RESERVED24;
+ __IM uint32_t RESERVED25;
+ __IM uint16_t RESERVED26;
union
{
@@ -19622,7 +21668,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */
} SNZCR_b;
};
- __IM uint8_t RESERVED25;
+ __IM uint8_t RESERVED27;
union
{
@@ -19652,7 +21698,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} SNZEDCR1_b;
};
- __IM uint16_t RESERVED26;
+ __IM uint16_t RESERVED28;
union
{
@@ -19695,7 +21741,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint32_t : 1;
} SNZREQCR_b;
};
- __IM uint16_t RESERVED27;
+ __IM uint16_t RESERVED29;
union
{
@@ -19733,7 +21779,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 3;
} OPCCR_b;
};
- __IM uint8_t RESERVED28;
+ __IM uint8_t RESERVED30;
union
{
@@ -19745,7 +21791,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 4;
} MOSCWTCR_b;
};
- __IM uint8_t RESERVED29[2];
+ __IM uint8_t RESERVED31[2];
union
{
@@ -19758,7 +21804,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 5;
} HOCOWTCR_b;
};
- __IM uint16_t RESERVED30[2];
+ __IM uint16_t RESERVED32[2];
union
{
@@ -19772,8 +21818,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 3;
} SOPCCR_b;
};
- __IM uint8_t RESERVED31;
- __IM uint32_t RESERVED32[5];
+ __IM uint8_t RESERVED33;
+ __IM uint32_t RESERVED34[5];
union
{
@@ -19807,8 +21853,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */
} RSTSR1_b;
};
- __IM uint16_t RESERVED33;
- __IM uint32_t RESERVED34[3];
+ __IM uint16_t RESERVED35;
+ __IM uint32_t RESERVED36[3];
union
{
@@ -19834,8 +21880,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */
} SDADCCKCR_b;
};
- __IM uint16_t RESERVED35;
- __IM uint32_t RESERVED36[3];
+ __IM uint16_t RESERVED37;
+ __IM uint32_t RESERVED38[3];
union
{
@@ -19890,7 +21936,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 6;
} LVD2SR_b;
};
- __IM uint32_t RESERVED37[183];
+ __IM uint32_t RESERVED39[183];
union
{
@@ -19918,7 +21964,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint32_t : 14;
} CGFSAR_b;
};
- __IM uint32_t RESERVED38;
+ __IM uint32_t RESERVED40;
union
{
@@ -19987,7 +22033,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint32_t : 8;
} BBFSAR_b;
};
- __IM uint32_t RESERVED39[3];
+ __IM uint32_t RESERVED41[3];
union
{
@@ -20049,8 +22095,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint32_t : 4;
} DPFSAR_b;
};
- __IM uint32_t RESERVED40[6];
- __IM uint16_t RESERVED41;
+ __IM uint32_t RESERVED42[6];
+ __IM uint16_t RESERVED43;
union
{
@@ -20268,7 +22314,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 3;
} DPSIEGR2_b;
};
- __IM uint8_t RESERVED42;
+ __IM uint8_t RESERVED44;
union
{
@@ -20326,7 +22372,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} RSTSR2_b;
};
- __IM uint8_t RESERVED43;
+ __IM uint8_t RESERVED45;
union
{
@@ -20343,7 +22389,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
* Enable */
} MOMCR_b;
};
- __IM uint16_t RESERVED44;
+ __IM uint16_t RESERVED46;
union
{
@@ -20413,7 +22459,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
} LVD2CMPCR_b;
};
};
- __IM uint8_t RESERVED45;
+ __IM uint8_t RESERVED47;
union
{
@@ -20446,7 +22492,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
__IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
} LVD2CR0_b;
};
- __IM uint8_t RESERVED46;
+ __IM uint8_t RESERVED48;
union
{
@@ -20481,7 +22527,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} VBTCR1_b;
};
- __IM uint32_t RESERVED47[8];
+ __IM uint32_t RESERVED49[8];
union
{
@@ -20509,8 +22555,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 6;
} VCCSEL_b;
};
- __IM uint16_t RESERVED48;
- __IM uint32_t RESERVED49[15];
+ __IM uint16_t RESERVED50;
+ __IM uint32_t RESERVED51[15];
union
{
@@ -20533,8 +22579,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 6;
} SOMCR_b;
};
- __IM uint16_t RESERVED50;
- __IM uint32_t RESERVED51[3];
+ __IM uint16_t RESERVED52;
+ __IM uint32_t RESERVED53[3];
union
{
@@ -20546,7 +22592,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} LOCOCR_b;
};
- __IM uint8_t RESERVED52;
+ __IM uint8_t RESERVED54;
union
{
@@ -20561,8 +22607,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
* trimming bits */
} LOCOUTCR_b;
};
- __IM uint8_t RESERVED53;
- __IM uint32_t RESERVED54[7];
+ __IM uint8_t RESERVED55;
+ __IM uint32_t RESERVED56[7];
union
{
@@ -20601,7 +22647,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} VBTCMPCR_b;
};
- __IM uint8_t RESERVED55;
+ __IM uint8_t RESERVED57;
union
{
@@ -20615,7 +22661,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 6;
} VBTLVDICR_b;
};
- __IM uint8_t RESERVED56;
+ __IM uint8_t RESERVED58;
union
{
@@ -20627,7 +22673,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 7;
} VBTWCTLR_b;
};
- __IM uint8_t RESERVED57;
+ __IM uint8_t RESERVED59;
union
{
@@ -20762,9 +22808,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
uint8_t : 4;
} VBTBER_b;
};
- __IM uint8_t RESERVED58;
- __IM uint16_t RESERVED59;
- __IM uint32_t RESERVED60[15];
+ __IM uint8_t RESERVED60;
+ __IM uint16_t RESERVED61;
+ __IM uint32_t RESERVED62[15];
union
{
@@ -24056,8 +26102,5627 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
};
} R_OSPI_Type; /*!< Size = 132 (0x84) */
+/* =========================================================================================================================== */
+/* ================ R_ADC_B0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 12-bit A/D Converter (R_ADC_B0)
+ */
+
+typedef struct /*!< (@ 0x40170000) R_ADC_B0 Structure */
+{
+ union
+ {
+ __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */
+
+ struct
+ {
+ __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */
+ uint32_t : 31;
+ } ADCLKENR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */
+
+ struct
+ {
+ __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */
+ uint32_t : 31;
+ } ADCLKSR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */
+
+ struct
+ {
+ __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */
+ uint32_t : 14;
+ __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */
+ uint32_t : 13;
+ } ADCLKCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */
+
+ struct
+ {
+ __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */
+ uint32_t : 5;
+ __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */
+ __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */
+ uint32_t : 14;
+ } ADSYCR_b;
+ };
+ __IM uint32_t RESERVED[4];
+
+ union
+ {
+ __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */
+ __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */
+ uint32_t : 30;
+ } ADERINTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */
+ __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */
+ uint32_t : 30;
+ } ADOVFINTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */
+ __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */
+ uint32_t : 14;
+ } ADCALINTCR_b;
+ };
+ __IM uint32_t RESERVED1[5];
+
+ union
+ {
+ __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */
+
+ struct
+ {
+ __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */
+ uint32_t : 4;
+ __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */
+ uint32_t : 20;
+ } ADMDR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */
+
+ struct
+ {
+ __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */
+ __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */
+ __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */
+ __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */
+ uint32_t : 4;
+ __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */
+ __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */
+ __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */
+ __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */
+ uint32_t : 20;
+ } ADGSPCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */
+
+ struct
+ {
+ __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */
+ uint32_t : 23;
+ } ADSGER_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */
+
+ struct
+ {
+ __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */
+ uint32_t : 6;
+ } ADSGCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */
+ uint32_t : 6;
+ __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */
+ uint32_t : 6;
+ } ADSGCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */
+ uint32_t : 30;
+ } ADSGCR2_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t ADIEn : 10; /*!< [9..0] Scan Group n Scan End Interrupt Enable */
+ uint32_t : 22;
+ } ADINTCR_b;
+ };
+ __IM uint32_t RESERVED3[24];
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT0_b;
+ };
+ __IM uint32_t RESERVED4;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT1_b;
+ };
+ __IM uint32_t RESERVED5;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT2_b;
+ };
+ __IM uint32_t RESERVED6;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT3_b;
+ };
+ __IM uint32_t RESERVED7;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT4_b;
+ };
+ __IM uint32_t RESERVED8;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT5_b;
+ };
+ __IM uint32_t RESERVED9;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT6_b;
+ };
+ __IM uint32_t RESERVED10;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT7_b;
+ };
+ __IM uint32_t RESERVED11;
+
+ union
+ {
+ __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */
+
+ struct
+ {
+ __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */
+ __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */
+ uint32_t : 30;
+ } ADTRGEXT8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */
+
+ struct
+ {
+ __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */
+ uint32_t : 26;
+ } ADTRGELC8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */
+
+ struct
+ {
+ __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */
+ uint32_t : 6;
+ __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */
+ uint32_t : 6;
+ } ADTRGGPT8_b;
+ };
+ __IM uint32_t RESERVED12[29];
+
+ union
+ {
+ __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ } ADTRGDLR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */
+
+ struct
+ {
+ __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ } ADTRGDLR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */
+
+ struct
+ {
+ __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ } ADTRGDLR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */
+
+ struct
+ {
+ __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */
+ uint32_t : 8;
+ } ADTRGDLR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */
+
+ struct
+ {
+ __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */
+ uint32_t : 24;
+ } ADTRGDLR4_b;
+ };
+ __IM uint32_t RESERVED13[11];
+
+ union
+ {
+ __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register
+ * 1 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register
+ * 2 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register
+ * 3 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register
+ * 4 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register
+ * 5 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register
+ * 6 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register
+ * 7 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register
+ * 8 */
+
+ struct
+ {
+ __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */
+ uint32_t : 13;
+ __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */
+ uint32_t : 3;
+ __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */
+ __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */
+ uint32_t : 2;
+ __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */
+ uint32_t : 4;
+ } ADSGDCR8_b;
+ };
+ __IM uint32_t RESERVED14[7];
+
+ union
+ {
+ __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */
+
+ struct
+ {
+ __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */
+ uint32_t : 6;
+ __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */
+ uint32_t : 6;
+ } ADSSTR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */
+ uint32_t : 6;
+ __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */
+ uint32_t : 6;
+ } ADSSTR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */
+
+ struct
+ {
+ __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */
+ uint32_t : 6;
+ __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */
+ uint32_t : 6;
+ } ADSSTR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */
+
+ struct
+ {
+ __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */
+ uint32_t : 6;
+ __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */
+ uint32_t : 6;
+ } ADSSTR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */
+
+ struct
+ {
+ __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */
+ uint32_t : 6;
+ __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */
+ uint32_t : 6;
+ } ADSSTR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */
+
+ struct
+ {
+ __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */
+ uint32_t : 6;
+ __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */
+ uint32_t : 6;
+ } ADSSTR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */
+
+ struct
+ {
+ __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */
+ uint32_t : 6;
+ __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */
+ uint32_t : 6;
+ } ADSSTR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */
+
+ struct
+ {
+ __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */
+ uint32_t : 6;
+ __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */
+ uint32_t : 6;
+ } ADSSTR7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */
+
+ struct
+ {
+ __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */
+ uint32_t : 2;
+ __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */
+ uint32_t : 18;
+ } ADCNVSTR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */
+
+ struct
+ {
+ __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */
+ uint32_t : 6;
+ __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */
+ uint32_t : 10;
+ } ADCALSTCR_b;
+ };
+ __IM uint32_t RESERVED15[6];
+
+ union
+ {
+ __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control
+ * Register 0 */
+
+ struct
+ {
+ __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */
+ __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */
+ __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */
+ uint32_t : 29;
+ } ADSHCR0_b;
+ };
+ __IM uint32_t RESERVED16;
+
+ union
+ {
+ __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State
+ * Register 0 */
+
+ struct
+ {
+ __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */
+ uint32_t : 8;
+ __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to
+ * 2 */
+ uint32_t : 13;
+ } ADSHSTR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control
+ * Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */
+ __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */
+ __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */
+ uint32_t : 29;
+ } ADSHCR1_b;
+ };
+ __IM uint32_t RESERVED17;
+
+ union
+ {
+ __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State
+ * Register 1 */
+
+ struct
+ {
+ __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */
+ uint32_t : 8;
+ __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to
+ * 6 */
+ uint32_t : 13;
+ } ADSHSTR1_b;
+ };
+ __IM uint32_t RESERVED18[6];
+
+ union
+ {
+ __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration
+ * State Register */
+
+ struct
+ {
+ __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling
+ * Time Configuration */
+ uint32_t : 8;
+ __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration
+ * Holding Time Configuration */
+ uint32_t : 13;
+ } ADCALSHCR_b;
+ };
+ __IM uint32_t RESERVED19[3];
+
+ union
+ {
+ __IOM uint32_t ADPGACR[4]; /*!< (@ 0x000002C0) Programmable Gain Amplifier Control Register
+ * [0..3] */
+
+ struct
+ {
+ uint32_t : 1;
+ __IOM uint32_t PGADEN : 1; /*!< [1..1] PGA Unit n Input Mode Select */
+ __IOM uint32_t PGASEL1 : 1; /*!< [2..2] PGA Unit n Transit Enable */
+ __IOM uint32_t PGAENAMP : 1; /*!< [3..3] PGA Unit n Enable */
+ uint32_t : 12;
+ __IOM uint32_t PGAGEN : 1; /*!< [16..16] PGA Unit n Gain Setting Enable */
+ uint32_t : 3;
+ __IOM uint32_t PGADG : 2; /*!< [21..20] PGA Unit n Differential Input Gain Setting */
+ uint32_t : 2;
+ __IOM uint32_t PGAGAIN : 4; /*!< [27..24] PGA Unit n Gain Setting */
+ uint32_t : 4;
+ } ADPGACR_b[4];
+ };
+ __IM uint32_t RESERVED20[12];
+
+ union
+ {
+ __IOM uint32_t ADPGAMONCR; /*!< (@ 0x00000300) Programable Gain Amp Monitor Output Control Register */
+
+ struct
+ {
+ __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Signal Selection */
+ uint32_t : 13;
+ __IOM uint32_t MONSEL0 : 1; /*!< [16..16] PGA Unit 0 Monitor Output Enable */
+ __IOM uint32_t MONSEL1 : 1; /*!< [17..17] PGA Unit 1 Monitor Output Enable */
+ __IOM uint32_t MONSEL2 : 1; /*!< [18..18] PGA Unit 2 Monitor Output Enable */
+ __IOM uint32_t MONSEL3 : 1; /*!< [19..19] PGA Unit 3 Monitor Output Enable */
+ uint32_t : 12;
+ } ADPGAMONCR_b;
+ };
+ __IM uint32_t RESERVED21[7];
+
+ union
+ {
+ __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */
+
+ struct
+ {
+ __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */
+ uint32_t : 31;
+ } ADREFCR_b;
+ };
+ __IM uint32_t RESERVED22[15];
+
+ union
+ {
+ __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */
+
+ struct
+ {
+ __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */
+ uint32_t : 16;
+ } ADUOFTR7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */
+
+ struct
+ {
+ __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */
+ uint32_t : 8;
+ } ADUGTR7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */
+ uint32_t : 23;
+ } ADLIMINTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */
+
+ struct
+ {
+ __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */
+ __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */
+ } ADLIMTR7_b;
+ };
+ __IM uint32_t RESERVED23[15];
+
+ union
+ {
+ __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */
+
+ struct
+ {
+ __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */
+ uint32_t : 24;
+ } ADCMPENR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */
+
+ struct
+ {
+ __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */
+ uint32_t : 28;
+ } ADCMPINTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */
+ uint32_t : 14;
+ __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */
+ uint32_t : 8;
+ } ADCCMPCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register
+ * 1 */
+
+ struct
+ {
+ __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */
+ uint32_t : 14;
+ __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */
+ uint32_t : 8;
+ } ADCCMPCR1_b;
+ };
+ __IM uint32_t RESERVED24[14];
+
+ union
+ {
+ __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */
+
+ struct
+ {
+ __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */
+ uint32_t : 6;
+ } ADCMPMDR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */
+ uint32_t : 6;
+ } ADCMPMDR1_b;
+ };
+ __IM uint32_t RESERVED25[2];
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */
+
+ struct
+ {
+ __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */
+ __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */
+ } ADCMPTBR7_b;
+ };
+ __IM uint32_t RESERVED26[18];
+
+ union
+ {
+ __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */
+
+ struct
+ {
+ __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */
+ __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */
+ __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */
+ __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */
+ __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */
+ __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */
+ __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */
+ __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */
+ __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */
+ uint32_t : 23;
+ } ADFIFOCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */
+
+ struct
+ {
+ __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */
+ __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */
+ uint32_t : 23;
+ } ADFIFOINTCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */
+
+ struct
+ {
+ __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ } ADFIFOINTLR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */
+
+ struct
+ {
+ __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ } ADFIFOINTLR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */
+
+ struct
+ {
+ __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ } ADFIFOINTLR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */
+
+ struct
+ {
+ __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */
+ uint32_t : 12;
+ } ADFIFOINTLR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */
+
+ struct
+ {
+ __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */
+ uint32_t : 28;
+ } ADFIFOINTLR4_b;
+ };
+ __IM uint32_t RESERVED27[73];
+
+ union
+ {
+ __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register
+ * 0 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register
+ * 0 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register
+ * 1 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register
+ * 1 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register
+ * 1 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register
+ * 1 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register
+ * 2 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register
+ * 2 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register
+ * 2 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register
+ * 2 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register
+ * 3 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register
+ * 3 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register
+ * 3 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register
+ * 3 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register
+ * 4 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register
+ * 4 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register
+ * 4 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register
+ * 4 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register
+ * 5 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register
+ * 5 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register
+ * 5 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register
+ * 5 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register
+ * 6 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register
+ * 6 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register
+ * 6 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register
+ * 6 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register
+ * 7 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register
+ * 7 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register
+ * 7 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register
+ * 7 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC7_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register
+ * 8 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register
+ * 8 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register
+ * 8 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register
+ * 8 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC8_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register
+ * 9 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR9_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register
+ * 9 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA9_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register
+ * 9 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB9_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register
+ * 9 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC9_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register
+ * 10 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR10_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register
+ * 10 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA10_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register
+ * 10 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB10_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register
+ * 10 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC10_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register
+ * 11 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR11_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register
+ * 11 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA11_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register
+ * 11 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB11_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register
+ * 11 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC11_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register
+ * 12 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR12_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register
+ * 12 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA12_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register
+ * 12 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB12_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register
+ * 12 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC12_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register
+ * 13 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR13_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register
+ * 13 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA13_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register
+ * 13 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB13_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register
+ * 13 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC13_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register
+ * 14 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR14_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register
+ * 14 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA14_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register
+ * 14 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB14_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register
+ * 14 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC14_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register
+ * 15 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR15_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register
+ * 15 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA15_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register
+ * 15 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB15_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register
+ * 15 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC15_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register
+ * 16 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR16_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register
+ * 16 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA16_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register
+ * 16 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB16_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register
+ * 16 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC16_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register
+ * 17 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR17_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register
+ * 17 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA17_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register
+ * 17 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB17_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register
+ * 17 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC17_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register
+ * 18 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR18_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register
+ * 18 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA18_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register
+ * 18 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB18_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register
+ * 18 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC18_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register
+ * 19 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR19_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register
+ * 19 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA19_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register
+ * 19 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB19_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register
+ * 19 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC19_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register
+ * 20 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR20_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register
+ * 20 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA20_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register
+ * 20 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB20_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register
+ * 20 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC20_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register
+ * 21 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR21_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register
+ * 21 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA21_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register
+ * 21 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB21_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register
+ * 21 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC21_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register
+ * 22 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR22_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register
+ * 22 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA22_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register
+ * 22 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB22_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register
+ * 22 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC22_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register
+ * 23 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR23_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register
+ * 23 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA23_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register
+ * 23 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB23_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register
+ * 23 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC23_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register
+ * 24 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR24_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register
+ * 24 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA24_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register
+ * 24 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB24_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register
+ * 24 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC24_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register
+ * 25 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR25_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register
+ * 25 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA25_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register
+ * 25 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB25_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register
+ * 25 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC25_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register
+ * 26 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR26_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register
+ * 26 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA26_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register
+ * 26 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB26_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register
+ * 26 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC26_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register
+ * 27 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR27_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register
+ * 27 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA27_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register
+ * 27 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB27_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register
+ * 27 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC27_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register
+ * 28 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR28_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register
+ * 28 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA28_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register
+ * 28 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB28_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register
+ * 28 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC28_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register
+ * 29 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR29_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register
+ * 29 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA29_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register
+ * 29 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB29_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register
+ * 29 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC29_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register
+ * 30 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR30_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register
+ * 30 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA30_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register
+ * 30 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB30_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register
+ * 30 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC30_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register
+ * 31 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR31_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register
+ * 31 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA31_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register
+ * 31 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB31_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register
+ * 31 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC31_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register
+ * 32 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR32_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register
+ * 32 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA32_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register
+ * 32 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB32_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register
+ * 32 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC32_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR33; /*!< (@ 0x00000810) A/D Conversion Channel Configuration Register
+ * 33 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR33_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA33; /*!< (@ 0x00000814) A/D Conversion Data Operation Control A Register
+ * 33 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA33_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB33; /*!< (@ 0x00000818) A/D Conversion Data Operation Control B Register
+ * 33 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB33_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC33; /*!< (@ 0x0000081C) A/D Conversion Data Operation Control C Register
+ * 33 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC33_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR34; /*!< (@ 0x00000820) A/D Conversion Channel Configuration Register
+ * 34 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR34_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA34; /*!< (@ 0x00000824) A/D Conversion Data Operation Control A Register
+ * 34 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA34_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB34; /*!< (@ 0x00000828) A/D Conversion Data Operation Control B Register
+ * 34 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB34_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC34; /*!< (@ 0x0000082C) A/D Conversion Data Operation Control C Register
+ * 34 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC34_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR35; /*!< (@ 0x00000830) A/D Conversion Channel Configuration Register
+ * 35 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR35_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA35; /*!< (@ 0x00000834) A/D Conversion Data Operation Control A Register
+ * 35 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA35_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB35; /*!< (@ 0x00000838) A/D Conversion Data Operation Control B Register
+ * 35 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB35_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC35; /*!< (@ 0x0000083C) A/D Conversion Data Operation Control C Register
+ * 35 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC35_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADCHCR36; /*!< (@ 0x00000840) A/D Conversion Channel Configuration Register
+ * 36 */
+
+ struct
+ {
+ __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */
+ uint32_t : 3;
+ __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */
+ __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */
+ __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */
+ uint32_t : 12;
+ } ADCHCR36_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRA36; /*!< (@ 0x00000844) A/D Conversion Data Operation Control A Register
+ * 36 */
+
+ struct
+ {
+ uint32_t : 16;
+ __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */
+ uint32_t : 4;
+ __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */
+ uint32_t : 4;
+ } ADDOPCRA36_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRB36; /*!< (@ 0x00000848) A/D Conversion Data Operation Control B Register
+ * 36 */
+
+ struct
+ {
+ __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */
+ uint32_t : 6;
+ __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */
+ uint32_t : 4;
+ __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */
+ uint32_t : 8;
+ } ADDOPCRB36_b;
+ };
+
+ union
+ {
+ __IOM uint32_t ADDOPCRC36; /*!< (@ 0x0000084C) A/D Conversion Data Operation Control C Register
+ * 36 */
+
+ struct
+ {
+ __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */
+ uint32_t : 12;
+ __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */
+ uint32_t : 2;
+ __IOM uint32_t SIGNSEL : 1; /*!< [20..20] TBD */
+ uint32_t : 11;
+ } ADDOPCRC36_b;
+ };
+ __IM uint32_t RESERVED28[236];
+
+ union
+ {
+ __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */
+
+ struct
+ {
+ __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control
+ * bits */
+ uint32_t : 5;
+ __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control
+ * bits */
+ uint32_t : 21;
+ } ADCALSTR_b;
+ };
+ __IM uint32_t RESERVED29;
+
+ union
+ {
+ __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */
+
+ struct
+ {
+ __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */
+ uint32_t : 23;
+ } ADTRGENR_b;
+ };
+ __IM uint32_t RESERVED30;
+
+ union
+ {
+ __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */
+
+ struct
+ {
+ __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */
+ uint32_t : 23;
+ } ADSYSTR_b;
+ };
+ __IM uint32_t RESERVED31[3];
+
+ union
+ {
+ __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */
+
+ struct
+ {
+ __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */
+ uint32_t : 31;
+ } ADSTR_b[9];
+ };
+ __IM uint32_t RESERVED32[7];
+
+ union
+ {
+ __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */
+
+ struct
+ {
+ __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */
+ uint32_t : 7;
+ __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */
+ uint32_t : 23;
+ } ADSTOPR_b;
+ };
+ __IM uint32_t RESERVED33[7];
+
+ union
+ {
+ __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */
+
+ struct
+ {
+ __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */
+ __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */
+ uint32_t : 14;
+ __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */
+ __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */
+ uint32_t : 14;
+ } ADSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */
+
+ struct
+ {
+ __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */
+ uint32_t : 23;
+ } ADGRSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */
+
+ struct
+ {
+ __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */
+ __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */
+ uint32_t : 30;
+ } ADERSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */
+ __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */
+ uint32_t : 30;
+ } ADERSCR_b;
+ };
+ __IM uint32_t RESERVED34[2];
+
+ union
+ {
+ __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */
+
+ struct
+ {
+ __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */
+ __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */
+ uint32_t : 30;
+ } ADCALENDSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */
+ __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */
+ uint32_t : 30;
+ } ADCALENDSCR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */
+
+ struct
+ {
+ __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */
+ __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */
+ uint32_t : 30;
+ } ADOVFERSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register
+ * 0 */
+
+ struct
+ {
+ __IM uint32_t OFVCHFn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag */
+ uint32_t : 3;
+ } ADOVFCHSR0_b;
+ };
+ __IM uint32_t RESERVED35[2];
+
+ union
+ {
+ __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status
+ * Register */
+
+ struct
+ {
+ __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag bit */
+ __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag bit */
+ __IM uint32_t OVFEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag bit */
+ uint32_t : 2;
+ __IM uint32_t OVFEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag bit */
+ __IM uint32_t OVFEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag bit */
+ __IM uint32_t OVFEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag bit */
+ __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag bit */
+ uint32_t : 23;
+ } ADOVFEXSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */
+ __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */
+ uint32_t : 30;
+ } ADOVFERSCR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear
+ * Register 0 */
+
+ struct
+ {
+ __OM uint32_t OVFCHCn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag Clear */
+ uint32_t : 3;
+ } ADOVFCHSCR0_b;
+ };
+ __IM uint32_t RESERVED36[2];
+
+ union
+ {
+ __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status
+ * Clear Register */
+
+ struct
+ {
+ __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag Clear */
+ __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag Clear */
+ __OM uint32_t OVFEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag Clear */
+ uint32_t : 2;
+ __OM uint32_t OVFEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag Clear */
+ __OM uint32_t OVFEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag Clear */
+ __OM uint32_t OVFEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag Clear */
+ __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag Clear */
+ uint32_t : 23;
+ } ADOVFEXSCR_b;
+ };
+ __IM uint32_t RESERVED37[2];
+
+ union
+ {
+ __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */
+ uint32_t : 12;
+ __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */
+ uint32_t : 12;
+ } ADFIFOSR0_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */
+
+ struct
+ {
+ __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */
+ uint32_t : 12;
+ __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */
+ uint32_t : 12;
+ } ADFIFOSR1_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */
+
+ struct
+ {
+ __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */
+ uint32_t : 12;
+ __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */
+ uint32_t : 12;
+ } ADFIFOSR2_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */
+
+ struct
+ {
+ __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */
+ uint32_t : 12;
+ __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */
+ uint32_t : 12;
+ } ADFIFOSR3_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */
+
+ struct
+ {
+ __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */
+ uint32_t : 28;
+ } ADFIFOSR4_b;
+ };
+ __IM uint32_t RESERVED38[3];
+
+ union
+ {
+ __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */
+
+ struct
+ {
+ __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */
+ uint32_t : 23;
+ } ADFIFODCR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */
+
+ struct
+ {
+ __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */
+ uint32_t : 7;
+ __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */
+ uint32_t : 7;
+ } ADFIFOERSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */
+ uint32_t : 7;
+ __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */
+ uint32_t : 7;
+ } ADFIFOERSCR_b;
+ };
+ __IM uint32_t RESERVED39;
+
+ union
+ {
+ __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */
+
+ struct
+ {
+ __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */
+ uint32_t : 24;
+ } ADCMPTBSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */
+ uint32_t : 24;
+ } ADCMPTBSCR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t CMPCHFn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag */
+ uint32_t : 3;
+ } ADCMPCHSR0_b;
+ };
+ __IM uint32_t RESERVED40[2];
+
+ union
+ {
+ __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */
+
+ struct
+ {
+ __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag */
+ __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag */
+ __IM uint32_t CMPEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag */
+ uint32_t : 2;
+ __IM uint32_t CMPEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag */
+ __IM uint32_t CMPEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag */
+ __IM uint32_t CMPEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag */
+ __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag */
+ uint32_t : 23;
+ } ADCMPEXSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */
+
+ struct
+ {
+ __OM uint32_t CMPCHCn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag Clear bit */
+ uint32_t : 3;
+ } ADCMPCHSCR0_b;
+ };
+ __IM uint32_t RESERVED41[2];
+
+ union
+ {
+ __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag Clear bit */
+ __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag Clear
+ * bit */
+ __OM uint32_t CMPEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag
+ * Clear bit */
+ uint32_t : 2;
+ __OM uint32_t CMPEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag Clear bit */
+ __OM uint32_t CMPEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag Clear bit */
+ __OM uint32_t CMPEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag Clear bit */
+ __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag Clear bit */
+ uint32_t : 23;
+ } ADCMPEXSCR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */
+
+ struct
+ {
+ __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */
+ uint32_t : 23;
+ } ADLIMGRSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t LIMCHFn : 29; /*!< [28..0] Analog Channel No. n : Limiter Clip Flag bit */
+ uint32_t : 3;
+ } ADLIMCHSR0_b;
+ };
+ __IM uint32_t RESERVED42[2];
+
+ union
+ {
+ __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */
+
+ struct
+ {
+ __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag bit */
+ __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag bit */
+ __IM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
+ * bit */
+ uint32_t : 2;
+ __IM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag bit */
+ __IM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag bit */
+ __IM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag bit */
+ __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag bit */
+ uint32_t : 23;
+ } ADLIMEXSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */
+ uint32_t : 23;
+ } ADLIMGRSCR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */
+
+ struct
+ {
+ __OM uint32_t LIMCHCn : 29; /*!< [28..0] Analog Channel No. n Limiter Clip Flag Clear bit */
+ uint32_t : 3;
+ } ADLIMCHSCR0_b;
+ };
+ __IM uint32_t RESERVED43[2];
+
+ union
+ {
+ __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag Clear */
+ __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag Clear */
+ __OM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
+ * Clear */
+ uint32_t : 2;
+ __OM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag Clear */
+ __OM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag Clear */
+ __OM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag Clear */
+ __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag Clear */
+ uint32_t : 23;
+ } ADLIMEXSCR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */
+
+ struct
+ {
+ __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */
+ uint32_t : 23;
+ } ADSCANENDSR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */
+
+ struct
+ {
+ __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */
+ uint32_t : 23;
+ } ADSCANENDSCR_b;
+ };
+ __IM uint32_t RESERVED44[170];
+
+ union
+ {
+ __IM uint32_t ADDR[29]; /*!< (@ 0x00001000) A/D Data Register [0..28] */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */
+ uint32_t : 15;
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */
+ } ADDR_b[29];
+ };
+ __IM uint32_t RESERVED45[67];
+
+ union
+ {
+ __IM uint32_t ADEXDR[9]; /*!< (@ 0x00001180) A/D Extended Analog Data Register [0..8] */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */
+ uint32_t : 8;
+ __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */
+ uint32_t : 4;
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */
+ } ADEXDR_b[9];
+ };
+ __IM uint32_t RESERVED46[23];
+
+ union
+ {
+ __IM uint32_t ADFIFODR0; /*!< (@ 0x00001200) FIFO Data Register 0 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR0_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR1; /*!< (@ 0x00001204) FIFO Data Register 1 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR1_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR2; /*!< (@ 0x00001208) FIFO Data Register 2 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR2_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR3; /*!< (@ 0x0000120C) FIFO Data Register 3 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR3_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR4; /*!< (@ 0x00001210) FIFO Data Register 4 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR4_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR5; /*!< (@ 0x00001214) FIFO Data Register 5 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR5_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR6; /*!< (@ 0x00001218) FIFO Data Register 6 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR6_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR7; /*!< (@ 0x0000121C) FIFO Data Register 7 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR7_b;
+ };
+
+ union
+ {
+ __IM uint32_t ADFIFODR8; /*!< (@ 0x00001220) FIFO Data Register 8 */
+
+ struct
+ {
+ __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */
+ uint32_t : 8;
+ __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */
+ __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */
+ } ADFIFODR8_b;
+ };
+} R_ADC_B0_Type; /*!< Size = 4644 (0x1224) */
+
+/* =========================================================================================================================== */
+/* ================ R_DOC_B ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC_B)
+ */
+
+typedef struct /*!< (@ 0x40109000) R_DOC_B Structure */
+{
+ union
+ {
+ __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
+
+ struct
+ {
+ __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
+ uint8_t : 1;
+ __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */
+ __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */
+ __IOM uint8_t DOPCIE : 1; /*!< [7..7] Data Operation Circuit Interrupt Enable */
+ } DOCR_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */
+
+ struct
+ {
+ __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */
+ uint8_t : 7;
+ } DOSR_b;
+ };
+ __IM uint8_t RESERVED2;
+ __IM uint16_t RESERVED3;
+
+ union
+ {
+ __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */
+
+ struct
+ {
+ __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */
+ uint8_t : 7;
+ } DOSCR_b;
+ };
+ __IM uint8_t RESERVED4;
+ __IM uint16_t RESERVED5;
+ __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */
+ __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */
+ __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */
+} R_DOC_B_Type; /*!< Size = 24 (0x18) */
+
+/* =========================================================================================================================== */
+/* ================ R_SCI_B0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communication Interface 0 (R_SCI_B0)
+ */
+
+typedef struct /*!< (@ 0x40118000) R_SCI_B0 Structure */
+{
+ union
+ {
+ __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */
+
+ struct
+ {
+ __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */
+ __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */
+ __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */
+ __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */
+ __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */
+ uint32_t : 11;
+ __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */
+ uint32_t : 2;
+ __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */
+ __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */
+ uint32_t : 3;
+ } RDR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */
+
+ struct
+ {
+ __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */
+ __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */
+ uint32_t : 2;
+ __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */
+ uint32_t : 19;
+ } TDR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */
+
+ struct
+ {
+ __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */
+ uint32_t : 3;
+ __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */
+ uint32_t : 3;
+ __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */
+ __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */
+ __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */
+ uint32_t : 5;
+ __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */
+ uint32_t : 3;
+ __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */
+ __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */
+ uint32_t : 2;
+ __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */
+ uint32_t : 7;
+ } CCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */
+ __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */
+ uint32_t : 2;
+ __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */
+ __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */
+ uint32_t : 2;
+ __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */
+ __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */
+ uint32_t : 2;
+ __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */
+ __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */
+ uint32_t : 2;
+ __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */
+ uint32_t : 3;
+ __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */
+ uint32_t : 3;
+ __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */
+ uint32_t : 1;
+ __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */
+ uint32_t : 3;
+ } CCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */
+ uint32_t : 1;
+ __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */
+ __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */
+ __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */
+ uint32_t : 1;
+ __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */
+ __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */
+ uint32_t : 3;
+ __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */
+ uint32_t : 2;
+ __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */
+ } CCR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */
+ uint32_t : 5;
+ __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */
+ __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */
+ uint32_t : 2;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */
+ __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */
+ __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */
+ __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */
+ __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */
+ __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */
+ __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */
+ __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */
+ uint32_t : 2;
+ __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */
+ uint32_t : 2;
+ __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */
+ __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */
+ uint32_t : 2;
+ } CCR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */
+
+ struct
+ {
+ __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */
+ uint32_t : 7;
+ __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */
+ __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */
+ uint32_t : 6;
+ __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */
+ __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */
+ __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */
+ __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */
+ } CCR4_b;
+ };
+
+ union
+ {
+ __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */
+
+ struct
+ {
+ __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */
+ uint8_t : 3;
+ __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */
+ uint8_t : 3;
+ } CESR_b;
+ };
+ __IM uint8_t RESERVED;
+ __IM uint16_t RESERVED1;
+
+ union
+ {
+ __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */
+
+ struct
+ {
+ __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */
+ uint32_t : 3;
+ __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */
+ __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */
+ uint32_t : 3;
+ __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */
+ uint32_t : 2;
+ __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */
+ __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */
+ __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */
+ uint32_t : 1;
+ __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */
+ __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */
+ uint32_t : 8;
+ } ICR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */
+
+ struct
+ {
+ __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */
+ uint32_t : 7;
+ __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */
+ uint32_t : 2;
+ __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */
+ __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */
+ uint32_t : 2;
+ __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */
+ __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */
+ uint32_t : 3;
+ } FCR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */
+
+ struct
+ {
+ __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */
+ __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */
+ __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */
+ uint32_t : 1;
+ __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */
+ __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */
+ __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */
+ uint32_t : 1;
+ __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */
+ __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */
+ uint32_t : 2;
+ __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */
+ __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */
+ uint32_t : 2;
+ __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */
+ __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */
+ __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */
+ uint32_t : 5;
+ } MCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */
+
+ struct
+ {
+ __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */
+ uint32_t : 7;
+ __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */
+ uint32_t : 3;
+ __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */
+ uint32_t : 11;
+ } DCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */
+
+ struct
+ {
+ __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */
+ uint32_t : 6;
+ __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */
+ __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */
+ __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */
+ __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */
+ __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */
+ __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */
+ __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */
+ uint32_t : 2;
+ __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */
+ __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */
+ __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */
+ uint32_t : 1;
+ __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */
+ uint32_t : 6;
+ } XCR0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */
+
+ struct
+ {
+ __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */
+ uint32_t : 3;
+ __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */
+ __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */
+ uint32_t : 2;
+ __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */
+ __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */
+ __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */
+ } XCR1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */
+ __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */
+ __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */
+ } XCR2_b;
+ };
+ __IM uint32_t RESERVED3[2];
+
+ union
+ {
+ __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */
+
+ struct
+ {
+ uint32_t : 4;
+ __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
+ uint32_t : 10;
+ __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */
+ __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */
+ __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */
+ __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */
+ uint32_t : 5;
+ __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */
+ uint32_t : 1;
+ __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */
+ __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */
+ __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */
+ __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */
+ __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */
+ __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */
+ } CSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */
+
+ struct
+ {
+ __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
+ uint32_t : 2;
+ __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+ * Flag */
+ uint32_t : 28;
+ } ISR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */
+
+ struct
+ {
+ __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */
+ uint32_t : 7;
+ __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */
+ uint32_t : 2;
+ __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */
+ uint32_t : 2;
+ __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */
+ uint32_t : 2;
+ } FRSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */
+
+ struct
+ {
+ __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */
+ uint32_t : 26;
+ } FTSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */
+
+ struct
+ {
+ __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */
+ __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */
+ __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */
+ uint32_t : 1;
+ __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */
+ uint32_t : 1;
+ __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */
+ uint32_t : 25;
+ } MSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */
+
+ struct
+ {
+ __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */
+ __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */
+ uint32_t : 6;
+ __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */
+ __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */
+ __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */
+ __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */
+ __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */
+ __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */
+ __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */
+ __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */
+ __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */
+ __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */
+ } XSR0_b;
+ };
+
+ union
+ {
+ __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */
+
+ struct
+ {
+ __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */
+ uint32_t : 16;
+ } XSR1_b;
+ };
+ __IM uint32_t RESERVED4;
+
+ union
+ {
+ __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */
+
+ struct
+ {
+ uint32_t : 4;
+ __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */
+ uint32_t : 11;
+ __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */
+ __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */
+ __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */
+ uint32_t : 5;
+ __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */
+ uint32_t : 1;
+ __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */
+ __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */
+ __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */
+ __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */
+ uint32_t : 1;
+ __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */
+ } CFCLR_b;
+ };
+
+ union
+ {
+ __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */
+
+ struct
+ {
+ uint32_t : 3;
+ __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */
+ uint32_t : 28;
+ } ICFCLR_b;
+ };
+
+ union
+ {
+ __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */
+
+ struct
+ {
+ __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */
+ uint32_t : 31;
+ } FFCLR_b;
+ };
+
+ union
+ {
+ __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */
+
+ struct
+ {
+ __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */
+ __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */
+ __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */
+ uint32_t : 1;
+ __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */
+ uint32_t : 27;
+ } MFCLR_b;
+ };
+
+ union
+ {
+ __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */
+ __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */
+ __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */
+ __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */
+ __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */
+ __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */
+ __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */
+ __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */
+ uint32_t : 16;
+ } XFCLR_b;
+ };
+} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */
+
+/* =========================================================================================================================== */
+/* ================ R_SPI_B0 ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface 0 (R_SPI_B0)
+ */
+
+typedef struct /*!< (@ 0x4011A000) R_SPI_B0 Structure */
+{
+ __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */
+
+ union
+ {
+ __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */
+
+ struct
+ {
+ __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */
+ uint32_t : 5;
+ __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */
+ uint32_t : 5;
+ __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */
+ uint32_t : 5;
+ __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */
+ uint32_t : 5;
+ } SPDECR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */
+
+ struct
+ {
+ __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */
+ uint32_t : 6;
+ __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */
+ __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */
+ __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */
+ uint32_t : 1;
+ __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */
+ __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */
+ __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */
+ __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */
+ uint32_t : 1;
+ __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */
+ __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */
+ __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */
+ __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */
+ __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */
+ __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */
+ uint32_t : 2;
+ __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */
+ __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */
+ uint32_t : 2;
+ __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */
+ __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */
+ __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */
+ } SPCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */
+ uint32_t : 1;
+ __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */
+ __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */
+ __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */
+ __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */
+ __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */
+ uint32_t : 2;
+ __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */
+ __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */
+ uint32_t : 10;
+ } SPCR2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */
+
+ struct
+ {
+ __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */
+ __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */
+ __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */
+ __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */
+ uint32_t : 4;
+ __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */
+ uint32_t : 8;
+ __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */
+ uint32_t : 5;
+ } SPCR3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD0_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD1_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD2_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD3_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD4_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD5_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD6_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */
+
+ struct
+ {
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
+ uint32_t : 3;
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
+ uint32_t : 4;
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
+ uint32_t : 3;
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
+ uint32_t : 5;
+ } SPCMD7_b;
+ };
+ __IM uint32_t RESERVED[3];
+
+ union
+ {
+ __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */
+
+ struct
+ {
+ __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
+ uint32_t : 2;
+ __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */
+ __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */
+ uint32_t : 3;
+ __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */
+ uint32_t : 22;
+ } SPDCR_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */
+
+ struct
+ {
+ __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */
+ uint32_t : 6;
+ __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */
+ uint32_t : 22;
+ } SPDCR2_b;
+ };
+ __IM uint32_t RESERVED1[2];
+
+ union
+ {
+ __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */
+
+ struct
+ {
+ uint32_t : 8;
+ __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */
+ uint32_t : 1;
+ __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */
+ uint32_t : 8;
+ __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */
+ __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */
+ __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */
+ __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */
+ __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */
+ __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */
+ __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */
+ __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */
+ __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */
+ } SPSR_b;
+ };
+ __IM uint32_t RESERVED2;
+
+ union
+ {
+ __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */
+
+ struct
+ {
+ __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */
+ uint32_t : 29;
+ } SPTFSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */
+
+ struct
+ {
+ __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */
+ uint32_t : 29;
+ } SPRFSR_b;
+ };
+
+ union
+ {
+ __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */
+
+ struct
+ {
+ __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */
+ uint32_t : 31;
+ } SPPSR_b;
+ };
+ __IM uint32_t RESERVED3;
+
+ union
+ {
+ __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */
+
+ struct
+ {
+ uint32_t : 23;
+ __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */
+ __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */
+ uint32_t : 1;
+ __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */
+ __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */
+ __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */
+ __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */
+ __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */
+ __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */
+ } SPSRC_b;
+ };
+
+ union
+ {
+ __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */
+
+ struct
+ {
+ __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */
+ uint32_t : 31;
+ } SPFCR_b;
+ };
+} R_SPI_B0_Type; /*!< Size = 112 (0x70) */
+
+/* =========================================================================================================================== */
+/* ================ R_TFU ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Trigonometric Function Unit (TFU) (R_TFU)
+ */
+
+typedef struct /*!< (@ 0x90003000) R_TFU Structure */
+{
+ __IM uint32_t RESERVED[4];
+
+ union
+ {
+ __IOM float SCDT0; /*!< (@ 0x00000010) TBD */
+
+ struct
+ {
+ __IOM uint32_t SCDT0 : 32; /*!< [31..0] TBD */
+ } SCDT0_b;
+ };
+
+ union
+ {
+ __IOM float SCDT1; /*!< (@ 0x00000014) TBD */
+
+ struct
+ {
+ __IOM uint32_t SCDT1 : 32; /*!< [31..0] TBD */
+ } SCDT1_b;
+ };
+
+ union
+ {
+ __IOM float ATDT0; /*!< (@ 0x00000018) TBD */
+
+ struct
+ {
+ __IOM uint32_t ATDT0 : 32; /*!< [31..0] TBD */
+ } ATDT0_b;
+ };
+
+ union
+ {
+ __IOM float ATDT1; /*!< (@ 0x0000001C) TBD */
+
+ struct
+ {
+ __IOM uint32_t ATDT1 : 32; /*!< [31..0] TBD */
+ } ATDT1_b;
+ };
+} R_TFU_Type; /*!< Size = 32 (0x20) */
+
/** @} */ /* End of group Device_Peripheral_peripherals */
+ #ifdef BSP_OVERRIDE_REG_HEADER
+ #include BSP_OVERRIDE_REG_HEADER
+ #endif
+
#include "base_addresses.h"
/* ========================================= End of section using anonymous unions ========================================= */
@@ -24640,6 +32305,355 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
#define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
+/* =========================================================================================================================== */
+/* ================ CFDC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= NCFG ========================================================== */
+ #define R_CANFDL_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */
+ #define R_CANFDL_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */
+ #define R_CANFDL_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */
+ #define R_CANFDL_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */
+ #define R_CANFDL_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */
+ #define R_CANFDL_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */
+ #define R_CANFDL_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */
+/* ========================================================== CTR ========================================================== */
+ #define R_CANFDL_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */
+ #define R_CANFDL_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */
+ #define R_CANFDL_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */
+ #define R_CANFDL_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+ #define R_CANFDL_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */
+ #define R_CANFDL_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+ #define R_CANFDL_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */
+ #define R_CANFDL_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */
+ #define R_CANFDL_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */
+ #define R_CANFDL_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */
+ #define R_CANFDL_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */
+ #define R_CANFDL_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */
+ #define R_CANFDL_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */
+ #define R_CANFDL_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */
+ #define R_CANFDL_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */
+ #define R_CANFDL_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */
+ #define R_CANFDL_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */
+ #define R_CANFDL_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */
+ #define R_CANFDL_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */
+ #define R_CANFDL_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */
+ #define R_CANFDL_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */
+ #define R_CANFDL_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
+/* ========================================================== STS ========================================================== */
+ #define R_CANFDL_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */
+ #define R_CANFDL_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */
+ #define R_CANFDL_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */
+ #define R_CANFDL_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */
+ #define R_CANFDL_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */
+ #define R_CANFDL_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */
+ #define R_CANFDL_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */
+ #define R_CANFDL_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */
+ #define R_CANFDL_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */
+ #define R_CANFDL_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */
+ #define R_CANFDL_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */
+ #define R_CANFDL_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERFL ========================================================== */
+ #define R_CANFDL_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */
+ #define R_CANFDL_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */
+ #define R_CANFDL_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */
+ #define R_CANFDL_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */
+ #define R_CANFDL_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */
+ #define R_CANFDL_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */
+ #define R_CANFDL_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */
+ #define R_CANFDL_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */
+ #define R_CANFDL_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */
+ #define R_CANFDL_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */
+ #define R_CANFDL_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */
+ #define R_CANFDL_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */
+ #define R_CANFDL_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */
+ #define R_CANFDL_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */
+ #define R_CANFDL_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */
+ #define R_CANFDL_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */
+ #define R_CANFDL_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DCFG ========================================================== */
+ #define R_CANFDL_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */
+ #define R_CANFDL_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */
+ #define R_CANFDL_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */
+ #define R_CANFDL_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */
+ #define R_CANFDL_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */
+ #define R_CANFDL_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */
+ #define R_CANFDL_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDCFG ========================================================= */
+ #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */
+ #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */
+ #define R_CANFDL_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */
+ #define R_CANFDL_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */
+ #define R_CANFDL_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */
+ #define R_CANFDL_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */
+ #define R_CANFDL_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */
+/* ========================================================= FDCTR ========================================================= */
+ #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */
+ #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */
+ #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFDL_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
+ #define R_CANFDL_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */
+ #define R_CANFDL_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */
+ #define R_CANFDL_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */
+ #define R_CANFDL_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */
+ #define R_CANFDL_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */
+ #define R_CANFDL_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */
+/* ========================================================= FDCRC ========================================================= */
+ #define R_CANFDL_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */
+ #define R_CANFDL_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */
+ #define R_CANFDL_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */
+ #define R_CANFDL_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ CFDGAFL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFDL_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */
+ #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */
+/* =========================================================== M =========================================================== */
+ #define R_CANFDL_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */
+ #define R_CANFDL_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */
+ #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */
+ #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */
+ #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */
+/* ========================================================== P0 =========================================================== */
+ #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */
+ #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== P1 =========================================================== */
+ #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */
+ #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDTHL ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= ACC0 ========================================================== */
+ #define R_CANFDL_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */
+ #define R_CANFDL_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */
+ #define R_CANFDL_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */
+ #define R_CANFDL_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */
+ #define R_CANFDL_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */
+/* ========================================================= ACC1 ========================================================== */
+ #define R_CANFDL_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */
+ #define R_CANFDL_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */
+ #define R_CANFDL_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */
+ #define R_CANFDL_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */
+
+/* =========================================================================================================================== */
+/* ================ CFDRF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFDL_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */
+ #define R_CANFDL_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */
+ #define R_CANFDL_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */
+ #define R_CANFDL_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFDL_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */
+ #define R_CANFDL_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFDL_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */
+ #define R_CANFDL_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFDL_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */
+ #define R_CANFDL_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */
+ #define R_CANFDL_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */
+ #define R_CANFDL_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */
+ #define R_CANFDL_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */
+ #define R_CANFDL_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFDL_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */
+ #define R_CANFDL_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDCF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFDL_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */
+ #define R_CANFDL_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */
+ #define R_CANFDL_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */
+ #define R_CANFDL_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFDL_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */
+ #define R_CANFDL_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFDL_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */
+ #define R_CANFDL_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFDL_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */
+ #define R_CANFDL_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */
+ #define R_CANFDL_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */
+ #define R_CANFDL_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */
+ #define R_CANFDL_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */
+ #define R_CANFDL_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFDL_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */
+ #define R_CANFDL_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDTM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFDL_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */
+ #define R_CANFDL_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */
+ #define R_CANFDL_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */
+ #define R_CANFDL_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFDL_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */
+ #define R_CANFDL_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFDL_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */
+ #define R_CANFDL_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDCTR ========================================================= */
+ #define R_CANFDL_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */
+ #define R_CANFDL_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */
+ #define R_CANFDL_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */
+ #define R_CANFDL_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */
+ #define R_CANFDL_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */
+ #define R_CANFDL_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFDL_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
+ #define R_CANFDL_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ RM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ID =========================================================== */
+ #define R_CANFDL_CFDRMC_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */
+ #define R_CANFDL_CFDRMC_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */
+ #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */
+ #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */
+ #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */
+/* ========================================================== PTR ========================================================== */
+ #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */
+ #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */
+ #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */
+ #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */
+/* ========================================================= FDSTS ========================================================= */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */
+ #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */
+/* ========================================================== DF =========================================================== */
+ #define R_CANFDL_CFDRMC_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */
+ #define R_CANFDL_CFDRMC_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */
+
+/* =========================================================================================================================== */
+/* ================ CFDRMC ================ */
+/* =========================================================================================================================== */
+
/* =========================================================================================================================== */
/* ================ ELSEGR ================ */
/* =========================================================================================================================== */
@@ -25276,6 +33290,89 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
#define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
+/* =========================================================================================================================== */
+/* ================ CSa ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== MOD ========================================================== */
+ #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
+ #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
+ #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
+ #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
+ #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
+ #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
+/* ========================================================= WCR1 ========================================================== */
+ #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
+ #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
+ #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
+ #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
+ #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
+ #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
+/* ========================================================= WCR2 ========================================================== */
+ #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
+ #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
+ #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
+ #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
+ #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
+ #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
+ #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
+ #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
+ #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
+ #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
+ #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
+
+/* =========================================================================================================================== */
+/* ================ CSb ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+ #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
+ #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
+ #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
+ #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
+ #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
+ #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
+/* ========================================================== REC ========================================================== */
+ #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
+ #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
+ #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
+ #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
+
+/* =========================================================================================================================== */
+/* ================ BUSERR ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== ADD ========================================================== */
+ #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
+ #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ERRRW ========================================================= */
+ #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */
+ #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ BUSTZFERR ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== TZFADD ========================================================= */
+ #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */
+ #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= TZFERRRW ======================================================== */
+ #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */
+ #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */
+
/* =========================================================================================================================== */
/* ================ PIPE_TR ================ */
/* =========================================================================================================================== */
@@ -25504,6 +33601,9 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
/* ======================================================== ADSHMSR ======================================================== */
#define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */
#define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */
+/* ======================================================== ADACSR ========================================================= */
+ #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */
+ #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */
/* ======================================================== ADGSPCR ======================================================== */
#define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */
#define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */
@@ -25874,8 +33974,6 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
/* ======================================================= ADREFMON ======================================================== */
#define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
#define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
- #define R_ADC0_ADREFMON_MONSEL_Pos (4UL) /*!< MONSEL (Bit 4) */
- #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */
/* =========================================================================================================================== */
/* ================ R_PSCU ================ */
@@ -25941,6 +34039,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */
#define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */
+ #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */
#define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */
@@ -25966,10 +34066,20 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */
#define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */
+ #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */
#define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */
#define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */
#define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */
+ #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */
+ #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */
+ #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */
+ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */
+ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */
/* ========================================================= PSARE ========================================================= */
#define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */
#define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */
@@ -26100,6 +34210,75 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */
#define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
+/* =========================================================================================================================== */
+/* ================ R_AGTW0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== AGT ========================================================== */
+ #define R_AGTW0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
+ #define R_AGTW0_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== AGTCMA ========================================================= */
+ #define R_AGTW0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
+ #define R_AGTW0_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== AGTCMB ========================================================= */
+ #define R_AGTW0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
+ #define R_AGTW0_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= AGTCR ========================================================= */
+ #define R_AGTW0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
+ #define R_AGTW0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
+ #define R_AGTW0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
+ #define R_AGTW0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */
+ #define R_AGTW0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
+ #define R_AGTW0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
+ #define R_AGTW0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
+ #define R_AGTW0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTMR1 ========================================================= */
+ #define R_AGTW0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */
+ #define R_AGTW0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */
+ #define R_AGTW0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
+ #define R_AGTW0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */
+ #define R_AGTW0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */
+/* ======================================================== AGTMR2 ========================================================= */
+ #define R_AGTW0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
+ #define R_AGTW0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
+ #define R_AGTW0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
+/* ======================================================== AGTIOC ========================================================= */
+ #define R_AGTW0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */
+ #define R_AGTW0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */
+ #define R_AGTW0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
+ #define R_AGTW0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
+ #define R_AGTW0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
+ #define R_AGTW0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */
+ #define R_AGTW0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTISR ========================================================= */
+ #define R_AGTW0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */
+ #define R_AGTW0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */
+/* ======================================================== AGTCMSR ======================================================== */
+ #define R_AGTW0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
+ #define R_AGTW0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
+ #define R_AGTW0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
+ #define R_AGTW0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
+ #define R_AGTW0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
+ #define R_AGTW0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
+ #define R_AGTW0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
+ #define R_AGTW0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
+/* ======================================================= AGTIOSEL ======================================================== */
+ #define R_AGTW0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */
+ #define R_AGTW0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
+
/* =========================================================================================================================== */
/* ================ R_BUS ================ */
/* =========================================================================================================================== */
@@ -27181,6 +35360,305 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
#define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
+/* =========================================================================================================================== */
+/* ================ R_CANFDL ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== CFDGCFG ======================================================== */
+ #define R_CANFDL_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */
+ #define R_CANFDL_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */
+ #define R_CANFDL_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */
+ #define R_CANFDL_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */
+ #define R_CANFDL_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */
+ #define R_CANFDL_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */
+ #define R_CANFDL_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */
+ #define R_CANFDL_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+ #define R_CANFDL_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */
+ #define R_CANFDL_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */
+ #define R_CANFDL_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */
+/* ======================================================== CFDGCTR ======================================================== */
+ #define R_CANFDL_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */
+ #define R_CANFDL_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */
+ #define R_CANFDL_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */
+ #define R_CANFDL_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */
+ #define R_CANFDL_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */
+ #define R_CANFDL_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */
+ #define R_CANFDL_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */
+ #define R_CANFDL_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */
+/* ======================================================== CFDGSTS ======================================================== */
+ #define R_CANFDL_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */
+ #define R_CANFDL_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */
+ #define R_CANFDL_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */
+ #define R_CANFDL_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */
+ #define R_CANFDL_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGERFL ======================================================== */
+ #define R_CANFDL_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */
+ #define R_CANFDL_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */
+ #define R_CANFDL_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */
+ #define R_CANFDL_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */
+ #define R_CANFDL_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */
+ #define R_CANFDL_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */
+/* ======================================================== CFDGTSC ======================================================== */
+ #define R_CANFDL_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */
+ #define R_CANFDL_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */
+/* ====================================================== CFDGAFLECTR ====================================================== */
+ #define R_CANFDL_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */
+ #define R_CANFDL_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */
+ #define R_CANFDL_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */
+ #define R_CANFDL_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDGAFLCFG0 ====================================================== */
+ #define R_CANFDL_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */
+ #define R_CANFDL_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */
+ #define R_CANFDL_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */
+ #define R_CANFDL_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */
+/* ======================================================== CFDRMNB ======================================================== */
+ #define R_CANFDL_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */
+ #define R_CANFDL_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */
+ #define R_CANFDL_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */
+ #define R_CANFDL_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */
+/* ======================================================= CFDRMND0 ======================================================== */
+ #define R_CANFDL_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */
+ #define R_CANFDL_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */
+/* ======================================================= CFDRMIEC ======================================================== */
+ #define R_CANFDL_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */
+ #define R_CANFDL_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CFDRFCC ======================================================== */
+ #define R_CANFDL_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */
+ #define R_CANFDL_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */
+ #define R_CANFDL_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */
+ #define R_CANFDL_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */
+ #define R_CANFDL_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */
+ #define R_CANFDL_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */
+ #define R_CANFDL_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */
+/* ======================================================= CFDRFSTS ======================================================== */
+ #define R_CANFDL_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */
+ #define R_CANFDL_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */
+ #define R_CANFDL_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */
+ #define R_CANFDL_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */
+ #define R_CANFDL_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */
+ #define R_CANFDL_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDRFPCTR ======================================================= */
+ #define R_CANFDL_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */
+ #define R_CANFDL_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */
+/* ======================================================== CFDCFCC ======================================================== */
+ #define R_CANFDL_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */
+ #define R_CANFDL_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */
+ #define R_CANFDL_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */
+ #define R_CANFDL_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */
+ #define R_CANFDL_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */
+ #define R_CANFDL_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */
+ #define R_CANFDL_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */
+ #define R_CANFDL_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */
+ #define R_CANFDL_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */
+ #define R_CANFDL_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */
+ #define R_CANFDL_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */
+ #define R_CANFDL_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */
+ #define R_CANFDL_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */
+ #define R_CANFDL_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */
+ #define R_CANFDL_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDCFSTS ======================================================== */
+ #define R_CANFDL_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */
+ #define R_CANFDL_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */
+ #define R_CANFDL_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */
+ #define R_CANFDL_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */
+ #define R_CANFDL_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */
+ #define R_CANFDL_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */
+ #define R_CANFDL_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDCFPCTR ======================================================= */
+ #define R_CANFDL_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */
+ #define R_CANFDL_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDFESTS ======================================================== */
+ #define R_CANFDL_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */
+ #define R_CANFDL_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */
+ #define R_CANFDL_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDFFSTS ======================================================== */
+ #define R_CANFDL_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */
+ #define R_CANFDL_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */
+ #define R_CANFDL_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDFMSTS ======================================================== */
+ #define R_CANFDL_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */
+ #define R_CANFDL_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */
+ #define R_CANFDL_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDRFISTS ======================================================= */
+ #define R_CANFDL_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */
+ #define R_CANFDL_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */
+/* ======================================================== CFDTMC ========================================================= */
+ #define R_CANFDL_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */
+ #define R_CANFDL_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */
+ #define R_CANFDL_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */
+ #define R_CANFDL_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDTMSTS ======================================================== */
+ #define R_CANFDL_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */
+ #define R_CANFDL_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */
+ #define R_CANFDL_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */
+ #define R_CANFDL_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */
+ #define R_CANFDL_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */
+ #define R_CANFDL_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDTMTRSTS ======================================================= */
+ #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */
+ #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */
+/* ====================================================== CFDTMTARSTS ====================================================== */
+ #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */
+ #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */
+/* ====================================================== CFDTMTCSTS ======================================================= */
+ #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */
+ #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */
+/* ====================================================== CFDTMTASTS ======================================================= */
+ #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */
+ #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */
+/* ======================================================= CFDTMIEC ======================================================== */
+ #define R_CANFDL_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */
+ #define R_CANFDL_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */
+/* ======================================================= CFDTXQCC0 ======================================================= */
+ #define R_CANFDL_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
+ #define R_CANFDL_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
+ #define R_CANFDL_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
+ #define R_CANFDL_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
+ #define R_CANFDL_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */
+/* ====================================================== CFDTXQSTS0 ======================================================= */
+ #define R_CANFDL_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
+ #define R_CANFDL_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
+ #define R_CANFDL_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
+ #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
+ #define R_CANFDL_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
+/* ====================================================== CFDTXQPCTR0 ====================================================== */
+ #define R_CANFDL_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
+ #define R_CANFDL_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDTHLCC ======================================================== */
+ #define R_CANFDL_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */
+ #define R_CANFDL_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */
+ #define R_CANFDL_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */
+ #define R_CANFDL_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */
+ #define R_CANFDL_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDTHLSTS ======================================================= */
+ #define R_CANFDL_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */
+ #define R_CANFDL_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */
+ #define R_CANFDL_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */
+ #define R_CANFDL_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */
+ #define R_CANFDL_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */
+ #define R_CANFDL_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */
+/* ====================================================== CFDTHLPCTR ======================================================= */
+ #define R_CANFDL_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */
+ #define R_CANFDL_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */
+/* ===================================================== CFDGTINTSTS0 ====================================================== */
+ #define R_CANFDL_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */
+ #define R_CANFDL_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */
+ #define R_CANFDL_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */
+ #define R_CANFDL_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */
+ #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */
+ #define R_CANFDL_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */
+/* ====================================================== CFDGTSTCFG ======================================================= */
+ #define R_CANFDL_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */
+ #define R_CANFDL_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */
+/* ====================================================== CFDGTSTCTR ======================================================= */
+ #define R_CANFDL_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */
+ #define R_CANFDL_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGFDCFG ======================================================= */
+ #define R_CANFDL_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */
+ #define R_CANFDL_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */
+ #define R_CANFDL_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */
+/* ======================================================= CFDGLOCKK ======================================================= */
+ #define R_CANFDL_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
+ #define R_CANFDL_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */
+/* ===================================================== CFDGAFLIGNENT ===================================================== */
+ #define R_CANFDL_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */
+ #define R_CANFDL_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */
+/* ===================================================== CFDGAFLIGNCTR ===================================================== */
+ #define R_CANFDL_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */
+ #define R_CANFDL_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_CANFDL_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDCDTCT ======================================================== */
+ #define R_CANFDL_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */
+ #define R_CANFDL_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */
+ #define R_CANFDL_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */
+ #define R_CANFDL_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDCDTSTS ======================================================= */
+ #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */
+ #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */
+ #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */
+ #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
+/* ======================================================= CFDGRSTC ======================================================== */
+ #define R_CANFDL_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */
+ #define R_CANFDL_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
+ #define R_CANFDL_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
+ #define R_CANFDL_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
+/* ======================================================= CFDRPGACC ======================================================= */
+ #define R_CANFDL_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
+ #define R_CANFDL_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
+
/* =========================================================================================================================== */
/* ================ R_CRC ================ */
/* =========================================================================================================================== */
@@ -27314,6 +35792,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */
#define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */
#define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */
+ #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */
+ #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */
#define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */
#define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */
/* ======================================================= CTSUTRMR ======================================================== */
@@ -27576,6 +36056,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_CTSU2_CTSUSR_DTSR_Msk (0x1000UL) /*!< DTSR (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUSR_SENSOVF_Pos (13UL) /*!< SENSOVF (Bit 13) */
#define R_CTSU2_CTSUSR_SENSOVF_Msk (0x2000UL) /*!< SENSOVF (Bitfield-Mask: 0x01) */
+ #define R_CTSU2_CTSUSR_SUOVF_Pos (14UL) /*!< SUOVF (Bit 14) */
+ #define R_CTSU2_CTSUSR_SUOVF_Msk (0x4000UL) /*!< SUOVF (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUSR_PS_Pos (15UL) /*!< PS (Bit 15) */
#define R_CTSU2_CTSUSR_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUSR_CFCRDCH_Pos (16UL) /*!< CFCRDCH (Bit 16) */
@@ -27625,8 +36107,12 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */
#define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */
#define R_CTSU2_CTSUCALIB_CFCMODE_Msk (0x400000UL) /*!< CFCMODE (Bitfield-Mask: 0x01) */
+ #define R_CTSU2_CTSUCALIB_DACMSEL_Pos (24UL) /*!< DACMSEL (Bit 24) */
+ #define R_CTSU2_CTSUCALIB_DACMSEL_Msk (0x1000000UL) /*!< DACMSEL (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUCALIB_DACCARRY_Pos (25UL) /*!< DACCARRY (Bit 25) */
#define R_CTSU2_CTSUCALIB_DACCARRY_Msk (0x2000000UL) /*!< DACCARRY (Bitfield-Mask: 0x01) */
+ #define R_CTSU2_CTSUCALIB_SUMSEL_Pos (26UL) /*!< SUMSEL (Bit 26) */
+ #define R_CTSU2_CTSUCALIB_SUMSEL_Msk (0x4000000UL) /*!< SUMSEL (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUCALIB_SUCARRY_Pos (27UL) /*!< SUCARRY (Bit 27) */
#define R_CTSU2_CTSUCALIB_SUCARRY_Msk (0x8000000UL) /*!< SUCARRY (Bitfield-Mask: 0x01) */
#define R_CTSU2_CTSUCALIB_DACCLK_Pos (28UL) /*!< DACCLK (Bit 28) */
@@ -28404,12 +36890,12 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */
#define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */
/* ======================================================== ELCSARA ======================================================== */
- #define R_ELC_ELCSARA_ELSEGR0_Pos (0UL) /*!< ELSEGR0 (Bit 0) */
- #define R_ELC_ELCSARA_ELSEGR0_Msk (0x1UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARA_ELSEGR1_Pos (1UL) /*!< ELSEGR1 (Bit 1) */
- #define R_ELC_ELCSARA_ELSEGR1_Msk (0x2UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
- #define R_ELC_ELCSARA_ELCR_Pos (2UL) /*!< ELCR (Bit 2) */
- #define R_ELC_ELCSARA_ELCR_Msk (0x4UL) /*!< ELCR (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */
+ #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */
+ #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
+ #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */
+ #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
/* ======================================================== ELCSARB ======================================================== */
#define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */
#define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
@@ -29896,6 +38382,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */
#define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */
/* ======================================================== GTUPSR ========================================================= */
+ #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */
+ #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */
#define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */
#define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */
#define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */
@@ -29919,6 +38407,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */
#define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */
/* ======================================================== GTDNSR ========================================================= */
+ #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */
+ #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */
#define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */
#define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */
#define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */
@@ -30247,13 +38737,21 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */
#define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */
+/* =========================================================================================================================== */
+/* ================ R_GPT_GTCLK ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== GTCLKCR ======================================================== */
+ #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */
+ #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */
+
/* =========================================================================================================================== */
/* ================ R_GPT_ODC ================ */
/* =========================================================================================================================== */
/* ======================================================= GTDLYCR1 ======================================================== */
- #define R_GPT_ODC_GTDLYCR1_DLLMOD_Pos (8UL) /*!< DLLMOD (Bit 8) */
- #define R_GPT_ODC_GTDLYCR1_DLLMOD_Msk (0x100UL) /*!< DLLMOD (Bitfield-Mask: 0x01) */
+ #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */
+ #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */
#define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */
#define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */
#define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */
@@ -30496,6 +38994,11 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */
#define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */
#define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */
+/* ========================================================= IELEN ========================================================= */
+ #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */
+ #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */
+ #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */
+ #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ R_IIC0 ================ */
@@ -30928,593 +39431,623 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
-/* ================ I3C ================ */
+/* ================ R_I3C0 ================ */
/* =========================================================================================================================== */
/* ========================================================= PRTS ========================================================== */
- #define I3C_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
- #define I3C_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
+ #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */
+/* ========================================================= CECTL ========================================================= */
+ #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */
+ #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */
/* ========================================================= BCTL ========================================================== */
- #define I3C_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */
- #define I3C_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */
- #define I3C_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */
- #define I3C_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */
- #define I3C_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */
- #define I3C_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */
- #define I3C_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */
- #define I3C_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */
- #define I3C_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */
- #define I3C_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */
- #define I3C_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */
- #define I3C_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */
+ #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */
+ #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */
+ #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */
+ #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */
+ #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */
+ #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */
/* ======================================================== MSDVAD ========================================================= */
- #define I3C_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */
- #define I3C_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */
- #define I3C_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */
- #define I3C_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */
+ #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */
+ #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */
/* ======================================================== RSTCTL ========================================================= */
- #define I3C_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */
- #define I3C_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */
- #define I3C_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */
- #define I3C_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */
- #define I3C_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */
- #define I3C_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */
- #define I3C_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */
- #define I3C_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */
- #define I3C_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */
- #define I3C_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */
+ #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */
+ #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */
+ #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */
+ #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */
+ #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */
+ #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */
+ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */
+ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */
+ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */
/* ========================================================= PRSST ========================================================= */
- #define I3C_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */
- #define I3C_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */
- #define I3C_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */
- #define I3C_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */
- #define I3C_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */
- #define I3C_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */
+ #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */
+ #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */
+ #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */
/* ========================================================= INST ========================================================== */
- #define I3C_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */
- #define I3C_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */
+ #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */
/* ========================================================= INSTE ========================================================= */
- #define I3C_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */
- #define I3C_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */
+ #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */
/* ========================================================= INIE ========================================================== */
- #define I3C_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */
- #define I3C_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */
+ #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */
/* ======================================================== INSTFC ========================================================= */
- #define I3C_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */
- #define I3C_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */
+ #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */
/* ========================================================= DVCT ========================================================== */
- #define I3C_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */
- #define I3C_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */
+ #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */
+ #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */
/* ======================================================== IBINCTL ======================================================== */
- #define I3C_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */
- #define I3C_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */
- #define I3C_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */
- #define I3C_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */
- #define I3C_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */
- #define I3C_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */
+ #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */
+ #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */
/* ========================================================= BFCTL ========================================================= */
- #define I3C_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */
- #define I3C_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */
- #define I3C_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */
- #define I3C_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */
- #define I3C_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */
- #define I3C_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */
- #define I3C_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */
- #define I3C_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */
- #define I3C_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */
+ #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */
+ #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */
+ #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */
+ #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */
+ #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */
+ #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */
+ #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */
/* ========================================================= SVCTL ========================================================= */
- #define I3C_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */
- #define I3C_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */
- #define I3C_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */
- #define I3C_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */
- #define I3C_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */
- #define I3C_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */
- #define I3C_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */
- #define I3C_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */
- #define I3C_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */
- #define I3C_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */
+ #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */
+ #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */
+ #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */
+ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */
+ #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */
/* ======================================================= REFCKCTL ======================================================== */
- #define I3C_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */
- #define I3C_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */
+ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */
+ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */
/* ========================================================= STDBR ========================================================= */
- #define I3C_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */
- #define I3C_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */
- #define I3C_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */
- #define I3C_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */
- #define I3C_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */
- #define I3C_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */
- #define I3C_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */
- #define I3C_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */
- #define I3C_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */
- #define I3C_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */
+ #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */
+ #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */
+ #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */
+ #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */
+ #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */
+ #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */
/* ========================================================= EXTBR ========================================================= */
- #define I3C_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */
- #define I3C_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */
- #define I3C_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */
- #define I3C_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */
- #define I3C_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */
- #define I3C_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */
- #define I3C_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */
- #define I3C_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */
+ #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */
+ #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */
+ #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */
+ #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */
+ #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */
/* ======================================================== BFRECDT ======================================================== */
- #define I3C_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */
- #define I3C_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */
+ #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */
+ #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */
/* ======================================================== BAVLCDT ======================================================== */
- #define I3C_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */
- #define I3C_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */
+ #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */
+ #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */
/* ======================================================== BIDLCDT ======================================================== */
- #define I3C_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */
- #define I3C_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */
+ #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */
+ #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */
/* ======================================================== OUTCTL ========================================================= */
- #define I3C_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */
- #define I3C_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */
- #define I3C_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */
- #define I3C_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */
- #define I3C_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */
- #define I3C_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */
- #define I3C_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */
- #define I3C_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */
- #define I3C_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */
- #define I3C_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */
- #define I3C_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */
- #define I3C_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */
+ #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */
+ #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */
+ #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */
+ #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */
+ #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */
+ #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */
+ #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */
/* ========================================================= INCTL ========================================================= */
- #define I3C_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */
- #define I3C_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */
- #define I3C_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */
- #define I3C_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */
+ #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */
+ #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */
+ #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */
/* ======================================================== TMOCTL ========================================================= */
- #define I3C_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */
- #define I3C_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */
- #define I3C_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */
- #define I3C_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */
- #define I3C_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */
- #define I3C_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */
- #define I3C_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */
- #define I3C_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */
+ #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */
+ #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */
+ #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */
+ #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */
+ #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */
+ #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */
/* ======================================================== ACKCTL ========================================================= */
- #define I3C_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */
- #define I3C_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */
- #define I3C_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */
- #define I3C_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */
- #define I3C_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */
- #define I3C_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */
+ #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */
+ #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */
+ #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */
+ #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */
+ #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */
/* ======================================================= SCSTRCTL ======================================================== */
- #define I3C_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */
- #define I3C_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */
- #define I3C_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */
- #define I3C_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */
+ #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */
/* ======================================================= SCSTLCTL ======================================================== */
- #define I3C_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */
- #define I3C_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */
- #define I3C_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */
- #define I3C_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */
- #define I3C_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */
- #define I3C_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */
- #define I3C_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */
- #define I3C_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */
- #define I3C_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */
- #define I3C_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */
+ #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */
+ #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */
+ #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */
+ #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */
+ #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */
/* ======================================================== SVTDLG0 ======================================================== */
- #define I3C_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */
- #define I3C_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */
+ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */
/* ======================================================== CNDCTL ========================================================= */
- #define I3C_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */
- #define I3C_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */
- #define I3C_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */
- #define I3C_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */
- #define I3C_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */
- #define I3C_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */
+ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */
+ #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */
+ #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */
/* ======================================================== NCMDQP ========================================================= */
/* ======================================================== NRSPQP ========================================================= */
/* ======================================================== NTDTBP0 ======================================================== */
/* ======================================================== NIBIQP ========================================================= */
/* ========================================================= NRSQP ========================================================= */
/* ======================================================== NQTHCTL ======================================================== */
- #define I3C_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */
- #define I3C_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */
- #define I3C_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */
- #define I3C_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */
- #define I3C_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */
- #define I3C_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */
- #define I3C_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */
- #define I3C_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */
+ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */
+ #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */
+ #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */
/* ======================================================= NTBTHCTL0 ======================================================= */
- #define I3C_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */
- #define I3C_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */
- #define I3C_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */
- #define I3C_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */
- #define I3C_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */
- #define I3C_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */
- #define I3C_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */
- #define I3C_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */
/* ======================================================= NRQTHCTL ======================================================== */
- #define I3C_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */
- #define I3C_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */
+ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */
/* ========================================================== BST ========================================================== */
- #define I3C_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */
- #define I3C_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */
- #define I3C_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */
- #define I3C_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */
- #define I3C_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */
- #define I3C_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */
- #define I3C_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */
- #define I3C_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */
- #define I3C_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */
- #define I3C_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */
- #define I3C_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */
- #define I3C_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */
- #define I3C_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */
- #define I3C_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */
+ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */
+ #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */
+ #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */
+ #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */
+ #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */
+ #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */
+ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */
/* ========================================================= BSTE ========================================================== */
- #define I3C_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */
- #define I3C_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */
- #define I3C_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */
- #define I3C_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */
- #define I3C_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */
- #define I3C_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */
- #define I3C_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */
- #define I3C_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */
- #define I3C_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */
+ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */
+ #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */
+ #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */
+ #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */
+ #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */
+ #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */
+ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */
/* ========================================================== BIE ========================================================== */
- #define I3C_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */
- #define I3C_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */
- #define I3C_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */
- #define I3C_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */
- #define I3C_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */
- #define I3C_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */
- #define I3C_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
- #define I3C_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */
- #define I3C_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */
+ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */
+ #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */
+ #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */
+ #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */
+ #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */
+ #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */
+ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */
/* ========================================================= BSTFC ========================================================= */
- #define I3C_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */
- #define I3C_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */
- #define I3C_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */
- #define I3C_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */
- #define I3C_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */
- #define I3C_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */
- #define I3C_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */
- #define I3C_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */
- #define I3C_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */
+ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */
+ #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */
+ #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */
+ #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */
+ #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */
+ #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */
+ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */
/* ========================================================= NTST ========================================================== */
- #define I3C_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */
- #define I3C_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */
- #define I3C_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */
- #define I3C_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */
- #define I3C_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */
- #define I3C_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */
- #define I3C_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */
- #define I3C_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */
- #define I3C_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */
- #define I3C_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */
- #define I3C_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */
- #define I3C_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */
- #define I3C_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */
- #define I3C_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */
- #define I3C_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */
- #define I3C_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */
+ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */
+ #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */
+ #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */
+ #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */
+ #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */
+ #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */
+ #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */
+ #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */
/* ========================================================= NTSTE ========================================================= */
- #define I3C_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */
- #define I3C_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */
- #define I3C_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */
- #define I3C_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */
- #define I3C_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */
- #define I3C_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */
- #define I3C_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */
- #define I3C_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */
- #define I3C_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */
- #define I3C_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */
+ #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */
+ #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */
+ #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */
+ #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */
+ #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */
+ #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */
+ #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */
+ #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */
/* ========================================================= NTIE ========================================================== */
- #define I3C_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */
- #define I3C_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */
- #define I3C_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */
- #define I3C_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */
- #define I3C_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */
- #define I3C_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */
- #define I3C_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */
- #define I3C_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */
- #define I3C_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */
- #define I3C_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */
+ #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */
+ #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */
+ #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */
+ #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */
+ #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */
+ #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */
+ #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */
+ #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */
/* ======================================================== NTSTFC ========================================================= */
- #define I3C_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */
- #define I3C_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */
- #define I3C_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */
- #define I3C_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */
- #define I3C_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */
- #define I3C_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */
- #define I3C_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */
- #define I3C_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */
- #define I3C_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */
- #define I3C_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */
+ #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */
+ #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */
+ #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */
+ #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */
+ #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */
+ #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */
+ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */
+ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */
+/* ========================================================= BCST ========================================================== */
+ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */
+ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */
+ #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */
+ #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */
/* ========================================================= SVST ========================================================== */
- #define I3C_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */
- #define I3C_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */
- #define I3C_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */
- #define I3C_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */
- #define I3C_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */
- #define I3C_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */
- #define I3C_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */
- #define I3C_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */
- #define I3C_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */
- #define I3C_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */
+ #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */
+ #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */
+ #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */
+ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */
+ #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */
/* ======================================================== DATBAS0 ======================================================== */
- #define I3C_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define I3C_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define I3C_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define I3C_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define I3C_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define I3C_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define I3C_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define I3C_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define I3C_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define I3C_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define I3C_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define I3C_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
/* ======================================================== DATBAS1 ======================================================== */
- #define I3C_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define I3C_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define I3C_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define I3C_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define I3C_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define I3C_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define I3C_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define I3C_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define I3C_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define I3C_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define I3C_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define I3C_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
/* ======================================================== DATBAS2 ======================================================== */
- #define I3C_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define I3C_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define I3C_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define I3C_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define I3C_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define I3C_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define I3C_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define I3C_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define I3C_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define I3C_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define I3C_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define I3C_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
/* ======================================================== DATBAS3 ======================================================== */
- #define I3C_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
- #define I3C_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
- #define I3C_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
- #define I3C_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
- #define I3C_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
- #define I3C_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
- #define I3C_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
- #define I3C_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
- #define I3C_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
- #define I3C_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
- #define I3C_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
- #define I3C_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
- #define I3C_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
+ #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
+ #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
+ #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
+ #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
+ #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
+ #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
+ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
/* ======================================================= EXDATBAS ======================================================== */
- #define I3C_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */
- #define I3C_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */
- #define I3C_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */
- #define I3C_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */
- #define I3C_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */
- #define I3C_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */
- #define I3C_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */
- #define I3C_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */
+ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */
+ #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */
+ #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */
+ #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */
+ #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */
/* ======================================================= SDATBAS0 ======================================================== */
- #define I3C_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
- #define I3C_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
- #define I3C_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
- #define I3C_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
- #define I3C_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
- #define I3C_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
- #define I3C_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
- #define I3C_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+ #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+/* ======================================================= SDATBAS1 ======================================================== */
+ #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
+/* ======================================================= SDATBAS2 ======================================================== */
+ #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
+ #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
+ #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
+ #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
/* ======================================================== MSDCT0 ========================================================= */
- #define I3C_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define I3C_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define I3C_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define I3C_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define I3C_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define I3C_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+ #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
/* ======================================================== MSDCT1 ========================================================= */
- #define I3C_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define I3C_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define I3C_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define I3C_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define I3C_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define I3C_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+ #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
/* ======================================================== MSDCT2 ========================================================= */
- #define I3C_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define I3C_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define I3C_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define I3C_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define I3C_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define I3C_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+ #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
/* ======================================================== MSDCT3 ========================================================= */
- #define I3C_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
- #define I3C_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
- #define I3C_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
- #define I3C_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
- #define I3C_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
- #define I3C_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
- #define I3C_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
+ #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
+ #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
+ #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
+ #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
+ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
+ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
/* ========================================================= SVDCT ========================================================= */
- #define I3C_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
- #define I3C_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
- #define I3C_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */
- #define I3C_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */
- #define I3C_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */
- #define I3C_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */
- #define I3C_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */
- #define I3C_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */
- #define I3C_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */
- #define I3C_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */
- #define I3C_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */
- #define I3C_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */
+ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
+ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
+ #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */
+ #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */
+ #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */
+ #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */
+ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */
+ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */
/* ======================================================= SDCTPIDL ======================================================== */
/* ======================================================= SDCTPIDH ======================================================== */
/* ======================================================== SVDVAD0 ======================================================== */
- #define I3C_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */
- #define I3C_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */
- #define I3C_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */
- #define I3C_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */
- #define I3C_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */
- #define I3C_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */
- #define I3C_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */
- #define I3C_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */
+ #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */
+ #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */
+ #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */
+ #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */
+ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */
/* ======================================================== CSECMD ========================================================= */
- #define I3C_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */
- #define I3C_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */
- #define I3C_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */
- #define I3C_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */
- #define I3C_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */
- #define I3C_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */
+ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */
+ #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */
+ #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */
/* ======================================================== CEACTST ======================================================== */
- #define I3C_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */
- #define I3C_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */
+ #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */
+ #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */
/* ========================================================= CMWLG ========================================================= */
- #define I3C_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */
- #define I3C_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */
+ #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */
/* ========================================================= CMRLG ========================================================= */
- #define I3C_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */
- #define I3C_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */
- #define I3C_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */
- #define I3C_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */
+ #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */
+ #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */
+ #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */
/* ======================================================== CETSTMD ======================================================== */
- #define I3C_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */
- #define I3C_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */
+ #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */
/* ======================================================== CGDVST ========================================================= */
- #define I3C_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */
- #define I3C_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */
- #define I3C_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */
- #define I3C_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */
- #define I3C_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */
- #define I3C_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */
- #define I3C_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */
- #define I3C_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */
+ #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */
+ #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */
+ #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */
+ #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */
+ #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */
+ #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */
/* ======================================================== CMDSPW ========================================================= */
- #define I3C_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */
- #define I3C_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */
+ #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */
+ #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */
/* ======================================================== CMDSPR ========================================================= */
- #define I3C_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */
- #define I3C_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */
+ #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */
+ #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */
+ #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */
+ #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */
/* ======================================================== CMDSPT ========================================================= */
- #define I3C_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */
- #define I3C_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */
- #define I3C_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */
- #define I3C_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */
+ #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */
+ #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */
+ #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */
+ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */
/* ========================================================= CETSM ========================================================= */
- #define I3C_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */
- #define I3C_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */
- #define I3C_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */
- #define I3C_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */
+ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */
+ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */
+ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */
/* ======================================================== BITCNT ========================================================= */
- #define I3C_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */
- #define I3C_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */
- #define I3C_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */
- #define I3C_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */
+ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */
+ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */
+ #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */
+ #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */
/* ======================================================== NQSTLV ========================================================= */
- #define I3C_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */
- #define I3C_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */
- #define I3C_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */
- #define I3C_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */
- #define I3C_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */
- #define I3C_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */
- #define I3C_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */
- #define I3C_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */
+ #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */
+ #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */
+ #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */
+ #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */
+ #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */
/* ======================================================= NDBSTLV0 ======================================================== */
- #define I3C_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */
- #define I3C_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */
- #define I3C_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */
- #define I3C_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */
+ #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */
/* ======================================================= NRSQSTLV ======================================================== */
- #define I3C_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */
- #define I3C_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */
+ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */
+ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */
/* ======================================================== PRSTDBG ======================================================== */
- #define I3C_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */
- #define I3C_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */
- #define I3C_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */
- #define I3C_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */
- #define I3C_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */
- #define I3C_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */
- #define I3C_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */
- #define I3C_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */
+ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */
+ #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */
+ #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */
+ #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */
+ #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */
/* ======================================================= MSERRCNT ======================================================== */
- #define I3C_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */
- #define I3C_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */
+ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */
+ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ R_MMF ================ */
@@ -31555,6 +40088,13 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
/* ================ R_MSTP ================ */
/* =========================================================================================================================== */
+/* ======================================================== MSTPCRA ======================================================== */
+ #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */
+ #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */
+ #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */
+ #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */
+ #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */
+ #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */
/* ======================================================== MSTPCRB ======================================================== */
#define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */
#define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */
@@ -31613,6 +40153,10 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */
#define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */
#define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */
+ #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */
+ #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */
+ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */
+ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */
#define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */
#define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */
#define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */
@@ -31691,6 +40235,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */
#define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */
/* ======================================================== MSTPCRE ======================================================== */
+ #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */
+ #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */
#define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */
#define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */
#define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */
@@ -32336,6 +40882,8 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */
#define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */
#define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */
+ #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */
+ #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */
#define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */
#define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */
#define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */
@@ -33150,6 +41698,121 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */
#define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */
+/* =========================================================================================================================== */
+/* ================ R_BUS_B ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== BUSSCNTFHBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTFLBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTS0BIU ====================================================== */
+ #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTPSBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTPLBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTPHBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
+/* ===================================================== BUSSCNTEQBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTEOBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSSCNTECBIU ====================================================== */
+ #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
+ #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
+/* ====================================================== BUS1ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS2ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS3ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS4ERRSTAT ====================================================== */
+ #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
+ #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
+ #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
+ #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
+ #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS1ERRCLR ======================================================= */
+ #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS2ERRCLR ======================================================= */
+ #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS3ERRCLR ======================================================= */
+ #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ====================================================== BUS4ERRCLR ======================================================= */
+ #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
+ #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
+ #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
+ #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
+ #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
+/* ==================================================== DMACDTCERRSTAT ===================================================== */
+ #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */
+ #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */
+/* ===================================================== DMACDTCERRCLR ===================================================== */
+ #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */
+ #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */
+/* ======================================================== CSRECEN ======================================================== */
+ #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
+ #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
+ #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
+ #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
+
/* =========================================================================================================================== */
/* ================ R_SRC ================ */
/* =========================================================================================================================== */
@@ -33338,732 +42001,771 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
/* =========================================================================================================================== */
/* ========================================================= SBYCR ========================================================= */
- #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */
- #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */
- #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */
+ #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */
+ #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */
/* ======================================================== MSTPCRA ======================================================== */
- #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */
- #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */
- #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */
- #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */
- #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */
- #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */
- #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */
/* ======================================================= SCKDIVCR ======================================================== */
- #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */
- #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */
- #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */
- #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */
- #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */
- #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */
- #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */
- #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */
/* ======================================================= SCKDIVCR2 ======================================================= */
- #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */
- #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */
/* ======================================================== SCKSCR ========================================================= */
- #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
- #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */
/* ======================================================== PLLCCR ========================================================= */
- #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */
- #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */
- #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */
- #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */
- #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */
/* ========================================================= PLLCR ========================================================= */
- #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */
- #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */
/* ======================================================== PLLCCR2 ======================================================== */
- #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */
- #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */
- #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */
/* ========================================================= BCKCR ========================================================= */
- #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */
- #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */
/* ======================================================== MEMWAIT ======================================================== */
- #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */
- #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */
/* ======================================================== MOSCCR ========================================================= */
- #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */
- #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */
/* ======================================================== HOCOCR ========================================================= */
- #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
- #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
/* ======================================================== MOCOCR ========================================================= */
- #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
- #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
/* ======================================================== FLLCR1 ========================================================= */
- #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */
- #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */
/* ======================================================== FLLCR2 ========================================================= */
- #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */
- #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */
/* ========================================================= OSCSF ========================================================= */
- #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */
- #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */
- #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */
- #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */
- #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */
+ #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */
+ #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */
/* ========================================================= CKOCR ========================================================= */
- #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */
- #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */
- #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */
- #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */
+ #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */
+ #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */
+ #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */
/* ======================================================== TRCKCR ========================================================= */
- #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */
- #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */
- #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */
+ #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */
/* ======================================================== OSTDCR ========================================================= */
- #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */
- #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */
- #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */
/* ======================================================== OSTDSR ========================================================= */
- #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */
- #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */
+/* ========================================================= LPOPT ========================================================= */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */
+ #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */
/* ======================================================= SLCDSCKCR ======================================================= */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */
- #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */
/* ======================================================== EBCKOCR ======================================================== */
- #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */
- #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */
/* ======================================================== SDCKOCR ======================================================== */
- #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */
- #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */
/* ======================================================= MOCOUTCR ======================================================== */
- #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */
- #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */
/* ======================================================= HOCOUTCR ======================================================== */
- #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */
- #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */
/* ========================================================= SNZCR ========================================================= */
- #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */
- #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */
- #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */
- #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */
+ #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */
/* ======================================================== SNZEDCR ======================================================== */
- #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */
- #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */
- #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */
- #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */
- #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */
- #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */
- #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */
- #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */
- #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */
/* ======================================================= SNZREQCR ======================================================== */
- #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
- #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
/* ======================================================== FLSTOP ========================================================= */
- #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */
- #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */
- #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */
/* ========================================================= PSMCR ========================================================= */
- #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */
- #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */
+ #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */
/* ========================================================= OPCCR ========================================================= */
- #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */
- #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */
- #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */
+ #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */
/* ======================================================== SOPCCR ========================================================= */
- #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */
- #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */
- #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */
/* ======================================================= MOSCWTCR ======================================================== */
- #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */
- #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */
/* ======================================================= HOCOWTCR ======================================================== */
- #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */
- #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */
/* ======================================================== RSTSR1 ========================================================= */
- #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */
- #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */
- #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */
- #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */
- #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */
- #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */
- #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */
- #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */
- #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */
- #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */
- #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */
+ #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */
+ #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */
+ #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */
+ #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */
+ #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */
+ #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */
/* ======================================================== STCONR ========================================================= */
- #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */
- #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */
+ #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */
/* ======================================================== LVD1CR1 ======================================================== */
- #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
- #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
- #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
/* ======================================================== LVD2CR1 ======================================================== */
- #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
- #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
- #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
/* ====================================================== USBCKCR_ALT ====================================================== */
- #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */
- #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */
/* ======================================================= SDADCCKCR ======================================================= */
- #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */
- #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */
/* ======================================================== LVD1SR ========================================================= */
- #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */
- #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */
- #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */
+ #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */
+ #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
/* ======================================================== LVD2SR ========================================================= */
- #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */
- #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */
- #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */
+ #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */
+ #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
/* ========================================================= PRCR ========================================================== */
- #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
- #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
- #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
- #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
- #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
- #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
- #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
+ #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
+ #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
+ #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
+ #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
+ #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIER0 ======================================================== */
- #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
- #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
+ #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIER1 ======================================================== */
- #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
- #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */
+ #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIER2 ======================================================== */
- #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */
- #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */
- #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */
- #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */
- #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */
- #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIER3 ======================================================== */
- #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */
- #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */
- #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */
- #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */
- #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIFR0 ======================================================== */
- #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
- #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIFR1 ======================================================== */
- #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
- #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIFR2 ======================================================== */
- #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */
- #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */
- #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */
- #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */
- #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */
- #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */
/* ======================================================== DPSIFR3 ======================================================== */
- #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */
- #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */
- #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */
- #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */
- #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */
/* ======================================================= DPSIEGR0 ======================================================== */
- #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
/* ======================================================= DPSIEGR1 ======================================================== */
- #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */
/* ======================================================= DPSIEGR2 ======================================================== */
- #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */
- #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */
- #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */
- #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */
/* ======================================================== DPSBYCR ======================================================== */
- #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */
- #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */
- #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */
- #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */
/* ======================================================== SYOCDCR ======================================================== */
- #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */
- #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */
- #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */
/* ========================================================= MOMCR ========================================================= */
- #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */
- #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */
- #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */
- #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */
- #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */
+ #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */
+ #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */
+ #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */
/* ======================================================== RSTSR0 ========================================================= */
- #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */
- #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */
- #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */
- #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */
- #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */
- #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */
+ #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */
/* ======================================================== RSTSR2 ========================================================= */
- #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */
- #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */
+ #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */
/* ======================================================== LVCMPCR ======================================================== */
- #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */
- #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */
- #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
/* ======================================================= LVD1CMPCR ======================================================= */
- #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
- #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
- #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */
- #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
/* ======================================================== LVDLVLR ======================================================== */
- #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */
- #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
- #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
/* ======================================================= LVD2CMPCR ======================================================= */
- #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */
- #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */
- #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
/* ======================================================== LVD1CR0 ======================================================== */
- #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
- #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
- #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
- #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
- #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
- #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
- #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
+ #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
+ #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
+ #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
/* ======================================================== LVD2CR0 ======================================================== */
- #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
- #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
- #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
- #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
- #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
- #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
- #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
+ #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
+ #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
+ #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
/* ======================================================== VBTCR1 ========================================================= */
- #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */
- #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */
/* ======================================================== DCDCCTL ======================================================== */
- #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */
- #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */
- #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */
- #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */
- #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */
- #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */
- #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */
+ #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */
+ #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */
/* ======================================================== VCCSEL ========================================================= */
- #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */
- #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */
/* ======================================================== SOSCCR ========================================================= */
- #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */
- #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */
/* ========================================================= SOMCR ========================================================= */
- #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */
- #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */
+ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */
/* ======================================================== LOCOCR ========================================================= */
- #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */
- #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */
/* ======================================================= LOCOUTCR ======================================================== */
- #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */
- #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */
/* ======================================================== VBTCR2 ========================================================= */
- #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */
- #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */
- #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */
/* ========================================================= VBTSR ========================================================= */
- #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */
- #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */
- #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */
- #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */
+ #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */
/* ======================================================= VBTCMPCR ======================================================== */
- #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */
- #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */
/* ======================================================= VBTLVDICR ======================================================= */
- #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */
- #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */
/* ======================================================= VBTWCTLR ======================================================== */
- #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */
- #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */
/* ====================================================== VBTWCH0OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */
- #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */
/* ====================================================== VBTWCH1OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */
- #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */
/* ====================================================== VBTWCH2OTSR ====================================================== */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */
- #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */
/* ======================================================= VBTICTLR ======================================================== */
- #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */
- #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */
- #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */
- #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */
/* ======================================================= VBTOCTLR ======================================================== */
- #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */
- #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */
- #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */
- #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */
- #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */
- #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */
- #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */
/* ======================================================== VBTWTER ======================================================== */
- #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */
- #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */
- #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */
- #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */
- #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */
- #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */
- #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */
+ #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */
+ #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */
+ #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */
/* ======================================================== VBTWEGR ======================================================== */
- #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */
- #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */
- #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */
- #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */
/* ======================================================== VBTWFR ========================================================= */
- #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */
- #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */
- #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */
- #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */
- #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */
- #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */
- #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */
+ #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */
+ #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */
+ #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */
/* ======================================================== VBTBKR ========================================================= */
- #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
- #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
/* ======================================================== FWEPROR ======================================================== */
- #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */
- #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */
+ #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */
/* ======================================================== PLL2CCR ======================================================== */
- #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */
- #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */
- #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */
- #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */
- #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */
/* ======================================================== PLL2CR ========================================================= */
- #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */
- #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */
/* ====================================================== USBCKDIVCR ======================================================= */
- #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */
- #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */
/* ====================================================== OCTACKDIVCR ====================================================== */
- #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */
- #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */
+/* ===================================================== SCISPICKDIVCR ===================================================== */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */
/* ===================================================== CANFDCKDIVCR ====================================================== */
- #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */
- #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== GPTCKDIVCR ======================================================= */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */
+/* ====================================================== IICCKDIVCR ======================================================= */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */
/* ======================================================== USBCKCR ======================================================== */
- #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */
- #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */
- #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */
- #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */
/* ======================================================= OCTACKCR ======================================================== */
- #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */
- #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */
- #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */
- #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */
+/* ====================================================== SCISPICKCR ======================================================= */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */
/* ======================================================= CANFDCKCR ======================================================= */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */
- #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== GPTCKCR ======================================================== */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */
+/* ======================================================== IICCKCR ======================================================== */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */
/* ======================================================= SNZREQCR1 ======================================================= */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */
- #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */
/* ======================================================= SNZEDCR1 ======================================================== */
- #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */
- #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */
/* ======================================================== CGFSAR ========================================================= */
- #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */
- #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */
- #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */
- #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */
- #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */
- #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */
- #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */
- #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */
- #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */
- #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */
- #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */
- #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
- #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
- #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
/* ======================================================== LPMSAR ========================================================= */
- #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */
- #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */
- #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */
- #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */
/* ======================================================== LVDSAR ========================================================= */
- #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
/* ======================================================== RSTSAR ========================================================= */
- #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
/* ======================================================== BBFSAR ========================================================= */
- #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
- #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
- #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
- #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
- #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
- #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
- #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
- #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */
- #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
- #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */
- #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */
- #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */
/* ======================================================== DPFSAR ========================================================= */
- #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */
- #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */
- #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */
- #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */
- #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */
- #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */
- #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */
- #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */
- #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */
- #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */
- #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */
- #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */
- #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */
- #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */
- #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */
- #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */
- #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */
- #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */
- #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */
- #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */
- #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */
- #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */
- #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */
- #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */
- #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */
- #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */
/* ======================================================== DPSWCR ========================================================= */
- #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */
- #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */
+ #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */
+ #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */
/* ====================================================== VBATTMNSELR ====================================================== */
- #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */
- #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */
/* ======================================================= VBATTMONR ======================================================= */
- #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */
- #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */
/* ======================================================== VBTBER ========================================================= */
- #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */
- #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */
+ #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */
+ #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ R_TSN ================ */
@@ -35202,6 +43904,2742 @@ typedef struct /*!< (@ 0x400A6000) R_OSPI Structure
#define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */
#define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */
+/* =========================================================================================================================== */
+/* ================ R_ADC_B0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================= ADCLKENR ======================================================== */
+ #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */
+ #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
+/* ======================================================== ADCLKSR ======================================================== */
+ #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */
+ #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */
+/* ======================================================== ADCLKCR ======================================================== */
+ #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
+ #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */
+ #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */
+/* ======================================================== ADSYCR ========================================================= */
+ #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */
+ #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */
+ #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */
+ #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */
+ #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADERINTCR ======================================================= */
+ #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */
+ #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */
+ #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADOVFINTCR ======================================================= */
+ #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */
+ #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */
+ #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADCALINTCR ======================================================= */
+ #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */
+ #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */
+ #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADMDR ========================================================= */
+ #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */
+ #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */
+ #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADGSPCR ======================================================== */
+ #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */
+ #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */
+ #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */
+ #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */
+ #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */
+ #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */
+ #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */
+ #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */
+ #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */
+/* ======================================================== ADSGER ========================================================= */
+ #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */
+ #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */
+/* ======================================================== ADSGCR0 ======================================================== */
+ #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */
+ #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */
+ #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */
+ #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */
+ #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */
+/* ======================================================== ADSGCR1 ======================================================== */
+ #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */
+ #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */
+ #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */
+ #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */
+ #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */
+/* ======================================================== ADSGCR2 ======================================================== */
+ #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */
+ #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */
+/* ======================================================== ADINTCR ======================================================== */
+ #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */
+ #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x3ffUL) /*!< ADIEn (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGEXT0 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT1 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT2 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT3 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT4 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT5 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT6 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT7 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGEXT8 ======================================================= */
+ #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */
+ #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */
+ #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADTRGELC0 ======================================================= */
+ #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC1 ======================================================= */
+ #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC2 ======================================================= */
+ #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC3 ======================================================= */
+ #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC4 ======================================================= */
+ #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC5 ======================================================= */
+ #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC6 ======================================================= */
+ #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC7 ======================================================= */
+ #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGELC8 ======================================================= */
+ #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */
+ #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADTRGGPT0 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT1 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT2 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT3 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT4 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT5 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT6 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT7 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGGPT8 ======================================================= */
+ #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */
+ #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */
+ #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADTRGDLR0 ======================================================= */
+ #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */
+ #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */
+ #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */
+/* ======================================================= ADTRGDLR1 ======================================================= */
+ #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */
+ #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */
+ #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */
+/* ======================================================= ADTRGDLR2 ======================================================= */
+ #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */
+ #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */
+ #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */
+/* ======================================================= ADTRGDLR3 ======================================================= */
+ #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */
+ #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */
+ #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */
+/* ======================================================= ADTRGDLR4 ======================================================= */
+ #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */
+ #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */
+/* ======================================================= ADSGDCR0 ======================================================== */
+ #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR1 ======================================================== */
+ #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR2 ======================================================== */
+ #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR3 ======================================================== */
+ #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR4 ======================================================== */
+ #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR5 ======================================================== */
+ #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR6 ======================================================== */
+ #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR7 ======================================================== */
+ #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADSGDCR8 ======================================================== */
+ #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */
+ #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */
+ #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */
+ #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */
+ #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */
+ #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADSSTR0 ======================================================== */
+ #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */
+ #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */
+ #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR1 ======================================================== */
+ #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */
+ #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */
+ #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR2 ======================================================== */
+ #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */
+ #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */
+ #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR3 ======================================================== */
+ #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */
+ #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */
+ #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR4 ======================================================== */
+ #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */
+ #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */
+ #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR5 ======================================================== */
+ #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */
+ #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */
+ #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR6 ======================================================== */
+ #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */
+ #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */
+ #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */
+/* ======================================================== ADSSTR7 ======================================================== */
+ #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */
+ #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */
+ #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */
+/* ======================================================= ADCNVSTR ======================================================== */
+ #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */
+ #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */
+ #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */
+ #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */
+/* ======================================================= ADCALSTCR ======================================================= */
+ #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */
+ #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */
+ #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */
+ #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */
+/* ======================================================== ADSHCR0 ======================================================== */
+ #define R_ADC_B0_ADSHCR0_SHEN0_Pos (0UL) /*!< SHEN0 (Bit 0) */
+ #define R_ADC_B0_ADSHCR0_SHEN0_Msk (0x1UL) /*!< SHEN0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSHCR0_SHEN1_Pos (1UL) /*!< SHEN1 (Bit 1) */
+ #define R_ADC_B0_ADSHCR0_SHEN1_Msk (0x2UL) /*!< SHEN1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSHCR0_SHEN2_Pos (2UL) /*!< SHEN2 (Bit 2) */
+ #define R_ADC_B0_ADSHCR0_SHEN2_Msk (0x4UL) /*!< SHEN2 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADSHSTR0 ======================================================== */
+ #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */
+ #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */
+ #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */
+/* ======================================================== ADSHCR1 ======================================================== */
+ #define R_ADC_B0_ADSHCR1_SHEN4_Pos (0UL) /*!< SHEN4 (Bit 0) */
+ #define R_ADC_B0_ADSHCR1_SHEN4_Msk (0x1UL) /*!< SHEN4 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSHCR1_SHEN5_Pos (1UL) /*!< SHEN5 (Bit 1) */
+ #define R_ADC_B0_ADSHCR1_SHEN5_Msk (0x2UL) /*!< SHEN5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSHCR1_SHEN6_Pos (2UL) /*!< SHEN6 (Bit 2) */
+ #define R_ADC_B0_ADSHCR1_SHEN6_Msk (0x4UL) /*!< SHEN6 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADSHSTR1 ======================================================== */
+ #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */
+ #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */
+ #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */
+/* ======================================================= ADCALSHCR ======================================================= */
+ #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */
+ #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */
+ #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */
+ #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */
+/* ======================================================== ADPGACR ======================================================== */
+ #define R_ADC_B0_ADPGACR_PGADEN_Pos (1UL) /*!< PGADEN (Bit 1) */
+ #define R_ADC_B0_ADPGACR_PGADEN_Msk (0x2UL) /*!< PGADEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGACR_PGASEL1_Pos (2UL) /*!< PGASEL1 (Bit 2) */
+ #define R_ADC_B0_ADPGACR_PGASEL1_Msk (0x4UL) /*!< PGASEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGACR_PGAENAMP_Pos (3UL) /*!< PGAENAMP (Bit 3) */
+ #define R_ADC_B0_ADPGACR_PGAENAMP_Msk (0x8UL) /*!< PGAENAMP (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGACR_PGAGEN_Pos (16UL) /*!< PGAGEN (Bit 16) */
+ #define R_ADC_B0_ADPGACR_PGAGEN_Msk (0x10000UL) /*!< PGAGEN (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGACR_PGADG_Pos (20UL) /*!< PGADG (Bit 20) */
+ #define R_ADC_B0_ADPGACR_PGADG_Msk (0x300000UL) /*!< PGADG (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADPGACR_PGAGAIN_Pos (24UL) /*!< PGAGAIN (Bit 24) */
+ #define R_ADC_B0_ADPGACR_PGAGAIN_Msk (0xf000000UL) /*!< PGAGAIN (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADPGAMONCR ======================================================= */
+ #define R_ADC_B0_ADPGAMONCR_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
+ #define R_ADC_B0_ADPGAMONCR_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL0_Pos (16UL) /*!< MONSEL0 (Bit 16) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL0_Msk (0x10000UL) /*!< MONSEL0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL1_Pos (17UL) /*!< MONSEL1 (Bit 17) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL1_Msk (0x20000UL) /*!< MONSEL1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL2_Pos (18UL) /*!< MONSEL2 (Bit 18) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL2_Msk (0x40000UL) /*!< MONSEL2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL3_Pos (19UL) /*!< MONSEL3 (Bit 19) */
+ #define R_ADC_B0_ADPGAMONCR_MONSEL3_Msk (0x80000UL) /*!< MONSEL3 (Bitfield-Mask: 0x01) */
+/* ======================================================== ADREFCR ======================================================== */
+ #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */
+ #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */
+/* ======================================================= ADUOFTR0 ======================================================== */
+ #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR1 ======================================================== */
+ #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR2 ======================================================== */
+ #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR3 ======================================================== */
+ #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR4 ======================================================== */
+ #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR5 ======================================================== */
+ #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR6 ======================================================== */
+ #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADUOFTR7 ======================================================== */
+ #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */
+ #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */
+/* ======================================================== ADUGTR0 ======================================================== */
+ #define R_ADC_B0_ADUGTR0_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR0_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR1 ======================================================== */
+ #define R_ADC_B0_ADUGTR1_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR1_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR2 ======================================================== */
+ #define R_ADC_B0_ADUGTR2_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR2_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR3 ======================================================== */
+ #define R_ADC_B0_ADUGTR3_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR3_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR4 ======================================================== */
+ #define R_ADC_B0_ADUGTR4_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR4_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR5 ======================================================== */
+ #define R_ADC_B0_ADUGTR5_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR5_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR6 ======================================================== */
+ #define R_ADC_B0_ADUGTR6_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR6_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ======================================================== ADUGTR7 ======================================================== */
+ #define R_ADC_B0_ADUGTR7_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */
+ #define R_ADC_B0_ADUGTR7_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */
+/* ====================================================== ADLIMINTCR ======================================================= */
+ #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */
+ #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */
+/* ======================================================= ADLIMTR0 ======================================================== */
+ #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR1 ======================================================== */
+ #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR2 ======================================================== */
+ #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR3 ======================================================== */
+ #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR4 ======================================================== */
+ #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR5 ======================================================== */
+ #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR6 ======================================================== */
+ #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADLIMTR7 ======================================================== */
+ #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */
+ #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */
+ #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPENR ======================================================== */
+ #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */
+ #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */
+/* ====================================================== ADCMPINTCR ======================================================= */
+ #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */
+ #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCCMPCR0 ======================================================= */
+ #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */
+ #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */
+ #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADCCMPCR1 ======================================================= */
+ #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */
+ #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */
+ #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADCMPMDR0 ======================================================= */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */
+ #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */
+/* ======================================================= ADCMPMDR1 ======================================================= */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */
+ #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */
+/* ======================================================= ADCMPTBR0 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR1 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR2 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR3 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR4 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR5 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR6 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADCMPTBR7 ======================================================= */
+ #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */
+ #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */
+ #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */
+/* ======================================================= ADFIFOCR ======================================================== */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */
+ #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADFIFOINTCR ====================================================== */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */
+ #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */
+/* ===================================================== ADFIFOINTLR0 ====================================================== */
+ #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */
+ #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */
+/* ===================================================== ADFIFOINTLR1 ====================================================== */
+ #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */
+ #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */
+/* ===================================================== ADFIFOINTLR2 ====================================================== */
+ #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */
+ #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */
+/* ===================================================== ADFIFOINTLR3 ====================================================== */
+ #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */
+ #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */
+/* ===================================================== ADFIFOINTLR4 ====================================================== */
+ #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */
+ #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR0 ======================================================== */
+ #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR1 ======================================================== */
+ #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR2 ======================================================== */
+ #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR3 ======================================================== */
+ #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR4 ======================================================== */
+ #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR5 ======================================================== */
+ #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR6 ======================================================== */
+ #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR7 ======================================================== */
+ #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR8 ======================================================== */
+ #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADCHCR9 ======================================================== */
+ #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR10 ======================================================== */
+ #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR11 ======================================================== */
+ #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR12 ======================================================== */
+ #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR13 ======================================================== */
+ #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR14 ======================================================== */
+ #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR15 ======================================================== */
+ #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR16 ======================================================== */
+ #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR17 ======================================================== */
+ #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR18 ======================================================== */
+ #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR19 ======================================================== */
+ #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR20 ======================================================== */
+ #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR21 ======================================================== */
+ #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR22 ======================================================== */
+ #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR23 ======================================================== */
+ #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR24 ======================================================== */
+ #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR25 ======================================================== */
+ #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR26 ======================================================== */
+ #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR27 ======================================================== */
+ #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR28 ======================================================== */
+ #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR29 ======================================================== */
+ #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR30 ======================================================== */
+ #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR31 ======================================================== */
+ #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR32 ======================================================== */
+ #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR33 ======================================================== */
+ #define R_ADC_B0_ADCHCR33_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR33_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR33_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR33_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR33_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR33_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR33_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR33_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR34 ======================================================== */
+ #define R_ADC_B0_ADCHCR34_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR34_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR34_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR34_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR34_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR34_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR34_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR34_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR35 ======================================================== */
+ #define R_ADC_B0_ADCHCR35_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR35_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR35_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR35_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR35_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR35_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR35_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR35_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADCHCR36 ======================================================== */
+ #define R_ADC_B0_ADCHCR36_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */
+ #define R_ADC_B0_ADCHCR36_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */
+ #define R_ADC_B0_ADCHCR36_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */
+ #define R_ADC_B0_ADCHCR36_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADCHCR36_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */
+ #define R_ADC_B0_ADCHCR36_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCHCR36_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */
+ #define R_ADC_B0_ADCHCR36_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA0 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA1 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA2 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA3 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA4 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA5 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA6 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA7 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA8 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRA9 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA10 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA11 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA12 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA13 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA14 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA15 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA16 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA17 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA18 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA19 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA20 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA21 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA22 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA23 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA24 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA25 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA26 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA27 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA28 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA29 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA30 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA31 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA32 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA33 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA33_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA33_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA34 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA34_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA34_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA35 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA35_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA35_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ====================================================== ADDOPCRA36 ======================================================= */
+ #define R_ADC_B0_ADDOPCRA36_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */
+ #define R_ADC_B0_ADDOPCRA36_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */
+ #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADDOPCRB0 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB1 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB2 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB3 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB4 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB5 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB6 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB7 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB8 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRB9 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB10 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB11 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB12 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB13 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB14 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB15 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB16 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB17 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB18 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB19 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB20 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB21 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB22 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB23 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB24 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB25 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB26 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB27 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB28 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB29 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB30 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB31 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB32 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB33 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB33_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB33_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB33_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB33_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB34 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB34_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB34_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB34_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB34_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB35 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB35_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB35_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB35_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB35_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ====================================================== ADDOPCRB36 ======================================================= */
+ #define R_ADC_B0_ADDOPCRB36_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */
+ #define R_ADC_B0_ADDOPCRB36_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRB36_ADC_Pos (8UL) /*!< ADC (Bit 8) */
+ #define R_ADC_B0_ADDOPCRB36_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */
+ #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */
+/* ======================================================= ADDOPCRC0 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC1 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC2 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC3 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC4 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC5 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC6 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC7 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC8 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADDOPCRC9 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC10 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC11 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC12 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC13 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC14 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC15 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC16 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC17 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC18 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC19 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC20 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC21 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC22 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC23 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC24 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC25 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC26 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC27 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC28 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC29 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC30 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC31 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC32 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC33 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC33_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC33_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC34 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC34_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC34_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC35 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC35_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC35_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ====================================================== ADDOPCRC36 ======================================================= */
+ #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */
+ #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADDOPCRC36_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */
+ #define R_ADC_B0_ADDOPCRC36_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
+ #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */
+ #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */
+/* ======================================================= ADCALSTR ======================================================== */
+ #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */
+ #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */
+ #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */
+/* ======================================================= ADTRGENR ======================================================== */
+ #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */
+ #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */
+/* ======================================================== ADSYSTR ======================================================== */
+ #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */
+ #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */
+/* ========================================================= ADSTR ========================================================= */
+ #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */
+ #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */
+/* ======================================================== ADSTOPR ======================================================== */
+ #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */
+ #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */
+ #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADSR ========================================================== */
+ #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */
+ #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */
+ #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */
+ #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */
+ #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */
+/* ======================================================== ADGRSR ========================================================= */
+ #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */
+ #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */
+/* ======================================================== ADERSR ========================================================= */
+ #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */
+ #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */
+ #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */
+/* ======================================================== ADERSCR ======================================================== */
+ #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */
+ #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */
+ #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADCALENDSR ======================================================= */
+ #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */
+ #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */
+ #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADCALENDSCR ====================================================== */
+ #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */
+ #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */
+ #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADOVFERSR ======================================================= */
+ #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */
+ #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */
+ #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADOVFCHSR0 ======================================================= */
+ #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Pos (0UL) /*!< OFVCHFn (Bit 0) */
+ #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Msk (0x1fffffffUL) /*!< OFVCHFn (Bitfield-Mask: 0x1fffffff) */
+/* ======================================================= ADOVFEXSR ======================================================= */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Pos (2UL) /*!< OVFEXF2 (Bit 2) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Msk (0x4UL) /*!< OVFEXF2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Pos (7UL) /*!< OVFEXF7 (Bit 7) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Msk (0x80UL) /*!< OVFEXF7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */
+ #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADOVFERSCR ======================================================= */
+ #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */
+ #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */
+ #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADOVFCHSCR0 ====================================================== */
+ #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */
+ #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x1fffffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x1fffffff) */
+/* ====================================================== ADOVFEXSCR ======================================================= */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Pos (2UL) /*!< OVFEXC2 (Bit 2) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Msk (0x4UL) /*!< OVFEXC2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Pos (7UL) /*!< OVFEXC7 (Bit 7) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Msk (0x80UL) /*!< OVFEXC7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */
+ #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFOSR0 ======================================================= */
+ #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */
+ #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */
+ #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADFIFOSR1 ======================================================= */
+ #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */
+ #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */
+ #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADFIFOSR2 ======================================================= */
+ #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */
+ #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */
+ #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADFIFOSR3 ======================================================= */
+ #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */
+ #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */
+ #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */
+ #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADFIFOSR4 ======================================================= */
+ #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */
+ #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */
+/* ======================================================= ADFIFODCR ======================================================= */
+ #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */
+ #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */
+/* ====================================================== ADFIFOERSR ======================================================= */
+ #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */
+ #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */
+ #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */
+ #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */
+/* ====================================================== ADFIFOERSCR ====================================================== */
+ #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */
+ #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */
+ #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */
+ #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */
+/* ======================================================= ADCMPTBSR ======================================================= */
+ #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */
+ #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */
+/* ====================================================== ADCMPTBSCR ======================================================= */
+ #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */
+ #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */
+/* ====================================================== ADCMPCHSR0 ======================================================= */
+ #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */
+ #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x1fffffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x1fffffff) */
+/* ======================================================= ADCMPEXSR ======================================================= */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Pos (2UL) /*!< CMPEXF2 (Bit 2) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Msk (0x4UL) /*!< CMPEXF2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Pos (7UL) /*!< CMPEXF7 (Bit 7) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Msk (0x80UL) /*!< CMPEXF7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */
+ #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADCMPCHSCR0 ====================================================== */
+ #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */
+ #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x1fffffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x1fffffff) */
+/* ====================================================== ADCMPEXSCR ======================================================= */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Pos (2UL) /*!< CMPEXC2 (Bit 2) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Msk (0x4UL) /*!< CMPEXC2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Pos (7UL) /*!< CMPEXC7 (Bit 7) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Msk (0x80UL) /*!< CMPEXC7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */
+ #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */
+/* ======================================================= ADLIMGRSR ======================================================= */
+ #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */
+ #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */
+/* ====================================================== ADLIMCHSR0 ======================================================= */
+ #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */
+ #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x1fffffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x1fffffff) */
+/* ======================================================= ADLIMEXSR ======================================================= */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */
+ #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADLIMGRSCR ======================================================= */
+ #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */
+ #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */
+/* ====================================================== ADLIMCHSCR0 ====================================================== */
+ #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */
+ #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x1fffffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x1fffffff) */
+/* ====================================================== ADLIMEXSCR ======================================================= */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */
+ #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */
+/* ====================================================== ADSCANENDSR ====================================================== */
+ #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */
+ #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */
+/* ===================================================== ADSCANENDSCR ====================================================== */
+ #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */
+ #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */
+/* ========================================================= ADDR ========================================================== */
+ #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================== ADEXDR ========================================================= */
+ #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */
+ #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */
+ #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR0 ======================================================= */
+ #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR1 ======================================================= */
+ #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR2 ======================================================= */
+ #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR3 ======================================================= */
+ #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR4 ======================================================= */
+ #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR5 ======================================================= */
+ #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR6 ======================================================= */
+ #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR7 ======================================================= */
+ #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ======================================================= ADFIFODR8 ======================================================= */
+ #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+ #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+ #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */
+ #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */
+ #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */
+ #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_DOC_B ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= DOCR ========================================================== */
+ #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
+ #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
+ #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */
+ #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */
+ #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */
+ #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */
+ #define R_DOC_B_DOCR_DOPCIE_Pos (7UL) /*!< DOPCIE (Bit 7) */
+ #define R_DOC_B_DOCR_DOPCIE_Msk (0x80UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */
+/* ========================================================= DOSR ========================================================== */
+ #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */
+ #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
+/* ========================================================= DOSCR ========================================================= */
+ #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */
+ #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
+/* ========================================================= DODIR ========================================================= */
+/* ======================================================== DODSR0 ========================================================= */
+/* ======================================================== DODSR1 ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================ R_SCI_B0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== RDR ========================================================== */
+ #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+ #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
+ #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */
+ #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */
+ #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */
+ #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */
+ #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
+ #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */
+ #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */
+ #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
+/* ========================================================== TDR ========================================================== */
+ #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
+ #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
+ #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
+ #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */
+ #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */
+/* ========================================================= CCR0 ========================================================== */
+ #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */
+ #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */
+ #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */
+ #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */
+ #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */
+ #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */
+ #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */
+ #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */
+ #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */
+ #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CCR1 ========================================================== */
+ #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */
+ #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */
+ #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */
+ #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */
+ #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */
+ #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */
+ #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */
+ #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */
+ #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
+ #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */
+ #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */
+ #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */
+ #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CCR2 ========================================================== */
+ #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */
+ #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */
+ #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */
+ #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */
+ #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */
+ #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */
+ #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */
+ #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */
+ #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */
+/* ========================================================= CCR3 ========================================================== */
+ #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */
+ #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */
+ #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */
+ #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */
+ #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */
+ #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */
+ #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */
+ #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */
+ #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */
+ #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */
+ #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */
+ #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */
+ #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */
+/* ========================================================= CCR4 ========================================================== */
+ #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+ #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
+ #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */
+ #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */
+ #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */
+ #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */
+ #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */
+ #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */
+ #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */
+/* ========================================================= CESR ========================================================== */
+ #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */
+ #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */
+ #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */
+/* ========================================================== ICR ========================================================== */
+ #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */
+ #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */
+ #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */
+ #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */
+ #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */
+ #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */
+ #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */
+ #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */
+ #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */
+ #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */
+ #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
+/* ========================================================== FCR ========================================================== */
+ #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */
+ #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
+ #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */
+ #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */
+ #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */
+ #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */
+ #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */
+ #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */
+ #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */
+/* ========================================================== MCR ========================================================== */
+ #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */
+ #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */
+ #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */
+ #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */
+ #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */
+ #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */
+ #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */
+ #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */
+ #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */
+ #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */
+ #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */
+ #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */
+ #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */
+ #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */
+ #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */
+ #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+ #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */
+ #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */
+ #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */
+ #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */
+ #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */
+/* ========================================================= XCR0 ========================================================== */
+ #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */
+ #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */
+ #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */
+ #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */
+ #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */
+ #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */
+ #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */
+ #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */
+ #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */
+ #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */
+ #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */
+ #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */
+ #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */
+ #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */
+ #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */
+/* ========================================================= XCR1 ========================================================== */
+ #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */
+ #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */
+ #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */
+ #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */
+ #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */
+ #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */
+ #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */
+/* ========================================================= XCR2 ========================================================== */
+ #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */
+ #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */
+ #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */
+ #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */
+/* ========================================================== CSR ========================================================== */
+ #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */
+ #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */
+ #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */
+ #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */
+ #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */
+ #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
+ #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */
+ #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */
+ #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */
+ #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */
+ #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */
+ #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */
+ #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+ #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
+ #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
+ #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
+/* ========================================================= FRSR ========================================================== */
+ #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */
+ #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */
+ #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */
+ #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */
+ #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */
+ #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */
+ #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */
+/* ========================================================= FTSR ========================================================== */
+ #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */
+ #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */
+/* ========================================================== MSR ========================================================== */
+ #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */
+ #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */
+ #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */
+ #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */
+ #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */
+ #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */
+/* ========================================================= XSR0 ========================================================== */
+ #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */
+ #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */
+ #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */
+ #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */
+ #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */
+ #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */
+ #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */
+ #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */
+ #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */
+ #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */
+ #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */
+ #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */
+ #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */
+ #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */
+/* ========================================================= XSR1 ========================================================== */
+ #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */
+ #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CFCLR ========================================================= */
+ #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */
+ #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */
+ #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */
+ #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */
+ #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */
+ #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */
+ #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */
+ #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */
+ #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */
+ #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */
+ #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */
+/* ======================================================== ICFCLR ========================================================= */
+ #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */
+ #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */
+/* ========================================================= FFCLR ========================================================= */
+ #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */
+ #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */
+/* ========================================================= MFCLR ========================================================= */
+ #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */
+ #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */
+ #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */
+ #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */
+ #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */
+/* ========================================================= XFCLR ========================================================= */
+ #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */
+ #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */
+ #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */
+ #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */
+ #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */
+ #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */
+ #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */
+ #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */
+ #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */
+ #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_SPI_B0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SPDR ========================================================== */
+/* ======================================================== SPDECR ========================================================= */
+ #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
+ #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
+ #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */
+ #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
+ #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */
+ #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
+ #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */
+ #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */
+/* ========================================================= SPCR ========================================================== */
+ #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */
+ #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */
+ #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */
+ #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */
+ #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */
+ #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */
+ #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */
+ #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */
+ #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */
+ #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */
+ #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */
+ #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */
+ #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */
+ #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */
+ #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */
+ #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */
+ #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */
+ #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */
+ #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */
+ #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */
+/* ========================================================= SPCR2 ========================================================= */
+ #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */
+ #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */
+ #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */
+ #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */
+ #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */
+ #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
+ #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */
+ #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */
+ #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */
+ #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
+/* ========================================================= SPCR3 ========================================================= */
+ #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
+ #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
+ #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
+ #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
+ #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */
+ #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */
+ #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */
+ #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD0 ========================================================= */
+ #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD1 ========================================================= */
+ #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD2 ========================================================= */
+ #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD3 ========================================================= */
+ #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD4 ========================================================= */
+ #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD5 ========================================================= */
+ #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD6 ========================================================= */
+ #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ======================================================== SPCMD7 ========================================================= */
+ #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
+ #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
+ #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
+ #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
+ #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
+ #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
+ #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
+ #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
+ #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */
+ #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
+ #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
+ #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
+/* ========================================================= SPDCR ========================================================= */
+ #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
+ #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */
+ #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */
+ #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */
+ #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */
+/* ======================================================== SPDCR2 ========================================================= */
+ #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */
+ #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */
+ #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
+ #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */
+/* ========================================================= SPSR ========================================================== */
+ #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */
+ #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */
+ #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */
+ #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */
+ #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */
+ #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */
+ #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */
+ #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */
+ #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */
+ #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */
+ #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */
+ #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */
+ #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */
+ #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */
+/* ======================================================== SPTFSR ========================================================= */
+ #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */
+ #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */
+/* ======================================================== SPRFSR ========================================================= */
+ #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */
+ #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */
+/* ========================================================= SPPSR ========================================================= */
+ #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */
+ #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */
+/* ========================================================= SPSRC ========================================================= */
+ #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */
+ #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */
+ #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */
+ #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */
+ #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */
+ #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */
+ #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */
+ #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */
+ #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */
+ #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */
+/* ========================================================= SPFCR ========================================================= */
+ #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */
+ #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */
+
+/* =========================================================================================================================== */
+/* ================ R_TFU ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= SCDT0 ========================================================= */
+ #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */
+ #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= SCDT1 ========================================================= */
+ #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */
+ #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ATDT0 ========================================================= */
+ #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */
+ #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ATDT1 ========================================================= */
+ #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */
+ #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */
+
/** @} */ /* End of group PosMask_peripherals */
#ifdef __cplusplus
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
similarity index 99%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
index 334ab87ff4..a2e07b2f03 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
@@ -63,6 +63,7 @@ void Reset_Handler (void)
/* Initialize system using BSP. */
SystemInit();
+ /* Call user application. */
#ifdef __ARMCC_VERSION
main();
#elif defined(__GNUC__)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
similarity index 93%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
index cfe71882c8..2e0f1e1c77 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
@@ -28,7 +28,6 @@
**********************************************************************************************************************/
#include
#include "bsp_api.h"
-#include "hal_data.h"
/***********************************************************************************************************************
* Macro definitions
@@ -68,7 +67,7 @@
**********************************************************************************************************************/
/** System Clock Frequency (Core Clock) */
-uint32_t SystemCoreClock = 0U;
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$BSS$$ZI$$Base;
@@ -136,6 +135,11 @@ void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
#endif
+#if BSP_CFG_EARLY_INIT
+static void bsp_init_uninitialized_vars(void);
+
+#endif
+
/*******************************************************************************************************************//**
* Initialize the MCU and the runtime environment.
**********************************************************************************************************************/
@@ -186,6 +190,16 @@ void SystemInit (void)
#endif
#endif
+#if BSP_FEATURE_TFU_SUPPORTED
+ R_BSP_MODULE_START(FSP_IP_TFU, 0U);
+#endif
+
+#if BSP_CFG_EARLY_INIT
+
+ /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */
+ bsp_init_uninitialized_vars();
+#endif
+
/* Call pre clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_RESET);
@@ -333,6 +347,9 @@ void SystemInit (void)
/* Initialize ELC events that will be used to trigger NVIC interrupts. */
bsp_irq_cfg();
+
+ /* Call any BSP specific code. No arguments are needed so NULL is sent. */
+ bsp_init(NULL);
}
/*******************************************************************************************************************//**
@@ -357,7 +374,6 @@ void R_BSP_WarmStart (bsp_warm_start_event_t event)
else if (BSP_WARM_START_POST_C == event)
{
/* C runtime environment, system clocks, and pins are all setup. */
- R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
}
else
{
@@ -409,4 +425,34 @@ static void bsp_reset_trng_circuit (void)
#endif
+#if BSP_CFG_EARLY_INIT
+
+/*******************************************************************************************************************//**
+ * Initialize BSP variables not handled by C runtime startup.
+ **********************************************************************************************************************/
+static void bsp_init_uninitialized_vars (void)
+{
+ g_protect_pfswe_counter = 0;
+
+ extern volatile uint16_t g_protect_counters[];
+ for (uint32_t i = 0; i < 4; i++)
+ {
+ g_protect_counters[i] = 0;
+ }
+
+ extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+ for (uint32_t i = 0; i < 16; i++)
+ {
+ g_bsp_group_irq_sources[i] = 0;
+ }
+
+ #if BSP_CFG_EARLY_INIT
+
+ /* Set SystemCoreClock to MOCO */
+ SystemCoreClock = BSP_MOCO_HZ;
+ #endif
+}
+
+#endif
+
/** @} (end addtogroup BSP_MCU) */
diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
new file mode 100644
index 0000000000..a8f399026d
--- /dev/null
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+#ifndef BSP_ARM_EXCEPTIONS_H
+#define BSP_ARM_EXCEPTIONS_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */
+typedef enum IRQn
+{
+ Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */
+ HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */
+ UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
+ PendSV_IRQn = -2, /* 14 Pendable request for system service */
+ SysTick_IRQn = -1, /* 15 System Tick Timer */
+} IRQn_Type;
+
+#endif
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
similarity index 79%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
index b52072e87a..2f2374b41b 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -155,7 +155,9 @@
BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS)
/* The number of clocks is used to size the g_clock_freq array. */
-#if BSP_PRV_PLL_SUPPORTED
+#if BSP_PRV_PLL2_SUPPORTED
+ #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + 1U)
+#elif BSP_PRV_PLL_SUPPORTED
#define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U)
#else
#define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U)
@@ -198,10 +200,144 @@
(BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos))
#endif
+/* All clocks with configurable source except PLL and CLKOUT can use PLL. */
+#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+ #define BSP_PRV_STABILIZE_PLL (1)
+#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
+ (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL)
+ #define BSP_PRV_PLL_USED (1)
+#else
+ #define BSP_PRV_PLL_USED (0)
+#endif
+
+/* All clocks with configurable source except the main clock, PLL, and CLKOUT can use PLL2. */
+#if defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
+ (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL2)
+ #define BSP_PRV_PLL2_USED (1)
+#else
+ #define BSP_PRV_PLL2_USED (0)
+#endif
+
+/* All clocks with configurable source except UCK, CANFD can use the main oscillator. */
+#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED
+ #define BSP_PRV_MAIN_OSC_USED (1)
+ #define BSP_PRV_STABILIZE_MAIN_OSC (1)
+#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)
+ #define BSP_PRV_MAIN_OSC_USED (1)
+#else
+ #define BSP_PRV_MAIN_OSC_USED (0)
+#endif
+
+/* All clocks with configurable source can use HOCO. */
+#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
+#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL_USED
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
+#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL2_USED
+ #define BSP_PRV_HOCO_USED (1)
+ #define BSP_PRV_STABILIZE_HOCO (1)
+#elif defined(BSP_CFG_UCK_SOURCE) && BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ && \
+ (BSP_CFG_UCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO)
+ #define BSP_PRV_HOCO_USED (1)
+#else
+ #define BSP_PRV_HOCO_USED (0)
+#endif
+
+/* All clocks with configurable source except UCK, CANFD, and PLL can use MOCO. */
+#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+ #define BSP_PRV_STABILIZE_MOCO (1)
+#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO)
+ #define BSP_PRV_MOCO_USED (1)
+#else
+ #define BSP_PRV_MOCO_USED (0)
+#endif
+
+/* All clocks with configurable source except UCK, CANFD, and PLL can use LOCO. */
+#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+ #define BSP_PRV_STABILIZE_LOCO (1)
+#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)
+ #define BSP_PRV_LOCO_USED (1)
+#else
+ #define BSP_PRV_LOCO_USED (0)
+#endif
+
/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock
* frequency. */
#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \
- BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE
+ !BSP_PRV_PLL_USED && !BSP_PRV_PLL2_USED
#define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED)
#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ
#define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
@@ -732,6 +868,28 @@ static void bsp_clock_freq_var_init (void)
R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory);
#endif
+ /* Update PLL Clock Frequency based on BSP Configuration. */
+#if BSP_PRV_PLL_SUPPORTED && BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE && BSP_PRV_PLL_USED
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) /
+ (BSP_CFG_PLL_DIV + 1U);
+ #else
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >>
+ BSP_CFG_PLL_DIV;
+ #endif
+#endif
+
+ /* Update PLL2 Clock Frequency based on BSP Configuration. */
+#if BSP_PRV_PLL2_SUPPORTED && BSP_PRV_PLL2_USED
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) /
+ (BSP_CFG_PLL2_DIV + 1U);
+ #else
+ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] =
+ ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV;
+ #endif
+#endif
+
/* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
SystemCoreClockUpdate();
}
@@ -792,7 +950,8 @@ void bsp_clock_init (void)
#endif
#endif
-#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#if BSP_FEATURE_CGC_HAS_SOSC
+ #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
/* If the board has a subclock, set the subclock drive and start the subclock if the subclock is stopped. If the
* subclock is running, the subclock drive is assumed to be set appropriately. */
@@ -801,15 +960,16 @@ void bsp_clock_init (void)
/* Configure the subclock drive if the subclock is not already running. */
R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK);
R_SYSTEM->SOSCCR = 0U;
- #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)
+ #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)
/* If the subclock is the system clock source OR if FLL is used, wait for stabilization. */
R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS);
- #endif
+ #endif
}
-#else
+ #else
R_SYSTEM->SOSCCR = 1U;
+ #endif
#endif
#if BSP_FEATURE_CGC_HAS_HOCOWTCR
@@ -846,7 +1006,7 @@ void bsp_clock_init (void)
/* MCUs that support low voltage mode start up in low voltage mode. */
bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
- #if BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_CLOCK_SOURCE && BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE
+ #if !BSP_PRV_HOCO_USED
/* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low
* voltage mode. */
@@ -867,17 +1027,77 @@ void bsp_clock_init (void)
R_SYSTEM->FLLCR1 = 1U;
#endif
- /* If the PLL is the desired source clock, ensure the source clock is running and stable and the power mode
- * allows PLL operation. */
-#if BSP_PRV_PLL_SUPPORTED
- #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
-
- /* Start PLL source clock. */
- #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+ /* Start all clocks used by other clocks first. */
+#if BSP_PRV_HOCO_USED
R_SYSTEM->HOCOCR = 0U;
- #else
- R_SYSTEM->MOSCCR = 0U;
+
+ #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE)
+
+ /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */
+ R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
+ #endif
+
+ #if BSP_PRV_STABILIZE_HOCO
+
+ /* Wait for HOCO to stabilize. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
+ #endif
+#endif
+#if BSP_PRV_MOCO_USED
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+
+ /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */
+ if (0U != R_SYSTEM->MOCOCR)
+ {
+ R_SYSTEM->MOCOCR = 0U;
+ #if BSP_PRV_STABILIZE_MOCO
+ R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
#endif
+ }
+ #endif
+#endif
+#if BSP_PRV_LOCO_USED
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+
+ /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */
+ if (0U != R_SYSTEM->LOCOCR)
+ {
+ R_SYSTEM->LOCOCR = 0U;
+ #if BSP_PRV_STABILIZE_LOCO
+ R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+ #endif
+ }
+
+ #else
+ R_SYSTEM->LOCOCR = 0U;
+ #if BSP_PRV_STABILIZE_LOCO
+ R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+ #endif
+ #endif
+#endif
+#if BSP_PRV_MAIN_OSC_USED
+ R_SYSTEM->MOSCCR = 0U;
+
+ #if BSP_PRV_STABILIZE_MAIN_OSC
+
+ /* Wait for main oscillator to stabilize. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
+ #endif
+#endif
+
+ /* Start clocks that require other clocks. At this point, all dependent clocks are running and stable if needed. */
+
+#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED
+ #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
+ R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR;
+
+ /* Start PLL2. */
+ R_SYSTEM->PLL2CR = 0U;
+ #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */
+#endif
+
+#if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED
+ #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
/* Configure the PLL registers. */
#if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE
@@ -895,74 +1115,15 @@ void bsp_clock_init (void)
* while setting PLLCCR. */
bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US));
#endif
-
- /* Verify PLL source is stable before starting PLL. */
- #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
- #if BSP_PRV_HOCO_USE_FLL
-
- /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */
- R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
- #endif
-
- /* Wait for HOCO to stabilize. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
- #else
-
- /* Wait for main oscillator to stabilize. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
- #endif
- #endif
-#endif
-
- /* Start source clock. */
-#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
- R_SYSTEM->HOCOCR = 0U;
-
- #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE)
-
- /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */
- R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
#endif
- /* Wait for HOCO to stabilize. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
-#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
- #if BSP_CFG_SOFT_RESET_SUPPORTED
-
- /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */
- if (0U != R_SYSTEM->MOCOCR)
- {
- R_SYSTEM->MOCOCR = 0U;
- R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
- }
- #endif
-#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
- #if BSP_CFG_SOFT_RESET_SUPPORTED
-
- /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */
- if (0U != R_SYSTEM->LOCOCR)
- {
- R_SYSTEM->LOCOCR = 0U;
- R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
- }
-
- #else
- R_SYSTEM->LOCOCR = 0U;
- R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
- #endif
-#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
- R_SYSTEM->MOSCCR = 0U;
-
- /* Wait for main oscillator to stabilize. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
-#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
R_SYSTEM->PLLCR = 0U;
+ #if BSP_PRV_STABILIZE_PLL
+
/* Wait for PLL to stabilize. */
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U);
-#else
-
- /* Do nothing. Subclock is already started and stabilized if it is populated and selected as system clock. */
+ #endif
#endif
/* Set source clock and dividers. */
@@ -984,6 +1145,15 @@ void bsp_clock_init (void)
/* Wait for PLL to stabilize. */
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0U);
+
+ #if BSP_FEATURE_CGC_HAS_PLL2
+
+ /* If the MCU has a PLL2, ensure PLL2 is stopped and stable before entering low speed mode. */
+ R_SYSTEM->PLL2CR = 1U;
+
+ /* Wait for PLL to stabilize. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0U);
+ #endif
}
#endif
#endif
@@ -1028,36 +1198,6 @@ void bsp_clock_init (void)
#endif
#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED
- #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
-
- /* Start PLL2 source clock. */
- #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE) && \
- (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_CLOCK_SOURCE)
- R_SYSTEM->HOCOCR = 0U;
-
- #if BSP_PRV_HOCO_USE_FLL
-
- /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */
- R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
- #endif
-
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
- #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE && \
- (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC != BSP_CFG_PLL_SOURCE) && \
- (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC != BSP_CFG_CLOCK_SOURCE)
- R_SYSTEM->MOSCCR = 0U;
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
- #endif /* BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE */
-
- R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR;
-
- /* Start PLL2. */
- R_SYSTEM->PLL2CR = 0U;
-
- /* Wait for PLL2 to stabilize. */
- FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 1U);
- #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */
-
#if BSP_CFG_UCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED
/* If the USB clock has a divider setting in SCKDIVCR2. */
@@ -1141,6 +1281,69 @@ void bsp_clock_init (void)
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->CANFDCKCR_b.CANFDCKSRDY, 0U);
#endif
+ /* Set the SCISPI clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+
+ /* Request to stop the SCISPI clock. */
+ R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 1;
+
+ /* Wait for the SCISPI clock to stop. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 1U);
+
+ /* Select the SCISPI clock divisor and source. */
+ R_SYSTEM->SCISPICKDIVCR = BSP_CFG_SCISPICLK_DIV;
+ R_SYSTEM->SCISPICKCR = BSP_CFG_SCISPICLK_SOURCE | R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk |
+ R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk;
+
+ /* Request to start the SCISPI clock. */
+ R_SYSTEM->SCISPICKCR_b.SCISPICKSREQ = 0;
+
+ /* Wait for the SCISPI clock to start. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SCISPICKCR_b.SCISPICKSRDY, 0U);
+#endif
+
+ /* Set the GPT clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+
+ /* Request to stop the GPT clock. */
+ R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 1;
+
+ /* Wait for the GPT clock to stop. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 1U);
+
+ /* Select the GPT clock divisor and source. */
+ R_SYSTEM->GPTCKDIVCR = BSP_CFG_GPTCLK_DIV;
+ R_SYSTEM->GPTCKCR = BSP_CFG_GPTCLK_SOURCE | R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk |
+ R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk;
+
+ /* Request to start the GPT clock. */
+ R_SYSTEM->GPTCKCR_b.GPTCKSREQ = 0;
+
+ /* Wait for the GPT clock to start. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->GPTCKCR_b.GPTCKSRDY, 0U);
+#endif
+
+ /* Set the IIC clock if it exists on the MCU */
+#if BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)
+
+ /* Request to stop the IIC clock. */
+ R_SYSTEM->IICCKCR_b.IICCKSREQ = 1;
+
+ /* Wait for the IIC clock to stop. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 1U);
+
+ /* Select the IIC clock divisor and source. */
+ R_SYSTEM->IICCKDIVCR = BSP_CFG_IICCLK_DIV;
+ R_SYSTEM->IICCKCR = BSP_CFG_IICCLK_SOURCE | R_SYSTEM_IICCKCR_IICCKSREQ_Msk |
+ R_SYSTEM_IICCKCR_IICCKSRDY_Msk;
+
+ /* Request to start the IIC clock. */
+ R_SYSTEM->IICCKCR_b.IICCKSREQ = 0;
+
+ /* Wait for the IIC clock to start. */
+ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->IICCKCR_b.IICCKSRDY, 0U);
+#endif
+
/* Lock CGC and LPM protection registers. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
@@ -1347,4 +1550,17 @@ void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting)
#endif
}
+/*******************************************************************************************************************//**
+ * Gets the frequency of a source clock.
+ * @param[in] clock Pointer to Octaclk setting structure which provides information regarding
+ * Octaclk source and divider settings to be applied.
+ * @return Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
+{
+ uint32_t source_clock = g_clock_freq[clock];
+
+ return source_clock;
+}
+
/** @} (end addtogroup BSP_MCU_PRV) */
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
similarity index 92%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
index 489a579620..68e4a77570 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
@@ -147,6 +147,28 @@ FSP_HEADER
#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2
#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4
#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6
+#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8
+
+/* SCISPI clock divider options. */
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6
+#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8
+
+/* GPT clock divider options. */
+#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1
+#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2
+#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4
+#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6
+#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8
+
+/* IIC clock divider options. */
+#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1
+#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2
+#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4
+#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6
+#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8
/* PLL divider options. */
#define BSP_CLOCKS_PLL_DIV_1 (0)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.c
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h
similarity index 89%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h
index 8fb10ce5ce..8f25cb6560 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_common.h
@@ -190,6 +190,13 @@ FSP_HEADER
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
#endif
+/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */
+#if BSP_CFG_EARLY_INIT
+ #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT)
+#else
+ #define BSP_SECTION_EARLY_INIT
+#endif
+
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
@@ -214,6 +221,18 @@ typedef enum e_fsp_priv_clock
FSP_PRIV_CLOCK_FCLK = 28,
} fsp_priv_clock_t;
+/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */
+typedef enum e_fsp_priv_source_clock
+{
+ FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator
+ FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator
+ FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator
+ FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator
+ FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator
+ FSP_PRIV_CLOCK_PLL = 5, ///< The PLL oscillator
+ FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 oscillator
+} fsp_priv_source_clock_t;
+
typedef struct st_bsp_unique_id
{
union
@@ -226,6 +245,7 @@ typedef struct st_bsp_unique_id
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
+uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
/***********************************************************************************************************************
* Global variables (defined in other files)
@@ -262,6 +282,24 @@ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
return (SystemCoreClock << iclk_div) >> clock_div;
}
+#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
+
+/*******************************************************************************************************************//**
+ * Gets the frequency of a SCI/SPI clock.
+ *
+ * @return Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
+{
+ uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
+ uint32_t clock_div = (scispidivcr & FSP_PRIV_SCKDIVCR_DIV_MASK);
+ fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
+
+ return R_BSP_SourceClockHzGet(scispicksel) >> clock_div;
+}
+
+#endif
+
/*******************************************************************************************************************//**
* Get unique ID for this device.
*
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c
similarity index 90%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c
index d3548a7a2d..4dd223547e 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.c
@@ -74,11 +74,27 @@
* at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
* overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
*
- *
* @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires
* that the BSP has already initialized the CGC (which it does as part of the Sysinit).
* Care should be taken to ensure this remains the case if in the future this function were to be called as part
* of the BSP initialization.
+ *
+ * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number
+ * of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified.
+ * Approximate overhead for this function is as follows:
+ * - CM4: 20-50 cycles
+ * - CM33: 10-60 cycles
+ * - CM23: 75-200 cycles
+ *
+ * @note If more accurate microsecond timing must be performed in software it is recommended to use
+ * bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE()
+ * to convert a calculated delay cycle count to a number of software delay loops.
+ *
+ * @note Delays may be longer than expected when compiler optimization is turned off.
+ *
+ * @warning The delay will be longer than specified on CM23 devices when the core clock is greater than 32 MHz. Setting
+ * BSP_DELAY_LOOP_CYCLES to 6 will improve accuracy at 48 MHz but will result in shorter than expected delays
+ * at lower speeds.
**********************************************************************************************************************/
void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_delay.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
similarity index 98%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
index 28d916b3d4..fd1d74e944 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
@@ -41,7 +41,7 @@
**********************************************************************************************************************/
/** This array holds callback functions. */
-static bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] = {0};
+bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] BSP_SECTION_EARLY_INIT;
void NMI_Handler(void);
static void bsp_group_irq_call(bsp_grp_irq_t irq);
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.c
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_guard.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c
similarity index 98%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c
index ba68472a68..ad0cbb7ac8 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.c
@@ -34,7 +34,7 @@
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
-volatile uint32_t g_protect_pfswe_counter;
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/***********************************************************************************************************************
* Private global variables and functions
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h
similarity index 83%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h
index dbb4a9859c..22b7f692b2 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_io.h
@@ -42,6 +42,7 @@ FSP_HEADER
#define BSP_IO_PWPR_B0WI_OFFSET (7U)
#define BSP_IO_PWPR_PFSWE_OFFSET (6U)
#define BSP_IO_PFS_PDR_OUTPUT (4U)
+#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE)
/***********************************************************************************************************************
* Typedef definitions
@@ -76,6 +77,9 @@ typedef enum e_bsp_io_port
BSP_IO_PORT_09 = 0x0900, ///< IO port 9
BSP_IO_PORT_10 = 0x0A00, ///< IO port 10
BSP_IO_PORT_11 = 0x0B00, ///< IO port 11
+ BSP_IO_PORT_12 = 0x0C00, ///< IO port 12
+ BSP_IO_PORT_13 = 0x0D00, ///< IO port 13
+ BSP_IO_PORT_14 = 0x0E00, ///< IO port 14
} bsp_io_port_t;
/** Superset list of all possible IO port pins. */
@@ -284,6 +288,57 @@ typedef enum e_bsp_io_port_pin_t
BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
+
+ BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
+ BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
+ BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2
+ BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3
+ BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4
+ BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5
+ BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6
+ BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7
+ BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8
+ BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9
+ BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10
+ BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11
+ BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12
+ BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13
+ BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14
+ BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15
+
+ BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
+ BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
+ BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
+ BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3
+ BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4
+ BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5
+ BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6
+ BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7
+ BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8
+ BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9
+ BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10
+ BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11
+ BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12
+ BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13
+ BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14
+ BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15
+
+ BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
+ BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
+ BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2
+ BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3
+ BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4
+ BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5
+ BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6
+ BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7
+ BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8
+ BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9
+ BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10
+ BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11
+ BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12
+ BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13
+ BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14
+ BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15
} bsp_io_port_pin_t;
/***********************************************************************************************************************
@@ -309,16 +364,34 @@ __STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin)
}
/*******************************************************************************************************************//**
- * Set a pin to output and set the output level to the level provided
+ * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS
+ * protection using R_BSP_PinAccessEnable() before calling this function.
*
* @param[in] pin The pin
* @param[in] level The level
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level)
{
+ /* Clear PMR, ASEL, ISEL and PODR bits. */
+ uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS;
+ pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK;
+
/* Set output level and pin direction to output. */
- uint32_t lvl = (uint32_t) level;
- R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = BSP_IO_PFS_PDR_OUTPUT | lvl;
+ uint32_t lvl = ((uint32_t) level | pfs_bits);
+ R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl);
+}
+
+/*******************************************************************************************************************//**
+ * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling
+ * this function.
+ *
+ * @param[in] pin The pin
+ * @param[in] cfg Configuration for the pin (PmnPFS register setting)
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg)
+{
+ /* Configure a pin. */
+ R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg;
}
/*******************************************************************************************************************//**
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.c
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_irq.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
similarity index 82%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
index 7391a52a8a..10b26dfcba 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
@@ -29,6 +29,16 @@ FSP_HEADER
* @{
**********************************************************************************************************************/
+#if BSP_FEATURE_TZ_HAS_TRUSTZONE
+
+/* MSTPCRA is located in R_MSTP for Star devices. */
+ #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA)
+#else
+
+/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */
+ #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA)
+#endif
+
/*******************************************************************************************************************//**
* Cancels the module stop state.
*
@@ -64,18 +74,31 @@ FSP_HEADER
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U));
#else
- #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
- #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
- #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE)
- #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \
+ #if (2U == BSP_FEATURE_ELC_VERSION)
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31);
+ #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
+ #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U);
+ #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
+ #else
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
+ #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE)
+ #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \
channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
- #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
- #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
+ #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
+ #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
+ #endif
#endif
-#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_SYSTEM->MSTPCRA
+#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U));
-#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_SYSTEM->MSTPCRA
+#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U));
#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel));
@@ -127,6 +150,10 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel));
#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel));
+#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel));
+#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel));
#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U));
#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC
@@ -139,10 +166,15 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel));
#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel));
-#define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD
-#define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U));
-#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD
-#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U));
+#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
+ #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel));
+#else
+ #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U));
+ #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U));
+#endif
#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel));
#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
similarity index 98%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
index fabb62a930..efab908a77 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -43,10 +43,7 @@
**********************************************************************************************************************/
/** Used for holding reference counters for protection bits. */
-static volatile uint16_t g_protect_counters[] =
-{
- 0U, 0U, 0U, 0U
-};
+volatile uint16_t g_protect_counters[4] BSP_SECTION_EARLY_INIT;
/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
static const uint16_t g_prcr_masks[] =
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
similarity index 99%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
index 2d359a2578..1df5ccbec0 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
@@ -108,8 +108,12 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
+
+ #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel =
BSP_CFG_ROM_REG_DUALSEL;
+
+ #endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
0xFFFFFFFF;
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c
similarity index 90%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c
index fd2530c385..62d9fe81f6 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.c
@@ -62,26 +62,28 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
#pragma section=".tz_data_flash_ns_start"
#pragma section=".tz_sdram_ns_start"
#pragma section=".tz_qspi_flash_ns_start"
+ #pragma section=".tz_ospi_device_0_ns_start"
+ #pragma section=".tz_ospi_device_1_ns_start"
/* &__tz__C is the address of the non-secure callable section. Must assign value to this variable or
* linker will give error. */
/* &__tz__N is the start address of the non-secure region. */
-BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
-BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
-BSP_DONT_REMOVE void const * const __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
-BSP_DONT_REMOVE void const * const __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
-BSP_DONT_REMOVE void const * const __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
+BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
+BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
+BSP_DONT_REMOVE void * __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
+BSP_DONT_REMOVE void * __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
+BSP_DONT_REMOVE void * __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
#if BSP_FEATURE_SDRAM_START_ADDRESS
-BSP_DONT_REMOVE void const * const __tz_SDRAM_N @".tz_sdram_ns_start";
+BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start";
#endif
-BSP_DONT_REMOVE void const * const __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
+BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
#if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
-BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
+BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
#endif
#if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
-BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
+BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
#endif
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
@@ -264,19 +266,23 @@ void R_BSP_SecurityInit (void)
R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR;
/* Initialize Type 2 SARs. */
- R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
- R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */
- R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */
- R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */
- R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */
- R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */
- R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */
- R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */
- R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */
- R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */
- R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */
- R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */
- R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */
+ R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
+ R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */
+ R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */
+ R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */
+ R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */
+ R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */
+ #ifdef BSP_TZ_CFG_BBFSAR
+ R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */
+ #endif
+ R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */
+ R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */
+ R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */
+ R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */
+ R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */
+ #ifdef BSP_TZ_CFG_ICUSARF
+ R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */
+ #endif
R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */
R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */
R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_security.h
diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
new file mode 100644
index 0000000000..2f3e203352
--- /dev/null
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
@@ -0,0 +1,228 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef RENESAS_TFU
+#define RENESAS_TFU
+
+/***********************************************************************************************************************
+ * Includes , "Project Includes"
+ **********************************************************************************************************************/
+
+/* Mathematical Functions includes. */
+#ifdef __cplusplus
+ #include
+#else
+ #include
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f
+
+#ifdef __GNUC__ /* and (arm)clang */
+ #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus)
+
+/* No form of inline is available, it happens only when -std=c89, gnu89 and
+ * above are OK */
+ #warning \
+ "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99"
+ #else
+ #ifdef __GNUC_GNU_INLINE__
+
+/* gnu89 semantics of inline and extern inline are essentially the exact
+ * opposite of those in C99 */
+ #define BSP_TFU_INLINE extern inline __attribute__((always_inline))
+ #else /* __GNUC_STDC_INLINE__ */
+ #define BSP_TFU_INLINE static inline __attribute__((always_inline))
+ #endif
+ #endif
+#elif __ICCARM__
+ #define BSP_TFU_INLINE
+#else
+ #error "Compiler not supported!"
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Calculates sine of the given angle.
+ * @param[in] angle The value of an angle in radian.
+ *
+ * @retval Sine value of an angle.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE float __sinf (float angle)
+{
+ /* Set the angle to R_TFU->SCDT1 */
+ R_TFU->SCDT1 = angle;
+
+ /* Read sin from R_TFU->SCDT1 */
+ return R_TFU->SCDT1;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates cosine of the given angle.
+ * @param[in] angle The value of an angle in radian.
+ *
+ * @retval Cosine value of an angle.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE float __cosf (float angle)
+{
+ /* Set the angle to R_TFU->SCDT1 */
+ R_TFU->SCDT1 = angle;
+
+ /* Read cos from R_TFU->SCDT1 */
+ return R_TFU->SCDT0;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates sine and cosine of the given angle.
+ * @param[in] angle The value of an angle in radian.
+ * @param[out] sin Sine value of an angle.
+ * @param[out] cos Cosine value of an angle.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos)
+{
+ /* Set the angle to R_TFU->SCDT1 */
+ R_TFU->SCDT1 = angle;
+
+ /* Read sin from R_TFU->SCDT1 */
+ *sin = R_TFU->SCDT1;
+
+ /* Read sin from R_TFU->SCDT1 */
+ *cos = R_TFU->SCDT0;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent based on given X-cordinate and Y-cordinate values.
+ * @param[in] y_cord Y-Axis cordinate value.
+ * @param[in] x_cord X-Axis cordinate value.
+ *
+ * @retval Arc tangent for given values.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord)
+{
+ /* Set X-cordinate to R_TFU->ATDT0 */
+ R_TFU->ATDT0 = x_cord;
+
+ /* set Y-cordinate to R_TFU->ATDT1 */
+ R_TFU->ATDT1 = y_cord;
+
+ /* Read arctan(y/x) from R_TFU->ATDT1 */
+ return R_TFU->ATDT1;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in] y_cord Y-cordinate value.
+ * @param[in] x_cord X-cordinate value.
+ *
+ * @retval Hypotenuse for given values.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord)
+{
+ /* Set X-coordinate to R_TFU->ATDT0 */
+ R_TFU->ATDT0 = x_cord;
+
+ /* set Y-coordinate to R_TFU->ATDT1 */
+ R_TFU->ATDT1 = y_cord;
+
+ /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
+ return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in] y_cord Y-cordinate value.
+ * @param[in] x_cord X-cordinate value.
+ * @param[out] atan2 Arc tangent for given values.
+ * @param[out] hypot Hypotenuse for given values.
+ **********************************************************************************************************************/
+#if __ICCARM__
+ #pragma inline = forced
+#endif
+BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot)
+{
+ /* Set X-coordinate to R_TFU->ATDT0 */
+ R_TFU->ATDT0 = x_cord;
+
+ /* set Y-coordinate to R_TFU->ATDT1 */
+ R_TFU->ATDT1 = y_cord;
+
+ /* Read arctan(y/x) from R_TFU->ATDT1 */
+ *atan2 = R_TFU->ATDT1;
+
+ /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
+ *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+}
+
+#if BSP_CFG_USE_TFU_MATHLIB
+ #define sinf(x) __sinf(x)
+ #define cosf(x) __cosf(x)
+ #define atan2f(y, x) __atan2f(y, x)
+ #define hypotf(x, y) __hypotf(x, y)
+ #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h)
+ #define sincosf(a, s, c) __sincosf(a, s, c)
+#endif
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif /* RENESAS_TFU */
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
index 561f707780..6242fdd4be 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
@@ -300,14 +300,14 @@ typedef enum e_elc_event_ra6m4
ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end
ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error
ELC_EVENT_SCI9_AM = (0x1BA), // Address match event
- ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0
- ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1
- ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2
- ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3
- ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0
- ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1
- ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2
- ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3
+ ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI1 extended serial mode event 0
+ ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI1 extended serial mode event 1
+ ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI1 extended serial mode event 2
+ ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI1 extended serial mode event 3
+ ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI2 extended serial mode event 0
+ ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI2 extended serial mode event 1
+ ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI2 extended serial mode event 2
+ ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI2 extended serial mode event 3
ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full
ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty
ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
similarity index 88%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
index 5f628ba782..eff7def062 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
@@ -82,12 +82,17 @@
#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
#define BSP_FEATURE_ADC_HAS_ADBUF (1U)
+#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
+#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
+
#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
+#define BSP_FEATURE_AGT_HAS_AGTW (0U)
#define BSP_FEATURE_BSP_FLASH_CACHE (1)
#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
+#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
@@ -124,6 +129,7 @@
#define BSP_FEATURE_CAN_NUM_CHANNELS (2U)
#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CANFD_LITE (0U)
#define BSP_FEATURE_CGC_HAS_BCLK (1U)
#define BSP_FEATURE_CGC_HAS_FCLK (1U)
@@ -138,6 +144,7 @@
#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
#define BSP_FEATURE_CGC_HAS_PLL (1U)
#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI.
+#define BSP_FEATURE_CGC_HAS_SOSC (1U)
#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M4 there is another register to enable write access for SRAMWTSC.
#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
@@ -180,15 +187,20 @@
#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
+#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U)
#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
+#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U)
#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
+#define BSP_FEATURE_DOC_VERSION (1U)
+
#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U)
#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register
#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
+#define BSP_FEATURE_ELC_VERSION (1U)
#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
@@ -220,6 +232,14 @@
#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFU)
+#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
+#define BSP_FEATURE_GPT_HAS_GTCLKCR (0U)
+#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U)
#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
@@ -228,8 +248,15 @@
#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U)
#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03)
+#define BSP_FEATURE_IIC_VERSION (1U)
+#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U)
+#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U)
-#define BSP_FEATURE_IOPORT_ELC_PORTS (4)
+#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU)
#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
@@ -253,13 +280,15 @@
#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
+#define BSP_FEATURE_IOPORT_VERSION (1U)
+
#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
-#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
-#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
@@ -270,11 +299,13 @@
#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U)
+#define BSP_FEATURE_SCI_VERSION (1U)
#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
+#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature
#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
@@ -298,6 +329,8 @@
#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
+#define BSP_FEATURE_TFU_SPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU
+
#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h b/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/r_icu/r_icu.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_icu/r_icu.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra/fsp/src/r_icu/r_icu.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/r_icu/r_icu.c
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c
similarity index 97%
rename from bsp/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c
index 8867b49f81..f45ae0b2e9 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_ioport/r_ioport.c
@@ -440,10 +440,10 @@ fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
ioport_size_t direction_values,
ioport_size_t mask)
{
- ioport_size_t orig_value;
- ioport_size_t set_bits;
- ioport_size_t clr_bits;
- ioport_size_t write_value;
+ uint32_t orig_value;
+ uint32_t set_bits;
+ uint32_t clr_bits;
+ uint32_t write_value;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
@@ -458,23 +458,23 @@ fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* Read current value of PCNTR1 register for the specified port */
- orig_value = p_ioport_regs->PCNTR1 & IOPORT_PRV_16BIT_MASK;
+ orig_value = p_ioport_regs->PCNTR1;
/* High bits */
set_bits = direction_values & mask;
/* Low bits */
/* Cast to ensure size */
- clr_bits = (ioport_size_t) ((~direction_values) & mask);
+ clr_bits = (uint32_t) ((~direction_values) & mask);
/* New value to write to port direction register */
write_value = orig_value;
write_value |= set_bits;
- /* Cast to ensure size */
- write_value &= (ioport_size_t) (~clr_bits);
+ /* Clear bits as needed */
+ write_value &= ~clr_bits;
- p_ioport_regs->PCNTR1 = write_value & IOPORT_PRV_16BIT_MASK;
+ p_ioport_regs->PCNTR1 = write_value;
return FSP_SUCCESS;
}
@@ -504,7 +504,7 @@ fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_event_data);
uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
- FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+ FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
@@ -543,7 +543,7 @@ fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_pin_event);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
- FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+ FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
@@ -599,7 +599,7 @@ fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl,
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
- FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+ FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
@@ -640,7 +640,7 @@ fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_por
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
- FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+ FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
@@ -673,8 +673,8 @@ fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_por
return FSP_SUCCESS;
}
-/*******************************************************************************************************************//**
- * Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
+/***********************************************************************************************************************
+ * DEPRECATED Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
*
* @retval FSP_SUCCESS Ethernet PHY mode set
* @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid
diff --git a/bsp/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c
similarity index 94%
rename from bsp/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c
rename to bsp/renesas/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c
index 35e2f091a5..7f33e83dff 100644
--- a/bsp/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c
+++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_sci_uart/r_sci_uart.c
@@ -279,6 +279,7 @@ const uart_api_t g_uart_on_sci =
.baudSet = R_SCI_UART_BaudSet,
.communicationAbort = R_SCI_UART_Abort,
.callbackSet = R_SCI_UART_CallbackSet,
+ .readStop = R_SCI_UART_ReadStop,
};
/*******************************************************************************************************************//**
@@ -297,7 +298,8 @@ const uart_api_t g_uart_on_sci =
* @retval FSP_SUCCESS Channel opened successfully.
* @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL.
* @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU.
- * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined.
+ * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined or selected channel
+ * does not support "Hardware CTS and Hardware RTS" flow control.
* @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another
* instance. Call close() then open() to reconfigure.
*
@@ -329,6 +331,12 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
FSP_ERR_INVALID_ARGUMENT);
}
+ if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control == SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS)
+ {
+ FSP_ERROR_RETURN((0U != (((1U << (p_cfg->channel)) & BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS))),
+ FSP_ERR_INVALID_ARGUMENT);
+ }
+
FSP_ASSERT(p_cfg->rxi_irq >= 0);
FSP_ASSERT(p_cfg->txi_irq >= 0);
FSP_ASSERT(p_cfg->tei_irq >= 0);
@@ -719,26 +727,19 @@ fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const
FSP_ASSERT((p_ctrl->p_reg->SCR_b.CKE & 0x2) == 0U);
#endif
+ /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is
+ * not supported. */
+ uint8_t preserved_scr = p_ctrl->p_reg->SCR & (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
+
/* Disables transmitter and receiver. This terminates any in-progress transmission. */
- p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TE_MASK | SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK |
- SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK);
- p_ctrl->p_tx_src = NULL;
+ p_ctrl->p_reg->SCR = preserved_scr & (uint8_t) ~(SCI_SCR_TE_MASK | SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK);
+ p_ctrl->p_tx_src = NULL;
/* Apply new baud rate register settings. */
r_sci_uart_baud_set(p_ctrl->p_reg, p_baud_setting);
- uint32_t mask_enable = 0;
-#if (SCI_UART_CFG_RX_ENABLE)
-
- /* Enable receive. */
- mask_enable |= (SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK);
-#endif
-#if (SCI_UART_CFG_TX_ENABLE)
-
- /* Enable transmit. */
- mask_enable |= SCI_SCR_TE_MASK;
-#endif
- p_ctrl->p_reg->SCR |= (uint8_t) mask_enable;
+ /* Restore all settings except transmit interrupts. */
+ p_ctrl->p_reg->SCR = preserved_scr;
return FSP_SUCCESS;
}
@@ -875,6 +876,64 @@ fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communica
return err;
}
+/*******************************************************************************************************************//**
+ * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort()
+ * and before the transfer is reset in the next call to read(), will arrive via the callback function with event
+ * UART_EVENT_RX_CHAR.
+ * Implements @ref uart_api_t::readStop
+ *
+ * @retval FSP_SUCCESS UART transaction aborted successfully.
+ * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL.
+ * @retval FSP_ERR_NOT_OPEN The control block has not been opened.
+ * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported.
+ *
+ * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ * return codes. This function calls:
+ * * @ref transfer_api_t::disable
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes)
+{
+ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+ FSP_ASSERT(p_ctrl);
+ FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#if (SCI_UART_CFG_RX_ENABLE)
+ *remaining_bytes = p_ctrl->rx_dest_bytes;
+ p_ctrl->rx_dest_bytes = 0U;
+ #if SCI_UART_CFG_DTC_SUPPORTED
+ if (NULL != p_ctrl->p_cfg->p_transfer_rx)
+ {
+ fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl);
+ FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+ transfer_properties_t transfer_info;
+ err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info);
+ FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+ *remaining_bytes = transfer_info.transfer_length_remaining;
+ }
+ #endif
+ #if SCI_UART_CFG_FIFO_SUPPORT
+ if (0U != p_ctrl->fifo_depth)
+ {
+ /* Reset the receive fifo */
+ p_ctrl->p_reg->FCR_b.RFRST = 1U;
+
+ /* Wait until RFRST cleared after 1 PCLK according to section 34.2.26 "FIFO Control Register (FCR) in the
+ * RA6M3 manual R01UH0886EJ0100 or the relevant section for the MCU being used.*/
+ FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 0U);
+ }
+ #endif
+#else
+
+ return FSP_ERR_UNSUPPORTED;
+#endif
+
+ return FSP_SUCCESS;
+}
+
/*******************************************************************************************************************//**
* Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate
* related registers.
@@ -1247,8 +1306,17 @@ static void r_sci_uart_config_set (sci_uart_instance_ctrl_t * const p_ctrl, uart
sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend;
- /* Configure CTS flow control if CTS/RTS flow control is enabled. */
- p_ctrl->p_reg->SPMR = ((uint8_t) (p_extend->flow_control << R_SCI0_SPMR_CTSE_Pos) & R_SCI0_SPMR_CTSE_Msk);
+ /* Configure flow control if CTS/RTS flow control is enabled. */
+#if BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS
+ if (p_extend->flow_control == SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS)
+ {
+ p_ctrl->p_reg->SPMR = R_SCI0_SPMR_CSTPEN_Msk | R_SCI0_SPMR_CTSE_Msk;
+ }
+ else
+#endif
+ {
+ p_ctrl->p_reg->SPMR = ((uint8_t) (p_extend->flow_control << R_SCI0_SPMR_CTSE_Pos) & R_SCI0_SPMR_CTSE_Msk);
+ }
uint32_t semr = 0;
@@ -1573,7 +1641,7 @@ void sci_uart_txi_isr (void)
* This interrupt also calls the callback function for RTS pin control if it is registered in R_SCI_UART_Open(). This is
* special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro
* 'SCI_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high,
- * then it is it is called again just before leaving this function to set the RTS pin low.
+ * then it is called again just before leaving this function to set the RTS pin low.
* @retval none
**********************************************************************************************************************/
void sci_uart_rxi_isr (void)
diff --git a/bsp/ra6m4-cpk/ra_cfg/SConscript b/bsp/renesas/ra6m4-cpk/ra_cfg/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/SConscript
rename to bsp/renesas/ra6m4-cpk/ra_cfg/SConscript
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/board_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/board_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/board_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
similarity index 88%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
index f3664077fc..48c4b5099e 100644
--- a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
+++ b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -28,13 +28,15 @@
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
- #define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
+ #define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) // DEPRECATED, replace with BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
-
+
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
diff --git a/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..b8641724a4
--- /dev/null
+++ b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,116 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+#define ARDUINO_AN00 (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_AN01 (BSP_IO_PORT_00_PIN_01)
+#define ARDUINO_AN02 (BSP_IO_PORT_00_PIN_02)
+#define ARDUINO_AN03 (BSP_IO_PORT_00_PIN_03)
+#define ARDUINO_AN04 (BSP_IO_PORT_00_PIN_04)
+#define ARDUINO_AN05 (BSP_IO_PORT_00_PIN_05)
+#define PMODA_IRQ11 (BSP_IO_PORT_00_PIN_06)
+#define J4_PIN23 (BSP_IO_PORT_00_PIN_07)
+#define PMODA_IO1 (BSP_IO_PORT_00_PIN_08)
+#define J4_PIN26 (BSP_IO_PORT_00_PIN_09)
+#define PMODA_IO2 (BSP_IO_PORT_00_PIN_14)
+#define PMODA_IO3 (BSP_IO_PORT_00_PIN_15)
+#define J1_PIN1 (BSP_IO_PORT_01_PIN_00)
+#define J2_PIN4 (BSP_IO_PORT_01_PIN_01)
+#define J2_PIN6 (BSP_IO_PORT_01_PIN_02)
+#define J1_PIN29 (BSP_IO_PORT_01_PIN_03)
+#define J3_PIN39 (BSP_IO_PORT_01_PIN_04)
+#define SW1 (BSP_IO_PORT_01_PIN_05)
+#define LED3 (BSP_IO_PORT_01_PIN_06)
+#define J3_PIN37 (BSP_IO_PORT_01_PIN_07)
+#define DEBUG_SWDIO_TMS (BSP_IO_PORT_01_PIN_08)
+#define DEBUG_TDO (BSP_IO_PORT_01_PIN_09)
+#define DEBUG_TDI (BSP_IO_PORT_01_PIN_10)
+#define J1_PIN33 (BSP_IO_PORT_01_PIN_11)
+#define J3_PIN15 (BSP_IO_PORT_01_PIN_12)
+#define J3_PIN16 (BSP_IO_PORT_01_PIN_13)
+#define J3_PIN17 (BSP_IO_PORT_01_PIN_14)
+#define J3_PIN18 (BSP_IO_PORT_01_PIN_15)
+#define NMI (BSP_IO_PORT_02_PIN_00)
+#define MD (BSP_IO_PORT_02_PIN_01)
+#define PMODA_MISO_RXD9 (BSP_IO_PORT_02_PIN_02)
+#define PMODA_MOSI_TXD9 (BSP_IO_PORT_02_PIN_03)
+#define PMODA_RSPCK (BSP_IO_PORT_02_PIN_04)
+#define PMODA_SSL_CTS9 (BSP_IO_PORT_02_PIN_05)
+#define J1_PIN3 (BSP_IO_PORT_02_PIN_06)
+#define J1_PIN8 (BSP_IO_PORT_02_PIN_07)
+#define J1_PIN32 (BSP_IO_PORT_02_PIN_08)
+#define J1_PIN30 (BSP_IO_PORT_02_PIN_09)
+#define J1_PIN28 (BSP_IO_PORT_02_PIN_10)
+#define J1_PIN22 (BSP_IO_PORT_02_PIN_11)
+#define EXTAL (BSP_IO_PORT_02_PIN_12)
+#define XTAL (BSP_IO_PORT_02_PIN_13)
+#define J1_PIN20 (BSP_IO_PORT_02_PIN_14)
+#define DEBUG_SWDCLK_TCK (BSP_IO_PORT_03_PIN_00)
+#define J1_PIN11 (BSP_IO_PORT_03_PIN_01)
+#define J3_PIN14 (BSP_IO_PORT_03_PIN_02)
+#define J3_PIN13 (BSP_IO_PORT_03_PIN_03)
+#define J3_PIN12 (BSP_IO_PORT_03_PIN_04)
+#define J3_PIN11 (BSP_IO_PORT_03_PIN_05)
+#define J3_PIN10 (BSP_IO_PORT_03_PIN_06)
+#define J3_PIN9 (BSP_IO_PORT_03_PIN_07)
+#define J3_PIN8 (BSP_IO_PORT_03_PIN_08)
+#define J3_PIN7 (BSP_IO_PORT_03_PIN_09)
+#define J3_PIN6 (BSP_IO_PORT_03_PIN_10)
+#define J3_PIN5 (BSP_IO_PORT_03_PIN_11)
+#define J3_PIN4 (BSP_IO_PORT_03_PIN_12)
+#define J1_PIN14 (BSP_IO_PORT_03_PIN_13)
+#define J4_PIN13 (BSP_IO_PORT_04_PIN_00)
+#define J4_PIN11 (BSP_IO_PORT_04_PIN_01)
+#define J1_PIN27 (BSP_IO_PORT_04_PIN_02)
+#define J4_PIN2 (BSP_IO_PORT_04_PIN_03)
+#define J4_PIN4 (BSP_IO_PORT_04_PIN_04)
+#define J4_PIN6 (BSP_IO_PORT_04_PIN_05)
+#define J4_PIN8 (BSP_IO_PORT_04_PIN_06)
+#define USB_VBUS_DETECT (BSP_IO_PORT_04_PIN_07)
+#define J2_PIN16 (BSP_IO_PORT_04_PIN_08)
+#define J2_PIN18 (BSP_IO_PORT_04_PIN_09)
+#define PMODB_MISO_RXD0 (BSP_IO_PORT_04_PIN_10)
+#define PMODB_MOSI_TXD0 (BSP_IO_PORT_04_PIN_11)
+#define PMODB_RSPCK (BSP_IO_PORT_04_PIN_12)
+#define PMODB_SSL_CTS0 (BSP_IO_PORT_04_PIN_13)
+#define ARDUINO_RST (BSP_IO_PORT_04_PIN_14)
+#define PMODB_IO1 (BSP_IO_PORT_04_PIN_15)
+#define USB_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USB_OC (BSP_IO_PORT_05_PIN_01)
+#define J4_PIN16 (BSP_IO_PORT_05_PIN_02)
+#define PMODB_IO2 (BSP_IO_PORT_05_PIN_03)
+#define PMODB_IO3 (BSP_IO_PORT_05_PIN_04)
+#define DLS_IRQ14 (BSP_IO_PORT_05_PIN_05)
+#define PMODB_IRQ15 (BSP_IO_PORT_05_PIN_06)
+#define J4_PIN24 (BSP_IO_PORT_05_PIN_07)
+#define DLS_SDA (BSP_IO_PORT_05_PIN_11)
+#define DLS_SCL (BSP_IO_PORT_05_PIN_12)
+#define J1_PIN23 (BSP_IO_PORT_06_PIN_00)
+#define J1_PIN19 (BSP_IO_PORT_06_PIN_01)
+#define J1_PIN21 (BSP_IO_PORT_06_PIN_02)
+#define J1_PIN25 (BSP_IO_PORT_06_PIN_03)
+#define J3_PIN36 (BSP_IO_PORT_06_PIN_04)
+#define J3_PIN35 (BSP_IO_PORT_06_PIN_05)
+#define J3_PIN19 (BSP_IO_PORT_06_PIN_08)
+#define J3_PIN20 (BSP_IO_PORT_06_PIN_09)
+#define J3_PIN21 (BSP_IO_PORT_06_PIN_10)
+#define ARDUINO_GPIO_CLK (BSP_IO_PORT_06_PIN_11)
+#define J3_PIN23 (BSP_IO_PORT_06_PIN_12)
+#define ARDUINO_TXD (BSP_IO_PORT_06_PIN_13)
+#define ARDUINO_RXD (BSP_IO_PORT_06_PIN_14)
+#define J4_PIN9 (BSP_IO_PORT_07_PIN_00)
+#define J4_PIN7 (BSP_IO_PORT_07_PIN_01)
+#define J4_PIN5 (BSP_IO_PORT_07_PIN_02)
+#define J4_PIN3 (BSP_IO_PORT_07_PIN_03)
+#define J4_PIN1 (BSP_IO_PORT_07_PIN_04)
+#define J2_PIN39 (BSP_IO_PORT_07_PIN_05)
+#define J2_PIN7 (BSP_IO_PORT_07_PIN_08)
+#define J2_PIN11 (BSP_IO_PORT_07_PIN_09)
+#define J2_PIN13 (BSP_IO_PORT_07_PIN_10)
+#define J2_PIN15 (BSP_IO_PORT_07_PIN_11)
+#define ARDUINO_GPIO_PWM (BSP_IO_PORT_07_PIN_12)
+#define ARDUINO_GPIO (BSP_IO_PORT_07_PIN_13)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M4 CPK */
+
+void BSP_PinConfigSecurityInit();
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_ioport_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_ioport_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_ioport_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_gen/SConscript b/bsp/renesas/ra6m4-cpk/ra_gen/SConscript
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/SConscript
rename to bsp/renesas/ra6m4-cpk/ra_gen/SConscript
diff --git a/bsp/ra6m4-cpk/ra_gen/bsp_clock_cfg.h b/bsp/renesas/ra6m4-cpk/ra_gen/bsp_clock_cfg.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/bsp_clock_cfg.h
rename to bsp/renesas/ra6m4-cpk/ra_gen/bsp_clock_cfg.h
diff --git a/bsp/ra6m4-cpk/ra_gen/common_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/common_data.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/common_data.c
rename to bsp/renesas/ra6m4-cpk/ra_gen/common_data.c
diff --git a/bsp/ra6m4-cpk/ra_gen/common_data.h b/bsp/renesas/ra6m4-cpk/ra_gen/common_data.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/common_data.h
rename to bsp/renesas/ra6m4-cpk/ra_gen/common_data.h
diff --git a/bsp/ra6m4-cpk/ra_gen/hal_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c
similarity index 97%
rename from bsp/ra6m4-cpk/ra_gen/hal_data.c
rename to bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c
index 1727d2e918..a7cdaf62af 100644
--- a/bsp/ra6m4-cpk/ra_gen/hal_data.c
+++ b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c
@@ -8,7 +8,12 @@ const external_irq_cfg_t g_external_irq0_cfg =
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = irq0_callback,
+ /** If NULL then do not add & */
+#if defined(NULL)
.p_context = NULL,
+#else
+ .p_context = &NULL,
+#endif
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
diff --git a/bsp/ra6m4-cpk/ra_gen/hal_data.h b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/hal_data.h
rename to bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h
diff --git a/bsp/ra6m4-cpk/ra_gen/main.c b/bsp/renesas/ra6m4-cpk/ra_gen/main.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/main.c
rename to bsp/renesas/ra6m4-cpk/ra_gen/main.c
diff --git a/bsp/ra6m4-cpk/ra_gen/pin_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/pin_data.c
similarity index 95%
rename from bsp/ra6m4-cpk/ra_gen/pin_data.c
rename to bsp/renesas/ra6m4-cpk/ra_gen/pin_data.c
index 448eee5d8e..f97d4a86a8 100644
--- a/bsp/ra6m4-cpk/ra_gen/pin_data.c
+++ b/bsp/renesas/ra6m4-cpk/ra_gen/pin_data.c
@@ -38,7 +38,7 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
},
{
.pin = BSP_IO_PORT_00_PIN_14,
- .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
},
{
.pin = BSP_IO_PORT_00_PIN_15,
@@ -178,7 +178,11 @@ void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void)
{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
@@ -192,7 +196,11 @@ void R_BSP_PinCfgSecurityInit(void)
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
}
}
diff --git a/bsp/ra6m4-cpk/ra_gen/vector_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c
similarity index 100%
rename from bsp/ra6m4-cpk/ra_gen/vector_data.c
rename to bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c
diff --git a/bsp/ra6m4-cpk/ra_gen/vector_data.h b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h
similarity index 54%
rename from bsp/ra6m4-cpk/ra_gen/vector_data.h
rename to bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h
index fd6cf29e21..0da697c477 100644
--- a/bsp/ra6m4-cpk/ra_gen/vector_data.h
+++ b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h
@@ -14,26 +14,13 @@
/* Vector table allocations */
#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */
+ #define SCI7_RXI_IRQn ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */
#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type) 1) /* SCI7 TXI (Transmit data empty) */
+ #define SCI7_TXI_IRQn ((IRQn_Type) 1) /* SCI7 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type) 2) /* SCI7 TEI (Transmit end) */
+ #define SCI7_TEI_IRQn ((IRQn_Type) 2) /* SCI7 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
+ #define SCI7_ERI_IRQn ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
- typedef enum IRQn {
- Reset_IRQn = -15,
- NonMaskableInt_IRQn = -14,
- HardFault_IRQn = -13,
- MemoryManagement_IRQn = -12,
- BusFault_IRQn = -11,
- UsageFault_IRQn = -10,
- SecureFault_IRQn = -9,
- SVCall_IRQn = -5,
- DebugMonitor_IRQn = -4,
- PendSV_IRQn = -2,
- SysTick_IRQn = -1,
- SCI7_RXI_IRQn = 0, /* SCI7 RXI (Received data full) */
- SCI7_TXI_IRQn = 1, /* SCI7 TXI (Transmit data empty) */
- SCI7_TEI_IRQn = 2, /* SCI7 TEI (Transmit end) */
- SCI7_ERI_IRQn = 3, /* SCI7 ERI (Receive error) */
- ICU_IRQ0_IRQn = 4, /* ICU IRQ0 (External pin interrupt 0) */
- } IRQn_Type;
+ #define ICU_IRQ0_IRQn ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
#endif /* VECTOR_DATA_H */
\ No newline at end of file
diff --git a/bsp/ra6m4-cpk/rtconfig.h b/bsp/renesas/ra6m4-cpk/rtconfig.h
similarity index 100%
rename from bsp/ra6m4-cpk/rtconfig.h
rename to bsp/renesas/ra6m4-cpk/rtconfig.h
diff --git a/bsp/ra6m4-cpk/rtconfig.py b/bsp/renesas/ra6m4-cpk/rtconfig.py
similarity index 93%
rename from bsp/ra6m4-cpk/rtconfig.py
rename to bsp/renesas/ra6m4-cpk/rtconfig.py
index d63467a2d6..ad55ddedbd 100644
--- a/bsp/ra6m4-cpk/rtconfig.py
+++ b/bsp/renesas/ra6m4-cpk/rtconfig.py
@@ -57,8 +57,8 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -Os'
- POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
- POST_ACTION += OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
+ POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
+ # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
diff --git a/bsp/ra6m4-cpk/script/ac6/fsp_keep.via b/bsp/renesas/ra6m4-cpk/script/ac6/fsp_keep.via
similarity index 96%
rename from bsp/ra6m4-cpk/script/ac6/fsp_keep.via
rename to bsp/renesas/ra6m4-cpk/script/ac6/fsp_keep.via
index 2740ed2ada..d2aed8ac1c 100644
--- a/bsp/ra6m4-cpk/script/ac6/fsp_keep.via
+++ b/bsp/renesas/ra6m4-cpk/script/ac6/fsp_keep.via
@@ -2,6 +2,7 @@
--keep=*(.application_vectors*)
--keep=*(.version)
--keep=bsp_rom_registers.o(.rom_registers*)
+--keep=*(.mcuboot_sce9_key*)
--keep=*(.usb_*_desc_*)
--keep=*(.eh_frame*)
--keep=*(.code_in_ram*)
diff --git a/bsp/ra6m4-cpk/script/fsp.ld b/bsp/renesas/ra6m4-cpk/script/fsp.ld
similarity index 96%
rename from bsp/ra6m4-cpk/script/fsp.ld
rename to bsp/renesas/ra6m4-cpk/script/fsp.ld
index 851bb2c45f..ce7c9b0139 100644
--- a/bsp/ra6m4-cpk/script/fsp.ld
+++ b/bsp/renesas/ra6m4-cpk/script/fsp.ld
@@ -66,6 +66,8 @@ MEMORY
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
@@ -146,6 +148,12 @@ SECTIONS
/* Reserving 0x100 bytes of space for ROM registers. */
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ . = ALIGN(128);
+ KEEP(*(.mcuboot_sce9_key*))
+
*(.text*)
KEEP(*(.version))
@@ -325,7 +333,7 @@ SECTIONS
_end_sg = .;
} > FLASH
- __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
@@ -358,6 +366,25 @@ SECTIONS
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
diff --git a/bsp/ra6m4-cpk/script/fsp.scat b/bsp/renesas/ra6m4-cpk/script/fsp.scat
similarity index 97%
rename from bsp/ra6m4-cpk/script/fsp.scat
rename to bsp/renesas/ra6m4-cpk/script/fsp.scat
index 825aaad2da..3db1452f53 100644
--- a/bsp/ra6m4-cpk/script/fsp.scat
+++ b/bsp/renesas/ra6m4-cpk/script/fsp.scat
@@ -201,6 +201,12 @@ LOAD_REGION_FLASH FLASH_ORIGIN ALIGN 0x80 LIMITED_FLASH_LENGTH
#endif
+ MCUBOOT_SCE9_KEY +0 FIXED
+ {
+ *(.mcuboot_sce9_key)
+ }
+
+
INIT_ARRAY +0 FIXED
{
*(.init_array)
@@ -275,6 +281,18 @@ LOAD_REGION_FLASH FLASH_ORIGIN ALIGN 0x80 LIMITED_FLASH_LENGTH
{
}
+ ; Support for OctaRAM
+ OSPI_DEVICE_0_NO_LOAD OSPI_DEVICE_0_START UNINIT NOCOMPRESS
+ {
+ *(.ospi_device_0_no_load*)
+ }
+
+ ; Support for OctaRAM
+ OSPI_DEVICE_1_NO_LOAD OSPI_DEVICE_1_START UNINIT NOCOMPRESS
+ {
+ *(.ospi_device_1_no_load*)
+ }
+
__tz_RAM_C RAM_NSC_START EMPTY 0
{
}
diff --git a/bsp/ra6m4-cpk/script/memory_regions.ld b/bsp/renesas/ra6m4-cpk/script/memory_regions.ld
similarity index 100%
rename from bsp/ra6m4-cpk/script/memory_regions.ld
rename to bsp/renesas/ra6m4-cpk/script/memory_regions.ld
diff --git a/bsp/ra6m4-cpk/script/memory_regions.scat b/bsp/renesas/ra6m4-cpk/script/memory_regions.scat
similarity index 100%
rename from bsp/ra6m4-cpk/script/memory_regions.scat
rename to bsp/renesas/ra6m4-cpk/script/memory_regions.scat
diff --git a/bsp/ra6m4-cpk/src/hal_entry.c b/bsp/renesas/ra6m4-cpk/src/hal_entry.c
similarity index 100%
rename from bsp/ra6m4-cpk/src/hal_entry.c
rename to bsp/renesas/ra6m4-cpk/src/hal_entry.c
diff --git a/bsp/ra6m4-cpk/template.uvoptx b/bsp/renesas/ra6m4-cpk/template.uvoptx
similarity index 80%
rename from bsp/ra6m4-cpk/template.uvoptx
rename to bsp/renesas/ra6m4-cpk/template.uvoptx
index 181ead903f..853ddaf732 100644
--- a/bsp/ra6m4-cpk/template.uvoptx
+++ b/bsp/renesas/ra6m4-cpk/template.uvoptx
@@ -169,14 +169,6 @@
-
- Source Group 1
- 0
- 0
- 0
- 0
-
-
:Renesas RA Smart Configurator:Common Sources
0
@@ -184,7 +176,7 @@
0
0
- 2
+ 1
1
1
0
@@ -195,42 +187,6 @@
0
0
-
- 2
- 2
- 5
- 0
- 0
- 0
- .\src\SConscript
- SConscript
- 0
- 0
-
-
- 2
- 3
- 1
- 0
- 0
- 0
- .\src\mqtt_client.c
- mqtt_client.c
- 0
- 0
-
-
- 2
- 4
- 5
- 0
- 0
- 0
- .\src\mqtt_client.h
- mqtt_client.h
- 0
- 0
-
diff --git a/bsp/ra6m4-cpk/template.uvprojx b/bsp/renesas/ra6m4-cpk/template.uvprojx
similarity index 95%
rename from bsp/ra6m4-cpk/template.uvprojx
rename to bsp/renesas/ra6m4-cpk/template.uvprojx
index 948f8b1586..ea623c0b2a 100644
--- a/bsp/ra6m4-cpk/template.uvprojx
+++ b/bsp/renesas/ra6m4-cpk/template.uvprojx
@@ -49,7 +49,7 @@
1
.\Objects\
- ra6m4
+ ra6m4_cpk
1
0
1
@@ -82,11 +82,11 @@
0
0
-
+ cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out"""
0
0
- 0
+ 2
0
0
@@ -380,9 +380,6 @@
-
- Source Group 1
-
:Renesas RA Smart Configurator:Common Sources
@@ -391,21 +388,6 @@
1
.\src\hal_entry.c
-
- SConscript
- 5
- .\src\SConscript
-
-
- mqtt_client.c
- 1
- .\src\mqtt_client.c
-
-
- mqtt_client.h
- 5
- .\src\mqtt_client.h
-