parent
cceba7ca86
commit
431ddb90f5
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2020-10-30 CDT first version
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* 2021-01-18 CDT MOdify SRAM_SIZE
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*/
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@ -18,7 +19,7 @@
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/* board configuration */
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#define SRAM_BASE 0x1FFE0000
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#define SRAM_SIZE 0x20000
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#define SRAM_SIZE 0x80000
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#define SRAM_END (SRAM_BASE + SRAM_SIZE)
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/* High speed sram. */
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2020-10-30 CDT first version
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* 2021-01-18 CDT modify i2c gpio init
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*/
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@ -81,8 +82,8 @@ static void hc32_i2c_gpio_init(struct hc32_i2c *i2c)
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{
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struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)i2c->ops.data;
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rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
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rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
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rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD);
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rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD);
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rt_pin_write(cfg->scl_pin, PIN_HIGH);
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rt_pin_write(cfg->sda_pin, PIN_HIGH);
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@ -98,8 +99,6 @@ static void hc32_set_sda(void *data, rt_int32_t state)
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{
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struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
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rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
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if (state)
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rt_pin_write(cfg->sda_pin, PIN_HIGH);
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else
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@ -116,8 +115,6 @@ static void hc32_set_scl(void *data, rt_int32_t state)
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{
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struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
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rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
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if (state)
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rt_pin_write(cfg->scl_pin, PIN_HIGH);
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else
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@ -133,8 +130,6 @@ static rt_int32_t hc32_get_sda(void *data)
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{
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struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
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rt_pin_mode(cfg->sda_pin, PIN_MODE_INPUT);
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return rt_pin_read(cfg->sda_pin);
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}
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@ -147,8 +142,6 @@ static rt_int32_t hc32_get_scl(void *data)
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{
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struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
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rt_pin_mode(cfg->scl_pin, PIN_MODE_INPUT);
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return rt_pin_read(cfg->scl_pin);
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}
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