[update] 整理cortex-a aarch32启动代码
1. 去除start_gcc.s中set_secondary_cpu_boot_address代码，这部分提取到qemu-vexpress-a9 bsp中。 2. 移动cpu.c中rt_hw_cpu_id函数到cp15_gcc.s，使用汇编实现，采用wake属性，方便bsp根据cpu特性获取CPU ID（多cpu集群中，不同厂家使用组合不一样）. 3. 整理start_gcc.s 适应多核启动，原来的代码只考虑到双核的情况。
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zhouji
zhouji
parent
484cda4d92
commit
42ce237dc9
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@ -26,10 +26,16 @@ static void rt_hw_timer2_isr(int vector, void *param)
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timer_clear_pending(0);
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}
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void set_secondary_cpu_boot_address(void)
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{
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extern void secondary_cpu_start(void);
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uint32_t *boot_address = (uint32_t *)0x10000030;
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*(boot_address + 1) = ~0ul;
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*boot_address = (uint32_t )&secondary_cpu_start;
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}
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void rt_hw_secondary_cpu_up(void)
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{
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extern void set_secondary_cpu_boot_address(void);
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set_secondary_cpu_boot_address();
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__asm__ volatile ("dsb":::"memory");
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rt_hw_ipi_send(0, 1 << 1);
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@ -15,8 +15,7 @@
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#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
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#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
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unsigned long rt_cpu_get_smp_id(void);
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int rt_hw_cpu_id(void);
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void rt_cpu_mmu_disable(void);
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void rt_cpu_mmu_enable(void);
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void rt_cpu_tlb_set(volatile unsigned long*);
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@ -8,9 +8,11 @@
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* 2013-07-05 Bernard the first version
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*/
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.globl rt_cpu_get_smp_id
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rt_cpu_get_smp_id:
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mrc p15, #0, r0, c0, c0, #5
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.weak rt_hw_cpu_id
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rt_hw_cpu_id:
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mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register
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ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2
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and r0, r0, r1
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bx lr
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.globl rt_cpu_vector_set_base
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@ -15,17 +15,6 @@
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#ifdef RT_USING_SMP
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int rt_hw_cpu_id(void)
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{
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int cpu_id;
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__asm__ volatile (
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"mrc p15, 0, %0, c0, c0, 5"
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:"=r"(cpu_id)
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);
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cpu_id &= 0xf;
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return cpu_id;
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};
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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lock->slock = 0;
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@ -22,20 +22,26 @@
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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#ifdef RT_USING_FPU
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.equ UND_Stack_Size, 0x00000400
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#else
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.equ UND_Stack_Size, 0x00000000
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#endif
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.equ SVC_Stack_Size, 0x00000400
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.equ ABT_Stack_Size, 0x00000000
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.equ ABT_Stack_Size, 0x00000400
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.equ RT_FIQ_STACK_PGSZ, 0x00000000
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.equ RT_IRQ_STACK_PGSZ, 0x00000800
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.equ USR_Stack_Size, 0x00000400
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.equ SUB_UND_Stack_Size, 0x00000400
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.equ SUB_SVC_Stack_Size, 0x00000400
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.equ SUB_ABT_Stack_Size, 0x00000400
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.equ SUB_RT_FIQ_STACK_PGSZ, 0x00000000
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.equ SUB_RT_IRQ_STACK_PGSZ, 0x00000400
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.equ SUB_USR_Stack_Size, 0x00000400
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#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
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#define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \
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SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ)
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.section .data.share.isr
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/* stack */
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.globl stack_start
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@ -82,9 +88,40 @@ continue:
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/* disable the data alignment check */
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mrc p15, 0, r1, c1, c0, 0
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bic r1, #(1<<1)
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bic r1, #(1<<0) /* Disable MMU */
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bic r1, #(1<<1) /* Disable Alignment fault checking */
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bic r1, #(1<<2) /* Disable data cache */
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bic r1, #(1<<11) /* Disable program flow prediction */
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bic r1, #(1<<12) /* Disable instruction cache */
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bic r1, #(3<<19) /* bit[20:19] must be zero */
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mcr p15, 0, r1, c1, c0, 0
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@ get cpu id, and subtract the offset from the stacks base address
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bl rt_hw_cpu_id
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mov r5, r0
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cmp r5, #0 @ cpu id == 0
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beq normal_setup
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@ cpu id > 0, stop or wait
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#ifdef RT_SMP_AUTO_BOOT
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ldr r0, =secondary_cpu_entry
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mov r1, #0
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str r1, [r0] /* clean secondary_cpu_entry */
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#endif /* RT_SMP_AUTO_BOOT */
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secondary_loop:
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@ cpu core 1 goes into sleep until core 0 wakeup it
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wfe
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#ifdef RT_SMP_AUTO_BOOT
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ldr r1, =secondary_cpu_entry
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ldr r0, [r1]
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cmp r0, #0
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blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
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#endif /* RT_SMP_AUTO_BOOT */
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b secondary_loop
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normal_setup:
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/* setup stack */
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bl stack_setup
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@ -105,6 +142,11 @@ bss_loop:
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mcr p15, 0, r1, c1, c0, 1 //enable smp
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#endif
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/* enable branch prediction */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #(1<<11)
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mcr p15, 0, r0, c1, c0, 0
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/* initialize the mmu table and enable mmu */
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ldr r0, =platform_mem_desc
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ldr r1, =platform_mem_desc_size
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@ -137,6 +179,7 @@ stack_setup:
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@ Set the startup stack for svc
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mov sp, r0
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sub r0, r0, #SVC_Stack_Size
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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@ -378,16 +421,6 @@ vector_resv:
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b .
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#ifdef RT_USING_SMP
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.global set_secondary_cpu_boot_address
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set_secondary_cpu_boot_address:
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ldr r0, =secondary_cpu_start
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mvn r1, #0 //0xffffffff
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ldr r2, =0x10000034
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str r1, [r2]
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str r0, [r2, #-4]
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mov pc, lr
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.global secondary_cpu_start
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secondary_cpu_start:
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@ -405,38 +438,52 @@ secondary_cpu_start:
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bic r0, #(1<<13)
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mcr p15, 0, r0, c1, c0, 0
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#ifdef RT_USING_FPU
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cps #Mode_UND
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ldr sp, =und_stack_2_limit
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#endif
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/* enable branch prediction */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #(1<<11)
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mcr p15, 0, r0, c1, c0, 0
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cps #Mode_IRQ
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ldr sp, =irq_stack_2_limit
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@ get cpu id, and subtract the offset from the stacks base address
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bl rt_hw_cpu_id
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sub r5, r0, #1
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cps #Mode_FIQ
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ldr sp, =irq_stack_2_limit
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ldr r0, =SUB_ISR_Stack_Size
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mul r0, r0, r5 @r0 = SUB_ISR_Stack_Size * (cpuid - 1)
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ldr r1, =sub_stack_top
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sub r0, r1, r0 @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1))
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cps #Mode_SVC
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mov sp, r0
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sub r0, r0, #SUB_SVC_Stack_Size
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cps #Mode_UND
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mov sp, r0
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sub r0, r0, #SUB_UND_Stack_Size
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cps #Mode_ABT
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mov sp, r0
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sub r0, r0, #SUB_ABT_Stack_Size
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cps #Mode_FIQ
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mov sp, r0
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sub r0, r0, #SUB_RT_FIQ_STACK_PGSZ
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cps #Mode_IRQ
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mov sp, r0
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sub r0, r0, #SUB_RT_IRQ_STACK_PGSZ
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cps #Mode_SVC
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ldr sp, =svc_stack_2_limit
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/* initialize the mmu table and enable mmu */
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bl rt_hw_mmu_init
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b secondary_cpu_c_start
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#endif
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.bss
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.align 2 //align to 2~2=4
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svc_stack_2:
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.space (1 << 10)
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svc_stack_2_limit:
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irq_stack_2:
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.space (1 << 10)
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irq_stack_2_limit:
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sub_stack_start:
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.space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1))
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sub_stack_top:
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#ifdef RT_USING_FPU
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und_stack_2:
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.space (1 << 10)
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und_stack_2_limit:
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#endif
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