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[bsp][mm32l07x][rsoc] Fix compilation issues with bsp of mm32l07x

This commit is contained in:
hydevcode 2024-09-30 00:33:10 +08:00 committed by GitHub
parent d0cf64631a
commit 4203bfeb1d
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GPG Key ID: B5690EEEBB952194
4 changed files with 534 additions and 461 deletions
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1
.github/workflows/bsp_buildings.yml vendored
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@ -93,6 +93,7 @@ jobs:
- "hc32l196" - "hc32l196"
- "mm32/mm32f3270-100ask-pitaya" - "mm32/mm32f3270-100ask-pitaya"
- "mm32f327x" - "mm32f327x"
- "mm32l07x"
- "sam7x" - "sam7x"
- "hk32/hk32f030c8-mini" - "hk32/hk32f030c8-mini"
- "acm32/acm32f0x0-nucleo" - "acm32/acm32f0x0-nucleo"

2
.github/workflows/manual_trigger_scons_except_STM32_all.yml vendored
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@ -185,7 +185,7 @@ jobs:
- {RTT_BSP_NAME: "mm32_mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32/mm32f3270-100ask-pitaya"} - {RTT_BSP_NAME: "mm32_mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32/mm32f3270-100ask-pitaya"}
- {RTT_BSP_NAME: "mm32f103x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f103x"} - {RTT_BSP_NAME: "mm32f103x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f103x"}
#- {RTT_BSP_NAME: "mm32f327x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f327x"} #编译问题 #- {RTT_BSP_NAME: "mm32f327x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f327x"} #编译问题
#- {RTT_BSP_NAME: "mm32l07x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l07x"} #编译问题 - {RTT_BSP_NAME: "mm32l07x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l07x"}
- {RTT_BSP_NAME: "mm32l3xx", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l3xx"} - {RTT_BSP_NAME: "mm32l3xx", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l3xx"}
- {RTT_BSP_NAME: "n32_n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g43xcl-stb"} - {RTT_BSP_NAME: "n32_n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g43xcl-stb"}
- {RTT_BSP_NAME: "n32_n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g457qel-stb"} - {RTT_BSP_NAME: "n32_n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g457qel-stb"}

92
bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/HAL_i2c.c
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@ -44,13 +44,13 @@
* @{ * @{
*/ */
/*I2c Enable disable*/ /* I2c Enable disable */
#define IC_ENABLE_Reset ((uint16_t)0xFFFE) #define IC_ENABLE_Reset ((uint16_t)0xFFFE)
#define IC_ENABLE_Set ((uint16_t)0x0001) #define IC_ENABLE_Set ((uint16_t)0x0001)
#define IC_CON_RESET ((uint16_t)0xFE8A) #define IC_CON_RESET ((uint16_t)0xFE8A)
#define INTR_MASK ((uint16_t)0xC000) #define INTR_MASK ((uint16_t)0xC000)
/*I2c DMA reset*/ /* I2c DMA reset */
#define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC) #define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC)
/* I2C START mask */ /* I2C START mask */
@ -68,7 +68,7 @@
#define IC_TAR_ENDUAL_Set ((uint16_t)0x1000) #define IC_TAR_ENDUAL_Set ((uint16_t)0x1000)
#define IC_TAR_ENDUAL_Reset ((uint16_t)0xEFFF) #define IC_TAR_ENDUAL_Reset ((uint16_t)0xEFFF)
/* I2C SPECIAL、GC_OR_START bits mask */ /* I2C SPECIAL GC_OR_START bits mask */
#define IC_TAR_GC_Set ((uint16_t)0x0800) #define IC_TAR_GC_Set ((uint16_t)0x0800)
#define IC_TAR_GC_Reset ((uint16_t)0xF7FF) #define IC_TAR_GC_Reset ((uint16_t)0xF7FF)
@ -78,7 +78,6 @@
static uint8_t I2C_CMD_DIR = 0; static uint8_t I2C_CMD_DIR = 0;
/*新增加的用户变量，外部调用时需要更新该变量值*/
uint16_t I2C_DMA_DIR = 0; uint16_t I2C_DMA_DIR = 0;
/** /**
@ -151,7 +150,7 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
uint16_t tmpreg = 0; uint16_t tmpreg = 0;
uint32_t pclk1 = 8000000; uint32_t pclk1 = 8000000;
//uint32_t minSclLowTime = 0; /* uint32_t minSclLowTime = 0; */
uint32_t i2cPeriod = 0; uint32_t i2cPeriod = 0;
uint32_t pclk1Period = 0; uint32_t pclk1Period = 0;
RCC_ClocksTypeDef rcc_clocks; RCC_ClocksTypeDef rcc_clocks;
@ -170,7 +169,7 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
/* Set pclk1 period value */ /* Set pclk1 period value */
pclk1Period = 1000000000/pclk1; pclk1Period = 1000000000/pclk1;
i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; /*ns unit*/
tmpreg = 0; tmpreg = 0;
/* Configure speed in standard mode */ /* Configure speed in standard mode */
if (I2C_InitStruct->I2C_ClockSpeed <= 100000) if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
@ -183,7 +182,7 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
} }
else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ else /* (I2C_InitStruct->I2C_ClockSpeed <= 400000) */
{ {
tmpreg = (i2cPeriod/pclk1Period)/2; tmpreg = (i2cPeriod/pclk1Period)/2;
I2Cx->IC_FS_SCL_LCNT = tmpreg; I2Cx->IC_FS_SCL_LCNT = tmpreg;
@ -192,11 +191,11 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
I2Cx->IC_FS_SCL_HCNT = tmpreg; I2Cx->IC_FS_SCL_HCNT = tmpreg;
} }
/*Get the I2Cx IC_CON value */ /* Get the I2Cx IC_CON value */
tmpreg = I2Cx->IC_CON; tmpreg = I2Cx->IC_CON;
/*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ /* Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits */
tmpreg &= IC_CON_RESET; tmpreg &= IC_CON_RESET;
/*Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ /* Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits */
tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN |IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode; tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN |IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode;
/* Write to I2Cx IC_CON */ /* Write to I2Cx IC_CON */
I2Cx->IC_CON = tmpreg; I2Cx->IC_CON = tmpreg;
@ -210,9 +209,9 @@ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
I2Cx->IC_INTR_MASK = tmpreg; I2Cx->IC_INTR_MASK = tmpreg;
/* Write to IC_RX_TL */ /* Write to IC_RX_TL */
I2Cx->IC_RX_TL = 0x0; //rxfifo depth is 1 I2Cx->IC_RX_TL = 0x0; /* rxfifo depth is 1 */
/* Write to IC_TX_TL */ /* Write to IC_TX_TL */
I2Cx->IC_TX_TL = 0x1; //tcfifo depth is 1 I2Cx->IC_TX_TL = 0x1; /* tcfifo depth is 1 */
} }
@ -344,7 +343,7 @@ void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
* @retval : None. * @retval : None.
*/ */
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
//void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address) /* void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address) */
{ {
uint16_t tmpreg = 0; uint16_t tmpreg = 0;
/* Check the parameters */ /* Check the parameters */
@ -614,13 +613,13 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
} }
/* Read the I2Cx status register */ /* Read the I2Cx status register */
flag1 = I2Cx->IC_RAW_INTR_STAT; flag1 = I2Cx->IC_RAW_INTR_STAT;
//flag1 = I2Cx->IC_INTR_STAT; /* flag1 = I2Cx->IC_INTR_STAT; */
/* Get the last event value from I2C status register */ /* Get the last event value from I2C status register */
lastevent = (flag1 ) & I2C_EVENT; lastevent = (flag1 ) & I2C_EVENT;
/* Check whether the last event is equal to I2C_EVENT */ /* Check whether the last event is equal to I2C_EVENT */
if (lastevent == I2C_EVENT ) if (lastevent == I2C_EVENT )
//if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET) /* if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET) */
{ {
/* SUCCESS: last event is equal to I2C_EVENT */ /* SUCCESS: last event is equal to I2C_EVENT */
status = SUCCESS; status = SUCCESS;
@ -665,6 +664,9 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
__IO uint32_t i2creg = 0, i2cxbase = 0; __IO uint32_t i2creg = 0, i2cxbase = 0;
((void)i2creg);
((void)i2cxbase);
/* Check the parameters */ /* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
@ -730,16 +732,26 @@ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
if((I2C_FLAG & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;} if((I2C_FLAG & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
if((I2C_FLAG & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER) {I2Cx->IC_CLR_RX_OVER;} {((void)I2Cx->IC_CLR_RX_UNDER);}
if((I2C_FLAG & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER) {I2Cx->IC_CLR_TX_OVER;} if((I2C_FLAG & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
if((I2C_FLAG & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ) {I2Cx->IC_CLR_RD_REQ;} {((void)I2Cx->IC_CLR_RX_OVER);}
if((I2C_FLAG & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT) {I2Cx->IC_CLR_TX_ABRT;} if((I2C_FLAG & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
if((I2C_FLAG & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE) {I2Cx->IC_CLR_RX_DONE;} {((void)I2Cx->IC_CLR_TX_OVER);}
if((I2C_FLAG & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;} if((I2C_FLAG & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
if((I2C_FLAG & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;} {((void)I2Cx->IC_CLR_RD_REQ);}
if((I2C_FLAG & I2C_FLAG_START_DET) == I2C_FLAG_START_DET){I2Cx->IC_CLR_START_DET;} if((I2C_FLAG & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
if((I2C_FLAG & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;} {((void)I2Cx->IC_CLR_TX_ABRT);}
if((I2C_FLAG & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
{((void)I2Cx->IC_CLR_RX_DONE);}
if((I2C_FLAG & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
{((void)I2Cx->IC_CLR_ACTIVITY);}
if((I2C_FLAG & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
{((void)I2Cx->IC_CLR_STOP_DET);}
if((I2C_FLAG & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
{((void)I2Cx->IC_CLR_START_DET);}
if((I2C_FLAG & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
{((void)I2Cx->IC_CLR_GEN_CALL);}
} }
/** /**
@ -811,16 +823,26 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
/* Clear the selected I2C flag */ /* Clear the selected I2C flag */
if((I2C_IT & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;} if((I2C_IT & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
if((I2C_IT & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER) {I2Cx->IC_CLR_RX_OVER;} {((void)I2Cx->IC_CLR_RX_UNDER);}
if((I2C_IT & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER) {I2Cx->IC_CLR_TX_OVER;} if((I2C_IT & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
if((I2C_IT & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ) {I2Cx->IC_CLR_RD_REQ;} {((void)I2Cx->IC_CLR_RX_OVER);}
if((I2C_IT & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT) {I2Cx->IC_CLR_TX_ABRT;} if((I2C_IT & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
if((I2C_IT & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE) {I2Cx->IC_CLR_RX_DONE;} {((void)I2Cx->IC_CLR_TX_OVER);}
if((I2C_IT & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;} if((I2C_IT & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
if((I2C_IT & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;} {((void)I2Cx->IC_CLR_RD_REQ);}
if((I2C_IT & I2C_IT_START_DET) == I2C_FLAG_START_DET){I2Cx->IC_CLR_START_DET;} if((I2C_IT & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
if((I2C_IT & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;} {((void)I2Cx->IC_CLR_TX_ABRT);}
if((I2C_IT & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
{((void)I2Cx->IC_CLR_RX_DONE);}
if((I2C_IT & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
{((void)I2Cx->IC_CLR_ACTIVITY);}
if((I2C_IT & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
{((void)I2Cx->IC_CLR_STOP_DET);}
if((I2C_IT & I2C_IT_START_DET) == I2C_FLAG_START_DET)
{((void)I2Cx->IC_CLR_START_DET);}
if((I2C_IT & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
{((void)I2Cx->IC_CLR_GEN_CALL);}
} }

660
bsp/mm32l07x/Libraries/MM32L0xx/Source/GCC_StartAsm/startup_MM32L0xx.s
View File

@ -1,305 +1,355 @@
;******************** (C) COPYRIGHT 2017 MindMotion ******************** /* ******************** (C) COPYRIGHT 2017 MindMotion ******************** */
;* File Name : startup_mm32L0xx.s /* File Name : startup_mm32L0xx.s */
;* Author : AE Team /* Author : AE Team */
;* Version : V2.0.0 /* Version : V2.0.0 */
;* Date : 22/08/2017 /* Date : 22/08/2017 */
;* Description : MM32L0xx Medium-density devices vector table for EWARM toolchain. /* Description : MM32L0xx Medium-density devices vector table for */
;* This module performs: /* GCC toolchain. */
;* - Set the initial SP /* This module performs: */
;* - Set the initial PC == __iar_program_start, /* - Set the initial SP */
;* - Set the vector table entries with the exceptions ISR /* - Set the initial PC == __iar_program_start, */
;* address /* - Set the vector table entries with the exceptions*/
;* - Configure the system clock /* ISR address */
;* - Branches to main in the C library (which eventually /* - Configure the system clock */
;* calls main()). /* - Branches to main in the C library (which */
;* After Reset the Cortex-M0 processor is in Thread mode, /* eventually calls main()). */
;* priority is Privileged, and the Stack is set to Main. /* After Reset the Cortex-M0 processor is in Thread */
;******************************************************************************* /* mode, priority is Privileged, and the Stack is set*/
; /* to Main. */
; /* ************************************************************************/
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or /* The vector table is normally located at address 0. When debugging in RAM, it can be located in RAM, aligned to at least 2^6. The name "__vector_table" has special meaning for C-SPY: it is where the SP start value is found, and the NVIC vector table register (VTOR) is initialized to this address if != 0. */
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified /* Cortex-M version */
; version to the workbench project.
; .syntax unified
; The vector table is normally located at address 0. .cpu cortex-m0
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. .fpu softvfp
; The name "__vector_table" has special meaning for C-SPY: .thumb
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0. .global __vector_table
;
; Cortex-M version .word _sidata
; .word _sdata
.word _edata
MODULE ?cstartup .word _sbss
.word _ebss
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3) .section .text.Reset_Handler
.weak Reset_Handler
SECTION .intvec:CODE:NOROOT(2) .type Reset_Handler, %function
Reset_Handler:
EXTERN __iar_program_start ldr r0, =_estack
EXTERN SystemInit msr msp, r0
PUBLIC __vector_table
/*Check if boot space corresponds to test memory*/
DATA ldr r0, =0x00000004
__vector_table ldr r1, [r0]
DCD sfe(CSTACK) lsrs r1, r1, #24
DCD Reset_Handler ; Reset Handler ldr r2, =0x1F
DCD NMI_Handler ; NMI Handler cmp r1, r2
DCD HardFault_Handler ; Hard Fault Handler bne ApplicationStart
DCD 0 ; Reserved
DCD 0 ; Reserved /*SYSCFG clock enable*/
DCD 0 ; Reserved ldr r0, =0x40021018
DCD 0 ; Reserved ldr r1, =0x00000001
DCD 0 ; Reserved str r1, [r0]
DCD 0 ; Reserved
DCD 0 ; Reserved /* Set CFGR1 register with flash memory remap at address 0 */
DCD SVC_Handler ; SVCall Handler ldr r0, =0x40010000
DCD 0 ; Reserved ldr r1, =0x00000000
DCD 0 ; Reserved str r1, [r0]
DCD PendSV_Handler ; PendSV Handler ApplicationStart:
DCD SysTick_Handler ; SysTick Handler /* Copy the data segment initializers from flash to SRAM */
movs r1, #0
; External Interrupts b LoopCopyDataInit
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect CopyDataInit:
DCD RTC_IRQHandler ; RTC through EXTI Line & Tamper ldr r3, =_sidata
DCD FLASH_IRQHandler ; FLASH ldr r3, [r3, r1]
DCD RCC_CRS_IRQHandler ; RCC & CRS str r3, [r0, r1]
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 adds r1, r1, #4
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 LoopCopyDataInit:
DCD 0 ; Reserved ldr r0, =_sdata
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 ldr r3, =_edata
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 adds r2, r0, r1
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 cmp r2, r3
DCD ADC_COMP_IRQHandler ; ADC1 & COMP bcc CopyDataInit
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation ldr r2, =_sbss
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare b LoopFillZerobss
DCD TIM2_IRQHandler ; TIM2 /* Zero fill the bss segment. */
DCD TIM3_IRQHandler ; TIM3 FillZerobss:
DCD 0 ; Reserved movs r3, #0
DCD 0 ; Reserved str r3, [r2]
DCD TIM14_IRQHandler ; TIM14 adds r2, r2, #4
DCD 0 ; Reserved
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17 LoopFillZerobss:
DCD I2C1_IRQHandler ; I2C1 ldr r3, = _ebss
DCD 0 ; Reserved cmp r2, r3
DCD SPI1_IRQHandler ; SPI1 bcc FillZerobss
DCD SPI2_IRQHandler ; SPI2
DCD UART1_IRQHandler ; UART1 /* Call the clock system intitialization function.*/
DCD UART2_IRQHandler ; UART2 bl SystemInit
DCD AES_IRQHandler ; AES
DCD CAN_IRQHandler ; CAN /* Call the application's entry point.*/
DCD USB_IRQHandler ; USB bl main
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; LoopForever:
;; b LoopForever
;; Default interrupt handlers.
;;
THUMB .size Reset_Handler, .-Reset_Handler
PUBWEAK Reset_Handler /* Vector Table Mapped to Address 0 at Reset */
SECTION .text:CODE:NOROOT:REORDER(2) .section .isr_vector, "a", %progbits
Reset_Handler .type __vector_table, %object
LDR R0, =SystemInit .size __vector_table, .-__vector_table
BLX R0
LDR R0, =__iar_program_start __vector_table:
BX R0 .word _estack
.word Reset_Handler
PUBWEAK NMI_Handler .word NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1) .word HardFault_Handler
NMI_Handler .word 0
B NMI_Handler .word 0
.word 0
.word 0
PUBWEAK HardFault_Handler .word 0
SECTION .text:CODE:NOROOT:REORDER(1) .word 0
HardFault_Handler .word 0
B HardFault_Handler .word SVC_Handler
.word 0
.word 0
PUBWEAK SVC_Handler .word PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1) .word SysTick_Handler
SVC_Handler
B SVC_Handler /* External Interrupts */
.word WWDG_IRQHandler
.word PVD_IRQHandler
PUBWEAK PendSV_Handler .word RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1) .word FLASH_IRQHandler
PendSV_Handler .word RCC_CRS_IRQHandler
B PendSV_Handler .word EXTI0_1_IRQHandler
.word EXTI2_3_IRQHandler
.word EXTI4_15_IRQHandler
PUBWEAK SysTick_Handler .word 0
SECTION .text:CODE:NOROOT:REORDER(1) .word DMA1_Channel1_IRQHandler
SysTick_Handler .word DMA1_Channel2_3_IRQHandler
B SysTick_Handler .word DMA1_Channel4_5_IRQHandler
.word ADC_COMP_IRQHandler
.word TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK WWDG_IRQHandler .word TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1) .word TIM2_IRQHandler
WWDG_IRQHandler .word TIM3_IRQHandler
B WWDG_IRQHandler .word 0
.word 0
.word TIM14_IRQHandler
PUBWEAK PVD_IRQHandler .word 0
SECTION .text:CODE:NOROOT:REORDER(1) .word TIM16_IRQHandler
PVD_IRQHandler .word TIM17_IRQHandler
B PVD_IRQHandler .word I2C1_IRQHandler
.word 0
.word SPI1_IRQHandler
PUBWEAK RTC_IRQHandler .word SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1) .word UART1_IRQHandler
RTC_IRQHandler .word UART2_IRQHandler
B RTC_IRQHandler .word AES_IRQHandler
.word CAN_IRQHandler
.word USB_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1) /* Dummy Exception Handlers (infinite loops which can be modified) */
FLASH_IRQHandler .section .text.NMI_Handler
B FLASH_IRQHandler .weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
PUBWEAK RCC_CRS_IRQHandler b NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_CRS_IRQHandler .section .text.HardFault_Handler
B RCC_CRS_IRQHandler .weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
PUBWEAK EXTI0_1_IRQHandler b HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_1_IRQHandler .section .text.SVC_Handler
B EXTI0_1_IRQHandler .weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
PUBWEAK EXTI2_3_IRQHandler b SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_3_IRQHandler .section .text.PendSV_Handler
B EXTI2_3_IRQHandler .weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
PUBWEAK EXTI4_15_IRQHandler b PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_15_IRQHandler .section .text.SysTick_Handler
B EXTI4_15_IRQHandler .weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
PUBWEAK DMA1_Channel1_IRQHandler b SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler .section .text.WWDG_IRQHandler
B DMA1_Channel1_IRQHandler .weak WWDG_IRQHandler
.type WWDG_IRQHandler, %function
WWDG_IRQHandler:
PUBWEAK DMA1_Channel2_3_IRQHandler b WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_3_IRQHandler .section .text.PVD_IRQHandler
B DMA1_Channel2_3_IRQHandler .weak PVD_IRQHandler
.type PVD_IRQHandler, %function
PVD_IRQHandler:
PUBWEAK DMA1_Channel4_5_IRQHandler b PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_IRQHandler .section .text.RTC_IRQHandler
B DMA1_Channel4_5_IRQHandler .weak RTC_IRQHandler
.type RTC_IRQHandler, %function
RTC_IRQHandler:
PUBWEAK ADC_COMP_IRQHandler b RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_COMP_IRQHandler .section .text.FLASH_IRQHandler
B ADC_COMP_IRQHandler .weak FLASH_IRQHandler
.type FLASH_IRQHandler, %function
FLASH_IRQHandler:
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler b FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_UP_TRG_COM_IRQHandler .section .text.RCC_CRS_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler .weak RCC_CRS_IRQHandler
.type RCC_CRS_IRQHandler, %function
RCC_CRS_IRQHandler:
PUBWEAK TIM1_CC_IRQHandler b RCC_CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler .section .text.EXTI0_1_IRQHandler
B TIM1_CC_IRQHandler .weak EXTI0_1_IRQHandler
.type EXTI0_1_IRQHandler, %function
EXTI0_1_IRQHandler:
PUBWEAK TIM2_IRQHandler b EXTI0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler .section .text.EXTI2_3_IRQHandler
B TIM2_IRQHandler .weak EXTI2_3_IRQHandler
.type EXTI2_3_IRQHandler, %function
EXTI2_3_IRQHandler:
PUBWEAK TIM3_IRQHandler b EXTI2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler .section .text.EXTI4_15_IRQHandler
B TIM3_IRQHandler .weak EXTI4_15_IRQHandler
.type EXTI4_15_IRQHandler, %function
EXTI4_15_IRQHandler:
PUBWEAK TIM14_IRQHandler b EXTI4_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM14_IRQHandler .section .text.DMA1_Channel1_IRQHandler
B TIM14_IRQHandler .weak DMA1_Channel1_IRQHandler
.type DMA1_Channel1_IRQHandler, %function
DMA1_Channel1_IRQHandler:
PUBWEAK TIM16_IRQHandler b DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler .section .text.DMA1_Channel2_3_IRQHandler
B TIM16_IRQHandler .weak DMA1_Channel2_3_IRQHandler
.type DMA1_Channel2_3_IRQHandler, %function
DMA1_Channel2_3_IRQHandler:
PUBWEAK TIM17_IRQHandler b DMA1_Channel2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler .section .text.DMA1_Channel4_5_IRQHandler
B TIM17_IRQHandler .weak DMA1_Channel4_5_IRQHandler
.type DMA1_Channel4_5_IRQHandler, %function
DMA1_Channel4_5_IRQHandler:
PUBWEAK I2C1_IRQHandler b DMA1_Channel4_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler .section .text.ADC_COMP_IRQHandler
B I2C1_IRQHandler .weak ADC_COMP_IRQHandler
.type ADC_COMP_IRQHandler, %function
ADC_COMP_IRQHandler:
PUBWEAK SPI1_IRQHandler b ADC_COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler .section .text.TIM1_BRK_UP_TRG_COM_IRQHandler
B SPI1_IRQHandler .weak TIM1_BRK_UP_TRG_COM_IRQHandler
.type TIM1_BRK_UP_TRG_COM_IRQHandler, %function
TIM1_BRK_UP_TRG_COM_IRQHandler:
PUBWEAK SPI2_IRQHandler b TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler .section .text.TIM1_CC_IRQHandler
B SPI2_IRQHandler .weak TIM1_CC_IRQHandler
.type TIM1_CC_IRQHandler, %function
TIM1_CC_IRQHandler:
PUBWEAK UART1_IRQHandler b TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART1_IRQHandler .section .text.TIM2_IRQHandler
B UART1_IRQHandler .weak TIM2_IRQHandler
.type TIM2_IRQHandler, %function
TIM2_IRQHandler:
PUBWEAK UART2_IRQHandler b TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART2_IRQHandler .section .text.TIM3_IRQHandler
B UART2_IRQHandler .weak TIM3_IRQHandler
.type TIM3_IRQHandler, %function
TIM3_IRQHandler:
PUBWEAK AES_IRQHandler b TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler .section .text.TIM14_IRQHandler
B AES_IRQHandler .weak TIM14_IRQHandler
.type TIM14_IRQHandler, %function
TIM14_IRQHandler:
PUBWEAK CAN_IRQHandler b TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN_IRQHandler .section .text.TIM16_IRQHandler
B CAN_IRQHandler .weak TIM16_IRQHandler
.type TIM16_IRQHandler, %function
TIM16_IRQHandler:
PUBWEAK USB_IRQHandler b TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_IRQHandler .section .text.TIM17_IRQHandler
B USB_IRQHandler .weak TIM17_IRQHandler
.type TIM17_IRQHandler, %function
END TIM17_IRQHandler:
;******************** (C) COPYRIGHT 2017 MindMotion ******************** b TIM17_IRQHandler
.section .text.I2C1_IRQHandler
.weak I2C1_IRQHandler
.type I2C1_IRQHandler, %function
I2C1_IRQHandler:
b I2C1_IRQHandler
.section .text.SPI1_IRQHandler
.weak SPI1_IRQHandler
.type SPI1_IRQHandler, %function
SPI1_IRQHandler:
b SPI1_IRQHandler
.section .text.SPI2_IRQHandler
.weak SPI2_IRQHandler
.type SPI2_IRQHandler, %function
SPI2_IRQHandler:
b SPI2_IRQHandler
.section .text.UART1_IRQHandler
.weak UART1_IRQHandler
.type UART1_IRQHandler, %function
UART1_IRQHandler:
b UART1_IRQHandler
.section .text.UART2_IRQHandler
.weak UART2_IRQHandler
.type UART2_IRQHandler, %function
UART2_IRQHandler:
b UART2_IRQHandler
.section .text.AES_IRQHandler
.weak AES_IRQHandler
.type AES_IRQHandler, %function
AES_IRQHandler:
b AES_IRQHandler
.section .text.CAN_IRQHandler
.weak CAN_IRQHandler
.type CAN_IRQHandler, %function
CAN_IRQHandler:
b CAN_IRQHandler
.section .text.USB_IRQHandler
.weak USB_IRQHandler
.type USB_IRQHandler, %function
USB_IRQHandler:
b USB_IRQHandler
/* ******************** (C) COPYRIGHT 2017 MindMotion ******************** */